Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
0fb0cc75 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
79a45b7d | 60 | #include "valprint.h" |
c906108c | 61 | |
8d5f9dcb DJ |
62 | static const struct objfile_data *mips_pdr_data; |
63 | ||
5bbcb741 | 64 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 65 | |
24e05951 | 66 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
67 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
68 | #define ST0_FR (1 << 26) | |
69 | ||
b0069a17 AC |
70 | /* The sizes of floating point registers. */ |
71 | ||
72 | enum | |
73 | { | |
74 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
75 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
76 | }; | |
77 | ||
1a69e1e4 DJ |
78 | enum |
79 | { | |
80 | MIPS32_REGSIZE = 4, | |
81 | MIPS64_REGSIZE = 8 | |
82 | }; | |
0dadbba0 | 83 | |
2e4ebe70 DJ |
84 | static const char *mips_abi_string; |
85 | ||
86 | static const char *mips_abi_strings[] = { | |
87 | "auto", | |
88 | "n32", | |
89 | "o32", | |
28d169de | 90 | "n64", |
2e4ebe70 DJ |
91 | "o64", |
92 | "eabi32", | |
93 | "eabi64", | |
94 | NULL | |
95 | }; | |
96 | ||
f8b73d13 DJ |
97 | /* The standard register names, and all the valid aliases for them. */ |
98 | struct register_alias | |
99 | { | |
100 | const char *name; | |
101 | int regnum; | |
102 | }; | |
103 | ||
104 | /* Aliases for o32 and most other ABIs. */ | |
105 | const struct register_alias mips_o32_aliases[] = { | |
106 | { "ta0", 12 }, | |
107 | { "ta1", 13 }, | |
108 | { "ta2", 14 }, | |
109 | { "ta3", 15 } | |
110 | }; | |
111 | ||
112 | /* Aliases for n32 and n64. */ | |
113 | const struct register_alias mips_n32_n64_aliases[] = { | |
114 | { "ta0", 8 }, | |
115 | { "ta1", 9 }, | |
116 | { "ta2", 10 }, | |
117 | { "ta3", 11 } | |
118 | }; | |
119 | ||
120 | /* Aliases for ABI-independent registers. */ | |
121 | const struct register_alias mips_register_aliases[] = { | |
122 | /* The architecture manuals specify these ABI-independent names for | |
123 | the GPRs. */ | |
124 | #define R(n) { "r" #n, n } | |
125 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
126 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
127 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
128 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
129 | #undef R | |
130 | ||
131 | /* k0 and k1 are sometimes called these instead (for "kernel | |
132 | temp"). */ | |
133 | { "kt0", 26 }, | |
134 | { "kt1", 27 }, | |
135 | ||
136 | /* This is the traditional GDB name for the CP0 status register. */ | |
137 | { "sr", MIPS_PS_REGNUM }, | |
138 | ||
139 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
140 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
141 | ||
142 | /* This is the traditional GDB name for the FCSR. */ | |
143 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
144 | }; | |
145 | ||
c906108c SS |
146 | #ifndef MIPS_DEFAULT_FPU_TYPE |
147 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
148 | #endif | |
149 | static int mips_fpu_type_auto = 1; | |
150 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 151 | |
9ace0497 | 152 | static int mips_debug = 0; |
7a292a7a | 153 | |
29709017 DJ |
154 | /* Properties (for struct target_desc) describing the g/G packet |
155 | layout. */ | |
156 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
157 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
158 | ||
4eb0ad19 DJ |
159 | struct target_desc *mips_tdesc_gp32; |
160 | struct target_desc *mips_tdesc_gp64; | |
161 | ||
56cea623 AC |
162 | const struct mips_regnum * |
163 | mips_regnum (struct gdbarch *gdbarch) | |
164 | { | |
165 | return gdbarch_tdep (gdbarch)->regnum; | |
166 | } | |
167 | ||
168 | static int | |
169 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
170 | { | |
171 | return mips_regnum (gdbarch)->fp0 + 12; | |
172 | } | |
173 | ||
74ed0bb4 MD |
174 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
175 | == MIPS_ABI_EABI32 \ | |
176 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 177 | |
74ed0bb4 | 178 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 179 | |
74ed0bb4 | 180 | #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 181 | |
74ed0bb4 | 182 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 183 | |
95404a3e AC |
184 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
185 | functions to test, set, or clear bit 0 of addresses. */ | |
186 | ||
187 | static CORE_ADDR | |
188 | is_mips16_addr (CORE_ADDR addr) | |
189 | { | |
190 | return ((addr) & 1); | |
191 | } | |
192 | ||
95404a3e AC |
193 | static CORE_ADDR |
194 | unmake_mips16_addr (CORE_ADDR addr) | |
195 | { | |
5b652102 | 196 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
197 | } |
198 | ||
d1973055 KB |
199 | /* Return the MIPS ABI associated with GDBARCH. */ |
200 | enum mips_abi | |
201 | mips_abi (struct gdbarch *gdbarch) | |
202 | { | |
203 | return gdbarch_tdep (gdbarch)->mips_abi; | |
204 | } | |
205 | ||
4246e332 | 206 | int |
1b13c4f6 | 207 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 208 | { |
29709017 DJ |
209 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
210 | ||
211 | /* If we know how big the registers are, use that size. */ | |
212 | if (tdep->register_size_valid_p) | |
213 | return tdep->register_size; | |
214 | ||
215 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
216 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
217 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
218 | } | |
219 | ||
480d3dd2 AC |
220 | /* Return the currently configured (or set) saved register size. */ |
221 | ||
e6bc2e8a | 222 | unsigned int |
13326b4e | 223 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 224 | { |
1a69e1e4 DJ |
225 | switch (mips_abi (gdbarch)) |
226 | { | |
227 | case MIPS_ABI_EABI32: | |
228 | case MIPS_ABI_O32: | |
229 | return 4; | |
230 | case MIPS_ABI_N32: | |
231 | case MIPS_ABI_N64: | |
232 | case MIPS_ABI_O64: | |
233 | case MIPS_ABI_EABI64: | |
234 | return 8; | |
235 | case MIPS_ABI_UNKNOWN: | |
236 | case MIPS_ABI_LAST: | |
237 | default: | |
238 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
239 | } | |
d929b26f AC |
240 | } |
241 | ||
71b8ef93 | 242 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 243 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 244 | "info" field is used for this purpose. |
5a89d8aa | 245 | |
95f1da47 | 246 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
247 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
248 | minimal symbol to mark it as a 16-bit function | |
249 | ||
f594e5e9 | 250 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 251 | |
5a89d8aa | 252 | static void |
6d82d43b AC |
253 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
254 | { | |
255 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
256 | { | |
b887350f | 257 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b AC |
258 | SYMBOL_VALUE_ADDRESS (msym) |= 1; |
259 | } | |
5a89d8aa MS |
260 | } |
261 | ||
71b8ef93 MS |
262 | static int |
263 | msymbol_is_special (struct minimal_symbol *msym) | |
264 | { | |
b887350f | 265 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
266 | } |
267 | ||
88658117 AC |
268 | /* XFER a value from the big/little/left end of the register. |
269 | Depending on the size of the value it might occupy the entire | |
270 | register or just part of it. Make an allowance for this, aligning | |
271 | things accordingly. */ | |
272 | ||
273 | static void | |
ba32f989 DJ |
274 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
275 | int reg_num, int length, | |
870cd05e MK |
276 | enum bfd_endian endian, gdb_byte *in, |
277 | const gdb_byte *out, int buf_offset) | |
88658117 | 278 | { |
88658117 | 279 | int reg_offset = 0; |
72a155b4 UW |
280 | |
281 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
282 | /* Need to transfer the left or right part of the register, based on |
283 | the targets byte order. */ | |
88658117 AC |
284 | switch (endian) |
285 | { | |
286 | case BFD_ENDIAN_BIG: | |
72a155b4 | 287 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
288 | break; |
289 | case BFD_ENDIAN_LITTLE: | |
290 | reg_offset = 0; | |
291 | break; | |
6d82d43b | 292 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
293 | reg_offset = 0; |
294 | break; | |
295 | default: | |
e2e0b3e5 | 296 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
297 | } |
298 | if (mips_debug) | |
cb1d2653 AC |
299 | fprintf_unfiltered (gdb_stderr, |
300 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
301 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
302 | if (mips_debug && out != NULL) |
303 | { | |
304 | int i; | |
cb1d2653 | 305 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 306 | for (i = 0; i < length; i++) |
cb1d2653 | 307 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
308 | } |
309 | if (in != NULL) | |
6d82d43b AC |
310 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
311 | in + buf_offset); | |
88658117 | 312 | if (out != NULL) |
6d82d43b AC |
313 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
314 | out + buf_offset); | |
88658117 AC |
315 | if (mips_debug && in != NULL) |
316 | { | |
317 | int i; | |
cb1d2653 | 318 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 319 | for (i = 0; i < length; i++) |
cb1d2653 | 320 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
321 | } |
322 | if (mips_debug) | |
323 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
324 | } | |
325 | ||
dd824b04 DJ |
326 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
327 | compatiblity mode. A return value of 1 means that we have | |
328 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
329 | ||
330 | static int | |
9c9acae0 | 331 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 332 | { |
72a155b4 | 333 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
334 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
335 | meaningful. */ | |
72a155b4 | 336 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
337 | return 0; |
338 | ||
339 | #if 0 | |
340 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
341 | in all the places we deal with FP registers. PR gdb/413. */ | |
342 | /* Otherwise check the FR bit in the status register - it controls | |
343 | the FP compatiblity mode. If it is clear we are in compatibility | |
344 | mode. */ | |
9c9acae0 | 345 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
346 | return 1; |
347 | #endif | |
361d1df0 | 348 | |
dd824b04 DJ |
349 | return 0; |
350 | } | |
351 | ||
7a292a7a | 352 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 353 | |
74ed0bb4 | 354 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 355 | |
a14ed312 | 356 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 357 | |
67b2c998 DJ |
358 | static struct type *mips_float_register_type (void); |
359 | static struct type *mips_double_register_type (void); | |
360 | ||
acdb74a0 AC |
361 | /* The list of available "set mips " and "show mips " commands */ |
362 | ||
363 | static struct cmd_list_element *setmipscmdlist = NULL; | |
364 | static struct cmd_list_element *showmipscmdlist = NULL; | |
365 | ||
5e2e9765 KB |
366 | /* Integer registers 0 thru 31 are handled explicitly by |
367 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 368 | are listed in the following tables. */ |
691c0433 | 369 | |
6d82d43b AC |
370 | enum |
371 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
372 | |
373 | /* Generic MIPS. */ | |
374 | ||
375 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
376 | "sr", "lo", "hi", "bad", "cause", "pc", |
377 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
378 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
379 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
380 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
381 | "fsr", "fir", "" /*"fp" */ , "", | |
382 | "", "", "", "", "", "", "", "", | |
383 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
384 | }; |
385 | ||
386 | /* Names of IDT R3041 registers. */ | |
387 | ||
388 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
389 | "sr", "lo", "hi", "bad", "cause", "pc", |
390 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
391 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
392 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
393 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
394 | "fsr", "fir", "", /*"fp" */ "", | |
395 | "", "", "bus", "ccfg", "", "", "", "", | |
396 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
397 | }; |
398 | ||
399 | /* Names of tx39 registers. */ | |
400 | ||
401 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
402 | "sr", "lo", "hi", "bad", "cause", "pc", |
403 | "", "", "", "", "", "", "", "", | |
404 | "", "", "", "", "", "", "", "", | |
405 | "", "", "", "", "", "", "", "", | |
406 | "", "", "", "", "", "", "", "", | |
407 | "", "", "", "", | |
408 | "", "", "", "", "", "", "", "", | |
409 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
410 | }; |
411 | ||
412 | /* Names of IRIX registers. */ | |
413 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
414 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
415 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
416 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
417 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
418 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
419 | }; |
420 | ||
cce74817 | 421 | |
5e2e9765 | 422 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 423 | static const char * |
d93859e2 | 424 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 425 | { |
d93859e2 | 426 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
427 | /* GPR names for all ABIs other than n32/n64. */ |
428 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
429 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
430 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
431 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
432 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
433 | }; |
434 | ||
435 | /* GPR names for n32 and n64 ABIs. */ | |
436 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
437 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
438 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
439 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
440 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
441 | }; |
442 | ||
d93859e2 | 443 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 444 | |
f57d151a UW |
445 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
446 | but then don't make the raw register names visible. */ | |
d93859e2 UW |
447 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
448 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
449 | return ""; |
450 | ||
5e2e9765 KB |
451 | /* The MIPS integer registers are always mapped from 0 to 31. The |
452 | names of the registers (which reflects the conventions regarding | |
453 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 454 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
455 | { |
456 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 457 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 458 | else |
a4b8ebc8 | 459 | return mips_gpr_names[rawnum]; |
5e2e9765 | 460 | } |
d93859e2 UW |
461 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
462 | return tdesc_register_name (gdbarch, rawnum); | |
463 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
464 | { |
465 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
466 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
467 | } | |
5e2e9765 KB |
468 | else |
469 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 470 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 471 | } |
5e2e9765 | 472 | |
a4b8ebc8 | 473 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 474 | |
a4b8ebc8 AC |
475 | static int |
476 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
477 | struct reggroup *reggroup) | |
478 | { | |
479 | int vector_p; | |
480 | int float_p; | |
481 | int raw_p; | |
72a155b4 UW |
482 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
483 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
484 | if (reggroup == all_reggroup) |
485 | return pseudo; | |
486 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
487 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
488 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
489 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
490 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
491 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
492 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
493 | return 0; |
494 | if (reggroup == float_reggroup) | |
495 | return float_p && pseudo; | |
496 | if (reggroup == vector_reggroup) | |
497 | return vector_p && pseudo; | |
498 | if (reggroup == general_reggroup) | |
499 | return (!vector_p && !float_p) && pseudo; | |
500 | /* Save the pseudo registers. Need to make certain that any code | |
501 | extracting register values from a saved register cache also uses | |
502 | pseudo registers. */ | |
503 | if (reggroup == save_reggroup) | |
504 | return raw_p && pseudo; | |
505 | /* Restore the same pseudo register. */ | |
506 | if (reggroup == restore_reggroup) | |
507 | return raw_p && pseudo; | |
6d82d43b | 508 | return 0; |
a4b8ebc8 AC |
509 | } |
510 | ||
f8b73d13 DJ |
511 | /* Return the groups that a MIPS register can be categorised into. |
512 | This version is only used if we have a target description which | |
513 | describes real registers (and their groups). */ | |
514 | ||
515 | static int | |
516 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
517 | struct reggroup *reggroup) | |
518 | { | |
519 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
520 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
521 | int ret; | |
522 | ||
523 | /* Only save, restore, and display the pseudo registers. Need to | |
524 | make certain that any code extracting register values from a | |
525 | saved register cache also uses pseudo registers. | |
526 | ||
527 | Note: saving and restoring the pseudo registers is slightly | |
528 | strange; if we have 64 bits, we should save and restore all | |
529 | 64 bits. But this is hard and has little benefit. */ | |
530 | if (!pseudo) | |
531 | return 0; | |
532 | ||
533 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
534 | if (ret != -1) | |
535 | return ret; | |
536 | ||
537 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
538 | } | |
539 | ||
a4b8ebc8 | 540 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 541 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 542 | registers. Take care of alignment and size problems. */ |
c5aa993b | 543 | |
a4b8ebc8 AC |
544 | static void |
545 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 546 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 547 | { |
72a155b4 UW |
548 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
549 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
550 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 551 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 552 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
553 | else if (register_size (gdbarch, rawnum) > |
554 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
555 | { |
556 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 557 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
558 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
559 | else | |
560 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
561 | } | |
562 | else | |
e2e0b3e5 | 563 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
564 | } |
565 | ||
566 | static void | |
6d82d43b AC |
567 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
568 | struct regcache *regcache, int cookednum, | |
47a35522 | 569 | const gdb_byte *buf) |
a4b8ebc8 | 570 | { |
72a155b4 UW |
571 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
572 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
573 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 574 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 575 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
576 | else if (register_size (gdbarch, rawnum) > |
577 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
578 | { |
579 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 580 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
581 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
582 | else | |
583 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
584 | } | |
585 | else | |
e2e0b3e5 | 586 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 587 | } |
c5aa993b | 588 | |
c906108c | 589 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 590 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
591 | |
592 | /* Heuristic_proc_start may hunt through the text section for a long | |
593 | time across a 2400 baud serial line. Allows the user to limit this | |
594 | search. */ | |
595 | ||
596 | static unsigned int heuristic_fence_post = 0; | |
597 | ||
46cd78fb | 598 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
599 | register N. NOTE: This defines the pseudo register type so need to |
600 | rebuild the architecture vector. */ | |
43e526b9 JM |
601 | |
602 | static int mips64_transfers_32bit_regs_p = 0; | |
603 | ||
719ec221 AC |
604 | static void |
605 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
606 | struct cmd_list_element *c) | |
43e526b9 | 607 | { |
719ec221 AC |
608 | struct gdbarch_info info; |
609 | gdbarch_info_init (&info); | |
610 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
611 | instead of relying on globals. Doing that would let generic code | |
612 | handle the search for this specific architecture. */ | |
613 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 614 | { |
719ec221 | 615 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 616 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 617 | } |
a4b8ebc8 AC |
618 | } |
619 | ||
47ebcfbe | 620 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 621 | |
ff2e87ac | 622 | static int |
0abe36f5 | 623 | mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
ff2e87ac | 624 | { |
0abe36f5 MD |
625 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
626 | && register_size (gdbarch, regnum) == 4 | |
627 | && (regnum % gdbarch_num_regs (gdbarch)) | |
628 | >= mips_regnum (gdbarch)->fp0 | |
629 | && (regnum % gdbarch_num_regs (gdbarch)) | |
630 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 631 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
632 | } |
633 | ||
42c466d7 | 634 | static void |
ff2e87ac | 635 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 636 | struct type *type, gdb_byte *to) |
102182a9 | 637 | { |
47a35522 MK |
638 | get_frame_register (frame, regnum + 0, to + 4); |
639 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
640 | } |
641 | ||
42c466d7 | 642 | static void |
ff2e87ac | 643 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 644 | struct type *type, const gdb_byte *from) |
102182a9 | 645 | { |
47a35522 MK |
646 | put_frame_register (frame, regnum + 0, from + 4); |
647 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
648 | } |
649 | ||
a4b8ebc8 AC |
650 | /* Return the GDB type object for the "standard" data type of data in |
651 | register REG. */ | |
78fde5f8 KB |
652 | |
653 | static struct type * | |
a4b8ebc8 AC |
654 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
655 | { | |
72a155b4 UW |
656 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
657 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
658 | && (regnum % gdbarch_num_regs (gdbarch)) | |
659 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 660 | { |
5ef80fb0 | 661 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 662 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
663 | if (mips_isa_regsize (gdbarch) == 4) |
664 | return builtin_type_ieee_single; | |
665 | else | |
666 | return builtin_type_ieee_double; | |
a6425924 | 667 | } |
72a155b4 | 668 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
669 | { |
670 | /* The raw or ISA registers. These are all sized according to | |
671 | the ISA regsize. */ | |
672 | if (mips_isa_regsize (gdbarch) == 4) | |
673 | return builtin_type_int32; | |
674 | else | |
675 | return builtin_type_int64; | |
676 | } | |
78fde5f8 | 677 | else |
d5ac5a39 AC |
678 | { |
679 | /* The cooked or ABI registers. These are sized according to | |
680 | the ABI (with a few complications). */ | |
72a155b4 UW |
681 | if (regnum >= (gdbarch_num_regs (gdbarch) |
682 | + mips_regnum (gdbarch)->fp_control_status) | |
683 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
684 | /* The pseudo/cooked view of the embedded registers is always |
685 | 32-bit. The raw view is handled below. */ | |
686 | return builtin_type_int32; | |
687 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
688 | /* The target, while possibly using a 64-bit register buffer, | |
689 | is only transfering 32-bits of each integer register. | |
690 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
691 | return builtin_type_int32; | |
692 | else if (mips_abi_regsize (gdbarch) == 4) | |
693 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
694 | 32- or 64-bit). */ | |
695 | return builtin_type_int32; | |
696 | else | |
697 | /* 64-bit ABI. */ | |
698 | return builtin_type_int64; | |
699 | } | |
78fde5f8 KB |
700 | } |
701 | ||
f8b73d13 DJ |
702 | /* Return the GDB type for the pseudo register REGNUM, which is the |
703 | ABI-level view. This function is only called if there is a target | |
704 | description which includes registers, so we know precisely the | |
705 | types of hardware registers. */ | |
706 | ||
707 | static struct type * | |
708 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
709 | { | |
710 | const int num_regs = gdbarch_num_regs (gdbarch); | |
711 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
712 | int rawnum = regnum % num_regs; | |
713 | struct type *rawtype; | |
714 | ||
715 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
716 | ||
717 | /* Absent registers are still absent. */ | |
718 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
719 | if (TYPE_LENGTH (rawtype) == 0) | |
720 | return rawtype; | |
721 | ||
722 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
723 | /* Present the floating point registers however the hardware did; | |
724 | do not try to convert between FPU layouts. */ | |
725 | return rawtype; | |
726 | ||
727 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
728 | { | |
729 | /* The pseudo/cooked view of embedded registers is always | |
730 | 32-bit, even if the target transfers 64-bit values for them. | |
731 | New targets relying on XML descriptions should only transfer | |
732 | the necessary 32 bits, but older versions of GDB expected 64, | |
733 | so allow the target to provide 64 bits without interfering | |
734 | with the displayed type. */ | |
735 | return builtin_type_int32; | |
736 | } | |
737 | ||
738 | /* Use pointer types for registers if we can. For n32 we can not, | |
739 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
740 | if (mips_abi_regsize (gdbarch) |
741 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
742 | { |
743 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 744 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 745 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 746 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
747 | } |
748 | ||
749 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
750 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
751 | return builtin_type_int32; | |
752 | ||
753 | /* For all other registers, pass through the hardware type. */ | |
754 | return rawtype; | |
755 | } | |
bcb0cc15 | 756 | |
c906108c | 757 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 758 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
759 | |
760 | static int | |
480d3dd2 | 761 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
762 | { |
763 | switch (mask_address_var) | |
764 | { | |
7f19b9a2 | 765 | case AUTO_BOOLEAN_TRUE: |
4014092b | 766 | return 1; |
7f19b9a2 | 767 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
768 | return 0; |
769 | break; | |
7f19b9a2 | 770 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 771 | return tdep->default_mask_address_p; |
4014092b | 772 | default: |
e2e0b3e5 | 773 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 774 | return -1; |
361d1df0 | 775 | } |
4014092b AC |
776 | } |
777 | ||
778 | static void | |
08546159 AC |
779 | show_mask_address (struct ui_file *file, int from_tty, |
780 | struct cmd_list_element *c, const char *value) | |
4014092b | 781 | { |
1cf3db46 | 782 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
783 | |
784 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
785 | switch (mask_address_var) |
786 | { | |
7f19b9a2 | 787 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
788 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
789 | break; | |
7f19b9a2 | 790 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
791 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
792 | break; | |
7f19b9a2 | 793 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
794 | printf_filtered |
795 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
796 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
797 | break; |
798 | default: | |
e2e0b3e5 | 799 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 800 | break; |
361d1df0 | 801 | } |
4014092b | 802 | } |
c906108c | 803 | |
c906108c SS |
804 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
805 | ||
0fe7e7c8 AC |
806 | int |
807 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
808 | { |
809 | struct minimal_symbol *sym; | |
810 | ||
811 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 812 | if (is_mips16_addr (memaddr)) |
c906108c SS |
813 | return 1; |
814 | ||
815 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
816 | the high bit of the info field. Use this to decide if the function is | |
817 | MIPS16 or normal MIPS. */ | |
818 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
819 | if (sym) | |
71b8ef93 | 820 | return msymbol_is_special (sym); |
c906108c SS |
821 | else |
822 | return 0; | |
823 | } | |
824 | ||
b2fa5097 | 825 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
826 | all registers should be sign extended for simplicity? */ |
827 | ||
828 | static CORE_ADDR | |
61a1198a | 829 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 830 | { |
61a1198a UW |
831 | ULONGEST pc; |
832 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
833 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
834 | return pc; | |
b6cb9035 AC |
835 | } |
836 | ||
58dfe9ff AC |
837 | static CORE_ADDR |
838 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
839 | { | |
72a155b4 UW |
840 | return frame_unwind_register_signed |
841 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
842 | } |
843 | ||
30244cd8 UW |
844 | static CORE_ADDR |
845 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
846 | { | |
72a155b4 UW |
847 | return frame_unwind_register_signed |
848 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
849 | } |
850 | ||
b8a22b94 | 851 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
852 | dummy frame. The frame ID's base needs to match the TOS value |
853 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
854 | breakpoint. */ | |
855 | ||
856 | static struct frame_id | |
b8a22b94 | 857 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 858 | { |
f57d151a | 859 | return frame_id_build |
b8a22b94 DJ |
860 | (get_frame_register_signed (this_frame, |
861 | gdbarch_num_regs (gdbarch) | |
862 | + MIPS_SP_REGNUM), | |
863 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
864 | } |
865 | ||
b6cb9035 | 866 | static void |
61a1198a | 867 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 868 | { |
61a1198a UW |
869 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
870 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 871 | } |
c906108c | 872 | |
c906108c SS |
873 | /* Fetch and return instruction from the specified location. If the PC |
874 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
875 | ||
d37cca3d | 876 | static ULONGEST |
acdb74a0 | 877 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 878 | { |
47a35522 | 879 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
880 | int instlen; |
881 | int status; | |
882 | ||
0fe7e7c8 | 883 | if (mips_pc_is_mips16 (addr)) |
c906108c | 884 | { |
95ac2dcf | 885 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 886 | addr = unmake_mips16_addr (addr); |
c906108c SS |
887 | } |
888 | else | |
95ac2dcf | 889 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 890 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
891 | if (status) |
892 | memory_error (status, addr); | |
893 | return extract_unsigned_integer (buf, instlen); | |
894 | } | |
895 | ||
c906108c | 896 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
897 | #define mips32_op(x) (x >> 26) |
898 | #define itype_op(x) (x >> 26) | |
899 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 900 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 901 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 902 | |
e135b889 DJ |
903 | #define jtype_op(x) (x >> 26) |
904 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 905 | |
e135b889 DJ |
906 | #define rtype_op(x) (x >> 26) |
907 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
908 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
909 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
910 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
911 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 912 | |
06987e64 MK |
913 | static LONGEST |
914 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 915 | { |
06987e64 | 916 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
917 | } |
918 | ||
f49e4e6d MS |
919 | /* Determine where to set a single step breakpoint while considering |
920 | branch prediction. */ | |
5a89d8aa | 921 | static CORE_ADDR |
0b1b3e42 | 922 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b JM |
923 | { |
924 | unsigned long inst; | |
925 | int op; | |
926 | inst = mips_fetch_instruction (pc); | |
e135b889 | 927 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 928 | { |
e135b889 | 929 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 930 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 931 | { |
e135b889 | 932 | op = (itype_op (inst) & 0x03); |
c906108c SS |
933 | switch (op) |
934 | { | |
e135b889 DJ |
935 | case 0: /* BEQL */ |
936 | goto equal_branch; | |
937 | case 1: /* BNEL */ | |
938 | goto neq_branch; | |
939 | case 2: /* BLEZL */ | |
940 | goto less_branch; | |
313628cc | 941 | case 3: /* BGTZL */ |
e135b889 | 942 | goto greater_branch; |
c5aa993b JM |
943 | default: |
944 | pc += 4; | |
c906108c SS |
945 | } |
946 | } | |
e135b889 | 947 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 948 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
949 | { |
950 | int tf = itype_rt (inst) & 0x01; | |
951 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 952 | int fcrcs = |
72a155b4 UW |
953 | get_frame_register_signed (frame, |
954 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 955 | fp_control_status); |
e135b889 DJ |
956 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
957 | ||
958 | if (((cond >> cnum) & 0x01) == tf) | |
959 | pc += mips32_relative_offset (inst) + 4; | |
960 | else | |
961 | pc += 8; | |
962 | } | |
c5aa993b JM |
963 | else |
964 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
965 | } |
966 | else | |
c5aa993b JM |
967 | { /* This gets way messy */ |
968 | ||
c906108c | 969 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 970 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 971 | { |
c5aa993b JM |
972 | case 0: /* SPECIAL */ |
973 | op = rtype_funct (inst); | |
974 | switch (op) | |
975 | { | |
976 | case 8: /* JR */ | |
977 | case 9: /* JALR */ | |
6c997a34 | 978 | /* Set PC to that address */ |
0b1b3e42 | 979 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 980 | break; |
e38d4e1a DJ |
981 | case 12: /* SYSCALL */ |
982 | { | |
983 | struct gdbarch_tdep *tdep; | |
984 | ||
985 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
986 | if (tdep->syscall_next_pc != NULL) | |
987 | pc = tdep->syscall_next_pc (frame); | |
988 | else | |
989 | pc += 4; | |
990 | } | |
991 | break; | |
c5aa993b JM |
992 | default: |
993 | pc += 4; | |
994 | } | |
995 | ||
6d82d43b | 996 | break; /* end SPECIAL */ |
c5aa993b | 997 | case 1: /* REGIMM */ |
c906108c | 998 | { |
e135b889 DJ |
999 | op = itype_rt (inst); /* branch condition */ |
1000 | switch (op) | |
c906108c | 1001 | { |
c5aa993b | 1002 | case 0: /* BLTZ */ |
e135b889 DJ |
1003 | case 2: /* BLTZL */ |
1004 | case 16: /* BLTZAL */ | |
c5aa993b | 1005 | case 18: /* BLTZALL */ |
c906108c | 1006 | less_branch: |
0b1b3e42 | 1007 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1008 | pc += mips32_relative_offset (inst) + 4; |
1009 | else | |
1010 | pc += 8; /* after the delay slot */ | |
1011 | break; | |
e135b889 | 1012 | case 1: /* BGEZ */ |
c5aa993b JM |
1013 | case 3: /* BGEZL */ |
1014 | case 17: /* BGEZAL */ | |
1015 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1016 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1017 | pc += mips32_relative_offset (inst) + 4; |
1018 | else | |
1019 | pc += 8; /* after the delay slot */ | |
1020 | break; | |
e135b889 | 1021 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1022 | default: |
1023 | pc += 4; | |
c906108c SS |
1024 | } |
1025 | } | |
6d82d43b | 1026 | break; /* end REGIMM */ |
c5aa993b JM |
1027 | case 2: /* J */ |
1028 | case 3: /* JAL */ | |
1029 | { | |
1030 | unsigned long reg; | |
1031 | reg = jtype_target (inst) << 2; | |
e135b889 | 1032 | /* Upper four bits get never changed... */ |
5b652102 | 1033 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1034 | } |
c5aa993b JM |
1035 | break; |
1036 | /* FIXME case JALX : */ | |
1037 | { | |
1038 | unsigned long reg; | |
1039 | reg = jtype_target (inst) << 2; | |
5b652102 | 1040 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1041 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1042 | } | |
c5aa993b | 1043 | break; /* The new PC will be alternate mode */ |
e135b889 | 1044 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1045 | equal_branch: |
0b1b3e42 UW |
1046 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1047 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1048 | pc += mips32_relative_offset (inst) + 4; |
1049 | else | |
1050 | pc += 8; | |
1051 | break; | |
e135b889 | 1052 | case 5: /* BNE, BNEL */ |
c5aa993b | 1053 | neq_branch: |
0b1b3e42 UW |
1054 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1055 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1056 | pc += mips32_relative_offset (inst) + 4; |
1057 | else | |
1058 | pc += 8; | |
1059 | break; | |
e135b889 | 1060 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1061 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1062 | pc += mips32_relative_offset (inst) + 4; |
1063 | else | |
1064 | pc += 8; | |
1065 | break; | |
1066 | case 7: | |
e135b889 DJ |
1067 | default: |
1068 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1069 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1070 | pc += mips32_relative_offset (inst) + 4; |
1071 | else | |
1072 | pc += 8; | |
1073 | break; | |
c5aa993b JM |
1074 | } /* switch */ |
1075 | } /* else */ | |
1076 | return pc; | |
1077 | } /* mips32_next_pc */ | |
c906108c SS |
1078 | |
1079 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1080 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1081 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1082 | We dont want to set a single step instruction on the extend instruction | |
1083 | either. | |
c5aa993b | 1084 | */ |
c906108c SS |
1085 | |
1086 | /* Lots of mips16 instruction formats */ | |
1087 | /* Predicting jumps requires itype,ritype,i8type | |
1088 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1089 | */ |
c906108c SS |
1090 | enum mips16_inst_fmts |
1091 | { | |
c5aa993b JM |
1092 | itype, /* 0 immediate 5,10 */ |
1093 | ritype, /* 1 5,3,8 */ | |
1094 | rrtype, /* 2 5,3,3,5 */ | |
1095 | rritype, /* 3 5,3,3,5 */ | |
1096 | rrrtype, /* 4 5,3,3,3,2 */ | |
1097 | rriatype, /* 5 5,3,3,1,4 */ | |
1098 | shifttype, /* 6 5,3,3,3,2 */ | |
1099 | i8type, /* 7 5,3,8 */ | |
1100 | i8movtype, /* 8 5,3,3,5 */ | |
1101 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1102 | i64type, /* 10 5,3,8 */ | |
1103 | ri64type, /* 11 5,3,3,5 */ | |
1104 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1105 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1106 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1107 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1108 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1109 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1110 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1111 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1112 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1113 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1114 | }; | |
12f02c2a AC |
1115 | /* I am heaping all the fields of the formats into one structure and |
1116 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1117 | struct upk_mips16 |
6d82d43b AC |
1118 | { |
1119 | CORE_ADDR offset; | |
1120 | unsigned int regx; /* Function in i8 type */ | |
1121 | unsigned int regy; | |
1122 | }; | |
c906108c SS |
1123 | |
1124 | ||
12f02c2a | 1125 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1126 | for the bits which make up the immediate extension. */ |
c906108c | 1127 | |
12f02c2a AC |
1128 | static CORE_ADDR |
1129 | extended_offset (unsigned int extension) | |
c906108c | 1130 | { |
12f02c2a | 1131 | CORE_ADDR value; |
c5aa993b JM |
1132 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1133 | value = value << 6; | |
1134 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1135 | value = value << 5; | |
1136 | value |= extension & 0x01f; /* extract 4:0 */ | |
1137 | return value; | |
c906108c SS |
1138 | } |
1139 | ||
1140 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1141 | instruction. It won't malfunction, but why make excess remote memory |
1142 | references? If the immediate operands get sign extended or something, | |
1143 | do it after the extension is performed. */ | |
c906108c | 1144 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1145 | when the offset is to be used in relative addressing. */ |
c906108c | 1146 | |
12f02c2a | 1147 | static unsigned int |
c5aa993b | 1148 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1149 | { |
47a35522 | 1150 | gdb_byte buf[8]; |
c5aa993b JM |
1151 | pc &= 0xfffffffe; /* clear the low order bit */ |
1152 | target_read_memory (pc, buf, 2); | |
1153 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1154 | } |
1155 | ||
1156 | static void | |
c5aa993b | 1157 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1158 | unsigned int extension, |
1159 | unsigned int inst, | |
6d82d43b | 1160 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1161 | { |
12f02c2a AC |
1162 | CORE_ADDR offset; |
1163 | int regx; | |
1164 | int regy; | |
1165 | switch (insn_format) | |
c906108c | 1166 | { |
c5aa993b | 1167 | case itype: |
c906108c | 1168 | { |
12f02c2a AC |
1169 | CORE_ADDR value; |
1170 | if (extension) | |
c5aa993b JM |
1171 | { |
1172 | value = extended_offset (extension); | |
1173 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1174 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1175 | } |
1176 | else | |
c5aa993b | 1177 | { |
12f02c2a | 1178 | value = inst & 0x7ff; |
c5aa993b | 1179 | /* FIXME : Consider sign extension */ |
c906108c | 1180 | } |
12f02c2a AC |
1181 | offset = value; |
1182 | regx = -1; | |
1183 | regy = -1; | |
c906108c | 1184 | } |
c5aa993b JM |
1185 | break; |
1186 | case ritype: | |
1187 | case i8type: | |
1188 | { /* A register identifier and an offset */ | |
c906108c SS |
1189 | /* Most of the fields are the same as I type but the |
1190 | immediate value is of a different length */ | |
12f02c2a AC |
1191 | CORE_ADDR value; |
1192 | if (extension) | |
c906108c | 1193 | { |
c5aa993b JM |
1194 | value = extended_offset (extension); |
1195 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1196 | value |= inst & 0xff; /* eleven bits from instruction */ |
1197 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1198 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1199 | { | |
1200 | value &= ~0x3fff; /* remove the sign bit */ | |
1201 | value = -value; | |
c906108c SS |
1202 | } |
1203 | } | |
c5aa993b JM |
1204 | else |
1205 | { | |
12f02c2a AC |
1206 | value = inst & 0xff; /* 8 bits */ |
1207 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1208 | /* FIXME: Do sign extension , this format needs it */ |
1209 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1210 | { | |
1211 | value &= 0xef; /* remove the sign bit */ | |
1212 | value = -value; | |
1213 | } | |
c5aa993b | 1214 | } |
12f02c2a AC |
1215 | offset = value; |
1216 | regy = -1; | |
c5aa993b | 1217 | break; |
c906108c | 1218 | } |
c5aa993b | 1219 | case jalxtype: |
c906108c | 1220 | { |
c5aa993b | 1221 | unsigned long value; |
12f02c2a AC |
1222 | unsigned int nexthalf; |
1223 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1224 | value = value << 16; |
1225 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1226 | value |= nexthalf; | |
12f02c2a AC |
1227 | offset = value; |
1228 | regx = -1; | |
1229 | regy = -1; | |
c5aa993b | 1230 | break; |
c906108c SS |
1231 | } |
1232 | default: | |
e2e0b3e5 | 1233 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1234 | } |
12f02c2a AC |
1235 | upk->offset = offset; |
1236 | upk->regx = regx; | |
1237 | upk->regy = regy; | |
c906108c SS |
1238 | } |
1239 | ||
1240 | ||
c5aa993b JM |
1241 | static CORE_ADDR |
1242 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1243 | { |
5b652102 | 1244 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1245 | } |
1246 | ||
12f02c2a | 1247 | static CORE_ADDR |
0b1b3e42 | 1248 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1249 | unsigned int extension, unsigned int insn) |
c906108c | 1250 | { |
12f02c2a AC |
1251 | int op = (insn >> 11); |
1252 | switch (op) | |
c906108c | 1253 | { |
6d82d43b | 1254 | case 2: /* Branch */ |
12f02c2a AC |
1255 | { |
1256 | CORE_ADDR offset; | |
1257 | struct upk_mips16 upk; | |
1258 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1259 | offset = upk.offset; | |
1260 | if (offset & 0x800) | |
1261 | { | |
1262 | offset &= 0xeff; | |
1263 | offset = -offset; | |
1264 | } | |
1265 | pc += (offset << 1) + 2; | |
1266 | break; | |
1267 | } | |
6d82d43b | 1268 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1269 | { |
1270 | struct upk_mips16 upk; | |
1271 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1272 | pc = add_offset_16 (pc, upk.offset); | |
1273 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1274 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1275 | else | |
1276 | pc |= 0x01; | |
1277 | break; | |
1278 | } | |
6d82d43b | 1279 | case 4: /* beqz */ |
12f02c2a AC |
1280 | { |
1281 | struct upk_mips16 upk; | |
1282 | int reg; | |
1283 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1284 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1285 | if (reg == 0) |
1286 | pc += (upk.offset << 1) + 2; | |
1287 | else | |
1288 | pc += 2; | |
1289 | break; | |
1290 | } | |
6d82d43b | 1291 | case 5: /* bnez */ |
12f02c2a AC |
1292 | { |
1293 | struct upk_mips16 upk; | |
1294 | int reg; | |
1295 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1296 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1297 | if (reg != 0) |
1298 | pc += (upk.offset << 1) + 2; | |
1299 | else | |
1300 | pc += 2; | |
1301 | break; | |
1302 | } | |
6d82d43b | 1303 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1304 | { |
1305 | struct upk_mips16 upk; | |
1306 | int reg; | |
1307 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1308 | /* upk.regx contains the opcode */ | |
0b1b3e42 | 1309 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1310 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1311 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1312 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1313 | pc += (upk.offset << 1) + 2; | |
1314 | else | |
1315 | pc += 2; | |
1316 | break; | |
1317 | } | |
6d82d43b | 1318 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1319 | { |
1320 | struct upk_mips16 upk; | |
1321 | /* upk.fmt = rrtype; */ | |
1322 | op = insn & 0x1f; | |
1323 | if (op == 0) | |
c5aa993b | 1324 | { |
12f02c2a AC |
1325 | int reg; |
1326 | upk.regx = (insn >> 8) & 0x07; | |
1327 | upk.regy = (insn >> 5) & 0x07; | |
1328 | switch (upk.regy) | |
c5aa993b | 1329 | { |
12f02c2a AC |
1330 | case 0: |
1331 | reg = upk.regx; | |
1332 | break; | |
1333 | case 1: | |
1334 | reg = 31; | |
6d82d43b | 1335 | break; /* Function return instruction */ |
12f02c2a AC |
1336 | case 2: |
1337 | reg = upk.regx; | |
1338 | break; | |
1339 | default: | |
1340 | reg = 31; | |
6d82d43b | 1341 | break; /* BOGUS Guess */ |
c906108c | 1342 | } |
0b1b3e42 | 1343 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1344 | } |
12f02c2a | 1345 | else |
c5aa993b | 1346 | pc += 2; |
12f02c2a AC |
1347 | break; |
1348 | } | |
1349 | case 30: | |
1350 | /* This is an instruction extension. Fetch the real instruction | |
1351 | (which follows the extension) and decode things based on | |
1352 | that. */ | |
1353 | { | |
1354 | pc += 2; | |
0b1b3e42 | 1355 | pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc)); |
12f02c2a AC |
1356 | break; |
1357 | } | |
1358 | default: | |
1359 | { | |
1360 | pc += 2; | |
1361 | break; | |
1362 | } | |
c906108c | 1363 | } |
c5aa993b | 1364 | return pc; |
12f02c2a | 1365 | } |
c906108c | 1366 | |
5a89d8aa | 1367 | static CORE_ADDR |
0b1b3e42 | 1368 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a AC |
1369 | { |
1370 | unsigned int insn = fetch_mips_16 (pc); | |
0b1b3e42 | 1371 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1372 | } |
1373 | ||
1374 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1375 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1376 | It works by decoding the current instruction and predicting where a |
1377 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1378 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1379 | static CORE_ADDR |
0b1b3e42 | 1380 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1381 | { |
ce1f96de | 1382 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1383 | return mips16_next_pc (frame, pc); |
c5aa993b | 1384 | else |
0b1b3e42 | 1385 | return mips32_next_pc (frame, pc); |
12f02c2a | 1386 | } |
c906108c | 1387 | |
edfae063 AC |
1388 | struct mips_frame_cache |
1389 | { | |
1390 | CORE_ADDR base; | |
1391 | struct trad_frame_saved_reg *saved_regs; | |
1392 | }; | |
1393 | ||
29639122 JB |
1394 | /* Set a register's saved stack address in temp_saved_regs. If an |
1395 | address has already been set for this register, do nothing; this | |
1396 | way we will only recognize the first save of a given register in a | |
1397 | function prologue. | |
eec63939 | 1398 | |
f57d151a UW |
1399 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1400 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1401 | Strictly speaking, only the second range is used as it is only second | |
1402 | range (the ABI instead of ISA registers) that comes into play when finding | |
1403 | saved registers in a frame. */ | |
eec63939 AC |
1404 | |
1405 | static void | |
74ed0bb4 MD |
1406 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1407 | int regnum, CORE_ADDR offset) | |
eec63939 | 1408 | { |
29639122 JB |
1409 | if (this_cache != NULL |
1410 | && this_cache->saved_regs[regnum].addr == -1) | |
1411 | { | |
74ed0bb4 MD |
1412 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1413 | = offset; | |
1414 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1415 | = offset; | |
29639122 | 1416 | } |
eec63939 AC |
1417 | } |
1418 | ||
eec63939 | 1419 | |
29639122 JB |
1420 | /* Fetch the immediate value from a MIPS16 instruction. |
1421 | If the previous instruction was an EXTEND, use it to extend | |
1422 | the upper bits of the immediate value. This is a helper function | |
1423 | for mips16_scan_prologue. */ | |
eec63939 | 1424 | |
29639122 JB |
1425 | static int |
1426 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1427 | unsigned short inst, /* current instruction */ | |
1428 | int nbits, /* number of bits in imm field */ | |
1429 | int scale, /* scale factor to be applied to imm */ | |
1430 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1431 | { |
29639122 | 1432 | int offset; |
eec63939 | 1433 | |
29639122 JB |
1434 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1435 | { | |
1436 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1437 | if (offset & 0x8000) /* check for negative extend */ | |
1438 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1439 | return offset | (inst & 0x1f); | |
1440 | } | |
eec63939 | 1441 | else |
29639122 JB |
1442 | { |
1443 | int max_imm = 1 << nbits; | |
1444 | int mask = max_imm - 1; | |
1445 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1446 | |
29639122 JB |
1447 | offset = inst & mask; |
1448 | if (is_signed && (offset & sign_bit)) | |
1449 | offset = 0 - (max_imm - offset); | |
1450 | return offset * scale; | |
1451 | } | |
1452 | } | |
eec63939 | 1453 | |
65596487 | 1454 | |
29639122 JB |
1455 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1456 | the associated FRAME_CACHE if not null. | |
1457 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1458 | |
29639122 JB |
1459 | static CORE_ADDR |
1460 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1461 | struct frame_info *this_frame, |
29639122 JB |
1462 | struct mips_frame_cache *this_cache) |
1463 | { | |
1464 | CORE_ADDR cur_pc; | |
1465 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1466 | CORE_ADDR sp; | |
1467 | long frame_offset = 0; /* Size of stack frame. */ | |
1468 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1469 | int frame_reg = MIPS_SP_REGNUM; | |
1470 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1471 | unsigned inst = 0; /* current instruction */ | |
1472 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1473 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1474 | int reg, offset; |
a343eb3c | 1475 | |
29639122 JB |
1476 | int extend_bytes = 0; |
1477 | int prev_extend_bytes; | |
1478 | CORE_ADDR end_prologue_addr = 0; | |
b8a22b94 | 1479 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
a343eb3c | 1480 | |
29639122 | 1481 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1482 | THIS_FRAME. */ |
1483 | if (this_frame != NULL) | |
1484 | sp = get_frame_register_signed (this_frame, | |
1485 | gdbarch_num_regs (gdbarch) | |
1486 | + MIPS_SP_REGNUM); | |
29639122 JB |
1487 | else |
1488 | sp = 0; | |
eec63939 | 1489 | |
29639122 JB |
1490 | if (limit_pc > start_pc + 200) |
1491 | limit_pc = start_pc + 200; | |
eec63939 | 1492 | |
95ac2dcf | 1493 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1494 | { |
1495 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1496 | the immediate offset extension from it in mips16_get_imm. */ | |
1497 | prev_inst = inst; | |
eec63939 | 1498 | |
29639122 JB |
1499 | /* Fetch and decode the instruction. */ |
1500 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1501 | |
29639122 JB |
1502 | /* Normally we ignore extend instructions. However, if it is |
1503 | not followed by a valid prologue instruction, then this | |
1504 | instruction is not part of the prologue either. We must | |
1505 | remember in this case to adjust the end_prologue_addr back | |
1506 | over the extend. */ | |
1507 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1508 | { | |
95ac2dcf | 1509 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1510 | continue; |
1511 | } | |
eec63939 | 1512 | |
29639122 JB |
1513 | prev_extend_bytes = extend_bytes; |
1514 | extend_bytes = 0; | |
eec63939 | 1515 | |
29639122 JB |
1516 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1517 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1518 | { | |
1519 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1520 | if (offset < 0) /* negative stack adjustment? */ | |
1521 | frame_offset -= offset; | |
1522 | else | |
1523 | /* Exit loop if a positive stack adjustment is found, which | |
1524 | usually means that the stack cleanup code in the function | |
1525 | epilogue is reached. */ | |
1526 | break; | |
1527 | } | |
1528 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1529 | { | |
1530 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1531 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1532 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1533 | } |
1534 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1535 | { | |
1536 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1537 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1538 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1539 | } |
1540 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1541 | { | |
1542 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1543 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1544 | } |
1545 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1546 | { | |
1547 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1548 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1549 | } |
1550 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1551 | { | |
1552 | frame_addr = sp; | |
1553 | frame_reg = 17; | |
1554 | } | |
1555 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1556 | { | |
1557 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1558 | frame_addr = sp + offset; | |
1559 | frame_reg = 17; | |
1560 | frame_adjust = offset; | |
1561 | } | |
1562 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1563 | { | |
1564 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1565 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1566 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1567 | } |
1568 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1569 | { | |
1570 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1571 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1572 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1573 | } |
1574 | else if ((inst & 0xf81f) == 0xe809 | |
1575 | && (inst & 0x700) != 0x700) /* entry */ | |
1576 | entry_inst = inst; /* save for later processing */ | |
2207132d MR |
1577 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1578 | { | |
1579 | save_inst = inst; /* save for later processing */ | |
1580 | if (prev_extend_bytes) /* extend */ | |
1581 | save_inst |= prev_inst << 16; | |
1582 | } | |
29639122 | 1583 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1584 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1585 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1586 | { | |
1587 | /* This instruction is part of the prologue, but we don't | |
1588 | need to do anything special to handle it. */ | |
1589 | } | |
1590 | else | |
1591 | { | |
1592 | /* This instruction is not an instruction typically found | |
1593 | in a prologue, so we must have reached the end of the | |
1594 | prologue. */ | |
1595 | if (end_prologue_addr == 0) | |
1596 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1597 | } | |
1598 | } | |
eec63939 | 1599 | |
29639122 JB |
1600 | /* The entry instruction is typically the first instruction in a function, |
1601 | and it stores registers at offsets relative to the value of the old SP | |
1602 | (before the prologue). But the value of the sp parameter to this | |
1603 | function is the new SP (after the prologue has been executed). So we | |
1604 | can't calculate those offsets until we've seen the entire prologue, | |
1605 | and can calculate what the old SP must have been. */ | |
1606 | if (entry_inst != 0) | |
1607 | { | |
1608 | int areg_count = (entry_inst >> 8) & 7; | |
1609 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1610 | |
29639122 JB |
1611 | /* The entry instruction always subtracts 32 from the SP. */ |
1612 | frame_offset += 32; | |
1613 | ||
1614 | /* Now we can calculate what the SP must have been at the | |
1615 | start of the function prologue. */ | |
1616 | sp += frame_offset; | |
1617 | ||
1618 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1619 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1620 | { | |
74ed0bb4 | 1621 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1622 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1623 | } |
1624 | ||
1625 | /* Check if the ra register was pushed on the stack. */ | |
1626 | offset = -4; | |
1627 | if (entry_inst & 0x20) | |
1628 | { | |
74ed0bb4 | 1629 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1630 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1631 | } |
1632 | ||
1633 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1634 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1635 | { | |
74ed0bb4 | 1636 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1637 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1638 | } |
1639 | } | |
1640 | ||
2207132d MR |
1641 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1642 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1643 | size of the frame is specified as an immediate field of instruction | |
1644 | and an extended variation exists which lets additional registers and | |
1645 | frame space to be specified. The instruction always treats registers | |
1646 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1647 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1648 | { | |
1649 | static int args_table[16] = { | |
1650 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1651 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1652 | }; | |
1653 | static int astatic_table[16] = { | |
1654 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1655 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1656 | }; | |
1657 | int aregs = (save_inst >> 16) & 0xf; | |
1658 | int xsregs = (save_inst >> 24) & 0x7; | |
1659 | int args = args_table[aregs]; | |
1660 | int astatic = astatic_table[aregs]; | |
1661 | long frame_size; | |
1662 | ||
1663 | if (args < 0) | |
1664 | { | |
1665 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1666 | args = 0; | |
1667 | } | |
1668 | if (astatic < 0) | |
1669 | { | |
1670 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1671 | astatic = 0; | |
1672 | } | |
1673 | ||
1674 | /* For standard SAVE the frame size of 0 means 128. */ | |
1675 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1676 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1677 | frame_size = 16; | |
1678 | frame_size *= 8; | |
1679 | frame_offset += frame_size; | |
1680 | ||
1681 | /* Now we can calculate what the SP must have been at the | |
1682 | start of the function prologue. */ | |
1683 | sp += frame_offset; | |
1684 | ||
1685 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1686 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1687 | { | |
74ed0bb4 | 1688 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1689 | offset += mips_abi_regsize (gdbarch); |
1690 | } | |
1691 | ||
1692 | offset = -4; | |
1693 | ||
1694 | /* Check if the RA register was pushed on the stack. */ | |
1695 | if (save_inst & 0x40) | |
1696 | { | |
74ed0bb4 | 1697 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1698 | offset -= mips_abi_regsize (gdbarch); |
1699 | } | |
1700 | ||
1701 | /* Check if the S8 register was pushed on the stack. */ | |
1702 | if (xsregs > 6) | |
1703 | { | |
74ed0bb4 | 1704 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1705 | offset -= mips_abi_regsize (gdbarch); |
1706 | xsregs--; | |
1707 | } | |
1708 | /* Check if S2-S7 were pushed on the stack. */ | |
1709 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1710 | { | |
74ed0bb4 | 1711 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1712 | offset -= mips_abi_regsize (gdbarch); |
1713 | } | |
1714 | ||
1715 | /* Check if the S1 register was pushed on the stack. */ | |
1716 | if (save_inst & 0x10) | |
1717 | { | |
74ed0bb4 | 1718 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1719 | offset -= mips_abi_regsize (gdbarch); |
1720 | } | |
1721 | /* Check if the S0 register was pushed on the stack. */ | |
1722 | if (save_inst & 0x20) | |
1723 | { | |
74ed0bb4 | 1724 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1725 | offset -= mips_abi_regsize (gdbarch); |
1726 | } | |
1727 | ||
1728 | /* Check if A0-A3 were pushed on the stack. */ | |
1729 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1730 | { | |
74ed0bb4 | 1731 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1732 | offset -= mips_abi_regsize (gdbarch); |
1733 | } | |
1734 | } | |
1735 | ||
29639122 JB |
1736 | if (this_cache != NULL) |
1737 | { | |
1738 | this_cache->base = | |
b8a22b94 DJ |
1739 | (get_frame_register_signed (this_frame, |
1740 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1741 | + frame_offset - frame_adjust); |
1742 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1743 | be able to get rid of the assignment below, evetually. But it's | |
1744 | still needed for now. */ | |
72a155b4 UW |
1745 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1746 | + mips_regnum (gdbarch)->pc] | |
1747 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1748 | } |
1749 | ||
1750 | /* If we didn't reach the end of the prologue when scanning the function | |
1751 | instructions, then set end_prologue_addr to the address of the | |
1752 | instruction immediately after the last one we scanned. */ | |
1753 | if (end_prologue_addr == 0) | |
1754 | end_prologue_addr = cur_pc; | |
1755 | ||
1756 | return end_prologue_addr; | |
eec63939 AC |
1757 | } |
1758 | ||
29639122 JB |
1759 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1760 | Procedures that use the 32-bit instruction set are handled by the | |
1761 | mips_insn32 unwinder. */ | |
1762 | ||
1763 | static struct mips_frame_cache * | |
b8a22b94 | 1764 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1765 | { |
29639122 | 1766 | struct mips_frame_cache *cache; |
eec63939 AC |
1767 | |
1768 | if ((*this_cache) != NULL) | |
1769 | return (*this_cache); | |
29639122 JB |
1770 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1771 | (*this_cache) = cache; | |
b8a22b94 | 1772 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1773 | |
29639122 JB |
1774 | /* Analyze the function prologue. */ |
1775 | { | |
b8a22b94 | 1776 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1777 | CORE_ADDR start_addr; |
eec63939 | 1778 | |
29639122 JB |
1779 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1780 | if (start_addr == 0) | |
74ed0bb4 | 1781 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
1782 | /* We can't analyze the prologue if we couldn't find the begining |
1783 | of the function. */ | |
1784 | if (start_addr == 0) | |
1785 | return cache; | |
eec63939 | 1786 | |
b8a22b94 | 1787 | mips16_scan_prologue (start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1788 | } |
1789 | ||
3e8c568d | 1790 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1791 | trad_frame_set_value (cache->saved_regs, |
b8a22b94 DJ |
1792 | gdbarch_num_regs (get_frame_arch (this_frame)) |
1793 | + MIPS_SP_REGNUM, | |
72a155b4 | 1794 | cache->base); |
eec63939 | 1795 | |
29639122 | 1796 | return (*this_cache); |
eec63939 AC |
1797 | } |
1798 | ||
1799 | static void | |
b8a22b94 | 1800 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 1801 | struct frame_id *this_id) |
eec63939 | 1802 | { |
b8a22b94 | 1803 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1804 | this_cache); |
b8a22b94 | 1805 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
1806 | } |
1807 | ||
b8a22b94 DJ |
1808 | static struct value * |
1809 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
1810 | void **this_cache, int regnum) | |
eec63939 | 1811 | { |
b8a22b94 | 1812 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1813 | this_cache); |
b8a22b94 DJ |
1814 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1815 | } | |
1816 | ||
1817 | static int | |
1818 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
1819 | struct frame_info *this_frame, void **this_cache) | |
1820 | { | |
1821 | CORE_ADDR pc = get_frame_pc (this_frame); | |
1822 | if (mips_pc_is_mips16 (pc)) | |
1823 | return 1; | |
1824 | return 0; | |
eec63939 AC |
1825 | } |
1826 | ||
29639122 | 1827 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1828 | { |
1829 | NORMAL_FRAME, | |
29639122 | 1830 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
1831 | mips_insn16_frame_prev_register, |
1832 | NULL, | |
1833 | mips_insn16_frame_sniffer | |
eec63939 AC |
1834 | }; |
1835 | ||
eec63939 | 1836 | static CORE_ADDR |
b8a22b94 | 1837 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 1838 | void **this_cache) |
eec63939 | 1839 | { |
b8a22b94 | 1840 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
1841 | this_cache); |
1842 | return info->base; | |
eec63939 AC |
1843 | } |
1844 | ||
29639122 | 1845 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1846 | { |
29639122 JB |
1847 | &mips_insn16_frame_unwind, |
1848 | mips_insn16_frame_base_address, | |
1849 | mips_insn16_frame_base_address, | |
1850 | mips_insn16_frame_base_address | |
eec63939 AC |
1851 | }; |
1852 | ||
1853 | static const struct frame_base * | |
b8a22b94 | 1854 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 1855 | { |
b8a22b94 DJ |
1856 | CORE_ADDR pc = get_frame_pc (this_frame); |
1857 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 1858 | return &mips_insn16_frame_base; |
eec63939 AC |
1859 | else |
1860 | return NULL; | |
edfae063 AC |
1861 | } |
1862 | ||
29639122 JB |
1863 | /* Mark all the registers as unset in the saved_regs array |
1864 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1865 | ||
74ed0bb4 MD |
1866 | static void |
1867 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 1868 | { |
29639122 JB |
1869 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1870 | return; | |
1871 | ||
1872 | { | |
74ed0bb4 | 1873 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 1874 | int i; |
64159455 | 1875 | |
29639122 JB |
1876 | for (i = 0; i < num_regs; i++) |
1877 | { | |
1878 | this_cache->saved_regs[i].addr = -1; | |
1879 | } | |
1880 | } | |
c906108c SS |
1881 | } |
1882 | ||
29639122 JB |
1883 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1884 | the associated FRAME_CACHE if not null. | |
1885 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1886 | |
875e1767 | 1887 | static CORE_ADDR |
29639122 | 1888 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
b8a22b94 | 1889 | struct frame_info *this_frame, |
29639122 | 1890 | struct mips_frame_cache *this_cache) |
c906108c | 1891 | { |
29639122 JB |
1892 | CORE_ADDR cur_pc; |
1893 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1894 | CORE_ADDR sp; | |
1895 | long frame_offset; | |
1896 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1897 | |
29639122 JB |
1898 | CORE_ADDR end_prologue_addr = 0; |
1899 | int seen_sp_adjust = 0; | |
1900 | int load_immediate_bytes = 0; | |
db5f024e | 1901 | int in_delay_slot = 0; |
b8a22b94 | 1902 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
7d1e6fb8 | 1903 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 1904 | |
29639122 | 1905 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1906 | THIS_FRAME. */ |
1907 | if (this_frame != NULL) | |
1908 | sp = get_frame_register_signed (this_frame, | |
1909 | gdbarch_num_regs (gdbarch) | |
1910 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1911 | else |
29639122 | 1912 | sp = 0; |
9022177c | 1913 | |
29639122 JB |
1914 | if (limit_pc > start_pc + 200) |
1915 | limit_pc = start_pc + 200; | |
9022177c | 1916 | |
29639122 | 1917 | restart: |
9022177c | 1918 | |
29639122 | 1919 | frame_offset = 0; |
95ac2dcf | 1920 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1921 | { |
29639122 JB |
1922 | unsigned long inst, high_word, low_word; |
1923 | int reg; | |
9022177c | 1924 | |
29639122 JB |
1925 | /* Fetch the instruction. */ |
1926 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1927 | |
29639122 JB |
1928 | /* Save some code by pre-extracting some useful fields. */ |
1929 | high_word = (inst >> 16) & 0xffff; | |
1930 | low_word = inst & 0xffff; | |
1931 | reg = high_word & 0x1f; | |
fe29b929 | 1932 | |
29639122 JB |
1933 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1934 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1935 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1936 | { | |
1937 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1938 | frame_offset += 0x10000 - low_word; | |
1939 | else | |
1940 | /* Exit loop if a positive stack adjustment is found, which | |
1941 | usually means that the stack cleanup code in the function | |
1942 | epilogue is reached. */ | |
1943 | break; | |
1944 | seen_sp_adjust = 1; | |
1945 | } | |
7d1e6fb8 KB |
1946 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
1947 | && !regsize_is_64_bits) | |
29639122 | 1948 | { |
74ed0bb4 | 1949 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 1950 | } |
7d1e6fb8 KB |
1951 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
1952 | && regsize_is_64_bits) | |
29639122 JB |
1953 | { |
1954 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 1955 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
1956 | } |
1957 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1958 | { | |
1959 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1960 | if ((long) low_word != frame_offset) | |
1961 | frame_addr = sp + low_word; | |
b8a22b94 | 1962 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1963 | { |
1964 | unsigned alloca_adjust; | |
a4b8ebc8 | 1965 | |
29639122 | 1966 | frame_reg = 30; |
b8a22b94 DJ |
1967 | frame_addr = get_frame_register_signed |
1968 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 1969 | |
29639122 JB |
1970 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1971 | if (alloca_adjust > 0) | |
1972 | { | |
1973 | /* FP > SP + frame_size. This may be because of | |
1974 | an alloca or somethings similar. Fix sp to | |
1975 | "pre-alloca" value, and try again. */ | |
1976 | sp += alloca_adjust; | |
1977 | /* Need to reset the status of all registers. Otherwise, | |
1978 | we will hit a guard that prevents the new address | |
1979 | for each register to be recomputed during the second | |
1980 | pass. */ | |
74ed0bb4 | 1981 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
1982 | goto restart; |
1983 | } | |
1984 | } | |
1985 | } | |
1986 | /* move $30,$sp. With different versions of gas this will be either | |
1987 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1988 | Accept any one of these. */ | |
1989 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1990 | { | |
1991 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 1992 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1993 | { |
1994 | unsigned alloca_adjust; | |
c906108c | 1995 | |
29639122 | 1996 | frame_reg = 30; |
b8a22b94 DJ |
1997 | frame_addr = get_frame_register_signed |
1998 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 1999 | |
29639122 JB |
2000 | alloca_adjust = (unsigned) (frame_addr - sp); |
2001 | if (alloca_adjust > 0) | |
2002 | { | |
2003 | /* FP > SP + frame_size. This may be because of | |
2004 | an alloca or somethings similar. Fix sp to | |
2005 | "pre-alloca" value, and try again. */ | |
2006 | sp = frame_addr; | |
2007 | /* Need to reset the status of all registers. Otherwise, | |
2008 | we will hit a guard that prevents the new address | |
2009 | for each register to be recomputed during the second | |
2010 | pass. */ | |
74ed0bb4 | 2011 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2012 | goto restart; |
2013 | } | |
2014 | } | |
2015 | } | |
7d1e6fb8 KB |
2016 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2017 | && !regsize_is_64_bits) | |
29639122 | 2018 | { |
74ed0bb4 | 2019 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2020 | } |
2021 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2022 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2023 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2024 | || high_word == 0x3c1c /* lui $gp,n */ | |
2025 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2026 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2027 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2028 | ) | |
2029 | { | |
2030 | /* These instructions are part of the prologue, but we don't | |
2031 | need to do anything special to handle them. */ | |
2032 | } | |
2033 | /* The instructions below load $at or $t0 with an immediate | |
2034 | value in preparation for a stack adjustment via | |
2035 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2036 | initialize a local variable, so we accept them only before | |
2037 | a stack adjustment instruction was seen. */ | |
2038 | else if (!seen_sp_adjust | |
2039 | && (high_word == 0x3c01 /* lui $at,n */ | |
2040 | || high_word == 0x3c08 /* lui $t0,n */ | |
2041 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2042 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2043 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2044 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2045 | )) | |
2046 | { | |
95ac2dcf | 2047 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2048 | } |
2049 | else | |
2050 | { | |
2051 | /* This instruction is not an instruction typically found | |
2052 | in a prologue, so we must have reached the end of the | |
2053 | prologue. */ | |
2054 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2055 | loop now? Why would we need to continue scanning the function | |
2056 | instructions? */ | |
2057 | if (end_prologue_addr == 0) | |
2058 | end_prologue_addr = cur_pc; | |
db5f024e DJ |
2059 | |
2060 | /* Check for branches and jumps. For now, only jump to | |
2061 | register are caught (i.e. returns). */ | |
2062 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2063 | in_delay_slot = 1; | |
29639122 | 2064 | } |
db5f024e DJ |
2065 | |
2066 | /* If the previous instruction was a jump, we must have reached | |
2067 | the end of the prologue by now. Stop scanning so that we do | |
2068 | not go past the function return. */ | |
2069 | if (in_delay_slot) | |
2070 | break; | |
a4b8ebc8 | 2071 | } |
c906108c | 2072 | |
29639122 JB |
2073 | if (this_cache != NULL) |
2074 | { | |
2075 | this_cache->base = | |
b8a22b94 DJ |
2076 | (get_frame_register_signed (this_frame, |
2077 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2078 | + frame_offset); |
2079 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2080 | this assignment below, eventually. But it's still needed | |
2081 | for now. */ | |
72a155b4 UW |
2082 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2083 | + mips_regnum (gdbarch)->pc] | |
2084 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2085 | + MIPS_RA_REGNUM]; |
29639122 | 2086 | } |
c906108c | 2087 | |
29639122 JB |
2088 | /* If we didn't reach the end of the prologue when scanning the function |
2089 | instructions, then set end_prologue_addr to the address of the | |
2090 | instruction immediately after the last one we scanned. */ | |
2091 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2092 | we may as well be careful and do our best if we have a null | |
2093 | end_prologue_addr. */ | |
2094 | if (end_prologue_addr == 0) | |
2095 | end_prologue_addr = cur_pc; | |
2096 | ||
2097 | /* In a frameless function, we might have incorrectly | |
2098 | skipped some load immediate instructions. Undo the skipping | |
2099 | if the load immediate was not followed by a stack adjustment. */ | |
2100 | if (load_immediate_bytes && !seen_sp_adjust) | |
2101 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2102 | |
29639122 | 2103 | return end_prologue_addr; |
c906108c SS |
2104 | } |
2105 | ||
29639122 JB |
2106 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2107 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2108 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2109 | unwinder. */ | |
c906108c | 2110 | |
29639122 | 2111 | static struct mips_frame_cache * |
b8a22b94 | 2112 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2113 | { |
29639122 | 2114 | struct mips_frame_cache *cache; |
c906108c | 2115 | |
29639122 JB |
2116 | if ((*this_cache) != NULL) |
2117 | return (*this_cache); | |
c5aa993b | 2118 | |
29639122 JB |
2119 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2120 | (*this_cache) = cache; | |
b8a22b94 | 2121 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2122 | |
29639122 JB |
2123 | /* Analyze the function prologue. */ |
2124 | { | |
b8a22b94 | 2125 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2126 | CORE_ADDR start_addr; |
c906108c | 2127 | |
29639122 JB |
2128 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2129 | if (start_addr == 0) | |
74ed0bb4 | 2130 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
2131 | /* We can't analyze the prologue if we couldn't find the begining |
2132 | of the function. */ | |
2133 | if (start_addr == 0) | |
2134 | return cache; | |
c5aa993b | 2135 | |
b8a22b94 | 2136 | mips32_scan_prologue (start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2137 | } |
2138 | ||
3e8c568d | 2139 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2140 | trad_frame_set_value (cache->saved_regs, |
b8a22b94 DJ |
2141 | gdbarch_num_regs (get_frame_arch (this_frame)) |
2142 | + MIPS_SP_REGNUM, | |
f57d151a | 2143 | cache->base); |
c5aa993b | 2144 | |
29639122 | 2145 | return (*this_cache); |
c906108c SS |
2146 | } |
2147 | ||
29639122 | 2148 | static void |
b8a22b94 | 2149 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2150 | struct frame_id *this_id) |
c906108c | 2151 | { |
b8a22b94 | 2152 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2153 | this_cache); |
b8a22b94 | 2154 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2155 | } |
c906108c | 2156 | |
b8a22b94 DJ |
2157 | static struct value * |
2158 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2159 | void **this_cache, int regnum) | |
29639122 | 2160 | { |
b8a22b94 | 2161 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2162 | this_cache); |
b8a22b94 DJ |
2163 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2164 | } | |
2165 | ||
2166 | static int | |
2167 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2168 | struct frame_info *this_frame, void **this_cache) | |
2169 | { | |
2170 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2171 | if (! mips_pc_is_mips16 (pc)) | |
2172 | return 1; | |
2173 | return 0; | |
c906108c SS |
2174 | } |
2175 | ||
29639122 JB |
2176 | static const struct frame_unwind mips_insn32_frame_unwind = |
2177 | { | |
2178 | NORMAL_FRAME, | |
2179 | mips_insn32_frame_this_id, | |
b8a22b94 DJ |
2180 | mips_insn32_frame_prev_register, |
2181 | NULL, | |
2182 | mips_insn32_frame_sniffer | |
29639122 | 2183 | }; |
c906108c | 2184 | |
1c645fec | 2185 | static CORE_ADDR |
b8a22b94 | 2186 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2187 | void **this_cache) |
c906108c | 2188 | { |
b8a22b94 | 2189 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2190 | this_cache); |
2191 | return info->base; | |
2192 | } | |
c906108c | 2193 | |
29639122 JB |
2194 | static const struct frame_base mips_insn32_frame_base = |
2195 | { | |
2196 | &mips_insn32_frame_unwind, | |
2197 | mips_insn32_frame_base_address, | |
2198 | mips_insn32_frame_base_address, | |
2199 | mips_insn32_frame_base_address | |
2200 | }; | |
1c645fec | 2201 | |
29639122 | 2202 | static const struct frame_base * |
b8a22b94 | 2203 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2204 | { |
b8a22b94 DJ |
2205 | CORE_ADDR pc = get_frame_pc (this_frame); |
2206 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2207 | return &mips_insn32_frame_base; |
a65bbe44 | 2208 | else |
29639122 JB |
2209 | return NULL; |
2210 | } | |
a65bbe44 | 2211 | |
29639122 | 2212 | static struct trad_frame_cache * |
b8a22b94 | 2213 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2214 | { |
2215 | CORE_ADDR pc; | |
2216 | CORE_ADDR start_addr; | |
2217 | CORE_ADDR stack_addr; | |
2218 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2219 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2220 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2221 | |
29639122 JB |
2222 | if ((*this_cache) != NULL) |
2223 | return (*this_cache); | |
b8a22b94 | 2224 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2225 | (*this_cache) = this_trad_cache; |
1c645fec | 2226 | |
29639122 | 2227 | /* The return address is in the link register. */ |
3e8c568d | 2228 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2229 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2230 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2231 | |
29639122 JB |
2232 | /* Frame ID, since it's a frameless / stackless function, no stack |
2233 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2234 | pc = get_frame_pc (this_frame); |
29639122 | 2235 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2236 | stack_addr = get_frame_register_signed (this_frame, |
2237 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2238 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2239 | |
29639122 JB |
2240 | /* Assume that the frame's base is the same as the |
2241 | stack-pointer. */ | |
2242 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2243 | |
29639122 JB |
2244 | return this_trad_cache; |
2245 | } | |
c906108c | 2246 | |
29639122 | 2247 | static void |
b8a22b94 | 2248 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2249 | struct frame_id *this_id) |
2250 | { | |
2251 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2252 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2253 | trad_frame_get_id (this_trad_cache, this_id); |
2254 | } | |
c906108c | 2255 | |
b8a22b94 DJ |
2256 | static struct value * |
2257 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2258 | void **this_cache, int regnum) | |
29639122 JB |
2259 | { |
2260 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2261 | = mips_stub_frame_cache (this_frame, this_cache); |
2262 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2263 | } |
c906108c | 2264 | |
b8a22b94 DJ |
2265 | static int |
2266 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2267 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2268 | { |
aa6c981f | 2269 | gdb_byte dummy[4]; |
979b38e0 | 2270 | struct obj_section *s; |
b8a22b94 | 2271 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2272 | struct minimal_symbol *msym; |
979b38e0 | 2273 | |
aa6c981f | 2274 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2275 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2276 | return 1; | |
aa6c981f | 2277 | |
29639122 | 2278 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2279 | return 1; |
979b38e0 DJ |
2280 | |
2281 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2282 | s = find_pc_section (pc); | |
2283 | ||
2284 | if (s != NULL | |
2285 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2286 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2287 | return 1; |
979b38e0 | 2288 | |
db5f024e DJ |
2289 | /* Calling a PIC function from a non-PIC function passes through a |
2290 | stub. The stub for foo is named ".pic.foo". */ | |
2291 | msym = lookup_minimal_symbol_by_pc (pc); | |
2292 | if (msym != NULL | |
2293 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2294 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2295 | return 1; | |
2296 | ||
b8a22b94 | 2297 | return 0; |
29639122 | 2298 | } |
c906108c | 2299 | |
b8a22b94 DJ |
2300 | static const struct frame_unwind mips_stub_frame_unwind = |
2301 | { | |
2302 | NORMAL_FRAME, | |
2303 | mips_stub_frame_this_id, | |
2304 | mips_stub_frame_prev_register, | |
2305 | NULL, | |
2306 | mips_stub_frame_sniffer | |
2307 | }; | |
2308 | ||
29639122 | 2309 | static CORE_ADDR |
b8a22b94 | 2310 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2311 | void **this_cache) |
2312 | { | |
2313 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2314 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2315 | return trad_frame_get_this_base (this_trad_cache); |
2316 | } | |
0fce0821 | 2317 | |
29639122 JB |
2318 | static const struct frame_base mips_stub_frame_base = |
2319 | { | |
2320 | &mips_stub_frame_unwind, | |
2321 | mips_stub_frame_base_address, | |
2322 | mips_stub_frame_base_address, | |
2323 | mips_stub_frame_base_address | |
2324 | }; | |
2325 | ||
2326 | static const struct frame_base * | |
b8a22b94 | 2327 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2328 | { |
b8a22b94 | 2329 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2330 | return &mips_stub_frame_base; |
2331 | else | |
2332 | return NULL; | |
2333 | } | |
2334 | ||
29639122 | 2335 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2336 | |
29639122 | 2337 | static CORE_ADDR |
24568a2c | 2338 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2339 | { |
24568a2c | 2340 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
29639122 JB |
2341 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2342 | /* This hack is a work-around for existing boards using PMON, the | |
2343 | simulator, and any other 64-bit targets that doesn't have true | |
2344 | 64-bit addressing. On these targets, the upper 32 bits of | |
2345 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2346 | likely to have been sign extended to all 1s by instruction | |
2347 | sequences that load 32-bit addresses. For example, a typical | |
2348 | piece of code that loads an address is this: | |
65596487 | 2349 | |
29639122 JB |
2350 | lui $r2, <upper 16 bits> |
2351 | ori $r2, <lower 16 bits> | |
65596487 | 2352 | |
29639122 JB |
2353 | But the lui sign-extends the value such that the upper 32 bits |
2354 | may be all 1s. The workaround is simply to mask off these | |
2355 | bits. In the future, gcc may be changed to support true 64-bit | |
2356 | addressing, and this masking will have to be disabled. */ | |
2357 | return addr &= 0xffffffffUL; | |
2358 | else | |
2359 | return addr; | |
65596487 JB |
2360 | } |
2361 | ||
3d5f6d12 DJ |
2362 | /* Instructions used during single-stepping of atomic sequences. */ |
2363 | #define LL_OPCODE 0x30 | |
2364 | #define LLD_OPCODE 0x34 | |
2365 | #define SC_OPCODE 0x38 | |
2366 | #define SCD_OPCODE 0x3c | |
2367 | ||
2368 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2369 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2370 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2371 | the sequence. */ | |
2372 | ||
2373 | static int | |
2374 | deal_with_atomic_sequence (CORE_ADDR pc) | |
2375 | { | |
2376 | CORE_ADDR breaks[2] = {-1, -1}; | |
2377 | CORE_ADDR loc = pc; | |
2378 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2379 | unsigned long insn; | |
2380 | int insn_count; | |
2381 | int index; | |
2382 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2383 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2384 | ||
2385 | if (pc & 0x01) | |
2386 | return 0; | |
2387 | ||
2388 | insn = mips_fetch_instruction (loc); | |
2389 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
2390 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2391 | return 0; | |
2392 | ||
2393 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2394 | instructions. */ | |
2395 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2396 | { | |
2397 | int is_branch = 0; | |
2398 | loc += MIPS_INSN32_SIZE; | |
2399 | insn = mips_fetch_instruction (loc); | |
2400 | ||
2401 | /* Assume that there is at most one branch in the atomic | |
2402 | sequence. If a branch is found, put a breakpoint in its | |
2403 | destination address. */ | |
2404 | switch (itype_op (insn)) | |
2405 | { | |
2406 | case 0: /* SPECIAL */ | |
2407 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
2408 | return 0; /* fallback to the standard single-step code. */ | |
2409 | break; | |
2410 | case 1: /* REGIMM */ | |
2411 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2412 | break; | |
2413 | case 2: /* J */ | |
2414 | case 3: /* JAL */ | |
2415 | return 0; /* fallback to the standard single-step code. */ | |
2416 | case 4: /* BEQ */ | |
2417 | case 5: /* BNE */ | |
2418 | case 6: /* BLEZ */ | |
2419 | case 7: /* BGTZ */ | |
2420 | case 20: /* BEQL */ | |
2421 | case 21: /* BNEL */ | |
2422 | case 22: /* BLEZL */ | |
2423 | case 23: /* BGTTL */ | |
2424 | is_branch = 1; | |
2425 | break; | |
2426 | case 17: /* COP1 */ | |
2427 | case 18: /* COP2 */ | |
2428 | case 19: /* COP3 */ | |
2429 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2430 | break; | |
2431 | } | |
2432 | if (is_branch) | |
2433 | { | |
2434 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2435 | if (last_breakpoint >= 1) | |
2436 | return 0; /* More than one branch found, fallback to the | |
2437 | standard single-step code. */ | |
2438 | breaks[1] = branch_bp; | |
2439 | last_breakpoint++; | |
2440 | } | |
2441 | ||
2442 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2443 | break; | |
2444 | } | |
2445 | ||
2446 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2447 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2448 | return 0; | |
2449 | ||
2450 | loc += MIPS_INSN32_SIZE; | |
2451 | ||
2452 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2453 | breaks[0] = loc; | |
2454 | ||
2455 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
2456 | placed (branch instruction's destination) in the atomic sequence */ | |
2457 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
2458 | last_breakpoint = 0; | |
2459 | ||
2460 | /* Effectively inserts the breakpoints. */ | |
2461 | for (index = 0; index <= last_breakpoint; index++) | |
2462 | insert_single_step_breakpoint (breaks[index]); | |
2463 | ||
2464 | return 1; | |
2465 | } | |
2466 | ||
29639122 JB |
2467 | /* mips_software_single_step() is called just before we want to resume |
2468 | the inferior, if we want to single-step it but there is no hardware | |
2469 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2470 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2471 | |
e6590a1b | 2472 | int |
0b1b3e42 | 2473 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2474 | { |
8181d85f | 2475 | CORE_ADDR pc, next_pc; |
65596487 | 2476 | |
0b1b3e42 | 2477 | pc = get_frame_pc (frame); |
3d5f6d12 DJ |
2478 | if (deal_with_atomic_sequence (pc)) |
2479 | return 1; | |
2480 | ||
0b1b3e42 | 2481 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2482 | |
e0cd558a | 2483 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2484 | return 1; |
29639122 | 2485 | } |
a65bbe44 | 2486 | |
29639122 JB |
2487 | /* Test whether the PC points to the return instruction at the |
2488 | end of a function. */ | |
65596487 | 2489 | |
29639122 JB |
2490 | static int |
2491 | mips_about_to_return (CORE_ADDR pc) | |
2492 | { | |
0fe7e7c8 | 2493 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2494 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2495 | generates a "jr $ra"; other times it generates code to load | |
2496 | the return address from the stack to an accessible register (such | |
2497 | as $a3), then a "jr" using that register. This second case | |
2498 | is almost impossible to distinguish from an indirect jump | |
2499 | used for switch statements, so we don't even try. */ | |
2500 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2501 | else | |
2502 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2503 | } | |
c906108c | 2504 | |
c906108c | 2505 | |
29639122 JB |
2506 | /* This fencepost looks highly suspicious to me. Removing it also |
2507 | seems suspicious as it could affect remote debugging across serial | |
2508 | lines. */ | |
c906108c | 2509 | |
29639122 | 2510 | static CORE_ADDR |
74ed0bb4 | 2511 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2512 | { |
2513 | CORE_ADDR start_pc; | |
2514 | CORE_ADDR fence; | |
2515 | int instlen; | |
2516 | int seen_adjsp = 0; | |
d6b48e9c | 2517 | struct inferior *inf; |
65596487 | 2518 | |
74ed0bb4 | 2519 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2520 | start_pc = pc; |
2521 | fence = start_pc - heuristic_fence_post; | |
2522 | if (start_pc == 0) | |
2523 | return 0; | |
65596487 | 2524 | |
29639122 JB |
2525 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2526 | fence = VM_MIN_ADDRESS; | |
65596487 | 2527 | |
95ac2dcf | 2528 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2529 | |
d6b48e9c PA |
2530 | inf = current_inferior (); |
2531 | ||
29639122 JB |
2532 | /* search back for previous return */ |
2533 | for (start_pc -= instlen;; start_pc -= instlen) | |
2534 | if (start_pc < fence) | |
2535 | { | |
2536 | /* It's not clear to me why we reach this point when | |
2537 | stop_soon, but with this test, at least we | |
2538 | don't print out warnings for every child forked (eg, on | |
2539 | decstation). 22apr93 rich@cygnus.com. */ | |
d6b48e9c | 2540 | if (inf->stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2541 | { |
2542 | static int blurb_printed = 0; | |
98b4dd94 | 2543 | |
8a3fe4f8 | 2544 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2545 | paddr_nz (pc)); |
2546 | ||
2547 | if (!blurb_printed) | |
2548 | { | |
2549 | /* This actually happens frequently in embedded | |
2550 | development, when you first connect to a board | |
2551 | and your stack pointer and pc are nowhere in | |
2552 | particular. This message needs to give people | |
2553 | in that situation enough information to | |
2554 | determine that it's no big deal. */ | |
2555 | printf_filtered ("\n\ | |
2556 | GDB is unable to find the start of the function at 0x%s\n\ | |
2557 | and thus can't determine the size of that function's stack frame.\n\ | |
2558 | This means that GDB may be unable to access that stack frame, or\n\ | |
2559 | the frames below it.\n\ | |
2560 | This problem is most likely caused by an invalid program counter or\n\ | |
2561 | stack pointer.\n\ | |
2562 | However, if you think GDB should simply search farther back\n\ | |
2563 | from 0x%s for code which looks like the beginning of a\n\ | |
2564 | function, you can increase the range of the search using the `set\n\ | |
2565 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2566 | blurb_printed = 1; | |
2567 | } | |
2568 | } | |
2569 | ||
2570 | return 0; | |
2571 | } | |
0fe7e7c8 | 2572 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2573 | { |
2574 | unsigned short inst; | |
2575 | ||
2576 | /* On MIPS16, any one of the following is likely to be the | |
2577 | start of a function: | |
193774b3 MR |
2578 | extend save |
2579 | save | |
29639122 JB |
2580 | entry |
2581 | addiu sp,-n | |
2582 | daddiu sp,-n | |
2583 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2584 | inst = mips_fetch_instruction (start_pc); | |
193774b3 MR |
2585 | if ((inst & 0xff80) == 0x6480) /* save */ |
2586 | { | |
2587 | if (start_pc - instlen >= fence) | |
2588 | { | |
2589 | inst = mips_fetch_instruction (start_pc - instlen); | |
2590 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2591 | start_pc -= instlen; | |
2592 | } | |
2593 | break; | |
2594 | } | |
2595 | else if (((inst & 0xf81f) == 0xe809 | |
2596 | && (inst & 0x700) != 0x700) /* entry */ | |
2597 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2598 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2599 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2600 | break; |
2601 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2602 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2603 | seen_adjsp = 1; | |
2604 | else | |
2605 | seen_adjsp = 0; | |
2606 | } | |
2607 | else if (mips_about_to_return (start_pc)) | |
2608 | { | |
4c7d22cb | 2609 | /* Skip return and its delay slot. */ |
95ac2dcf | 2610 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2611 | break; |
2612 | } | |
2613 | ||
2614 | return start_pc; | |
c906108c SS |
2615 | } |
2616 | ||
6c0d6680 DJ |
2617 | struct mips_objfile_private |
2618 | { | |
2619 | bfd_size_type size; | |
2620 | char *contents; | |
2621 | }; | |
2622 | ||
f09ded24 AC |
2623 | /* According to the current ABI, should the type be passed in a |
2624 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2625 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2626 | FP registers and, consequently this returns false - forces FP |
2627 | arguments into integer registers. */ | |
2628 | ||
2629 | static int | |
74ed0bb4 MD |
2630 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2631 | struct type *arg_type) | |
f09ded24 AC |
2632 | { |
2633 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2634 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2635 | && (typecode == TYPE_CODE_STRUCT |
2636 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2637 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2638 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2639 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2640 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2641 | } |
2642 | ||
49e790b0 DJ |
2643 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2644 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2645 | ||
2646 | static int | |
2647 | mips_type_needs_double_align (struct type *type) | |
2648 | { | |
2649 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2650 | |
49e790b0 DJ |
2651 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2652 | return 1; | |
2653 | else if (typecode == TYPE_CODE_STRUCT) | |
2654 | { | |
2655 | if (TYPE_NFIELDS (type) < 1) | |
2656 | return 0; | |
2657 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2658 | } | |
2659 | else if (typecode == TYPE_CODE_UNION) | |
2660 | { | |
361d1df0 | 2661 | int i, n; |
49e790b0 DJ |
2662 | |
2663 | n = TYPE_NFIELDS (type); | |
2664 | for (i = 0; i < n; i++) | |
2665 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2666 | return 1; | |
2667 | return 0; | |
2668 | } | |
2669 | return 0; | |
2670 | } | |
2671 | ||
dc604539 AC |
2672 | /* Adjust the address downward (direction of stack growth) so that it |
2673 | is correctly aligned for a new stack frame. */ | |
2674 | static CORE_ADDR | |
2675 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2676 | { | |
5b03f266 | 2677 | return align_down (addr, 16); |
dc604539 AC |
2678 | } |
2679 | ||
f7ab6ec6 | 2680 | static CORE_ADDR |
7d9b040b | 2681 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2682 | struct regcache *regcache, CORE_ADDR bp_addr, |
2683 | int nargs, struct value **args, CORE_ADDR sp, | |
2684 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2685 | { |
2686 | int argreg; | |
2687 | int float_argreg; | |
2688 | int argnum; | |
2689 | int len = 0; | |
2690 | int stack_offset = 0; | |
480d3dd2 | 2691 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2692 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2693 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2694 | |
25ab4790 AC |
2695 | /* For shared libraries, "t9" needs to point at the function |
2696 | address. */ | |
4c7d22cb | 2697 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2698 | |
2699 | /* Set the return address register to point to the entry point of | |
2700 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2701 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2702 | |
c906108c | 2703 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2704 | are properly aligned. The stack has to be at least 64-bit |
2705 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2706 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2707 | aligned, so we round to this widest known alignment. */ | |
2708 | ||
5b03f266 AC |
2709 | sp = align_down (sp, 16); |
2710 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2711 | |
46e0f506 | 2712 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2713 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2714 | passed in registers, but that's OK. */ |
c906108c | 2715 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2716 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2717 | sp -= align_up (len, 16); |
c906108c | 2718 | |
9ace0497 | 2719 | if (mips_debug) |
6d82d43b | 2720 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2721 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2722 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2723 | |
c906108c | 2724 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2725 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2726 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2727 | |
46e0f506 | 2728 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2729 | if (struct_return) |
9ace0497 AC |
2730 | { |
2731 | if (mips_debug) | |
2732 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2733 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2734 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2735 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2736 | } |
c906108c SS |
2737 | |
2738 | /* Now load as many as possible of the first arguments into | |
2739 | registers, and push the rest onto the stack. Loop thru args | |
2740 | from first to last. */ | |
2741 | for (argnum = 0; argnum < nargs; argnum++) | |
2742 | { | |
47a35522 MK |
2743 | const gdb_byte *val; |
2744 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2745 | struct value *arg = args[argnum]; |
4991999e | 2746 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2747 | int len = TYPE_LENGTH (arg_type); |
2748 | enum type_code typecode = TYPE_CODE (arg_type); | |
2749 | ||
9ace0497 AC |
2750 | if (mips_debug) |
2751 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2752 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2753 | argnum + 1, len, (int) typecode); |
9ace0497 | 2754 | |
c906108c | 2755 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2756 | reference. */ |
1a69e1e4 | 2757 | if (len > regsize |
9ace0497 | 2758 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2759 | { |
1a69e1e4 | 2760 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2761 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2762 | len = regsize; |
c906108c | 2763 | val = valbuf; |
9ace0497 AC |
2764 | if (mips_debug) |
2765 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2766 | } |
2767 | else | |
47a35522 | 2768 | val = value_contents (arg); |
c906108c SS |
2769 | |
2770 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2771 | even-numbered floating point register. Round the FP register |
2772 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2773 | left. Non MIPS_EABI targets also pass the FP in the integer |
2774 | registers so also round up normal registers. */ | |
74ed0bb4 | 2775 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
2776 | { |
2777 | if ((float_argreg & 1)) | |
2778 | float_argreg++; | |
2779 | } | |
c906108c SS |
2780 | |
2781 | /* Floating point arguments passed in registers have to be | |
2782 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2783 | are passed in register pairs; the even register gets |
2784 | the low word, and the odd register gets the high word. | |
2785 | On non-EABI processors, the first two floating point arguments are | |
2786 | also copied to general registers, because MIPS16 functions | |
2787 | don't use float registers for arguments. This duplication of | |
2788 | arguments in general registers can't hurt non-MIPS16 functions | |
2789 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2790 | /* MIPS_EABI squeezes a struct that contains a single floating |
2791 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2792 | stack. */ |
74ed0bb4 MD |
2793 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
2794 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 2795 | { |
6da397e0 KB |
2796 | /* EABI32 will pass doubles in consecutive registers, even on |
2797 | 64-bit cores. At one time, we used to check the size of | |
2798 | `float_argreg' to determine whether or not to pass doubles | |
2799 | in consecutive registers, but this is not sufficient for | |
2800 | making the ABI determination. */ | |
2801 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2802 | { |
72a155b4 | 2803 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 2804 | == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2805 | unsigned long regval; |
2806 | ||
2807 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2808 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2809 | if (mips_debug) |
acdb74a0 | 2810 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2811 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2812 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2813 | |
2814 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2815 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2816 | if (mips_debug) |
acdb74a0 | 2817 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2818 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2819 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2820 | } |
2821 | else | |
2822 | { | |
2823 | /* This is a floating point value that fits entirely | |
2824 | in a single register. */ | |
53a5351d | 2825 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2826 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2827 | LONGEST regval = extract_unsigned_integer (val, len); |
2828 | if (mips_debug) | |
acdb74a0 | 2829 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2830 | float_argreg, phex (regval, len)); |
9c9acae0 | 2831 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2832 | } |
2833 | } | |
2834 | else | |
2835 | { | |
2836 | /* Copy the argument to general registers or the stack in | |
2837 | register-sized pieces. Large arguments are split between | |
2838 | registers and stack. */ | |
1a69e1e4 DJ |
2839 | /* Note: structs whose size is not a multiple of regsize |
2840 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2841 | them in registers where gcc sometimes puts them on the |
2842 | stack. For maximum compatibility, we will put them in | |
2843 | both places. */ | |
1a69e1e4 | 2844 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2845 | |
f09ded24 | 2846 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2847 | register are only written to memory. */ |
c906108c SS |
2848 | while (len > 0) |
2849 | { | |
ebafbe83 | 2850 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2851 | int stack_used_p = 0; |
1a69e1e4 | 2852 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2853 | |
acdb74a0 AC |
2854 | if (mips_debug) |
2855 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2856 | partial_len); | |
2857 | ||
566f0f7a | 2858 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 2859 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 2860 | || odd_sized_struct |
74ed0bb4 | 2861 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 2862 | { |
c906108c SS |
2863 | /* Should shorter than int integer values be |
2864 | promoted to int before being stored? */ | |
c906108c | 2865 | int longword_offset = 0; |
9ace0497 | 2866 | CORE_ADDR addr; |
566f0f7a | 2867 | stack_used_p = 1; |
72a155b4 | 2868 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2869 | { |
1a69e1e4 | 2870 | if (regsize == 8 |
480d3dd2 AC |
2871 | && (typecode == TYPE_CODE_INT |
2872 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2873 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2874 | longword_offset = regsize - len; |
480d3dd2 AC |
2875 | else if ((typecode == TYPE_CODE_STRUCT |
2876 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2877 | && TYPE_LENGTH (arg_type) < regsize) |
2878 | longword_offset = regsize - len; | |
7a292a7a | 2879 | } |
c5aa993b | 2880 | |
9ace0497 AC |
2881 | if (mips_debug) |
2882 | { | |
cb3d25d1 MS |
2883 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2884 | paddr_nz (stack_offset)); | |
2885 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2886 | paddr_nz (longword_offset)); | |
9ace0497 | 2887 | } |
361d1df0 | 2888 | |
9ace0497 AC |
2889 | addr = sp + stack_offset + longword_offset; |
2890 | ||
2891 | if (mips_debug) | |
2892 | { | |
2893 | int i; | |
6d82d43b | 2894 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2895 | paddr_nz (addr)); |
9ace0497 AC |
2896 | for (i = 0; i < partial_len; i++) |
2897 | { | |
6d82d43b | 2898 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2899 | val[i] & 0xff); |
9ace0497 AC |
2900 | } |
2901 | } | |
2902 | write_memory (addr, val, partial_len); | |
c906108c SS |
2903 | } |
2904 | ||
f09ded24 AC |
2905 | /* Note!!! This is NOT an else clause. Odd sized |
2906 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2907 | arguments will not. */ |
566f0f7a | 2908 | /* Write this portion of the argument to a general |
6d82d43b | 2909 | purpose register. */ |
74ed0bb4 MD |
2910 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
2911 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 2912 | { |
6d82d43b AC |
2913 | LONGEST regval = |
2914 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2915 | |
9ace0497 | 2916 | if (mips_debug) |
acdb74a0 | 2917 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2918 | argreg, |
1a69e1e4 | 2919 | phex (regval, regsize)); |
9c9acae0 | 2920 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
c906108c | 2921 | argreg++; |
c906108c | 2922 | } |
c5aa993b | 2923 | |
c906108c SS |
2924 | len -= partial_len; |
2925 | val += partial_len; | |
2926 | ||
566f0f7a | 2927 | /* Compute the the offset into the stack at which we |
6d82d43b | 2928 | will copy the next parameter. |
566f0f7a | 2929 | |
566f0f7a | 2930 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2931 | only needs to be adjusted when it has been used. */ |
c906108c | 2932 | |
46e0f506 | 2933 | if (stack_used_p) |
1a69e1e4 | 2934 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2935 | } |
2936 | } | |
9ace0497 AC |
2937 | if (mips_debug) |
2938 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2939 | } |
2940 | ||
f10683bb | 2941 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2942 | |
0f71a2f6 JM |
2943 | /* Return adjusted stack pointer. */ |
2944 | return sp; | |
2945 | } | |
2946 | ||
a1f5b845 | 2947 | /* Determine the return value convention being used. */ |
6d82d43b | 2948 | |
9c8fdbfa | 2949 | static enum return_value_convention |
c055b101 | 2950 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 2951 | struct type *type, struct regcache *regcache, |
47a35522 | 2952 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2953 | { |
609ba780 JM |
2954 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2955 | int fp_return_type = 0; | |
2956 | int offset, regnum, xfer; | |
2957 | ||
9c8fdbfa AC |
2958 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2959 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
2960 | |
2961 | /* Floating point type? */ | |
2962 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2963 | { | |
2964 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2965 | fp_return_type = 1; | |
2966 | /* Structs with a single field of float type | |
2967 | are returned in a floating point register. */ | |
2968 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2969 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2970 | && TYPE_NFIELDS (type) == 1) | |
2971 | { | |
2972 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
2973 | ||
2974 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
2975 | fp_return_type = 1; | |
2976 | } | |
2977 | } | |
2978 | ||
2979 | if (fp_return_type) | |
2980 | { | |
2981 | /* A floating-point value belongs in the least significant part | |
2982 | of FP0/FP1. */ | |
2983 | if (mips_debug) | |
2984 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
2985 | regnum = mips_regnum (gdbarch)->fp0; | |
2986 | } | |
2987 | else | |
2988 | { | |
2989 | /* An integer value goes in V0/V1. */ | |
2990 | if (mips_debug) | |
2991 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
2992 | regnum = MIPS_V0_REGNUM; | |
2993 | } | |
2994 | for (offset = 0; | |
2995 | offset < TYPE_LENGTH (type); | |
2996 | offset += mips_abi_regsize (gdbarch), regnum++) | |
2997 | { | |
2998 | xfer = mips_abi_regsize (gdbarch); | |
2999 | if (offset + xfer > TYPE_LENGTH (type)) | |
3000 | xfer = TYPE_LENGTH (type) - offset; | |
3001 | mips_xfer_register (gdbarch, regcache, | |
3002 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3003 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3004 | offset); | |
3005 | } | |
3006 | ||
9c8fdbfa | 3007 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3008 | } |
3009 | ||
6d82d43b AC |
3010 | |
3011 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3012 | |
8d26208a DJ |
3013 | /* Search for a naturally aligned double at OFFSET inside a struct |
3014 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3015 | registers. */ | |
3016 | ||
3017 | static int | |
74ed0bb4 MD |
3018 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3019 | int offset) | |
8d26208a DJ |
3020 | { |
3021 | int i; | |
3022 | ||
3023 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3024 | return 0; | |
3025 | ||
74ed0bb4 | 3026 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3027 | return 0; |
3028 | ||
3029 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3030 | return 0; | |
3031 | ||
3032 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3033 | { | |
3034 | int pos; | |
3035 | struct type *field_type; | |
3036 | ||
3037 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3038 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3039 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3040 | continue; | |
3041 | ||
3042 | /* If we have gone past the offset, there is no double to pass. */ | |
3043 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3044 | if (pos > offset) | |
3045 | return 0; | |
3046 | ||
3047 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3048 | ||
3049 | /* If this field is entirely before the requested offset, go | |
3050 | on to the next one. */ | |
3051 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3052 | continue; | |
3053 | ||
3054 | /* If this is our special aligned double, we can stop. */ | |
3055 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3056 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3057 | return 1; | |
3058 | ||
3059 | /* This field starts at or before the requested offset, and | |
3060 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3061 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3062 | } |
3063 | ||
3064 | return 0; | |
3065 | } | |
3066 | ||
f7ab6ec6 | 3067 | static CORE_ADDR |
7d9b040b | 3068 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3069 | struct regcache *regcache, CORE_ADDR bp_addr, |
3070 | int nargs, struct value **args, CORE_ADDR sp, | |
3071 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3072 | { |
3073 | int argreg; | |
3074 | int float_argreg; | |
3075 | int argnum; | |
3076 | int len = 0; | |
3077 | int stack_offset = 0; | |
480d3dd2 | 3078 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3079 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3080 | |
25ab4790 AC |
3081 | /* For shared libraries, "t9" needs to point at the function |
3082 | address. */ | |
4c7d22cb | 3083 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3084 | |
3085 | /* Set the return address register to point to the entry point of | |
3086 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3087 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3088 | |
cb3d25d1 MS |
3089 | /* First ensure that the stack and structure return address (if any) |
3090 | are properly aligned. The stack has to be at least 64-bit | |
3091 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3092 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3093 | aligned, so we round to this widest known alignment. */ | |
3094 | ||
5b03f266 AC |
3095 | sp = align_down (sp, 16); |
3096 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3097 | |
3098 | /* Now make space on the stack for the args. */ | |
3099 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3100 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3101 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3102 | |
3103 | if (mips_debug) | |
6d82d43b | 3104 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3105 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3106 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3107 | |
3108 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3109 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3110 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3111 | |
46e0f506 | 3112 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3113 | if (struct_return) |
3114 | { | |
3115 | if (mips_debug) | |
3116 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3117 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 3118 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3119 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3120 | } |
3121 | ||
3122 | /* Now load as many as possible of the first arguments into | |
3123 | registers, and push the rest onto the stack. Loop thru args | |
3124 | from first to last. */ | |
3125 | for (argnum = 0; argnum < nargs; argnum++) | |
3126 | { | |
47a35522 | 3127 | const gdb_byte *val; |
cb3d25d1 | 3128 | struct value *arg = args[argnum]; |
4991999e | 3129 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3130 | int len = TYPE_LENGTH (arg_type); |
3131 | enum type_code typecode = TYPE_CODE (arg_type); | |
3132 | ||
3133 | if (mips_debug) | |
3134 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3135 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3136 | argnum + 1, len, (int) typecode); |
3137 | ||
47a35522 | 3138 | val = value_contents (arg); |
cb3d25d1 | 3139 | |
5b68030f JM |
3140 | /* A 128-bit long double value requires an even-odd pair of |
3141 | floating-point registers. */ | |
3142 | if (len == 16 | |
3143 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3144 | && (float_argreg & 1)) | |
3145 | { | |
3146 | float_argreg++; | |
3147 | argreg++; | |
3148 | } | |
3149 | ||
74ed0bb4 MD |
3150 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3151 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3152 | { |
3153 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3154 | in a single register or a pair of registers. */ |
3155 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
3156 | LONGEST regval = extract_unsigned_integer (val, reglen); | |
cb3d25d1 MS |
3157 | if (mips_debug) |
3158 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3159 | float_argreg, phex (regval, reglen)); |
8d26208a | 3160 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3161 | |
3162 | if (mips_debug) | |
3163 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3164 | argreg, phex (regval, reglen)); |
9c9acae0 | 3165 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3166 | float_argreg++; |
3167 | argreg++; | |
5b68030f JM |
3168 | if (len == 16) |
3169 | { | |
3170 | regval = extract_unsigned_integer (val + reglen, reglen); | |
3171 | if (mips_debug) | |
3172 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3173 | float_argreg, phex (regval, reglen)); | |
3174 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3175 | ||
3176 | if (mips_debug) | |
3177 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3178 | argreg, phex (regval, reglen)); | |
3179 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3180 | float_argreg++; | |
3181 | argreg++; | |
3182 | } | |
cb3d25d1 MS |
3183 | } |
3184 | else | |
3185 | { | |
3186 | /* Copy the argument to general registers or the stack in | |
3187 | register-sized pieces. Large arguments are split between | |
3188 | registers and stack. */ | |
ab2e1992 MR |
3189 | /* For N32/N64, structs, unions, or other composite types are |
3190 | treated as a sequence of doublewords, and are passed in integer | |
3191 | or floating point registers as though they were simple scalar | |
3192 | parameters to the extent that they fit, with any excess on the | |
3193 | stack packed according to the normal memory layout of the | |
3194 | object. | |
3195 | The caller does not reserve space for the register arguments; | |
3196 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3197 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3198 | register are only written to memory. */ |
cb3d25d1 MS |
3199 | while (len > 0) |
3200 | { | |
ad018eee | 3201 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3202 | int stack_used_p = 0; |
1a69e1e4 | 3203 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3204 | |
3205 | if (mips_debug) | |
3206 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3207 | partial_len); | |
3208 | ||
74ed0bb4 MD |
3209 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3210 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3211 | |
cb3d25d1 | 3212 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3213 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3214 | { |
3215 | /* Should shorter than int integer values be | |
3216 | promoted to int before being stored? */ | |
3217 | int longword_offset = 0; | |
3218 | CORE_ADDR addr; | |
3219 | stack_used_p = 1; | |
72a155b4 | 3220 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3221 | { |
1a69e1e4 | 3222 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3223 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3224 | && len <= 4) |
3225 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3226 | } |
3227 | ||
3228 | if (mips_debug) | |
3229 | { | |
3230 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3231 | paddr_nz (stack_offset)); | |
3232 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3233 | paddr_nz (longword_offset)); | |
3234 | } | |
3235 | ||
3236 | addr = sp + stack_offset + longword_offset; | |
3237 | ||
3238 | if (mips_debug) | |
3239 | { | |
3240 | int i; | |
6d82d43b | 3241 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3242 | paddr_nz (addr)); |
3243 | for (i = 0; i < partial_len; i++) | |
3244 | { | |
6d82d43b | 3245 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3246 | val[i] & 0xff); |
3247 | } | |
3248 | } | |
3249 | write_memory (addr, val, partial_len); | |
3250 | } | |
3251 | ||
3252 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3253 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3254 | /* Write this portion of the argument to a general |
6d82d43b | 3255 | purpose register. */ |
74ed0bb4 | 3256 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3257 | { |
5863b5d5 MR |
3258 | LONGEST regval; |
3259 | ||
3260 | /* Sign extend pointers, 32-bit integers and signed | |
3261 | 16-bit and 8-bit integers; everything else is taken | |
3262 | as is. */ | |
3263 | ||
3264 | if ((partial_len == 4 | |
3265 | && (typecode == TYPE_CODE_PTR | |
3266 | || typecode == TYPE_CODE_INT)) | |
3267 | || (partial_len < 4 | |
3268 | && typecode == TYPE_CODE_INT | |
3269 | && !TYPE_UNSIGNED (arg_type))) | |
3270 | regval = extract_signed_integer (val, partial_len); | |
3271 | else | |
3272 | regval = extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3273 | |
3274 | /* A non-floating-point argument being passed in a | |
3275 | general register. If a struct or union, and if | |
3276 | the remaining length is smaller than the register | |
3277 | size, we have to adjust the register value on | |
3278 | big endian targets. | |
3279 | ||
3280 | It does not seem to be necessary to do the | |
1a69e1e4 | 3281 | same for integral types. */ |
cb3d25d1 | 3282 | |
72a155b4 | 3283 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3284 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3285 | && (typecode == TYPE_CODE_STRUCT |
3286 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3287 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3288 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3289 | |
3290 | if (mips_debug) | |
3291 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3292 | argreg, | |
1a69e1e4 | 3293 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3294 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3295 | |
74ed0bb4 | 3296 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3297 | TYPE_LENGTH (arg_type) - len)) |
3298 | { | |
3299 | if (mips_debug) | |
3300 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3301 | float_argreg, | |
3302 | phex (regval, MIPS64_REGSIZE)); | |
3303 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3304 | regval); | |
3305 | } | |
3306 | ||
3307 | float_argreg++; | |
cb3d25d1 MS |
3308 | argreg++; |
3309 | } | |
3310 | ||
3311 | len -= partial_len; | |
3312 | val += partial_len; | |
3313 | ||
3314 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3315 | will copy the next parameter. |
cb3d25d1 MS |
3316 | |
3317 | In N32 (N64?), the stack_offset only needs to be | |
3318 | adjusted when it has been used. */ | |
3319 | ||
3320 | if (stack_used_p) | |
1a69e1e4 | 3321 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3322 | } |
3323 | } | |
3324 | if (mips_debug) | |
3325 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3326 | } | |
3327 | ||
f10683bb | 3328 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3329 | |
cb3d25d1 MS |
3330 | /* Return adjusted stack pointer. */ |
3331 | return sp; | |
3332 | } | |
3333 | ||
6d82d43b | 3334 | static enum return_value_convention |
c055b101 | 3335 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3336 | struct type *type, struct regcache *regcache, |
47a35522 | 3337 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3338 | { |
72a155b4 | 3339 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3340 | |
3341 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3342 | ||
3343 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3344 | if needed), as appropriate for the type. Composite results (struct, | |
3345 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3346 | following rules: | |
3347 | ||
3348 | * A struct with only one or two floating point fields is returned in $f0 | |
3349 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3350 | case. | |
3351 | ||
3352 | * Any other struct or union results of at most 128 bits are returned in | |
3353 | $2 (first 64 bits) and $3 (remainder, if necessary). | |
3354 | ||
3355 | * Larger composite results are handled by converting the function to a | |
3356 | procedure with an implicit first parameter, which is a pointer to an area | |
3357 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3358 | that all composite results be handled by conversion to implicit first | |
3359 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3360 | specific exception to return COMPLEX results in the floating point | |
3361 | registers.] */ | |
3362 | ||
3363 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3364 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3365 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3366 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3367 | && TYPE_LENGTH (type) == 16 | |
3368 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3369 | { | |
3370 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3371 | two registers are used in the same as memory order, so the | |
3372 | eight bytes with the lower memory address are in $f0. */ | |
3373 | if (mips_debug) | |
3374 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3375 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3376 | gdbarch_num_regs (gdbarch) |
3377 | + mips_regnum (gdbarch)->fp0, | |
3378 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3379 | readbuf, writebuf, 0); |
ba32f989 | 3380 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3381 | gdbarch_num_regs (gdbarch) |
3382 | + mips_regnum (gdbarch)->fp0 + 2, | |
3383 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3384 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3385 | writebuf ? writebuf + 8 : writebuf, 0); |
3386 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3387 | } | |
6d82d43b AC |
3388 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3389 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3390 | { | |
59aa1faa | 3391 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3392 | if (mips_debug) |
3393 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3394 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3395 | gdbarch_num_regs (gdbarch) |
3396 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3397 | TYPE_LENGTH (type), |
72a155b4 | 3398 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3399 | readbuf, writebuf, 0); |
6d82d43b AC |
3400 | return RETURN_VALUE_REGISTER_CONVENTION; |
3401 | } | |
3402 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3403 | && TYPE_NFIELDS (type) <= 2 | |
3404 | && TYPE_NFIELDS (type) >= 1 | |
3405 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3406 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3407 | == TYPE_CODE_FLT)) |
3408 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3409 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3410 | == TYPE_CODE_FLT) |
b18bb924 | 3411 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3412 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3413 | { |
3414 | /* A struct that contains one or two floats. Each value is part | |
3415 | in the least significant part of their floating point | |
5b68030f | 3416 | register (or GPR, for soft float). */ |
6d82d43b AC |
3417 | int regnum; |
3418 | int field; | |
5b68030f JM |
3419 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3420 | ? mips_regnum (gdbarch)->fp0 | |
3421 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3422 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3423 | { | |
3424 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3425 | / TARGET_CHAR_BIT); | |
3426 | if (mips_debug) | |
3427 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3428 | offset); | |
5b68030f JM |
3429 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3430 | { | |
3431 | /* A 16-byte long double field goes in two consecutive | |
3432 | registers. */ | |
3433 | mips_xfer_register (gdbarch, regcache, | |
3434 | gdbarch_num_regs (gdbarch) + regnum, | |
3435 | 8, | |
3436 | gdbarch_byte_order (gdbarch), | |
3437 | readbuf, writebuf, offset); | |
3438 | mips_xfer_register (gdbarch, regcache, | |
3439 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3440 | 8, | |
3441 | gdbarch_byte_order (gdbarch), | |
3442 | readbuf, writebuf, offset + 8); | |
3443 | } | |
3444 | else | |
3445 | mips_xfer_register (gdbarch, regcache, | |
3446 | gdbarch_num_regs (gdbarch) + regnum, | |
3447 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3448 | gdbarch_byte_order (gdbarch), | |
3449 | readbuf, writebuf, offset); | |
6d82d43b AC |
3450 | } |
3451 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3452 | } | |
3453 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3454 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3455 | { | |
3456 | /* A structure or union. Extract the left justified value, | |
3457 | regardless of the byte order. I.e. DO NOT USE | |
3458 | mips_xfer_lower. */ | |
3459 | int offset; | |
3460 | int regnum; | |
4c7d22cb | 3461 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3462 | offset < TYPE_LENGTH (type); |
72a155b4 | 3463 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3464 | { |
72a155b4 | 3465 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3466 | if (offset + xfer > TYPE_LENGTH (type)) |
3467 | xfer = TYPE_LENGTH (type) - offset; | |
3468 | if (mips_debug) | |
3469 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3470 | offset, xfer, regnum); | |
ba32f989 DJ |
3471 | mips_xfer_register (gdbarch, regcache, |
3472 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3473 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3474 | offset); | |
6d82d43b AC |
3475 | } |
3476 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3477 | } | |
3478 | else | |
3479 | { | |
3480 | /* A scalar extract each part but least-significant-byte | |
3481 | justified. */ | |
3482 | int offset; | |
3483 | int regnum; | |
4c7d22cb | 3484 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3485 | offset < TYPE_LENGTH (type); |
72a155b4 | 3486 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3487 | { |
72a155b4 | 3488 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3489 | if (offset + xfer > TYPE_LENGTH (type)) |
3490 | xfer = TYPE_LENGTH (type) - offset; | |
3491 | if (mips_debug) | |
3492 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3493 | offset, xfer, regnum); | |
ba32f989 DJ |
3494 | mips_xfer_register (gdbarch, regcache, |
3495 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3496 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3497 | readbuf, writebuf, offset); |
6d82d43b AC |
3498 | } |
3499 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3500 | } | |
3501 | } | |
3502 | ||
3503 | /* O32 ABI stuff. */ | |
3504 | ||
3505 | static CORE_ADDR | |
7d9b040b | 3506 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3507 | struct regcache *regcache, CORE_ADDR bp_addr, |
3508 | int nargs, struct value **args, CORE_ADDR sp, | |
3509 | int struct_return, CORE_ADDR struct_addr) | |
3510 | { | |
3511 | int argreg; | |
3512 | int float_argreg; | |
3513 | int argnum; | |
3514 | int len = 0; | |
3515 | int stack_offset = 0; | |
3516 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3517 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3518 | |
3519 | /* For shared libraries, "t9" needs to point at the function | |
3520 | address. */ | |
4c7d22cb | 3521 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3522 | |
3523 | /* Set the return address register to point to the entry point of | |
3524 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3525 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3526 | |
3527 | /* First ensure that the stack and structure return address (if any) | |
3528 | are properly aligned. The stack has to be at least 64-bit | |
3529 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3530 | aligned. For n32 and n64, stack frames need to be 128-bit |
3531 | aligned, so we round to this widest known alignment. */ | |
3532 | ||
5b03f266 AC |
3533 | sp = align_down (sp, 16); |
3534 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3535 | |
3536 | /* Now make space on the stack for the args. */ | |
3537 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3538 | { |
3539 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3540 | int arglen = TYPE_LENGTH (arg_type); | |
3541 | ||
3542 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3543 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3544 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3545 | /* Allocate space on the stack. */ |
1a69e1e4 | 3546 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3547 | } |
5b03f266 | 3548 | sp -= align_up (len, 16); |
ebafbe83 MS |
3549 | |
3550 | if (mips_debug) | |
6d82d43b | 3551 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3552 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3553 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3554 | |
3555 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3556 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3557 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3558 | |
bcb0cc15 | 3559 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3560 | if (struct_return) |
3561 | { | |
3562 | if (mips_debug) | |
3563 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3564 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 | 3565 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3566 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3567 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3568 | } |
3569 | ||
3570 | /* Now load as many as possible of the first arguments into | |
3571 | registers, and push the rest onto the stack. Loop thru args | |
3572 | from first to last. */ | |
3573 | for (argnum = 0; argnum < nargs; argnum++) | |
3574 | { | |
47a35522 | 3575 | const gdb_byte *val; |
ebafbe83 | 3576 | struct value *arg = args[argnum]; |
4991999e | 3577 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3578 | int len = TYPE_LENGTH (arg_type); |
3579 | enum type_code typecode = TYPE_CODE (arg_type); | |
3580 | ||
3581 | if (mips_debug) | |
3582 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3583 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3584 | argnum + 1, len, (int) typecode); |
3585 | ||
47a35522 | 3586 | val = value_contents (arg); |
46cac009 AC |
3587 | |
3588 | /* 32-bit ABIs always start floating point arguments in an | |
3589 | even-numbered floating point register. Round the FP register | |
3590 | up before the check to see if there are any FP registers | |
3591 | left. O32/O64 targets also pass the FP in the integer | |
3592 | registers so also round up normal registers. */ | |
74ed0bb4 | 3593 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3594 | { |
3595 | if ((float_argreg & 1)) | |
3596 | float_argreg++; | |
3597 | } | |
3598 | ||
3599 | /* Floating point arguments passed in registers have to be | |
3600 | treated specially. On 32-bit architectures, doubles | |
3601 | are passed in register pairs; the even register gets | |
3602 | the low word, and the odd register gets the high word. | |
3603 | On O32/O64, the first two floating point arguments are | |
3604 | also copied to general registers, because MIPS16 functions | |
3605 | don't use float registers for arguments. This duplication of | |
3606 | arguments in general registers can't hurt non-MIPS16 functions | |
3607 | because those registers are normally skipped. */ | |
3608 | ||
74ed0bb4 MD |
3609 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3610 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3611 | { |
8b07f6d8 | 3612 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3613 | { |
72a155b4 | 3614 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3615 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3616 | unsigned long regval; |
3617 | ||
3618 | /* Write the low word of the double to the even register(s). */ | |
3619 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3620 | if (mips_debug) | |
3621 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3622 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3623 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3624 | if (mips_debug) |
3625 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3626 | argreg, phex (regval, 4)); | |
9c9acae0 | 3627 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3628 | |
3629 | /* Write the high word of the double to the odd register(s). */ | |
3630 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3631 | if (mips_debug) | |
3632 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3633 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3634 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3635 | |
3636 | if (mips_debug) | |
3637 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3638 | argreg, phex (regval, 4)); | |
9c9acae0 | 3639 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3640 | } |
3641 | else | |
3642 | { | |
3643 | /* This is a floating point value that fits entirely | |
3644 | in a single register. */ | |
3645 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3646 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3647 | LONGEST regval = extract_unsigned_integer (val, len); |
3648 | if (mips_debug) | |
3649 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3650 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3651 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
5b68030f JM |
3652 | /* Although two FP registers are reserved for each |
3653 | argument, only one corresponding integer register is | |
3654 | reserved. */ | |
46cac009 AC |
3655 | if (mips_debug) |
3656 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3657 | argreg, phex (regval, len)); | |
5b68030f | 3658 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3659 | } |
3660 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3661 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3662 | } |
3663 | else | |
3664 | { | |
3665 | /* Copy the argument to general registers or the stack in | |
3666 | register-sized pieces. Large arguments are split between | |
3667 | registers and stack. */ | |
1a69e1e4 DJ |
3668 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3669 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3670 | them in registers where gcc sometimes puts them on the |
3671 | stack. For maximum compatibility, we will put them in | |
3672 | both places. */ | |
1a69e1e4 DJ |
3673 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3674 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3675 | /* Structures should be aligned to eight bytes (even arg registers) |
3676 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3677 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3678 | { |
3679 | if ((argreg & 1)) | |
968b5391 MR |
3680 | { |
3681 | argreg++; | |
1a69e1e4 | 3682 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3683 | } |
46cac009 | 3684 | } |
46cac009 AC |
3685 | while (len > 0) |
3686 | { | |
3687 | /* Remember if the argument was written to the stack. */ | |
3688 | int stack_used_p = 0; | |
1a69e1e4 | 3689 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3690 | |
3691 | if (mips_debug) | |
3692 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3693 | partial_len); | |
3694 | ||
3695 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3696 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3697 | || odd_sized_struct) |
46cac009 AC |
3698 | { |
3699 | /* Should shorter than int integer values be | |
3700 | promoted to int before being stored? */ | |
3701 | int longword_offset = 0; | |
3702 | CORE_ADDR addr; | |
3703 | stack_used_p = 1; | |
46cac009 AC |
3704 | |
3705 | if (mips_debug) | |
3706 | { | |
3707 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3708 | paddr_nz (stack_offset)); | |
3709 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3710 | paddr_nz (longword_offset)); | |
3711 | } | |
3712 | ||
3713 | addr = sp + stack_offset + longword_offset; | |
3714 | ||
3715 | if (mips_debug) | |
3716 | { | |
3717 | int i; | |
6d82d43b | 3718 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3719 | paddr_nz (addr)); |
3720 | for (i = 0; i < partial_len; i++) | |
3721 | { | |
6d82d43b | 3722 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3723 | val[i] & 0xff); |
3724 | } | |
3725 | } | |
3726 | write_memory (addr, val, partial_len); | |
3727 | } | |
3728 | ||
3729 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3730 | structs may go thru BOTH paths. */ |
46cac009 | 3731 | /* Write this portion of the argument to a general |
6d82d43b | 3732 | purpose register. */ |
74ed0bb4 | 3733 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 AC |
3734 | { |
3735 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3736 | /* Value may need to be sign extended, because |
1b13c4f6 | 3737 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3738 | |
3739 | /* A non-floating-point argument being passed in a | |
3740 | general register. If a struct or union, and if | |
3741 | the remaining length is smaller than the register | |
3742 | size, we have to adjust the register value on | |
3743 | big endian targets. | |
3744 | ||
3745 | It does not seem to be necessary to do the | |
3746 | same for integral types. | |
3747 | ||
3748 | Also don't do this adjustment on O64 binaries. | |
3749 | ||
3750 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3751 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3752 | mips_abi_regsize(), generates a left shift |
3753 | as part of storing the argument in a register | |
3754 | (the left shift isn't generated when | |
1b13c4f6 | 3755 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3756 | it is quite possible that this is GCC |
3757 | contradicting the LE/O32 ABI, GDB has not been | |
3758 | adjusted to accommodate this. Either someone | |
3759 | needs to demonstrate that the LE/O32 ABI | |
3760 | specifies such a left shift OR this new ABI gets | |
3761 | identified as such and GDB gets tweaked | |
3762 | accordingly. */ | |
3763 | ||
72a155b4 | 3764 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3765 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3766 | && (typecode == TYPE_CODE_STRUCT |
3767 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3768 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3769 | * TARGET_CHAR_BIT); |
46cac009 AC |
3770 | |
3771 | if (mips_debug) | |
3772 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3773 | argreg, | |
1a69e1e4 | 3774 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3775 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3776 | argreg++; |
3777 | ||
3778 | /* Prevent subsequent floating point arguments from | |
3779 | being passed in floating point registers. */ | |
74ed0bb4 | 3780 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
3781 | } |
3782 | ||
3783 | len -= partial_len; | |
3784 | val += partial_len; | |
3785 | ||
3786 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3787 | will copy the next parameter. |
46cac009 | 3788 | |
6d82d43b AC |
3789 | In older ABIs, the caller reserved space for |
3790 | registers that contained arguments. This was loosely | |
3791 | refered to as their "home". Consequently, space is | |
3792 | always allocated. */ | |
46cac009 | 3793 | |
1a69e1e4 | 3794 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3795 | } |
3796 | } | |
3797 | if (mips_debug) | |
3798 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3799 | } | |
3800 | ||
f10683bb | 3801 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3802 | |
46cac009 AC |
3803 | /* Return adjusted stack pointer. */ |
3804 | return sp; | |
3805 | } | |
3806 | ||
6d82d43b | 3807 | static enum return_value_convention |
c055b101 CV |
3808 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
3809 | struct type *type, struct regcache *regcache, | |
47a35522 | 3810 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3811 | { |
72a155b4 | 3812 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
3813 | |
3814 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3815 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3816 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3817 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3818 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3819 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3820 | { | |
3821 | /* A single-precision floating-point value. It fits in the | |
3822 | least significant part of FP0. */ | |
3823 | if (mips_debug) | |
3824 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3825 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3826 | gdbarch_num_regs (gdbarch) |
3827 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3828 | TYPE_LENGTH (type), |
72a155b4 | 3829 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3830 | readbuf, writebuf, 0); |
6d82d43b AC |
3831 | return RETURN_VALUE_REGISTER_CONVENTION; |
3832 | } | |
3833 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3834 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3835 | { | |
3836 | /* A double-precision floating-point value. The most | |
3837 | significant part goes in FP1, and the least significant in | |
3838 | FP0. */ | |
3839 | if (mips_debug) | |
3840 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 3841 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
3842 | { |
3843 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 3844 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3845 | gdbarch_num_regs (gdbarch) |
3846 | + mips_regnum (gdbarch)->fp0 + | |
3847 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3848 | readbuf, writebuf, 0); |
ba32f989 | 3849 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3850 | gdbarch_num_regs (gdbarch) |
3851 | + mips_regnum (gdbarch)->fp0 + 1, | |
3852 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3853 | readbuf, writebuf, 4); |
6d82d43b AC |
3854 | break; |
3855 | case BFD_ENDIAN_BIG: | |
ba32f989 | 3856 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3857 | gdbarch_num_regs (gdbarch) |
3858 | + mips_regnum (gdbarch)->fp0 + 1, | |
3859 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3860 | readbuf, writebuf, 0); |
ba32f989 | 3861 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3862 | gdbarch_num_regs (gdbarch) |
3863 | + mips_regnum (gdbarch)->fp0 + 0, | |
3864 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3865 | readbuf, writebuf, 4); |
6d82d43b AC |
3866 | break; |
3867 | default: | |
e2e0b3e5 | 3868 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3869 | } |
3870 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3871 | } | |
3872 | #if 0 | |
3873 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3874 | && TYPE_NFIELDS (type) <= 2 | |
3875 | && TYPE_NFIELDS (type) >= 1 | |
3876 | && ((TYPE_NFIELDS (type) == 1 | |
3877 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3878 | == TYPE_CODE_FLT)) | |
3879 | || (TYPE_NFIELDS (type) == 2 | |
3880 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3881 | == TYPE_CODE_FLT) | |
3882 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3883 | == TYPE_CODE_FLT))) | |
3884 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3885 | { | |
3886 | /* A struct that contains one or two floats. Each value is part | |
3887 | in the least significant part of their floating point | |
3888 | register.. */ | |
870cd05e | 3889 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3890 | int regnum; |
3891 | int field; | |
72a155b4 | 3892 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
3893 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3894 | { | |
3895 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3896 | / TARGET_CHAR_BIT); | |
3897 | if (mips_debug) | |
3898 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3899 | offset); | |
ba32f989 DJ |
3900 | mips_xfer_register (gdbarch, regcache, |
3901 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 3902 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 3903 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3904 | readbuf, writebuf, offset); |
6d82d43b AC |
3905 | } |
3906 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3907 | } | |
3908 | #endif | |
3909 | #if 0 | |
3910 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3911 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3912 | { | |
3913 | /* A structure or union. Extract the left justified value, | |
3914 | regardless of the byte order. I.e. DO NOT USE | |
3915 | mips_xfer_lower. */ | |
3916 | int offset; | |
3917 | int regnum; | |
4c7d22cb | 3918 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3919 | offset < TYPE_LENGTH (type); |
72a155b4 | 3920 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3921 | { |
72a155b4 | 3922 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3923 | if (offset + xfer > TYPE_LENGTH (type)) |
3924 | xfer = TYPE_LENGTH (type) - offset; | |
3925 | if (mips_debug) | |
3926 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3927 | offset, xfer, regnum); | |
ba32f989 DJ |
3928 | mips_xfer_register (gdbarch, regcache, |
3929 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
3930 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3931 | } | |
3932 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3933 | } | |
3934 | #endif | |
3935 | else | |
3936 | { | |
3937 | /* A scalar extract each part but least-significant-byte | |
3938 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3939 | the ISA. */ |
6d82d43b AC |
3940 | int offset; |
3941 | int regnum; | |
4c7d22cb | 3942 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3943 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3944 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3945 | { |
1a69e1e4 | 3946 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3947 | if (offset + xfer > TYPE_LENGTH (type)) |
3948 | xfer = TYPE_LENGTH (type) - offset; | |
3949 | if (mips_debug) | |
3950 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3951 | offset, xfer, regnum); | |
ba32f989 DJ |
3952 | mips_xfer_register (gdbarch, regcache, |
3953 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 3954 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3955 | readbuf, writebuf, offset); |
6d82d43b AC |
3956 | } |
3957 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3958 | } | |
3959 | } | |
3960 | ||
3961 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3962 | ABI. */ | |
46cac009 AC |
3963 | |
3964 | static CORE_ADDR | |
7d9b040b | 3965 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3966 | struct regcache *regcache, CORE_ADDR bp_addr, |
3967 | int nargs, | |
3968 | struct value **args, CORE_ADDR sp, | |
3969 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3970 | { |
3971 | int argreg; | |
3972 | int float_argreg; | |
3973 | int argnum; | |
3974 | int len = 0; | |
3975 | int stack_offset = 0; | |
480d3dd2 | 3976 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3977 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3978 | |
25ab4790 AC |
3979 | /* For shared libraries, "t9" needs to point at the function |
3980 | address. */ | |
4c7d22cb | 3981 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3982 | |
3983 | /* Set the return address register to point to the entry point of | |
3984 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3985 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3986 | |
46cac009 AC |
3987 | /* First ensure that the stack and structure return address (if any) |
3988 | are properly aligned. The stack has to be at least 64-bit | |
3989 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3990 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3991 | aligned, so we round to this widest known alignment. */ | |
3992 | ||
5b03f266 AC |
3993 | sp = align_down (sp, 16); |
3994 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3995 | |
3996 | /* Now make space on the stack for the args. */ | |
3997 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3998 | { |
3999 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4000 | int arglen = TYPE_LENGTH (arg_type); | |
4001 | ||
968b5391 | 4002 | /* Allocate space on the stack. */ |
1a69e1e4 | 4003 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4004 | } |
5b03f266 | 4005 | sp -= align_up (len, 16); |
46cac009 AC |
4006 | |
4007 | if (mips_debug) | |
6d82d43b | 4008 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
4009 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
4010 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
4011 | |
4012 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4013 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4014 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4015 | |
4016 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4017 | if (struct_return) | |
4018 | { | |
4019 | if (mips_debug) | |
4020 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4021 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 | 4022 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 4023 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4024 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4025 | } |
4026 | ||
4027 | /* Now load as many as possible of the first arguments into | |
4028 | registers, and push the rest onto the stack. Loop thru args | |
4029 | from first to last. */ | |
4030 | for (argnum = 0; argnum < nargs; argnum++) | |
4031 | { | |
47a35522 | 4032 | const gdb_byte *val; |
46cac009 | 4033 | struct value *arg = args[argnum]; |
4991999e | 4034 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4035 | int len = TYPE_LENGTH (arg_type); |
4036 | enum type_code typecode = TYPE_CODE (arg_type); | |
4037 | ||
4038 | if (mips_debug) | |
4039 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4040 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4041 | argnum + 1, len, (int) typecode); |
4042 | ||
47a35522 | 4043 | val = value_contents (arg); |
ebafbe83 | 4044 | |
ebafbe83 MS |
4045 | /* Floating point arguments passed in registers have to be |
4046 | treated specially. On 32-bit architectures, doubles | |
4047 | are passed in register pairs; the even register gets | |
4048 | the low word, and the odd register gets the high word. | |
4049 | On O32/O64, the first two floating point arguments are | |
4050 | also copied to general registers, because MIPS16 functions | |
4051 | don't use float registers for arguments. This duplication of | |
4052 | arguments in general registers can't hurt non-MIPS16 functions | |
4053 | because those registers are normally skipped. */ | |
4054 | ||
74ed0bb4 MD |
4055 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4056 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4057 | { |
2afd3f0a MR |
4058 | LONGEST regval = extract_unsigned_integer (val, len); |
4059 | if (mips_debug) | |
4060 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4061 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4062 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4063 | if (mips_debug) |
4064 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4065 | argreg, phex (regval, len)); | |
9c9acae0 | 4066 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4067 | argreg++; |
ebafbe83 | 4068 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4069 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4070 | } |
4071 | else | |
4072 | { | |
4073 | /* Copy the argument to general registers or the stack in | |
4074 | register-sized pieces. Large arguments are split between | |
4075 | registers and stack. */ | |
1a69e1e4 | 4076 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4077 | are treated specially: Irix cc passes them in registers |
4078 | where gcc sometimes puts them on the stack. For maximum | |
4079 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4080 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4081 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4082 | while (len > 0) |
4083 | { | |
4084 | /* Remember if the argument was written to the stack. */ | |
4085 | int stack_used_p = 0; | |
1a69e1e4 | 4086 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4087 | |
4088 | if (mips_debug) | |
4089 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4090 | partial_len); | |
4091 | ||
4092 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4093 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4094 | || odd_sized_struct) |
ebafbe83 MS |
4095 | { |
4096 | /* Should shorter than int integer values be | |
4097 | promoted to int before being stored? */ | |
4098 | int longword_offset = 0; | |
4099 | CORE_ADDR addr; | |
4100 | stack_used_p = 1; | |
72a155b4 | 4101 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4102 | { |
1a69e1e4 DJ |
4103 | if ((typecode == TYPE_CODE_INT |
4104 | || typecode == TYPE_CODE_PTR | |
4105 | || typecode == TYPE_CODE_FLT) | |
4106 | && len <= 4) | |
4107 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4108 | } |
4109 | ||
4110 | if (mips_debug) | |
4111 | { | |
4112 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4113 | paddr_nz (stack_offset)); | |
4114 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4115 | paddr_nz (longword_offset)); | |
4116 | } | |
4117 | ||
4118 | addr = sp + stack_offset + longword_offset; | |
4119 | ||
4120 | if (mips_debug) | |
4121 | { | |
4122 | int i; | |
6d82d43b | 4123 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4124 | paddr_nz (addr)); |
4125 | for (i = 0; i < partial_len; i++) | |
4126 | { | |
6d82d43b | 4127 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4128 | val[i] & 0xff); |
4129 | } | |
4130 | } | |
4131 | write_memory (addr, val, partial_len); | |
4132 | } | |
4133 | ||
4134 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4135 | structs may go thru BOTH paths. */ |
ebafbe83 | 4136 | /* Write this portion of the argument to a general |
6d82d43b | 4137 | purpose register. */ |
74ed0bb4 | 4138 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 MS |
4139 | { |
4140 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4141 | /* Value may need to be sign extended, because |
1b13c4f6 | 4142 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4143 | |
4144 | /* A non-floating-point argument being passed in a | |
4145 | general register. If a struct or union, and if | |
4146 | the remaining length is smaller than the register | |
4147 | size, we have to adjust the register value on | |
4148 | big endian targets. | |
4149 | ||
4150 | It does not seem to be necessary to do the | |
401835eb | 4151 | same for integral types. */ |
480d3dd2 | 4152 | |
72a155b4 | 4153 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4154 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4155 | && (typecode == TYPE_CODE_STRUCT |
4156 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4157 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4158 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4159 | |
4160 | if (mips_debug) | |
4161 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4162 | argreg, | |
1a69e1e4 | 4163 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4164 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4165 | argreg++; |
4166 | ||
4167 | /* Prevent subsequent floating point arguments from | |
4168 | being passed in floating point registers. */ | |
74ed0bb4 | 4169 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4170 | } |
4171 | ||
4172 | len -= partial_len; | |
4173 | val += partial_len; | |
4174 | ||
4175 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4176 | will copy the next parameter. |
ebafbe83 | 4177 | |
6d82d43b AC |
4178 | In older ABIs, the caller reserved space for |
4179 | registers that contained arguments. This was loosely | |
4180 | refered to as their "home". Consequently, space is | |
4181 | always allocated. */ | |
ebafbe83 | 4182 | |
1a69e1e4 | 4183 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4184 | } |
4185 | } | |
4186 | if (mips_debug) | |
4187 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4188 | } | |
4189 | ||
f10683bb | 4190 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4191 | |
ebafbe83 MS |
4192 | /* Return adjusted stack pointer. */ |
4193 | return sp; | |
4194 | } | |
4195 | ||
9c8fdbfa | 4196 | static enum return_value_convention |
c055b101 | 4197 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4198 | struct type *type, struct regcache *regcache, |
47a35522 | 4199 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4200 | { |
72a155b4 | 4201 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4202 | |
4203 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4204 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4205 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4206 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4207 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4208 | { |
4209 | /* A floating-point value. It fits in the least significant | |
4210 | part of FP0. */ | |
4211 | if (mips_debug) | |
4212 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4213 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4214 | gdbarch_num_regs (gdbarch) |
4215 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4216 | TYPE_LENGTH (type), |
72a155b4 | 4217 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4218 | readbuf, writebuf, 0); |
7a076fd2 FF |
4219 | return RETURN_VALUE_REGISTER_CONVENTION; |
4220 | } | |
4221 | else | |
4222 | { | |
4223 | /* A scalar extract each part but least-significant-byte | |
4224 | justified. */ | |
4225 | int offset; | |
4226 | int regnum; | |
4227 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4228 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4229 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4230 | { |
1a69e1e4 | 4231 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4232 | if (offset + xfer > TYPE_LENGTH (type)) |
4233 | xfer = TYPE_LENGTH (type) - offset; | |
4234 | if (mips_debug) | |
4235 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4236 | offset, xfer, regnum); | |
ba32f989 DJ |
4237 | mips_xfer_register (gdbarch, regcache, |
4238 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4239 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4240 | readbuf, writebuf, offset); |
7a076fd2 FF |
4241 | } |
4242 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4243 | } | |
6d82d43b AC |
4244 | } |
4245 | ||
dd824b04 DJ |
4246 | /* Floating point register management. |
4247 | ||
4248 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4249 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4250 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4251 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4252 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4253 | double precision floats into two 32-bit chunks and store them in | |
4254 | consecutive fp regs. To display 64-bit floats stored in this | |
4255 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4256 | Throw in user-configurable endianness and you have a real mess. | |
4257 | ||
4258 | The way this works is: | |
4259 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4260 | double-precision value will be split across two logical registers. | |
4261 | The lower-numbered logical register will hold the low-order bits, | |
4262 | regardless of the processor's endianness. | |
4263 | - If we are on a 64-bit processor, and we are looking for a | |
4264 | single-precision value, it will be in the low ordered bits | |
4265 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4266 | save slot in memory. | |
4267 | - If we are in 64-bit mode, everything is straightforward. | |
4268 | ||
4269 | Note that this code only deals with "live" registers at the top of the | |
4270 | stack. We will attempt to deal with saved registers later, when | |
4271 | the raw/cooked register interface is in place. (We need a general | |
4272 | interface that can deal with dynamic saved register sizes -- fp | |
4273 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4274 | and below). */ | |
4275 | ||
67b2c998 DJ |
4276 | static struct type * |
4277 | mips_float_register_type (void) | |
4278 | { | |
8da61cc4 | 4279 | return builtin_type_ieee_single; |
67b2c998 DJ |
4280 | } |
4281 | ||
4282 | static struct type * | |
4283 | mips_double_register_type (void) | |
4284 | { | |
8da61cc4 | 4285 | return builtin_type_ieee_double; |
67b2c998 DJ |
4286 | } |
4287 | ||
dd824b04 DJ |
4288 | /* Copy a 32-bit single-precision value from the current frame |
4289 | into rare_buffer. */ | |
4290 | ||
4291 | static void | |
e11c53d2 | 4292 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4293 | gdb_byte *rare_buffer) |
dd824b04 | 4294 | { |
72a155b4 UW |
4295 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4296 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4297 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4298 | |
e11c53d2 | 4299 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4300 | error (_("can't read register %d (%s)"), |
72a155b4 | 4301 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4302 | if (raw_size == 8) |
4303 | { | |
4304 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4305 | 32 bits. */ |
dd824b04 DJ |
4306 | int offset; |
4307 | ||
72a155b4 | 4308 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4309 | offset = 4; |
4310 | else | |
4311 | offset = 0; | |
4312 | ||
4313 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4314 | } | |
4315 | else | |
4316 | { | |
4317 | memcpy (rare_buffer, raw_buffer, 4); | |
4318 | } | |
4319 | } | |
4320 | ||
4321 | /* Copy a 64-bit double-precision value from the current frame into | |
4322 | rare_buffer. This may include getting half of it from the next | |
4323 | register. */ | |
4324 | ||
4325 | static void | |
e11c53d2 | 4326 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4327 | gdb_byte *rare_buffer) |
dd824b04 | 4328 | { |
72a155b4 UW |
4329 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4330 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4331 | |
9c9acae0 | 4332 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4333 | { |
4334 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4335 | all 64 bits. */ |
e11c53d2 | 4336 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4337 | error (_("can't read register %d (%s)"), |
72a155b4 | 4338 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4339 | } |
4340 | else | |
4341 | { | |
72a155b4 | 4342 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4343 | |
72a155b4 | 4344 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4345 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4346 | _("mips_read_fp_register_double: bad access to " |
4347 | "odd-numbered FP register")); | |
dd824b04 DJ |
4348 | |
4349 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4350 | each register. */ |
72a155b4 | 4351 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4352 | { |
e11c53d2 AC |
4353 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4354 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4355 | } |
361d1df0 | 4356 | else |
dd824b04 | 4357 | { |
e11c53d2 AC |
4358 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4359 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4360 | } |
4361 | } | |
4362 | } | |
4363 | ||
c906108c | 4364 | static void |
e11c53d2 AC |
4365 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4366 | int regnum) | |
c5aa993b | 4367 | { /* do values for FP (float) regs */ |
72a155b4 | 4368 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4369 | gdb_byte *raw_buffer; |
3903d437 AC |
4370 | double doub, flt1; /* doubles extracted from raw hex data */ |
4371 | int inv1, inv2; | |
c5aa993b | 4372 | |
72a155b4 | 4373 | raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)); |
c906108c | 4374 | |
72a155b4 | 4375 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4376 | fprintf_filtered (file, "%*s", |
72a155b4 | 4377 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4378 | ""); |
f0ef6b29 | 4379 | |
72a155b4 | 4380 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4381 | { |
79a45b7d TT |
4382 | struct value_print_options opts; |
4383 | ||
f0ef6b29 KB |
4384 | /* 4-byte registers: Print hex and floating. Also print even |
4385 | numbered registers as doubles. */ | |
e11c53d2 | 4386 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4387 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4388 | |
79a45b7d TT |
4389 | get_formatted_print_options (&opts, 'x'); |
4390 | print_scalar_formatted (raw_buffer, builtin_type_uint32, &opts, 'w', | |
6d82d43b | 4391 | file); |
dd824b04 | 4392 | |
e11c53d2 | 4393 | fprintf_filtered (file, " flt: "); |
1adad886 | 4394 | if (inv1) |
e11c53d2 | 4395 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4396 | else |
e11c53d2 | 4397 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4398 | |
72a155b4 | 4399 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4400 | { |
e11c53d2 | 4401 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4402 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4403 | &inv2); |
1adad886 | 4404 | |
e11c53d2 | 4405 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4406 | if (inv2) |
e11c53d2 | 4407 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4408 | else |
e11c53d2 | 4409 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4410 | } |
c906108c SS |
4411 | } |
4412 | else | |
dd824b04 | 4413 | { |
79a45b7d TT |
4414 | struct value_print_options opts; |
4415 | ||
f0ef6b29 | 4416 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4417 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4418 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4419 | |
e11c53d2 | 4420 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4421 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4422 | ||
79a45b7d TT |
4423 | get_formatted_print_options (&opts, 'x'); |
4424 | print_scalar_formatted (raw_buffer, builtin_type_uint64, &opts, 'g', | |
6d82d43b | 4425 | file); |
f0ef6b29 | 4426 | |
e11c53d2 | 4427 | fprintf_filtered (file, " flt: "); |
1adad886 | 4428 | if (inv1) |
e11c53d2 | 4429 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4430 | else |
e11c53d2 | 4431 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4432 | |
e11c53d2 | 4433 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4434 | if (inv2) |
e11c53d2 | 4435 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4436 | else |
e11c53d2 | 4437 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4438 | } |
4439 | } | |
4440 | ||
4441 | static void | |
e11c53d2 | 4442 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4443 | int regnum) |
f0ef6b29 | 4444 | { |
a4b8ebc8 | 4445 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4446 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4447 | int offset; |
79a45b7d | 4448 | struct value_print_options opts; |
1adad886 | 4449 | |
7b9ee6a8 | 4450 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4451 | { |
e11c53d2 | 4452 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4453 | return; |
4454 | } | |
4455 | ||
4456 | /* Get the data in raw format. */ | |
e11c53d2 | 4457 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4458 | { |
c9f4d572 | 4459 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4460 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4461 | return; |
c906108c | 4462 | } |
f0ef6b29 | 4463 | |
72a155b4 | 4464 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4465 | |
4466 | /* The problem with printing numeric register names (r26, etc.) is that | |
4467 | the user can't use them on input. Probably the best solution is to | |
4468 | fix it so that either the numeric or the funky (a2, etc.) names | |
4469 | are accepted on input. */ | |
4470 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4471 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4472 | else |
e11c53d2 | 4473 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4474 | |
72a155b4 | 4475 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4476 | offset = |
72a155b4 | 4477 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
f0ef6b29 KB |
4478 | else |
4479 | offset = 0; | |
4480 | ||
79a45b7d | 4481 | get_formatted_print_options (&opts, 'x'); |
6d82d43b | 4482 | print_scalar_formatted (raw_buffer + offset, |
79a45b7d | 4483 | register_type (gdbarch, regnum), &opts, 0, |
6d82d43b | 4484 | file); |
c906108c SS |
4485 | } |
4486 | ||
f0ef6b29 KB |
4487 | /* Replacement for generic do_registers_info. |
4488 | Print regs in pretty columns. */ | |
4489 | ||
4490 | static int | |
e11c53d2 AC |
4491 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4492 | int regnum) | |
f0ef6b29 | 4493 | { |
e11c53d2 AC |
4494 | fprintf_filtered (file, " "); |
4495 | mips_print_fp_register (file, frame, regnum); | |
4496 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4497 | return regnum + 1; |
4498 | } | |
4499 | ||
4500 | ||
c906108c SS |
4501 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4502 | ||
4503 | static int | |
e11c53d2 | 4504 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4505 | int start_regnum) |
c906108c | 4506 | { |
a4b8ebc8 | 4507 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4508 | /* do values for GP (int) regs */ |
47a35522 | 4509 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4510 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4511 | int col, byte; |
a4b8ebc8 | 4512 | int regnum; |
c906108c SS |
4513 | |
4514 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4515 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4516 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4517 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4518 | regnum++) |
c906108c | 4519 | { |
72a155b4 | 4520 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4521 | continue; /* unused register */ |
7b9ee6a8 | 4522 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4523 | TYPE_CODE_FLT) |
c5aa993b | 4524 | break; /* end the row: reached FP register */ |
0cc93a06 | 4525 | /* Large registers are handled separately. */ |
72a155b4 | 4526 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4527 | { |
4528 | if (col > 0) | |
4529 | break; /* End the row before this register. */ | |
4530 | ||
4531 | /* Print this register on a row by itself. */ | |
4532 | mips_print_register (file, frame, regnum); | |
4533 | fprintf_filtered (file, "\n"); | |
4534 | return regnum + 1; | |
4535 | } | |
d05f6826 DJ |
4536 | if (col == 0) |
4537 | fprintf_filtered (file, " "); | |
6d82d43b | 4538 | fprintf_filtered (file, |
72a155b4 UW |
4539 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4540 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4541 | col++; |
4542 | } | |
d05f6826 DJ |
4543 | |
4544 | if (col == 0) | |
4545 | return regnum; | |
4546 | ||
a4b8ebc8 | 4547 | /* print the R0 to R31 names */ |
72a155b4 | 4548 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4549 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4550 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4551 | else |
4552 | fprintf_filtered (file, "\n "); | |
c906108c | 4553 | |
c906108c | 4554 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4555 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4556 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4557 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4558 | regnum++) |
c906108c | 4559 | { |
72a155b4 | 4560 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4561 | continue; /* unused register */ |
7b9ee6a8 | 4562 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4563 | TYPE_CODE_FLT) |
c5aa993b | 4564 | break; /* end row: reached FP register */ |
72a155b4 | 4565 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4566 | break; /* End row: large register. */ |
4567 | ||
c906108c | 4568 | /* OK: get the data in raw format. */ |
e11c53d2 | 4569 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4570 | error (_("can't read register %d (%s)"), |
72a155b4 | 4571 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4572 | /* pad small registers */ |
4246e332 | 4573 | for (byte = 0; |
72a155b4 UW |
4574 | byte < (mips_abi_regsize (gdbarch) |
4575 | - register_size (gdbarch, regnum)); byte++) | |
c906108c SS |
4576 | printf_filtered (" "); |
4577 | /* Now print the register value in hex, endian order. */ | |
72a155b4 | 4578 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4579 | for (byte = |
72a155b4 UW |
4580 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4581 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4582 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4583 | else |
72a155b4 | 4584 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4585 | byte >= 0; byte--) |
47a35522 | 4586 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4587 | fprintf_filtered (file, " "); |
c906108c SS |
4588 | col++; |
4589 | } | |
c5aa993b | 4590 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4591 | fprintf_filtered (file, "\n"); |
c906108c SS |
4592 | |
4593 | return regnum; | |
4594 | } | |
4595 | ||
4596 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4597 | ||
bf1f5b4c | 4598 | static void |
e11c53d2 AC |
4599 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4600 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4601 | { |
c5aa993b | 4602 | if (regnum != -1) /* do one specified register */ |
c906108c | 4603 | { |
72a155b4 UW |
4604 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4605 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4606 | error (_("Not a valid register for the current processor type")); |
c906108c | 4607 | |
0cc93a06 | 4608 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4609 | fprintf_filtered (file, "\n"); |
c906108c | 4610 | } |
c5aa993b JM |
4611 | else |
4612 | /* do all (or most) registers */ | |
c906108c | 4613 | { |
72a155b4 UW |
4614 | regnum = gdbarch_num_regs (gdbarch); |
4615 | while (regnum < gdbarch_num_regs (gdbarch) | |
4616 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4617 | { |
7b9ee6a8 | 4618 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4619 | TYPE_CODE_FLT) |
e11c53d2 AC |
4620 | { |
4621 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4622 | regnum = print_fp_register_row (file, frame, regnum); | |
4623 | else | |
4624 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4625 | } | |
c906108c | 4626 | else |
e11c53d2 | 4627 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4628 | } |
4629 | } | |
4630 | } | |
4631 | ||
c906108c SS |
4632 | /* Is this a branch with a delay slot? */ |
4633 | ||
c906108c | 4634 | static int |
acdb74a0 | 4635 | is_delayed (unsigned long insn) |
c906108c SS |
4636 | { |
4637 | int i; | |
4638 | for (i = 0; i < NUMOPCODES; ++i) | |
4639 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4640 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4641 | break; | |
4642 | return (i < NUMOPCODES | |
4643 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4644 | | INSN_COND_BRANCH_DELAY | |
4645 | | INSN_COND_BRANCH_LIKELY))); | |
4646 | } | |
4647 | ||
63807e1d | 4648 | static int |
3352ef37 AC |
4649 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4650 | struct frame_info *frame) | |
c906108c | 4651 | { |
3352ef37 | 4652 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4653 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4654 | |
4655 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4656 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4657 | return 0; |
4658 | ||
06648491 MK |
4659 | if (!breakpoint_here_p (pc + 4)) |
4660 | return 0; | |
4661 | ||
3352ef37 AC |
4662 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4663 | /* If error reading memory, guess that it is not a delayed | |
4664 | branch. */ | |
c906108c | 4665 | return 0; |
4c7d22cb | 4666 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4667 | } |
4668 | ||
6d82d43b AC |
4669 | /* To skip prologues, I use this predicate. Returns either PC itself |
4670 | if the code at PC does not look like a function prologue; otherwise | |
4671 | returns an address that (if we're lucky) follows the prologue. If | |
4672 | LENIENT, then we must skip everything which is involved in setting | |
4673 | up the frame (it's OK to skip more, just so long as we don't skip | |
4674 | anything which might clobber the registers which are being saved. | |
4675 | We must skip more in the case where part of the prologue is in the | |
4676 | delay slot of a non-prologue instruction). */ | |
4677 | ||
4678 | static CORE_ADDR | |
6093d2eb | 4679 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4680 | { |
8b622e6a AC |
4681 | CORE_ADDR limit_pc; |
4682 | CORE_ADDR func_addr; | |
4683 | ||
6d82d43b AC |
4684 | /* See if we can determine the end of the prologue via the symbol table. |
4685 | If so, then return either PC, or the PC after the prologue, whichever | |
4686 | is greater. */ | |
8b622e6a AC |
4687 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4688 | { | |
4689 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4690 | if (post_prologue_pc != 0) | |
4691 | return max (pc, post_prologue_pc); | |
4692 | } | |
6d82d43b AC |
4693 | |
4694 | /* Can't determine prologue from the symbol table, need to examine | |
4695 | instructions. */ | |
4696 | ||
98b4dd94 JB |
4697 | /* Find an upper limit on the function prologue using the debug |
4698 | information. If the debug information could not be used to provide | |
4699 | that bound, then use an arbitrary large number as the upper bound. */ | |
4700 | limit_pc = skip_prologue_using_sal (pc); | |
4701 | if (limit_pc == 0) | |
4702 | limit_pc = pc + 100; /* Magic. */ | |
4703 | ||
0fe7e7c8 | 4704 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4705 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4706 | else |
a65bbe44 | 4707 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4708 | } |
4709 | ||
97ab0fdd MR |
4710 | /* Check whether the PC is in a function epilogue (32-bit version). |
4711 | This is a helper function for mips_in_function_epilogue_p. */ | |
4712 | static int | |
4713 | mips32_in_function_epilogue_p (CORE_ADDR pc) | |
4714 | { | |
4715 | CORE_ADDR func_addr = 0, func_end = 0; | |
4716 | ||
4717 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4718 | { | |
4719 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4720 | CORE_ADDR addr = func_end - 12; | |
4721 | ||
4722 | if (addr < func_addr + 4) | |
4723 | addr = func_addr + 4; | |
4724 | if (pc < addr) | |
4725 | return 0; | |
4726 | ||
4727 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4728 | { | |
4729 | unsigned long high_word; | |
4730 | unsigned long inst; | |
4731 | ||
4732 | inst = mips_fetch_instruction (pc); | |
4733 | high_word = (inst >> 16) & 0xffff; | |
4734 | ||
4735 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4736 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4737 | && inst != 0x03e00008 /* jr $ra */ | |
4738 | && inst != 0x00000000) /* nop */ | |
4739 | return 0; | |
4740 | } | |
4741 | ||
4742 | return 1; | |
4743 | } | |
4744 | ||
4745 | return 0; | |
4746 | } | |
4747 | ||
4748 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4749 | This is a helper function for mips_in_function_epilogue_p. */ | |
4750 | static int | |
4751 | mips16_in_function_epilogue_p (CORE_ADDR pc) | |
4752 | { | |
4753 | CORE_ADDR func_addr = 0, func_end = 0; | |
4754 | ||
4755 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4756 | { | |
4757 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4758 | CORE_ADDR addr = func_end - 12; | |
4759 | ||
4760 | if (addr < func_addr + 4) | |
4761 | addr = func_addr + 4; | |
4762 | if (pc < addr) | |
4763 | return 0; | |
4764 | ||
4765 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4766 | { | |
4767 | unsigned short inst; | |
4768 | ||
4769 | inst = mips_fetch_instruction (pc); | |
4770 | ||
4771 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4772 | continue; | |
4773 | ||
4774 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4775 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4776 | && inst != 0xe820 /* jr $ra */ | |
4777 | && inst != 0xe8a0 /* jrc $ra */ | |
4778 | && inst != 0x6500) /* nop */ | |
4779 | return 0; | |
4780 | } | |
4781 | ||
4782 | return 1; | |
4783 | } | |
4784 | ||
4785 | return 0; | |
4786 | } | |
4787 | ||
4788 | /* The epilogue is defined here as the area at the end of a function, | |
4789 | after an instruction which destroys the function's stack frame. */ | |
4790 | static int | |
4791 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4792 | { | |
4793 | if (mips_pc_is_mips16 (pc)) | |
4794 | return mips16_in_function_epilogue_p (pc); | |
4795 | else | |
4796 | return mips32_in_function_epilogue_p (pc); | |
4797 | } | |
4798 | ||
a5ea2558 AC |
4799 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4800 | used for all MIPS-specific commands. */ | |
4801 | ||
a5ea2558 | 4802 | static void |
acdb74a0 | 4803 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4804 | { |
4805 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4806 | } | |
4807 | ||
a5ea2558 | 4808 | static void |
acdb74a0 | 4809 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4810 | { |
6d82d43b AC |
4811 | printf_unfiltered |
4812 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4813 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4814 | } | |
4815 | ||
c906108c SS |
4816 | /* Commands to show/set the MIPS FPU type. */ |
4817 | ||
c906108c | 4818 | static void |
acdb74a0 | 4819 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4820 | { |
c906108c | 4821 | char *fpu; |
6ca0852e | 4822 | |
1cf3db46 | 4823 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
4824 | { |
4825 | printf_unfiltered | |
4826 | ("The MIPS floating-point coprocessor is unknown " | |
4827 | "because the current architecture is not MIPS.\n"); | |
4828 | return; | |
4829 | } | |
4830 | ||
1cf3db46 | 4831 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
4832 | { |
4833 | case MIPS_FPU_SINGLE: | |
4834 | fpu = "single-precision"; | |
4835 | break; | |
4836 | case MIPS_FPU_DOUBLE: | |
4837 | fpu = "double-precision"; | |
4838 | break; | |
4839 | case MIPS_FPU_NONE: | |
4840 | fpu = "absent (none)"; | |
4841 | break; | |
93d56215 | 4842 | default: |
e2e0b3e5 | 4843 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4844 | } |
4845 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4846 | printf_unfiltered |
4847 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4848 | fpu); | |
c906108c | 4849 | else |
6d82d43b AC |
4850 | printf_unfiltered |
4851 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4852 | } |
4853 | ||
4854 | ||
c906108c | 4855 | static void |
acdb74a0 | 4856 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4857 | { |
6d82d43b AC |
4858 | printf_unfiltered |
4859 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4860 | show_mipsfpu_command (args, from_tty); |
4861 | } | |
4862 | ||
c906108c | 4863 | static void |
acdb74a0 | 4864 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4865 | { |
8d5838b5 AC |
4866 | struct gdbarch_info info; |
4867 | gdbarch_info_init (&info); | |
c906108c SS |
4868 | mips_fpu_type = MIPS_FPU_SINGLE; |
4869 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4870 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4871 | instead of relying on globals. Doing that would let generic code | |
4872 | handle the search for this specific architecture. */ | |
4873 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4874 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4875 | } |
4876 | ||
c906108c | 4877 | static void |
acdb74a0 | 4878 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4879 | { |
8d5838b5 AC |
4880 | struct gdbarch_info info; |
4881 | gdbarch_info_init (&info); | |
c906108c SS |
4882 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4883 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4884 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4885 | instead of relying on globals. Doing that would let generic code | |
4886 | handle the search for this specific architecture. */ | |
4887 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4888 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4889 | } |
4890 | ||
c906108c | 4891 | static void |
acdb74a0 | 4892 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4893 | { |
8d5838b5 AC |
4894 | struct gdbarch_info info; |
4895 | gdbarch_info_init (&info); | |
c906108c SS |
4896 | mips_fpu_type = MIPS_FPU_NONE; |
4897 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4898 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4899 | instead of relying on globals. Doing that would let generic code | |
4900 | handle the search for this specific architecture. */ | |
4901 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4902 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4903 | } |
4904 | ||
c906108c | 4905 | static void |
acdb74a0 | 4906 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4907 | { |
4908 | mips_fpu_type_auto = 1; | |
4909 | } | |
4910 | ||
c906108c | 4911 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4912 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4913 | the relevant processor still exists (it dates back to '94) and | |
4914 | secondly this is not the way to do this. The processor type should | |
4915 | be set by forcing an architecture change. */ | |
c906108c | 4916 | |
691c0433 AC |
4917 | void |
4918 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4919 | { |
bb486190 UW |
4920 | struct regcache *regcache = get_current_regcache (); |
4921 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
4922 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 4923 | ULONGEST prid; |
c906108c | 4924 | |
bb486190 | 4925 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 4926 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4927 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4928 | } |
4929 | ||
4930 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4931 | callable as an sfunc. */ | |
4932 | ||
4933 | static void | |
acdb74a0 AC |
4934 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4935 | struct cmd_list_element *c) | |
c906108c SS |
4936 | { |
4937 | reinit_frame_cache (); | |
4938 | } | |
4939 | ||
a89aa300 AC |
4940 | static int |
4941 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4942 | { |
d31431ed AC |
4943 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4944 | disassembler needs to be able to locally determine the ISA, and | |
4945 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4946 | work. */ | |
ec4045ea AC |
4947 | if (mips_pc_is_mips16 (memaddr)) |
4948 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4949 | |
4950 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4951 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4952 | |
e5ab0dce | 4953 | /* Set the disassembler options. */ |
9dae60cc | 4954 | if (!info->disassembler_options) |
e5ab0dce AC |
4955 | /* This string is not recognized explicitly by the disassembler, |
4956 | but it tells the disassembler to not try to guess the ABI from | |
4957 | the bfd elf headers, such that, if the user overrides the ABI | |
4958 | of a program linked as NewABI, the disassembly will follow the | |
4959 | register naming conventions specified by the user. */ | |
4960 | info->disassembler_options = "gpr-names=32"; | |
4961 | ||
c906108c | 4962 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 4963 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
4964 | return print_insn_big_mips (memaddr, info); |
4965 | else | |
4966 | return print_insn_little_mips (memaddr, info); | |
4967 | } | |
4968 | ||
9dae60cc UW |
4969 | static int |
4970 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
4971 | { | |
4972 | /* Set up the disassembler info, so that we get the right | |
4973 | register names from libopcodes. */ | |
4974 | info->disassembler_options = "gpr-names=n32"; | |
4975 | info->flavour = bfd_target_elf_flavour; | |
4976 | ||
4977 | return gdb_print_insn_mips (memaddr, info); | |
4978 | } | |
4979 | ||
4980 | static int | |
4981 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
4982 | { | |
4983 | /* Set up the disassembler info, so that we get the right | |
4984 | register names from libopcodes. */ | |
4985 | info->disassembler_options = "gpr-names=64"; | |
4986 | info->flavour = bfd_target_elf_flavour; | |
4987 | ||
4988 | return gdb_print_insn_mips (memaddr, info); | |
4989 | } | |
4990 | ||
3b3b875c UW |
4991 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4992 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4993 | It returns a pointer to a string of bytes that encode a breakpoint | |
4994 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4995 | necessary) to point to the actual memory location where the breakpoint | |
4996 | should be inserted. */ | |
c906108c | 4997 | |
47a35522 | 4998 | static const gdb_byte * |
67d57894 | 4999 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5000 | { |
67d57894 | 5001 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5002 | { |
0fe7e7c8 | 5003 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5004 | { |
47a35522 | 5005 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5006 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5007 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5008 | return mips16_big_breakpoint; |
5009 | } | |
5010 | else | |
5011 | { | |
aaab4dba AC |
5012 | /* The IDT board uses an unusual breakpoint value, and |
5013 | sometimes gets confused when it sees the usual MIPS | |
5014 | breakpoint instruction. */ | |
47a35522 MK |
5015 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5016 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5017 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5018 | |
c5aa993b | 5019 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5020 | |
5021 | if (strcmp (target_shortname, "mips") == 0) | |
5022 | return idt_big_breakpoint; | |
5023 | else if (strcmp (target_shortname, "ddb") == 0 | |
5024 | || strcmp (target_shortname, "pmon") == 0 | |
5025 | || strcmp (target_shortname, "lsi") == 0) | |
5026 | return pmon_big_breakpoint; | |
5027 | else | |
5028 | return big_breakpoint; | |
5029 | } | |
5030 | } | |
5031 | else | |
5032 | { | |
0fe7e7c8 | 5033 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5034 | { |
47a35522 | 5035 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5036 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5037 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5038 | return mips16_little_breakpoint; |
5039 | } | |
5040 | else | |
5041 | { | |
47a35522 MK |
5042 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5043 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5044 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5045 | |
c5aa993b | 5046 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5047 | |
5048 | if (strcmp (target_shortname, "mips") == 0) | |
5049 | return idt_little_breakpoint; | |
5050 | else if (strcmp (target_shortname, "ddb") == 0 | |
5051 | || strcmp (target_shortname, "pmon") == 0 | |
5052 | || strcmp (target_shortname, "lsi") == 0) | |
5053 | return pmon_little_breakpoint; | |
5054 | else | |
5055 | return little_breakpoint; | |
5056 | } | |
5057 | } | |
5058 | } | |
5059 | ||
5060 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5061 | PC, which is either the callee or the caller. There are several | |
5062 | cases which must be handled: | |
5063 | ||
5064 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5065 | target PC is in $31 ($ra). |
c906108c | 5066 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5067 | and the target PC is in $2. |
c906108c | 5068 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5069 | before the jal instruction, this is effectively a call stub |
5070 | and the the target PC is in $2. Otherwise this is effectively | |
5071 | a return stub and the target PC is in $18. | |
c906108c SS |
5072 | |
5073 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5074 | gory details. */ |
c906108c | 5075 | |
757a7cc6 | 5076 | static CORE_ADDR |
db5f024e | 5077 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c SS |
5078 | { |
5079 | char *name; | |
5080 | CORE_ADDR start_addr; | |
5081 | ||
5082 | /* Find the starting address and name of the function containing the PC. */ | |
5083 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5084 | return 0; | |
5085 | ||
5086 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5087 | target PC is in $31 ($ra). */ | |
5088 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5089 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5090 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5091 | |
5092 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5093 | { | |
5094 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5095 | and the target PC is in $2. */ | |
5096 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5097 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5098 | |
5099 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5100 | before the jal instruction, this is effectively a call stub |
5101 | and the the target PC is in $2. Otherwise this is effectively | |
5102 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5103 | else if (name[19] == 's' || name[19] == 'd') |
5104 | { | |
5105 | if (pc == start_addr) | |
5106 | { | |
5107 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5108 | stub. Such a stub for a function bar might have a name |
5109 | like __fn_stub_bar, and might look like this: | |
5110 | mfc1 $4,$f13 | |
5111 | mfc1 $5,$f12 | |
5112 | mfc1 $6,$f15 | |
5113 | mfc1 $7,$f14 | |
5114 | la $1,bar (becomes a lui/addiu pair) | |
5115 | jr $1 | |
5116 | So scan down to the lui/addi and extract the target | |
5117 | address from those two instructions. */ | |
c906108c | 5118 | |
52f729a7 | 5119 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 5120 | ULONGEST inst; |
c906108c SS |
5121 | int i; |
5122 | ||
5123 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5124 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5125 | 0) | |
c906108c SS |
5126 | return target_pc; |
5127 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5128 | && strcmp (name, "etext") != 0 | |
5129 | && strcmp (name, "_etext") != 0) | |
5130 | return target_pc; | |
5131 | ||
5132 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5133 | The limit on the search is arbitrarily set to 20 |
5134 | instructions. FIXME. */ | |
95ac2dcf | 5135 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5136 | { |
c5aa993b JM |
5137 | inst = mips_fetch_instruction (target_pc); |
5138 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5139 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5140 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5141 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5142 | } |
5143 | ||
5144 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5145 | return target_pc; | |
5146 | } | |
5147 | else | |
5148 | /* This is the 'return' part of a call stub. The return | |
5149 | address is in $r18. */ | |
52f729a7 | 5150 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5151 | } |
5152 | } | |
c5aa993b | 5153 | return 0; /* not a stub */ |
c906108c SS |
5154 | } |
5155 | ||
db5f024e DJ |
5156 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5157 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5158 | so that $t9 has the correct value at function entry. */ | |
5159 | ||
5160 | static CORE_ADDR | |
5161 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5162 | { | |
5163 | struct minimal_symbol *msym; | |
5164 | int i; | |
5165 | gdb_byte stub_code[16]; | |
5166 | int32_t stub_words[4]; | |
5167 | ||
5168 | /* The stub for foo is named ".pic.foo", and is either two | |
5169 | instructions inserted before foo or a three instruction sequence | |
5170 | which jumps to foo. */ | |
5171 | msym = lookup_minimal_symbol_by_pc (pc); | |
5172 | if (msym == NULL | |
5173 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5174 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5175 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5176 | return 0; | |
5177 | ||
5178 | /* A two-instruction header. */ | |
5179 | if (MSYMBOL_SIZE (msym) == 8) | |
5180 | return pc + 8; | |
5181 | ||
5182 | /* A three-instruction (plus delay slot) trampoline. */ | |
5183 | if (MSYMBOL_SIZE (msym) == 16) | |
5184 | { | |
5185 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5186 | return 0; | |
5187 | for (i = 0; i < 4; i++) | |
5188 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, 4); | |
5189 | ||
5190 | /* A stub contains these instructions: | |
5191 | lui t9, %hi(target) | |
5192 | j target | |
5193 | addiu t9, t9, %lo(target) | |
5194 | nop | |
5195 | ||
5196 | This works even for N64, since stubs are only generated with | |
5197 | -msym32. */ | |
5198 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5199 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5200 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5201 | && stub_words[3] == 0x00000000) | |
5202 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5203 | + (stub_words[2] & 0x0000ffff)); | |
5204 | } | |
5205 | ||
5206 | /* Not a recognized stub. */ | |
5207 | return 0; | |
5208 | } | |
5209 | ||
5210 | static CORE_ADDR | |
5211 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5212 | { | |
5213 | CORE_ADDR target_pc; | |
5214 | ||
5215 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5216 | if (target_pc) | |
5217 | return target_pc; | |
5218 | ||
5219 | target_pc = find_solib_trampoline_target (frame, pc); | |
5220 | if (target_pc) | |
5221 | return target_pc; | |
5222 | ||
5223 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5224 | if (target_pc) | |
5225 | return target_pc; | |
5226 | ||
5227 | return 0; | |
5228 | } | |
5229 | ||
a4b8ebc8 | 5230 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5231 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5232 | |
5233 | static int | |
d3f73121 | 5234 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5235 | { |
a4b8ebc8 | 5236 | int regnum; |
2f38ef89 | 5237 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5238 | regnum = num; |
2f38ef89 | 5239 | else if (num >= 38 && num < 70) |
d3f73121 | 5240 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5241 | else if (num == 70) |
d3f73121 | 5242 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5243 | else if (num == 71) |
d3f73121 | 5244 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5245 | else |
a4b8ebc8 AC |
5246 | /* This will hopefully (eventually) provoke a warning. Should |
5247 | we be calling complaint() here? */ | |
d3f73121 MD |
5248 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5249 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5250 | } |
5251 | ||
2f38ef89 | 5252 | |
a4b8ebc8 | 5253 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5254 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5255 | |
5256 | static int | |
d3f73121 | 5257 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5258 | { |
a4b8ebc8 | 5259 | int regnum; |
2f38ef89 | 5260 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5261 | regnum = num; |
2f38ef89 | 5262 | else if (num >= 32 && num < 64) |
d3f73121 | 5263 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5264 | else if (num == 64) |
d3f73121 | 5265 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5266 | else if (num == 65) |
d3f73121 | 5267 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5268 | else |
a4b8ebc8 AC |
5269 | /* This will hopefully (eventually) provoke a warning. Should we |
5270 | be calling complaint() here? */ | |
d3f73121 MD |
5271 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5272 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5273 | } |
5274 | ||
5275 | static int | |
e7faf938 | 5276 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5277 | { |
5278 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5279 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5280 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5281 | decide if it is valid. Should instead define a standard sim/gdb | |
5282 | register numbering scheme. */ | |
e7faf938 MD |
5283 | if (gdbarch_register_name (gdbarch, |
5284 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5285 | && gdbarch_register_name (gdbarch, | |
5286 | gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5287 | return regnum; |
5288 | else | |
6d82d43b | 5289 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5290 | } |
5291 | ||
2f38ef89 | 5292 | |
4844f454 CV |
5293 | /* Convert an integer into an address. Extracting the value signed |
5294 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5295 | |
5296 | static CORE_ADDR | |
79dd2d24 | 5297 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5298 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5299 | { |
4844f454 | 5300 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
5301 | } |
5302 | ||
82e91389 DJ |
5303 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5304 | than most other architectures; we just need to be explicit about it, | |
5305 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5306 | an assertion failure. */ | |
5307 | ||
5308 | static void | |
a54fba4c MD |
5309 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5310 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5311 | { |
5312 | *reg = MIPS_SP_REGNUM; | |
5313 | *offset = 0; | |
5314 | } | |
5315 | ||
caaa3122 DJ |
5316 | static void |
5317 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5318 | { | |
5319 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5320 | const char *name = bfd_get_section_name (abfd, sect); | |
5321 | ||
5322 | if (*abip != MIPS_ABI_UNKNOWN) | |
5323 | return; | |
5324 | ||
5325 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5326 | return; | |
5327 | ||
5328 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5329 | *abip = MIPS_ABI_O32; | |
5330 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5331 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5332 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5333 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5334 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5335 | *abip = MIPS_ABI_O64; | |
5336 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5337 | *abip = MIPS_ABI_EABI32; | |
5338 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5339 | *abip = MIPS_ABI_EABI64; | |
5340 | else | |
8a3fe4f8 | 5341 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5342 | } |
5343 | ||
22e47e37 FF |
5344 | static void |
5345 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5346 | { | |
5347 | int *lbp = (int *) obj; | |
5348 | const char *name = bfd_get_section_name (abfd, sect); | |
5349 | ||
5350 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5351 | *lbp = 32; | |
5352 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5353 | *lbp = 64; | |
5354 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5355 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5356 | } | |
5357 | ||
2e4ebe70 DJ |
5358 | static enum mips_abi |
5359 | global_mips_abi (void) | |
5360 | { | |
5361 | int i; | |
5362 | ||
5363 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5364 | if (mips_abi_strings[i] == mips_abi_string) | |
5365 | return (enum mips_abi) i; | |
5366 | ||
e2e0b3e5 | 5367 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5368 | } |
5369 | ||
29709017 DJ |
5370 | static void |
5371 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5372 | { | |
29709017 DJ |
5373 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5374 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5375 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5376 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5377 | |
5378 | /* If the size matches the full set of registers GDB traditionally | |
5379 | knows about, including floating point, for either 32-bit or | |
5380 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5381 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5382 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5383 | |
5384 | /* Otherwise we don't have a useful guess. */ | |
5385 | } | |
5386 | ||
f8b73d13 DJ |
5387 | static struct value * |
5388 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5389 | { | |
5390 | const int *reg_p = baton; | |
5391 | return value_of_register (*reg_p, frame); | |
5392 | } | |
5393 | ||
c2d11a7d | 5394 | static struct gdbarch * |
6d82d43b | 5395 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5396 | { |
c2d11a7d JM |
5397 | struct gdbarch *gdbarch; |
5398 | struct gdbarch_tdep *tdep; | |
5399 | int elf_flags; | |
2e4ebe70 | 5400 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5401 | int i, num_regs; |
8d5838b5 | 5402 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5403 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5404 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5405 | |
5406 | /* Check any target description for validity. */ | |
5407 | if (tdesc_has_registers (info.target_desc)) | |
5408 | { | |
5409 | static const char *const mips_gprs[] = { | |
5410 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5411 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5412 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5413 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5414 | }; | |
5415 | static const char *const mips_fprs[] = { | |
5416 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5417 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5418 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5419 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5420 | }; | |
5421 | ||
5422 | const struct tdesc_feature *feature; | |
5423 | int valid_p; | |
5424 | ||
5425 | feature = tdesc_find_feature (info.target_desc, | |
5426 | "org.gnu.gdb.mips.cpu"); | |
5427 | if (feature == NULL) | |
5428 | return NULL; | |
5429 | ||
5430 | tdesc_data = tdesc_data_alloc (); | |
5431 | ||
5432 | valid_p = 1; | |
5433 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5434 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5435 | mips_gprs[i]); | |
5436 | ||
5437 | ||
5438 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5439 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5440 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5441 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5442 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5443 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5444 | ||
5445 | if (!valid_p) | |
5446 | { | |
5447 | tdesc_data_cleanup (tdesc_data); | |
5448 | return NULL; | |
5449 | } | |
5450 | ||
5451 | feature = tdesc_find_feature (info.target_desc, | |
5452 | "org.gnu.gdb.mips.cp0"); | |
5453 | if (feature == NULL) | |
5454 | { | |
5455 | tdesc_data_cleanup (tdesc_data); | |
5456 | return NULL; | |
5457 | } | |
5458 | ||
5459 | valid_p = 1; | |
5460 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5461 | MIPS_EMBED_BADVADDR_REGNUM, | |
5462 | "badvaddr"); | |
5463 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5464 | MIPS_PS_REGNUM, "status"); | |
5465 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5466 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5467 | ||
5468 | if (!valid_p) | |
5469 | { | |
5470 | tdesc_data_cleanup (tdesc_data); | |
5471 | return NULL; | |
5472 | } | |
5473 | ||
5474 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5475 | backend is not prepared for that, though. */ | |
5476 | feature = tdesc_find_feature (info.target_desc, | |
5477 | "org.gnu.gdb.mips.fpu"); | |
5478 | if (feature == NULL) | |
5479 | { | |
5480 | tdesc_data_cleanup (tdesc_data); | |
5481 | return NULL; | |
5482 | } | |
5483 | ||
5484 | valid_p = 1; | |
5485 | for (i = 0; i < 32; i++) | |
5486 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5487 | i + MIPS_EMBED_FP0_REGNUM, | |
5488 | mips_fprs[i]); | |
5489 | ||
5490 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5491 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5492 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5493 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5494 | ||
5495 | if (!valid_p) | |
5496 | { | |
5497 | tdesc_data_cleanup (tdesc_data); | |
5498 | return NULL; | |
5499 | } | |
5500 | ||
5501 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5502 | when only 32-bit registers are provided. */ | |
5503 | } | |
c2d11a7d | 5504 | |
ec03c1ac AC |
5505 | /* First of all, extract the elf_flags, if available. */ |
5506 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5507 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5508 | else if (arches != NULL) |
5509 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5510 | else |
5511 | elf_flags = 0; | |
5512 | if (gdbarch_debug) | |
5513 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5514 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5515 | |
102182a9 | 5516 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5517 | switch ((elf_flags & EF_MIPS_ABI)) |
5518 | { | |
5519 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5520 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5521 | break; |
5522 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5523 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5524 | break; |
5525 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5526 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5527 | break; |
5528 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5529 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5530 | break; |
5531 | default: | |
acdb74a0 | 5532 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5533 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5534 | else |
ec03c1ac | 5535 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5536 | break; |
5537 | } | |
acdb74a0 | 5538 | |
caaa3122 | 5539 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5540 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5541 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5542 | |
dc305454 | 5543 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5544 | MIPS architecture (if there is one). */ |
5545 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5546 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5547 | |
32a6503c | 5548 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5549 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5550 | && info.bfd_arch_info != NULL |
5551 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5552 | { | |
5553 | switch (info.bfd_arch_info->mach) | |
5554 | { | |
5555 | case bfd_mach_mips3900: | |
ec03c1ac | 5556 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5557 | break; |
5558 | case bfd_mach_mips4100: | |
5559 | case bfd_mach_mips5000: | |
ec03c1ac | 5560 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5561 | break; |
1d06468c EZ |
5562 | case bfd_mach_mips8000: |
5563 | case bfd_mach_mips10000: | |
32a6503c KB |
5564 | /* On Irix, ELF64 executables use the N64 ABI. The |
5565 | pseudo-sections which describe the ABI aren't present | |
5566 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5567 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5568 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5569 | found_abi = MIPS_ABI_N64; |
28d169de | 5570 | else |
ec03c1ac | 5571 | found_abi = MIPS_ABI_N32; |
1d06468c | 5572 | break; |
bf64bfd6 AC |
5573 | } |
5574 | } | |
2e4ebe70 | 5575 | |
26c53e50 DJ |
5576 | /* Default 64-bit objects to N64 instead of O32. */ |
5577 | if (found_abi == MIPS_ABI_UNKNOWN | |
5578 | && info.abfd != NULL | |
5579 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5580 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5581 | found_abi = MIPS_ABI_N64; | |
5582 | ||
ec03c1ac AC |
5583 | if (gdbarch_debug) |
5584 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5585 | found_abi); | |
5586 | ||
5587 | /* What has the user specified from the command line? */ | |
5588 | wanted_abi = global_mips_abi (); | |
5589 | if (gdbarch_debug) | |
5590 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5591 | wanted_abi); | |
2e4ebe70 DJ |
5592 | |
5593 | /* Now that we have found what the ABI for this binary would be, | |
5594 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5595 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5596 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5597 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5598 | mips_abi = found_abi; | |
5599 | else | |
5600 | mips_abi = MIPS_ABI_O32; | |
5601 | if (gdbarch_debug) | |
5602 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5603 | mips_abi); | |
2e4ebe70 | 5604 | |
ec03c1ac | 5605 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5606 | if (gdbarch_debug) |
ec03c1ac AC |
5607 | fprintf_unfiltered (gdb_stdlog, |
5608 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5609 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5610 | |
8d5838b5 | 5611 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5612 | #ifdef HAVE_ELF |
5613 | if (info.abfd | |
5614 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5615 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5616 | Tag_GNU_MIPS_ABI_FP); | |
5617 | #endif /* HAVE_ELF */ | |
5618 | ||
8d5838b5 AC |
5619 | if (!mips_fpu_type_auto) |
5620 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5621 | else if (elf_fpu_type != 0) |
5622 | { | |
5623 | switch (elf_fpu_type) | |
5624 | { | |
5625 | case 1: | |
5626 | fpu_type = MIPS_FPU_DOUBLE; | |
5627 | break; | |
5628 | case 2: | |
5629 | fpu_type = MIPS_FPU_SINGLE; | |
5630 | break; | |
5631 | case 3: | |
5632 | default: | |
5633 | /* Soft float or unknown. */ | |
5634 | fpu_type = MIPS_FPU_NONE; | |
5635 | break; | |
5636 | } | |
5637 | } | |
8d5838b5 AC |
5638 | else if (info.bfd_arch_info != NULL |
5639 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5640 | switch (info.bfd_arch_info->mach) | |
5641 | { | |
5642 | case bfd_mach_mips3900: | |
5643 | case bfd_mach_mips4100: | |
5644 | case bfd_mach_mips4111: | |
a9d61c86 | 5645 | case bfd_mach_mips4120: |
8d5838b5 AC |
5646 | fpu_type = MIPS_FPU_NONE; |
5647 | break; | |
5648 | case bfd_mach_mips4650: | |
5649 | fpu_type = MIPS_FPU_SINGLE; | |
5650 | break; | |
5651 | default: | |
5652 | fpu_type = MIPS_FPU_DOUBLE; | |
5653 | break; | |
5654 | } | |
5655 | else if (arches != NULL) | |
5656 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5657 | else | |
5658 | fpu_type = MIPS_FPU_DOUBLE; | |
5659 | if (gdbarch_debug) | |
5660 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5661 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5662 | |
29709017 DJ |
5663 | /* Check for blatant incompatibilities. */ |
5664 | ||
5665 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5666 | ABI. */ | |
5667 | if (info.target_desc | |
5668 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5669 | && mips_abi != MIPS_ABI_EABI32 | |
5670 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5671 | { |
5672 | if (tdesc_data != NULL) | |
5673 | tdesc_data_cleanup (tdesc_data); | |
5674 | return NULL; | |
5675 | } | |
29709017 | 5676 | |
c2d11a7d JM |
5677 | /* try to find a pre-existing architecture */ |
5678 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5679 | arches != NULL; | |
5680 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5681 | { | |
5682 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5683 | using. */ |
9103eae0 | 5684 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5685 | continue; |
9103eae0 | 5686 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5687 | continue; |
719ec221 AC |
5688 | /* Need to be pedantic about which register virtual size is |
5689 | used. */ | |
5690 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5691 | != mips64_transfers_32bit_regs_p) | |
5692 | continue; | |
8d5838b5 AC |
5693 | /* Be pedantic about which FPU is selected. */ |
5694 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5695 | continue; | |
f8b73d13 DJ |
5696 | |
5697 | if (tdesc_data != NULL) | |
5698 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5699 | return arches->gdbarch; |
c2d11a7d JM |
5700 | } |
5701 | ||
102182a9 | 5702 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5703 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5704 | gdbarch = gdbarch_alloc (&info, tdep); | |
5705 | tdep->elf_flags = elf_flags; | |
719ec221 | 5706 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5707 | tdep->found_abi = found_abi; |
5708 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5709 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5710 | tdep->register_size_valid_p = 0; |
5711 | tdep->register_size = 0; | |
5712 | ||
5713 | if (info.target_desc) | |
5714 | { | |
5715 | /* Some useful properties can be inferred from the target. */ | |
5716 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5717 | { | |
5718 | tdep->register_size_valid_p = 1; | |
5719 | tdep->register_size = 4; | |
5720 | } | |
5721 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5722 | { | |
5723 | tdep->register_size_valid_p = 1; | |
5724 | tdep->register_size = 8; | |
5725 | } | |
5726 | } | |
c2d11a7d | 5727 | |
102182a9 | 5728 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5729 | set_gdbarch_short_bit (gdbarch, 16); |
5730 | set_gdbarch_int_bit (gdbarch, 32); | |
5731 | set_gdbarch_float_bit (gdbarch, 32); | |
5732 | set_gdbarch_double_bit (gdbarch, 64); | |
5733 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5734 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5735 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5736 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5737 | |
6d82d43b | 5738 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5739 | mips_elf_make_msymbol_special); |
5740 | ||
16e109ca | 5741 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5742 | { |
16e109ca | 5743 | const char **reg_names; |
56cea623 AC |
5744 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5745 | struct mips_regnum); | |
f8b73d13 DJ |
5746 | if (tdesc_has_registers (info.target_desc)) |
5747 | { | |
5748 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5749 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5750 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5751 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5752 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5753 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5754 | regnum->fp_control_status = 70; | |
5755 | regnum->fp_implementation_revision = 71; | |
5756 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5757 | reg_names = NULL; | |
5758 | } | |
5759 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5760 | { |
5761 | regnum->fp0 = 32; | |
5762 | regnum->pc = 64; | |
5763 | regnum->cause = 65; | |
5764 | regnum->badvaddr = 66; | |
5765 | regnum->hi = 67; | |
5766 | regnum->lo = 68; | |
5767 | regnum->fp_control_status = 69; | |
5768 | regnum->fp_implementation_revision = 70; | |
5769 | num_regs = 71; | |
16e109ca | 5770 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5771 | } |
5772 | else | |
5773 | { | |
5774 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5775 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5776 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5777 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5778 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5779 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5780 | regnum->fp_control_status = 70; | |
5781 | regnum->fp_implementation_revision = 71; | |
5782 | num_regs = 90; | |
16e109ca AC |
5783 | if (info.bfd_arch_info != NULL |
5784 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5785 | reg_names = mips_tx39_reg_names; | |
5786 | else | |
5787 | reg_names = mips_generic_reg_names; | |
56cea623 | 5788 | } |
3e8c568d | 5789 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
56cea623 | 5790 | replaced by read_pc? */ |
f10683bb MH |
5791 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5792 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5793 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5794 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5795 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5796 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5797 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5798 | tdep->mips_processor_reg_names = reg_names; |
5799 | tdep->regnum = regnum; | |
56cea623 | 5800 | } |
fe29b929 | 5801 | |
0dadbba0 | 5802 | switch (mips_abi) |
c2d11a7d | 5803 | { |
0dadbba0 | 5804 | case MIPS_ABI_O32: |
25ab4790 | 5805 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5806 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5807 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5808 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5809 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5810 | set_gdbarch_long_bit (gdbarch, 32); |
5811 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5812 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5813 | break; | |
0dadbba0 | 5814 | case MIPS_ABI_O64: |
25ab4790 | 5815 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5816 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5817 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5818 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5819 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5820 | set_gdbarch_long_bit (gdbarch, 32); |
5821 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5822 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5823 | break; | |
0dadbba0 | 5824 | case MIPS_ABI_EABI32: |
25ab4790 | 5825 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5826 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5827 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5828 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5829 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5830 | set_gdbarch_long_bit (gdbarch, 32); |
5831 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5832 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5833 | break; | |
0dadbba0 | 5834 | case MIPS_ABI_EABI64: |
25ab4790 | 5835 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5836 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5837 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5838 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5839 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5840 | set_gdbarch_long_bit (gdbarch, 64); |
5841 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5842 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5843 | break; | |
0dadbba0 | 5844 | case MIPS_ABI_N32: |
25ab4790 | 5845 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5846 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5847 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5848 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5849 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5850 | set_gdbarch_long_bit (gdbarch, 32); |
5851 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5852 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5853 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5854 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
5855 | break; |
5856 | case MIPS_ABI_N64: | |
25ab4790 | 5857 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5858 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5859 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5860 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5861 | tdep->default_mask_address_p = 0; |
5862 | set_gdbarch_long_bit (gdbarch, 64); | |
5863 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5864 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5865 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5866 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 5867 | break; |
c2d11a7d | 5868 | default: |
e2e0b3e5 | 5869 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5870 | } |
5871 | ||
22e47e37 FF |
5872 | /* GCC creates a pseudo-section whose name specifies the size of |
5873 | longs, since -mlong32 or -mlong64 may be used independent of | |
5874 | other options. How those options affect pointer sizes is ABI and | |
5875 | architecture dependent, so use them to override the default sizes | |
5876 | set by the ABI. This table shows the relationship between ABI, | |
5877 | -mlongXX, and size of pointers: | |
5878 | ||
5879 | ABI -mlongXX ptr bits | |
5880 | --- -------- -------- | |
5881 | o32 32 32 | |
5882 | o32 64 32 | |
5883 | n32 32 32 | |
5884 | n32 64 64 | |
5885 | o64 32 32 | |
5886 | o64 64 64 | |
5887 | n64 32 32 | |
5888 | n64 64 64 | |
5889 | eabi32 32 32 | |
5890 | eabi32 64 32 | |
5891 | eabi64 32 32 | |
5892 | eabi64 64 64 | |
5893 | ||
5894 | Note that for o32 and eabi32, pointers are always 32 bits | |
5895 | regardless of any -mlongXX option. For all others, pointers and | |
5896 | longs are the same, as set by -mlongXX or set by defaults. | |
5897 | */ | |
5898 | ||
5899 | if (info.abfd != NULL) | |
5900 | { | |
5901 | int long_bit = 0; | |
5902 | ||
5903 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5904 | if (long_bit) | |
5905 | { | |
5906 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5907 | switch (mips_abi) | |
5908 | { | |
5909 | case MIPS_ABI_O32: | |
5910 | case MIPS_ABI_EABI32: | |
5911 | break; | |
5912 | case MIPS_ABI_N32: | |
5913 | case MIPS_ABI_O64: | |
5914 | case MIPS_ABI_N64: | |
5915 | case MIPS_ABI_EABI64: | |
5916 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5917 | break; | |
5918 | default: | |
5919 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5920 | } | |
5921 | } | |
5922 | } | |
5923 | ||
a5ea2558 AC |
5924 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5925 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5926 | comment: | |
5927 | ||
5928 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5929 | flag in object files because to do so would make it impossible to | |
102182a9 | 5930 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5931 | unnecessarily restrictive. |
361d1df0 | 5932 | |
a5ea2558 AC |
5933 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5934 | but to set this flag before gcc is built with such multilibs will | |
5935 | break too many systems.'' | |
5936 | ||
5937 | But even more unhelpfully, the default linker output target for | |
5938 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5939 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5940 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5941 | this flag to detect 32-bit mode would do the wrong thing given |
5942 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5943 | as 32-bit programs by default. */ |
a5ea2558 | 5944 | |
6c997a34 | 5945 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5946 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5947 | |
102182a9 MS |
5948 | /* Add/remove bits from an address. The MIPS needs be careful to |
5949 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5950 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5951 | ||
58dfe9ff AC |
5952 | /* Unwind the frame. */ |
5953 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5954 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 5955 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 5956 | |
102182a9 | 5957 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5958 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5959 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5960 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
5961 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
5962 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5963 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5964 | |
c2d11a7d JM |
5965 | /* MIPS version of CALL_DUMMY */ |
5966 | ||
9710e734 AC |
5967 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5968 | replaced by a command, and all targets will default to on stack | |
5969 | (regardless of the stack's execute status). */ | |
5970 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5971 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5972 | |
87783b8b AC |
5973 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5974 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5975 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5976 | ||
f7b9e9fc AC |
5977 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5978 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5979 | |
5980 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5981 | |
97ab0fdd MR |
5982 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
5983 | ||
fc0c74b1 AC |
5984 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5985 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5986 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5987 | |
a4b8ebc8 | 5988 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5989 | |
e11c53d2 | 5990 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5991 | |
9dae60cc UW |
5992 | if (mips_abi == MIPS_ABI_N32) |
5993 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
5994 | else if (mips_abi == MIPS_ABI_N64) | |
5995 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
5996 | else | |
5997 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 5998 | |
3a3bc038 AC |
5999 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6000 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6001 | need to all be folded into the target vector. Since they are | |
6002 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6003 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6004 | is sitting on? */ | |
6005 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6006 | ||
e7d6a6d2 | 6007 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6008 | |
3352ef37 AC |
6009 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
6010 | ||
0d5de010 DJ |
6011 | /* Virtual tables. */ |
6012 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6013 | ||
29709017 DJ |
6014 | mips_register_g_packet_guesses (gdbarch); |
6015 | ||
6de918a6 | 6016 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6017 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6018 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6019 | |
5792a79b | 6020 | /* Unwind the frame. */ |
b8a22b94 DJ |
6021 | dwarf2_append_unwinders (gdbarch); |
6022 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6023 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6024 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6025 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6026 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6027 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6028 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6029 | |
f8b73d13 DJ |
6030 | if (tdesc_data) |
6031 | { | |
6032 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6033 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6034 | |
6035 | /* Override the normal target description methods to handle our | |
6036 | dual real and pseudo registers. */ | |
6037 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6038 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
6039 | ||
6040 | num_regs = gdbarch_num_regs (gdbarch); | |
6041 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6042 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6043 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6044 | } | |
6045 | ||
6046 | /* Add ABI-specific aliases for the registers. */ | |
6047 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6048 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6049 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6050 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6051 | else | |
6052 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6053 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6054 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6055 | ||
6056 | /* Add some other standard aliases. */ | |
6057 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6058 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6059 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6060 | ||
4b9b3959 AC |
6061 | return gdbarch; |
6062 | } | |
6063 | ||
2e4ebe70 | 6064 | static void |
6d82d43b | 6065 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6066 | { |
6067 | struct gdbarch_info info; | |
6068 | ||
6069 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6070 | mips_gdbarch_init will take care of the rest. */ | |
6071 | gdbarch_info_init (&info); | |
6072 | gdbarch_update_p (info); | |
6073 | } | |
6074 | ||
ad188201 KB |
6075 | /* Print out which MIPS ABI is in use. */ |
6076 | ||
6077 | static void | |
1f8ca57c JB |
6078 | show_mips_abi (struct ui_file *file, |
6079 | int from_tty, | |
6080 | struct cmd_list_element *ignored_cmd, | |
6081 | const char *ignored_value) | |
ad188201 | 6082 | { |
1cf3db46 | 6083 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6084 | fprintf_filtered |
6085 | (file, | |
6086 | "The MIPS ABI is unknown because the current architecture " | |
6087 | "is not MIPS.\n"); | |
ad188201 KB |
6088 | else |
6089 | { | |
6090 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6091 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6092 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6093 | ||
6094 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6095 | fprintf_filtered |
6096 | (file, | |
6097 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6098 | actual_abi_str); |
ad188201 | 6099 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6100 | fprintf_filtered |
6101 | (file, | |
6102 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6103 | actual_abi_str); |
ad188201 KB |
6104 | else |
6105 | { | |
6106 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
6107 | fprintf_filtered |
6108 | (file, | |
6109 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 6110 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6111 | } |
6112 | } | |
6113 | } | |
6114 | ||
4b9b3959 | 6115 | static void |
72a155b4 | 6116 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6117 | { |
72a155b4 | 6118 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6119 | if (tdep != NULL) |
c2d11a7d | 6120 | { |
acdb74a0 AC |
6121 | int ef_mips_arch; |
6122 | int ef_mips_32bitmode; | |
f49e4e6d | 6123 | /* Determine the ISA. */ |
acdb74a0 AC |
6124 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6125 | { | |
6126 | case E_MIPS_ARCH_1: | |
6127 | ef_mips_arch = 1; | |
6128 | break; | |
6129 | case E_MIPS_ARCH_2: | |
6130 | ef_mips_arch = 2; | |
6131 | break; | |
6132 | case E_MIPS_ARCH_3: | |
6133 | ef_mips_arch = 3; | |
6134 | break; | |
6135 | case E_MIPS_ARCH_4: | |
93d56215 | 6136 | ef_mips_arch = 4; |
acdb74a0 AC |
6137 | break; |
6138 | default: | |
93d56215 | 6139 | ef_mips_arch = 0; |
acdb74a0 AC |
6140 | break; |
6141 | } | |
f49e4e6d | 6142 | /* Determine the size of a pointer. */ |
acdb74a0 | 6143 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6144 | fprintf_unfiltered (file, |
6145 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6146 | tdep->elf_flags); |
4b9b3959 | 6147 | fprintf_unfiltered (file, |
acdb74a0 AC |
6148 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6149 | ef_mips_32bitmode); | |
6150 | fprintf_unfiltered (file, | |
6151 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6152 | ef_mips_arch); | |
6153 | fprintf_unfiltered (file, | |
6154 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6155 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6156 | fprintf_unfiltered (file, |
6157 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6158 | mips_mask_address_p (tdep), |
4014092b | 6159 | tdep->default_mask_address_p); |
c2d11a7d | 6160 | } |
4b9b3959 AC |
6161 | fprintf_unfiltered (file, |
6162 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6163 | MIPS_DEFAULT_FPU_TYPE, | |
6164 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6165 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6166 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6167 | : "???")); | |
74ed0bb4 MD |
6168 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6169 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6170 | fprintf_unfiltered (file, |
6171 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6172 | MIPS_FPU_TYPE (gdbarch), |
6173 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6174 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6175 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6176 | : "???")); |
c2d11a7d JM |
6177 | } |
6178 | ||
6d82d43b | 6179 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6180 | |
c906108c | 6181 | void |
acdb74a0 | 6182 | _initialize_mips_tdep (void) |
c906108c SS |
6183 | { |
6184 | static struct cmd_list_element *mipsfpulist = NULL; | |
6185 | struct cmd_list_element *c; | |
6186 | ||
6d82d43b | 6187 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6188 | if (MIPS_ABI_LAST + 1 |
6189 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6190 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6191 | |
4b9b3959 | 6192 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6193 | |
8d5f9dcb DJ |
6194 | mips_pdr_data = register_objfile_data (); |
6195 | ||
4eb0ad19 DJ |
6196 | /* Create feature sets with the appropriate properties. The values |
6197 | are not important. */ | |
6198 | mips_tdesc_gp32 = allocate_target_description (); | |
6199 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6200 | ||
6201 | mips_tdesc_gp64 = allocate_target_description (); | |
6202 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6203 | ||
a5ea2558 AC |
6204 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6205 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 6206 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6207 | &setmipscmdlist, "set mips ", 0, &setlist); |
6208 | ||
6209 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6210 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6211 | &showmipscmdlist, "show mips ", 0, &showlist); |
6212 | ||
2e4ebe70 | 6213 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6214 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6215 | &mips_abi_string, _("\ | |
6216 | Set the MIPS ABI used by this program."), _("\ | |
6217 | Show the MIPS ABI used by this program."), _("\ | |
6218 | This option can be set to one of:\n\ | |
6219 | auto - the default ABI associated with the current binary\n\ | |
6220 | o32\n\ | |
6221 | o64\n\ | |
6222 | n32\n\ | |
6223 | n64\n\ | |
6224 | eabi32\n\ | |
6225 | eabi64"), | |
6226 | mips_abi_update, | |
6227 | show_mips_abi, | |
6228 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6229 | |
c906108c SS |
6230 | /* Let the user turn off floating point and set the fence post for |
6231 | heuristic_proc_start. */ | |
6232 | ||
6233 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6234 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6235 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6236 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6237 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6238 | &mipsfpulist); |
6239 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6240 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6241 | &mipsfpulist); |
6242 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6243 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6244 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6245 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6246 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6247 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6248 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6249 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6250 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6251 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6252 | &mipsfpulist); |
6253 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6254 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6255 | &showlist); |
6256 | ||
c906108c SS |
6257 | /* We really would like to have both "0" and "unlimited" work, but |
6258 | command.c doesn't deal with that. So make it a var_zinteger | |
6259 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6260 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6261 | &heuristic_fence_post, _("\ |
6262 | Set the distance searched for the start of a function."), _("\ | |
6263 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6264 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6265 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6266 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6267 | reinit_frame_cache_sfunc, |
7915a72c | 6268 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 6269 | &setlist, &showlist); |
c906108c SS |
6270 | |
6271 | /* Allow the user to control whether the upper bits of 64-bit | |
6272 | addresses should be zeroed. */ | |
7915a72c AC |
6273 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6274 | &mask_address_var, _("\ | |
6275 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6276 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 6277 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 6278 | allow GDB to determine the correct value."), |
08546159 AC |
6279 | NULL, show_mask_address, |
6280 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6281 | |
6282 | /* Allow the user to control the size of 32 bit registers within the | |
6283 | raw remote packet. */ | |
b3f42336 | 6284 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6285 | &mips64_transfers_32bit_regs_p, _("\ |
6286 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6287 | _("\ | |
6288 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6289 | _("\ | |
719ec221 AC |
6290 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6291 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6292 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6293 | set_mips64_transfers_32bit_regs, |
7915a72c | 6294 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 6295 | &setlist, &showlist); |
9ace0497 AC |
6296 | |
6297 | /* Debug this files internals. */ | |
6bcadd06 | 6298 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6299 | &mips_debug, _("\ |
6300 | Set mips debugging."), _("\ | |
6301 | Show mips debugging."), _("\ | |
6302 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6303 | NULL, |
7915a72c | 6304 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 6305 | &setdebuglist, &showdebuglist); |
c906108c | 6306 | } |