Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
7b6bb8da | 5 | 2010, 2011 Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
79a45b7d | 60 | #include "valprint.h" |
175ff332 | 61 | #include "ax.h" |
c906108c | 62 | |
8d5f9dcb DJ |
63 | static const struct objfile_data *mips_pdr_data; |
64 | ||
5bbcb741 | 65 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 66 | |
24e05951 | 67 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
68 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
69 | #define ST0_FR (1 << 26) | |
70 | ||
b0069a17 AC |
71 | /* The sizes of floating point registers. */ |
72 | ||
73 | enum | |
74 | { | |
75 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
76 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
77 | }; | |
78 | ||
1a69e1e4 DJ |
79 | enum |
80 | { | |
81 | MIPS32_REGSIZE = 4, | |
82 | MIPS64_REGSIZE = 8 | |
83 | }; | |
0dadbba0 | 84 | |
2e4ebe70 DJ |
85 | static const char *mips_abi_string; |
86 | ||
87 | static const char *mips_abi_strings[] = { | |
88 | "auto", | |
89 | "n32", | |
90 | "o32", | |
28d169de | 91 | "n64", |
2e4ebe70 DJ |
92 | "o64", |
93 | "eabi32", | |
94 | "eabi64", | |
95 | NULL | |
96 | }; | |
97 | ||
f8b73d13 DJ |
98 | /* The standard register names, and all the valid aliases for them. */ |
99 | struct register_alias | |
100 | { | |
101 | const char *name; | |
102 | int regnum; | |
103 | }; | |
104 | ||
105 | /* Aliases for o32 and most other ABIs. */ | |
106 | const struct register_alias mips_o32_aliases[] = { | |
107 | { "ta0", 12 }, | |
108 | { "ta1", 13 }, | |
109 | { "ta2", 14 }, | |
110 | { "ta3", 15 } | |
111 | }; | |
112 | ||
113 | /* Aliases for n32 and n64. */ | |
114 | const struct register_alias mips_n32_n64_aliases[] = { | |
115 | { "ta0", 8 }, | |
116 | { "ta1", 9 }, | |
117 | { "ta2", 10 }, | |
118 | { "ta3", 11 } | |
119 | }; | |
120 | ||
121 | /* Aliases for ABI-independent registers. */ | |
122 | const struct register_alias mips_register_aliases[] = { | |
123 | /* The architecture manuals specify these ABI-independent names for | |
124 | the GPRs. */ | |
125 | #define R(n) { "r" #n, n } | |
126 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
127 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
128 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
129 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
130 | #undef R | |
131 | ||
132 | /* k0 and k1 are sometimes called these instead (for "kernel | |
133 | temp"). */ | |
134 | { "kt0", 26 }, | |
135 | { "kt1", 27 }, | |
136 | ||
137 | /* This is the traditional GDB name for the CP0 status register. */ | |
138 | { "sr", MIPS_PS_REGNUM }, | |
139 | ||
140 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
141 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
142 | ||
143 | /* This is the traditional GDB name for the FCSR. */ | |
144 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
145 | }; | |
146 | ||
865093a3 AR |
147 | const struct register_alias mips_numeric_register_aliases[] = { |
148 | #define R(n) { #n, n } | |
149 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
150 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
151 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
152 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
153 | #undef R | |
154 | }; | |
155 | ||
c906108c SS |
156 | #ifndef MIPS_DEFAULT_FPU_TYPE |
157 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
158 | #endif | |
159 | static int mips_fpu_type_auto = 1; | |
160 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 161 | |
9ace0497 | 162 | static int mips_debug = 0; |
7a292a7a | 163 | |
29709017 DJ |
164 | /* Properties (for struct target_desc) describing the g/G packet |
165 | layout. */ | |
166 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
167 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
168 | ||
4eb0ad19 DJ |
169 | struct target_desc *mips_tdesc_gp32; |
170 | struct target_desc *mips_tdesc_gp64; | |
171 | ||
56cea623 AC |
172 | const struct mips_regnum * |
173 | mips_regnum (struct gdbarch *gdbarch) | |
174 | { | |
175 | return gdbarch_tdep (gdbarch)->regnum; | |
176 | } | |
177 | ||
178 | static int | |
179 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
180 | { | |
181 | return mips_regnum (gdbarch)->fp0 + 12; | |
182 | } | |
183 | ||
74ed0bb4 MD |
184 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
185 | == MIPS_ABI_EABI32 \ | |
186 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 187 | |
025bb325 MS |
188 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
189 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 190 | |
025bb325 MS |
191 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
192 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 193 | |
74ed0bb4 | 194 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 195 | |
95404a3e AC |
196 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
197 | functions to test, set, or clear bit 0 of addresses. */ | |
198 | ||
199 | static CORE_ADDR | |
200 | is_mips16_addr (CORE_ADDR addr) | |
201 | { | |
202 | return ((addr) & 1); | |
203 | } | |
204 | ||
95404a3e AC |
205 | static CORE_ADDR |
206 | unmake_mips16_addr (CORE_ADDR addr) | |
207 | { | |
5b652102 | 208 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
209 | } |
210 | ||
930bd0e0 KB |
211 | static CORE_ADDR |
212 | make_mips16_addr (CORE_ADDR addr) | |
213 | { | |
214 | return ((addr) | (CORE_ADDR) 1); | |
215 | } | |
216 | ||
d1973055 KB |
217 | /* Return the MIPS ABI associated with GDBARCH. */ |
218 | enum mips_abi | |
219 | mips_abi (struct gdbarch *gdbarch) | |
220 | { | |
221 | return gdbarch_tdep (gdbarch)->mips_abi; | |
222 | } | |
223 | ||
4246e332 | 224 | int |
1b13c4f6 | 225 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 226 | { |
29709017 DJ |
227 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
228 | ||
229 | /* If we know how big the registers are, use that size. */ | |
230 | if (tdep->register_size_valid_p) | |
231 | return tdep->register_size; | |
232 | ||
233 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
234 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
235 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
236 | } | |
237 | ||
025bb325 | 238 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 239 | |
e6bc2e8a | 240 | unsigned int |
13326b4e | 241 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 242 | { |
1a69e1e4 DJ |
243 | switch (mips_abi (gdbarch)) |
244 | { | |
245 | case MIPS_ABI_EABI32: | |
246 | case MIPS_ABI_O32: | |
247 | return 4; | |
248 | case MIPS_ABI_N32: | |
249 | case MIPS_ABI_N64: | |
250 | case MIPS_ABI_O64: | |
251 | case MIPS_ABI_EABI64: | |
252 | return 8; | |
253 | case MIPS_ABI_UNKNOWN: | |
254 | case MIPS_ABI_LAST: | |
255 | default: | |
256 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
257 | } | |
d929b26f AC |
258 | } |
259 | ||
71b8ef93 | 260 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 261 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 262 | "info" field is used for this purpose. |
5a89d8aa | 263 | |
95f1da47 | 264 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
265 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
266 | minimal symbol to mark it as a 16-bit function | |
267 | ||
f594e5e9 | 268 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 269 | |
5a89d8aa | 270 | static void |
6d82d43b AC |
271 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
272 | { | |
273 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
274 | { | |
b887350f | 275 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b | 276 | } |
5a89d8aa MS |
277 | } |
278 | ||
71b8ef93 MS |
279 | static int |
280 | msymbol_is_special (struct minimal_symbol *msym) | |
281 | { | |
b887350f | 282 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
283 | } |
284 | ||
88658117 AC |
285 | /* XFER a value from the big/little/left end of the register. |
286 | Depending on the size of the value it might occupy the entire | |
287 | register or just part of it. Make an allowance for this, aligning | |
288 | things accordingly. */ | |
289 | ||
290 | static void | |
ba32f989 DJ |
291 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
292 | int reg_num, int length, | |
870cd05e MK |
293 | enum bfd_endian endian, gdb_byte *in, |
294 | const gdb_byte *out, int buf_offset) | |
88658117 | 295 | { |
88658117 | 296 | int reg_offset = 0; |
72a155b4 UW |
297 | |
298 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
299 | /* Need to transfer the left or right part of the register, based on |
300 | the targets byte order. */ | |
88658117 AC |
301 | switch (endian) |
302 | { | |
303 | case BFD_ENDIAN_BIG: | |
72a155b4 | 304 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
305 | break; |
306 | case BFD_ENDIAN_LITTLE: | |
307 | reg_offset = 0; | |
308 | break; | |
6d82d43b | 309 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
310 | reg_offset = 0; |
311 | break; | |
312 | default: | |
e2e0b3e5 | 313 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
314 | } |
315 | if (mips_debug) | |
cb1d2653 AC |
316 | fprintf_unfiltered (gdb_stderr, |
317 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
318 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
319 | if (mips_debug && out != NULL) |
320 | { | |
321 | int i; | |
cb1d2653 | 322 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 323 | for (i = 0; i < length; i++) |
cb1d2653 | 324 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
325 | } |
326 | if (in != NULL) | |
6d82d43b AC |
327 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
328 | in + buf_offset); | |
88658117 | 329 | if (out != NULL) |
6d82d43b AC |
330 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
331 | out + buf_offset); | |
88658117 AC |
332 | if (mips_debug && in != NULL) |
333 | { | |
334 | int i; | |
cb1d2653 | 335 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 336 | for (i = 0; i < length; i++) |
cb1d2653 | 337 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
338 | } |
339 | if (mips_debug) | |
340 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
341 | } | |
342 | ||
dd824b04 DJ |
343 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
344 | compatiblity mode. A return value of 1 means that we have | |
345 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
346 | ||
347 | static int | |
9c9acae0 | 348 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 349 | { |
72a155b4 | 350 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
351 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
352 | meaningful. */ | |
72a155b4 | 353 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
354 | return 0; |
355 | ||
356 | #if 0 | |
357 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
358 | in all the places we deal with FP registers. PR gdb/413. */ | |
359 | /* Otherwise check the FR bit in the status register - it controls | |
360 | the FP compatiblity mode. If it is clear we are in compatibility | |
361 | mode. */ | |
9c9acae0 | 362 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
363 | return 1; |
364 | #endif | |
361d1df0 | 365 | |
dd824b04 DJ |
366 | return 0; |
367 | } | |
368 | ||
7a292a7a | 369 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 370 | |
74ed0bb4 | 371 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 372 | |
a14ed312 | 373 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 374 | |
025bb325 | 375 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
376 | |
377 | static struct cmd_list_element *setmipscmdlist = NULL; | |
378 | static struct cmd_list_element *showmipscmdlist = NULL; | |
379 | ||
5e2e9765 KB |
380 | /* Integer registers 0 thru 31 are handled explicitly by |
381 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 382 | are listed in the following tables. */ |
691c0433 | 383 | |
6d82d43b AC |
384 | enum |
385 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
386 | |
387 | /* Generic MIPS. */ | |
388 | ||
389 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
390 | "sr", "lo", "hi", "bad", "cause", "pc", |
391 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
392 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
393 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
394 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
395 | "fsr", "fir", "" /*"fp" */ , "", | |
396 | "", "", "", "", "", "", "", "", | |
397 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
398 | }; |
399 | ||
400 | /* Names of IDT R3041 registers. */ | |
401 | ||
402 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
403 | "sr", "lo", "hi", "bad", "cause", "pc", |
404 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
405 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
406 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
407 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
408 | "fsr", "fir", "", /*"fp" */ "", | |
409 | "", "", "bus", "ccfg", "", "", "", "", | |
410 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
411 | }; |
412 | ||
413 | /* Names of tx39 registers. */ | |
414 | ||
415 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
416 | "sr", "lo", "hi", "bad", "cause", "pc", |
417 | "", "", "", "", "", "", "", "", | |
418 | "", "", "", "", "", "", "", "", | |
419 | "", "", "", "", "", "", "", "", | |
420 | "", "", "", "", "", "", "", "", | |
421 | "", "", "", "", | |
422 | "", "", "", "", "", "", "", "", | |
423 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
424 | }; |
425 | ||
426 | /* Names of IRIX registers. */ | |
427 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
428 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
429 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
430 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
431 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
432 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
433 | }; |
434 | ||
cce74817 | 435 | |
5e2e9765 | 436 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 437 | static const char * |
d93859e2 | 438 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 439 | { |
d93859e2 | 440 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
441 | /* GPR names for all ABIs other than n32/n64. */ |
442 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
443 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
444 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
445 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
446 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
447 | }; |
448 | ||
449 | /* GPR names for n32 and n64 ABIs. */ | |
450 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
451 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
452 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
453 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
454 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
455 | }; |
456 | ||
d93859e2 | 457 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 458 | |
f57d151a | 459 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
460 | but then don't make the raw register names visible. This (upper) |
461 | range of user visible register numbers are the pseudo-registers. | |
462 | ||
463 | This approach was adopted accommodate the following scenario: | |
464 | It is possible to debug a 64-bit device using a 32-bit | |
465 | programming model. In such instances, the raw registers are | |
466 | configured to be 64-bits wide, while the pseudo registers are | |
467 | configured to be 32-bits wide. The registers that the user | |
468 | sees - the pseudo registers - match the users expectations | |
469 | given the programming model being used. */ | |
d93859e2 UW |
470 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
471 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
472 | return ""; |
473 | ||
5e2e9765 KB |
474 | /* The MIPS integer registers are always mapped from 0 to 31. The |
475 | names of the registers (which reflects the conventions regarding | |
476 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 477 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
478 | { |
479 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 480 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 481 | else |
a4b8ebc8 | 482 | return mips_gpr_names[rawnum]; |
5e2e9765 | 483 | } |
d93859e2 UW |
484 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
485 | return tdesc_register_name (gdbarch, rawnum); | |
486 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
487 | { |
488 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
489 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
490 | } | |
5e2e9765 KB |
491 | else |
492 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 493 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 494 | } |
5e2e9765 | 495 | |
a4b8ebc8 | 496 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 497 | |
a4b8ebc8 AC |
498 | static int |
499 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
500 | struct reggroup *reggroup) | |
501 | { | |
502 | int vector_p; | |
503 | int float_p; | |
504 | int raw_p; | |
72a155b4 UW |
505 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
506 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
507 | if (reggroup == all_reggroup) |
508 | return pseudo; | |
509 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
510 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
511 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
512 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
513 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
514 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
515 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
516 | return 0; |
517 | if (reggroup == float_reggroup) | |
518 | return float_p && pseudo; | |
519 | if (reggroup == vector_reggroup) | |
520 | return vector_p && pseudo; | |
521 | if (reggroup == general_reggroup) | |
522 | return (!vector_p && !float_p) && pseudo; | |
523 | /* Save the pseudo registers. Need to make certain that any code | |
524 | extracting register values from a saved register cache also uses | |
525 | pseudo registers. */ | |
526 | if (reggroup == save_reggroup) | |
527 | return raw_p && pseudo; | |
528 | /* Restore the same pseudo register. */ | |
529 | if (reggroup == restore_reggroup) | |
530 | return raw_p && pseudo; | |
6d82d43b | 531 | return 0; |
a4b8ebc8 AC |
532 | } |
533 | ||
f8b73d13 DJ |
534 | /* Return the groups that a MIPS register can be categorised into. |
535 | This version is only used if we have a target description which | |
536 | describes real registers (and their groups). */ | |
537 | ||
538 | static int | |
539 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
540 | struct reggroup *reggroup) | |
541 | { | |
542 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
543 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
544 | int ret; | |
545 | ||
546 | /* Only save, restore, and display the pseudo registers. Need to | |
547 | make certain that any code extracting register values from a | |
548 | saved register cache also uses pseudo registers. | |
549 | ||
550 | Note: saving and restoring the pseudo registers is slightly | |
551 | strange; if we have 64 bits, we should save and restore all | |
552 | 64 bits. But this is hard and has little benefit. */ | |
553 | if (!pseudo) | |
554 | return 0; | |
555 | ||
556 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
557 | if (ret != -1) | |
558 | return ret; | |
559 | ||
560 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
561 | } | |
562 | ||
a4b8ebc8 | 563 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 564 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 565 | registers. Take care of alignment and size problems. */ |
c5aa993b | 566 | |
05d1431c | 567 | static enum register_status |
a4b8ebc8 | 568 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 569 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 570 | { |
72a155b4 UW |
571 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
572 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
573 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 574 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 575 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
576 | else if (register_size (gdbarch, rawnum) > |
577 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 578 | { |
8bdf35dc | 579 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 580 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 581 | else |
8bdf35dc KB |
582 | { |
583 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
584 | LONGEST regval; | |
05d1431c PA |
585 | enum register_status status; |
586 | ||
587 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
588 | if (status == REG_VALID) | |
589 | store_signed_integer (buf, 4, byte_order, regval); | |
590 | return status; | |
8bdf35dc | 591 | } |
47ebcfbe AC |
592 | } |
593 | else | |
e2e0b3e5 | 594 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
595 | } |
596 | ||
597 | static void | |
6d82d43b AC |
598 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
599 | struct regcache *regcache, int cookednum, | |
47a35522 | 600 | const gdb_byte *buf) |
a4b8ebc8 | 601 | { |
72a155b4 UW |
602 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
603 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
604 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 605 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 606 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
607 | else if (register_size (gdbarch, rawnum) > |
608 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 609 | { |
8bdf35dc | 610 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
611 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
612 | else | |
8bdf35dc KB |
613 | { |
614 | /* Sign extend the shortened version of the register prior | |
615 | to placing it in the raw register. This is required for | |
616 | some mips64 parts in order to avoid unpredictable behavior. */ | |
617 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
618 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
619 | regcache_raw_write_signed (regcache, rawnum, regval); | |
620 | } | |
47ebcfbe AC |
621 | } |
622 | else | |
e2e0b3e5 | 623 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 624 | } |
c5aa993b | 625 | |
175ff332 HZ |
626 | static int |
627 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
628 | struct agent_expr *ax, int reg) | |
629 | { | |
630 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
631 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
632 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
633 | ||
634 | ax_reg_mask (ax, rawnum); | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
639 | static int | |
640 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
641 | struct agent_expr *ax, int reg) | |
642 | { | |
643 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
644 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
645 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
646 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
647 | { | |
648 | ax_reg (ax, rawnum); | |
649 | ||
650 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
651 | { | |
652 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
653 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
654 | { | |
655 | ax_const_l (ax, 32); | |
656 | ax_simple (ax, aop_lsh); | |
657 | } | |
658 | ax_const_l (ax, 32); | |
659 | ax_simple (ax, aop_rsh_signed); | |
660 | } | |
661 | } | |
662 | else | |
663 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
c906108c | 668 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 669 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
670 | |
671 | /* Heuristic_proc_start may hunt through the text section for a long | |
672 | time across a 2400 baud serial line. Allows the user to limit this | |
673 | search. */ | |
674 | ||
675 | static unsigned int heuristic_fence_post = 0; | |
676 | ||
46cd78fb | 677 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
678 | register N. NOTE: This defines the pseudo register type so need to |
679 | rebuild the architecture vector. */ | |
43e526b9 JM |
680 | |
681 | static int mips64_transfers_32bit_regs_p = 0; | |
682 | ||
719ec221 AC |
683 | static void |
684 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
685 | struct cmd_list_element *c) | |
43e526b9 | 686 | { |
719ec221 AC |
687 | struct gdbarch_info info; |
688 | gdbarch_info_init (&info); | |
689 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
690 | instead of relying on globals. Doing that would let generic code | |
691 | handle the search for this specific architecture. */ | |
692 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 693 | { |
719ec221 | 694 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 695 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 696 | } |
a4b8ebc8 AC |
697 | } |
698 | ||
47ebcfbe | 699 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 700 | |
ee51a8c7 KB |
701 | /* This predicate tests for the case of an 8 byte floating point |
702 | value that is being transferred to or from a pair of floating point | |
703 | registers each of which are (or are considered to be) only 4 bytes | |
704 | wide. */ | |
ff2e87ac | 705 | static int |
ee51a8c7 KB |
706 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
707 | struct type *type) | |
ff2e87ac | 708 | { |
0abe36f5 MD |
709 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
710 | && register_size (gdbarch, regnum) == 4 | |
711 | && (regnum % gdbarch_num_regs (gdbarch)) | |
712 | >= mips_regnum (gdbarch)->fp0 | |
713 | && (regnum % gdbarch_num_regs (gdbarch)) | |
714 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 715 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
716 | } |
717 | ||
ee51a8c7 KB |
718 | /* This predicate tests for the case of a value of less than 8 |
719 | bytes in width that is being transfered to or from an 8 byte | |
720 | general purpose register. */ | |
721 | static int | |
722 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
723 | struct type *type) | |
724 | { | |
725 | int num_regs = gdbarch_num_regs (gdbarch); | |
726 | ||
727 | return (register_size (gdbarch, regnum) == 8 | |
728 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
729 | && TYPE_LENGTH (type) < 8); | |
730 | } | |
731 | ||
732 | static int | |
025bb325 MS |
733 | mips_convert_register_p (struct gdbarch *gdbarch, |
734 | int regnum, struct type *type) | |
ee51a8c7 KB |
735 | { |
736 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
737 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
738 | } | |
739 | ||
8dccd430 | 740 | static int |
ff2e87ac | 741 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
742 | struct type *type, gdb_byte *to, |
743 | int *optimizedp, int *unavailablep) | |
102182a9 | 744 | { |
ee51a8c7 KB |
745 | struct gdbarch *gdbarch = get_frame_arch (frame); |
746 | ||
747 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
748 | { | |
749 | get_frame_register (frame, regnum + 0, to + 4); | |
750 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
751 | |
752 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
753 | optimizedp, unavailablep)) | |
754 | return 0; | |
755 | ||
756 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
757 | optimizedp, unavailablep)) | |
758 | return 0; | |
759 | *optimizedp = *unavailablep = 0; | |
760 | return 1; | |
ee51a8c7 KB |
761 | } |
762 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
763 | { | |
764 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
765 | CORE_ADDR offset; |
766 | ||
767 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
768 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
769 | optimizedp, unavailablep)) | |
770 | return 0; | |
771 | ||
772 | *optimizedp = *unavailablep = 0; | |
773 | return 1; | |
ee51a8c7 KB |
774 | } |
775 | else | |
776 | { | |
777 | internal_error (__FILE__, __LINE__, | |
778 | _("mips_register_to_value: unrecognized case")); | |
779 | } | |
102182a9 MS |
780 | } |
781 | ||
42c466d7 | 782 | static void |
ff2e87ac | 783 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 784 | struct type *type, const gdb_byte *from) |
102182a9 | 785 | { |
ee51a8c7 KB |
786 | struct gdbarch *gdbarch = get_frame_arch (frame); |
787 | ||
788 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
789 | { | |
790 | put_frame_register (frame, regnum + 0, from + 4); | |
791 | put_frame_register (frame, regnum + 1, from + 0); | |
792 | } | |
793 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
794 | { | |
795 | gdb_byte fill[8]; | |
796 | int len = TYPE_LENGTH (type); | |
797 | ||
798 | /* Sign extend values, irrespective of type, that are stored to | |
799 | a 64-bit general purpose register. (32-bit unsigned values | |
800 | are stored as signed quantities within a 64-bit register. | |
801 | When performing an operation, in compiled code, that combines | |
802 | a 32-bit unsigned value with a signed 64-bit value, a type | |
803 | conversion is first performed that zeroes out the high 32 bits.) */ | |
804 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
805 | { | |
806 | if (from[0] & 0x80) | |
807 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
808 | else | |
809 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
810 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
811 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
812 | } | |
813 | else | |
814 | { | |
815 | if (from[len-1] & 0x80) | |
816 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
817 | else | |
818 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
819 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
820 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
821 | } | |
822 | } | |
823 | else | |
824 | { | |
825 | internal_error (__FILE__, __LINE__, | |
826 | _("mips_value_to_register: unrecognized case")); | |
827 | } | |
102182a9 MS |
828 | } |
829 | ||
a4b8ebc8 AC |
830 | /* Return the GDB type object for the "standard" data type of data in |
831 | register REG. */ | |
78fde5f8 KB |
832 | |
833 | static struct type * | |
a4b8ebc8 AC |
834 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
835 | { | |
72a155b4 UW |
836 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
837 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
838 | && (regnum % gdbarch_num_regs (gdbarch)) | |
839 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 840 | { |
5ef80fb0 | 841 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 842 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 843 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 844 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 845 | else |
27067745 | 846 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 847 | } |
72a155b4 | 848 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
849 | { |
850 | /* The raw or ISA registers. These are all sized according to | |
851 | the ISA regsize. */ | |
852 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 853 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 854 | else |
df4df182 | 855 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 856 | } |
78fde5f8 | 857 | else |
d5ac5a39 AC |
858 | { |
859 | /* The cooked or ABI registers. These are sized according to | |
860 | the ABI (with a few complications). */ | |
72a155b4 UW |
861 | if (regnum >= (gdbarch_num_regs (gdbarch) |
862 | + mips_regnum (gdbarch)->fp_control_status) | |
863 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
864 | /* The pseudo/cooked view of the embedded registers is always |
865 | 32-bit. The raw view is handled below. */ | |
df4df182 | 866 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
867 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
868 | /* The target, while possibly using a 64-bit register buffer, | |
869 | is only transfering 32-bits of each integer register. | |
870 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 871 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
872 | else if (mips_abi_regsize (gdbarch) == 4) |
873 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
874 | 32- or 64-bit). */ | |
df4df182 | 875 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
876 | else |
877 | /* 64-bit ABI. */ | |
df4df182 | 878 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 879 | } |
78fde5f8 KB |
880 | } |
881 | ||
f8b73d13 DJ |
882 | /* Return the GDB type for the pseudo register REGNUM, which is the |
883 | ABI-level view. This function is only called if there is a target | |
884 | description which includes registers, so we know precisely the | |
885 | types of hardware registers. */ | |
886 | ||
887 | static struct type * | |
888 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
889 | { | |
890 | const int num_regs = gdbarch_num_regs (gdbarch); | |
891 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
892 | int rawnum = regnum % num_regs; | |
893 | struct type *rawtype; | |
894 | ||
895 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
896 | ||
897 | /* Absent registers are still absent. */ | |
898 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
899 | if (TYPE_LENGTH (rawtype) == 0) | |
900 | return rawtype; | |
901 | ||
902 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
903 | /* Present the floating point registers however the hardware did; | |
904 | do not try to convert between FPU layouts. */ | |
905 | return rawtype; | |
906 | ||
907 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
908 | { | |
909 | /* The pseudo/cooked view of embedded registers is always | |
910 | 32-bit, even if the target transfers 64-bit values for them. | |
911 | New targets relying on XML descriptions should only transfer | |
912 | the necessary 32 bits, but older versions of GDB expected 64, | |
913 | so allow the target to provide 64 bits without interfering | |
914 | with the displayed type. */ | |
df4df182 | 915 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
916 | } |
917 | ||
918 | /* Use pointer types for registers if we can. For n32 we can not, | |
919 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
920 | if (mips_abi_regsize (gdbarch) |
921 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
922 | { |
923 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 924 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 925 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 926 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
927 | } |
928 | ||
929 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
930 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
df4df182 | 931 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
932 | |
933 | /* For all other registers, pass through the hardware type. */ | |
934 | return rawtype; | |
935 | } | |
bcb0cc15 | 936 | |
025bb325 | 937 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 938 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
939 | |
940 | static int | |
480d3dd2 | 941 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
942 | { |
943 | switch (mask_address_var) | |
944 | { | |
7f19b9a2 | 945 | case AUTO_BOOLEAN_TRUE: |
4014092b | 946 | return 1; |
7f19b9a2 | 947 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
948 | return 0; |
949 | break; | |
7f19b9a2 | 950 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 951 | return tdep->default_mask_address_p; |
4014092b | 952 | default: |
025bb325 MS |
953 | internal_error (__FILE__, __LINE__, |
954 | _("mips_mask_address_p: bad switch")); | |
4014092b | 955 | return -1; |
361d1df0 | 956 | } |
4014092b AC |
957 | } |
958 | ||
959 | static void | |
08546159 AC |
960 | show_mask_address (struct ui_file *file, int from_tty, |
961 | struct cmd_list_element *c, const char *value) | |
4014092b | 962 | { |
1cf3db46 | 963 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
964 | |
965 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
966 | switch (mask_address_var) |
967 | { | |
7f19b9a2 | 968 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
969 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
970 | break; | |
7f19b9a2 | 971 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
972 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
973 | break; | |
7f19b9a2 | 974 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
975 | printf_filtered |
976 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
977 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
978 | break; |
979 | default: | |
e2e0b3e5 | 980 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 981 | break; |
361d1df0 | 982 | } |
4014092b | 983 | } |
c906108c | 984 | |
c906108c SS |
985 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
986 | ||
0fe7e7c8 AC |
987 | int |
988 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
989 | { |
990 | struct minimal_symbol *sym; | |
991 | ||
025bb325 | 992 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ |
95404a3e | 993 | if (is_mips16_addr (memaddr)) |
c906108c SS |
994 | return 1; |
995 | ||
996 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
997 | the high bit of the info field. Use this to decide if the function is | |
998 | MIPS16 or normal MIPS. */ | |
999 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1000 | if (sym) | |
71b8ef93 | 1001 | return msymbol_is_special (sym); |
c906108c SS |
1002 | else |
1003 | return 0; | |
1004 | } | |
1005 | ||
b2fa5097 | 1006 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1007 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1008 | |
1009 | static CORE_ADDR | |
61a1198a | 1010 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1011 | { |
61a1198a UW |
1012 | ULONGEST pc; |
1013 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
1014 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
930bd0e0 KB |
1015 | if (is_mips16_addr (pc)) |
1016 | pc = unmake_mips16_addr (pc); | |
61a1198a | 1017 | return pc; |
b6cb9035 AC |
1018 | } |
1019 | ||
58dfe9ff AC |
1020 | static CORE_ADDR |
1021 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1022 | { | |
930bd0e0 KB |
1023 | ULONGEST pc; |
1024 | ||
1025 | pc = frame_unwind_register_signed | |
1026 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
1027 | if (is_mips16_addr (pc)) | |
1028 | pc = unmake_mips16_addr (pc); | |
1029 | return pc; | |
edfae063 AC |
1030 | } |
1031 | ||
30244cd8 UW |
1032 | static CORE_ADDR |
1033 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1034 | { | |
72a155b4 UW |
1035 | return frame_unwind_register_signed |
1036 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1037 | } |
1038 | ||
b8a22b94 | 1039 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1040 | dummy frame. The frame ID's base needs to match the TOS value |
1041 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1042 | breakpoint. */ | |
1043 | ||
1044 | static struct frame_id | |
b8a22b94 | 1045 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1046 | { |
f57d151a | 1047 | return frame_id_build |
b8a22b94 DJ |
1048 | (get_frame_register_signed (this_frame, |
1049 | gdbarch_num_regs (gdbarch) | |
1050 | + MIPS_SP_REGNUM), | |
1051 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1052 | } |
1053 | ||
b6cb9035 | 1054 | static void |
61a1198a | 1055 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1056 | { |
61a1198a | 1057 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
930bd0e0 KB |
1058 | if (mips_pc_is_mips16 (pc)) |
1059 | regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc)); | |
1060 | else | |
1061 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 1062 | } |
c906108c | 1063 | |
c906108c SS |
1064 | /* Fetch and return instruction from the specified location. If the PC |
1065 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
1066 | ||
d37cca3d | 1067 | static ULONGEST |
e17a4113 | 1068 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 1069 | { |
e17a4113 | 1070 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1071 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1072 | int instlen; |
1073 | int status; | |
1074 | ||
0fe7e7c8 | 1075 | if (mips_pc_is_mips16 (addr)) |
c906108c | 1076 | { |
95ac2dcf | 1077 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 1078 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1079 | } |
1080 | else | |
95ac2dcf | 1081 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 1082 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
1083 | if (status) |
1084 | memory_error (status, addr); | |
e17a4113 | 1085 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1086 | } |
1087 | ||
025bb325 | 1088 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1089 | #define mips32_op(x) (x >> 26) |
1090 | #define itype_op(x) (x >> 26) | |
1091 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1092 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1093 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1094 | |
e135b889 DJ |
1095 | #define jtype_op(x) (x >> 26) |
1096 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1097 | |
e135b889 DJ |
1098 | #define rtype_op(x) (x >> 26) |
1099 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1100 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1101 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1102 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1103 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1104 | |
06987e64 MK |
1105 | static LONGEST |
1106 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1107 | { |
06987e64 | 1108 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1109 | } |
1110 | ||
f49e4e6d MS |
1111 | /* Determine where to set a single step breakpoint while considering |
1112 | branch prediction. */ | |
5a89d8aa | 1113 | static CORE_ADDR |
0b1b3e42 | 1114 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1115 | { |
e17a4113 | 1116 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1117 | unsigned long inst; |
1118 | int op; | |
e17a4113 | 1119 | inst = mips_fetch_instruction (gdbarch, pc); |
025bb325 MS |
1120 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1121 | instruction. */ | |
c5aa993b | 1122 | { |
e135b889 | 1123 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1124 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1125 | { |
e135b889 | 1126 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1127 | switch (op) |
1128 | { | |
e135b889 DJ |
1129 | case 0: /* BEQL */ |
1130 | goto equal_branch; | |
1131 | case 1: /* BNEL */ | |
1132 | goto neq_branch; | |
1133 | case 2: /* BLEZL */ | |
1134 | goto less_branch; | |
313628cc | 1135 | case 3: /* BGTZL */ |
e135b889 | 1136 | goto greater_branch; |
c5aa993b JM |
1137 | default: |
1138 | pc += 4; | |
c906108c SS |
1139 | } |
1140 | } | |
e135b889 | 1141 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1142 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1143 | { |
1144 | int tf = itype_rt (inst) & 0x01; | |
1145 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 1146 | int fcrcs = |
72a155b4 UW |
1147 | get_frame_register_signed (frame, |
1148 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 1149 | fp_control_status); |
e135b889 DJ |
1150 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1151 | ||
1152 | if (((cond >> cnum) & 0x01) == tf) | |
1153 | pc += mips32_relative_offset (inst) + 4; | |
1154 | else | |
1155 | pc += 8; | |
1156 | } | |
c5aa993b | 1157 | else |
025bb325 | 1158 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1159 | } |
1160 | else | |
025bb325 | 1161 | { /* This gets way messy. */ |
c5aa993b | 1162 | |
025bb325 MS |
1163 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
1164 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | |
c906108c | 1165 | { |
c5aa993b JM |
1166 | case 0: /* SPECIAL */ |
1167 | op = rtype_funct (inst); | |
1168 | switch (op) | |
1169 | { | |
1170 | case 8: /* JR */ | |
1171 | case 9: /* JALR */ | |
025bb325 | 1172 | /* Set PC to that address. */ |
0b1b3e42 | 1173 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1174 | break; |
e38d4e1a DJ |
1175 | case 12: /* SYSCALL */ |
1176 | { | |
1177 | struct gdbarch_tdep *tdep; | |
1178 | ||
1179 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1180 | if (tdep->syscall_next_pc != NULL) | |
1181 | pc = tdep->syscall_next_pc (frame); | |
1182 | else | |
1183 | pc += 4; | |
1184 | } | |
1185 | break; | |
c5aa993b JM |
1186 | default: |
1187 | pc += 4; | |
1188 | } | |
1189 | ||
6d82d43b | 1190 | break; /* end SPECIAL */ |
025bb325 | 1191 | case 1: /* REGIMM */ |
c906108c | 1192 | { |
e135b889 DJ |
1193 | op = itype_rt (inst); /* branch condition */ |
1194 | switch (op) | |
c906108c | 1195 | { |
c5aa993b | 1196 | case 0: /* BLTZ */ |
e135b889 DJ |
1197 | case 2: /* BLTZL */ |
1198 | case 16: /* BLTZAL */ | |
c5aa993b | 1199 | case 18: /* BLTZALL */ |
c906108c | 1200 | less_branch: |
0b1b3e42 | 1201 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1202 | pc += mips32_relative_offset (inst) + 4; |
1203 | else | |
1204 | pc += 8; /* after the delay slot */ | |
1205 | break; | |
e135b889 | 1206 | case 1: /* BGEZ */ |
c5aa993b JM |
1207 | case 3: /* BGEZL */ |
1208 | case 17: /* BGEZAL */ | |
1209 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1210 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1211 | pc += mips32_relative_offset (inst) + 4; |
1212 | else | |
1213 | pc += 8; /* after the delay slot */ | |
1214 | break; | |
e135b889 | 1215 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1216 | default: |
1217 | pc += 4; | |
c906108c SS |
1218 | } |
1219 | } | |
6d82d43b | 1220 | break; /* end REGIMM */ |
c5aa993b JM |
1221 | case 2: /* J */ |
1222 | case 3: /* JAL */ | |
1223 | { | |
1224 | unsigned long reg; | |
1225 | reg = jtype_target (inst) << 2; | |
025bb325 | 1226 | /* Upper four bits get never changed... */ |
5b652102 | 1227 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1228 | } |
c5aa993b JM |
1229 | break; |
1230 | /* FIXME case JALX : */ | |
1231 | { | |
1232 | unsigned long reg; | |
1233 | reg = jtype_target (inst) << 2; | |
025bb325 | 1234 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1235 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1236 | } | |
c5aa993b | 1237 | break; /* The new PC will be alternate mode */ |
e135b889 | 1238 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1239 | equal_branch: |
0b1b3e42 UW |
1240 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1241 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1242 | pc += mips32_relative_offset (inst) + 4; |
1243 | else | |
1244 | pc += 8; | |
1245 | break; | |
e135b889 | 1246 | case 5: /* BNE, BNEL */ |
c5aa993b | 1247 | neq_branch: |
0b1b3e42 UW |
1248 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1249 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1250 | pc += mips32_relative_offset (inst) + 4; |
1251 | else | |
1252 | pc += 8; | |
1253 | break; | |
e135b889 | 1254 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1255 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1256 | pc += mips32_relative_offset (inst) + 4; |
1257 | else | |
1258 | pc += 8; | |
1259 | break; | |
1260 | case 7: | |
e135b889 DJ |
1261 | default: |
1262 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1263 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1264 | pc += mips32_relative_offset (inst) + 4; |
1265 | else | |
1266 | pc += 8; | |
1267 | break; | |
c5aa993b JM |
1268 | } /* switch */ |
1269 | } /* else */ | |
1270 | return pc; | |
1271 | } /* mips32_next_pc */ | |
c906108c SS |
1272 | |
1273 | /* Decoding the next place to set a breakpoint is irregular for the | |
025bb325 MS |
1274 | mips 16 variant, but fortunately, there fewer instructions. We have |
1275 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1276 | 32 bit instructions. We dont want to set a single step instruction | |
1277 | on the extend instruction either. */ | |
c906108c SS |
1278 | |
1279 | /* Lots of mips16 instruction formats */ | |
1280 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1281 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1282 | enum mips16_inst_fmts |
1283 | { | |
c5aa993b JM |
1284 | itype, /* 0 immediate 5,10 */ |
1285 | ritype, /* 1 5,3,8 */ | |
1286 | rrtype, /* 2 5,3,3,5 */ | |
1287 | rritype, /* 3 5,3,3,5 */ | |
1288 | rrrtype, /* 4 5,3,3,3,2 */ | |
1289 | rriatype, /* 5 5,3,3,1,4 */ | |
1290 | shifttype, /* 6 5,3,3,3,2 */ | |
1291 | i8type, /* 7 5,3,8 */ | |
1292 | i8movtype, /* 8 5,3,3,5 */ | |
1293 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1294 | i64type, /* 10 5,3,8 */ | |
1295 | ri64type, /* 11 5,3,3,5 */ | |
1296 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1297 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1298 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1299 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1300 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1301 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1302 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1303 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1304 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1305 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1306 | }; | |
12f02c2a | 1307 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 1308 | then, only the fields which are involved in instruction extension. */ |
c906108c | 1309 | struct upk_mips16 |
6d82d43b AC |
1310 | { |
1311 | CORE_ADDR offset; | |
025bb325 | 1312 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
1313 | unsigned int regy; |
1314 | }; | |
c906108c SS |
1315 | |
1316 | ||
12f02c2a | 1317 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1318 | for the bits which make up the immediate extension. */ |
c906108c | 1319 | |
12f02c2a AC |
1320 | static CORE_ADDR |
1321 | extended_offset (unsigned int extension) | |
c906108c | 1322 | { |
12f02c2a | 1323 | CORE_ADDR value; |
130854df MR |
1324 | |
1325 | value = (extension >> 21) & 0x3f; /* Extract 15:11. */ | |
c5aa993b | 1326 | value = value << 6; |
130854df | 1327 | value |= (extension >> 16) & 0x1f; /* Extract 10:5. */ |
c5aa993b | 1328 | value = value << 5; |
130854df MR |
1329 | value |= extension & 0x1f; /* Extract 4:0. */ |
1330 | ||
c5aa993b | 1331 | return value; |
c906108c SS |
1332 | } |
1333 | ||
1334 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1335 | instruction. It won't malfunction, but why make excess remote memory |
1336 | references? If the immediate operands get sign extended or something, | |
1337 | do it after the extension is performed. */ | |
c906108c | 1338 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1339 | when the offset is to be used in relative addressing. */ |
c906108c | 1340 | |
12f02c2a | 1341 | static unsigned int |
e17a4113 | 1342 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1343 | { |
e17a4113 | 1344 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1345 | gdb_byte buf[8]; |
025bb325 | 1346 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
c5aa993b | 1347 | target_read_memory (pc, buf, 2); |
e17a4113 | 1348 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1349 | } |
1350 | ||
1351 | static void | |
e17a4113 | 1352 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1353 | unsigned int extension, |
1354 | unsigned int inst, | |
6d82d43b | 1355 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1356 | { |
12f02c2a AC |
1357 | CORE_ADDR offset; |
1358 | int regx; | |
1359 | int regy; | |
1360 | switch (insn_format) | |
c906108c | 1361 | { |
c5aa993b | 1362 | case itype: |
c906108c | 1363 | { |
12f02c2a AC |
1364 | CORE_ADDR value; |
1365 | if (extension) | |
c5aa993b JM |
1366 | { |
1367 | value = extended_offset (extension); | |
1368 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1369 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1370 | } |
1371 | else | |
c5aa993b | 1372 | { |
12f02c2a | 1373 | value = inst & 0x7ff; |
025bb325 | 1374 | /* FIXME : Consider sign extension. */ |
c906108c | 1375 | } |
12f02c2a AC |
1376 | offset = value; |
1377 | regx = -1; | |
1378 | regy = -1; | |
c906108c | 1379 | } |
c5aa993b JM |
1380 | break; |
1381 | case ritype: | |
1382 | case i8type: | |
025bb325 | 1383 | { /* A register identifier and an offset. */ |
c906108c | 1384 | /* Most of the fields are the same as I type but the |
025bb325 | 1385 | immediate value is of a different length. */ |
12f02c2a AC |
1386 | CORE_ADDR value; |
1387 | if (extension) | |
c906108c | 1388 | { |
c5aa993b | 1389 | value = extended_offset (extension); |
025bb325 | 1390 | value = value << 8; /* from the original instruction */ |
12f02c2a AC |
1391 | value |= inst & 0xff; /* eleven bits from instruction */ |
1392 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
025bb325 | 1393 | if (value & 0x4000) /* Test the sign bit, bit 26. */ |
c5aa993b | 1394 | { |
025bb325 | 1395 | value &= ~0x3fff; /* Remove the sign bit. */ |
c5aa993b | 1396 | value = -value; |
c906108c SS |
1397 | } |
1398 | } | |
c5aa993b JM |
1399 | else |
1400 | { | |
12f02c2a AC |
1401 | value = inst & 0xff; /* 8 bits */ |
1402 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
025bb325 MS |
1403 | /* FIXME: Do sign extension, this format needs it. */ |
1404 | if (value & 0x80) /* THIS CONFUSES ME. */ | |
c5aa993b | 1405 | { |
025bb325 | 1406 | value &= 0xef; /* Remove the sign bit. */ |
c5aa993b JM |
1407 | value = -value; |
1408 | } | |
c5aa993b | 1409 | } |
12f02c2a AC |
1410 | offset = value; |
1411 | regy = -1; | |
c5aa993b | 1412 | break; |
c906108c | 1413 | } |
c5aa993b | 1414 | case jalxtype: |
c906108c | 1415 | { |
c5aa993b | 1416 | unsigned long value; |
12f02c2a AC |
1417 | unsigned int nexthalf; |
1418 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1419 | value = value << 16; |
025bb325 MS |
1420 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit |
1421 | still set. */ | |
c5aa993b | 1422 | value |= nexthalf; |
12f02c2a AC |
1423 | offset = value; |
1424 | regx = -1; | |
1425 | regy = -1; | |
c5aa993b | 1426 | break; |
c906108c SS |
1427 | } |
1428 | default: | |
e2e0b3e5 | 1429 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1430 | } |
12f02c2a AC |
1431 | upk->offset = offset; |
1432 | upk->regx = regx; | |
1433 | upk->regy = regy; | |
c906108c SS |
1434 | } |
1435 | ||
1436 | ||
c5aa993b JM |
1437 | static CORE_ADDR |
1438 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1439 | { |
5b652102 | 1440 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1441 | } |
1442 | ||
12f02c2a | 1443 | static CORE_ADDR |
0b1b3e42 | 1444 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1445 | unsigned int extension, unsigned int insn) |
c906108c | 1446 | { |
e17a4113 | 1447 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1448 | int op = (insn >> 11); |
1449 | switch (op) | |
c906108c | 1450 | { |
6d82d43b | 1451 | case 2: /* Branch */ |
12f02c2a AC |
1452 | { |
1453 | CORE_ADDR offset; | |
1454 | struct upk_mips16 upk; | |
e17a4113 | 1455 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
12f02c2a AC |
1456 | offset = upk.offset; |
1457 | if (offset & 0x800) | |
1458 | { | |
1459 | offset &= 0xeff; | |
1460 | offset = -offset; | |
1461 | } | |
1462 | pc += (offset << 1) + 2; | |
1463 | break; | |
1464 | } | |
025bb325 MS |
1465 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
1466 | instructions. */ | |
12f02c2a AC |
1467 | { |
1468 | struct upk_mips16 upk; | |
e17a4113 | 1469 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1470 | pc = add_offset_16 (pc, upk.offset); |
1471 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 1472 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
1473 | else |
1474 | pc |= 0x01; | |
1475 | break; | |
1476 | } | |
6d82d43b | 1477 | case 4: /* beqz */ |
12f02c2a AC |
1478 | { |
1479 | struct upk_mips16 upk; | |
1480 | int reg; | |
e17a4113 | 1481 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1482 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1483 | if (reg == 0) |
1484 | pc += (upk.offset << 1) + 2; | |
1485 | else | |
1486 | pc += 2; | |
1487 | break; | |
1488 | } | |
6d82d43b | 1489 | case 5: /* bnez */ |
12f02c2a AC |
1490 | { |
1491 | struct upk_mips16 upk; | |
1492 | int reg; | |
e17a4113 | 1493 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1494 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1495 | if (reg != 0) |
1496 | pc += (upk.offset << 1) + 2; | |
1497 | else | |
1498 | pc += 2; | |
1499 | break; | |
1500 | } | |
6d82d43b | 1501 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1502 | { |
1503 | struct upk_mips16 upk; | |
1504 | int reg; | |
e17a4113 | 1505 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1506 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1507 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1508 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1509 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1510 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1511 | pc += (upk.offset << 1) + 2; | |
1512 | else | |
1513 | pc += 2; | |
1514 | break; | |
1515 | } | |
6d82d43b | 1516 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1517 | { |
1518 | struct upk_mips16 upk; | |
1519 | /* upk.fmt = rrtype; */ | |
1520 | op = insn & 0x1f; | |
1521 | if (op == 0) | |
c5aa993b | 1522 | { |
12f02c2a AC |
1523 | int reg; |
1524 | upk.regx = (insn >> 8) & 0x07; | |
1525 | upk.regy = (insn >> 5) & 0x07; | |
1526 | switch (upk.regy) | |
c5aa993b | 1527 | { |
12f02c2a AC |
1528 | case 0: |
1529 | reg = upk.regx; | |
1530 | break; | |
1531 | case 1: | |
1532 | reg = 31; | |
025bb325 | 1533 | break; /* Function return instruction. */ |
12f02c2a AC |
1534 | case 2: |
1535 | reg = upk.regx; | |
1536 | break; | |
1537 | default: | |
1538 | reg = 31; | |
6d82d43b | 1539 | break; /* BOGUS Guess */ |
c906108c | 1540 | } |
0b1b3e42 | 1541 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1542 | } |
12f02c2a | 1543 | else |
c5aa993b | 1544 | pc += 2; |
12f02c2a AC |
1545 | break; |
1546 | } | |
1547 | case 30: | |
1548 | /* This is an instruction extension. Fetch the real instruction | |
1549 | (which follows the extension) and decode things based on | |
025bb325 | 1550 | that. */ |
12f02c2a AC |
1551 | { |
1552 | pc += 2; | |
e17a4113 UW |
1553 | pc = extended_mips16_next_pc (frame, pc, insn, |
1554 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1555 | break; |
1556 | } | |
1557 | default: | |
1558 | { | |
1559 | pc += 2; | |
1560 | break; | |
1561 | } | |
c906108c | 1562 | } |
c5aa993b | 1563 | return pc; |
12f02c2a | 1564 | } |
c906108c | 1565 | |
5a89d8aa | 1566 | static CORE_ADDR |
0b1b3e42 | 1567 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1568 | { |
e17a4113 UW |
1569 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1570 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1571 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1572 | } |
1573 | ||
1574 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1575 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 1576 | It works by decoding the current instruction and predicting where a |
025bb325 | 1577 | branch will go. This isnt hard because all the data is available. |
ce1f96de | 1578 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1579 | static CORE_ADDR |
0b1b3e42 | 1580 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1581 | { |
ce1f96de | 1582 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1583 | return mips16_next_pc (frame, pc); |
c5aa993b | 1584 | else |
0b1b3e42 | 1585 | return mips32_next_pc (frame, pc); |
12f02c2a | 1586 | } |
c906108c | 1587 | |
edfae063 AC |
1588 | struct mips_frame_cache |
1589 | { | |
1590 | CORE_ADDR base; | |
1591 | struct trad_frame_saved_reg *saved_regs; | |
1592 | }; | |
1593 | ||
29639122 JB |
1594 | /* Set a register's saved stack address in temp_saved_regs. If an |
1595 | address has already been set for this register, do nothing; this | |
1596 | way we will only recognize the first save of a given register in a | |
1597 | function prologue. | |
eec63939 | 1598 | |
f57d151a UW |
1599 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1600 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1601 | Strictly speaking, only the second range is used as it is only second | |
1602 | range (the ABI instead of ISA registers) that comes into play when finding | |
1603 | saved registers in a frame. */ | |
eec63939 AC |
1604 | |
1605 | static void | |
74ed0bb4 MD |
1606 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1607 | int regnum, CORE_ADDR offset) | |
eec63939 | 1608 | { |
29639122 JB |
1609 | if (this_cache != NULL |
1610 | && this_cache->saved_regs[regnum].addr == -1) | |
1611 | { | |
74ed0bb4 MD |
1612 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1613 | = offset; | |
1614 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1615 | = offset; | |
29639122 | 1616 | } |
eec63939 AC |
1617 | } |
1618 | ||
eec63939 | 1619 | |
29639122 JB |
1620 | /* Fetch the immediate value from a MIPS16 instruction. |
1621 | If the previous instruction was an EXTEND, use it to extend | |
1622 | the upper bits of the immediate value. This is a helper function | |
1623 | for mips16_scan_prologue. */ | |
eec63939 | 1624 | |
29639122 JB |
1625 | static int |
1626 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1627 | unsigned short inst, /* current instruction */ | |
1628 | int nbits, /* number of bits in imm field */ | |
1629 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 1630 | int is_signed) /* is the imm field signed? */ |
eec63939 | 1631 | { |
29639122 | 1632 | int offset; |
eec63939 | 1633 | |
29639122 JB |
1634 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1635 | { | |
1636 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1637 | if (offset & 0x8000) /* check for negative extend */ | |
1638 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1639 | return offset | (inst & 0x1f); | |
1640 | } | |
eec63939 | 1641 | else |
29639122 JB |
1642 | { |
1643 | int max_imm = 1 << nbits; | |
1644 | int mask = max_imm - 1; | |
1645 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1646 | |
29639122 JB |
1647 | offset = inst & mask; |
1648 | if (is_signed && (offset & sign_bit)) | |
1649 | offset = 0 - (max_imm - offset); | |
1650 | return offset * scale; | |
1651 | } | |
1652 | } | |
eec63939 | 1653 | |
65596487 | 1654 | |
29639122 JB |
1655 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1656 | the associated FRAME_CACHE if not null. | |
1657 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1658 | |
29639122 | 1659 | static CORE_ADDR |
e17a4113 UW |
1660 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1661 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1662 | struct frame_info *this_frame, |
29639122 JB |
1663 | struct mips_frame_cache *this_cache) |
1664 | { | |
1665 | CORE_ADDR cur_pc; | |
025bb325 | 1666 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
1667 | CORE_ADDR sp; |
1668 | long frame_offset = 0; /* Size of stack frame. */ | |
1669 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1670 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 1671 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
1672 | unsigned inst = 0; /* current instruction */ |
1673 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1674 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1675 | int reg, offset; |
a343eb3c | 1676 | |
29639122 JB |
1677 | int extend_bytes = 0; |
1678 | int prev_extend_bytes; | |
1679 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1680 | |
29639122 | 1681 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1682 | THIS_FRAME. */ |
1683 | if (this_frame != NULL) | |
1684 | sp = get_frame_register_signed (this_frame, | |
1685 | gdbarch_num_regs (gdbarch) | |
1686 | + MIPS_SP_REGNUM); | |
29639122 JB |
1687 | else |
1688 | sp = 0; | |
eec63939 | 1689 | |
29639122 JB |
1690 | if (limit_pc > start_pc + 200) |
1691 | limit_pc = start_pc + 200; | |
eec63939 | 1692 | |
95ac2dcf | 1693 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1694 | { |
1695 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1696 | the immediate offset extension from it in mips16_get_imm. */ | |
1697 | prev_inst = inst; | |
eec63939 | 1698 | |
025bb325 | 1699 | /* Fetch and decode the instruction. */ |
e17a4113 | 1700 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1701 | |
29639122 JB |
1702 | /* Normally we ignore extend instructions. However, if it is |
1703 | not followed by a valid prologue instruction, then this | |
1704 | instruction is not part of the prologue either. We must | |
1705 | remember in this case to adjust the end_prologue_addr back | |
1706 | over the extend. */ | |
1707 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1708 | { | |
95ac2dcf | 1709 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1710 | continue; |
1711 | } | |
eec63939 | 1712 | |
29639122 JB |
1713 | prev_extend_bytes = extend_bytes; |
1714 | extend_bytes = 0; | |
eec63939 | 1715 | |
29639122 JB |
1716 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1717 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1718 | { | |
1719 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 1720 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
1721 | frame_offset -= offset; |
1722 | else | |
1723 | /* Exit loop if a positive stack adjustment is found, which | |
1724 | usually means that the stack cleanup code in the function | |
1725 | epilogue is reached. */ | |
1726 | break; | |
1727 | } | |
1728 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1729 | { | |
1730 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1731 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1732 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1733 | } |
1734 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1735 | { | |
1736 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1737 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1738 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1739 | } |
1740 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1741 | { | |
1742 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1743 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1744 | } |
1745 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1746 | { | |
1747 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1748 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1749 | } |
1750 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1751 | { | |
1752 | frame_addr = sp; | |
1753 | frame_reg = 17; | |
1754 | } | |
1755 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1756 | { | |
1757 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1758 | frame_addr = sp + offset; | |
1759 | frame_reg = 17; | |
1760 | frame_adjust = offset; | |
1761 | } | |
1762 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1763 | { | |
1764 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1765 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1766 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1767 | } |
1768 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1769 | { | |
1770 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1771 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1772 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1773 | } |
1774 | else if ((inst & 0xf81f) == 0xe809 | |
1775 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 1776 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
1777 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1778 | { | |
025bb325 | 1779 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
1780 | if (prev_extend_bytes) /* extend */ |
1781 | save_inst |= prev_inst << 16; | |
1782 | } | |
29639122 | 1783 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1784 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1785 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1786 | { | |
1787 | /* This instruction is part of the prologue, but we don't | |
1788 | need to do anything special to handle it. */ | |
1789 | } | |
1790 | else | |
1791 | { | |
1792 | /* This instruction is not an instruction typically found | |
1793 | in a prologue, so we must have reached the end of the | |
1794 | prologue. */ | |
1795 | if (end_prologue_addr == 0) | |
1796 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1797 | } | |
1798 | } | |
eec63939 | 1799 | |
29639122 JB |
1800 | /* The entry instruction is typically the first instruction in a function, |
1801 | and it stores registers at offsets relative to the value of the old SP | |
1802 | (before the prologue). But the value of the sp parameter to this | |
1803 | function is the new SP (after the prologue has been executed). So we | |
1804 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 1805 | and can calculate what the old SP must have been. */ |
29639122 JB |
1806 | if (entry_inst != 0) |
1807 | { | |
1808 | int areg_count = (entry_inst >> 8) & 7; | |
1809 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1810 | |
29639122 JB |
1811 | /* The entry instruction always subtracts 32 from the SP. */ |
1812 | frame_offset += 32; | |
1813 | ||
1814 | /* Now we can calculate what the SP must have been at the | |
1815 | start of the function prologue. */ | |
1816 | sp += frame_offset; | |
1817 | ||
1818 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1819 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1820 | { | |
74ed0bb4 | 1821 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1822 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1823 | } |
1824 | ||
1825 | /* Check if the ra register was pushed on the stack. */ | |
1826 | offset = -4; | |
1827 | if (entry_inst & 0x20) | |
1828 | { | |
74ed0bb4 | 1829 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1830 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1831 | } |
1832 | ||
1833 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1834 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1835 | { | |
74ed0bb4 | 1836 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1837 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1838 | } |
1839 | } | |
1840 | ||
2207132d MR |
1841 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1842 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1843 | size of the frame is specified as an immediate field of instruction | |
1844 | and an extended variation exists which lets additional registers and | |
1845 | frame space to be specified. The instruction always treats registers | |
1846 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1847 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1848 | { | |
1849 | static int args_table[16] = { | |
1850 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1851 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1852 | }; | |
1853 | static int astatic_table[16] = { | |
1854 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1855 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1856 | }; | |
1857 | int aregs = (save_inst >> 16) & 0xf; | |
1858 | int xsregs = (save_inst >> 24) & 0x7; | |
1859 | int args = args_table[aregs]; | |
1860 | int astatic = astatic_table[aregs]; | |
1861 | long frame_size; | |
1862 | ||
1863 | if (args < 0) | |
1864 | { | |
1865 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1866 | args = 0; | |
1867 | } | |
1868 | if (astatic < 0) | |
1869 | { | |
1870 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1871 | astatic = 0; | |
1872 | } | |
1873 | ||
1874 | /* For standard SAVE the frame size of 0 means 128. */ | |
1875 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1876 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1877 | frame_size = 16; | |
1878 | frame_size *= 8; | |
1879 | frame_offset += frame_size; | |
1880 | ||
1881 | /* Now we can calculate what the SP must have been at the | |
1882 | start of the function prologue. */ | |
1883 | sp += frame_offset; | |
1884 | ||
1885 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1886 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1887 | { | |
74ed0bb4 | 1888 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1889 | offset += mips_abi_regsize (gdbarch); |
1890 | } | |
1891 | ||
1892 | offset = -4; | |
1893 | ||
1894 | /* Check if the RA register was pushed on the stack. */ | |
1895 | if (save_inst & 0x40) | |
1896 | { | |
74ed0bb4 | 1897 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1898 | offset -= mips_abi_regsize (gdbarch); |
1899 | } | |
1900 | ||
1901 | /* Check if the S8 register was pushed on the stack. */ | |
1902 | if (xsregs > 6) | |
1903 | { | |
74ed0bb4 | 1904 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1905 | offset -= mips_abi_regsize (gdbarch); |
1906 | xsregs--; | |
1907 | } | |
1908 | /* Check if S2-S7 were pushed on the stack. */ | |
1909 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1910 | { | |
74ed0bb4 | 1911 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1912 | offset -= mips_abi_regsize (gdbarch); |
1913 | } | |
1914 | ||
1915 | /* Check if the S1 register was pushed on the stack. */ | |
1916 | if (save_inst & 0x10) | |
1917 | { | |
74ed0bb4 | 1918 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1919 | offset -= mips_abi_regsize (gdbarch); |
1920 | } | |
1921 | /* Check if the S0 register was pushed on the stack. */ | |
1922 | if (save_inst & 0x20) | |
1923 | { | |
74ed0bb4 | 1924 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1925 | offset -= mips_abi_regsize (gdbarch); |
1926 | } | |
1927 | ||
1928 | /* Check if A0-A3 were pushed on the stack. */ | |
1929 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1930 | { | |
74ed0bb4 | 1931 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1932 | offset -= mips_abi_regsize (gdbarch); |
1933 | } | |
1934 | } | |
1935 | ||
29639122 JB |
1936 | if (this_cache != NULL) |
1937 | { | |
1938 | this_cache->base = | |
b8a22b94 DJ |
1939 | (get_frame_register_signed (this_frame, |
1940 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1941 | + frame_offset - frame_adjust); |
1942 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
025bb325 | 1943 | be able to get rid of the assignment below, evetually. But it's |
29639122 | 1944 | still needed for now. */ |
72a155b4 UW |
1945 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1946 | + mips_regnum (gdbarch)->pc] | |
1947 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1948 | } |
1949 | ||
1950 | /* If we didn't reach the end of the prologue when scanning the function | |
1951 | instructions, then set end_prologue_addr to the address of the | |
1952 | instruction immediately after the last one we scanned. */ | |
1953 | if (end_prologue_addr == 0) | |
1954 | end_prologue_addr = cur_pc; | |
1955 | ||
1956 | return end_prologue_addr; | |
eec63939 AC |
1957 | } |
1958 | ||
29639122 JB |
1959 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1960 | Procedures that use the 32-bit instruction set are handled by the | |
1961 | mips_insn32 unwinder. */ | |
1962 | ||
1963 | static struct mips_frame_cache * | |
b8a22b94 | 1964 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1965 | { |
e17a4113 | 1966 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 1967 | struct mips_frame_cache *cache; |
eec63939 AC |
1968 | |
1969 | if ((*this_cache) != NULL) | |
1970 | return (*this_cache); | |
29639122 JB |
1971 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1972 | (*this_cache) = cache; | |
b8a22b94 | 1973 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1974 | |
29639122 JB |
1975 | /* Analyze the function prologue. */ |
1976 | { | |
b8a22b94 | 1977 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1978 | CORE_ADDR start_addr; |
eec63939 | 1979 | |
29639122 JB |
1980 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1981 | if (start_addr == 0) | |
e17a4113 | 1982 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
1983 | /* We can't analyze the prologue if we couldn't find the begining |
1984 | of the function. */ | |
1985 | if (start_addr == 0) | |
1986 | return cache; | |
eec63939 | 1987 | |
e17a4113 | 1988 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1989 | } |
1990 | ||
3e8c568d | 1991 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1992 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 1993 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 1994 | cache->base); |
eec63939 | 1995 | |
29639122 | 1996 | return (*this_cache); |
eec63939 AC |
1997 | } |
1998 | ||
1999 | static void | |
b8a22b94 | 2000 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2001 | struct frame_id *this_id) |
eec63939 | 2002 | { |
b8a22b94 | 2003 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2004 | this_cache); |
21327321 DJ |
2005 | /* This marks the outermost frame. */ |
2006 | if (info->base == 0) | |
2007 | return; | |
b8a22b94 | 2008 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
2009 | } |
2010 | ||
b8a22b94 DJ |
2011 | static struct value * |
2012 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2013 | void **this_cache, int regnum) | |
eec63939 | 2014 | { |
b8a22b94 | 2015 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2016 | this_cache); |
b8a22b94 DJ |
2017 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2018 | } | |
2019 | ||
2020 | static int | |
2021 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2022 | struct frame_info *this_frame, void **this_cache) | |
2023 | { | |
2024 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2025 | if (mips_pc_is_mips16 (pc)) | |
2026 | return 1; | |
2027 | return 0; | |
eec63939 AC |
2028 | } |
2029 | ||
29639122 | 2030 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
2031 | { |
2032 | NORMAL_FRAME, | |
8fbca658 | 2033 | default_frame_unwind_stop_reason, |
29639122 | 2034 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
2035 | mips_insn16_frame_prev_register, |
2036 | NULL, | |
2037 | mips_insn16_frame_sniffer | |
eec63939 AC |
2038 | }; |
2039 | ||
eec63939 | 2040 | static CORE_ADDR |
b8a22b94 | 2041 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 2042 | void **this_cache) |
eec63939 | 2043 | { |
b8a22b94 | 2044 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
2045 | this_cache); |
2046 | return info->base; | |
eec63939 AC |
2047 | } |
2048 | ||
29639122 | 2049 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2050 | { |
29639122 JB |
2051 | &mips_insn16_frame_unwind, |
2052 | mips_insn16_frame_base_address, | |
2053 | mips_insn16_frame_base_address, | |
2054 | mips_insn16_frame_base_address | |
eec63939 AC |
2055 | }; |
2056 | ||
2057 | static const struct frame_base * | |
b8a22b94 | 2058 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 2059 | { |
b8a22b94 DJ |
2060 | CORE_ADDR pc = get_frame_pc (this_frame); |
2061 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 2062 | return &mips_insn16_frame_base; |
eec63939 AC |
2063 | else |
2064 | return NULL; | |
edfae063 AC |
2065 | } |
2066 | ||
29639122 JB |
2067 | /* Mark all the registers as unset in the saved_regs array |
2068 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
2069 | ||
74ed0bb4 MD |
2070 | static void |
2071 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 2072 | { |
29639122 JB |
2073 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
2074 | return; | |
2075 | ||
2076 | { | |
74ed0bb4 | 2077 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 2078 | int i; |
64159455 | 2079 | |
29639122 JB |
2080 | for (i = 0; i < num_regs; i++) |
2081 | { | |
2082 | this_cache->saved_regs[i].addr = -1; | |
2083 | } | |
2084 | } | |
c906108c SS |
2085 | } |
2086 | ||
025bb325 | 2087 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
2088 | the associated FRAME_CACHE if not null. |
2089 | Return the address of the first instruction past the prologue. */ | |
c906108c | 2090 | |
875e1767 | 2091 | static CORE_ADDR |
e17a4113 UW |
2092 | mips32_scan_prologue (struct gdbarch *gdbarch, |
2093 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2094 | struct frame_info *this_frame, |
29639122 | 2095 | struct mips_frame_cache *this_cache) |
c906108c | 2096 | { |
29639122 | 2097 | CORE_ADDR cur_pc; |
025bb325 MS |
2098 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
2099 | frame-pointer. */ | |
29639122 JB |
2100 | CORE_ADDR sp; |
2101 | long frame_offset; | |
2102 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2103 | |
29639122 JB |
2104 | CORE_ADDR end_prologue_addr = 0; |
2105 | int seen_sp_adjust = 0; | |
2106 | int load_immediate_bytes = 0; | |
db5f024e | 2107 | int in_delay_slot = 0; |
7d1e6fb8 | 2108 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 2109 | |
29639122 | 2110 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2111 | THIS_FRAME. */ |
2112 | if (this_frame != NULL) | |
2113 | sp = get_frame_register_signed (this_frame, | |
2114 | gdbarch_num_regs (gdbarch) | |
2115 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2116 | else |
29639122 | 2117 | sp = 0; |
9022177c | 2118 | |
29639122 JB |
2119 | if (limit_pc > start_pc + 200) |
2120 | limit_pc = start_pc + 200; | |
9022177c | 2121 | |
29639122 | 2122 | restart: |
9022177c | 2123 | |
29639122 | 2124 | frame_offset = 0; |
95ac2dcf | 2125 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 2126 | { |
29639122 JB |
2127 | unsigned long inst, high_word, low_word; |
2128 | int reg; | |
9022177c | 2129 | |
025bb325 | 2130 | /* Fetch the instruction. */ |
e17a4113 | 2131 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 2132 | |
29639122 JB |
2133 | /* Save some code by pre-extracting some useful fields. */ |
2134 | high_word = (inst >> 16) & 0xffff; | |
2135 | low_word = inst & 0xffff; | |
2136 | reg = high_word & 0x1f; | |
fe29b929 | 2137 | |
025bb325 | 2138 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
2139 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2140 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2141 | { | |
025bb325 | 2142 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
2143 | frame_offset += 0x10000 - low_word; |
2144 | else | |
2145 | /* Exit loop if a positive stack adjustment is found, which | |
2146 | usually means that the stack cleanup code in the function | |
2147 | epilogue is reached. */ | |
2148 | break; | |
2149 | seen_sp_adjust = 1; | |
2150 | } | |
7d1e6fb8 KB |
2151 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
2152 | && !regsize_is_64_bits) | |
29639122 | 2153 | { |
74ed0bb4 | 2154 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 2155 | } |
7d1e6fb8 KB |
2156 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
2157 | && regsize_is_64_bits) | |
29639122 JB |
2158 | { |
2159 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 2160 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
2161 | } |
2162 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2163 | { | |
2164 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2165 | if ((long) low_word != frame_offset) | |
2166 | frame_addr = sp + low_word; | |
b8a22b94 | 2167 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2168 | { |
2169 | unsigned alloca_adjust; | |
a4b8ebc8 | 2170 | |
29639122 | 2171 | frame_reg = 30; |
b8a22b94 DJ |
2172 | frame_addr = get_frame_register_signed |
2173 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2174 | |
29639122 JB |
2175 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
2176 | if (alloca_adjust > 0) | |
2177 | { | |
025bb325 | 2178 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2179 | an alloca or somethings similar. Fix sp to |
2180 | "pre-alloca" value, and try again. */ | |
2181 | sp += alloca_adjust; | |
2182 | /* Need to reset the status of all registers. Otherwise, | |
2183 | we will hit a guard that prevents the new address | |
2184 | for each register to be recomputed during the second | |
2185 | pass. */ | |
74ed0bb4 | 2186 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2187 | goto restart; |
2188 | } | |
2189 | } | |
2190 | } | |
2191 | /* move $30,$sp. With different versions of gas this will be either | |
2192 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2193 | Accept any one of these. */ | |
2194 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2195 | { | |
2196 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2197 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2198 | { |
2199 | unsigned alloca_adjust; | |
c906108c | 2200 | |
29639122 | 2201 | frame_reg = 30; |
b8a22b94 DJ |
2202 | frame_addr = get_frame_register_signed |
2203 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2204 | |
29639122 JB |
2205 | alloca_adjust = (unsigned) (frame_addr - sp); |
2206 | if (alloca_adjust > 0) | |
2207 | { | |
025bb325 | 2208 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2209 | an alloca or somethings similar. Fix sp to |
2210 | "pre-alloca" value, and try again. */ | |
2211 | sp = frame_addr; | |
2212 | /* Need to reset the status of all registers. Otherwise, | |
2213 | we will hit a guard that prevents the new address | |
2214 | for each register to be recomputed during the second | |
2215 | pass. */ | |
74ed0bb4 | 2216 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2217 | goto restart; |
2218 | } | |
2219 | } | |
2220 | } | |
7d1e6fb8 KB |
2221 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2222 | && !regsize_is_64_bits) | |
29639122 | 2223 | { |
74ed0bb4 | 2224 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2225 | } |
2226 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2227 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2228 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2229 | || high_word == 0x3c1c /* lui $gp,n */ | |
2230 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2231 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2232 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2233 | ) | |
2234 | { | |
2235 | /* These instructions are part of the prologue, but we don't | |
2236 | need to do anything special to handle them. */ | |
2237 | } | |
2238 | /* The instructions below load $at or $t0 with an immediate | |
2239 | value in preparation for a stack adjustment via | |
025bb325 | 2240 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
2241 | initialize a local variable, so we accept them only before |
2242 | a stack adjustment instruction was seen. */ | |
2243 | else if (!seen_sp_adjust | |
2244 | && (high_word == 0x3c01 /* lui $at,n */ | |
2245 | || high_word == 0x3c08 /* lui $t0,n */ | |
2246 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2247 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2248 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2249 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2250 | )) | |
2251 | { | |
95ac2dcf | 2252 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2253 | } |
2254 | else | |
2255 | { | |
2256 | /* This instruction is not an instruction typically found | |
2257 | in a prologue, so we must have reached the end of the | |
2258 | prologue. */ | |
2259 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2260 | loop now? Why would we need to continue scanning the function | |
2261 | instructions? */ | |
2262 | if (end_prologue_addr == 0) | |
2263 | end_prologue_addr = cur_pc; | |
db5f024e DJ |
2264 | |
2265 | /* Check for branches and jumps. For now, only jump to | |
2266 | register are caught (i.e. returns). */ | |
2267 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2268 | in_delay_slot = 1; | |
29639122 | 2269 | } |
db5f024e DJ |
2270 | |
2271 | /* If the previous instruction was a jump, we must have reached | |
2272 | the end of the prologue by now. Stop scanning so that we do | |
2273 | not go past the function return. */ | |
2274 | if (in_delay_slot) | |
2275 | break; | |
a4b8ebc8 | 2276 | } |
c906108c | 2277 | |
29639122 JB |
2278 | if (this_cache != NULL) |
2279 | { | |
2280 | this_cache->base = | |
b8a22b94 DJ |
2281 | (get_frame_register_signed (this_frame, |
2282 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2283 | + frame_offset); |
2284 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2285 | this assignment below, eventually. But it's still needed | |
2286 | for now. */ | |
72a155b4 UW |
2287 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2288 | + mips_regnum (gdbarch)->pc] | |
2289 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2290 | + MIPS_RA_REGNUM]; |
29639122 | 2291 | } |
c906108c | 2292 | |
29639122 JB |
2293 | /* If we didn't reach the end of the prologue when scanning the function |
2294 | instructions, then set end_prologue_addr to the address of the | |
2295 | instruction immediately after the last one we scanned. */ | |
2296 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2297 | we may as well be careful and do our best if we have a null | |
2298 | end_prologue_addr. */ | |
2299 | if (end_prologue_addr == 0) | |
2300 | end_prologue_addr = cur_pc; | |
2301 | ||
2302 | /* In a frameless function, we might have incorrectly | |
025bb325 | 2303 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
2304 | if the load immediate was not followed by a stack adjustment. */ |
2305 | if (load_immediate_bytes && !seen_sp_adjust) | |
2306 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2307 | |
29639122 | 2308 | return end_prologue_addr; |
c906108c SS |
2309 | } |
2310 | ||
29639122 JB |
2311 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2312 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2313 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2314 | unwinder. */ | |
c906108c | 2315 | |
29639122 | 2316 | static struct mips_frame_cache * |
b8a22b94 | 2317 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2318 | { |
e17a4113 | 2319 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2320 | struct mips_frame_cache *cache; |
c906108c | 2321 | |
29639122 JB |
2322 | if ((*this_cache) != NULL) |
2323 | return (*this_cache); | |
c5aa993b | 2324 | |
29639122 JB |
2325 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2326 | (*this_cache) = cache; | |
b8a22b94 | 2327 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2328 | |
29639122 JB |
2329 | /* Analyze the function prologue. */ |
2330 | { | |
b8a22b94 | 2331 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2332 | CORE_ADDR start_addr; |
c906108c | 2333 | |
29639122 JB |
2334 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2335 | if (start_addr == 0) | |
e17a4113 | 2336 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2337 | /* We can't analyze the prologue if we couldn't find the begining |
2338 | of the function. */ | |
2339 | if (start_addr == 0) | |
2340 | return cache; | |
c5aa993b | 2341 | |
e17a4113 | 2342 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2343 | } |
2344 | ||
3e8c568d | 2345 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2346 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2347 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2348 | cache->base); |
c5aa993b | 2349 | |
29639122 | 2350 | return (*this_cache); |
c906108c SS |
2351 | } |
2352 | ||
29639122 | 2353 | static void |
b8a22b94 | 2354 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2355 | struct frame_id *this_id) |
c906108c | 2356 | { |
b8a22b94 | 2357 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2358 | this_cache); |
21327321 DJ |
2359 | /* This marks the outermost frame. */ |
2360 | if (info->base == 0) | |
2361 | return; | |
b8a22b94 | 2362 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2363 | } |
c906108c | 2364 | |
b8a22b94 DJ |
2365 | static struct value * |
2366 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2367 | void **this_cache, int regnum) | |
29639122 | 2368 | { |
b8a22b94 | 2369 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2370 | this_cache); |
b8a22b94 DJ |
2371 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2372 | } | |
2373 | ||
2374 | static int | |
2375 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2376 | struct frame_info *this_frame, void **this_cache) | |
2377 | { | |
2378 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2379 | if (! mips_pc_is_mips16 (pc)) | |
2380 | return 1; | |
2381 | return 0; | |
c906108c SS |
2382 | } |
2383 | ||
29639122 JB |
2384 | static const struct frame_unwind mips_insn32_frame_unwind = |
2385 | { | |
2386 | NORMAL_FRAME, | |
8fbca658 | 2387 | default_frame_unwind_stop_reason, |
29639122 | 2388 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
2389 | mips_insn32_frame_prev_register, |
2390 | NULL, | |
2391 | mips_insn32_frame_sniffer | |
29639122 | 2392 | }; |
c906108c | 2393 | |
1c645fec | 2394 | static CORE_ADDR |
b8a22b94 | 2395 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2396 | void **this_cache) |
c906108c | 2397 | { |
b8a22b94 | 2398 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2399 | this_cache); |
2400 | return info->base; | |
2401 | } | |
c906108c | 2402 | |
29639122 JB |
2403 | static const struct frame_base mips_insn32_frame_base = |
2404 | { | |
2405 | &mips_insn32_frame_unwind, | |
2406 | mips_insn32_frame_base_address, | |
2407 | mips_insn32_frame_base_address, | |
2408 | mips_insn32_frame_base_address | |
2409 | }; | |
1c645fec | 2410 | |
29639122 | 2411 | static const struct frame_base * |
b8a22b94 | 2412 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2413 | { |
b8a22b94 DJ |
2414 | CORE_ADDR pc = get_frame_pc (this_frame); |
2415 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2416 | return &mips_insn32_frame_base; |
a65bbe44 | 2417 | else |
29639122 JB |
2418 | return NULL; |
2419 | } | |
a65bbe44 | 2420 | |
29639122 | 2421 | static struct trad_frame_cache * |
b8a22b94 | 2422 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2423 | { |
2424 | CORE_ADDR pc; | |
2425 | CORE_ADDR start_addr; | |
2426 | CORE_ADDR stack_addr; | |
2427 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2428 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2429 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2430 | |
29639122 JB |
2431 | if ((*this_cache) != NULL) |
2432 | return (*this_cache); | |
b8a22b94 | 2433 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2434 | (*this_cache) = this_trad_cache; |
1c645fec | 2435 | |
29639122 | 2436 | /* The return address is in the link register. */ |
3e8c568d | 2437 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2438 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2439 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2440 | |
29639122 JB |
2441 | /* Frame ID, since it's a frameless / stackless function, no stack |
2442 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2443 | pc = get_frame_pc (this_frame); |
29639122 | 2444 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2445 | stack_addr = get_frame_register_signed (this_frame, |
2446 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2447 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2448 | |
29639122 JB |
2449 | /* Assume that the frame's base is the same as the |
2450 | stack-pointer. */ | |
2451 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2452 | |
29639122 JB |
2453 | return this_trad_cache; |
2454 | } | |
c906108c | 2455 | |
29639122 | 2456 | static void |
b8a22b94 | 2457 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2458 | struct frame_id *this_id) |
2459 | { | |
2460 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2461 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2462 | trad_frame_get_id (this_trad_cache, this_id); |
2463 | } | |
c906108c | 2464 | |
b8a22b94 DJ |
2465 | static struct value * |
2466 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2467 | void **this_cache, int regnum) | |
29639122 JB |
2468 | { |
2469 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2470 | = mips_stub_frame_cache (this_frame, this_cache); |
2471 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2472 | } |
c906108c | 2473 | |
b8a22b94 DJ |
2474 | static int |
2475 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2476 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2477 | { |
aa6c981f | 2478 | gdb_byte dummy[4]; |
979b38e0 | 2479 | struct obj_section *s; |
b8a22b94 | 2480 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2481 | struct minimal_symbol *msym; |
979b38e0 | 2482 | |
aa6c981f | 2483 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2484 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2485 | return 1; | |
aa6c981f | 2486 | |
29639122 | 2487 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2488 | return 1; |
979b38e0 DJ |
2489 | |
2490 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2491 | s = find_pc_section (pc); | |
2492 | ||
2493 | if (s != NULL | |
2494 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2495 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2496 | return 1; |
979b38e0 | 2497 | |
db5f024e DJ |
2498 | /* Calling a PIC function from a non-PIC function passes through a |
2499 | stub. The stub for foo is named ".pic.foo". */ | |
2500 | msym = lookup_minimal_symbol_by_pc (pc); | |
2501 | if (msym != NULL | |
2502 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2503 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2504 | return 1; | |
2505 | ||
b8a22b94 | 2506 | return 0; |
29639122 | 2507 | } |
c906108c | 2508 | |
b8a22b94 DJ |
2509 | static const struct frame_unwind mips_stub_frame_unwind = |
2510 | { | |
2511 | NORMAL_FRAME, | |
8fbca658 | 2512 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
2513 | mips_stub_frame_this_id, |
2514 | mips_stub_frame_prev_register, | |
2515 | NULL, | |
2516 | mips_stub_frame_sniffer | |
2517 | }; | |
2518 | ||
29639122 | 2519 | static CORE_ADDR |
b8a22b94 | 2520 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2521 | void **this_cache) |
2522 | { | |
2523 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2524 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2525 | return trad_frame_get_this_base (this_trad_cache); |
2526 | } | |
0fce0821 | 2527 | |
29639122 JB |
2528 | static const struct frame_base mips_stub_frame_base = |
2529 | { | |
2530 | &mips_stub_frame_unwind, | |
2531 | mips_stub_frame_base_address, | |
2532 | mips_stub_frame_base_address, | |
2533 | mips_stub_frame_base_address | |
2534 | }; | |
2535 | ||
2536 | static const struct frame_base * | |
b8a22b94 | 2537 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2538 | { |
b8a22b94 | 2539 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2540 | return &mips_stub_frame_base; |
2541 | else | |
2542 | return NULL; | |
2543 | } | |
2544 | ||
29639122 | 2545 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2546 | |
29639122 | 2547 | static CORE_ADDR |
24568a2c | 2548 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2549 | { |
24568a2c | 2550 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 KB |
2551 | |
2552 | if (is_mips16_addr (addr)) | |
2553 | addr = unmake_mips16_addr (addr); | |
2554 | ||
29639122 JB |
2555 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2556 | /* This hack is a work-around for existing boards using PMON, the | |
2557 | simulator, and any other 64-bit targets that doesn't have true | |
2558 | 64-bit addressing. On these targets, the upper 32 bits of | |
2559 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2560 | likely to have been sign extended to all 1s by instruction | |
2561 | sequences that load 32-bit addresses. For example, a typical | |
2562 | piece of code that loads an address is this: | |
65596487 | 2563 | |
29639122 JB |
2564 | lui $r2, <upper 16 bits> |
2565 | ori $r2, <lower 16 bits> | |
65596487 | 2566 | |
29639122 JB |
2567 | But the lui sign-extends the value such that the upper 32 bits |
2568 | may be all 1s. The workaround is simply to mask off these | |
2569 | bits. In the future, gcc may be changed to support true 64-bit | |
2570 | addressing, and this masking will have to be disabled. */ | |
2571 | return addr &= 0xffffffffUL; | |
2572 | else | |
2573 | return addr; | |
65596487 JB |
2574 | } |
2575 | ||
3d5f6d12 DJ |
2576 | /* Instructions used during single-stepping of atomic sequences. */ |
2577 | #define LL_OPCODE 0x30 | |
2578 | #define LLD_OPCODE 0x34 | |
2579 | #define SC_OPCODE 0x38 | |
2580 | #define SCD_OPCODE 0x3c | |
2581 | ||
2582 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2583 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2584 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2585 | the sequence. */ | |
2586 | ||
2587 | static int | |
6c95b8df PA |
2588 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2589 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
2590 | { |
2591 | CORE_ADDR breaks[2] = {-1, -1}; | |
2592 | CORE_ADDR loc = pc; | |
2593 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2594 | unsigned long insn; | |
2595 | int insn_count; | |
2596 | int index; | |
2597 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2598 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2599 | ||
2600 | if (pc & 0x01) | |
2601 | return 0; | |
2602 | ||
e17a4113 | 2603 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2604 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2605 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2606 | return 0; | |
2607 | ||
2608 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2609 | instructions. */ | |
2610 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2611 | { | |
2612 | int is_branch = 0; | |
2613 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2614 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2615 | |
2616 | /* Assume that there is at most one branch in the atomic | |
2617 | sequence. If a branch is found, put a breakpoint in its | |
2618 | destination address. */ | |
2619 | switch (itype_op (insn)) | |
2620 | { | |
2621 | case 0: /* SPECIAL */ | |
2622 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 2623 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2624 | break; |
2625 | case 1: /* REGIMM */ | |
2626 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2627 | break; | |
2628 | case 2: /* J */ | |
2629 | case 3: /* JAL */ | |
025bb325 | 2630 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2631 | case 4: /* BEQ */ |
2632 | case 5: /* BNE */ | |
2633 | case 6: /* BLEZ */ | |
2634 | case 7: /* BGTZ */ | |
2635 | case 20: /* BEQL */ | |
2636 | case 21: /* BNEL */ | |
2637 | case 22: /* BLEZL */ | |
2638 | case 23: /* BGTTL */ | |
2639 | is_branch = 1; | |
2640 | break; | |
2641 | case 17: /* COP1 */ | |
2642 | case 18: /* COP2 */ | |
2643 | case 19: /* COP3 */ | |
2644 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2645 | break; | |
2646 | } | |
2647 | if (is_branch) | |
2648 | { | |
2649 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2650 | if (last_breakpoint >= 1) | |
2651 | return 0; /* More than one branch found, fallback to the | |
2652 | standard single-step code. */ | |
2653 | breaks[1] = branch_bp; | |
2654 | last_breakpoint++; | |
2655 | } | |
2656 | ||
2657 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2658 | break; | |
2659 | } | |
2660 | ||
2661 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2662 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2663 | return 0; | |
2664 | ||
2665 | loc += MIPS_INSN32_SIZE; | |
2666 | ||
2667 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2668 | breaks[0] = loc; | |
2669 | ||
2670 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 2671 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
2672 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
2673 | last_breakpoint = 0; | |
2674 | ||
2675 | /* Effectively inserts the breakpoints. */ | |
2676 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 2677 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
2678 | |
2679 | return 1; | |
2680 | } | |
2681 | ||
29639122 JB |
2682 | /* mips_software_single_step() is called just before we want to resume |
2683 | the inferior, if we want to single-step it but there is no hardware | |
2684 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2685 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2686 | |
e6590a1b | 2687 | int |
0b1b3e42 | 2688 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2689 | { |
a6d9a66e | 2690 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2691 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 2692 | CORE_ADDR pc, next_pc; |
65596487 | 2693 | |
0b1b3e42 | 2694 | pc = get_frame_pc (frame); |
6c95b8df | 2695 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
2696 | return 1; |
2697 | ||
0b1b3e42 | 2698 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2699 | |
6c95b8df | 2700 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 2701 | return 1; |
29639122 | 2702 | } |
a65bbe44 | 2703 | |
29639122 | 2704 | /* Test whether the PC points to the return instruction at the |
025bb325 | 2705 | end of a function. */ |
65596487 | 2706 | |
29639122 | 2707 | static int |
e17a4113 | 2708 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2709 | { |
0fe7e7c8 | 2710 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2711 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2712 | generates a "jr $ra"; other times it generates code to load | |
2713 | the return address from the stack to an accessible register (such | |
2714 | as $a3), then a "jr" using that register. This second case | |
2715 | is almost impossible to distinguish from an indirect jump | |
2716 | used for switch statements, so we don't even try. */ | |
e17a4113 | 2717 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
29639122 | 2718 | else |
e17a4113 | 2719 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
29639122 | 2720 | } |
c906108c | 2721 | |
c906108c | 2722 | |
29639122 JB |
2723 | /* This fencepost looks highly suspicious to me. Removing it also |
2724 | seems suspicious as it could affect remote debugging across serial | |
2725 | lines. */ | |
c906108c | 2726 | |
29639122 | 2727 | static CORE_ADDR |
74ed0bb4 | 2728 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2729 | { |
2730 | CORE_ADDR start_pc; | |
2731 | CORE_ADDR fence; | |
2732 | int instlen; | |
2733 | int seen_adjsp = 0; | |
d6b48e9c | 2734 | struct inferior *inf; |
65596487 | 2735 | |
74ed0bb4 | 2736 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2737 | start_pc = pc; |
2738 | fence = start_pc - heuristic_fence_post; | |
2739 | if (start_pc == 0) | |
2740 | return 0; | |
65596487 | 2741 | |
29639122 JB |
2742 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2743 | fence = VM_MIN_ADDRESS; | |
65596487 | 2744 | |
95ac2dcf | 2745 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2746 | |
d6b48e9c PA |
2747 | inf = current_inferior (); |
2748 | ||
025bb325 | 2749 | /* Search back for previous return. */ |
29639122 JB |
2750 | for (start_pc -= instlen;; start_pc -= instlen) |
2751 | if (start_pc < fence) | |
2752 | { | |
2753 | /* It's not clear to me why we reach this point when | |
2754 | stop_soon, but with this test, at least we | |
2755 | don't print out warnings for every child forked (eg, on | |
2756 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 2757 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2758 | { |
2759 | static int blurb_printed = 0; | |
98b4dd94 | 2760 | |
5af949e3 UW |
2761 | warning (_("GDB can't find the start of the function at %s."), |
2762 | paddress (gdbarch, pc)); | |
29639122 JB |
2763 | |
2764 | if (!blurb_printed) | |
2765 | { | |
2766 | /* This actually happens frequently in embedded | |
2767 | development, when you first connect to a board | |
2768 | and your stack pointer and pc are nowhere in | |
2769 | particular. This message needs to give people | |
2770 | in that situation enough information to | |
2771 | determine that it's no big deal. */ | |
2772 | printf_filtered ("\n\ | |
5af949e3 | 2773 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2774 | and thus can't determine the size of that function's stack frame.\n\ |
2775 | This means that GDB may be unable to access that stack frame, or\n\ | |
2776 | the frames below it.\n\ | |
2777 | This problem is most likely caused by an invalid program counter or\n\ | |
2778 | stack pointer.\n\ | |
2779 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2780 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2781 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2782 | heuristic-fence-post' command.\n", |
2783 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2784 | blurb_printed = 1; |
2785 | } | |
2786 | } | |
2787 | ||
2788 | return 0; | |
2789 | } | |
0fe7e7c8 | 2790 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2791 | { |
2792 | unsigned short inst; | |
2793 | ||
2794 | /* On MIPS16, any one of the following is likely to be the | |
2795 | start of a function: | |
193774b3 MR |
2796 | extend save |
2797 | save | |
29639122 JB |
2798 | entry |
2799 | addiu sp,-n | |
2800 | daddiu sp,-n | |
025bb325 | 2801 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
e17a4113 | 2802 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2803 | if ((inst & 0xff80) == 0x6480) /* save */ |
2804 | { | |
2805 | if (start_pc - instlen >= fence) | |
2806 | { | |
e17a4113 | 2807 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2808 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2809 | start_pc -= instlen; | |
2810 | } | |
2811 | break; | |
2812 | } | |
2813 | else if (((inst & 0xf81f) == 0xe809 | |
2814 | && (inst & 0x700) != 0x700) /* entry */ | |
2815 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2816 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2817 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2818 | break; |
2819 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2820 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2821 | seen_adjsp = 1; | |
2822 | else | |
2823 | seen_adjsp = 0; | |
2824 | } | |
e17a4113 | 2825 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2826 | { |
4c7d22cb | 2827 | /* Skip return and its delay slot. */ |
95ac2dcf | 2828 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2829 | break; |
2830 | } | |
2831 | ||
2832 | return start_pc; | |
c906108c SS |
2833 | } |
2834 | ||
6c0d6680 DJ |
2835 | struct mips_objfile_private |
2836 | { | |
2837 | bfd_size_type size; | |
2838 | char *contents; | |
2839 | }; | |
2840 | ||
f09ded24 AC |
2841 | /* According to the current ABI, should the type be passed in a |
2842 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2843 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 2844 | FP registers and, consequently this returns false - forces FP |
025bb325 | 2845 | arguments into integer registers. */ |
f09ded24 AC |
2846 | |
2847 | static int | |
74ed0bb4 MD |
2848 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2849 | struct type *arg_type) | |
f09ded24 AC |
2850 | { |
2851 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2852 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2853 | && (typecode == TYPE_CODE_STRUCT |
2854 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2855 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2856 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2857 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2858 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2859 | } |
2860 | ||
49e790b0 | 2861 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 2862 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
2863 | |
2864 | static int | |
2865 | mips_type_needs_double_align (struct type *type) | |
2866 | { | |
2867 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2868 | |
49e790b0 DJ |
2869 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2870 | return 1; | |
2871 | else if (typecode == TYPE_CODE_STRUCT) | |
2872 | { | |
2873 | if (TYPE_NFIELDS (type) < 1) | |
2874 | return 0; | |
2875 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2876 | } | |
2877 | else if (typecode == TYPE_CODE_UNION) | |
2878 | { | |
361d1df0 | 2879 | int i, n; |
49e790b0 DJ |
2880 | |
2881 | n = TYPE_NFIELDS (type); | |
2882 | for (i = 0; i < n; i++) | |
2883 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2884 | return 1; | |
2885 | return 0; | |
2886 | } | |
2887 | return 0; | |
2888 | } | |
2889 | ||
dc604539 AC |
2890 | /* Adjust the address downward (direction of stack growth) so that it |
2891 | is correctly aligned for a new stack frame. */ | |
2892 | static CORE_ADDR | |
2893 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2894 | { | |
5b03f266 | 2895 | return align_down (addr, 16); |
dc604539 AC |
2896 | } |
2897 | ||
f7ab6ec6 | 2898 | static CORE_ADDR |
7d9b040b | 2899 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2900 | struct regcache *regcache, CORE_ADDR bp_addr, |
2901 | int nargs, struct value **args, CORE_ADDR sp, | |
2902 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2903 | { |
2904 | int argreg; | |
2905 | int float_argreg; | |
2906 | int argnum; | |
2907 | int len = 0; | |
2908 | int stack_offset = 0; | |
480d3dd2 | 2909 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 2910 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 2911 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2912 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2913 | |
25ab4790 AC |
2914 | /* For shared libraries, "t9" needs to point at the function |
2915 | address. */ | |
4c7d22cb | 2916 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2917 | |
2918 | /* Set the return address register to point to the entry point of | |
2919 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2920 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2921 | |
c906108c | 2922 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2923 | are properly aligned. The stack has to be at least 64-bit |
2924 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2925 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2926 | aligned, so we round to this widest known alignment. */ | |
2927 | ||
5b03f266 AC |
2928 | sp = align_down (sp, 16); |
2929 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2930 | |
46e0f506 | 2931 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2932 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2933 | passed in registers, but that's OK. */ |
c906108c | 2934 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2935 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2936 | sp -= align_up (len, 16); |
c906108c | 2937 | |
9ace0497 | 2938 | if (mips_debug) |
6d82d43b | 2939 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2940 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2941 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2942 | |
c906108c | 2943 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2944 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2945 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2946 | |
46e0f506 | 2947 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2948 | if (struct_return) |
9ace0497 AC |
2949 | { |
2950 | if (mips_debug) | |
2951 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
2952 | "mips_eabi_push_dummy_call: " |
2953 | "struct_return reg=%d %s\n", | |
5af949e3 | 2954 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 2955 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2956 | } |
c906108c SS |
2957 | |
2958 | /* Now load as many as possible of the first arguments into | |
2959 | registers, and push the rest onto the stack. Loop thru args | |
2960 | from first to last. */ | |
2961 | for (argnum = 0; argnum < nargs; argnum++) | |
2962 | { | |
47a35522 MK |
2963 | const gdb_byte *val; |
2964 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2965 | struct value *arg = args[argnum]; |
4991999e | 2966 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2967 | int len = TYPE_LENGTH (arg_type); |
2968 | enum type_code typecode = TYPE_CODE (arg_type); | |
2969 | ||
9ace0497 AC |
2970 | if (mips_debug) |
2971 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2972 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2973 | argnum + 1, len, (int) typecode); |
9ace0497 | 2974 | |
930bd0e0 KB |
2975 | /* Function pointer arguments to mips16 code need to be made into |
2976 | mips16 pointers. */ | |
2977 | if (typecode == TYPE_CODE_PTR | |
2978 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
2979 | { | |
2980 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
2981 | len, byte_order); | |
2982 | if (mips_pc_is_mips16 (addr)) | |
2983 | { | |
2984 | store_signed_integer (valbuf, len, byte_order, | |
2985 | make_mips16_addr (addr)); | |
2986 | val = valbuf; | |
2987 | } | |
2988 | else | |
2989 | val = value_contents (arg); | |
2990 | } | |
c906108c | 2991 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2992 | reference. */ |
930bd0e0 | 2993 | else if (len > regsize |
9ace0497 | 2994 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2995 | { |
e17a4113 UW |
2996 | store_unsigned_integer (valbuf, regsize, byte_order, |
2997 | value_address (arg)); | |
c906108c | 2998 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2999 | len = regsize; |
c906108c | 3000 | val = valbuf; |
9ace0497 AC |
3001 | if (mips_debug) |
3002 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3003 | } |
3004 | else | |
47a35522 | 3005 | val = value_contents (arg); |
c906108c SS |
3006 | |
3007 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3008 | even-numbered floating point register. Round the FP register |
3009 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3010 | left. Non MIPS_EABI targets also pass the FP in the integer |
3011 | registers so also round up normal registers. */ | |
74ed0bb4 | 3012 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
3013 | { |
3014 | if ((float_argreg & 1)) | |
3015 | float_argreg++; | |
3016 | } | |
c906108c SS |
3017 | |
3018 | /* Floating point arguments passed in registers have to be | |
3019 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3020 | are passed in register pairs; the even register gets |
3021 | the low word, and the odd register gets the high word. | |
3022 | On non-EABI processors, the first two floating point arguments are | |
3023 | also copied to general registers, because MIPS16 functions | |
3024 | don't use float registers for arguments. This duplication of | |
3025 | arguments in general registers can't hurt non-MIPS16 functions | |
3026 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3027 | /* MIPS_EABI squeezes a struct that contains a single floating |
3028 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3029 | stack. */ |
74ed0bb4 MD |
3030 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3031 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 3032 | { |
6da397e0 KB |
3033 | /* EABI32 will pass doubles in consecutive registers, even on |
3034 | 64-bit cores. At one time, we used to check the size of | |
3035 | `float_argreg' to determine whether or not to pass doubles | |
3036 | in consecutive registers, but this is not sufficient for | |
3037 | making the ABI determination. */ | |
3038 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 3039 | { |
72a155b4 | 3040 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3041 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 3042 | long regval; |
c906108c SS |
3043 | |
3044 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
3045 | regval = extract_signed_integer (val + low_offset, |
3046 | 4, byte_order); | |
9ace0497 | 3047 | if (mips_debug) |
acdb74a0 | 3048 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3049 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3050 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3051 | |
3052 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
3053 | regval = extract_signed_integer (val + 4 - low_offset, |
3054 | 4, byte_order); | |
9ace0497 | 3055 | if (mips_debug) |
acdb74a0 | 3056 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3057 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3058 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3059 | } |
3060 | else | |
3061 | { | |
3062 | /* This is a floating point value that fits entirely | |
3063 | in a single register. */ | |
53a5351d | 3064 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3065 | above to ensure that it is even register aligned. */ |
a8852dc5 | 3066 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 3067 | if (mips_debug) |
acdb74a0 | 3068 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3069 | float_argreg, phex (regval, len)); |
a8852dc5 | 3070 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3071 | } |
3072 | } | |
3073 | else | |
3074 | { | |
3075 | /* Copy the argument to general registers or the stack in | |
3076 | register-sized pieces. Large arguments are split between | |
3077 | registers and stack. */ | |
1a69e1e4 DJ |
3078 | /* Note: structs whose size is not a multiple of regsize |
3079 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3080 | them in registers where gcc sometimes puts them on the |
3081 | stack. For maximum compatibility, we will put them in | |
3082 | both places. */ | |
1a69e1e4 | 3083 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 3084 | |
f09ded24 | 3085 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3086 | register are only written to memory. */ |
c906108c SS |
3087 | while (len > 0) |
3088 | { | |
ebafbe83 | 3089 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3090 | int stack_used_p = 0; |
1a69e1e4 | 3091 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 3092 | |
acdb74a0 AC |
3093 | if (mips_debug) |
3094 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3095 | partial_len); | |
3096 | ||
566f0f7a | 3097 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3098 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 3099 | || odd_sized_struct |
74ed0bb4 | 3100 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 3101 | { |
c906108c | 3102 | /* Should shorter than int integer values be |
025bb325 | 3103 | promoted to int before being stored? */ |
c906108c | 3104 | int longword_offset = 0; |
9ace0497 | 3105 | CORE_ADDR addr; |
566f0f7a | 3106 | stack_used_p = 1; |
72a155b4 | 3107 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 3108 | { |
1a69e1e4 | 3109 | if (regsize == 8 |
480d3dd2 AC |
3110 | && (typecode == TYPE_CODE_INT |
3111 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3112 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 3113 | longword_offset = regsize - len; |
480d3dd2 AC |
3114 | else if ((typecode == TYPE_CODE_STRUCT |
3115 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
3116 | && TYPE_LENGTH (arg_type) < regsize) |
3117 | longword_offset = regsize - len; | |
7a292a7a | 3118 | } |
c5aa993b | 3119 | |
9ace0497 AC |
3120 | if (mips_debug) |
3121 | { | |
5af949e3 UW |
3122 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3123 | paddress (gdbarch, stack_offset)); | |
3124 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3125 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 3126 | } |
361d1df0 | 3127 | |
9ace0497 AC |
3128 | addr = sp + stack_offset + longword_offset; |
3129 | ||
3130 | if (mips_debug) | |
3131 | { | |
3132 | int i; | |
5af949e3 UW |
3133 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3134 | paddress (gdbarch, addr)); | |
9ace0497 AC |
3135 | for (i = 0; i < partial_len; i++) |
3136 | { | |
6d82d43b | 3137 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3138 | val[i] & 0xff); |
9ace0497 AC |
3139 | } |
3140 | } | |
3141 | write_memory (addr, val, partial_len); | |
c906108c SS |
3142 | } |
3143 | ||
f09ded24 AC |
3144 | /* Note!!! This is NOT an else clause. Odd sized |
3145 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3146 | arguments will not. */ |
566f0f7a | 3147 | /* Write this portion of the argument to a general |
6d82d43b | 3148 | purpose register. */ |
74ed0bb4 MD |
3149 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
3150 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 3151 | { |
6d82d43b | 3152 | LONGEST regval = |
a8852dc5 | 3153 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 3154 | |
9ace0497 | 3155 | if (mips_debug) |
acdb74a0 | 3156 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3157 | argreg, |
1a69e1e4 | 3158 | phex (regval, regsize)); |
a8852dc5 | 3159 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 3160 | argreg++; |
c906108c | 3161 | } |
c5aa993b | 3162 | |
c906108c SS |
3163 | len -= partial_len; |
3164 | val += partial_len; | |
3165 | ||
b021a221 MS |
3166 | /* Compute the offset into the stack at which we will |
3167 | copy the next parameter. | |
566f0f7a | 3168 | |
566f0f7a | 3169 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3170 | only needs to be adjusted when it has been used. */ |
c906108c | 3171 | |
46e0f506 | 3172 | if (stack_used_p) |
1a69e1e4 | 3173 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
3174 | } |
3175 | } | |
9ace0497 AC |
3176 | if (mips_debug) |
3177 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3178 | } |
3179 | ||
f10683bb | 3180 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3181 | |
0f71a2f6 JM |
3182 | /* Return adjusted stack pointer. */ |
3183 | return sp; | |
3184 | } | |
3185 | ||
a1f5b845 | 3186 | /* Determine the return value convention being used. */ |
6d82d43b | 3187 | |
9c8fdbfa | 3188 | static enum return_value_convention |
c055b101 | 3189 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 3190 | struct type *type, struct regcache *regcache, |
47a35522 | 3191 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3192 | { |
609ba780 JM |
3193 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3194 | int fp_return_type = 0; | |
3195 | int offset, regnum, xfer; | |
3196 | ||
9c8fdbfa AC |
3197 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3198 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
3199 | |
3200 | /* Floating point type? */ | |
3201 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3202 | { | |
3203 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
3204 | fp_return_type = 1; | |
3205 | /* Structs with a single field of float type | |
3206 | are returned in a floating point register. */ | |
3207 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3208 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3209 | && TYPE_NFIELDS (type) == 1) | |
3210 | { | |
3211 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
3212 | ||
3213 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
3214 | fp_return_type = 1; | |
3215 | } | |
3216 | } | |
3217 | ||
3218 | if (fp_return_type) | |
3219 | { | |
3220 | /* A floating-point value belongs in the least significant part | |
3221 | of FP0/FP1. */ | |
3222 | if (mips_debug) | |
3223 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3224 | regnum = mips_regnum (gdbarch)->fp0; | |
3225 | } | |
3226 | else | |
3227 | { | |
3228 | /* An integer value goes in V0/V1. */ | |
3229 | if (mips_debug) | |
3230 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3231 | regnum = MIPS_V0_REGNUM; | |
3232 | } | |
3233 | for (offset = 0; | |
3234 | offset < TYPE_LENGTH (type); | |
3235 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3236 | { | |
3237 | xfer = mips_abi_regsize (gdbarch); | |
3238 | if (offset + xfer > TYPE_LENGTH (type)) | |
3239 | xfer = TYPE_LENGTH (type) - offset; | |
3240 | mips_xfer_register (gdbarch, regcache, | |
3241 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3242 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3243 | offset); | |
3244 | } | |
3245 | ||
9c8fdbfa | 3246 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3247 | } |
3248 | ||
6d82d43b AC |
3249 | |
3250 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3251 | |
8d26208a DJ |
3252 | /* Search for a naturally aligned double at OFFSET inside a struct |
3253 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3254 | registers. */ | |
3255 | ||
3256 | static int | |
74ed0bb4 MD |
3257 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3258 | int offset) | |
8d26208a DJ |
3259 | { |
3260 | int i; | |
3261 | ||
3262 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3263 | return 0; | |
3264 | ||
74ed0bb4 | 3265 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3266 | return 0; |
3267 | ||
3268 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3269 | return 0; | |
3270 | ||
3271 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3272 | { | |
3273 | int pos; | |
3274 | struct type *field_type; | |
3275 | ||
3276 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3277 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3278 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3279 | continue; | |
3280 | ||
3281 | /* If we have gone past the offset, there is no double to pass. */ | |
3282 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3283 | if (pos > offset) | |
3284 | return 0; | |
3285 | ||
3286 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3287 | ||
3288 | /* If this field is entirely before the requested offset, go | |
3289 | on to the next one. */ | |
3290 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3291 | continue; | |
3292 | ||
3293 | /* If this is our special aligned double, we can stop. */ | |
3294 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3295 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3296 | return 1; | |
3297 | ||
3298 | /* This field starts at or before the requested offset, and | |
3299 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3300 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3301 | } |
3302 | ||
3303 | return 0; | |
3304 | } | |
3305 | ||
f7ab6ec6 | 3306 | static CORE_ADDR |
7d9b040b | 3307 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3308 | struct regcache *regcache, CORE_ADDR bp_addr, |
3309 | int nargs, struct value **args, CORE_ADDR sp, | |
3310 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3311 | { |
3312 | int argreg; | |
3313 | int float_argreg; | |
3314 | int argnum; | |
3315 | int len = 0; | |
3316 | int stack_offset = 0; | |
480d3dd2 | 3317 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3318 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3319 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3320 | |
25ab4790 AC |
3321 | /* For shared libraries, "t9" needs to point at the function |
3322 | address. */ | |
4c7d22cb | 3323 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3324 | |
3325 | /* Set the return address register to point to the entry point of | |
3326 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3327 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3328 | |
cb3d25d1 MS |
3329 | /* First ensure that the stack and structure return address (if any) |
3330 | are properly aligned. The stack has to be at least 64-bit | |
3331 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3332 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3333 | aligned, so we round to this widest known alignment. */ | |
3334 | ||
5b03f266 AC |
3335 | sp = align_down (sp, 16); |
3336 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3337 | |
3338 | /* Now make space on the stack for the args. */ | |
3339 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3340 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3341 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3342 | |
3343 | if (mips_debug) | |
6d82d43b | 3344 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3345 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3346 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3347 | |
3348 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3349 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3350 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3351 | |
46e0f506 | 3352 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3353 | if (struct_return) |
3354 | { | |
3355 | if (mips_debug) | |
3356 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3357 | "mips_n32n64_push_dummy_call: " |
3358 | "struct_return reg=%d %s\n", | |
5af949e3 | 3359 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3360 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3361 | } |
3362 | ||
3363 | /* Now load as many as possible of the first arguments into | |
3364 | registers, and push the rest onto the stack. Loop thru args | |
3365 | from first to last. */ | |
3366 | for (argnum = 0; argnum < nargs; argnum++) | |
3367 | { | |
47a35522 | 3368 | const gdb_byte *val; |
cb3d25d1 | 3369 | struct value *arg = args[argnum]; |
4991999e | 3370 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3371 | int len = TYPE_LENGTH (arg_type); |
3372 | enum type_code typecode = TYPE_CODE (arg_type); | |
3373 | ||
3374 | if (mips_debug) | |
3375 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3376 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3377 | argnum + 1, len, (int) typecode); |
3378 | ||
47a35522 | 3379 | val = value_contents (arg); |
cb3d25d1 | 3380 | |
5b68030f JM |
3381 | /* A 128-bit long double value requires an even-odd pair of |
3382 | floating-point registers. */ | |
3383 | if (len == 16 | |
3384 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3385 | && (float_argreg & 1)) | |
3386 | { | |
3387 | float_argreg++; | |
3388 | argreg++; | |
3389 | } | |
3390 | ||
74ed0bb4 MD |
3391 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3392 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3393 | { |
3394 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3395 | in a single register or a pair of registers. */ |
3396 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3397 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3398 | if (mips_debug) |
3399 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3400 | float_argreg, phex (regval, reglen)); |
8d26208a | 3401 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3402 | |
3403 | if (mips_debug) | |
3404 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3405 | argreg, phex (regval, reglen)); |
9c9acae0 | 3406 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3407 | float_argreg++; |
3408 | argreg++; | |
5b68030f JM |
3409 | if (len == 16) |
3410 | { | |
e17a4113 UW |
3411 | regval = extract_unsigned_integer (val + reglen, |
3412 | reglen, byte_order); | |
5b68030f JM |
3413 | if (mips_debug) |
3414 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3415 | float_argreg, phex (regval, reglen)); | |
3416 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3417 | ||
3418 | if (mips_debug) | |
3419 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3420 | argreg, phex (regval, reglen)); | |
3421 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3422 | float_argreg++; | |
3423 | argreg++; | |
3424 | } | |
cb3d25d1 MS |
3425 | } |
3426 | else | |
3427 | { | |
3428 | /* Copy the argument to general registers or the stack in | |
3429 | register-sized pieces. Large arguments are split between | |
3430 | registers and stack. */ | |
ab2e1992 MR |
3431 | /* For N32/N64, structs, unions, or other composite types are |
3432 | treated as a sequence of doublewords, and are passed in integer | |
3433 | or floating point registers as though they were simple scalar | |
3434 | parameters to the extent that they fit, with any excess on the | |
3435 | stack packed according to the normal memory layout of the | |
3436 | object. | |
3437 | The caller does not reserve space for the register arguments; | |
3438 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3439 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3440 | register are only written to memory. */ |
cb3d25d1 MS |
3441 | while (len > 0) |
3442 | { | |
ad018eee | 3443 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3444 | int stack_used_p = 0; |
1a69e1e4 | 3445 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3446 | |
3447 | if (mips_debug) | |
3448 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3449 | partial_len); | |
3450 | ||
74ed0bb4 MD |
3451 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3452 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3453 | |
cb3d25d1 | 3454 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3455 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3456 | { |
3457 | /* Should shorter than int integer values be | |
025bb325 | 3458 | promoted to int before being stored? */ |
cb3d25d1 MS |
3459 | int longword_offset = 0; |
3460 | CORE_ADDR addr; | |
3461 | stack_used_p = 1; | |
72a155b4 | 3462 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3463 | { |
1a69e1e4 | 3464 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3465 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3466 | && len <= 4) |
3467 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3468 | } |
3469 | ||
3470 | if (mips_debug) | |
3471 | { | |
5af949e3 UW |
3472 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3473 | paddress (gdbarch, stack_offset)); | |
3474 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3475 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3476 | } |
3477 | ||
3478 | addr = sp + stack_offset + longword_offset; | |
3479 | ||
3480 | if (mips_debug) | |
3481 | { | |
3482 | int i; | |
5af949e3 UW |
3483 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3484 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3485 | for (i = 0; i < partial_len; i++) |
3486 | { | |
6d82d43b | 3487 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3488 | val[i] & 0xff); |
3489 | } | |
3490 | } | |
3491 | write_memory (addr, val, partial_len); | |
3492 | } | |
3493 | ||
3494 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3495 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3496 | /* Write this portion of the argument to a general |
6d82d43b | 3497 | purpose register. */ |
74ed0bb4 | 3498 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3499 | { |
5863b5d5 MR |
3500 | LONGEST regval; |
3501 | ||
3502 | /* Sign extend pointers, 32-bit integers and signed | |
3503 | 16-bit and 8-bit integers; everything else is taken | |
3504 | as is. */ | |
3505 | ||
3506 | if ((partial_len == 4 | |
3507 | && (typecode == TYPE_CODE_PTR | |
3508 | || typecode == TYPE_CODE_INT)) | |
3509 | || (partial_len < 4 | |
3510 | && typecode == TYPE_CODE_INT | |
3511 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3512 | regval = extract_signed_integer (val, partial_len, |
3513 | byte_order); | |
5863b5d5 | 3514 | else |
e17a4113 UW |
3515 | regval = extract_unsigned_integer (val, partial_len, |
3516 | byte_order); | |
cb3d25d1 MS |
3517 | |
3518 | /* A non-floating-point argument being passed in a | |
3519 | general register. If a struct or union, and if | |
3520 | the remaining length is smaller than the register | |
3521 | size, we have to adjust the register value on | |
3522 | big endian targets. | |
3523 | ||
3524 | It does not seem to be necessary to do the | |
1a69e1e4 | 3525 | same for integral types. */ |
cb3d25d1 | 3526 | |
72a155b4 | 3527 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3528 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3529 | && (typecode == TYPE_CODE_STRUCT |
3530 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3531 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3532 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3533 | |
3534 | if (mips_debug) | |
3535 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3536 | argreg, | |
1a69e1e4 | 3537 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3538 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3539 | |
74ed0bb4 | 3540 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3541 | TYPE_LENGTH (arg_type) - len)) |
3542 | { | |
3543 | if (mips_debug) | |
3544 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3545 | float_argreg, | |
3546 | phex (regval, MIPS64_REGSIZE)); | |
3547 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3548 | regval); | |
3549 | } | |
3550 | ||
3551 | float_argreg++; | |
cb3d25d1 MS |
3552 | argreg++; |
3553 | } | |
3554 | ||
3555 | len -= partial_len; | |
3556 | val += partial_len; | |
3557 | ||
b021a221 MS |
3558 | /* Compute the offset into the stack at which we will |
3559 | copy the next parameter. | |
cb3d25d1 MS |
3560 | |
3561 | In N32 (N64?), the stack_offset only needs to be | |
3562 | adjusted when it has been used. */ | |
3563 | ||
3564 | if (stack_used_p) | |
1a69e1e4 | 3565 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3566 | } |
3567 | } | |
3568 | if (mips_debug) | |
3569 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3570 | } | |
3571 | ||
f10683bb | 3572 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3573 | |
cb3d25d1 MS |
3574 | /* Return adjusted stack pointer. */ |
3575 | return sp; | |
3576 | } | |
3577 | ||
6d82d43b | 3578 | static enum return_value_convention |
c055b101 | 3579 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3580 | struct type *type, struct regcache *regcache, |
47a35522 | 3581 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3582 | { |
72a155b4 | 3583 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3584 | |
3585 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3586 | ||
3587 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3588 | if needed), as appropriate for the type. Composite results (struct, | |
3589 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3590 | following rules: | |
3591 | ||
3592 | * A struct with only one or two floating point fields is returned in $f0 | |
3593 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3594 | case. | |
3595 | ||
f08877ba | 3596 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
3597 | $2 (first 64 bits) and $3 (remainder, if necessary). |
3598 | ||
3599 | * Larger composite results are handled by converting the function to a | |
3600 | procedure with an implicit first parameter, which is a pointer to an area | |
3601 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3602 | that all composite results be handled by conversion to implicit first | |
3603 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3604 | specific exception to return COMPLEX results in the floating point | |
3605 | registers.] */ | |
3606 | ||
f08877ba | 3607 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3608 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3609 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3610 | && TYPE_LENGTH (type) == 16 | |
3611 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3612 | { | |
3613 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3614 | two registers are used in the same as memory order, so the | |
3615 | eight bytes with the lower memory address are in $f0. */ | |
3616 | if (mips_debug) | |
3617 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3618 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3619 | gdbarch_num_regs (gdbarch) |
3620 | + mips_regnum (gdbarch)->fp0, | |
3621 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3622 | readbuf, writebuf, 0); |
ba32f989 | 3623 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3624 | gdbarch_num_regs (gdbarch) |
3625 | + mips_regnum (gdbarch)->fp0 + 2, | |
3626 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3627 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3628 | writebuf ? writebuf + 8 : writebuf, 0); |
3629 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3630 | } | |
6d82d43b AC |
3631 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3632 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3633 | { | |
59aa1faa | 3634 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3635 | if (mips_debug) |
3636 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3637 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3638 | gdbarch_num_regs (gdbarch) |
3639 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3640 | TYPE_LENGTH (type), |
72a155b4 | 3641 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3642 | readbuf, writebuf, 0); |
6d82d43b AC |
3643 | return RETURN_VALUE_REGISTER_CONVENTION; |
3644 | } | |
3645 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3646 | && TYPE_NFIELDS (type) <= 2 | |
3647 | && TYPE_NFIELDS (type) >= 1 | |
3648 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3649 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3650 | == TYPE_CODE_FLT)) |
3651 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3652 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3653 | == TYPE_CODE_FLT) |
b18bb924 | 3654 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3655 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3656 | { |
3657 | /* A struct that contains one or two floats. Each value is part | |
3658 | in the least significant part of their floating point | |
5b68030f | 3659 | register (or GPR, for soft float). */ |
6d82d43b AC |
3660 | int regnum; |
3661 | int field; | |
5b68030f JM |
3662 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3663 | ? mips_regnum (gdbarch)->fp0 | |
3664 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3665 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3666 | { | |
3667 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3668 | / TARGET_CHAR_BIT); | |
3669 | if (mips_debug) | |
3670 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3671 | offset); | |
5b68030f JM |
3672 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3673 | { | |
3674 | /* A 16-byte long double field goes in two consecutive | |
3675 | registers. */ | |
3676 | mips_xfer_register (gdbarch, regcache, | |
3677 | gdbarch_num_regs (gdbarch) + regnum, | |
3678 | 8, | |
3679 | gdbarch_byte_order (gdbarch), | |
3680 | readbuf, writebuf, offset); | |
3681 | mips_xfer_register (gdbarch, regcache, | |
3682 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3683 | 8, | |
3684 | gdbarch_byte_order (gdbarch), | |
3685 | readbuf, writebuf, offset + 8); | |
3686 | } | |
3687 | else | |
3688 | mips_xfer_register (gdbarch, regcache, | |
3689 | gdbarch_num_regs (gdbarch) + regnum, | |
3690 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3691 | gdbarch_byte_order (gdbarch), | |
3692 | readbuf, writebuf, offset); | |
6d82d43b AC |
3693 | } |
3694 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3695 | } | |
3696 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
3697 | || TYPE_CODE (type) == TYPE_CODE_UNION |
3698 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 3699 | { |
f08877ba | 3700 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
3701 | regardless of the byte order. I.e. DO NOT USE |
3702 | mips_xfer_lower. */ | |
3703 | int offset; | |
3704 | int regnum; | |
4c7d22cb | 3705 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3706 | offset < TYPE_LENGTH (type); |
72a155b4 | 3707 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3708 | { |
72a155b4 | 3709 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3710 | if (offset + xfer > TYPE_LENGTH (type)) |
3711 | xfer = TYPE_LENGTH (type) - offset; | |
3712 | if (mips_debug) | |
3713 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3714 | offset, xfer, regnum); | |
ba32f989 DJ |
3715 | mips_xfer_register (gdbarch, regcache, |
3716 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3717 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3718 | offset); | |
6d82d43b AC |
3719 | } |
3720 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3721 | } | |
3722 | else | |
3723 | { | |
3724 | /* A scalar extract each part but least-significant-byte | |
3725 | justified. */ | |
3726 | int offset; | |
3727 | int regnum; | |
4c7d22cb | 3728 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3729 | offset < TYPE_LENGTH (type); |
72a155b4 | 3730 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3731 | { |
72a155b4 | 3732 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3733 | if (offset + xfer > TYPE_LENGTH (type)) |
3734 | xfer = TYPE_LENGTH (type) - offset; | |
3735 | if (mips_debug) | |
3736 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3737 | offset, xfer, regnum); | |
ba32f989 DJ |
3738 | mips_xfer_register (gdbarch, regcache, |
3739 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3740 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3741 | readbuf, writebuf, offset); |
6d82d43b AC |
3742 | } |
3743 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3744 | } | |
3745 | } | |
3746 | ||
3747 | /* O32 ABI stuff. */ | |
3748 | ||
3749 | static CORE_ADDR | |
7d9b040b | 3750 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3751 | struct regcache *regcache, CORE_ADDR bp_addr, |
3752 | int nargs, struct value **args, CORE_ADDR sp, | |
3753 | int struct_return, CORE_ADDR struct_addr) | |
3754 | { | |
3755 | int argreg; | |
3756 | int float_argreg; | |
3757 | int argnum; | |
3758 | int len = 0; | |
3759 | int stack_offset = 0; | |
3760 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3761 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3762 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3763 | |
3764 | /* For shared libraries, "t9" needs to point at the function | |
3765 | address. */ | |
4c7d22cb | 3766 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3767 | |
3768 | /* Set the return address register to point to the entry point of | |
3769 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3770 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3771 | |
3772 | /* First ensure that the stack and structure return address (if any) | |
3773 | are properly aligned. The stack has to be at least 64-bit | |
3774 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3775 | aligned. For n32 and n64, stack frames need to be 128-bit |
3776 | aligned, so we round to this widest known alignment. */ | |
3777 | ||
5b03f266 AC |
3778 | sp = align_down (sp, 16); |
3779 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3780 | |
3781 | /* Now make space on the stack for the args. */ | |
3782 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3783 | { |
3784 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3785 | int arglen = TYPE_LENGTH (arg_type); | |
3786 | ||
3787 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3788 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3789 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3790 | /* Allocate space on the stack. */ |
1a69e1e4 | 3791 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3792 | } |
5b03f266 | 3793 | sp -= align_up (len, 16); |
ebafbe83 MS |
3794 | |
3795 | if (mips_debug) | |
6d82d43b | 3796 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3797 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3798 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3799 | |
3800 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3801 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3802 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3803 | |
bcb0cc15 | 3804 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3805 | if (struct_return) |
3806 | { | |
3807 | if (mips_debug) | |
3808 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3809 | "mips_o32_push_dummy_call: " |
3810 | "struct_return reg=%d %s\n", | |
5af949e3 | 3811 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3812 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3813 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3814 | } |
3815 | ||
3816 | /* Now load as many as possible of the first arguments into | |
3817 | registers, and push the rest onto the stack. Loop thru args | |
3818 | from first to last. */ | |
3819 | for (argnum = 0; argnum < nargs; argnum++) | |
3820 | { | |
47a35522 | 3821 | const gdb_byte *val; |
ebafbe83 | 3822 | struct value *arg = args[argnum]; |
4991999e | 3823 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3824 | int len = TYPE_LENGTH (arg_type); |
3825 | enum type_code typecode = TYPE_CODE (arg_type); | |
3826 | ||
3827 | if (mips_debug) | |
3828 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3829 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3830 | argnum + 1, len, (int) typecode); |
3831 | ||
47a35522 | 3832 | val = value_contents (arg); |
46cac009 AC |
3833 | |
3834 | /* 32-bit ABIs always start floating point arguments in an | |
3835 | even-numbered floating point register. Round the FP register | |
3836 | up before the check to see if there are any FP registers | |
3837 | left. O32/O64 targets also pass the FP in the integer | |
3838 | registers so also round up normal registers. */ | |
74ed0bb4 | 3839 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3840 | { |
3841 | if ((float_argreg & 1)) | |
3842 | float_argreg++; | |
3843 | } | |
3844 | ||
3845 | /* Floating point arguments passed in registers have to be | |
3846 | treated specially. On 32-bit architectures, doubles | |
3847 | are passed in register pairs; the even register gets | |
3848 | the low word, and the odd register gets the high word. | |
3849 | On O32/O64, the first two floating point arguments are | |
3850 | also copied to general registers, because MIPS16 functions | |
3851 | don't use float registers for arguments. This duplication of | |
3852 | arguments in general registers can't hurt non-MIPS16 functions | |
3853 | because those registers are normally skipped. */ | |
3854 | ||
74ed0bb4 MD |
3855 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3856 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3857 | { |
8b07f6d8 | 3858 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3859 | { |
72a155b4 | 3860 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3861 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3862 | unsigned long regval; |
3863 | ||
3864 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
3865 | regval = extract_unsigned_integer (val + low_offset, |
3866 | 4, byte_order); | |
46cac009 AC |
3867 | if (mips_debug) |
3868 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3869 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3870 | regcache_cooked_write_unsigned (regcache, |
3871 | float_argreg++, regval); | |
46cac009 AC |
3872 | if (mips_debug) |
3873 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3874 | argreg, phex (regval, 4)); | |
9c9acae0 | 3875 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3876 | |
3877 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
3878 | regval = extract_unsigned_integer (val + 4 - low_offset, |
3879 | 4, byte_order); | |
46cac009 AC |
3880 | if (mips_debug) |
3881 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3882 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3883 | regcache_cooked_write_unsigned (regcache, |
3884 | float_argreg++, regval); | |
46cac009 AC |
3885 | |
3886 | if (mips_debug) | |
3887 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3888 | argreg, phex (regval, 4)); | |
9c9acae0 | 3889 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3890 | } |
3891 | else | |
3892 | { | |
3893 | /* This is a floating point value that fits entirely | |
3894 | in a single register. */ | |
3895 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3896 | above to ensure that it is even register aligned. */ |
e17a4113 | 3897 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
3898 | if (mips_debug) |
3899 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3900 | float_argreg, phex (regval, len)); | |
025bb325 MS |
3901 | regcache_cooked_write_unsigned (regcache, |
3902 | float_argreg++, regval); | |
5b68030f JM |
3903 | /* Although two FP registers are reserved for each |
3904 | argument, only one corresponding integer register is | |
3905 | reserved. */ | |
46cac009 AC |
3906 | if (mips_debug) |
3907 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3908 | argreg, phex (regval, len)); | |
5b68030f | 3909 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3910 | } |
3911 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3912 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3913 | } |
3914 | else | |
3915 | { | |
3916 | /* Copy the argument to general registers or the stack in | |
3917 | register-sized pieces. Large arguments are split between | |
3918 | registers and stack. */ | |
1a69e1e4 DJ |
3919 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3920 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3921 | them in registers where gcc sometimes puts them on the |
3922 | stack. For maximum compatibility, we will put them in | |
3923 | both places. */ | |
1a69e1e4 DJ |
3924 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3925 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3926 | /* Structures should be aligned to eight bytes (even arg registers) |
3927 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3928 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3929 | { |
3930 | if ((argreg & 1)) | |
968b5391 MR |
3931 | { |
3932 | argreg++; | |
1a69e1e4 | 3933 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3934 | } |
46cac009 | 3935 | } |
46cac009 AC |
3936 | while (len > 0) |
3937 | { | |
3938 | /* Remember if the argument was written to the stack. */ | |
3939 | int stack_used_p = 0; | |
1a69e1e4 | 3940 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3941 | |
3942 | if (mips_debug) | |
3943 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3944 | partial_len); | |
3945 | ||
3946 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3947 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3948 | || odd_sized_struct) |
46cac009 AC |
3949 | { |
3950 | /* Should shorter than int integer values be | |
025bb325 | 3951 | promoted to int before being stored? */ |
46cac009 AC |
3952 | int longword_offset = 0; |
3953 | CORE_ADDR addr; | |
3954 | stack_used_p = 1; | |
46cac009 AC |
3955 | |
3956 | if (mips_debug) | |
3957 | { | |
5af949e3 UW |
3958 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3959 | paddress (gdbarch, stack_offset)); | |
3960 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3961 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
3962 | } |
3963 | ||
3964 | addr = sp + stack_offset + longword_offset; | |
3965 | ||
3966 | if (mips_debug) | |
3967 | { | |
3968 | int i; | |
5af949e3 UW |
3969 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3970 | paddress (gdbarch, addr)); | |
46cac009 AC |
3971 | for (i = 0; i < partial_len; i++) |
3972 | { | |
6d82d43b | 3973 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3974 | val[i] & 0xff); |
3975 | } | |
3976 | } | |
3977 | write_memory (addr, val, partial_len); | |
3978 | } | |
3979 | ||
3980 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3981 | structs may go thru BOTH paths. */ |
46cac009 | 3982 | /* Write this portion of the argument to a general |
6d82d43b | 3983 | purpose register. */ |
74ed0bb4 | 3984 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 3985 | { |
e17a4113 UW |
3986 | LONGEST regval = extract_signed_integer (val, partial_len, |
3987 | byte_order); | |
4246e332 | 3988 | /* Value may need to be sign extended, because |
1b13c4f6 | 3989 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3990 | |
3991 | /* A non-floating-point argument being passed in a | |
3992 | general register. If a struct or union, and if | |
3993 | the remaining length is smaller than the register | |
3994 | size, we have to adjust the register value on | |
3995 | big endian targets. | |
3996 | ||
3997 | It does not seem to be necessary to do the | |
3998 | same for integral types. | |
3999 | ||
4000 | Also don't do this adjustment on O64 binaries. | |
4001 | ||
4002 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4003 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
4004 | mips_abi_regsize(), generates a left shift |
4005 | as part of storing the argument in a register | |
4006 | (the left shift isn't generated when | |
1b13c4f6 | 4007 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4008 | it is quite possible that this is GCC |
4009 | contradicting the LE/O32 ABI, GDB has not been | |
4010 | adjusted to accommodate this. Either someone | |
4011 | needs to demonstrate that the LE/O32 ABI | |
4012 | specifies such a left shift OR this new ABI gets | |
4013 | identified as such and GDB gets tweaked | |
4014 | accordingly. */ | |
4015 | ||
72a155b4 | 4016 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4017 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
4018 | && (typecode == TYPE_CODE_STRUCT |
4019 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4020 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 4021 | * TARGET_CHAR_BIT); |
46cac009 AC |
4022 | |
4023 | if (mips_debug) | |
4024 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4025 | argreg, | |
1a69e1e4 | 4026 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 4027 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
4028 | argreg++; |
4029 | ||
4030 | /* Prevent subsequent floating point arguments from | |
4031 | being passed in floating point registers. */ | |
74ed0bb4 | 4032 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
4033 | } |
4034 | ||
4035 | len -= partial_len; | |
4036 | val += partial_len; | |
4037 | ||
b021a221 MS |
4038 | /* Compute the offset into the stack at which we will |
4039 | copy the next parameter. | |
46cac009 | 4040 | |
6d82d43b AC |
4041 | In older ABIs, the caller reserved space for |
4042 | registers that contained arguments. This was loosely | |
4043 | refered to as their "home". Consequently, space is | |
4044 | always allocated. */ | |
46cac009 | 4045 | |
1a69e1e4 | 4046 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
4047 | } |
4048 | } | |
4049 | if (mips_debug) | |
4050 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4051 | } | |
4052 | ||
f10683bb | 4053 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4054 | |
46cac009 AC |
4055 | /* Return adjusted stack pointer. */ |
4056 | return sp; | |
4057 | } | |
4058 | ||
6d82d43b | 4059 | static enum return_value_convention |
c055b101 CV |
4060 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
4061 | struct type *type, struct regcache *regcache, | |
47a35522 | 4062 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4063 | { |
72a155b4 | 4064 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
4065 | |
4066 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4067 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4068 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4069 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4070 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4071 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4072 | { | |
4073 | /* A single-precision floating-point value. It fits in the | |
4074 | least significant part of FP0. */ | |
4075 | if (mips_debug) | |
4076 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4077 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4078 | gdbarch_num_regs (gdbarch) |
4079 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 4080 | TYPE_LENGTH (type), |
72a155b4 | 4081 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4082 | readbuf, writebuf, 0); |
6d82d43b AC |
4083 | return RETURN_VALUE_REGISTER_CONVENTION; |
4084 | } | |
4085 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4086 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4087 | { | |
4088 | /* A double-precision floating-point value. The most | |
4089 | significant part goes in FP1, and the least significant in | |
4090 | FP0. */ | |
4091 | if (mips_debug) | |
4092 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 4093 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
4094 | { |
4095 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 4096 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4097 | gdbarch_num_regs (gdbarch) |
4098 | + mips_regnum (gdbarch)->fp0 + | |
4099 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4100 | readbuf, writebuf, 0); |
ba32f989 | 4101 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4102 | gdbarch_num_regs (gdbarch) |
4103 | + mips_regnum (gdbarch)->fp0 + 1, | |
4104 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4105 | readbuf, writebuf, 4); |
6d82d43b AC |
4106 | break; |
4107 | case BFD_ENDIAN_BIG: | |
ba32f989 | 4108 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4109 | gdbarch_num_regs (gdbarch) |
4110 | + mips_regnum (gdbarch)->fp0 + 1, | |
4111 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4112 | readbuf, writebuf, 0); |
ba32f989 | 4113 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4114 | gdbarch_num_regs (gdbarch) |
4115 | + mips_regnum (gdbarch)->fp0 + 0, | |
4116 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4117 | readbuf, writebuf, 4); |
6d82d43b AC |
4118 | break; |
4119 | default: | |
e2e0b3e5 | 4120 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
4121 | } |
4122 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4123 | } | |
4124 | #if 0 | |
4125 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4126 | && TYPE_NFIELDS (type) <= 2 | |
4127 | && TYPE_NFIELDS (type) >= 1 | |
4128 | && ((TYPE_NFIELDS (type) == 1 | |
4129 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4130 | == TYPE_CODE_FLT)) | |
4131 | || (TYPE_NFIELDS (type) == 2 | |
4132 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4133 | == TYPE_CODE_FLT) | |
4134 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4135 | == TYPE_CODE_FLT))) | |
4136 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4137 | { | |
4138 | /* A struct that contains one or two floats. Each value is part | |
4139 | in the least significant part of their floating point | |
4140 | register.. */ | |
870cd05e | 4141 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
4142 | int regnum; |
4143 | int field; | |
72a155b4 | 4144 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
4145 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4146 | { | |
4147 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4148 | / TARGET_CHAR_BIT); | |
4149 | if (mips_debug) | |
4150 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4151 | offset); | |
ba32f989 DJ |
4152 | mips_xfer_register (gdbarch, regcache, |
4153 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 4154 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 4155 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4156 | readbuf, writebuf, offset); |
6d82d43b AC |
4157 | } |
4158 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4159 | } | |
4160 | #endif | |
4161 | #if 0 | |
4162 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4163 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4164 | { | |
4165 | /* A structure or union. Extract the left justified value, | |
4166 | regardless of the byte order. I.e. DO NOT USE | |
4167 | mips_xfer_lower. */ | |
4168 | int offset; | |
4169 | int regnum; | |
4c7d22cb | 4170 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4171 | offset < TYPE_LENGTH (type); |
72a155b4 | 4172 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 4173 | { |
72a155b4 | 4174 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
4175 | if (offset + xfer > TYPE_LENGTH (type)) |
4176 | xfer = TYPE_LENGTH (type) - offset; | |
4177 | if (mips_debug) | |
4178 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4179 | offset, xfer, regnum); | |
ba32f989 DJ |
4180 | mips_xfer_register (gdbarch, regcache, |
4181 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
4182 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
4183 | } | |
4184 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4185 | } | |
4186 | #endif | |
4187 | else | |
4188 | { | |
4189 | /* A scalar extract each part but least-significant-byte | |
4190 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 4191 | the ISA. */ |
6d82d43b AC |
4192 | int offset; |
4193 | int regnum; | |
4c7d22cb | 4194 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4195 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 4196 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 4197 | { |
1a69e1e4 | 4198 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
4199 | if (offset + xfer > TYPE_LENGTH (type)) |
4200 | xfer = TYPE_LENGTH (type) - offset; | |
4201 | if (mips_debug) | |
4202 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4203 | offset, xfer, regnum); | |
ba32f989 DJ |
4204 | mips_xfer_register (gdbarch, regcache, |
4205 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 4206 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4207 | readbuf, writebuf, offset); |
6d82d43b AC |
4208 | } |
4209 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4210 | } | |
4211 | } | |
4212 | ||
4213 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4214 | ABI. */ | |
46cac009 AC |
4215 | |
4216 | static CORE_ADDR | |
7d9b040b | 4217 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4218 | struct regcache *regcache, CORE_ADDR bp_addr, |
4219 | int nargs, | |
4220 | struct value **args, CORE_ADDR sp, | |
4221 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4222 | { |
4223 | int argreg; | |
4224 | int float_argreg; | |
4225 | int argnum; | |
4226 | int len = 0; | |
4227 | int stack_offset = 0; | |
480d3dd2 | 4228 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4229 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4230 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4231 | |
25ab4790 AC |
4232 | /* For shared libraries, "t9" needs to point at the function |
4233 | address. */ | |
4c7d22cb | 4234 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4235 | |
4236 | /* Set the return address register to point to the entry point of | |
4237 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4238 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4239 | |
46cac009 AC |
4240 | /* First ensure that the stack and structure return address (if any) |
4241 | are properly aligned. The stack has to be at least 64-bit | |
4242 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4243 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4244 | aligned, so we round to this widest known alignment. */ | |
4245 | ||
5b03f266 AC |
4246 | sp = align_down (sp, 16); |
4247 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4248 | |
4249 | /* Now make space on the stack for the args. */ | |
4250 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4251 | { |
4252 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4253 | int arglen = TYPE_LENGTH (arg_type); | |
4254 | ||
968b5391 | 4255 | /* Allocate space on the stack. */ |
1a69e1e4 | 4256 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4257 | } |
5b03f266 | 4258 | sp -= align_up (len, 16); |
46cac009 AC |
4259 | |
4260 | if (mips_debug) | |
6d82d43b | 4261 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4262 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4263 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4264 | |
4265 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4266 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4267 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4268 | |
4269 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4270 | if (struct_return) | |
4271 | { | |
4272 | if (mips_debug) | |
4273 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4274 | "mips_o64_push_dummy_call: " |
4275 | "struct_return reg=%d %s\n", | |
5af949e3 | 4276 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4277 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4278 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4279 | } |
4280 | ||
4281 | /* Now load as many as possible of the first arguments into | |
4282 | registers, and push the rest onto the stack. Loop thru args | |
4283 | from first to last. */ | |
4284 | for (argnum = 0; argnum < nargs; argnum++) | |
4285 | { | |
47a35522 | 4286 | const gdb_byte *val; |
930bd0e0 | 4287 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 4288 | struct value *arg = args[argnum]; |
4991999e | 4289 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4290 | int len = TYPE_LENGTH (arg_type); |
4291 | enum type_code typecode = TYPE_CODE (arg_type); | |
4292 | ||
4293 | if (mips_debug) | |
4294 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4295 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4296 | argnum + 1, len, (int) typecode); |
4297 | ||
47a35522 | 4298 | val = value_contents (arg); |
ebafbe83 | 4299 | |
930bd0e0 KB |
4300 | /* Function pointer arguments to mips16 code need to be made into |
4301 | mips16 pointers. */ | |
4302 | if (typecode == TYPE_CODE_PTR | |
4303 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4304 | { | |
4305 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4306 | len, byte_order); | |
4307 | if (mips_pc_is_mips16 (addr)) | |
4308 | { | |
4309 | store_signed_integer (valbuf, len, byte_order, | |
4310 | make_mips16_addr (addr)); | |
4311 | val = valbuf; | |
4312 | } | |
4313 | } | |
4314 | ||
ebafbe83 MS |
4315 | /* Floating point arguments passed in registers have to be |
4316 | treated specially. On 32-bit architectures, doubles | |
4317 | are passed in register pairs; the even register gets | |
4318 | the low word, and the odd register gets the high word. | |
4319 | On O32/O64, the first two floating point arguments are | |
4320 | also copied to general registers, because MIPS16 functions | |
4321 | don't use float registers for arguments. This duplication of | |
4322 | arguments in general registers can't hurt non-MIPS16 functions | |
4323 | because those registers are normally skipped. */ | |
4324 | ||
74ed0bb4 MD |
4325 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4326 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4327 | { |
e17a4113 | 4328 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4329 | if (mips_debug) |
4330 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4331 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4332 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4333 | if (mips_debug) |
4334 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4335 | argreg, phex (regval, len)); | |
9c9acae0 | 4336 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4337 | argreg++; |
ebafbe83 | 4338 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4339 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4340 | } |
4341 | else | |
4342 | { | |
4343 | /* Copy the argument to general registers or the stack in | |
4344 | register-sized pieces. Large arguments are split between | |
4345 | registers and stack. */ | |
1a69e1e4 | 4346 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4347 | are treated specially: Irix cc passes them in registers |
4348 | where gcc sometimes puts them on the stack. For maximum | |
4349 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4350 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4351 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4352 | while (len > 0) |
4353 | { | |
4354 | /* Remember if the argument was written to the stack. */ | |
4355 | int stack_used_p = 0; | |
1a69e1e4 | 4356 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4357 | |
4358 | if (mips_debug) | |
4359 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4360 | partial_len); | |
4361 | ||
4362 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4363 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4364 | || odd_sized_struct) |
ebafbe83 MS |
4365 | { |
4366 | /* Should shorter than int integer values be | |
025bb325 | 4367 | promoted to int before being stored? */ |
ebafbe83 MS |
4368 | int longword_offset = 0; |
4369 | CORE_ADDR addr; | |
4370 | stack_used_p = 1; | |
72a155b4 | 4371 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4372 | { |
1a69e1e4 DJ |
4373 | if ((typecode == TYPE_CODE_INT |
4374 | || typecode == TYPE_CODE_PTR | |
4375 | || typecode == TYPE_CODE_FLT) | |
4376 | && len <= 4) | |
4377 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4378 | } |
4379 | ||
4380 | if (mips_debug) | |
4381 | { | |
5af949e3 UW |
4382 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4383 | paddress (gdbarch, stack_offset)); | |
4384 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4385 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4386 | } |
4387 | ||
4388 | addr = sp + stack_offset + longword_offset; | |
4389 | ||
4390 | if (mips_debug) | |
4391 | { | |
4392 | int i; | |
5af949e3 UW |
4393 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4394 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4395 | for (i = 0; i < partial_len; i++) |
4396 | { | |
6d82d43b | 4397 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4398 | val[i] & 0xff); |
4399 | } | |
4400 | } | |
4401 | write_memory (addr, val, partial_len); | |
4402 | } | |
4403 | ||
4404 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4405 | structs may go thru BOTH paths. */ |
ebafbe83 | 4406 | /* Write this portion of the argument to a general |
6d82d43b | 4407 | purpose register. */ |
74ed0bb4 | 4408 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4409 | { |
e17a4113 UW |
4410 | LONGEST regval = extract_signed_integer (val, partial_len, |
4411 | byte_order); | |
4246e332 | 4412 | /* Value may need to be sign extended, because |
1b13c4f6 | 4413 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4414 | |
4415 | /* A non-floating-point argument being passed in a | |
4416 | general register. If a struct or union, and if | |
4417 | the remaining length is smaller than the register | |
4418 | size, we have to adjust the register value on | |
4419 | big endian targets. | |
4420 | ||
4421 | It does not seem to be necessary to do the | |
025bb325 | 4422 | same for integral types. */ |
480d3dd2 | 4423 | |
72a155b4 | 4424 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4425 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4426 | && (typecode == TYPE_CODE_STRUCT |
4427 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4428 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4429 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4430 | |
4431 | if (mips_debug) | |
4432 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4433 | argreg, | |
1a69e1e4 | 4434 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4435 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4436 | argreg++; |
4437 | ||
4438 | /* Prevent subsequent floating point arguments from | |
4439 | being passed in floating point registers. */ | |
74ed0bb4 | 4440 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4441 | } |
4442 | ||
4443 | len -= partial_len; | |
4444 | val += partial_len; | |
4445 | ||
b021a221 MS |
4446 | /* Compute the offset into the stack at which we will |
4447 | copy the next parameter. | |
ebafbe83 | 4448 | |
6d82d43b AC |
4449 | In older ABIs, the caller reserved space for |
4450 | registers that contained arguments. This was loosely | |
4451 | refered to as their "home". Consequently, space is | |
4452 | always allocated. */ | |
ebafbe83 | 4453 | |
1a69e1e4 | 4454 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4455 | } |
4456 | } | |
4457 | if (mips_debug) | |
4458 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4459 | } | |
4460 | ||
f10683bb | 4461 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4462 | |
ebafbe83 MS |
4463 | /* Return adjusted stack pointer. */ |
4464 | return sp; | |
4465 | } | |
4466 | ||
9c8fdbfa | 4467 | static enum return_value_convention |
c055b101 | 4468 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4469 | struct type *type, struct regcache *regcache, |
47a35522 | 4470 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4471 | { |
72a155b4 | 4472 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4473 | |
4474 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4475 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4476 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4477 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4478 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4479 | { |
4480 | /* A floating-point value. It fits in the least significant | |
4481 | part of FP0. */ | |
4482 | if (mips_debug) | |
4483 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4484 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4485 | gdbarch_num_regs (gdbarch) |
4486 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4487 | TYPE_LENGTH (type), |
72a155b4 | 4488 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4489 | readbuf, writebuf, 0); |
7a076fd2 FF |
4490 | return RETURN_VALUE_REGISTER_CONVENTION; |
4491 | } | |
4492 | else | |
4493 | { | |
4494 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 4495 | justified. */ |
7a076fd2 FF |
4496 | int offset; |
4497 | int regnum; | |
4498 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4499 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4500 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4501 | { |
1a69e1e4 | 4502 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4503 | if (offset + xfer > TYPE_LENGTH (type)) |
4504 | xfer = TYPE_LENGTH (type) - offset; | |
4505 | if (mips_debug) | |
4506 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4507 | offset, xfer, regnum); | |
ba32f989 DJ |
4508 | mips_xfer_register (gdbarch, regcache, |
4509 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4510 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4511 | readbuf, writebuf, offset); |
7a076fd2 FF |
4512 | } |
4513 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4514 | } | |
6d82d43b AC |
4515 | } |
4516 | ||
dd824b04 DJ |
4517 | /* Floating point register management. |
4518 | ||
4519 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4520 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4521 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4522 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4523 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4524 | double precision floats into two 32-bit chunks and store them in | |
4525 | consecutive fp regs. To display 64-bit floats stored in this | |
4526 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4527 | Throw in user-configurable endianness and you have a real mess. | |
4528 | ||
4529 | The way this works is: | |
4530 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4531 | double-precision value will be split across two logical registers. | |
4532 | The lower-numbered logical register will hold the low-order bits, | |
4533 | regardless of the processor's endianness. | |
4534 | - If we are on a 64-bit processor, and we are looking for a | |
4535 | single-precision value, it will be in the low ordered bits | |
4536 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4537 | save slot in memory. | |
4538 | - If we are in 64-bit mode, everything is straightforward. | |
4539 | ||
4540 | Note that this code only deals with "live" registers at the top of the | |
4541 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 4542 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
4543 | interface that can deal with dynamic saved register sizes -- fp |
4544 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4545 | and below). */ | |
4546 | ||
4547 | /* Copy a 32-bit single-precision value from the current frame | |
4548 | into rare_buffer. */ | |
4549 | ||
4550 | static void | |
e11c53d2 | 4551 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4552 | gdb_byte *rare_buffer) |
dd824b04 | 4553 | { |
72a155b4 UW |
4554 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4555 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4556 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4557 | |
e11c53d2 | 4558 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4559 | error (_("can't read register %d (%s)"), |
72a155b4 | 4560 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4561 | if (raw_size == 8) |
4562 | { | |
4563 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4564 | 32 bits. */ |
dd824b04 DJ |
4565 | int offset; |
4566 | ||
72a155b4 | 4567 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4568 | offset = 4; |
4569 | else | |
4570 | offset = 0; | |
4571 | ||
4572 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4573 | } | |
4574 | else | |
4575 | { | |
4576 | memcpy (rare_buffer, raw_buffer, 4); | |
4577 | } | |
4578 | } | |
4579 | ||
4580 | /* Copy a 64-bit double-precision value from the current frame into | |
4581 | rare_buffer. This may include getting half of it from the next | |
4582 | register. */ | |
4583 | ||
4584 | static void | |
e11c53d2 | 4585 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4586 | gdb_byte *rare_buffer) |
dd824b04 | 4587 | { |
72a155b4 UW |
4588 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4589 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4590 | |
9c9acae0 | 4591 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4592 | { |
4593 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4594 | all 64 bits. */ |
e11c53d2 | 4595 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4596 | error (_("can't read register %d (%s)"), |
72a155b4 | 4597 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4598 | } |
4599 | else | |
4600 | { | |
72a155b4 | 4601 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4602 | |
72a155b4 | 4603 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4604 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4605 | _("mips_read_fp_register_double: bad access to " |
4606 | "odd-numbered FP register")); | |
dd824b04 DJ |
4607 | |
4608 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4609 | each register. */ |
72a155b4 | 4610 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4611 | { |
e11c53d2 AC |
4612 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4613 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4614 | } |
361d1df0 | 4615 | else |
dd824b04 | 4616 | { |
e11c53d2 AC |
4617 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4618 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4619 | } |
4620 | } | |
4621 | } | |
4622 | ||
c906108c | 4623 | static void |
e11c53d2 AC |
4624 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4625 | int regnum) | |
025bb325 | 4626 | { /* Do values for FP (float) regs. */ |
72a155b4 | 4627 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4628 | gdb_byte *raw_buffer; |
025bb325 | 4629 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 4630 | int inv1, inv2; |
c5aa993b | 4631 | |
025bb325 MS |
4632 | raw_buffer = alloca (2 * register_size (gdbarch, |
4633 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 4634 | |
72a155b4 | 4635 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4636 | fprintf_filtered (file, "%*s", |
72a155b4 | 4637 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4638 | ""); |
f0ef6b29 | 4639 | |
72a155b4 | 4640 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4641 | { |
79a45b7d TT |
4642 | struct value_print_options opts; |
4643 | ||
f0ef6b29 KB |
4644 | /* 4-byte registers: Print hex and floating. Also print even |
4645 | numbered registers as doubles. */ | |
e11c53d2 | 4646 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
4647 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4648 | raw_buffer, &inv1); | |
c5aa993b | 4649 | |
79a45b7d | 4650 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4651 | print_scalar_formatted (raw_buffer, |
4652 | builtin_type (gdbarch)->builtin_uint32, | |
4653 | &opts, 'w', file); | |
dd824b04 | 4654 | |
e11c53d2 | 4655 | fprintf_filtered (file, " flt: "); |
1adad886 | 4656 | if (inv1) |
e11c53d2 | 4657 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4658 | else |
e11c53d2 | 4659 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4660 | |
72a155b4 | 4661 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4662 | { |
e11c53d2 | 4663 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4664 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4665 | raw_buffer, &inv2); | |
1adad886 | 4666 | |
e11c53d2 | 4667 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4668 | if (inv2) |
e11c53d2 | 4669 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4670 | else |
e11c53d2 | 4671 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4672 | } |
c906108c SS |
4673 | } |
4674 | else | |
dd824b04 | 4675 | { |
79a45b7d TT |
4676 | struct value_print_options opts; |
4677 | ||
f0ef6b29 | 4678 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4679 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4680 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4681 | raw_buffer, &inv1); | |
c906108c | 4682 | |
e11c53d2 | 4683 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4684 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4685 | raw_buffer, &inv2); | |
f0ef6b29 | 4686 | |
79a45b7d | 4687 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4688 | print_scalar_formatted (raw_buffer, |
4689 | builtin_type (gdbarch)->builtin_uint64, | |
4690 | &opts, 'g', file); | |
f0ef6b29 | 4691 | |
e11c53d2 | 4692 | fprintf_filtered (file, " flt: "); |
1adad886 | 4693 | if (inv1) |
e11c53d2 | 4694 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4695 | else |
e11c53d2 | 4696 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4697 | |
e11c53d2 | 4698 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4699 | if (inv2) |
e11c53d2 | 4700 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4701 | else |
e11c53d2 | 4702 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4703 | } |
4704 | } | |
4705 | ||
4706 | static void | |
e11c53d2 | 4707 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4708 | int regnum) |
f0ef6b29 | 4709 | { |
a4b8ebc8 | 4710 | struct gdbarch *gdbarch = get_frame_arch (frame); |
f0ef6b29 | 4711 | int offset; |
79a45b7d | 4712 | struct value_print_options opts; |
de15c4ab | 4713 | struct value *val; |
1adad886 | 4714 | |
7b9ee6a8 | 4715 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4716 | { |
e11c53d2 | 4717 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4718 | return; |
4719 | } | |
4720 | ||
de15c4ab PA |
4721 | val = get_frame_register_value (frame, regnum); |
4722 | if (value_optimized_out (val)) | |
f0ef6b29 | 4723 | { |
c9f4d572 | 4724 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4725 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4726 | return; |
c906108c | 4727 | } |
f0ef6b29 | 4728 | |
72a155b4 | 4729 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4730 | |
4731 | /* The problem with printing numeric register names (r26, etc.) is that | |
4732 | the user can't use them on input. Probably the best solution is to | |
4733 | fix it so that either the numeric or the funky (a2, etc.) names | |
4734 | are accepted on input. */ | |
4735 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4736 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4737 | else |
e11c53d2 | 4738 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4739 | |
79a45b7d | 4740 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
4741 | val_print_scalar_formatted (value_type (val), |
4742 | value_contents_for_printing (val), | |
4743 | value_embedded_offset (val), | |
4744 | val, | |
4745 | &opts, 0, file); | |
c906108c SS |
4746 | } |
4747 | ||
f0ef6b29 KB |
4748 | /* Replacement for generic do_registers_info. |
4749 | Print regs in pretty columns. */ | |
4750 | ||
4751 | static int | |
e11c53d2 AC |
4752 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4753 | int regnum) | |
f0ef6b29 | 4754 | { |
e11c53d2 AC |
4755 | fprintf_filtered (file, " "); |
4756 | mips_print_fp_register (file, frame, regnum); | |
4757 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4758 | return regnum + 1; |
4759 | } | |
4760 | ||
4761 | ||
025bb325 | 4762 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
4763 | |
4764 | static int | |
e11c53d2 | 4765 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4766 | int start_regnum) |
c906108c | 4767 | { |
a4b8ebc8 | 4768 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 4769 | /* Do values for GP (int) regs. */ |
47a35522 | 4770 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
4771 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
4772 | per row. */ | |
c906108c | 4773 | int col, byte; |
a4b8ebc8 | 4774 | int regnum; |
c906108c | 4775 | |
025bb325 | 4776 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 4777 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4778 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4779 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4780 | regnum++) |
c906108c | 4781 | { |
72a155b4 | 4782 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4783 | continue; /* unused register */ |
7b9ee6a8 | 4784 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4785 | TYPE_CODE_FLT) |
025bb325 | 4786 | break; /* End the row: reached FP register. */ |
0cc93a06 | 4787 | /* Large registers are handled separately. */ |
72a155b4 | 4788 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4789 | { |
4790 | if (col > 0) | |
4791 | break; /* End the row before this register. */ | |
4792 | ||
4793 | /* Print this register on a row by itself. */ | |
4794 | mips_print_register (file, frame, regnum); | |
4795 | fprintf_filtered (file, "\n"); | |
4796 | return regnum + 1; | |
4797 | } | |
d05f6826 DJ |
4798 | if (col == 0) |
4799 | fprintf_filtered (file, " "); | |
6d82d43b | 4800 | fprintf_filtered (file, |
72a155b4 UW |
4801 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4802 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4803 | col++; |
4804 | } | |
d05f6826 DJ |
4805 | |
4806 | if (col == 0) | |
4807 | return regnum; | |
4808 | ||
025bb325 | 4809 | /* Print the R0 to R31 names. */ |
72a155b4 | 4810 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4811 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4812 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4813 | else |
4814 | fprintf_filtered (file, "\n "); | |
c906108c | 4815 | |
025bb325 | 4816 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 4817 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4818 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4819 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4820 | regnum++) |
c906108c | 4821 | { |
72a155b4 | 4822 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4823 | continue; /* unused register */ |
7b9ee6a8 | 4824 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4825 | TYPE_CODE_FLT) |
025bb325 | 4826 | break; /* End row: reached FP register. */ |
72a155b4 | 4827 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4828 | break; /* End row: large register. */ |
4829 | ||
c906108c | 4830 | /* OK: get the data in raw format. */ |
e11c53d2 | 4831 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4832 | error (_("can't read register %d (%s)"), |
72a155b4 | 4833 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4834 | /* pad small registers */ |
4246e332 | 4835 | for (byte = 0; |
72a155b4 UW |
4836 | byte < (mips_abi_regsize (gdbarch) |
4837 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 4838 | printf_filtered (" "); |
025bb325 | 4839 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 4840 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4841 | for (byte = |
72a155b4 UW |
4842 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4843 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4844 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4845 | else |
72a155b4 | 4846 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4847 | byte >= 0; byte--) |
47a35522 | 4848 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4849 | fprintf_filtered (file, " "); |
c906108c SS |
4850 | col++; |
4851 | } | |
025bb325 | 4852 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4853 | fprintf_filtered (file, "\n"); |
c906108c SS |
4854 | |
4855 | return regnum; | |
4856 | } | |
4857 | ||
025bb325 | 4858 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 4859 | |
bf1f5b4c | 4860 | static void |
e11c53d2 AC |
4861 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4862 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4863 | { |
025bb325 | 4864 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 4865 | { |
72a155b4 UW |
4866 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4867 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4868 | error (_("Not a valid register for the current processor type")); |
c906108c | 4869 | |
0cc93a06 | 4870 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4871 | fprintf_filtered (file, "\n"); |
c906108c | 4872 | } |
c5aa993b | 4873 | else |
025bb325 | 4874 | /* Do all (or most) registers. */ |
c906108c | 4875 | { |
72a155b4 UW |
4876 | regnum = gdbarch_num_regs (gdbarch); |
4877 | while (regnum < gdbarch_num_regs (gdbarch) | |
4878 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4879 | { |
7b9ee6a8 | 4880 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4881 | TYPE_CODE_FLT) |
e11c53d2 | 4882 | { |
025bb325 | 4883 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
4884 | regnum = print_fp_register_row (file, frame, regnum); |
4885 | else | |
025bb325 | 4886 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 4887 | } |
c906108c | 4888 | else |
e11c53d2 | 4889 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4890 | } |
4891 | } | |
4892 | } | |
4893 | ||
c906108c SS |
4894 | /* Is this a branch with a delay slot? */ |
4895 | ||
c906108c | 4896 | static int |
acdb74a0 | 4897 | is_delayed (unsigned long insn) |
c906108c SS |
4898 | { |
4899 | int i; | |
4900 | for (i = 0; i < NUMOPCODES; ++i) | |
4901 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4902 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4903 | break; | |
4904 | return (i < NUMOPCODES | |
4905 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4906 | | INSN_COND_BRANCH_DELAY | |
4907 | | INSN_COND_BRANCH_LIKELY))); | |
4908 | } | |
4909 | ||
63807e1d | 4910 | static int |
3352ef37 AC |
4911 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4912 | struct frame_info *frame) | |
c906108c | 4913 | { |
e17a4113 | 4914 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 4915 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4916 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4917 | |
4918 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4919 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4920 | return 0; |
4921 | ||
6c95b8df | 4922 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
06648491 MK |
4923 | return 0; |
4924 | ||
3352ef37 AC |
4925 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4926 | /* If error reading memory, guess that it is not a delayed | |
4927 | branch. */ | |
c906108c | 4928 | return 0; |
e17a4113 | 4929 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
4930 | } |
4931 | ||
6d82d43b AC |
4932 | /* To skip prologues, I use this predicate. Returns either PC itself |
4933 | if the code at PC does not look like a function prologue; otherwise | |
4934 | returns an address that (if we're lucky) follows the prologue. If | |
4935 | LENIENT, then we must skip everything which is involved in setting | |
4936 | up the frame (it's OK to skip more, just so long as we don't skip | |
4937 | anything which might clobber the registers which are being saved. | |
4938 | We must skip more in the case where part of the prologue is in the | |
4939 | delay slot of a non-prologue instruction). */ | |
4940 | ||
4941 | static CORE_ADDR | |
6093d2eb | 4942 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4943 | { |
8b622e6a AC |
4944 | CORE_ADDR limit_pc; |
4945 | CORE_ADDR func_addr; | |
4946 | ||
6d82d43b AC |
4947 | /* See if we can determine the end of the prologue via the symbol table. |
4948 | If so, then return either PC, or the PC after the prologue, whichever | |
4949 | is greater. */ | |
8b622e6a AC |
4950 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4951 | { | |
d80b854b UW |
4952 | CORE_ADDR post_prologue_pc |
4953 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
4954 | if (post_prologue_pc != 0) |
4955 | return max (pc, post_prologue_pc); | |
4956 | } | |
6d82d43b AC |
4957 | |
4958 | /* Can't determine prologue from the symbol table, need to examine | |
4959 | instructions. */ | |
4960 | ||
98b4dd94 JB |
4961 | /* Find an upper limit on the function prologue using the debug |
4962 | information. If the debug information could not be used to provide | |
4963 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 4964 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
4965 | if (limit_pc == 0) |
4966 | limit_pc = pc + 100; /* Magic. */ | |
4967 | ||
0fe7e7c8 | 4968 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 4969 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 4970 | else |
e17a4113 | 4971 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
4972 | } |
4973 | ||
97ab0fdd MR |
4974 | /* Check whether the PC is in a function epilogue (32-bit version). |
4975 | This is a helper function for mips_in_function_epilogue_p. */ | |
4976 | static int | |
e17a4113 | 4977 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4978 | { |
4979 | CORE_ADDR func_addr = 0, func_end = 0; | |
4980 | ||
4981 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4982 | { | |
4983 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4984 | CORE_ADDR addr = func_end - 12; | |
4985 | ||
4986 | if (addr < func_addr + 4) | |
4987 | addr = func_addr + 4; | |
4988 | if (pc < addr) | |
4989 | return 0; | |
4990 | ||
4991 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4992 | { | |
4993 | unsigned long high_word; | |
4994 | unsigned long inst; | |
4995 | ||
e17a4113 | 4996 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4997 | high_word = (inst >> 16) & 0xffff; |
4998 | ||
4999 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
5000 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
5001 | && inst != 0x03e00008 /* jr $ra */ | |
5002 | && inst != 0x00000000) /* nop */ | |
5003 | return 0; | |
5004 | } | |
5005 | ||
5006 | return 1; | |
5007 | } | |
5008 | ||
5009 | return 0; | |
5010 | } | |
5011 | ||
5012 | /* Check whether the PC is in a function epilogue (16-bit version). | |
5013 | This is a helper function for mips_in_function_epilogue_p. */ | |
5014 | static int | |
e17a4113 | 5015 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
5016 | { |
5017 | CORE_ADDR func_addr = 0, func_end = 0; | |
5018 | ||
5019 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
5020 | { | |
5021 | /* The MIPS epilogue is max. 12 bytes long. */ | |
5022 | CORE_ADDR addr = func_end - 12; | |
5023 | ||
5024 | if (addr < func_addr + 4) | |
5025 | addr = func_addr + 4; | |
5026 | if (pc < addr) | |
5027 | return 0; | |
5028 | ||
5029 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
5030 | { | |
5031 | unsigned short inst; | |
5032 | ||
e17a4113 | 5033 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
5034 | |
5035 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
5036 | continue; | |
5037 | ||
5038 | if (inst != 0x6300 /* addiu $sp,offset */ | |
5039 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
5040 | && inst != 0xe820 /* jr $ra */ | |
5041 | && inst != 0xe8a0 /* jrc $ra */ | |
5042 | && inst != 0x6500) /* nop */ | |
5043 | return 0; | |
5044 | } | |
5045 | ||
5046 | return 1; | |
5047 | } | |
5048 | ||
5049 | return 0; | |
5050 | } | |
5051 | ||
5052 | /* The epilogue is defined here as the area at the end of a function, | |
5053 | after an instruction which destroys the function's stack frame. */ | |
5054 | static int | |
5055 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
5056 | { | |
5057 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 5058 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 5059 | else |
e17a4113 | 5060 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
5061 | } |
5062 | ||
025bb325 | 5063 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
5064 | used for all MIPS-specific commands. */ |
5065 | ||
a5ea2558 | 5066 | static void |
acdb74a0 | 5067 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5068 | { |
5069 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5070 | } | |
5071 | ||
a5ea2558 | 5072 | static void |
acdb74a0 | 5073 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5074 | { |
6d82d43b AC |
5075 | printf_unfiltered |
5076 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5077 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5078 | } | |
5079 | ||
c906108c SS |
5080 | /* Commands to show/set the MIPS FPU type. */ |
5081 | ||
c906108c | 5082 | static void |
acdb74a0 | 5083 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5084 | { |
c906108c | 5085 | char *fpu; |
6ca0852e | 5086 | |
1cf3db46 | 5087 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
5088 | { |
5089 | printf_unfiltered | |
5090 | ("The MIPS floating-point coprocessor is unknown " | |
5091 | "because the current architecture is not MIPS.\n"); | |
5092 | return; | |
5093 | } | |
5094 | ||
1cf3db46 | 5095 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
5096 | { |
5097 | case MIPS_FPU_SINGLE: | |
5098 | fpu = "single-precision"; | |
5099 | break; | |
5100 | case MIPS_FPU_DOUBLE: | |
5101 | fpu = "double-precision"; | |
5102 | break; | |
5103 | case MIPS_FPU_NONE: | |
5104 | fpu = "absent (none)"; | |
5105 | break; | |
93d56215 | 5106 | default: |
e2e0b3e5 | 5107 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
5108 | } |
5109 | if (mips_fpu_type_auto) | |
025bb325 MS |
5110 | printf_unfiltered ("The MIPS floating-point coprocessor " |
5111 | "is set automatically (currently %s)\n", | |
5112 | fpu); | |
c906108c | 5113 | else |
6d82d43b AC |
5114 | printf_unfiltered |
5115 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5116 | } |
5117 | ||
5118 | ||
c906108c | 5119 | static void |
acdb74a0 | 5120 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5121 | { |
025bb325 MS |
5122 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
5123 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5124 | show_mipsfpu_command (args, from_tty); |
5125 | } | |
5126 | ||
c906108c | 5127 | static void |
acdb74a0 | 5128 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5129 | { |
8d5838b5 AC |
5130 | struct gdbarch_info info; |
5131 | gdbarch_info_init (&info); | |
c906108c SS |
5132 | mips_fpu_type = MIPS_FPU_SINGLE; |
5133 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5134 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5135 | instead of relying on globals. Doing that would let generic code | |
5136 | handle the search for this specific architecture. */ | |
5137 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5138 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5139 | } |
5140 | ||
c906108c | 5141 | static void |
acdb74a0 | 5142 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5143 | { |
8d5838b5 AC |
5144 | struct gdbarch_info info; |
5145 | gdbarch_info_init (&info); | |
c906108c SS |
5146 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5147 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5148 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5149 | instead of relying on globals. Doing that would let generic code | |
5150 | handle the search for this specific architecture. */ | |
5151 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5152 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5153 | } |
5154 | ||
c906108c | 5155 | static void |
acdb74a0 | 5156 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5157 | { |
8d5838b5 AC |
5158 | struct gdbarch_info info; |
5159 | gdbarch_info_init (&info); | |
c906108c SS |
5160 | mips_fpu_type = MIPS_FPU_NONE; |
5161 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5162 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5163 | instead of relying on globals. Doing that would let generic code | |
5164 | handle the search for this specific architecture. */ | |
5165 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5166 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5167 | } |
5168 | ||
c906108c | 5169 | static void |
acdb74a0 | 5170 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5171 | { |
5172 | mips_fpu_type_auto = 1; | |
5173 | } | |
5174 | ||
c906108c | 5175 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5176 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5177 | the relevant processor still exists (it dates back to '94) and | |
5178 | secondly this is not the way to do this. The processor type should | |
5179 | be set by forcing an architecture change. */ | |
c906108c | 5180 | |
691c0433 AC |
5181 | void |
5182 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5183 | { |
bb486190 UW |
5184 | struct regcache *regcache = get_current_regcache (); |
5185 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
5186 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 5187 | ULONGEST prid; |
c906108c | 5188 | |
bb486190 | 5189 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 5190 | if ((prid & ~0xf) == 0x700) |
691c0433 | 5191 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5192 | } |
5193 | ||
5194 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5195 | callable as an sfunc. */ | |
5196 | ||
5197 | static void | |
acdb74a0 AC |
5198 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5199 | struct cmd_list_element *c) | |
c906108c SS |
5200 | { |
5201 | reinit_frame_cache (); | |
5202 | } | |
5203 | ||
a89aa300 AC |
5204 | static int |
5205 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5206 | { |
d31431ed AC |
5207 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5208 | disassembler needs to be able to locally determine the ISA, and | |
5209 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5210 | work. */ | |
ec4045ea AC |
5211 | if (mips_pc_is_mips16 (memaddr)) |
5212 | info->mach = bfd_mach_mips16; | |
c906108c SS |
5213 | |
5214 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5215 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5216 | |
e5ab0dce | 5217 | /* Set the disassembler options. */ |
9dae60cc | 5218 | if (!info->disassembler_options) |
e5ab0dce AC |
5219 | /* This string is not recognized explicitly by the disassembler, |
5220 | but it tells the disassembler to not try to guess the ABI from | |
5221 | the bfd elf headers, such that, if the user overrides the ABI | |
5222 | of a program linked as NewABI, the disassembly will follow the | |
5223 | register naming conventions specified by the user. */ | |
5224 | info->disassembler_options = "gpr-names=32"; | |
5225 | ||
c906108c | 5226 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 5227 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
5228 | return print_insn_big_mips (memaddr, info); |
5229 | else | |
5230 | return print_insn_little_mips (memaddr, info); | |
5231 | } | |
5232 | ||
9dae60cc UW |
5233 | static int |
5234 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
5235 | { | |
5236 | /* Set up the disassembler info, so that we get the right | |
5237 | register names from libopcodes. */ | |
5238 | info->disassembler_options = "gpr-names=n32"; | |
5239 | info->flavour = bfd_target_elf_flavour; | |
5240 | ||
5241 | return gdb_print_insn_mips (memaddr, info); | |
5242 | } | |
5243 | ||
5244 | static int | |
5245 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5246 | { | |
5247 | /* Set up the disassembler info, so that we get the right | |
5248 | register names from libopcodes. */ | |
5249 | info->disassembler_options = "gpr-names=64"; | |
5250 | info->flavour = bfd_target_elf_flavour; | |
5251 | ||
5252 | return gdb_print_insn_mips (memaddr, info); | |
5253 | } | |
5254 | ||
025bb325 MS |
5255 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
5256 | program counter value to determine whether a 16- or 32-bit breakpoint | |
5257 | should be used. It returns a pointer to a string of bytes that encode a | |
5258 | breakpoint instruction, stores the length of the string to *lenptr, and | |
5259 | adjusts pc (if necessary) to point to the actual memory location where | |
5260 | the breakpoint should be inserted. */ | |
c906108c | 5261 | |
47a35522 | 5262 | static const gdb_byte * |
025bb325 MS |
5263 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
5264 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 5265 | { |
67d57894 | 5266 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5267 | { |
0fe7e7c8 | 5268 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5269 | { |
47a35522 | 5270 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5271 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5272 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5273 | return mips16_big_breakpoint; |
5274 | } | |
5275 | else | |
5276 | { | |
aaab4dba AC |
5277 | /* The IDT board uses an unusual breakpoint value, and |
5278 | sometimes gets confused when it sees the usual MIPS | |
5279 | breakpoint instruction. */ | |
47a35522 MK |
5280 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5281 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5282 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 5283 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 5284 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 5285 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 5286 | |
c5aa993b | 5287 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5288 | |
5289 | if (strcmp (target_shortname, "mips") == 0) | |
5290 | return idt_big_breakpoint; | |
5291 | else if (strcmp (target_shortname, "ddb") == 0 | |
5292 | || strcmp (target_shortname, "pmon") == 0 | |
5293 | || strcmp (target_shortname, "lsi") == 0) | |
5294 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
5295 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5296 | return irix_big_breakpoint; | |
c906108c SS |
5297 | else |
5298 | return big_breakpoint; | |
5299 | } | |
5300 | } | |
5301 | else | |
5302 | { | |
0fe7e7c8 | 5303 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5304 | { |
47a35522 | 5305 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5306 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5307 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5308 | return mips16_little_breakpoint; |
5309 | } | |
5310 | else | |
5311 | { | |
47a35522 MK |
5312 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5313 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5314 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5315 | |
c5aa993b | 5316 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5317 | |
5318 | if (strcmp (target_shortname, "mips") == 0) | |
5319 | return idt_little_breakpoint; | |
5320 | else if (strcmp (target_shortname, "ddb") == 0 | |
5321 | || strcmp (target_shortname, "pmon") == 0 | |
5322 | || strcmp (target_shortname, "lsi") == 0) | |
5323 | return pmon_little_breakpoint; | |
5324 | else | |
5325 | return little_breakpoint; | |
5326 | } | |
5327 | } | |
5328 | } | |
5329 | ||
5330 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5331 | PC, which is either the callee or the caller. There are several | |
5332 | cases which must be handled: | |
5333 | ||
5334 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5335 | target PC is in $31 ($ra). |
c906108c | 5336 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5337 | and the target PC is in $2. |
c906108c | 5338 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b | 5339 | before the jal instruction, this is effectively a call stub |
b021a221 | 5340 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5341 | a return stub and the target PC is in $18. |
c906108c SS |
5342 | |
5343 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5344 | gory details. */ |
c906108c | 5345 | |
757a7cc6 | 5346 | static CORE_ADDR |
db5f024e | 5347 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5348 | { |
e17a4113 | 5349 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c SS |
5350 | char *name; |
5351 | CORE_ADDR start_addr; | |
5352 | ||
5353 | /* Find the starting address and name of the function containing the PC. */ | |
5354 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5355 | return 0; | |
5356 | ||
5357 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5358 | target PC is in $31 ($ra). */ | |
5359 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5360 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5361 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5362 | |
5363 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5364 | { | |
5365 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5366 | and the target PC is in $2. */ | |
5367 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5368 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5369 | |
5370 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5371 | before the jal instruction, this is effectively a call stub |
b021a221 | 5372 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5373 | a return stub and the target PC is in $18. */ |
c906108c SS |
5374 | else if (name[19] == 's' || name[19] == 'd') |
5375 | { | |
5376 | if (pc == start_addr) | |
5377 | { | |
5378 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5379 | stub. Such a stub for a function bar might have a name |
5380 | like __fn_stub_bar, and might look like this: | |
5381 | mfc1 $4,$f13 | |
5382 | mfc1 $5,$f12 | |
5383 | mfc1 $6,$f15 | |
5384 | mfc1 $7,$f14 | |
5385 | la $1,bar (becomes a lui/addiu pair) | |
5386 | jr $1 | |
5387 | So scan down to the lui/addi and extract the target | |
5388 | address from those two instructions. */ | |
c906108c | 5389 | |
52f729a7 | 5390 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 5391 | ULONGEST inst; |
c906108c SS |
5392 | int i; |
5393 | ||
5394 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5395 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5396 | 0) | |
c906108c SS |
5397 | return target_pc; |
5398 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5399 | && strcmp (name, "etext") != 0 | |
5400 | && strcmp (name, "_etext") != 0) | |
5401 | return target_pc; | |
5402 | ||
5403 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5404 | The limit on the search is arbitrarily set to 20 |
5405 | instructions. FIXME. */ | |
95ac2dcf | 5406 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5407 | { |
e17a4113 | 5408 | inst = mips_fetch_instruction (gdbarch, target_pc); |
c5aa993b | 5409 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
025bb325 | 5410 | pc = (inst << 16) & 0xffff0000; /* high word */ |
c5aa993b | 5411 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ |
025bb325 | 5412 | return pc | (inst & 0xffff); /* low word */ |
c906108c SS |
5413 | } |
5414 | ||
5415 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5416 | return target_pc; | |
5417 | } | |
5418 | else | |
5419 | /* This is the 'return' part of a call stub. The return | |
5420 | address is in $r18. */ | |
52f729a7 | 5421 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5422 | } |
5423 | } | |
c5aa993b | 5424 | return 0; /* not a stub */ |
c906108c SS |
5425 | } |
5426 | ||
db5f024e DJ |
5427 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5428 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5429 | so that $t9 has the correct value at function entry. */ | |
5430 | ||
5431 | static CORE_ADDR | |
5432 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5433 | { | |
e17a4113 UW |
5434 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5435 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
5436 | struct minimal_symbol *msym; |
5437 | int i; | |
5438 | gdb_byte stub_code[16]; | |
5439 | int32_t stub_words[4]; | |
5440 | ||
5441 | /* The stub for foo is named ".pic.foo", and is either two | |
5442 | instructions inserted before foo or a three instruction sequence | |
5443 | which jumps to foo. */ | |
5444 | msym = lookup_minimal_symbol_by_pc (pc); | |
5445 | if (msym == NULL | |
5446 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5447 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5448 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5449 | return 0; | |
5450 | ||
5451 | /* A two-instruction header. */ | |
5452 | if (MSYMBOL_SIZE (msym) == 8) | |
5453 | return pc + 8; | |
5454 | ||
5455 | /* A three-instruction (plus delay slot) trampoline. */ | |
5456 | if (MSYMBOL_SIZE (msym) == 16) | |
5457 | { | |
5458 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5459 | return 0; | |
5460 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
5461 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
5462 | 4, byte_order); | |
db5f024e DJ |
5463 | |
5464 | /* A stub contains these instructions: | |
5465 | lui t9, %hi(target) | |
5466 | j target | |
5467 | addiu t9, t9, %lo(target) | |
5468 | nop | |
5469 | ||
5470 | This works even for N64, since stubs are only generated with | |
5471 | -msym32. */ | |
5472 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5473 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5474 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5475 | && stub_words[3] == 0x00000000) | |
5476 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5477 | + (stub_words[2] & 0x0000ffff)); | |
5478 | } | |
5479 | ||
5480 | /* Not a recognized stub. */ | |
5481 | return 0; | |
5482 | } | |
5483 | ||
5484 | static CORE_ADDR | |
5485 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5486 | { | |
5487 | CORE_ADDR target_pc; | |
5488 | ||
5489 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5490 | if (target_pc) | |
5491 | return target_pc; | |
5492 | ||
5493 | target_pc = find_solib_trampoline_target (frame, pc); | |
5494 | if (target_pc) | |
5495 | return target_pc; | |
5496 | ||
5497 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5498 | if (target_pc) | |
5499 | return target_pc; | |
5500 | ||
5501 | return 0; | |
5502 | } | |
5503 | ||
a4b8ebc8 | 5504 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5505 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5506 | |
5507 | static int | |
d3f73121 | 5508 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5509 | { |
a4b8ebc8 | 5510 | int regnum; |
2f38ef89 | 5511 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5512 | regnum = num; |
2f38ef89 | 5513 | else if (num >= 38 && num < 70) |
d3f73121 | 5514 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5515 | else if (num == 70) |
d3f73121 | 5516 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5517 | else if (num == 71) |
d3f73121 | 5518 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5519 | else |
a4b8ebc8 AC |
5520 | /* This will hopefully (eventually) provoke a warning. Should |
5521 | we be calling complaint() here? */ | |
d3f73121 MD |
5522 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5523 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5524 | } |
5525 | ||
2f38ef89 | 5526 | |
a4b8ebc8 | 5527 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5528 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5529 | |
5530 | static int | |
d3f73121 | 5531 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5532 | { |
a4b8ebc8 | 5533 | int regnum; |
2f38ef89 | 5534 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5535 | regnum = num; |
2f38ef89 | 5536 | else if (num >= 32 && num < 64) |
d3f73121 | 5537 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5538 | else if (num == 64) |
d3f73121 | 5539 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5540 | else if (num == 65) |
d3f73121 | 5541 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5542 | else |
a4b8ebc8 AC |
5543 | /* This will hopefully (eventually) provoke a warning. Should we |
5544 | be calling complaint() here? */ | |
d3f73121 MD |
5545 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5546 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5547 | } |
5548 | ||
5549 | static int | |
e7faf938 | 5550 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5551 | { |
5552 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5553 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5554 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5555 | decide if it is valid. Should instead define a standard sim/gdb | |
5556 | register numbering scheme. */ | |
e7faf938 MD |
5557 | if (gdbarch_register_name (gdbarch, |
5558 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5559 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
5560 | gdbarch_num_regs (gdbarch) |
5561 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5562 | return regnum; |
5563 | else | |
6d82d43b | 5564 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5565 | } |
5566 | ||
2f38ef89 | 5567 | |
4844f454 CV |
5568 | /* Convert an integer into an address. Extracting the value signed |
5569 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5570 | |
5571 | static CORE_ADDR | |
79dd2d24 | 5572 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5573 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5574 | { |
e17a4113 UW |
5575 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
5576 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
5577 | } |
5578 | ||
82e91389 DJ |
5579 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5580 | than most other architectures; we just need to be explicit about it, | |
5581 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5582 | an assertion failure. */ | |
5583 | ||
5584 | static void | |
a54fba4c MD |
5585 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5586 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5587 | { |
5588 | *reg = MIPS_SP_REGNUM; | |
5589 | *offset = 0; | |
5590 | } | |
5591 | ||
caaa3122 DJ |
5592 | static void |
5593 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5594 | { | |
5595 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5596 | const char *name = bfd_get_section_name (abfd, sect); | |
5597 | ||
5598 | if (*abip != MIPS_ABI_UNKNOWN) | |
5599 | return; | |
5600 | ||
5601 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5602 | return; | |
5603 | ||
5604 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5605 | *abip = MIPS_ABI_O32; | |
5606 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5607 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5608 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5609 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5610 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5611 | *abip = MIPS_ABI_O64; | |
5612 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5613 | *abip = MIPS_ABI_EABI32; | |
5614 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5615 | *abip = MIPS_ABI_EABI64; | |
5616 | else | |
8a3fe4f8 | 5617 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5618 | } |
5619 | ||
22e47e37 FF |
5620 | static void |
5621 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5622 | { | |
5623 | int *lbp = (int *) obj; | |
5624 | const char *name = bfd_get_section_name (abfd, sect); | |
5625 | ||
5626 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5627 | *lbp = 32; | |
5628 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5629 | *lbp = 64; | |
5630 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5631 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5632 | } | |
5633 | ||
2e4ebe70 DJ |
5634 | static enum mips_abi |
5635 | global_mips_abi (void) | |
5636 | { | |
5637 | int i; | |
5638 | ||
5639 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5640 | if (mips_abi_strings[i] == mips_abi_string) | |
5641 | return (enum mips_abi) i; | |
5642 | ||
e2e0b3e5 | 5643 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5644 | } |
5645 | ||
29709017 DJ |
5646 | static void |
5647 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5648 | { | |
29709017 DJ |
5649 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5650 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5651 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5652 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5653 | |
5654 | /* If the size matches the full set of registers GDB traditionally | |
5655 | knows about, including floating point, for either 32-bit or | |
5656 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5657 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5658 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5659 | |
5660 | /* Otherwise we don't have a useful guess. */ | |
5661 | } | |
5662 | ||
f8b73d13 DJ |
5663 | static struct value * |
5664 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5665 | { | |
5666 | const int *reg_p = baton; | |
5667 | return value_of_register (*reg_p, frame); | |
5668 | } | |
5669 | ||
c2d11a7d | 5670 | static struct gdbarch * |
6d82d43b | 5671 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5672 | { |
c2d11a7d JM |
5673 | struct gdbarch *gdbarch; |
5674 | struct gdbarch_tdep *tdep; | |
5675 | int elf_flags; | |
2e4ebe70 | 5676 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5677 | int i, num_regs; |
8d5838b5 | 5678 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5679 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5680 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5681 | |
5682 | /* Check any target description for validity. */ | |
5683 | if (tdesc_has_registers (info.target_desc)) | |
5684 | { | |
5685 | static const char *const mips_gprs[] = { | |
5686 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5687 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5688 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5689 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5690 | }; | |
5691 | static const char *const mips_fprs[] = { | |
5692 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5693 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5694 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5695 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5696 | }; | |
5697 | ||
5698 | const struct tdesc_feature *feature; | |
5699 | int valid_p; | |
5700 | ||
5701 | feature = tdesc_find_feature (info.target_desc, | |
5702 | "org.gnu.gdb.mips.cpu"); | |
5703 | if (feature == NULL) | |
5704 | return NULL; | |
5705 | ||
5706 | tdesc_data = tdesc_data_alloc (); | |
5707 | ||
5708 | valid_p = 1; | |
5709 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5710 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5711 | mips_gprs[i]); | |
5712 | ||
5713 | ||
5714 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5715 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5716 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5717 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5718 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5719 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5720 | ||
5721 | if (!valid_p) | |
5722 | { | |
5723 | tdesc_data_cleanup (tdesc_data); | |
5724 | return NULL; | |
5725 | } | |
5726 | ||
5727 | feature = tdesc_find_feature (info.target_desc, | |
5728 | "org.gnu.gdb.mips.cp0"); | |
5729 | if (feature == NULL) | |
5730 | { | |
5731 | tdesc_data_cleanup (tdesc_data); | |
5732 | return NULL; | |
5733 | } | |
5734 | ||
5735 | valid_p = 1; | |
5736 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5737 | MIPS_EMBED_BADVADDR_REGNUM, | |
5738 | "badvaddr"); | |
5739 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5740 | MIPS_PS_REGNUM, "status"); | |
5741 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5742 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5743 | ||
5744 | if (!valid_p) | |
5745 | { | |
5746 | tdesc_data_cleanup (tdesc_data); | |
5747 | return NULL; | |
5748 | } | |
5749 | ||
5750 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5751 | backend is not prepared for that, though. */ | |
5752 | feature = tdesc_find_feature (info.target_desc, | |
5753 | "org.gnu.gdb.mips.fpu"); | |
5754 | if (feature == NULL) | |
5755 | { | |
5756 | tdesc_data_cleanup (tdesc_data); | |
5757 | return NULL; | |
5758 | } | |
5759 | ||
5760 | valid_p = 1; | |
5761 | for (i = 0; i < 32; i++) | |
5762 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5763 | i + MIPS_EMBED_FP0_REGNUM, | |
5764 | mips_fprs[i]); | |
5765 | ||
5766 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5767 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5768 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5769 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5770 | ||
5771 | if (!valid_p) | |
5772 | { | |
5773 | tdesc_data_cleanup (tdesc_data); | |
5774 | return NULL; | |
5775 | } | |
5776 | ||
5777 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5778 | when only 32-bit registers are provided. */ | |
5779 | } | |
c2d11a7d | 5780 | |
ec03c1ac AC |
5781 | /* First of all, extract the elf_flags, if available. */ |
5782 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5783 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5784 | else if (arches != NULL) |
5785 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5786 | else |
5787 | elf_flags = 0; | |
5788 | if (gdbarch_debug) | |
5789 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5790 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5791 | |
102182a9 | 5792 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5793 | switch ((elf_flags & EF_MIPS_ABI)) |
5794 | { | |
5795 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5796 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5797 | break; |
5798 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5799 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5800 | break; |
5801 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5802 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5803 | break; |
5804 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5805 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5806 | break; |
5807 | default: | |
acdb74a0 | 5808 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5809 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5810 | else |
ec03c1ac | 5811 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5812 | break; |
5813 | } | |
acdb74a0 | 5814 | |
caaa3122 | 5815 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5816 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5817 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5818 | |
dc305454 | 5819 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5820 | MIPS architecture (if there is one). */ |
5821 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5822 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5823 | |
32a6503c | 5824 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5825 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5826 | && info.bfd_arch_info != NULL |
5827 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5828 | { | |
5829 | switch (info.bfd_arch_info->mach) | |
5830 | { | |
5831 | case bfd_mach_mips3900: | |
ec03c1ac | 5832 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5833 | break; |
5834 | case bfd_mach_mips4100: | |
5835 | case bfd_mach_mips5000: | |
ec03c1ac | 5836 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5837 | break; |
1d06468c EZ |
5838 | case bfd_mach_mips8000: |
5839 | case bfd_mach_mips10000: | |
32a6503c KB |
5840 | /* On Irix, ELF64 executables use the N64 ABI. The |
5841 | pseudo-sections which describe the ABI aren't present | |
5842 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5843 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5844 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5845 | found_abi = MIPS_ABI_N64; |
28d169de | 5846 | else |
ec03c1ac | 5847 | found_abi = MIPS_ABI_N32; |
1d06468c | 5848 | break; |
bf64bfd6 AC |
5849 | } |
5850 | } | |
2e4ebe70 | 5851 | |
26c53e50 DJ |
5852 | /* Default 64-bit objects to N64 instead of O32. */ |
5853 | if (found_abi == MIPS_ABI_UNKNOWN | |
5854 | && info.abfd != NULL | |
5855 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5856 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5857 | found_abi = MIPS_ABI_N64; | |
5858 | ||
ec03c1ac AC |
5859 | if (gdbarch_debug) |
5860 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5861 | found_abi); | |
5862 | ||
5863 | /* What has the user specified from the command line? */ | |
5864 | wanted_abi = global_mips_abi (); | |
5865 | if (gdbarch_debug) | |
5866 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5867 | wanted_abi); | |
2e4ebe70 DJ |
5868 | |
5869 | /* Now that we have found what the ABI for this binary would be, | |
5870 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5871 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5872 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5873 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5874 | mips_abi = found_abi; | |
5875 | else | |
5876 | mips_abi = MIPS_ABI_O32; | |
5877 | if (gdbarch_debug) | |
5878 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5879 | mips_abi); | |
2e4ebe70 | 5880 | |
ec03c1ac | 5881 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5882 | if (gdbarch_debug) |
ec03c1ac | 5883 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
5884 | "mips_gdbarch_init: " |
5885 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 5886 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 5887 | |
8d5838b5 | 5888 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5889 | #ifdef HAVE_ELF |
5890 | if (info.abfd | |
5891 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5892 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5893 | Tag_GNU_MIPS_ABI_FP); | |
5894 | #endif /* HAVE_ELF */ | |
5895 | ||
8d5838b5 AC |
5896 | if (!mips_fpu_type_auto) |
5897 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5898 | else if (elf_fpu_type != 0) |
5899 | { | |
5900 | switch (elf_fpu_type) | |
5901 | { | |
5902 | case 1: | |
5903 | fpu_type = MIPS_FPU_DOUBLE; | |
5904 | break; | |
5905 | case 2: | |
5906 | fpu_type = MIPS_FPU_SINGLE; | |
5907 | break; | |
5908 | case 3: | |
5909 | default: | |
5910 | /* Soft float or unknown. */ | |
5911 | fpu_type = MIPS_FPU_NONE; | |
5912 | break; | |
5913 | } | |
5914 | } | |
8d5838b5 AC |
5915 | else if (info.bfd_arch_info != NULL |
5916 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5917 | switch (info.bfd_arch_info->mach) | |
5918 | { | |
5919 | case bfd_mach_mips3900: | |
5920 | case bfd_mach_mips4100: | |
5921 | case bfd_mach_mips4111: | |
a9d61c86 | 5922 | case bfd_mach_mips4120: |
8d5838b5 AC |
5923 | fpu_type = MIPS_FPU_NONE; |
5924 | break; | |
5925 | case bfd_mach_mips4650: | |
5926 | fpu_type = MIPS_FPU_SINGLE; | |
5927 | break; | |
5928 | default: | |
5929 | fpu_type = MIPS_FPU_DOUBLE; | |
5930 | break; | |
5931 | } | |
5932 | else if (arches != NULL) | |
5933 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5934 | else | |
5935 | fpu_type = MIPS_FPU_DOUBLE; | |
5936 | if (gdbarch_debug) | |
5937 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5938 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5939 | |
29709017 DJ |
5940 | /* Check for blatant incompatibilities. */ |
5941 | ||
5942 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5943 | ABI. */ | |
5944 | if (info.target_desc | |
5945 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5946 | && mips_abi != MIPS_ABI_EABI32 | |
5947 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5948 | { |
5949 | if (tdesc_data != NULL) | |
5950 | tdesc_data_cleanup (tdesc_data); | |
5951 | return NULL; | |
5952 | } | |
29709017 | 5953 | |
025bb325 | 5954 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
5955 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
5956 | arches != NULL; | |
5957 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5958 | { | |
5959 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5960 | using. */ |
9103eae0 | 5961 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5962 | continue; |
9103eae0 | 5963 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5964 | continue; |
719ec221 AC |
5965 | /* Need to be pedantic about which register virtual size is |
5966 | used. */ | |
5967 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5968 | != mips64_transfers_32bit_regs_p) | |
5969 | continue; | |
8d5838b5 AC |
5970 | /* Be pedantic about which FPU is selected. */ |
5971 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5972 | continue; | |
f8b73d13 DJ |
5973 | |
5974 | if (tdesc_data != NULL) | |
5975 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5976 | return arches->gdbarch; |
c2d11a7d JM |
5977 | } |
5978 | ||
102182a9 | 5979 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5980 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5981 | gdbarch = gdbarch_alloc (&info, tdep); | |
5982 | tdep->elf_flags = elf_flags; | |
719ec221 | 5983 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5984 | tdep->found_abi = found_abi; |
5985 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5986 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5987 | tdep->register_size_valid_p = 0; |
5988 | tdep->register_size = 0; | |
50e8a0d5 HZ |
5989 | tdep->gregset = NULL; |
5990 | tdep->gregset64 = NULL; | |
5991 | tdep->fpregset = NULL; | |
5992 | tdep->fpregset64 = NULL; | |
29709017 DJ |
5993 | |
5994 | if (info.target_desc) | |
5995 | { | |
5996 | /* Some useful properties can be inferred from the target. */ | |
5997 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5998 | { | |
5999 | tdep->register_size_valid_p = 1; | |
6000 | tdep->register_size = 4; | |
6001 | } | |
6002 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
6003 | { | |
6004 | tdep->register_size_valid_p = 1; | |
6005 | tdep->register_size = 8; | |
6006 | } | |
6007 | } | |
c2d11a7d | 6008 | |
102182a9 | 6009 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
6010 | set_gdbarch_short_bit (gdbarch, 16); |
6011 | set_gdbarch_int_bit (gdbarch, 32); | |
6012 | set_gdbarch_float_bit (gdbarch, 32); | |
6013 | set_gdbarch_double_bit (gdbarch, 64); | |
6014 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
6015 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
6016 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
6017 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 6018 | |
175ff332 HZ |
6019 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
6020 | mips_ax_pseudo_register_collect); | |
6021 | set_gdbarch_ax_pseudo_register_push_stack | |
6022 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
6023 | ||
6d82d43b | 6024 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
6025 | mips_elf_make_msymbol_special); |
6026 | ||
16e109ca | 6027 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 6028 | { |
16e109ca | 6029 | const char **reg_names; |
56cea623 AC |
6030 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
6031 | struct mips_regnum); | |
f8b73d13 DJ |
6032 | if (tdesc_has_registers (info.target_desc)) |
6033 | { | |
6034 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6035 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6036 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6037 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6038 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6039 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6040 | regnum->fp_control_status = 70; | |
6041 | regnum->fp_implementation_revision = 71; | |
6042 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
6043 | reg_names = NULL; | |
6044 | } | |
6045 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
6046 | { |
6047 | regnum->fp0 = 32; | |
6048 | regnum->pc = 64; | |
6049 | regnum->cause = 65; | |
6050 | regnum->badvaddr = 66; | |
6051 | regnum->hi = 67; | |
6052 | regnum->lo = 68; | |
6053 | regnum->fp_control_status = 69; | |
6054 | regnum->fp_implementation_revision = 70; | |
6055 | num_regs = 71; | |
16e109ca | 6056 | reg_names = mips_irix_reg_names; |
56cea623 AC |
6057 | } |
6058 | else | |
6059 | { | |
6060 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6061 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6062 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6063 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6064 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6065 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6066 | regnum->fp_control_status = 70; | |
6067 | regnum->fp_implementation_revision = 71; | |
6068 | num_regs = 90; | |
16e109ca AC |
6069 | if (info.bfd_arch_info != NULL |
6070 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6071 | reg_names = mips_tx39_reg_names; | |
6072 | else | |
6073 | reg_names = mips_generic_reg_names; | |
56cea623 | 6074 | } |
3e8c568d | 6075 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
fb14de7b | 6076 | replaced by gdbarch_read_pc? */ |
f10683bb MH |
6077 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
6078 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
6079 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
6080 | set_gdbarch_num_regs (gdbarch, num_regs); | |
6081 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 6082 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 6083 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
6084 | tdep->mips_processor_reg_names = reg_names; |
6085 | tdep->regnum = regnum; | |
56cea623 | 6086 | } |
fe29b929 | 6087 | |
0dadbba0 | 6088 | switch (mips_abi) |
c2d11a7d | 6089 | { |
0dadbba0 | 6090 | case MIPS_ABI_O32: |
25ab4790 | 6091 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6092 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 6093 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6094 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6095 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6096 | set_gdbarch_long_bit (gdbarch, 32); |
6097 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6098 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6099 | break; | |
0dadbba0 | 6100 | case MIPS_ABI_O64: |
25ab4790 | 6101 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 6102 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 6103 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6104 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6105 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6106 | set_gdbarch_long_bit (gdbarch, 32); |
6107 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6108 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6109 | break; | |
0dadbba0 | 6110 | case MIPS_ABI_EABI32: |
25ab4790 | 6111 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6112 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6113 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6114 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6115 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6116 | set_gdbarch_long_bit (gdbarch, 32); |
6117 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6118 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6119 | break; | |
0dadbba0 | 6120 | case MIPS_ABI_EABI64: |
25ab4790 | 6121 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6122 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6123 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6124 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6125 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6126 | set_gdbarch_long_bit (gdbarch, 64); |
6127 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6128 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6129 | break; | |
0dadbba0 | 6130 | case MIPS_ABI_N32: |
25ab4790 | 6131 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6132 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6133 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6134 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6135 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6136 | set_gdbarch_long_bit (gdbarch, 32); |
6137 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6138 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6139 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6140 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
6141 | break; |
6142 | case MIPS_ABI_N64: | |
25ab4790 | 6143 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6144 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6145 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6146 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6147 | tdep->default_mask_address_p = 0; |
6148 | set_gdbarch_long_bit (gdbarch, 64); | |
6149 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6150 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6151 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6152 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 6153 | break; |
c2d11a7d | 6154 | default: |
e2e0b3e5 | 6155 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
6156 | } |
6157 | ||
22e47e37 FF |
6158 | /* GCC creates a pseudo-section whose name specifies the size of |
6159 | longs, since -mlong32 or -mlong64 may be used independent of | |
6160 | other options. How those options affect pointer sizes is ABI and | |
6161 | architecture dependent, so use them to override the default sizes | |
6162 | set by the ABI. This table shows the relationship between ABI, | |
6163 | -mlongXX, and size of pointers: | |
6164 | ||
6165 | ABI -mlongXX ptr bits | |
6166 | --- -------- -------- | |
6167 | o32 32 32 | |
6168 | o32 64 32 | |
6169 | n32 32 32 | |
6170 | n32 64 64 | |
6171 | o64 32 32 | |
6172 | o64 64 64 | |
6173 | n64 32 32 | |
6174 | n64 64 64 | |
6175 | eabi32 32 32 | |
6176 | eabi32 64 32 | |
6177 | eabi64 32 32 | |
6178 | eabi64 64 64 | |
6179 | ||
6180 | Note that for o32 and eabi32, pointers are always 32 bits | |
6181 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 6182 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
6183 | |
6184 | if (info.abfd != NULL) | |
6185 | { | |
6186 | int long_bit = 0; | |
6187 | ||
6188 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
6189 | if (long_bit) | |
6190 | { | |
6191 | set_gdbarch_long_bit (gdbarch, long_bit); | |
6192 | switch (mips_abi) | |
6193 | { | |
6194 | case MIPS_ABI_O32: | |
6195 | case MIPS_ABI_EABI32: | |
6196 | break; | |
6197 | case MIPS_ABI_N32: | |
6198 | case MIPS_ABI_O64: | |
6199 | case MIPS_ABI_N64: | |
6200 | case MIPS_ABI_EABI64: | |
6201 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
6202 | break; | |
6203 | default: | |
6204 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
6205 | } | |
6206 | } | |
6207 | } | |
6208 | ||
a5ea2558 AC |
6209 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6210 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6211 | comment: | |
6212 | ||
6213 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6214 | flag in object files because to do so would make it impossible to | |
102182a9 | 6215 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6216 | unnecessarily restrictive. |
361d1df0 | 6217 | |
a5ea2558 AC |
6218 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6219 | but to set this flag before gcc is built with such multilibs will | |
6220 | break too many systems.'' | |
6221 | ||
6222 | But even more unhelpfully, the default linker output target for | |
6223 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6224 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6225 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6226 | this flag to detect 32-bit mode would do the wrong thing given |
6227 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6228 | as 32-bit programs by default. */ |
a5ea2558 | 6229 | |
6c997a34 | 6230 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6231 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 6232 | |
102182a9 MS |
6233 | /* Add/remove bits from an address. The MIPS needs be careful to |
6234 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6235 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6236 | ||
58dfe9ff AC |
6237 | /* Unwind the frame. */ |
6238 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 6239 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 6240 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 6241 | |
102182a9 | 6242 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6243 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6244 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6245 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
6246 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
6247 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6248 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6249 | |
025bb325 | 6250 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 6251 | |
9710e734 AC |
6252 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6253 | replaced by a command, and all targets will default to on stack | |
6254 | (regardless of the stack's execute status). */ | |
6255 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6256 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6257 | |
87783b8b AC |
6258 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6259 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6260 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6261 | ||
f7b9e9fc AC |
6262 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6263 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6264 | |
6265 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6266 | |
97ab0fdd MR |
6267 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6268 | ||
fc0c74b1 AC |
6269 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6270 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6271 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6272 | |
a4b8ebc8 | 6273 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6274 | |
e11c53d2 | 6275 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6276 | |
9dae60cc UW |
6277 | if (mips_abi == MIPS_ABI_N32) |
6278 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
6279 | else if (mips_abi == MIPS_ABI_N64) | |
6280 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
6281 | else | |
6282 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 6283 | |
d92524f1 PM |
6284 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6285 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6286 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6287 | being used as guards for target_stopped_by_watchpoint, why not have |
6288 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6289 | is sitting on? */ |
6290 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6291 | ||
e7d6a6d2 | 6292 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6293 | |
025bb325 MS |
6294 | set_gdbarch_single_step_through_delay (gdbarch, |
6295 | mips_single_step_through_delay); | |
3352ef37 | 6296 | |
0d5de010 DJ |
6297 | /* Virtual tables. */ |
6298 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6299 | ||
29709017 DJ |
6300 | mips_register_g_packet_guesses (gdbarch); |
6301 | ||
6de918a6 | 6302 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6303 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6304 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6305 | |
5792a79b | 6306 | /* Unwind the frame. */ |
b8a22b94 DJ |
6307 | dwarf2_append_unwinders (gdbarch); |
6308 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6309 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6310 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6311 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6312 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6313 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6314 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6315 | |
f8b73d13 DJ |
6316 | if (tdesc_data) |
6317 | { | |
6318 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6319 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6320 | |
6321 | /* Override the normal target description methods to handle our | |
6322 | dual real and pseudo registers. */ | |
6323 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
6324 | set_gdbarch_register_reggroup_p (gdbarch, |
6325 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
6326 | |
6327 | num_regs = gdbarch_num_regs (gdbarch); | |
6328 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6329 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6330 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6331 | } | |
6332 | ||
6333 | /* Add ABI-specific aliases for the registers. */ | |
6334 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6335 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6336 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6337 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6338 | else | |
6339 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6340 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6341 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6342 | ||
6343 | /* Add some other standard aliases. */ | |
6344 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6345 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6346 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6347 | ||
865093a3 AR |
6348 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6349 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6350 | value_of_mips_user_reg, | |
6351 | &mips_numeric_register_aliases[i].regnum); | |
6352 | ||
4b9b3959 AC |
6353 | return gdbarch; |
6354 | } | |
6355 | ||
2e4ebe70 | 6356 | static void |
6d82d43b | 6357 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6358 | { |
6359 | struct gdbarch_info info; | |
6360 | ||
6361 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6362 | mips_gdbarch_init will take care of the rest. */ | |
6363 | gdbarch_info_init (&info); | |
6364 | gdbarch_update_p (info); | |
6365 | } | |
6366 | ||
ad188201 KB |
6367 | /* Print out which MIPS ABI is in use. */ |
6368 | ||
6369 | static void | |
1f8ca57c JB |
6370 | show_mips_abi (struct ui_file *file, |
6371 | int from_tty, | |
6372 | struct cmd_list_element *ignored_cmd, | |
6373 | const char *ignored_value) | |
ad188201 | 6374 | { |
1cf3db46 | 6375 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6376 | fprintf_filtered |
6377 | (file, | |
6378 | "The MIPS ABI is unknown because the current architecture " | |
6379 | "is not MIPS.\n"); | |
ad188201 KB |
6380 | else |
6381 | { | |
6382 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6383 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6384 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6385 | ||
6386 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6387 | fprintf_filtered |
6388 | (file, | |
6389 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6390 | actual_abi_str); |
ad188201 | 6391 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6392 | fprintf_filtered |
6393 | (file, | |
6394 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6395 | actual_abi_str); |
ad188201 KB |
6396 | else |
6397 | { | |
6398 | /* Probably shouldn't happen... */ | |
025bb325 MS |
6399 | fprintf_filtered (file, |
6400 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
6401 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 6402 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6403 | } |
6404 | } | |
6405 | } | |
6406 | ||
4b9b3959 | 6407 | static void |
72a155b4 | 6408 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6409 | { |
72a155b4 | 6410 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6411 | if (tdep != NULL) |
c2d11a7d | 6412 | { |
acdb74a0 AC |
6413 | int ef_mips_arch; |
6414 | int ef_mips_32bitmode; | |
f49e4e6d | 6415 | /* Determine the ISA. */ |
acdb74a0 AC |
6416 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6417 | { | |
6418 | case E_MIPS_ARCH_1: | |
6419 | ef_mips_arch = 1; | |
6420 | break; | |
6421 | case E_MIPS_ARCH_2: | |
6422 | ef_mips_arch = 2; | |
6423 | break; | |
6424 | case E_MIPS_ARCH_3: | |
6425 | ef_mips_arch = 3; | |
6426 | break; | |
6427 | case E_MIPS_ARCH_4: | |
93d56215 | 6428 | ef_mips_arch = 4; |
acdb74a0 AC |
6429 | break; |
6430 | default: | |
93d56215 | 6431 | ef_mips_arch = 0; |
acdb74a0 AC |
6432 | break; |
6433 | } | |
f49e4e6d | 6434 | /* Determine the size of a pointer. */ |
acdb74a0 | 6435 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6436 | fprintf_unfiltered (file, |
6437 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6438 | tdep->elf_flags); |
4b9b3959 | 6439 | fprintf_unfiltered (file, |
acdb74a0 AC |
6440 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6441 | ef_mips_32bitmode); | |
6442 | fprintf_unfiltered (file, | |
6443 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6444 | ef_mips_arch); | |
6445 | fprintf_unfiltered (file, | |
6446 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6447 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 6448 | fprintf_unfiltered (file, |
025bb325 MS |
6449 | "mips_dump_tdep: " |
6450 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6451 | mips_mask_address_p (tdep), |
4014092b | 6452 | tdep->default_mask_address_p); |
c2d11a7d | 6453 | } |
4b9b3959 AC |
6454 | fprintf_unfiltered (file, |
6455 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6456 | MIPS_DEFAULT_FPU_TYPE, | |
6457 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6458 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6459 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6460 | : "???")); | |
74ed0bb4 MD |
6461 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6462 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6463 | fprintf_unfiltered (file, |
6464 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6465 | MIPS_FPU_TYPE (gdbarch), |
6466 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6467 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6468 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6469 | : "???")); |
c2d11a7d JM |
6470 | } |
6471 | ||
025bb325 | 6472 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6473 | |
c906108c | 6474 | void |
acdb74a0 | 6475 | _initialize_mips_tdep (void) |
c906108c SS |
6476 | { |
6477 | static struct cmd_list_element *mipsfpulist = NULL; | |
6478 | struct cmd_list_element *c; | |
6479 | ||
6d82d43b | 6480 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6481 | if (MIPS_ABI_LAST + 1 |
6482 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6483 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6484 | |
4b9b3959 | 6485 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6486 | |
8d5f9dcb DJ |
6487 | mips_pdr_data = register_objfile_data (); |
6488 | ||
4eb0ad19 DJ |
6489 | /* Create feature sets with the appropriate properties. The values |
6490 | are not important. */ | |
6491 | mips_tdesc_gp32 = allocate_target_description (); | |
6492 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6493 | ||
6494 | mips_tdesc_gp64 = allocate_target_description (); | |
6495 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6496 | ||
025bb325 | 6497 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 6498 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 6499 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6500 | &setmipscmdlist, "set mips ", 0, &setlist); |
6501 | ||
6502 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6503 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6504 | &showmipscmdlist, "show mips ", 0, &showlist); |
6505 | ||
025bb325 | 6506 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6507 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6508 | &mips_abi_string, _("\ | |
6509 | Set the MIPS ABI used by this program."), _("\ | |
6510 | Show the MIPS ABI used by this program."), _("\ | |
6511 | This option can be set to one of:\n\ | |
6512 | auto - the default ABI associated with the current binary\n\ | |
6513 | o32\n\ | |
6514 | o64\n\ | |
6515 | n32\n\ | |
6516 | n64\n\ | |
6517 | eabi32\n\ | |
6518 | eabi64"), | |
6519 | mips_abi_update, | |
6520 | show_mips_abi, | |
6521 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6522 | |
c906108c SS |
6523 | /* Let the user turn off floating point and set the fence post for |
6524 | heuristic_proc_start. */ | |
6525 | ||
6526 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6527 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6528 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6529 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6530 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6531 | &mipsfpulist); |
6532 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6533 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6534 | &mipsfpulist); |
6535 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6536 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6537 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6538 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6539 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6540 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6541 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6542 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6543 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6544 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6545 | &mipsfpulist); |
6546 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6547 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6548 | &showlist); |
6549 | ||
c906108c SS |
6550 | /* We really would like to have both "0" and "unlimited" work, but |
6551 | command.c doesn't deal with that. So make it a var_zinteger | |
6552 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6553 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6554 | &heuristic_fence_post, _("\ |
6555 | Set the distance searched for the start of a function."), _("\ | |
6556 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6557 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6558 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6559 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6560 | reinit_frame_cache_sfunc, |
025bb325 MS |
6561 | NULL, /* FIXME: i18n: The distance searched for |
6562 | the start of a function is %s. */ | |
6bcadd06 | 6563 | &setlist, &showlist); |
c906108c SS |
6564 | |
6565 | /* Allow the user to control whether the upper bits of 64-bit | |
6566 | addresses should be zeroed. */ | |
7915a72c AC |
6567 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6568 | &mask_address_var, _("\ | |
6569 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6570 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 6571 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 6572 | allow GDB to determine the correct value."), |
08546159 AC |
6573 | NULL, show_mask_address, |
6574 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6575 | |
6576 | /* Allow the user to control the size of 32 bit registers within the | |
6577 | raw remote packet. */ | |
b3f42336 | 6578 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6579 | &mips64_transfers_32bit_regs_p, _("\ |
6580 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6581 | _("\ | |
6582 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6583 | _("\ | |
719ec221 AC |
6584 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6585 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6586 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6587 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
6588 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
6589 | MIPS target that transfers 32-bit | |
6590 | quantities is %s. */ | |
7915a72c | 6591 | &setlist, &showlist); |
9ace0497 | 6592 | |
025bb325 | 6593 | /* Debug this files internals. */ |
6bcadd06 | 6594 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6595 | &mips_debug, _("\ |
6596 | Set mips debugging."), _("\ | |
6597 | Show mips debugging."), _("\ | |
6598 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6599 | NULL, |
025bb325 MS |
6600 | NULL, /* FIXME: i18n: Mips debugging is |
6601 | currently %s. */ | |
6bcadd06 | 6602 | &setdebuglist, &showdebuglist); |
c906108c | 6603 | } |