Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
24e05951 | 65 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
66 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 | #define ST0_FR (1 << 26) | |
68 | ||
b0069a17 AC |
69 | /* The sizes of floating point registers. */ |
70 | ||
71 | enum | |
72 | { | |
73 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
74 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
75 | }; | |
76 | ||
1a69e1e4 DJ |
77 | enum |
78 | { | |
79 | MIPS32_REGSIZE = 4, | |
80 | MIPS64_REGSIZE = 8 | |
81 | }; | |
0dadbba0 | 82 | |
2e4ebe70 DJ |
83 | static const char *mips_abi_string; |
84 | ||
85 | static const char *mips_abi_strings[] = { | |
86 | "auto", | |
87 | "n32", | |
88 | "o32", | |
28d169de | 89 | "n64", |
2e4ebe70 DJ |
90 | "o64", |
91 | "eabi32", | |
92 | "eabi64", | |
93 | NULL | |
94 | }; | |
95 | ||
f8b73d13 DJ |
96 | /* The standard register names, and all the valid aliases for them. */ |
97 | struct register_alias | |
98 | { | |
99 | const char *name; | |
100 | int regnum; | |
101 | }; | |
102 | ||
103 | /* Aliases for o32 and most other ABIs. */ | |
104 | const struct register_alias mips_o32_aliases[] = { | |
105 | { "ta0", 12 }, | |
106 | { "ta1", 13 }, | |
107 | { "ta2", 14 }, | |
108 | { "ta3", 15 } | |
109 | }; | |
110 | ||
111 | /* Aliases for n32 and n64. */ | |
112 | const struct register_alias mips_n32_n64_aliases[] = { | |
113 | { "ta0", 8 }, | |
114 | { "ta1", 9 }, | |
115 | { "ta2", 10 }, | |
116 | { "ta3", 11 } | |
117 | }; | |
118 | ||
119 | /* Aliases for ABI-independent registers. */ | |
120 | const struct register_alias mips_register_aliases[] = { | |
121 | /* The architecture manuals specify these ABI-independent names for | |
122 | the GPRs. */ | |
123 | #define R(n) { "r" #n, n } | |
124 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
125 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
126 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
127 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
128 | #undef R | |
129 | ||
130 | /* k0 and k1 are sometimes called these instead (for "kernel | |
131 | temp"). */ | |
132 | { "kt0", 26 }, | |
133 | { "kt1", 27 }, | |
134 | ||
135 | /* This is the traditional GDB name for the CP0 status register. */ | |
136 | { "sr", MIPS_PS_REGNUM }, | |
137 | ||
138 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
139 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
140 | ||
141 | /* This is the traditional GDB name for the FCSR. */ | |
142 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
143 | }; | |
144 | ||
7a292a7a | 145 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 146 | support single-precision floating-point operations. */ |
c906108c SS |
147 | |
148 | enum mips_fpu_type | |
6d82d43b AC |
149 | { |
150 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
151 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
152 | MIPS_FPU_NONE /* No floating point. */ | |
153 | }; | |
c906108c SS |
154 | |
155 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
156 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
157 | #endif | |
158 | static int mips_fpu_type_auto = 1; | |
159 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 160 | |
9ace0497 | 161 | static int mips_debug = 0; |
7a292a7a | 162 | |
29709017 DJ |
163 | /* Properties (for struct target_desc) describing the g/G packet |
164 | layout. */ | |
165 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
166 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
167 | ||
4eb0ad19 DJ |
168 | struct target_desc *mips_tdesc_gp32; |
169 | struct target_desc *mips_tdesc_gp64; | |
170 | ||
c2d11a7d JM |
171 | /* MIPS specific per-architecture information */ |
172 | struct gdbarch_tdep | |
6d82d43b AC |
173 | { |
174 | /* from the elf header */ | |
175 | int elf_flags; | |
176 | ||
177 | /* mips options */ | |
178 | enum mips_abi mips_abi; | |
179 | enum mips_abi found_abi; | |
180 | enum mips_fpu_type mips_fpu_type; | |
181 | int mips_last_arg_regnum; | |
182 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
183 | int default_mask_address_p; |
184 | /* Is the target using 64-bit raw integer registers but only | |
185 | storing a left-aligned 32-bit value in each? */ | |
186 | int mips64_transfers_32bit_regs_p; | |
187 | /* Indexes for various registers. IRIX and embedded have | |
188 | different values. This contains the "public" fields. Don't | |
189 | add any that do not need to be public. */ | |
190 | const struct mips_regnum *regnum; | |
191 | /* Register names table for the current register set. */ | |
192 | const char **mips_processor_reg_names; | |
29709017 DJ |
193 | |
194 | /* The size of register data available from the target, if known. | |
195 | This doesn't quite obsolete the manual | |
196 | mips64_transfers_32bit_regs_p, since that is documented to force | |
197 | left alignment even for big endian (very strange). */ | |
198 | int register_size_valid_p; | |
199 | int register_size; | |
6d82d43b | 200 | }; |
c2d11a7d | 201 | |
fed7ba43 JB |
202 | static int |
203 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
2244f671 | 204 | const void *from) |
fed7ba43 JB |
205 | { |
206 | return 1; | |
207 | } | |
208 | ||
209 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
210 | They are implemented as a pair of 64bit doubles where the high | |
211 | part holds the result of the operation rounded to double, and | |
212 | the low double holds the difference between the exact result and | |
213 | the rounded result. So "high" + "low" contains the result with | |
214 | added precision. Unfortunately, the floatformat structure used | |
215 | by GDB is not powerful enough to describe this format. As a temporary | |
216 | measure, we define a 128bit floatformat that only uses the high part. | |
217 | We lose a bit of precision but that's probably the best we can do | |
218 | for now with the current infrastructure. */ | |
219 | ||
220 | static const struct floatformat floatformat_n32n64_long_double_big = | |
221 | { | |
222 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
223 | floatformat_intbit_no, | |
8da61cc4 | 224 | "floatformat_n32n64_long_double_big", |
fed7ba43 JB |
225 | n32n64_floatformat_always_valid |
226 | }; | |
227 | ||
8da61cc4 DJ |
228 | static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] = |
229 | { | |
230 | &floatformat_n32n64_long_double_big, | |
231 | &floatformat_n32n64_long_double_big | |
232 | }; | |
233 | ||
56cea623 AC |
234 | const struct mips_regnum * |
235 | mips_regnum (struct gdbarch *gdbarch) | |
236 | { | |
237 | return gdbarch_tdep (gdbarch)->regnum; | |
238 | } | |
239 | ||
240 | static int | |
241 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
242 | { | |
243 | return mips_regnum (gdbarch)->fp0 + 12; | |
244 | } | |
245 | ||
0dadbba0 | 246 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 247 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 248 | |
c2d11a7d | 249 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 250 | |
c2d11a7d | 251 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 252 | |
c2d11a7d | 253 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 254 | |
95404a3e AC |
255 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
256 | functions to test, set, or clear bit 0 of addresses. */ | |
257 | ||
258 | static CORE_ADDR | |
259 | is_mips16_addr (CORE_ADDR addr) | |
260 | { | |
261 | return ((addr) & 1); | |
262 | } | |
263 | ||
95404a3e AC |
264 | static CORE_ADDR |
265 | unmake_mips16_addr (CORE_ADDR addr) | |
266 | { | |
5b652102 | 267 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
268 | } |
269 | ||
d1973055 KB |
270 | /* Return the MIPS ABI associated with GDBARCH. */ |
271 | enum mips_abi | |
272 | mips_abi (struct gdbarch *gdbarch) | |
273 | { | |
274 | return gdbarch_tdep (gdbarch)->mips_abi; | |
275 | } | |
276 | ||
4246e332 | 277 | int |
1b13c4f6 | 278 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 279 | { |
29709017 DJ |
280 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
281 | ||
282 | /* If we know how big the registers are, use that size. */ | |
283 | if (tdep->register_size_valid_p) | |
284 | return tdep->register_size; | |
285 | ||
286 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
287 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
288 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
289 | } | |
290 | ||
480d3dd2 AC |
291 | /* Return the currently configured (or set) saved register size. */ |
292 | ||
e6bc2e8a | 293 | unsigned int |
13326b4e | 294 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 295 | { |
1a69e1e4 DJ |
296 | switch (mips_abi (gdbarch)) |
297 | { | |
298 | case MIPS_ABI_EABI32: | |
299 | case MIPS_ABI_O32: | |
300 | return 4; | |
301 | case MIPS_ABI_N32: | |
302 | case MIPS_ABI_N64: | |
303 | case MIPS_ABI_O64: | |
304 | case MIPS_ABI_EABI64: | |
305 | return 8; | |
306 | case MIPS_ABI_UNKNOWN: | |
307 | case MIPS_ABI_LAST: | |
308 | default: | |
309 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
310 | } | |
d929b26f AC |
311 | } |
312 | ||
71b8ef93 | 313 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 314 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 315 | "info" field is used for this purpose. |
5a89d8aa | 316 | |
95f1da47 | 317 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
318 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
319 | minimal symbol to mark it as a 16-bit function | |
320 | ||
f594e5e9 | 321 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 322 | |
5a89d8aa | 323 | static void |
6d82d43b AC |
324 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
325 | { | |
326 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
327 | { | |
328 | MSYMBOL_INFO (msym) = (char *) | |
329 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
330 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
331 | } | |
5a89d8aa MS |
332 | } |
333 | ||
71b8ef93 MS |
334 | static int |
335 | msymbol_is_special (struct minimal_symbol *msym) | |
336 | { | |
337 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
338 | } | |
339 | ||
88658117 AC |
340 | /* XFER a value from the big/little/left end of the register. |
341 | Depending on the size of the value it might occupy the entire | |
342 | register or just part of it. Make an allowance for this, aligning | |
343 | things accordingly. */ | |
344 | ||
345 | static void | |
346 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
870cd05e MK |
347 | enum bfd_endian endian, gdb_byte *in, |
348 | const gdb_byte *out, int buf_offset) | |
88658117 | 349 | { |
88658117 | 350 | int reg_offset = 0; |
72a155b4 UW |
351 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
352 | ||
353 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
354 | /* Need to transfer the left or right part of the register, based on |
355 | the targets byte order. */ | |
88658117 AC |
356 | switch (endian) |
357 | { | |
358 | case BFD_ENDIAN_BIG: | |
72a155b4 | 359 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
360 | break; |
361 | case BFD_ENDIAN_LITTLE: | |
362 | reg_offset = 0; | |
363 | break; | |
6d82d43b | 364 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
365 | reg_offset = 0; |
366 | break; | |
367 | default: | |
e2e0b3e5 | 368 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
369 | } |
370 | if (mips_debug) | |
cb1d2653 AC |
371 | fprintf_unfiltered (gdb_stderr, |
372 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
373 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
374 | if (mips_debug && out != NULL) |
375 | { | |
376 | int i; | |
cb1d2653 | 377 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 378 | for (i = 0; i < length; i++) |
cb1d2653 | 379 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
380 | } |
381 | if (in != NULL) | |
6d82d43b AC |
382 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
383 | in + buf_offset); | |
88658117 | 384 | if (out != NULL) |
6d82d43b AC |
385 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
386 | out + buf_offset); | |
88658117 AC |
387 | if (mips_debug && in != NULL) |
388 | { | |
389 | int i; | |
cb1d2653 | 390 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 391 | for (i = 0; i < length; i++) |
cb1d2653 | 392 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
393 | } |
394 | if (mips_debug) | |
395 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
396 | } | |
397 | ||
dd824b04 DJ |
398 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
399 | compatiblity mode. A return value of 1 means that we have | |
400 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
401 | ||
402 | static int | |
9c9acae0 | 403 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 404 | { |
72a155b4 | 405 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
406 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
407 | meaningful. */ | |
72a155b4 | 408 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
409 | return 0; |
410 | ||
411 | #if 0 | |
412 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
413 | in all the places we deal with FP registers. PR gdb/413. */ | |
414 | /* Otherwise check the FR bit in the status register - it controls | |
415 | the FP compatiblity mode. If it is clear we are in compatibility | |
416 | mode. */ | |
9c9acae0 | 417 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
418 | return 1; |
419 | #endif | |
361d1df0 | 420 | |
dd824b04 DJ |
421 | return 0; |
422 | } | |
423 | ||
7a292a7a | 424 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 425 | |
a14ed312 | 426 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 427 | |
a14ed312 | 428 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 429 | |
67b2c998 DJ |
430 | static struct type *mips_float_register_type (void); |
431 | static struct type *mips_double_register_type (void); | |
432 | ||
acdb74a0 AC |
433 | /* The list of available "set mips " and "show mips " commands */ |
434 | ||
435 | static struct cmd_list_element *setmipscmdlist = NULL; | |
436 | static struct cmd_list_element *showmipscmdlist = NULL; | |
437 | ||
5e2e9765 KB |
438 | /* Integer registers 0 thru 31 are handled explicitly by |
439 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 440 | are listed in the following tables. */ |
691c0433 | 441 | |
6d82d43b AC |
442 | enum |
443 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
444 | |
445 | /* Generic MIPS. */ | |
446 | ||
447 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
448 | "sr", "lo", "hi", "bad", "cause", "pc", |
449 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
450 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
451 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
452 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
453 | "fsr", "fir", "" /*"fp" */ , "", | |
454 | "", "", "", "", "", "", "", "", | |
455 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
456 | }; |
457 | ||
458 | /* Names of IDT R3041 registers. */ | |
459 | ||
460 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
461 | "sr", "lo", "hi", "bad", "cause", "pc", |
462 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
463 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
464 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
465 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
466 | "fsr", "fir", "", /*"fp" */ "", | |
467 | "", "", "bus", "ccfg", "", "", "", "", | |
468 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
469 | }; |
470 | ||
471 | /* Names of tx39 registers. */ | |
472 | ||
473 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
474 | "sr", "lo", "hi", "bad", "cause", "pc", |
475 | "", "", "", "", "", "", "", "", | |
476 | "", "", "", "", "", "", "", "", | |
477 | "", "", "", "", "", "", "", "", | |
478 | "", "", "", "", "", "", "", "", | |
479 | "", "", "", "", | |
480 | "", "", "", "", "", "", "", "", | |
481 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
482 | }; |
483 | ||
484 | /* Names of IRIX registers. */ | |
485 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
486 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
487 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
488 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
489 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
490 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
491 | }; |
492 | ||
cce74817 | 493 | |
5e2e9765 | 494 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 495 | static const char * |
5e2e9765 | 496 | mips_register_name (int regno) |
cce74817 | 497 | { |
691c0433 | 498 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
499 | /* GPR names for all ABIs other than n32/n64. */ |
500 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
501 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
502 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
503 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
504 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
505 | }; |
506 | ||
507 | /* GPR names for n32 and n64 ABIs. */ | |
508 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
509 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
510 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
511 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
512 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
513 | }; |
514 | ||
515 | enum mips_abi abi = mips_abi (current_gdbarch); | |
516 | ||
f57d151a UW |
517 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
518 | but then don't make the raw register names visible. */ | |
519 | int rawnum = regno % gdbarch_num_regs (current_gdbarch); | |
520 | if (regno < gdbarch_num_regs (current_gdbarch)) | |
a4b8ebc8 AC |
521 | return ""; |
522 | ||
5e2e9765 KB |
523 | /* The MIPS integer registers are always mapped from 0 to 31. The |
524 | names of the registers (which reflects the conventions regarding | |
525 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 526 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
527 | { |
528 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 529 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 530 | else |
a4b8ebc8 | 531 | return mips_gpr_names[rawnum]; |
5e2e9765 | 532 | } |
f8b73d13 DJ |
533 | else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch))) |
534 | return tdesc_register_name (rawnum); | |
f57d151a | 535 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (current_gdbarch)) |
691c0433 AC |
536 | { |
537 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
538 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
539 | } | |
5e2e9765 KB |
540 | else |
541 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 542 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 543 | } |
5e2e9765 | 544 | |
a4b8ebc8 | 545 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 546 | |
a4b8ebc8 AC |
547 | static int |
548 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
549 | struct reggroup *reggroup) | |
550 | { | |
551 | int vector_p; | |
552 | int float_p; | |
553 | int raw_p; | |
72a155b4 UW |
554 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
555 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
556 | if (reggroup == all_reggroup) |
557 | return pseudo; | |
558 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
559 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
560 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
561 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
562 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
563 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
564 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
565 | return 0; |
566 | if (reggroup == float_reggroup) | |
567 | return float_p && pseudo; | |
568 | if (reggroup == vector_reggroup) | |
569 | return vector_p && pseudo; | |
570 | if (reggroup == general_reggroup) | |
571 | return (!vector_p && !float_p) && pseudo; | |
572 | /* Save the pseudo registers. Need to make certain that any code | |
573 | extracting register values from a saved register cache also uses | |
574 | pseudo registers. */ | |
575 | if (reggroup == save_reggroup) | |
576 | return raw_p && pseudo; | |
577 | /* Restore the same pseudo register. */ | |
578 | if (reggroup == restore_reggroup) | |
579 | return raw_p && pseudo; | |
6d82d43b | 580 | return 0; |
a4b8ebc8 AC |
581 | } |
582 | ||
f8b73d13 DJ |
583 | /* Return the groups that a MIPS register can be categorised into. |
584 | This version is only used if we have a target description which | |
585 | describes real registers (and their groups). */ | |
586 | ||
587 | static int | |
588 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
589 | struct reggroup *reggroup) | |
590 | { | |
591 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
592 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
593 | int ret; | |
594 | ||
595 | /* Only save, restore, and display the pseudo registers. Need to | |
596 | make certain that any code extracting register values from a | |
597 | saved register cache also uses pseudo registers. | |
598 | ||
599 | Note: saving and restoring the pseudo registers is slightly | |
600 | strange; if we have 64 bits, we should save and restore all | |
601 | 64 bits. But this is hard and has little benefit. */ | |
602 | if (!pseudo) | |
603 | return 0; | |
604 | ||
605 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
606 | if (ret != -1) | |
607 | return ret; | |
608 | ||
609 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
610 | } | |
611 | ||
a4b8ebc8 | 612 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 613 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 614 | registers. Take care of alignment and size problems. */ |
c5aa993b | 615 | |
a4b8ebc8 AC |
616 | static void |
617 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 618 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 619 | { |
72a155b4 UW |
620 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
621 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
622 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 623 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 624 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
625 | else if (register_size (gdbarch, rawnum) > |
626 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
627 | { |
628 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 629 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
630 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
631 | else | |
632 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
633 | } | |
634 | else | |
e2e0b3e5 | 635 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
636 | } |
637 | ||
638 | static void | |
6d82d43b AC |
639 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
640 | struct regcache *regcache, int cookednum, | |
47a35522 | 641 | const gdb_byte *buf) |
a4b8ebc8 | 642 | { |
72a155b4 UW |
643 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
644 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
645 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 646 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 647 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
648 | else if (register_size (gdbarch, rawnum) > |
649 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
650 | { |
651 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 652 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
653 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
654 | else | |
655 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
656 | } | |
657 | else | |
e2e0b3e5 | 658 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 659 | } |
c5aa993b | 660 | |
c906108c | 661 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 662 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
663 | |
664 | /* Heuristic_proc_start may hunt through the text section for a long | |
665 | time across a 2400 baud serial line. Allows the user to limit this | |
666 | search. */ | |
667 | ||
668 | static unsigned int heuristic_fence_post = 0; | |
669 | ||
46cd78fb | 670 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
671 | register N. NOTE: This defines the pseudo register type so need to |
672 | rebuild the architecture vector. */ | |
43e526b9 JM |
673 | |
674 | static int mips64_transfers_32bit_regs_p = 0; | |
675 | ||
719ec221 AC |
676 | static void |
677 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
678 | struct cmd_list_element *c) | |
43e526b9 | 679 | { |
719ec221 AC |
680 | struct gdbarch_info info; |
681 | gdbarch_info_init (&info); | |
682 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
683 | instead of relying on globals. Doing that would let generic code | |
684 | handle the search for this specific architecture. */ | |
685 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 686 | { |
719ec221 | 687 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 688 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 689 | } |
a4b8ebc8 AC |
690 | } |
691 | ||
47ebcfbe | 692 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 693 | |
ff2e87ac AC |
694 | static int |
695 | mips_convert_register_p (int regnum, struct type *type) | |
696 | { | |
4c6b5505 | 697 | return (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
719ec221 | 698 | && register_size (current_gdbarch, regnum) == 4 |
f57d151a UW |
699 | && (regnum % gdbarch_num_regs (current_gdbarch)) |
700 | >= mips_regnum (current_gdbarch)->fp0 | |
701 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
702 | < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 703 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
704 | } |
705 | ||
42c466d7 | 706 | static void |
ff2e87ac | 707 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 708 | struct type *type, gdb_byte *to) |
102182a9 | 709 | { |
47a35522 MK |
710 | get_frame_register (frame, regnum + 0, to + 4); |
711 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
712 | } |
713 | ||
42c466d7 | 714 | static void |
ff2e87ac | 715 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 716 | struct type *type, const gdb_byte *from) |
102182a9 | 717 | { |
47a35522 MK |
718 | put_frame_register (frame, regnum + 0, from + 4); |
719 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
720 | } |
721 | ||
a4b8ebc8 AC |
722 | /* Return the GDB type object for the "standard" data type of data in |
723 | register REG. */ | |
78fde5f8 KB |
724 | |
725 | static struct type * | |
a4b8ebc8 AC |
726 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
727 | { | |
72a155b4 UW |
728 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
729 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
730 | && (regnum % gdbarch_num_regs (gdbarch)) | |
731 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 732 | { |
5ef80fb0 | 733 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 734 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
735 | if (mips_isa_regsize (gdbarch) == 4) |
736 | return builtin_type_ieee_single; | |
737 | else | |
738 | return builtin_type_ieee_double; | |
a6425924 | 739 | } |
72a155b4 | 740 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
741 | { |
742 | /* The raw or ISA registers. These are all sized according to | |
743 | the ISA regsize. */ | |
744 | if (mips_isa_regsize (gdbarch) == 4) | |
745 | return builtin_type_int32; | |
746 | else | |
747 | return builtin_type_int64; | |
748 | } | |
78fde5f8 | 749 | else |
d5ac5a39 AC |
750 | { |
751 | /* The cooked or ABI registers. These are sized according to | |
752 | the ABI (with a few complications). */ | |
72a155b4 UW |
753 | if (regnum >= (gdbarch_num_regs (gdbarch) |
754 | + mips_regnum (gdbarch)->fp_control_status) | |
755 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
756 | /* The pseudo/cooked view of the embedded registers is always |
757 | 32-bit. The raw view is handled below. */ | |
758 | return builtin_type_int32; | |
759 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
760 | /* The target, while possibly using a 64-bit register buffer, | |
761 | is only transfering 32-bits of each integer register. | |
762 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
763 | return builtin_type_int32; | |
764 | else if (mips_abi_regsize (gdbarch) == 4) | |
765 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
766 | 32- or 64-bit). */ | |
767 | return builtin_type_int32; | |
768 | else | |
769 | /* 64-bit ABI. */ | |
770 | return builtin_type_int64; | |
771 | } | |
78fde5f8 KB |
772 | } |
773 | ||
f8b73d13 DJ |
774 | /* Return the GDB type for the pseudo register REGNUM, which is the |
775 | ABI-level view. This function is only called if there is a target | |
776 | description which includes registers, so we know precisely the | |
777 | types of hardware registers. */ | |
778 | ||
779 | static struct type * | |
780 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
781 | { | |
782 | const int num_regs = gdbarch_num_regs (gdbarch); | |
783 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
784 | int rawnum = regnum % num_regs; | |
785 | struct type *rawtype; | |
786 | ||
787 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
788 | ||
789 | /* Absent registers are still absent. */ | |
790 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
791 | if (TYPE_LENGTH (rawtype) == 0) | |
792 | return rawtype; | |
793 | ||
794 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
795 | /* Present the floating point registers however the hardware did; | |
796 | do not try to convert between FPU layouts. */ | |
797 | return rawtype; | |
798 | ||
799 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
800 | { | |
801 | /* The pseudo/cooked view of embedded registers is always | |
802 | 32-bit, even if the target transfers 64-bit values for them. | |
803 | New targets relying on XML descriptions should only transfer | |
804 | the necessary 32 bits, but older versions of GDB expected 64, | |
805 | so allow the target to provide 64 bits without interfering | |
806 | with the displayed type. */ | |
807 | return builtin_type_int32; | |
808 | } | |
809 | ||
810 | /* Use pointer types for registers if we can. For n32 we can not, | |
811 | since we do not have a 64-bit pointer type. */ | |
812 | if (mips_abi_regsize (gdbarch) == TYPE_LENGTH (builtin_type_void_data_ptr)) | |
813 | { | |
814 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
815 | return builtin_type_void_data_ptr; | |
816 | else if (rawnum == MIPS_EMBED_PC_REGNUM) | |
817 | return builtin_type_void_func_ptr; | |
818 | } | |
819 | ||
820 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
821 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
822 | return builtin_type_int32; | |
823 | ||
824 | /* For all other registers, pass through the hardware type. */ | |
825 | return rawtype; | |
826 | } | |
bcb0cc15 | 827 | |
c906108c | 828 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 829 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
830 | |
831 | static int | |
480d3dd2 | 832 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
833 | { |
834 | switch (mask_address_var) | |
835 | { | |
7f19b9a2 | 836 | case AUTO_BOOLEAN_TRUE: |
4014092b | 837 | return 1; |
7f19b9a2 | 838 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
839 | return 0; |
840 | break; | |
7f19b9a2 | 841 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 842 | return tdep->default_mask_address_p; |
4014092b | 843 | default: |
e2e0b3e5 | 844 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 845 | return -1; |
361d1df0 | 846 | } |
4014092b AC |
847 | } |
848 | ||
849 | static void | |
08546159 AC |
850 | show_mask_address (struct ui_file *file, int from_tty, |
851 | struct cmd_list_element *c, const char *value) | |
4014092b | 852 | { |
480d3dd2 | 853 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
08546159 AC |
854 | |
855 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
856 | switch (mask_address_var) |
857 | { | |
7f19b9a2 | 858 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
859 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
860 | break; | |
7f19b9a2 | 861 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
862 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
863 | break; | |
7f19b9a2 | 864 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
865 | printf_filtered |
866 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
867 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
868 | break; |
869 | default: | |
e2e0b3e5 | 870 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 871 | break; |
361d1df0 | 872 | } |
4014092b | 873 | } |
c906108c | 874 | |
c906108c SS |
875 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
876 | ||
0fe7e7c8 AC |
877 | int |
878 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
879 | { |
880 | struct minimal_symbol *sym; | |
881 | ||
882 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 883 | if (is_mips16_addr (memaddr)) |
c906108c SS |
884 | return 1; |
885 | ||
886 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
887 | the high bit of the info field. Use this to decide if the function is | |
888 | MIPS16 or normal MIPS. */ | |
889 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
890 | if (sym) | |
71b8ef93 | 891 | return msymbol_is_special (sym); |
c906108c SS |
892 | else |
893 | return 0; | |
894 | } | |
895 | ||
b2fa5097 | 896 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
897 | all registers should be sign extended for simplicity? */ |
898 | ||
899 | static CORE_ADDR | |
61a1198a | 900 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 901 | { |
61a1198a UW |
902 | ULONGEST pc; |
903 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
904 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
905 | return pc; | |
b6cb9035 AC |
906 | } |
907 | ||
58dfe9ff AC |
908 | static CORE_ADDR |
909 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
910 | { | |
72a155b4 UW |
911 | return frame_unwind_register_signed |
912 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
913 | } |
914 | ||
30244cd8 UW |
915 | static CORE_ADDR |
916 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
917 | { | |
72a155b4 UW |
918 | return frame_unwind_register_signed |
919 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
920 | } |
921 | ||
edfae063 AC |
922 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
923 | dummy frame. The frame ID's base needs to match the TOS value | |
924 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
925 | breakpoint. */ | |
926 | ||
927 | static struct frame_id | |
928 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
929 | { | |
f57d151a UW |
930 | return frame_id_build |
931 | (frame_unwind_register_signed (next_frame, | |
72a155b4 | 932 | gdbarch_num_regs (gdbarch) |
f57d151a UW |
933 | + MIPS_SP_REGNUM), |
934 | frame_pc_unwind (next_frame)); | |
58dfe9ff AC |
935 | } |
936 | ||
b6cb9035 | 937 | static void |
61a1198a | 938 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 939 | { |
61a1198a UW |
940 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
941 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 942 | } |
c906108c | 943 | |
c906108c SS |
944 | /* Fetch and return instruction from the specified location. If the PC |
945 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
946 | ||
d37cca3d | 947 | static ULONGEST |
acdb74a0 | 948 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 949 | { |
47a35522 | 950 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
951 | int instlen; |
952 | int status; | |
953 | ||
0fe7e7c8 | 954 | if (mips_pc_is_mips16 (addr)) |
c906108c | 955 | { |
95ac2dcf | 956 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 957 | addr = unmake_mips16_addr (addr); |
c906108c SS |
958 | } |
959 | else | |
95ac2dcf | 960 | instlen = MIPS_INSN32_SIZE; |
359a9262 | 961 | status = read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
962 | if (status) |
963 | memory_error (status, addr); | |
964 | return extract_unsigned_integer (buf, instlen); | |
965 | } | |
966 | ||
c906108c | 967 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
968 | #define mips32_op(x) (x >> 26) |
969 | #define itype_op(x) (x >> 26) | |
970 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 971 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 972 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 973 | |
e135b889 DJ |
974 | #define jtype_op(x) (x >> 26) |
975 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 976 | |
e135b889 DJ |
977 | #define rtype_op(x) (x >> 26) |
978 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
979 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
980 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
981 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
982 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 983 | |
06987e64 MK |
984 | static LONGEST |
985 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 986 | { |
06987e64 | 987 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
988 | } |
989 | ||
f49e4e6d MS |
990 | /* Determine where to set a single step breakpoint while considering |
991 | branch prediction. */ | |
5a89d8aa | 992 | static CORE_ADDR |
0b1b3e42 | 993 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b JM |
994 | { |
995 | unsigned long inst; | |
996 | int op; | |
997 | inst = mips_fetch_instruction (pc); | |
e135b889 | 998 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 999 | { |
e135b889 | 1000 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1001 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1002 | { |
e135b889 | 1003 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1004 | switch (op) |
1005 | { | |
e135b889 DJ |
1006 | case 0: /* BEQL */ |
1007 | goto equal_branch; | |
1008 | case 1: /* BNEL */ | |
1009 | goto neq_branch; | |
1010 | case 2: /* BLEZL */ | |
1011 | goto less_branch; | |
313628cc | 1012 | case 3: /* BGTZL */ |
e135b889 | 1013 | goto greater_branch; |
c5aa993b JM |
1014 | default: |
1015 | pc += 4; | |
c906108c SS |
1016 | } |
1017 | } | |
e135b889 | 1018 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1019 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1020 | { |
1021 | int tf = itype_rt (inst) & 0x01; | |
1022 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 1023 | int fcrcs = |
72a155b4 UW |
1024 | get_frame_register_signed (frame, |
1025 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 1026 | fp_control_status); |
e135b889 DJ |
1027 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1028 | ||
1029 | if (((cond >> cnum) & 0x01) == tf) | |
1030 | pc += mips32_relative_offset (inst) + 4; | |
1031 | else | |
1032 | pc += 8; | |
1033 | } | |
c5aa993b JM |
1034 | else |
1035 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1036 | } |
1037 | else | |
c5aa993b JM |
1038 | { /* This gets way messy */ |
1039 | ||
c906108c | 1040 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1041 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1042 | { |
c5aa993b JM |
1043 | case 0: /* SPECIAL */ |
1044 | op = rtype_funct (inst); | |
1045 | switch (op) | |
1046 | { | |
1047 | case 8: /* JR */ | |
1048 | case 9: /* JALR */ | |
6c997a34 | 1049 | /* Set PC to that address */ |
0b1b3e42 | 1050 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b JM |
1051 | break; |
1052 | default: | |
1053 | pc += 4; | |
1054 | } | |
1055 | ||
6d82d43b | 1056 | break; /* end SPECIAL */ |
c5aa993b | 1057 | case 1: /* REGIMM */ |
c906108c | 1058 | { |
e135b889 DJ |
1059 | op = itype_rt (inst); /* branch condition */ |
1060 | switch (op) | |
c906108c | 1061 | { |
c5aa993b | 1062 | case 0: /* BLTZ */ |
e135b889 DJ |
1063 | case 2: /* BLTZL */ |
1064 | case 16: /* BLTZAL */ | |
c5aa993b | 1065 | case 18: /* BLTZALL */ |
c906108c | 1066 | less_branch: |
0b1b3e42 | 1067 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1068 | pc += mips32_relative_offset (inst) + 4; |
1069 | else | |
1070 | pc += 8; /* after the delay slot */ | |
1071 | break; | |
e135b889 | 1072 | case 1: /* BGEZ */ |
c5aa993b JM |
1073 | case 3: /* BGEZL */ |
1074 | case 17: /* BGEZAL */ | |
1075 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1076 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1077 | pc += mips32_relative_offset (inst) + 4; |
1078 | else | |
1079 | pc += 8; /* after the delay slot */ | |
1080 | break; | |
e135b889 | 1081 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1082 | default: |
1083 | pc += 4; | |
c906108c SS |
1084 | } |
1085 | } | |
6d82d43b | 1086 | break; /* end REGIMM */ |
c5aa993b JM |
1087 | case 2: /* J */ |
1088 | case 3: /* JAL */ | |
1089 | { | |
1090 | unsigned long reg; | |
1091 | reg = jtype_target (inst) << 2; | |
e135b889 | 1092 | /* Upper four bits get never changed... */ |
5b652102 | 1093 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1094 | } |
c5aa993b JM |
1095 | break; |
1096 | /* FIXME case JALX : */ | |
1097 | { | |
1098 | unsigned long reg; | |
1099 | reg = jtype_target (inst) << 2; | |
5b652102 | 1100 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1101 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1102 | } | |
c5aa993b | 1103 | break; /* The new PC will be alternate mode */ |
e135b889 | 1104 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1105 | equal_branch: |
0b1b3e42 UW |
1106 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1107 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1108 | pc += mips32_relative_offset (inst) + 4; |
1109 | else | |
1110 | pc += 8; | |
1111 | break; | |
e135b889 | 1112 | case 5: /* BNE, BNEL */ |
c5aa993b | 1113 | neq_branch: |
0b1b3e42 UW |
1114 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1115 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1116 | pc += mips32_relative_offset (inst) + 4; |
1117 | else | |
1118 | pc += 8; | |
1119 | break; | |
e135b889 | 1120 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1121 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1122 | pc += mips32_relative_offset (inst) + 4; |
1123 | else | |
1124 | pc += 8; | |
1125 | break; | |
1126 | case 7: | |
e135b889 DJ |
1127 | default: |
1128 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1129 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1130 | pc += mips32_relative_offset (inst) + 4; |
1131 | else | |
1132 | pc += 8; | |
1133 | break; | |
c5aa993b JM |
1134 | } /* switch */ |
1135 | } /* else */ | |
1136 | return pc; | |
1137 | } /* mips32_next_pc */ | |
c906108c SS |
1138 | |
1139 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1140 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1141 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1142 | We dont want to set a single step instruction on the extend instruction | |
1143 | either. | |
c5aa993b | 1144 | */ |
c906108c SS |
1145 | |
1146 | /* Lots of mips16 instruction formats */ | |
1147 | /* Predicting jumps requires itype,ritype,i8type | |
1148 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1149 | */ |
c906108c SS |
1150 | enum mips16_inst_fmts |
1151 | { | |
c5aa993b JM |
1152 | itype, /* 0 immediate 5,10 */ |
1153 | ritype, /* 1 5,3,8 */ | |
1154 | rrtype, /* 2 5,3,3,5 */ | |
1155 | rritype, /* 3 5,3,3,5 */ | |
1156 | rrrtype, /* 4 5,3,3,3,2 */ | |
1157 | rriatype, /* 5 5,3,3,1,4 */ | |
1158 | shifttype, /* 6 5,3,3,3,2 */ | |
1159 | i8type, /* 7 5,3,8 */ | |
1160 | i8movtype, /* 8 5,3,3,5 */ | |
1161 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1162 | i64type, /* 10 5,3,8 */ | |
1163 | ri64type, /* 11 5,3,3,5 */ | |
1164 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1165 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1166 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1167 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1168 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1169 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1170 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1171 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1172 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1173 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1174 | }; | |
12f02c2a AC |
1175 | /* I am heaping all the fields of the formats into one structure and |
1176 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1177 | struct upk_mips16 |
6d82d43b AC |
1178 | { |
1179 | CORE_ADDR offset; | |
1180 | unsigned int regx; /* Function in i8 type */ | |
1181 | unsigned int regy; | |
1182 | }; | |
c906108c SS |
1183 | |
1184 | ||
12f02c2a AC |
1185 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1186 | for the bits which make up the immediatate extension. */ | |
c906108c | 1187 | |
12f02c2a AC |
1188 | static CORE_ADDR |
1189 | extended_offset (unsigned int extension) | |
c906108c | 1190 | { |
12f02c2a | 1191 | CORE_ADDR value; |
c5aa993b JM |
1192 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1193 | value = value << 6; | |
1194 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1195 | value = value << 5; | |
1196 | value |= extension & 0x01f; /* extract 4:0 */ | |
1197 | return value; | |
c906108c SS |
1198 | } |
1199 | ||
1200 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1201 | instruction. It won't malfunction, but why make excess remote memory |
1202 | references? If the immediate operands get sign extended or something, | |
1203 | do it after the extension is performed. */ | |
c906108c | 1204 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1205 | when the offset is to be used in relative addressing. */ |
c906108c | 1206 | |
12f02c2a | 1207 | static unsigned int |
c5aa993b | 1208 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1209 | { |
47a35522 | 1210 | gdb_byte buf[8]; |
c5aa993b JM |
1211 | pc &= 0xfffffffe; /* clear the low order bit */ |
1212 | target_read_memory (pc, buf, 2); | |
1213 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1214 | } |
1215 | ||
1216 | static void | |
c5aa993b | 1217 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1218 | unsigned int extension, |
1219 | unsigned int inst, | |
6d82d43b | 1220 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1221 | { |
12f02c2a AC |
1222 | CORE_ADDR offset; |
1223 | int regx; | |
1224 | int regy; | |
1225 | switch (insn_format) | |
c906108c | 1226 | { |
c5aa993b | 1227 | case itype: |
c906108c | 1228 | { |
12f02c2a AC |
1229 | CORE_ADDR value; |
1230 | if (extension) | |
c5aa993b JM |
1231 | { |
1232 | value = extended_offset (extension); | |
1233 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1234 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1235 | } |
1236 | else | |
c5aa993b | 1237 | { |
12f02c2a | 1238 | value = inst & 0x7ff; |
c5aa993b | 1239 | /* FIXME : Consider sign extension */ |
c906108c | 1240 | } |
12f02c2a AC |
1241 | offset = value; |
1242 | regx = -1; | |
1243 | regy = -1; | |
c906108c | 1244 | } |
c5aa993b JM |
1245 | break; |
1246 | case ritype: | |
1247 | case i8type: | |
1248 | { /* A register identifier and an offset */ | |
c906108c SS |
1249 | /* Most of the fields are the same as I type but the |
1250 | immediate value is of a different length */ | |
12f02c2a AC |
1251 | CORE_ADDR value; |
1252 | if (extension) | |
c906108c | 1253 | { |
c5aa993b JM |
1254 | value = extended_offset (extension); |
1255 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1256 | value |= inst & 0xff; /* eleven bits from instruction */ |
1257 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1258 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1259 | { | |
1260 | value &= ~0x3fff; /* remove the sign bit */ | |
1261 | value = -value; | |
c906108c SS |
1262 | } |
1263 | } | |
c5aa993b JM |
1264 | else |
1265 | { | |
12f02c2a AC |
1266 | value = inst & 0xff; /* 8 bits */ |
1267 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1268 | /* FIXME: Do sign extension , this format needs it */ |
1269 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1270 | { | |
1271 | value &= 0xef; /* remove the sign bit */ | |
1272 | value = -value; | |
1273 | } | |
c5aa993b | 1274 | } |
12f02c2a AC |
1275 | offset = value; |
1276 | regy = -1; | |
c5aa993b | 1277 | break; |
c906108c | 1278 | } |
c5aa993b | 1279 | case jalxtype: |
c906108c | 1280 | { |
c5aa993b | 1281 | unsigned long value; |
12f02c2a AC |
1282 | unsigned int nexthalf; |
1283 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1284 | value = value << 16; |
1285 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1286 | value |= nexthalf; | |
12f02c2a AC |
1287 | offset = value; |
1288 | regx = -1; | |
1289 | regy = -1; | |
c5aa993b | 1290 | break; |
c906108c SS |
1291 | } |
1292 | default: | |
e2e0b3e5 | 1293 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1294 | } |
12f02c2a AC |
1295 | upk->offset = offset; |
1296 | upk->regx = regx; | |
1297 | upk->regy = regy; | |
c906108c SS |
1298 | } |
1299 | ||
1300 | ||
c5aa993b JM |
1301 | static CORE_ADDR |
1302 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1303 | { |
5b652102 | 1304 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1305 | } |
1306 | ||
12f02c2a | 1307 | static CORE_ADDR |
0b1b3e42 | 1308 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1309 | unsigned int extension, unsigned int insn) |
c906108c | 1310 | { |
12f02c2a AC |
1311 | int op = (insn >> 11); |
1312 | switch (op) | |
c906108c | 1313 | { |
6d82d43b | 1314 | case 2: /* Branch */ |
12f02c2a AC |
1315 | { |
1316 | CORE_ADDR offset; | |
1317 | struct upk_mips16 upk; | |
1318 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1319 | offset = upk.offset; | |
1320 | if (offset & 0x800) | |
1321 | { | |
1322 | offset &= 0xeff; | |
1323 | offset = -offset; | |
1324 | } | |
1325 | pc += (offset << 1) + 2; | |
1326 | break; | |
1327 | } | |
6d82d43b | 1328 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1329 | { |
1330 | struct upk_mips16 upk; | |
1331 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1332 | pc = add_offset_16 (pc, upk.offset); | |
1333 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1334 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1335 | else | |
1336 | pc |= 0x01; | |
1337 | break; | |
1338 | } | |
6d82d43b | 1339 | case 4: /* beqz */ |
12f02c2a AC |
1340 | { |
1341 | struct upk_mips16 upk; | |
1342 | int reg; | |
1343 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1344 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1345 | if (reg == 0) |
1346 | pc += (upk.offset << 1) + 2; | |
1347 | else | |
1348 | pc += 2; | |
1349 | break; | |
1350 | } | |
6d82d43b | 1351 | case 5: /* bnez */ |
12f02c2a AC |
1352 | { |
1353 | struct upk_mips16 upk; | |
1354 | int reg; | |
1355 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1356 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1357 | if (reg != 0) |
1358 | pc += (upk.offset << 1) + 2; | |
1359 | else | |
1360 | pc += 2; | |
1361 | break; | |
1362 | } | |
6d82d43b | 1363 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1364 | { |
1365 | struct upk_mips16 upk; | |
1366 | int reg; | |
1367 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1368 | /* upk.regx contains the opcode */ | |
0b1b3e42 | 1369 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1370 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1371 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1372 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1373 | pc += (upk.offset << 1) + 2; | |
1374 | else | |
1375 | pc += 2; | |
1376 | break; | |
1377 | } | |
6d82d43b | 1378 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1379 | { |
1380 | struct upk_mips16 upk; | |
1381 | /* upk.fmt = rrtype; */ | |
1382 | op = insn & 0x1f; | |
1383 | if (op == 0) | |
c5aa993b | 1384 | { |
12f02c2a AC |
1385 | int reg; |
1386 | upk.regx = (insn >> 8) & 0x07; | |
1387 | upk.regy = (insn >> 5) & 0x07; | |
1388 | switch (upk.regy) | |
c5aa993b | 1389 | { |
12f02c2a AC |
1390 | case 0: |
1391 | reg = upk.regx; | |
1392 | break; | |
1393 | case 1: | |
1394 | reg = 31; | |
6d82d43b | 1395 | break; /* Function return instruction */ |
12f02c2a AC |
1396 | case 2: |
1397 | reg = upk.regx; | |
1398 | break; | |
1399 | default: | |
1400 | reg = 31; | |
6d82d43b | 1401 | break; /* BOGUS Guess */ |
c906108c | 1402 | } |
0b1b3e42 | 1403 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1404 | } |
12f02c2a | 1405 | else |
c5aa993b | 1406 | pc += 2; |
12f02c2a AC |
1407 | break; |
1408 | } | |
1409 | case 30: | |
1410 | /* This is an instruction extension. Fetch the real instruction | |
1411 | (which follows the extension) and decode things based on | |
1412 | that. */ | |
1413 | { | |
1414 | pc += 2; | |
0b1b3e42 | 1415 | pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc)); |
12f02c2a AC |
1416 | break; |
1417 | } | |
1418 | default: | |
1419 | { | |
1420 | pc += 2; | |
1421 | break; | |
1422 | } | |
c906108c | 1423 | } |
c5aa993b | 1424 | return pc; |
12f02c2a | 1425 | } |
c906108c | 1426 | |
5a89d8aa | 1427 | static CORE_ADDR |
0b1b3e42 | 1428 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a AC |
1429 | { |
1430 | unsigned int insn = fetch_mips_16 (pc); | |
0b1b3e42 | 1431 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1432 | } |
1433 | ||
1434 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1435 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1436 | It works by decoding the current instruction and predicting where a |
1437 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1438 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1439 | static CORE_ADDR |
0b1b3e42 | 1440 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1441 | { |
ce1f96de | 1442 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1443 | return mips16_next_pc (frame, pc); |
c5aa993b | 1444 | else |
0b1b3e42 | 1445 | return mips32_next_pc (frame, pc); |
12f02c2a | 1446 | } |
c906108c | 1447 | |
edfae063 AC |
1448 | struct mips_frame_cache |
1449 | { | |
1450 | CORE_ADDR base; | |
1451 | struct trad_frame_saved_reg *saved_regs; | |
1452 | }; | |
1453 | ||
29639122 JB |
1454 | /* Set a register's saved stack address in temp_saved_regs. If an |
1455 | address has already been set for this register, do nothing; this | |
1456 | way we will only recognize the first save of a given register in a | |
1457 | function prologue. | |
eec63939 | 1458 | |
f57d151a UW |
1459 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1460 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1461 | Strictly speaking, only the second range is used as it is only second | |
1462 | range (the ABI instead of ISA registers) that comes into play when finding | |
1463 | saved registers in a frame. */ | |
eec63939 AC |
1464 | |
1465 | static void | |
29639122 JB |
1466 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1467 | CORE_ADDR offset) | |
eec63939 | 1468 | { |
29639122 JB |
1469 | if (this_cache != NULL |
1470 | && this_cache->saved_regs[regnum].addr == -1) | |
1471 | { | |
f57d151a UW |
1472 | this_cache->saved_regs[regnum |
1473 | + 0 * gdbarch_num_regs (current_gdbarch)].addr | |
1474 | = offset; | |
1475 | this_cache->saved_regs[regnum | |
1476 | + 1 * gdbarch_num_regs (current_gdbarch)].addr | |
1477 | = offset; | |
29639122 | 1478 | } |
eec63939 AC |
1479 | } |
1480 | ||
eec63939 | 1481 | |
29639122 JB |
1482 | /* Fetch the immediate value from a MIPS16 instruction. |
1483 | If the previous instruction was an EXTEND, use it to extend | |
1484 | the upper bits of the immediate value. This is a helper function | |
1485 | for mips16_scan_prologue. */ | |
eec63939 | 1486 | |
29639122 JB |
1487 | static int |
1488 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1489 | unsigned short inst, /* current instruction */ | |
1490 | int nbits, /* number of bits in imm field */ | |
1491 | int scale, /* scale factor to be applied to imm */ | |
1492 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1493 | { |
29639122 | 1494 | int offset; |
eec63939 | 1495 | |
29639122 JB |
1496 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1497 | { | |
1498 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1499 | if (offset & 0x8000) /* check for negative extend */ | |
1500 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1501 | return offset | (inst & 0x1f); | |
1502 | } | |
eec63939 | 1503 | else |
29639122 JB |
1504 | { |
1505 | int max_imm = 1 << nbits; | |
1506 | int mask = max_imm - 1; | |
1507 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1508 | |
29639122 JB |
1509 | offset = inst & mask; |
1510 | if (is_signed && (offset & sign_bit)) | |
1511 | offset = 0 - (max_imm - offset); | |
1512 | return offset * scale; | |
1513 | } | |
1514 | } | |
eec63939 | 1515 | |
65596487 | 1516 | |
29639122 JB |
1517 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1518 | the associated FRAME_CACHE if not null. | |
1519 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1520 | |
29639122 JB |
1521 | static CORE_ADDR |
1522 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1523 | struct frame_info *next_frame, | |
1524 | struct mips_frame_cache *this_cache) | |
1525 | { | |
1526 | CORE_ADDR cur_pc; | |
1527 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1528 | CORE_ADDR sp; | |
1529 | long frame_offset = 0; /* Size of stack frame. */ | |
1530 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1531 | int frame_reg = MIPS_SP_REGNUM; | |
1532 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1533 | unsigned inst = 0; /* current instruction */ | |
1534 | unsigned entry_inst = 0; /* the entry instruction */ | |
1535 | int reg, offset; | |
a343eb3c | 1536 | |
29639122 JB |
1537 | int extend_bytes = 0; |
1538 | int prev_extend_bytes; | |
1539 | CORE_ADDR end_prologue_addr = 0; | |
72a155b4 | 1540 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
a343eb3c | 1541 | |
29639122 JB |
1542 | /* Can be called when there's no process, and hence when there's no |
1543 | NEXT_FRAME. */ | |
1544 | if (next_frame != NULL) | |
d2ca4222 | 1545 | sp = frame_unwind_register_signed (next_frame, |
72a155b4 | 1546 | gdbarch_num_regs (gdbarch) |
d2ca4222 | 1547 | + MIPS_SP_REGNUM); |
29639122 JB |
1548 | else |
1549 | sp = 0; | |
eec63939 | 1550 | |
29639122 JB |
1551 | if (limit_pc > start_pc + 200) |
1552 | limit_pc = start_pc + 200; | |
eec63939 | 1553 | |
95ac2dcf | 1554 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1555 | { |
1556 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1557 | the immediate offset extension from it in mips16_get_imm. */ | |
1558 | prev_inst = inst; | |
eec63939 | 1559 | |
29639122 JB |
1560 | /* Fetch and decode the instruction. */ |
1561 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1562 | |
29639122 JB |
1563 | /* Normally we ignore extend instructions. However, if it is |
1564 | not followed by a valid prologue instruction, then this | |
1565 | instruction is not part of the prologue either. We must | |
1566 | remember in this case to adjust the end_prologue_addr back | |
1567 | over the extend. */ | |
1568 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1569 | { | |
95ac2dcf | 1570 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1571 | continue; |
1572 | } | |
eec63939 | 1573 | |
29639122 JB |
1574 | prev_extend_bytes = extend_bytes; |
1575 | extend_bytes = 0; | |
eec63939 | 1576 | |
29639122 JB |
1577 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1578 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1579 | { | |
1580 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1581 | if (offset < 0) /* negative stack adjustment? */ | |
1582 | frame_offset -= offset; | |
1583 | else | |
1584 | /* Exit loop if a positive stack adjustment is found, which | |
1585 | usually means that the stack cleanup code in the function | |
1586 | epilogue is reached. */ | |
1587 | break; | |
1588 | } | |
1589 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1590 | { | |
1591 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1592 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1593 | set_reg_offset (this_cache, reg, sp + offset); | |
1594 | } | |
1595 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1596 | { | |
1597 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1598 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1599 | set_reg_offset (this_cache, reg, sp + offset); | |
1600 | } | |
1601 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1602 | { | |
1603 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1604 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1605 | } |
1606 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1607 | { | |
1608 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1609 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1610 | } |
1611 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1612 | { | |
1613 | frame_addr = sp; | |
1614 | frame_reg = 17; | |
1615 | } | |
1616 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1617 | { | |
1618 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1619 | frame_addr = sp + offset; | |
1620 | frame_reg = 17; | |
1621 | frame_adjust = offset; | |
1622 | } | |
1623 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1624 | { | |
1625 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1626 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1627 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1628 | } | |
1629 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1630 | { | |
1631 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1632 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1633 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1634 | } | |
1635 | else if ((inst & 0xf81f) == 0xe809 | |
1636 | && (inst & 0x700) != 0x700) /* entry */ | |
1637 | entry_inst = inst; /* save for later processing */ | |
1638 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
95ac2dcf | 1639 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1640 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1641 | { | |
1642 | /* This instruction is part of the prologue, but we don't | |
1643 | need to do anything special to handle it. */ | |
1644 | } | |
1645 | else | |
1646 | { | |
1647 | /* This instruction is not an instruction typically found | |
1648 | in a prologue, so we must have reached the end of the | |
1649 | prologue. */ | |
1650 | if (end_prologue_addr == 0) | |
1651 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1652 | } | |
1653 | } | |
eec63939 | 1654 | |
29639122 JB |
1655 | /* The entry instruction is typically the first instruction in a function, |
1656 | and it stores registers at offsets relative to the value of the old SP | |
1657 | (before the prologue). But the value of the sp parameter to this | |
1658 | function is the new SP (after the prologue has been executed). So we | |
1659 | can't calculate those offsets until we've seen the entire prologue, | |
1660 | and can calculate what the old SP must have been. */ | |
1661 | if (entry_inst != 0) | |
1662 | { | |
1663 | int areg_count = (entry_inst >> 8) & 7; | |
1664 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1665 | |
29639122 JB |
1666 | /* The entry instruction always subtracts 32 from the SP. */ |
1667 | frame_offset += 32; | |
1668 | ||
1669 | /* Now we can calculate what the SP must have been at the | |
1670 | start of the function prologue. */ | |
1671 | sp += frame_offset; | |
1672 | ||
1673 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1674 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1675 | { | |
1676 | set_reg_offset (this_cache, reg, sp + offset); | |
72a155b4 | 1677 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1678 | } |
1679 | ||
1680 | /* Check if the ra register was pushed on the stack. */ | |
1681 | offset = -4; | |
1682 | if (entry_inst & 0x20) | |
1683 | { | |
4c7d22cb | 1684 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1685 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1686 | } |
1687 | ||
1688 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1689 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1690 | { | |
1691 | set_reg_offset (this_cache, reg, sp + offset); | |
72a155b4 | 1692 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1693 | } |
1694 | } | |
1695 | ||
1696 | if (this_cache != NULL) | |
1697 | { | |
1698 | this_cache->base = | |
f57d151a | 1699 | (frame_unwind_register_signed (next_frame, |
72a155b4 | 1700 | gdbarch_num_regs (gdbarch) + frame_reg) |
29639122 JB |
1701 | + frame_offset - frame_adjust); |
1702 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1703 | be able to get rid of the assignment below, evetually. But it's | |
1704 | still needed for now. */ | |
72a155b4 UW |
1705 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1706 | + mips_regnum (gdbarch)->pc] | |
1707 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1708 | } |
1709 | ||
1710 | /* If we didn't reach the end of the prologue when scanning the function | |
1711 | instructions, then set end_prologue_addr to the address of the | |
1712 | instruction immediately after the last one we scanned. */ | |
1713 | if (end_prologue_addr == 0) | |
1714 | end_prologue_addr = cur_pc; | |
1715 | ||
1716 | return end_prologue_addr; | |
eec63939 AC |
1717 | } |
1718 | ||
29639122 JB |
1719 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1720 | Procedures that use the 32-bit instruction set are handled by the | |
1721 | mips_insn32 unwinder. */ | |
1722 | ||
1723 | static struct mips_frame_cache * | |
1724 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1725 | { |
29639122 | 1726 | struct mips_frame_cache *cache; |
eec63939 AC |
1727 | |
1728 | if ((*this_cache) != NULL) | |
1729 | return (*this_cache); | |
29639122 JB |
1730 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1731 | (*this_cache) = cache; | |
1732 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1733 | |
29639122 JB |
1734 | /* Analyze the function prologue. */ |
1735 | { | |
6de5b849 JB |
1736 | const CORE_ADDR pc = |
1737 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 1738 | CORE_ADDR start_addr; |
eec63939 | 1739 | |
29639122 JB |
1740 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1741 | if (start_addr == 0) | |
1742 | start_addr = heuristic_proc_start (pc); | |
1743 | /* We can't analyze the prologue if we couldn't find the begining | |
1744 | of the function. */ | |
1745 | if (start_addr == 0) | |
1746 | return cache; | |
eec63939 | 1747 | |
29639122 JB |
1748 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1749 | } | |
1750 | ||
3e8c568d | 1751 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 UW |
1752 | trad_frame_set_value (cache->saved_regs, |
1753 | gdbarch_num_regs (get_frame_arch (next_frame)) | |
1754 | + MIPS_SP_REGNUM, | |
1755 | cache->base); | |
eec63939 | 1756 | |
29639122 | 1757 | return (*this_cache); |
eec63939 AC |
1758 | } |
1759 | ||
1760 | static void | |
29639122 JB |
1761 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1762 | struct frame_id *this_id) | |
eec63939 | 1763 | { |
29639122 JB |
1764 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1765 | this_cache); | |
93d42b30 DJ |
1766 | (*this_id) = frame_id_build (info->base, |
1767 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
eec63939 AC |
1768 | } |
1769 | ||
1770 | static void | |
29639122 | 1771 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1772 | void **this_cache, |
1773 | int regnum, int *optimizedp, | |
1774 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1775 | int *realnump, gdb_byte *valuep) |
eec63939 | 1776 | { |
29639122 JB |
1777 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1778 | this_cache); | |
1779 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1780 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1781 | } |
1782 | ||
29639122 | 1783 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1784 | { |
1785 | NORMAL_FRAME, | |
29639122 JB |
1786 | mips_insn16_frame_this_id, |
1787 | mips_insn16_frame_prev_register | |
eec63939 AC |
1788 | }; |
1789 | ||
1790 | static const struct frame_unwind * | |
29639122 | 1791 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 | 1792 | { |
6de5b849 | 1793 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 1794 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1795 | return &mips_insn16_frame_unwind; |
1796 | return NULL; | |
eec63939 AC |
1797 | } |
1798 | ||
1799 | static CORE_ADDR | |
29639122 JB |
1800 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1801 | void **this_cache) | |
eec63939 | 1802 | { |
29639122 JB |
1803 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1804 | this_cache); | |
1805 | return info->base; | |
eec63939 AC |
1806 | } |
1807 | ||
29639122 | 1808 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1809 | { |
29639122 JB |
1810 | &mips_insn16_frame_unwind, |
1811 | mips_insn16_frame_base_address, | |
1812 | mips_insn16_frame_base_address, | |
1813 | mips_insn16_frame_base_address | |
eec63939 AC |
1814 | }; |
1815 | ||
1816 | static const struct frame_base * | |
29639122 | 1817 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1818 | { |
29639122 JB |
1819 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1820 | return &mips_insn16_frame_base; | |
eec63939 AC |
1821 | else |
1822 | return NULL; | |
edfae063 AC |
1823 | } |
1824 | ||
29639122 JB |
1825 | /* Mark all the registers as unset in the saved_regs array |
1826 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1827 | ||
1828 | void | |
1829 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1830 | { |
29639122 JB |
1831 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1832 | return; | |
1833 | ||
1834 | { | |
f57d151a | 1835 | const int num_regs = gdbarch_num_regs (current_gdbarch); |
29639122 | 1836 | int i; |
64159455 | 1837 | |
29639122 JB |
1838 | for (i = 0; i < num_regs; i++) |
1839 | { | |
1840 | this_cache->saved_regs[i].addr = -1; | |
1841 | } | |
1842 | } | |
c906108c SS |
1843 | } |
1844 | ||
29639122 JB |
1845 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1846 | the associated FRAME_CACHE if not null. | |
1847 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1848 | |
875e1767 | 1849 | static CORE_ADDR |
29639122 JB |
1850 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1851 | struct frame_info *next_frame, | |
1852 | struct mips_frame_cache *this_cache) | |
c906108c | 1853 | { |
29639122 JB |
1854 | CORE_ADDR cur_pc; |
1855 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1856 | CORE_ADDR sp; | |
1857 | long frame_offset; | |
1858 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1859 | |
29639122 JB |
1860 | CORE_ADDR end_prologue_addr = 0; |
1861 | int seen_sp_adjust = 0; | |
1862 | int load_immediate_bytes = 0; | |
72a155b4 | 1863 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
8fa9cfa1 | 1864 | |
29639122 JB |
1865 | /* Can be called when there's no process, and hence when there's no |
1866 | NEXT_FRAME. */ | |
1867 | if (next_frame != NULL) | |
d2ca4222 | 1868 | sp = frame_unwind_register_signed (next_frame, |
72a155b4 | 1869 | gdbarch_num_regs (gdbarch) |
d2ca4222 | 1870 | + MIPS_SP_REGNUM); |
8fa9cfa1 | 1871 | else |
29639122 | 1872 | sp = 0; |
9022177c | 1873 | |
29639122 JB |
1874 | if (limit_pc > start_pc + 200) |
1875 | limit_pc = start_pc + 200; | |
9022177c | 1876 | |
29639122 | 1877 | restart: |
9022177c | 1878 | |
29639122 | 1879 | frame_offset = 0; |
95ac2dcf | 1880 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1881 | { |
29639122 JB |
1882 | unsigned long inst, high_word, low_word; |
1883 | int reg; | |
9022177c | 1884 | |
29639122 JB |
1885 | /* Fetch the instruction. */ |
1886 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1887 | |
29639122 JB |
1888 | /* Save some code by pre-extracting some useful fields. */ |
1889 | high_word = (inst >> 16) & 0xffff; | |
1890 | low_word = inst & 0xffff; | |
1891 | reg = high_word & 0x1f; | |
fe29b929 | 1892 | |
29639122 JB |
1893 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1894 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1895 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1896 | { | |
1897 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1898 | frame_offset += 0x10000 - low_word; | |
1899 | else | |
1900 | /* Exit loop if a positive stack adjustment is found, which | |
1901 | usually means that the stack cleanup code in the function | |
1902 | epilogue is reached. */ | |
1903 | break; | |
1904 | seen_sp_adjust = 1; | |
1905 | } | |
1906 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1907 | { | |
1908 | set_reg_offset (this_cache, reg, sp + low_word); | |
1909 | } | |
1910 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1911 | { | |
1912 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1913 | set_reg_offset (this_cache, reg, sp + low_word); | |
1914 | } | |
1915 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1916 | { | |
1917 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1918 | if ((long) low_word != frame_offset) | |
1919 | frame_addr = sp + low_word; | |
d2ca4222 | 1920 | else if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1921 | { |
1922 | unsigned alloca_adjust; | |
a4b8ebc8 | 1923 | |
29639122 | 1924 | frame_reg = 30; |
d2ca4222 | 1925 | frame_addr = frame_unwind_register_signed |
72a155b4 | 1926 | (next_frame, gdbarch_num_regs (gdbarch) + 30); |
d2ca4222 | 1927 | |
29639122 JB |
1928 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1929 | if (alloca_adjust > 0) | |
1930 | { | |
1931 | /* FP > SP + frame_size. This may be because of | |
1932 | an alloca or somethings similar. Fix sp to | |
1933 | "pre-alloca" value, and try again. */ | |
1934 | sp += alloca_adjust; | |
1935 | /* Need to reset the status of all registers. Otherwise, | |
1936 | we will hit a guard that prevents the new address | |
1937 | for each register to be recomputed during the second | |
1938 | pass. */ | |
1939 | reset_saved_regs (this_cache); | |
1940 | goto restart; | |
1941 | } | |
1942 | } | |
1943 | } | |
1944 | /* move $30,$sp. With different versions of gas this will be either | |
1945 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1946 | Accept any one of these. */ | |
1947 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1948 | { | |
1949 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
d2ca4222 | 1950 | if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1951 | { |
1952 | unsigned alloca_adjust; | |
c906108c | 1953 | |
29639122 | 1954 | frame_reg = 30; |
d2ca4222 | 1955 | frame_addr = frame_unwind_register_signed |
72a155b4 | 1956 | (next_frame, gdbarch_num_regs (gdbarch) + 30); |
d2ca4222 | 1957 | |
29639122 JB |
1958 | alloca_adjust = (unsigned) (frame_addr - sp); |
1959 | if (alloca_adjust > 0) | |
1960 | { | |
1961 | /* FP > SP + frame_size. This may be because of | |
1962 | an alloca or somethings similar. Fix sp to | |
1963 | "pre-alloca" value, and try again. */ | |
1964 | sp = frame_addr; | |
1965 | /* Need to reset the status of all registers. Otherwise, | |
1966 | we will hit a guard that prevents the new address | |
1967 | for each register to be recomputed during the second | |
1968 | pass. */ | |
1969 | reset_saved_regs (this_cache); | |
1970 | goto restart; | |
1971 | } | |
1972 | } | |
1973 | } | |
1974 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
1975 | { | |
1976 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
1977 | } | |
1978 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
1979 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
1980 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
1981 | || high_word == 0x3c1c /* lui $gp,n */ | |
1982 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
1983 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1984 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
1985 | ) | |
1986 | { | |
1987 | /* These instructions are part of the prologue, but we don't | |
1988 | need to do anything special to handle them. */ | |
1989 | } | |
1990 | /* The instructions below load $at or $t0 with an immediate | |
1991 | value in preparation for a stack adjustment via | |
1992 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
1993 | initialize a local variable, so we accept them only before | |
1994 | a stack adjustment instruction was seen. */ | |
1995 | else if (!seen_sp_adjust | |
1996 | && (high_word == 0x3c01 /* lui $at,n */ | |
1997 | || high_word == 0x3c08 /* lui $t0,n */ | |
1998 | || high_word == 0x3421 /* ori $at,$at,n */ | |
1999 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2000 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2001 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2002 | )) | |
2003 | { | |
95ac2dcf | 2004 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2005 | } |
2006 | else | |
2007 | { | |
2008 | /* This instruction is not an instruction typically found | |
2009 | in a prologue, so we must have reached the end of the | |
2010 | prologue. */ | |
2011 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2012 | loop now? Why would we need to continue scanning the function | |
2013 | instructions? */ | |
2014 | if (end_prologue_addr == 0) | |
2015 | end_prologue_addr = cur_pc; | |
2016 | } | |
a4b8ebc8 | 2017 | } |
c906108c | 2018 | |
29639122 JB |
2019 | if (this_cache != NULL) |
2020 | { | |
2021 | this_cache->base = | |
f57d151a | 2022 | (frame_unwind_register_signed (next_frame, |
72a155b4 | 2023 | gdbarch_num_regs (gdbarch) + frame_reg) |
29639122 JB |
2024 | + frame_offset); |
2025 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2026 | this assignment below, eventually. But it's still needed | |
2027 | for now. */ | |
72a155b4 UW |
2028 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2029 | + mips_regnum (gdbarch)->pc] | |
2030 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2031 | + MIPS_RA_REGNUM]; |
29639122 | 2032 | } |
c906108c | 2033 | |
29639122 JB |
2034 | /* If we didn't reach the end of the prologue when scanning the function |
2035 | instructions, then set end_prologue_addr to the address of the | |
2036 | instruction immediately after the last one we scanned. */ | |
2037 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2038 | we may as well be careful and do our best if we have a null | |
2039 | end_prologue_addr. */ | |
2040 | if (end_prologue_addr == 0) | |
2041 | end_prologue_addr = cur_pc; | |
2042 | ||
2043 | /* In a frameless function, we might have incorrectly | |
2044 | skipped some load immediate instructions. Undo the skipping | |
2045 | if the load immediate was not followed by a stack adjustment. */ | |
2046 | if (load_immediate_bytes && !seen_sp_adjust) | |
2047 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2048 | |
29639122 | 2049 | return end_prologue_addr; |
c906108c SS |
2050 | } |
2051 | ||
29639122 JB |
2052 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2053 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2054 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2055 | unwinder. */ | |
c906108c | 2056 | |
29639122 JB |
2057 | static struct mips_frame_cache * |
2058 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 2059 | { |
29639122 | 2060 | struct mips_frame_cache *cache; |
c906108c | 2061 | |
29639122 JB |
2062 | if ((*this_cache) != NULL) |
2063 | return (*this_cache); | |
c5aa993b | 2064 | |
29639122 JB |
2065 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2066 | (*this_cache) = cache; | |
2067 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 2068 | |
29639122 JB |
2069 | /* Analyze the function prologue. */ |
2070 | { | |
6de5b849 JB |
2071 | const CORE_ADDR pc = |
2072 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 2073 | CORE_ADDR start_addr; |
c906108c | 2074 | |
29639122 JB |
2075 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2076 | if (start_addr == 0) | |
2077 | start_addr = heuristic_proc_start (pc); | |
2078 | /* We can't analyze the prologue if we couldn't find the begining | |
2079 | of the function. */ | |
2080 | if (start_addr == 0) | |
2081 | return cache; | |
c5aa993b | 2082 | |
29639122 JB |
2083 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
2084 | } | |
2085 | ||
3e8c568d | 2086 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2087 | trad_frame_set_value (cache->saved_regs, |
72a155b4 UW |
2088 | gdbarch_num_regs (get_frame_arch (next_frame)) |
2089 | + MIPS_SP_REGNUM, | |
f57d151a | 2090 | cache->base); |
c5aa993b | 2091 | |
29639122 | 2092 | return (*this_cache); |
c906108c SS |
2093 | } |
2094 | ||
29639122 JB |
2095 | static void |
2096 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2097 | struct frame_id *this_id) | |
c906108c | 2098 | { |
29639122 JB |
2099 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2100 | this_cache); | |
93d42b30 DJ |
2101 | (*this_id) = frame_id_build (info->base, |
2102 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
29639122 | 2103 | } |
c906108c | 2104 | |
29639122 JB |
2105 | static void |
2106 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
2107 | void **this_cache, | |
2108 | int regnum, int *optimizedp, | |
2109 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2110 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2111 | { |
2112 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
2113 | this_cache); | |
2114 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2115 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
2116 | } |
2117 | ||
29639122 JB |
2118 | static const struct frame_unwind mips_insn32_frame_unwind = |
2119 | { | |
2120 | NORMAL_FRAME, | |
2121 | mips_insn32_frame_this_id, | |
2122 | mips_insn32_frame_prev_register | |
2123 | }; | |
c906108c | 2124 | |
29639122 JB |
2125 | static const struct frame_unwind * |
2126 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2127 | { | |
6de5b849 | 2128 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 2129 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2130 | return &mips_insn32_frame_unwind; |
2131 | return NULL; | |
2132 | } | |
c906108c | 2133 | |
1c645fec | 2134 | static CORE_ADDR |
29639122 JB |
2135 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2136 | void **this_cache) | |
c906108c | 2137 | { |
29639122 JB |
2138 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2139 | this_cache); | |
2140 | return info->base; | |
2141 | } | |
c906108c | 2142 | |
29639122 JB |
2143 | static const struct frame_base mips_insn32_frame_base = |
2144 | { | |
2145 | &mips_insn32_frame_unwind, | |
2146 | mips_insn32_frame_base_address, | |
2147 | mips_insn32_frame_base_address, | |
2148 | mips_insn32_frame_base_address | |
2149 | }; | |
1c645fec | 2150 | |
29639122 JB |
2151 | static const struct frame_base * |
2152 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2153 | { | |
2154 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2155 | return &mips_insn32_frame_base; | |
a65bbe44 | 2156 | else |
29639122 JB |
2157 | return NULL; |
2158 | } | |
a65bbe44 | 2159 | |
29639122 JB |
2160 | static struct trad_frame_cache * |
2161 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2162 | { | |
2163 | CORE_ADDR pc; | |
2164 | CORE_ADDR start_addr; | |
2165 | CORE_ADDR stack_addr; | |
2166 | struct trad_frame_cache *this_trad_cache; | |
72a155b4 | 2167 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
c906108c | 2168 | |
29639122 JB |
2169 | if ((*this_cache) != NULL) |
2170 | return (*this_cache); | |
2171 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2172 | (*this_cache) = this_trad_cache; | |
1c645fec | 2173 | |
29639122 | 2174 | /* The return address is in the link register. */ |
3e8c568d | 2175 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 UW |
2176 | gdbarch_pc_regnum (gdbarch), |
2177 | (gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM)); | |
1c645fec | 2178 | |
29639122 JB |
2179 | /* Frame ID, since it's a frameless / stackless function, no stack |
2180 | space is allocated and SP on entry is the current SP. */ | |
2181 | pc = frame_pc_unwind (next_frame); | |
2182 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2183 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
aa6c981f | 2184 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2185 | |
29639122 JB |
2186 | /* Assume that the frame's base is the same as the |
2187 | stack-pointer. */ | |
2188 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2189 | |
29639122 JB |
2190 | return this_trad_cache; |
2191 | } | |
c906108c | 2192 | |
29639122 JB |
2193 | static void |
2194 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2195 | struct frame_id *this_id) | |
2196 | { | |
2197 | struct trad_frame_cache *this_trad_cache | |
2198 | = mips_stub_frame_cache (next_frame, this_cache); | |
2199 | trad_frame_get_id (this_trad_cache, this_id); | |
2200 | } | |
c906108c | 2201 | |
29639122 JB |
2202 | static void |
2203 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2204 | void **this_cache, | |
2205 | int regnum, int *optimizedp, | |
2206 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2207 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2208 | { |
2209 | struct trad_frame_cache *this_trad_cache | |
2210 | = mips_stub_frame_cache (next_frame, this_cache); | |
2211 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2212 | lvalp, addrp, realnump, valuep); | |
2213 | } | |
c906108c | 2214 | |
29639122 JB |
2215 | static const struct frame_unwind mips_stub_frame_unwind = |
2216 | { | |
2217 | NORMAL_FRAME, | |
2218 | mips_stub_frame_this_id, | |
2219 | mips_stub_frame_prev_register | |
2220 | }; | |
c906108c | 2221 | |
29639122 JB |
2222 | static const struct frame_unwind * |
2223 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2224 | { | |
aa6c981f | 2225 | gdb_byte dummy[4]; |
979b38e0 | 2226 | struct obj_section *s; |
93d42b30 | 2227 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
979b38e0 | 2228 | |
aa6c981f DJ |
2229 | /* Use the stub unwinder for unreadable code. */ |
2230 | if (target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) | |
2231 | return &mips_stub_frame_unwind; | |
2232 | ||
29639122 JB |
2233 | if (in_plt_section (pc, NULL)) |
2234 | return &mips_stub_frame_unwind; | |
979b38e0 DJ |
2235 | |
2236 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2237 | s = find_pc_section (pc); | |
2238 | ||
2239 | if (s != NULL | |
2240 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2241 | ".MIPS.stubs") == 0) | |
2242 | return &mips_stub_frame_unwind; | |
2243 | ||
2244 | return NULL; | |
29639122 | 2245 | } |
c906108c | 2246 | |
29639122 JB |
2247 | static CORE_ADDR |
2248 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2249 | void **this_cache) | |
2250 | { | |
2251 | struct trad_frame_cache *this_trad_cache | |
2252 | = mips_stub_frame_cache (next_frame, this_cache); | |
2253 | return trad_frame_get_this_base (this_trad_cache); | |
2254 | } | |
0fce0821 | 2255 | |
29639122 JB |
2256 | static const struct frame_base mips_stub_frame_base = |
2257 | { | |
2258 | &mips_stub_frame_unwind, | |
2259 | mips_stub_frame_base_address, | |
2260 | mips_stub_frame_base_address, | |
2261 | mips_stub_frame_base_address | |
2262 | }; | |
2263 | ||
2264 | static const struct frame_base * | |
2265 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2266 | { | |
2267 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2268 | return &mips_stub_frame_base; | |
2269 | else | |
2270 | return NULL; | |
2271 | } | |
2272 | ||
29639122 | 2273 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2274 | |
29639122 JB |
2275 | static CORE_ADDR |
2276 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2277 | { |
29639122 JB |
2278 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2279 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2280 | /* This hack is a work-around for existing boards using PMON, the | |
2281 | simulator, and any other 64-bit targets that doesn't have true | |
2282 | 64-bit addressing. On these targets, the upper 32 bits of | |
2283 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2284 | likely to have been sign extended to all 1s by instruction | |
2285 | sequences that load 32-bit addresses. For example, a typical | |
2286 | piece of code that loads an address is this: | |
65596487 | 2287 | |
29639122 JB |
2288 | lui $r2, <upper 16 bits> |
2289 | ori $r2, <lower 16 bits> | |
65596487 | 2290 | |
29639122 JB |
2291 | But the lui sign-extends the value such that the upper 32 bits |
2292 | may be all 1s. The workaround is simply to mask off these | |
2293 | bits. In the future, gcc may be changed to support true 64-bit | |
2294 | addressing, and this masking will have to be disabled. */ | |
2295 | return addr &= 0xffffffffUL; | |
2296 | else | |
2297 | return addr; | |
65596487 JB |
2298 | } |
2299 | ||
29639122 JB |
2300 | /* mips_software_single_step() is called just before we want to resume |
2301 | the inferior, if we want to single-step it but there is no hardware | |
2302 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2303 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2304 | |
e6590a1b | 2305 | int |
0b1b3e42 | 2306 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2307 | { |
8181d85f | 2308 | CORE_ADDR pc, next_pc; |
65596487 | 2309 | |
0b1b3e42 UW |
2310 | pc = get_frame_pc (frame); |
2311 | next_pc = mips_next_pc (frame, pc); | |
e6590a1b | 2312 | |
e0cd558a | 2313 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2314 | return 1; |
29639122 | 2315 | } |
a65bbe44 | 2316 | |
29639122 JB |
2317 | /* Test whether the PC points to the return instruction at the |
2318 | end of a function. */ | |
65596487 | 2319 | |
29639122 JB |
2320 | static int |
2321 | mips_about_to_return (CORE_ADDR pc) | |
2322 | { | |
0fe7e7c8 | 2323 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2324 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2325 | generates a "jr $ra"; other times it generates code to load | |
2326 | the return address from the stack to an accessible register (such | |
2327 | as $a3), then a "jr" using that register. This second case | |
2328 | is almost impossible to distinguish from an indirect jump | |
2329 | used for switch statements, so we don't even try. */ | |
2330 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2331 | else | |
2332 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2333 | } | |
c906108c | 2334 | |
c906108c | 2335 | |
29639122 JB |
2336 | /* This fencepost looks highly suspicious to me. Removing it also |
2337 | seems suspicious as it could affect remote debugging across serial | |
2338 | lines. */ | |
c906108c | 2339 | |
29639122 JB |
2340 | static CORE_ADDR |
2341 | heuristic_proc_start (CORE_ADDR pc) | |
2342 | { | |
2343 | CORE_ADDR start_pc; | |
2344 | CORE_ADDR fence; | |
2345 | int instlen; | |
2346 | int seen_adjsp = 0; | |
65596487 | 2347 | |
bf6ae464 | 2348 | pc = gdbarch_addr_bits_remove (current_gdbarch, pc); |
29639122 JB |
2349 | start_pc = pc; |
2350 | fence = start_pc - heuristic_fence_post; | |
2351 | if (start_pc == 0) | |
2352 | return 0; | |
65596487 | 2353 | |
29639122 JB |
2354 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2355 | fence = VM_MIN_ADDRESS; | |
65596487 | 2356 | |
95ac2dcf | 2357 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2358 | |
29639122 JB |
2359 | /* search back for previous return */ |
2360 | for (start_pc -= instlen;; start_pc -= instlen) | |
2361 | if (start_pc < fence) | |
2362 | { | |
2363 | /* It's not clear to me why we reach this point when | |
2364 | stop_soon, but with this test, at least we | |
2365 | don't print out warnings for every child forked (eg, on | |
2366 | decstation). 22apr93 rich@cygnus.com. */ | |
2367 | if (stop_soon == NO_STOP_QUIETLY) | |
2368 | { | |
2369 | static int blurb_printed = 0; | |
98b4dd94 | 2370 | |
8a3fe4f8 | 2371 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2372 | paddr_nz (pc)); |
2373 | ||
2374 | if (!blurb_printed) | |
2375 | { | |
2376 | /* This actually happens frequently in embedded | |
2377 | development, when you first connect to a board | |
2378 | and your stack pointer and pc are nowhere in | |
2379 | particular. This message needs to give people | |
2380 | in that situation enough information to | |
2381 | determine that it's no big deal. */ | |
2382 | printf_filtered ("\n\ | |
2383 | GDB is unable to find the start of the function at 0x%s\n\ | |
2384 | and thus can't determine the size of that function's stack frame.\n\ | |
2385 | This means that GDB may be unable to access that stack frame, or\n\ | |
2386 | the frames below it.\n\ | |
2387 | This problem is most likely caused by an invalid program counter or\n\ | |
2388 | stack pointer.\n\ | |
2389 | However, if you think GDB should simply search farther back\n\ | |
2390 | from 0x%s for code which looks like the beginning of a\n\ | |
2391 | function, you can increase the range of the search using the `set\n\ | |
2392 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2393 | blurb_printed = 1; | |
2394 | } | |
2395 | } | |
2396 | ||
2397 | return 0; | |
2398 | } | |
0fe7e7c8 | 2399 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2400 | { |
2401 | unsigned short inst; | |
2402 | ||
2403 | /* On MIPS16, any one of the following is likely to be the | |
2404 | start of a function: | |
193774b3 MR |
2405 | extend save |
2406 | save | |
29639122 JB |
2407 | entry |
2408 | addiu sp,-n | |
2409 | daddiu sp,-n | |
2410 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2411 | inst = mips_fetch_instruction (start_pc); | |
193774b3 MR |
2412 | if ((inst & 0xff80) == 0x6480) /* save */ |
2413 | { | |
2414 | if (start_pc - instlen >= fence) | |
2415 | { | |
2416 | inst = mips_fetch_instruction (start_pc - instlen); | |
2417 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2418 | start_pc -= instlen; | |
2419 | } | |
2420 | break; | |
2421 | } | |
2422 | else if (((inst & 0xf81f) == 0xe809 | |
2423 | && (inst & 0x700) != 0x700) /* entry */ | |
2424 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2425 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2426 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2427 | break; |
2428 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2429 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2430 | seen_adjsp = 1; | |
2431 | else | |
2432 | seen_adjsp = 0; | |
2433 | } | |
2434 | else if (mips_about_to_return (start_pc)) | |
2435 | { | |
4c7d22cb | 2436 | /* Skip return and its delay slot. */ |
95ac2dcf | 2437 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2438 | break; |
2439 | } | |
2440 | ||
2441 | return start_pc; | |
c906108c SS |
2442 | } |
2443 | ||
6c0d6680 DJ |
2444 | struct mips_objfile_private |
2445 | { | |
2446 | bfd_size_type size; | |
2447 | char *contents; | |
2448 | }; | |
2449 | ||
f09ded24 AC |
2450 | /* According to the current ABI, should the type be passed in a |
2451 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2452 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2453 | FP registers and, consequently this returns false - forces FP |
2454 | arguments into integer registers. */ | |
2455 | ||
2456 | static int | |
2457 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2458 | { | |
2459 | return ((typecode == TYPE_CODE_FLT | |
2460 | || (MIPS_EABI | |
6d82d43b AC |
2461 | && (typecode == TYPE_CODE_STRUCT |
2462 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2463 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2464 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2465 | == TYPE_CODE_FLT)) | |
c86b5b38 | 2466 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2467 | } |
2468 | ||
49e790b0 DJ |
2469 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2470 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2471 | ||
2472 | static int | |
2473 | mips_type_needs_double_align (struct type *type) | |
2474 | { | |
2475 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2476 | |
49e790b0 DJ |
2477 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2478 | return 1; | |
2479 | else if (typecode == TYPE_CODE_STRUCT) | |
2480 | { | |
2481 | if (TYPE_NFIELDS (type) < 1) | |
2482 | return 0; | |
2483 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2484 | } | |
2485 | else if (typecode == TYPE_CODE_UNION) | |
2486 | { | |
361d1df0 | 2487 | int i, n; |
49e790b0 DJ |
2488 | |
2489 | n = TYPE_NFIELDS (type); | |
2490 | for (i = 0; i < n; i++) | |
2491 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2492 | return 1; | |
2493 | return 0; | |
2494 | } | |
2495 | return 0; | |
2496 | } | |
2497 | ||
dc604539 AC |
2498 | /* Adjust the address downward (direction of stack growth) so that it |
2499 | is correctly aligned for a new stack frame. */ | |
2500 | static CORE_ADDR | |
2501 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2502 | { | |
5b03f266 | 2503 | return align_down (addr, 16); |
dc604539 AC |
2504 | } |
2505 | ||
f7ab6ec6 | 2506 | static CORE_ADDR |
7d9b040b | 2507 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2508 | struct regcache *regcache, CORE_ADDR bp_addr, |
2509 | int nargs, struct value **args, CORE_ADDR sp, | |
2510 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2511 | { |
2512 | int argreg; | |
2513 | int float_argreg; | |
2514 | int argnum; | |
2515 | int len = 0; | |
2516 | int stack_offset = 0; | |
480d3dd2 | 2517 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2518 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2519 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2520 | |
25ab4790 AC |
2521 | /* For shared libraries, "t9" needs to point at the function |
2522 | address. */ | |
4c7d22cb | 2523 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2524 | |
2525 | /* Set the return address register to point to the entry point of | |
2526 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2527 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2528 | |
c906108c | 2529 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2530 | are properly aligned. The stack has to be at least 64-bit |
2531 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2532 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2533 | aligned, so we round to this widest known alignment. */ | |
2534 | ||
5b03f266 AC |
2535 | sp = align_down (sp, 16); |
2536 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2537 | |
46e0f506 | 2538 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2539 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2540 | passed in registers, but that's OK. */ |
c906108c | 2541 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2542 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2543 | sp -= align_up (len, 16); |
c906108c | 2544 | |
9ace0497 | 2545 | if (mips_debug) |
6d82d43b | 2546 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2547 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2548 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2549 | |
c906108c | 2550 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2551 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2552 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2553 | |
46e0f506 | 2554 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2555 | if (struct_return) |
9ace0497 AC |
2556 | { |
2557 | if (mips_debug) | |
2558 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2559 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2560 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2561 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2562 | } |
c906108c SS |
2563 | |
2564 | /* Now load as many as possible of the first arguments into | |
2565 | registers, and push the rest onto the stack. Loop thru args | |
2566 | from first to last. */ | |
2567 | for (argnum = 0; argnum < nargs; argnum++) | |
2568 | { | |
47a35522 MK |
2569 | const gdb_byte *val; |
2570 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2571 | struct value *arg = args[argnum]; |
4991999e | 2572 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2573 | int len = TYPE_LENGTH (arg_type); |
2574 | enum type_code typecode = TYPE_CODE (arg_type); | |
2575 | ||
9ace0497 AC |
2576 | if (mips_debug) |
2577 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2578 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2579 | argnum + 1, len, (int) typecode); |
9ace0497 | 2580 | |
c906108c | 2581 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2582 | reference. */ |
1a69e1e4 | 2583 | if (len > regsize |
9ace0497 | 2584 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2585 | { |
1a69e1e4 | 2586 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2587 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2588 | len = regsize; |
c906108c | 2589 | val = valbuf; |
9ace0497 AC |
2590 | if (mips_debug) |
2591 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2592 | } |
2593 | else | |
47a35522 | 2594 | val = value_contents (arg); |
c906108c SS |
2595 | |
2596 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2597 | even-numbered floating point register. Round the FP register |
2598 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2599 | left. Non MIPS_EABI targets also pass the FP in the integer |
2600 | registers so also round up normal registers. */ | |
1a69e1e4 | 2601 | if (regsize < 8 && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2602 | { |
2603 | if ((float_argreg & 1)) | |
2604 | float_argreg++; | |
2605 | } | |
c906108c SS |
2606 | |
2607 | /* Floating point arguments passed in registers have to be | |
2608 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2609 | are passed in register pairs; the even register gets |
2610 | the low word, and the odd register gets the high word. | |
2611 | On non-EABI processors, the first two floating point arguments are | |
2612 | also copied to general registers, because MIPS16 functions | |
2613 | don't use float registers for arguments. This duplication of | |
2614 | arguments in general registers can't hurt non-MIPS16 functions | |
2615 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2616 | /* MIPS_EABI squeezes a struct that contains a single floating |
2617 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2618 | stack. */ |
f09ded24 AC |
2619 | if (fp_register_arg_p (typecode, arg_type) |
2620 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2621 | { |
6da397e0 KB |
2622 | /* EABI32 will pass doubles in consecutive registers, even on |
2623 | 64-bit cores. At one time, we used to check the size of | |
2624 | `float_argreg' to determine whether or not to pass doubles | |
2625 | in consecutive registers, but this is not sufficient for | |
2626 | making the ABI determination. */ | |
2627 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2628 | { |
72a155b4 | 2629 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 2630 | == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2631 | unsigned long regval; |
2632 | ||
2633 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2634 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2635 | if (mips_debug) |
acdb74a0 | 2636 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2637 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2638 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2639 | |
2640 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2641 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2642 | if (mips_debug) |
acdb74a0 | 2643 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2644 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2645 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2646 | } |
2647 | else | |
2648 | { | |
2649 | /* This is a floating point value that fits entirely | |
2650 | in a single register. */ | |
53a5351d | 2651 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2652 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2653 | LONGEST regval = extract_unsigned_integer (val, len); |
2654 | if (mips_debug) | |
acdb74a0 | 2655 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2656 | float_argreg, phex (regval, len)); |
9c9acae0 | 2657 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2658 | } |
2659 | } | |
2660 | else | |
2661 | { | |
2662 | /* Copy the argument to general registers or the stack in | |
2663 | register-sized pieces. Large arguments are split between | |
2664 | registers and stack. */ | |
1a69e1e4 DJ |
2665 | /* Note: structs whose size is not a multiple of regsize |
2666 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2667 | them in registers where gcc sometimes puts them on the |
2668 | stack. For maximum compatibility, we will put them in | |
2669 | both places. */ | |
1a69e1e4 | 2670 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2671 | |
f09ded24 | 2672 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2673 | register are only written to memory. */ |
c906108c SS |
2674 | while (len > 0) |
2675 | { | |
ebafbe83 | 2676 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2677 | int stack_used_p = 0; |
1a69e1e4 | 2678 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2679 | |
acdb74a0 AC |
2680 | if (mips_debug) |
2681 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2682 | partial_len); | |
2683 | ||
566f0f7a | 2684 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2685 | if (argreg > MIPS_LAST_ARG_REGNUM |
2686 | || odd_sized_struct | |
2687 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2688 | { |
c906108c SS |
2689 | /* Should shorter than int integer values be |
2690 | promoted to int before being stored? */ | |
c906108c | 2691 | int longword_offset = 0; |
9ace0497 | 2692 | CORE_ADDR addr; |
566f0f7a | 2693 | stack_used_p = 1; |
72a155b4 | 2694 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2695 | { |
1a69e1e4 | 2696 | if (regsize == 8 |
480d3dd2 AC |
2697 | && (typecode == TYPE_CODE_INT |
2698 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2699 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2700 | longword_offset = regsize - len; |
480d3dd2 AC |
2701 | else if ((typecode == TYPE_CODE_STRUCT |
2702 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2703 | && TYPE_LENGTH (arg_type) < regsize) |
2704 | longword_offset = regsize - len; | |
7a292a7a | 2705 | } |
c5aa993b | 2706 | |
9ace0497 AC |
2707 | if (mips_debug) |
2708 | { | |
cb3d25d1 MS |
2709 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2710 | paddr_nz (stack_offset)); | |
2711 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2712 | paddr_nz (longword_offset)); | |
9ace0497 | 2713 | } |
361d1df0 | 2714 | |
9ace0497 AC |
2715 | addr = sp + stack_offset + longword_offset; |
2716 | ||
2717 | if (mips_debug) | |
2718 | { | |
2719 | int i; | |
6d82d43b | 2720 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2721 | paddr_nz (addr)); |
9ace0497 AC |
2722 | for (i = 0; i < partial_len; i++) |
2723 | { | |
6d82d43b | 2724 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2725 | val[i] & 0xff); |
9ace0497 AC |
2726 | } |
2727 | } | |
2728 | write_memory (addr, val, partial_len); | |
c906108c SS |
2729 | } |
2730 | ||
f09ded24 AC |
2731 | /* Note!!! This is NOT an else clause. Odd sized |
2732 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2733 | arguments will not. */ |
566f0f7a | 2734 | /* Write this portion of the argument to a general |
6d82d43b | 2735 | purpose register. */ |
f09ded24 AC |
2736 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2737 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2738 | { |
6d82d43b AC |
2739 | LONGEST regval = |
2740 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2741 | |
9ace0497 | 2742 | if (mips_debug) |
acdb74a0 | 2743 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2744 | argreg, |
1a69e1e4 | 2745 | phex (regval, regsize)); |
9c9acae0 | 2746 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
c906108c | 2747 | argreg++; |
c906108c | 2748 | } |
c5aa993b | 2749 | |
c906108c SS |
2750 | len -= partial_len; |
2751 | val += partial_len; | |
2752 | ||
566f0f7a | 2753 | /* Compute the the offset into the stack at which we |
6d82d43b | 2754 | will copy the next parameter. |
566f0f7a | 2755 | |
566f0f7a | 2756 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2757 | only needs to be adjusted when it has been used. */ |
c906108c | 2758 | |
46e0f506 | 2759 | if (stack_used_p) |
1a69e1e4 | 2760 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2761 | } |
2762 | } | |
9ace0497 AC |
2763 | if (mips_debug) |
2764 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2765 | } |
2766 | ||
f10683bb | 2767 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2768 | |
0f71a2f6 JM |
2769 | /* Return adjusted stack pointer. */ |
2770 | return sp; | |
2771 | } | |
2772 | ||
a1f5b845 | 2773 | /* Determine the return value convention being used. */ |
6d82d43b | 2774 | |
9c8fdbfa AC |
2775 | static enum return_value_convention |
2776 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2777 | struct type *type, struct regcache *regcache, | |
47a35522 | 2778 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2779 | { |
9c8fdbfa AC |
2780 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2781 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2782 | if (readbuf) | |
2783 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2784 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2785 | } |
2786 | ||
6d82d43b AC |
2787 | |
2788 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2789 | |
8d26208a DJ |
2790 | /* Search for a naturally aligned double at OFFSET inside a struct |
2791 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
2792 | registers. */ | |
2793 | ||
2794 | static int | |
2795 | mips_n32n64_fp_arg_chunk_p (struct type *arg_type, int offset) | |
2796 | { | |
2797 | int i; | |
2798 | ||
2799 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
2800 | return 0; | |
2801 | ||
2802 | if (MIPS_FPU_TYPE != MIPS_FPU_DOUBLE) | |
2803 | return 0; | |
2804 | ||
2805 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
2806 | return 0; | |
2807 | ||
2808 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
2809 | { | |
2810 | int pos; | |
2811 | struct type *field_type; | |
2812 | ||
2813 | /* We're only looking at normal fields. */ | |
2814 | if (TYPE_FIELD_STATIC (arg_type, i) | |
2815 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) | |
2816 | continue; | |
2817 | ||
2818 | /* If we have gone past the offset, there is no double to pass. */ | |
2819 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
2820 | if (pos > offset) | |
2821 | return 0; | |
2822 | ||
2823 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
2824 | ||
2825 | /* If this field is entirely before the requested offset, go | |
2826 | on to the next one. */ | |
2827 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
2828 | continue; | |
2829 | ||
2830 | /* If this is our special aligned double, we can stop. */ | |
2831 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
2832 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
2833 | return 1; | |
2834 | ||
2835 | /* This field starts at or before the requested offset, and | |
2836 | overlaps it. If it is a structure, recurse inwards. */ | |
2837 | return mips_n32n64_fp_arg_chunk_p (field_type, offset - pos); | |
2838 | } | |
2839 | ||
2840 | return 0; | |
2841 | } | |
2842 | ||
f7ab6ec6 | 2843 | static CORE_ADDR |
7d9b040b | 2844 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2845 | struct regcache *regcache, CORE_ADDR bp_addr, |
2846 | int nargs, struct value **args, CORE_ADDR sp, | |
2847 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2848 | { |
2849 | int argreg; | |
2850 | int float_argreg; | |
2851 | int argnum; | |
2852 | int len = 0; | |
2853 | int stack_offset = 0; | |
480d3dd2 | 2854 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2855 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2856 | |
25ab4790 AC |
2857 | /* For shared libraries, "t9" needs to point at the function |
2858 | address. */ | |
4c7d22cb | 2859 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2860 | |
2861 | /* Set the return address register to point to the entry point of | |
2862 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2863 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2864 | |
cb3d25d1 MS |
2865 | /* First ensure that the stack and structure return address (if any) |
2866 | are properly aligned. The stack has to be at least 64-bit | |
2867 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2868 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2869 | aligned, so we round to this widest known alignment. */ | |
2870 | ||
5b03f266 AC |
2871 | sp = align_down (sp, 16); |
2872 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2873 | |
2874 | /* Now make space on the stack for the args. */ | |
2875 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 2876 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 2877 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2878 | |
2879 | if (mips_debug) | |
6d82d43b | 2880 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2881 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2882 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2883 | |
2884 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2885 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2886 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 2887 | |
46e0f506 | 2888 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2889 | if (struct_return) |
2890 | { | |
2891 | if (mips_debug) | |
2892 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2893 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2894 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2895 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
2896 | } |
2897 | ||
2898 | /* Now load as many as possible of the first arguments into | |
2899 | registers, and push the rest onto the stack. Loop thru args | |
2900 | from first to last. */ | |
2901 | for (argnum = 0; argnum < nargs; argnum++) | |
2902 | { | |
47a35522 | 2903 | const gdb_byte *val; |
cb3d25d1 | 2904 | struct value *arg = args[argnum]; |
4991999e | 2905 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
2906 | int len = TYPE_LENGTH (arg_type); |
2907 | enum type_code typecode = TYPE_CODE (arg_type); | |
2908 | ||
2909 | if (mips_debug) | |
2910 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2911 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2912 | argnum + 1, len, (int) typecode); |
2913 | ||
47a35522 | 2914 | val = value_contents (arg); |
cb3d25d1 MS |
2915 | |
2916 | if (fp_register_arg_p (typecode, arg_type) | |
8d26208a | 2917 | && argreg <= MIPS_LAST_ARG_REGNUM) |
cb3d25d1 MS |
2918 | { |
2919 | /* This is a floating point value that fits entirely | |
2920 | in a single register. */ | |
cb3d25d1 MS |
2921 | LONGEST regval = extract_unsigned_integer (val, len); |
2922 | if (mips_debug) | |
2923 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2924 | float_argreg, phex (regval, len)); | |
8d26208a | 2925 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
2926 | |
2927 | if (mips_debug) | |
2928 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2929 | argreg, phex (regval, len)); | |
9c9acae0 | 2930 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
2931 | float_argreg++; |
2932 | argreg++; | |
cb3d25d1 MS |
2933 | } |
2934 | else | |
2935 | { | |
2936 | /* Copy the argument to general registers or the stack in | |
2937 | register-sized pieces. Large arguments are split between | |
2938 | registers and stack. */ | |
ab2e1992 MR |
2939 | /* For N32/N64, structs, unions, or other composite types are |
2940 | treated as a sequence of doublewords, and are passed in integer | |
2941 | or floating point registers as though they were simple scalar | |
2942 | parameters to the extent that they fit, with any excess on the | |
2943 | stack packed according to the normal memory layout of the | |
2944 | object. | |
2945 | The caller does not reserve space for the register arguments; | |
2946 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 2947 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2948 | register are only written to memory. */ |
cb3d25d1 MS |
2949 | while (len > 0) |
2950 | { | |
ad018eee | 2951 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 2952 | int stack_used_p = 0; |
1a69e1e4 | 2953 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
2954 | |
2955 | if (mips_debug) | |
2956 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2957 | partial_len); | |
2958 | ||
8d26208a DJ |
2959 | if (fp_register_arg_p (typecode, arg_type)) |
2960 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM); | |
2961 | ||
cb3d25d1 | 2962 | /* Write this portion of the argument to the stack. */ |
ab2e1992 | 2963 | if (argreg > MIPS_LAST_ARG_REGNUM) |
cb3d25d1 MS |
2964 | { |
2965 | /* Should shorter than int integer values be | |
2966 | promoted to int before being stored? */ | |
2967 | int longword_offset = 0; | |
2968 | CORE_ADDR addr; | |
2969 | stack_used_p = 1; | |
72a155b4 | 2970 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 2971 | { |
1a69e1e4 DJ |
2972 | if ((typecode == TYPE_CODE_INT |
2973 | || typecode == TYPE_CODE_PTR | |
2974 | || typecode == TYPE_CODE_FLT) | |
2975 | && len <= 4) | |
2976 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
2977 | } |
2978 | ||
2979 | if (mips_debug) | |
2980 | { | |
2981 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2982 | paddr_nz (stack_offset)); | |
2983 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2984 | paddr_nz (longword_offset)); | |
2985 | } | |
2986 | ||
2987 | addr = sp + stack_offset + longword_offset; | |
2988 | ||
2989 | if (mips_debug) | |
2990 | { | |
2991 | int i; | |
6d82d43b | 2992 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
2993 | paddr_nz (addr)); |
2994 | for (i = 0; i < partial_len; i++) | |
2995 | { | |
6d82d43b | 2996 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
2997 | val[i] & 0xff); |
2998 | } | |
2999 | } | |
3000 | write_memory (addr, val, partial_len); | |
3001 | } | |
3002 | ||
3003 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3004 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3005 | /* Write this portion of the argument to a general |
6d82d43b | 3006 | purpose register. */ |
8d26208a | 3007 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
cb3d25d1 | 3008 | { |
6d82d43b AC |
3009 | LONGEST regval = |
3010 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3011 | |
3012 | /* A non-floating-point argument being passed in a | |
3013 | general register. If a struct or union, and if | |
3014 | the remaining length is smaller than the register | |
3015 | size, we have to adjust the register value on | |
3016 | big endian targets. | |
3017 | ||
3018 | It does not seem to be necessary to do the | |
1a69e1e4 | 3019 | same for integral types. */ |
cb3d25d1 | 3020 | |
72a155b4 | 3021 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3022 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3023 | && (typecode == TYPE_CODE_STRUCT |
3024 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3025 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3026 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3027 | |
3028 | if (mips_debug) | |
3029 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3030 | argreg, | |
1a69e1e4 | 3031 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3032 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3033 | |
3034 | if (mips_n32n64_fp_arg_chunk_p (arg_type, | |
3035 | TYPE_LENGTH (arg_type) - len)) | |
3036 | { | |
3037 | if (mips_debug) | |
3038 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3039 | float_argreg, | |
3040 | phex (regval, MIPS64_REGSIZE)); | |
3041 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3042 | regval); | |
3043 | } | |
3044 | ||
3045 | float_argreg++; | |
cb3d25d1 MS |
3046 | argreg++; |
3047 | } | |
3048 | ||
3049 | len -= partial_len; | |
3050 | val += partial_len; | |
3051 | ||
3052 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3053 | will copy the next parameter. |
cb3d25d1 MS |
3054 | |
3055 | In N32 (N64?), the stack_offset only needs to be | |
3056 | adjusted when it has been used. */ | |
3057 | ||
3058 | if (stack_used_p) | |
1a69e1e4 | 3059 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3060 | } |
3061 | } | |
3062 | if (mips_debug) | |
3063 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3064 | } | |
3065 | ||
f10683bb | 3066 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3067 | |
cb3d25d1 MS |
3068 | /* Return adjusted stack pointer. */ |
3069 | return sp; | |
3070 | } | |
3071 | ||
6d82d43b AC |
3072 | static enum return_value_convention |
3073 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3074 | struct type *type, struct regcache *regcache, | |
47a35522 | 3075 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3076 | { |
72a155b4 | 3077 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3078 | |
3079 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3080 | ||
3081 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3082 | if needed), as appropriate for the type. Composite results (struct, | |
3083 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3084 | following rules: | |
3085 | ||
3086 | * A struct with only one or two floating point fields is returned in $f0 | |
3087 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3088 | case. | |
3089 | ||
3090 | * Any other struct or union results of at most 128 bits are returned in | |
3091 | $2 (first 64 bits) and $3 (remainder, if necessary). | |
3092 | ||
3093 | * Larger composite results are handled by converting the function to a | |
3094 | procedure with an implicit first parameter, which is a pointer to an area | |
3095 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3096 | that all composite results be handled by conversion to implicit first | |
3097 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3098 | specific exception to return COMPLEX results in the floating point | |
3099 | registers.] */ | |
3100 | ||
3101 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3102 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3103 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3104 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3105 | && TYPE_LENGTH (type) == 16 | |
3106 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3107 | { | |
3108 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3109 | two registers are used in the same as memory order, so the | |
3110 | eight bytes with the lower memory address are in $f0. */ | |
3111 | if (mips_debug) | |
3112 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
3113 | mips_xfer_register (regcache, | |
72a155b4 UW |
3114 | gdbarch_num_regs (gdbarch) |
3115 | + mips_regnum (gdbarch)->fp0, | |
3116 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3117 | readbuf, writebuf, 0); |
d05f6826 | 3118 | mips_xfer_register (regcache, |
72a155b4 UW |
3119 | gdbarch_num_regs (gdbarch) |
3120 | + mips_regnum (gdbarch)->fp0 + 2, | |
3121 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3122 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3123 | writebuf ? writebuf + 8 : writebuf, 0); |
3124 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3125 | } | |
6d82d43b AC |
3126 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3127 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3128 | { | |
59aa1faa | 3129 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3130 | if (mips_debug) |
3131 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3132 | mips_xfer_register (regcache, | |
72a155b4 UW |
3133 | gdbarch_num_regs (gdbarch) |
3134 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3135 | TYPE_LENGTH (type), |
72a155b4 | 3136 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3137 | readbuf, writebuf, 0); |
6d82d43b AC |
3138 | return RETURN_VALUE_REGISTER_CONVENTION; |
3139 | } | |
3140 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3141 | && TYPE_NFIELDS (type) <= 2 | |
3142 | && TYPE_NFIELDS (type) >= 1 | |
3143 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3144 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3145 | == TYPE_CODE_FLT)) |
3146 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3147 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3148 | == TYPE_CODE_FLT) |
b18bb924 | 3149 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
6d82d43b AC |
3150 | == TYPE_CODE_FLT))) |
3151 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3152 | { | |
3153 | /* A struct that contains one or two floats. Each value is part | |
3154 | in the least significant part of their floating point | |
3155 | register.. */ | |
6d82d43b AC |
3156 | int regnum; |
3157 | int field; | |
72a155b4 | 3158 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
3159 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3160 | { | |
3161 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3162 | / TARGET_CHAR_BIT); | |
3163 | if (mips_debug) | |
3164 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3165 | offset); | |
72a155b4 | 3166 | mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) |
f57d151a | 3167 | + regnum, |
6d82d43b | 3168 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 3169 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3170 | readbuf, writebuf, offset); |
6d82d43b AC |
3171 | } |
3172 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3173 | } | |
3174 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3175 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3176 | { | |
3177 | /* A structure or union. Extract the left justified value, | |
3178 | regardless of the byte order. I.e. DO NOT USE | |
3179 | mips_xfer_lower. */ | |
3180 | int offset; | |
3181 | int regnum; | |
4c7d22cb | 3182 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3183 | offset < TYPE_LENGTH (type); |
72a155b4 | 3184 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3185 | { |
72a155b4 | 3186 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3187 | if (offset + xfer > TYPE_LENGTH (type)) |
3188 | xfer = TYPE_LENGTH (type) - offset; | |
3189 | if (mips_debug) | |
3190 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3191 | offset, xfer, regnum); | |
72a155b4 UW |
3192 | mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) + regnum, |
3193 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, | |
3194 | offset); | |
6d82d43b AC |
3195 | } |
3196 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3197 | } | |
3198 | else | |
3199 | { | |
3200 | /* A scalar extract each part but least-significant-byte | |
3201 | justified. */ | |
3202 | int offset; | |
3203 | int regnum; | |
4c7d22cb | 3204 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3205 | offset < TYPE_LENGTH (type); |
72a155b4 | 3206 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3207 | { |
72a155b4 | 3208 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3209 | if (offset + xfer > TYPE_LENGTH (type)) |
3210 | xfer = TYPE_LENGTH (type) - offset; | |
3211 | if (mips_debug) | |
3212 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3213 | offset, xfer, regnum); | |
72a155b4 UW |
3214 | mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) + regnum, |
3215 | xfer, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3216 | readbuf, writebuf, offset); |
6d82d43b AC |
3217 | } |
3218 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3219 | } | |
3220 | } | |
3221 | ||
3222 | /* O32 ABI stuff. */ | |
3223 | ||
3224 | static CORE_ADDR | |
7d9b040b | 3225 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3226 | struct regcache *regcache, CORE_ADDR bp_addr, |
3227 | int nargs, struct value **args, CORE_ADDR sp, | |
3228 | int struct_return, CORE_ADDR struct_addr) | |
3229 | { | |
3230 | int argreg; | |
3231 | int float_argreg; | |
3232 | int argnum; | |
3233 | int len = 0; | |
3234 | int stack_offset = 0; | |
3235 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3236 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3237 | |
3238 | /* For shared libraries, "t9" needs to point at the function | |
3239 | address. */ | |
4c7d22cb | 3240 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3241 | |
3242 | /* Set the return address register to point to the entry point of | |
3243 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3244 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3245 | |
3246 | /* First ensure that the stack and structure return address (if any) | |
3247 | are properly aligned. The stack has to be at least 64-bit | |
3248 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3249 | aligned. For n32 and n64, stack frames need to be 128-bit |
3250 | aligned, so we round to this widest known alignment. */ | |
3251 | ||
5b03f266 AC |
3252 | sp = align_down (sp, 16); |
3253 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3254 | |
3255 | /* Now make space on the stack for the args. */ | |
3256 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3257 | { |
3258 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3259 | int arglen = TYPE_LENGTH (arg_type); | |
3260 | ||
3261 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3262 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3263 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3264 | /* Allocate space on the stack. */ |
1a69e1e4 | 3265 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3266 | } |
5b03f266 | 3267 | sp -= align_up (len, 16); |
ebafbe83 MS |
3268 | |
3269 | if (mips_debug) | |
6d82d43b | 3270 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3271 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3272 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3273 | |
3274 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3275 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3276 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3277 | |
bcb0cc15 | 3278 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3279 | if (struct_return) |
3280 | { | |
3281 | if (mips_debug) | |
3282 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3283 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 | 3284 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3285 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3286 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3287 | } |
3288 | ||
3289 | /* Now load as many as possible of the first arguments into | |
3290 | registers, and push the rest onto the stack. Loop thru args | |
3291 | from first to last. */ | |
3292 | for (argnum = 0; argnum < nargs; argnum++) | |
3293 | { | |
47a35522 | 3294 | const gdb_byte *val; |
ebafbe83 | 3295 | struct value *arg = args[argnum]; |
4991999e | 3296 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3297 | int len = TYPE_LENGTH (arg_type); |
3298 | enum type_code typecode = TYPE_CODE (arg_type); | |
3299 | ||
3300 | if (mips_debug) | |
3301 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3302 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3303 | argnum + 1, len, (int) typecode); |
3304 | ||
47a35522 | 3305 | val = value_contents (arg); |
46cac009 AC |
3306 | |
3307 | /* 32-bit ABIs always start floating point arguments in an | |
3308 | even-numbered floating point register. Round the FP register | |
3309 | up before the check to see if there are any FP registers | |
3310 | left. O32/O64 targets also pass the FP in the integer | |
3311 | registers so also round up normal registers. */ | |
2afd3f0a | 3312 | if (fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3313 | { |
3314 | if ((float_argreg & 1)) | |
3315 | float_argreg++; | |
3316 | } | |
3317 | ||
3318 | /* Floating point arguments passed in registers have to be | |
3319 | treated specially. On 32-bit architectures, doubles | |
3320 | are passed in register pairs; the even register gets | |
3321 | the low word, and the odd register gets the high word. | |
3322 | On O32/O64, the first two floating point arguments are | |
3323 | also copied to general registers, because MIPS16 functions | |
3324 | don't use float registers for arguments. This duplication of | |
3325 | arguments in general registers can't hurt non-MIPS16 functions | |
3326 | because those registers are normally skipped. */ | |
3327 | ||
3328 | if (fp_register_arg_p (typecode, arg_type) | |
3329 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3330 | { | |
8b07f6d8 | 3331 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3332 | { |
72a155b4 | 3333 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3334 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3335 | unsigned long regval; |
3336 | ||
3337 | /* Write the low word of the double to the even register(s). */ | |
3338 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3339 | if (mips_debug) | |
3340 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3341 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3342 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3343 | if (mips_debug) |
3344 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3345 | argreg, phex (regval, 4)); | |
9c9acae0 | 3346 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3347 | |
3348 | /* Write the high word of the double to the odd register(s). */ | |
3349 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3350 | if (mips_debug) | |
3351 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3352 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3353 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3354 | |
3355 | if (mips_debug) | |
3356 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3357 | argreg, phex (regval, 4)); | |
9c9acae0 | 3358 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3359 | } |
3360 | else | |
3361 | { | |
3362 | /* This is a floating point value that fits entirely | |
3363 | in a single register. */ | |
3364 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3365 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3366 | LONGEST regval = extract_unsigned_integer (val, len); |
3367 | if (mips_debug) | |
3368 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3369 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3370 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 | 3371 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
6d82d43b AC |
3372 | registers for each argument. The below is (my |
3373 | guess) to ensure that the corresponding integer | |
3374 | register has reserved the same space. */ | |
46cac009 AC |
3375 | if (mips_debug) |
3376 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3377 | argreg, phex (regval, len)); | |
9c9acae0 | 3378 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3379 | argreg += 2; |
46cac009 AC |
3380 | } |
3381 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3382 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3383 | } |
3384 | else | |
3385 | { | |
3386 | /* Copy the argument to general registers or the stack in | |
3387 | register-sized pieces. Large arguments are split between | |
3388 | registers and stack. */ | |
1a69e1e4 DJ |
3389 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3390 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3391 | them in registers where gcc sometimes puts them on the |
3392 | stack. For maximum compatibility, we will put them in | |
3393 | both places. */ | |
1a69e1e4 DJ |
3394 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3395 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3396 | /* Structures should be aligned to eight bytes (even arg registers) |
3397 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3398 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3399 | { |
3400 | if ((argreg & 1)) | |
968b5391 MR |
3401 | { |
3402 | argreg++; | |
1a69e1e4 | 3403 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3404 | } |
46cac009 | 3405 | } |
46cac009 AC |
3406 | while (len > 0) |
3407 | { | |
3408 | /* Remember if the argument was written to the stack. */ | |
3409 | int stack_used_p = 0; | |
1a69e1e4 | 3410 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3411 | |
3412 | if (mips_debug) | |
3413 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3414 | partial_len); | |
3415 | ||
3416 | /* Write this portion of the argument to the stack. */ | |
3417 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3418 | || odd_sized_struct) |
46cac009 AC |
3419 | { |
3420 | /* Should shorter than int integer values be | |
3421 | promoted to int before being stored? */ | |
3422 | int longword_offset = 0; | |
3423 | CORE_ADDR addr; | |
3424 | stack_used_p = 1; | |
46cac009 AC |
3425 | |
3426 | if (mips_debug) | |
3427 | { | |
3428 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3429 | paddr_nz (stack_offset)); | |
3430 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3431 | paddr_nz (longword_offset)); | |
3432 | } | |
3433 | ||
3434 | addr = sp + stack_offset + longword_offset; | |
3435 | ||
3436 | if (mips_debug) | |
3437 | { | |
3438 | int i; | |
6d82d43b | 3439 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3440 | paddr_nz (addr)); |
3441 | for (i = 0; i < partial_len; i++) | |
3442 | { | |
6d82d43b | 3443 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3444 | val[i] & 0xff); |
3445 | } | |
3446 | } | |
3447 | write_memory (addr, val, partial_len); | |
3448 | } | |
3449 | ||
3450 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3451 | structs may go thru BOTH paths. */ |
46cac009 | 3452 | /* Write this portion of the argument to a general |
6d82d43b | 3453 | purpose register. */ |
968b5391 | 3454 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
46cac009 AC |
3455 | { |
3456 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3457 | /* Value may need to be sign extended, because |
1b13c4f6 | 3458 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3459 | |
3460 | /* A non-floating-point argument being passed in a | |
3461 | general register. If a struct or union, and if | |
3462 | the remaining length is smaller than the register | |
3463 | size, we have to adjust the register value on | |
3464 | big endian targets. | |
3465 | ||
3466 | It does not seem to be necessary to do the | |
3467 | same for integral types. | |
3468 | ||
3469 | Also don't do this adjustment on O64 binaries. | |
3470 | ||
3471 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3472 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3473 | mips_abi_regsize(), generates a left shift |
3474 | as part of storing the argument in a register | |
3475 | (the left shift isn't generated when | |
1b13c4f6 | 3476 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3477 | it is quite possible that this is GCC |
3478 | contradicting the LE/O32 ABI, GDB has not been | |
3479 | adjusted to accommodate this. Either someone | |
3480 | needs to demonstrate that the LE/O32 ABI | |
3481 | specifies such a left shift OR this new ABI gets | |
3482 | identified as such and GDB gets tweaked | |
3483 | accordingly. */ | |
3484 | ||
72a155b4 | 3485 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3486 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3487 | && (typecode == TYPE_CODE_STRUCT |
3488 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3489 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3490 | * TARGET_CHAR_BIT); |
46cac009 AC |
3491 | |
3492 | if (mips_debug) | |
3493 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3494 | argreg, | |
1a69e1e4 | 3495 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3496 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3497 | argreg++; |
3498 | ||
3499 | /* Prevent subsequent floating point arguments from | |
3500 | being passed in floating point registers. */ | |
3501 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3502 | } | |
3503 | ||
3504 | len -= partial_len; | |
3505 | val += partial_len; | |
3506 | ||
3507 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3508 | will copy the next parameter. |
46cac009 | 3509 | |
6d82d43b AC |
3510 | In older ABIs, the caller reserved space for |
3511 | registers that contained arguments. This was loosely | |
3512 | refered to as their "home". Consequently, space is | |
3513 | always allocated. */ | |
46cac009 | 3514 | |
1a69e1e4 | 3515 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3516 | } |
3517 | } | |
3518 | if (mips_debug) | |
3519 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3520 | } | |
3521 | ||
f10683bb | 3522 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3523 | |
46cac009 AC |
3524 | /* Return adjusted stack pointer. */ |
3525 | return sp; | |
3526 | } | |
3527 | ||
6d82d43b AC |
3528 | static enum return_value_convention |
3529 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3530 | struct regcache *regcache, | |
47a35522 | 3531 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3532 | { |
72a155b4 | 3533 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
3534 | |
3535 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3536 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3537 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3538 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3539 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3540 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3541 | { | |
3542 | /* A single-precision floating-point value. It fits in the | |
3543 | least significant part of FP0. */ | |
3544 | if (mips_debug) | |
3545 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3546 | mips_xfer_register (regcache, | |
72a155b4 UW |
3547 | gdbarch_num_regs (gdbarch) |
3548 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3549 | TYPE_LENGTH (type), |
72a155b4 | 3550 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3551 | readbuf, writebuf, 0); |
6d82d43b AC |
3552 | return RETURN_VALUE_REGISTER_CONVENTION; |
3553 | } | |
3554 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3555 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3556 | { | |
3557 | /* A double-precision floating-point value. The most | |
3558 | significant part goes in FP1, and the least significant in | |
3559 | FP0. */ | |
3560 | if (mips_debug) | |
3561 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 3562 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
3563 | { |
3564 | case BFD_ENDIAN_LITTLE: | |
3565 | mips_xfer_register (regcache, | |
72a155b4 UW |
3566 | gdbarch_num_regs (gdbarch) |
3567 | + mips_regnum (gdbarch)->fp0 + | |
3568 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3569 | readbuf, writebuf, 0); |
6d82d43b | 3570 | mips_xfer_register (regcache, |
72a155b4 UW |
3571 | gdbarch_num_regs (gdbarch) |
3572 | + mips_regnum (gdbarch)->fp0 + 1, | |
3573 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3574 | readbuf, writebuf, 4); |
6d82d43b AC |
3575 | break; |
3576 | case BFD_ENDIAN_BIG: | |
3577 | mips_xfer_register (regcache, | |
72a155b4 UW |
3578 | gdbarch_num_regs (gdbarch) |
3579 | + mips_regnum (gdbarch)->fp0 + 1, | |
3580 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3581 | readbuf, writebuf, 0); |
6d82d43b | 3582 | mips_xfer_register (regcache, |
72a155b4 UW |
3583 | gdbarch_num_regs (gdbarch) |
3584 | + mips_regnum (gdbarch)->fp0 + 0, | |
3585 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3586 | readbuf, writebuf, 4); |
6d82d43b AC |
3587 | break; |
3588 | default: | |
e2e0b3e5 | 3589 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3590 | } |
3591 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3592 | } | |
3593 | #if 0 | |
3594 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3595 | && TYPE_NFIELDS (type) <= 2 | |
3596 | && TYPE_NFIELDS (type) >= 1 | |
3597 | && ((TYPE_NFIELDS (type) == 1 | |
3598 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3599 | == TYPE_CODE_FLT)) | |
3600 | || (TYPE_NFIELDS (type) == 2 | |
3601 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3602 | == TYPE_CODE_FLT) | |
3603 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3604 | == TYPE_CODE_FLT))) | |
3605 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3606 | { | |
3607 | /* A struct that contains one or two floats. Each value is part | |
3608 | in the least significant part of their floating point | |
3609 | register.. */ | |
870cd05e | 3610 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3611 | int regnum; |
3612 | int field; | |
72a155b4 | 3613 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
3614 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3615 | { | |
3616 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3617 | / TARGET_CHAR_BIT); | |
3618 | if (mips_debug) | |
3619 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3620 | offset); | |
72a155b4 | 3621 | mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) |
f57d151a | 3622 | + regnum, |
6d82d43b | 3623 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 3624 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3625 | readbuf, writebuf, offset); |
6d82d43b AC |
3626 | } |
3627 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3628 | } | |
3629 | #endif | |
3630 | #if 0 | |
3631 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3632 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3633 | { | |
3634 | /* A structure or union. Extract the left justified value, | |
3635 | regardless of the byte order. I.e. DO NOT USE | |
3636 | mips_xfer_lower. */ | |
3637 | int offset; | |
3638 | int regnum; | |
4c7d22cb | 3639 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3640 | offset < TYPE_LENGTH (type); |
72a155b4 | 3641 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3642 | { |
72a155b4 | 3643 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3644 | if (offset + xfer > TYPE_LENGTH (type)) |
3645 | xfer = TYPE_LENGTH (type) - offset; | |
3646 | if (mips_debug) | |
3647 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3648 | offset, xfer, regnum); | |
72a155b4 | 3649 | mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) |
f57d151a | 3650 | + regnum, xfer, |
6d82d43b AC |
3651 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3652 | } | |
3653 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3654 | } | |
3655 | #endif | |
3656 | else | |
3657 | { | |
3658 | /* A scalar extract each part but least-significant-byte | |
3659 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3660 | the ISA. */ |
6d82d43b AC |
3661 | int offset; |
3662 | int regnum; | |
4c7d22cb | 3663 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3664 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3665 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3666 | { |
1a69e1e4 | 3667 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3668 | if (offset + xfer > TYPE_LENGTH (type)) |
3669 | xfer = TYPE_LENGTH (type) - offset; | |
3670 | if (mips_debug) | |
3671 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3672 | offset, xfer, regnum); | |
72a155b4 | 3673 | mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) |
f57d151a | 3674 | + regnum, xfer, |
72a155b4 | 3675 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3676 | readbuf, writebuf, offset); |
6d82d43b AC |
3677 | } |
3678 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3679 | } | |
3680 | } | |
3681 | ||
3682 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3683 | ABI. */ | |
46cac009 AC |
3684 | |
3685 | static CORE_ADDR | |
7d9b040b | 3686 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3687 | struct regcache *regcache, CORE_ADDR bp_addr, |
3688 | int nargs, | |
3689 | struct value **args, CORE_ADDR sp, | |
3690 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3691 | { |
3692 | int argreg; | |
3693 | int float_argreg; | |
3694 | int argnum; | |
3695 | int len = 0; | |
3696 | int stack_offset = 0; | |
480d3dd2 | 3697 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3698 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3699 | |
25ab4790 AC |
3700 | /* For shared libraries, "t9" needs to point at the function |
3701 | address. */ | |
4c7d22cb | 3702 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3703 | |
3704 | /* Set the return address register to point to the entry point of | |
3705 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3706 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3707 | |
46cac009 AC |
3708 | /* First ensure that the stack and structure return address (if any) |
3709 | are properly aligned. The stack has to be at least 64-bit | |
3710 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3711 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3712 | aligned, so we round to this widest known alignment. */ | |
3713 | ||
5b03f266 AC |
3714 | sp = align_down (sp, 16); |
3715 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3716 | |
3717 | /* Now make space on the stack for the args. */ | |
3718 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3719 | { |
3720 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3721 | int arglen = TYPE_LENGTH (arg_type); | |
3722 | ||
968b5391 | 3723 | /* Allocate space on the stack. */ |
1a69e1e4 | 3724 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 3725 | } |
5b03f266 | 3726 | sp -= align_up (len, 16); |
46cac009 AC |
3727 | |
3728 | if (mips_debug) | |
6d82d43b | 3729 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3730 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3731 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3732 | |
3733 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3734 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3735 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
3736 | |
3737 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3738 | if (struct_return) | |
3739 | { | |
3740 | if (mips_debug) | |
3741 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3742 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 | 3743 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3744 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3745 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
3746 | } |
3747 | ||
3748 | /* Now load as many as possible of the first arguments into | |
3749 | registers, and push the rest onto the stack. Loop thru args | |
3750 | from first to last. */ | |
3751 | for (argnum = 0; argnum < nargs; argnum++) | |
3752 | { | |
47a35522 | 3753 | const gdb_byte *val; |
46cac009 | 3754 | struct value *arg = args[argnum]; |
4991999e | 3755 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
3756 | int len = TYPE_LENGTH (arg_type); |
3757 | enum type_code typecode = TYPE_CODE (arg_type); | |
3758 | ||
3759 | if (mips_debug) | |
3760 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3761 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3762 | argnum + 1, len, (int) typecode); |
3763 | ||
47a35522 | 3764 | val = value_contents (arg); |
ebafbe83 | 3765 | |
ebafbe83 MS |
3766 | /* Floating point arguments passed in registers have to be |
3767 | treated specially. On 32-bit architectures, doubles | |
3768 | are passed in register pairs; the even register gets | |
3769 | the low word, and the odd register gets the high word. | |
3770 | On O32/O64, the first two floating point arguments are | |
3771 | also copied to general registers, because MIPS16 functions | |
3772 | don't use float registers for arguments. This duplication of | |
3773 | arguments in general registers can't hurt non-MIPS16 functions | |
3774 | because those registers are normally skipped. */ | |
3775 | ||
3776 | if (fp_register_arg_p (typecode, arg_type) | |
3777 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3778 | { | |
2afd3f0a MR |
3779 | LONGEST regval = extract_unsigned_integer (val, len); |
3780 | if (mips_debug) | |
3781 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3782 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3783 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
3784 | if (mips_debug) |
3785 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3786 | argreg, phex (regval, len)); | |
9c9acae0 | 3787 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3788 | argreg++; |
ebafbe83 | 3789 | /* Reserve space for the FP register. */ |
1a69e1e4 | 3790 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
3791 | } |
3792 | else | |
3793 | { | |
3794 | /* Copy the argument to general registers or the stack in | |
3795 | register-sized pieces. Large arguments are split between | |
3796 | registers and stack. */ | |
1a69e1e4 | 3797 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
3798 | are treated specially: Irix cc passes them in registers |
3799 | where gcc sometimes puts them on the stack. For maximum | |
3800 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
3801 | int odd_sized_struct = (len > MIPS64_REGSIZE |
3802 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
3803 | while (len > 0) |
3804 | { | |
3805 | /* Remember if the argument was written to the stack. */ | |
3806 | int stack_used_p = 0; | |
1a69e1e4 | 3807 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
3808 | |
3809 | if (mips_debug) | |
3810 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3811 | partial_len); | |
3812 | ||
3813 | /* Write this portion of the argument to the stack. */ | |
3814 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3815 | || odd_sized_struct) |
ebafbe83 MS |
3816 | { |
3817 | /* Should shorter than int integer values be | |
3818 | promoted to int before being stored? */ | |
3819 | int longword_offset = 0; | |
3820 | CORE_ADDR addr; | |
3821 | stack_used_p = 1; | |
72a155b4 | 3822 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 3823 | { |
1a69e1e4 DJ |
3824 | if ((typecode == TYPE_CODE_INT |
3825 | || typecode == TYPE_CODE_PTR | |
3826 | || typecode == TYPE_CODE_FLT) | |
3827 | && len <= 4) | |
3828 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
3829 | } |
3830 | ||
3831 | if (mips_debug) | |
3832 | { | |
3833 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3834 | paddr_nz (stack_offset)); | |
3835 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3836 | paddr_nz (longword_offset)); | |
3837 | } | |
3838 | ||
3839 | addr = sp + stack_offset + longword_offset; | |
3840 | ||
3841 | if (mips_debug) | |
3842 | { | |
3843 | int i; | |
6d82d43b | 3844 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3845 | paddr_nz (addr)); |
3846 | for (i = 0; i < partial_len; i++) | |
3847 | { | |
6d82d43b | 3848 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3849 | val[i] & 0xff); |
3850 | } | |
3851 | } | |
3852 | write_memory (addr, val, partial_len); | |
3853 | } | |
3854 | ||
3855 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3856 | structs may go thru BOTH paths. */ |
ebafbe83 | 3857 | /* Write this portion of the argument to a general |
6d82d43b | 3858 | purpose register. */ |
968b5391 | 3859 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
ebafbe83 MS |
3860 | { |
3861 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3862 | /* Value may need to be sign extended, because |
1b13c4f6 | 3863 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3864 | |
3865 | /* A non-floating-point argument being passed in a | |
3866 | general register. If a struct or union, and if | |
3867 | the remaining length is smaller than the register | |
3868 | size, we have to adjust the register value on | |
3869 | big endian targets. | |
3870 | ||
3871 | It does not seem to be necessary to do the | |
401835eb | 3872 | same for integral types. */ |
480d3dd2 | 3873 | |
72a155b4 | 3874 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3875 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3876 | && (typecode == TYPE_CODE_STRUCT |
3877 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3878 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3879 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
3880 | |
3881 | if (mips_debug) | |
3882 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3883 | argreg, | |
1a69e1e4 | 3884 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3885 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
3886 | argreg++; |
3887 | ||
3888 | /* Prevent subsequent floating point arguments from | |
3889 | being passed in floating point registers. */ | |
3890 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3891 | } | |
3892 | ||
3893 | len -= partial_len; | |
3894 | val += partial_len; | |
3895 | ||
3896 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3897 | will copy the next parameter. |
ebafbe83 | 3898 | |
6d82d43b AC |
3899 | In older ABIs, the caller reserved space for |
3900 | registers that contained arguments. This was loosely | |
3901 | refered to as their "home". Consequently, space is | |
3902 | always allocated. */ | |
ebafbe83 | 3903 | |
1a69e1e4 | 3904 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
3905 | } |
3906 | } | |
3907 | if (mips_debug) | |
3908 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3909 | } | |
3910 | ||
f10683bb | 3911 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3912 | |
ebafbe83 MS |
3913 | /* Return adjusted stack pointer. */ |
3914 | return sp; | |
3915 | } | |
3916 | ||
9c8fdbfa AC |
3917 | static enum return_value_convention |
3918 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3919 | struct type *type, struct regcache *regcache, | |
47a35522 | 3920 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3921 | { |
72a155b4 | 3922 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
3923 | |
3924 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3925 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3926 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3927 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3928 | else if (fp_register_arg_p (TYPE_CODE (type), type)) | |
3929 | { | |
3930 | /* A floating-point value. It fits in the least significant | |
3931 | part of FP0. */ | |
3932 | if (mips_debug) | |
3933 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3934 | mips_xfer_register (regcache, | |
72a155b4 UW |
3935 | gdbarch_num_regs (gdbarch) |
3936 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 3937 | TYPE_LENGTH (type), |
72a155b4 | 3938 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3939 | readbuf, writebuf, 0); |
7a076fd2 FF |
3940 | return RETURN_VALUE_REGISTER_CONVENTION; |
3941 | } | |
3942 | else | |
3943 | { | |
3944 | /* A scalar extract each part but least-significant-byte | |
3945 | justified. */ | |
3946 | int offset; | |
3947 | int regnum; | |
3948 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
3949 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 3950 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 3951 | { |
1a69e1e4 | 3952 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
3953 | if (offset + xfer > TYPE_LENGTH (type)) |
3954 | xfer = TYPE_LENGTH (type) - offset; | |
3955 | if (mips_debug) | |
3956 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3957 | offset, xfer, regnum); | |
72a155b4 UW |
3958 | mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) + regnum, |
3959 | xfer, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3960 | readbuf, writebuf, offset); |
7a076fd2 FF |
3961 | } |
3962 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3963 | } | |
6d82d43b AC |
3964 | } |
3965 | ||
dd824b04 DJ |
3966 | /* Floating point register management. |
3967 | ||
3968 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3969 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3970 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3971 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3972 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3973 | double precision floats into two 32-bit chunks and store them in | |
3974 | consecutive fp regs. To display 64-bit floats stored in this | |
3975 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3976 | Throw in user-configurable endianness and you have a real mess. | |
3977 | ||
3978 | The way this works is: | |
3979 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3980 | double-precision value will be split across two logical registers. | |
3981 | The lower-numbered logical register will hold the low-order bits, | |
3982 | regardless of the processor's endianness. | |
3983 | - If we are on a 64-bit processor, and we are looking for a | |
3984 | single-precision value, it will be in the low ordered bits | |
3985 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3986 | save slot in memory. | |
3987 | - If we are in 64-bit mode, everything is straightforward. | |
3988 | ||
3989 | Note that this code only deals with "live" registers at the top of the | |
3990 | stack. We will attempt to deal with saved registers later, when | |
3991 | the raw/cooked register interface is in place. (We need a general | |
3992 | interface that can deal with dynamic saved register sizes -- fp | |
3993 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3994 | and below). */ | |
3995 | ||
67b2c998 DJ |
3996 | static struct type * |
3997 | mips_float_register_type (void) | |
3998 | { | |
8da61cc4 | 3999 | return builtin_type_ieee_single; |
67b2c998 DJ |
4000 | } |
4001 | ||
4002 | static struct type * | |
4003 | mips_double_register_type (void) | |
4004 | { | |
8da61cc4 | 4005 | return builtin_type_ieee_double; |
67b2c998 DJ |
4006 | } |
4007 | ||
dd824b04 DJ |
4008 | /* Copy a 32-bit single-precision value from the current frame |
4009 | into rare_buffer. */ | |
4010 | ||
4011 | static void | |
e11c53d2 | 4012 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4013 | gdb_byte *rare_buffer) |
dd824b04 | 4014 | { |
72a155b4 UW |
4015 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4016 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4017 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4018 | |
e11c53d2 | 4019 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4020 | error (_("can't read register %d (%s)"), |
72a155b4 | 4021 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4022 | if (raw_size == 8) |
4023 | { | |
4024 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4025 | 32 bits. */ |
dd824b04 DJ |
4026 | int offset; |
4027 | ||
72a155b4 | 4028 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4029 | offset = 4; |
4030 | else | |
4031 | offset = 0; | |
4032 | ||
4033 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4034 | } | |
4035 | else | |
4036 | { | |
4037 | memcpy (rare_buffer, raw_buffer, 4); | |
4038 | } | |
4039 | } | |
4040 | ||
4041 | /* Copy a 64-bit double-precision value from the current frame into | |
4042 | rare_buffer. This may include getting half of it from the next | |
4043 | register. */ | |
4044 | ||
4045 | static void | |
e11c53d2 | 4046 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4047 | gdb_byte *rare_buffer) |
dd824b04 | 4048 | { |
72a155b4 UW |
4049 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4050 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4051 | |
9c9acae0 | 4052 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4053 | { |
4054 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4055 | all 64 bits. */ |
e11c53d2 | 4056 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4057 | error (_("can't read register %d (%s)"), |
72a155b4 | 4058 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4059 | } |
4060 | else | |
4061 | { | |
72a155b4 | 4062 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4063 | |
72a155b4 | 4064 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4065 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4066 | _("mips_read_fp_register_double: bad access to " |
4067 | "odd-numbered FP register")); | |
dd824b04 DJ |
4068 | |
4069 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4070 | each register. */ |
72a155b4 | 4071 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4072 | { |
e11c53d2 AC |
4073 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4074 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4075 | } |
361d1df0 | 4076 | else |
dd824b04 | 4077 | { |
e11c53d2 AC |
4078 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4079 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4080 | } |
4081 | } | |
4082 | } | |
4083 | ||
c906108c | 4084 | static void |
e11c53d2 AC |
4085 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4086 | int regnum) | |
c5aa993b | 4087 | { /* do values for FP (float) regs */ |
72a155b4 | 4088 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4089 | gdb_byte *raw_buffer; |
3903d437 AC |
4090 | double doub, flt1; /* doubles extracted from raw hex data */ |
4091 | int inv1, inv2; | |
c5aa993b | 4092 | |
72a155b4 | 4093 | raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)); |
c906108c | 4094 | |
72a155b4 | 4095 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4096 | fprintf_filtered (file, "%*s", |
72a155b4 | 4097 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4098 | ""); |
f0ef6b29 | 4099 | |
72a155b4 | 4100 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4101 | { |
f0ef6b29 KB |
4102 | /* 4-byte registers: Print hex and floating. Also print even |
4103 | numbered registers as doubles. */ | |
e11c53d2 | 4104 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4105 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4106 | |
6d82d43b AC |
4107 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4108 | file); | |
dd824b04 | 4109 | |
e11c53d2 | 4110 | fprintf_filtered (file, " flt: "); |
1adad886 | 4111 | if (inv1) |
e11c53d2 | 4112 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4113 | else |
e11c53d2 | 4114 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4115 | |
72a155b4 | 4116 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4117 | { |
e11c53d2 | 4118 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4119 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4120 | &inv2); |
1adad886 | 4121 | |
e11c53d2 | 4122 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4123 | if (inv2) |
e11c53d2 | 4124 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4125 | else |
e11c53d2 | 4126 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4127 | } |
c906108c SS |
4128 | } |
4129 | else | |
dd824b04 | 4130 | { |
f0ef6b29 | 4131 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4132 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4133 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4134 | |
e11c53d2 | 4135 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4136 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4137 | ||
361d1df0 | 4138 | |
6d82d43b AC |
4139 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4140 | file); | |
f0ef6b29 | 4141 | |
e11c53d2 | 4142 | fprintf_filtered (file, " flt: "); |
1adad886 | 4143 | if (inv1) |
e11c53d2 | 4144 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4145 | else |
e11c53d2 | 4146 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4147 | |
e11c53d2 | 4148 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4149 | if (inv2) |
e11c53d2 | 4150 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4151 | else |
e11c53d2 | 4152 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4153 | } |
4154 | } | |
4155 | ||
4156 | static void | |
e11c53d2 | 4157 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4158 | int regnum) |
f0ef6b29 | 4159 | { |
a4b8ebc8 | 4160 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4161 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4162 | int offset; |
1adad886 | 4163 | |
7b9ee6a8 | 4164 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4165 | { |
e11c53d2 | 4166 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4167 | return; |
4168 | } | |
4169 | ||
4170 | /* Get the data in raw format. */ | |
e11c53d2 | 4171 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4172 | { |
c9f4d572 | 4173 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4174 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4175 | return; |
c906108c | 4176 | } |
f0ef6b29 | 4177 | |
72a155b4 | 4178 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4179 | |
4180 | /* The problem with printing numeric register names (r26, etc.) is that | |
4181 | the user can't use them on input. Probably the best solution is to | |
4182 | fix it so that either the numeric or the funky (a2, etc.) names | |
4183 | are accepted on input. */ | |
4184 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4185 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4186 | else |
e11c53d2 | 4187 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4188 | |
72a155b4 | 4189 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4190 | offset = |
72a155b4 | 4191 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
f0ef6b29 KB |
4192 | else |
4193 | offset = 0; | |
4194 | ||
6d82d43b | 4195 | print_scalar_formatted (raw_buffer + offset, |
7b9ee6a8 | 4196 | register_type (gdbarch, regnum), 'x', 0, |
6d82d43b | 4197 | file); |
c906108c SS |
4198 | } |
4199 | ||
f0ef6b29 KB |
4200 | /* Replacement for generic do_registers_info. |
4201 | Print regs in pretty columns. */ | |
4202 | ||
4203 | static int | |
e11c53d2 AC |
4204 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4205 | int regnum) | |
f0ef6b29 | 4206 | { |
e11c53d2 AC |
4207 | fprintf_filtered (file, " "); |
4208 | mips_print_fp_register (file, frame, regnum); | |
4209 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4210 | return regnum + 1; |
4211 | } | |
4212 | ||
4213 | ||
c906108c SS |
4214 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4215 | ||
4216 | static int | |
e11c53d2 | 4217 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4218 | int start_regnum) |
c906108c | 4219 | { |
a4b8ebc8 | 4220 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4221 | /* do values for GP (int) regs */ |
47a35522 | 4222 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4223 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4224 | int col, byte; |
a4b8ebc8 | 4225 | int regnum; |
c906108c SS |
4226 | |
4227 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4228 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4229 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4230 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4231 | regnum++) |
c906108c | 4232 | { |
72a155b4 | 4233 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4234 | continue; /* unused register */ |
7b9ee6a8 | 4235 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4236 | TYPE_CODE_FLT) |
c5aa993b | 4237 | break; /* end the row: reached FP register */ |
0cc93a06 | 4238 | /* Large registers are handled separately. */ |
72a155b4 | 4239 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4240 | { |
4241 | if (col > 0) | |
4242 | break; /* End the row before this register. */ | |
4243 | ||
4244 | /* Print this register on a row by itself. */ | |
4245 | mips_print_register (file, frame, regnum); | |
4246 | fprintf_filtered (file, "\n"); | |
4247 | return regnum + 1; | |
4248 | } | |
d05f6826 DJ |
4249 | if (col == 0) |
4250 | fprintf_filtered (file, " "); | |
6d82d43b | 4251 | fprintf_filtered (file, |
72a155b4 UW |
4252 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4253 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4254 | col++; |
4255 | } | |
d05f6826 DJ |
4256 | |
4257 | if (col == 0) | |
4258 | return regnum; | |
4259 | ||
a4b8ebc8 | 4260 | /* print the R0 to R31 names */ |
72a155b4 | 4261 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4262 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4263 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4264 | else |
4265 | fprintf_filtered (file, "\n "); | |
c906108c | 4266 | |
c906108c | 4267 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4268 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4269 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4270 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4271 | regnum++) |
c906108c | 4272 | { |
72a155b4 | 4273 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4274 | continue; /* unused register */ |
7b9ee6a8 | 4275 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4276 | TYPE_CODE_FLT) |
c5aa993b | 4277 | break; /* end row: reached FP register */ |
72a155b4 | 4278 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4279 | break; /* End row: large register. */ |
4280 | ||
c906108c | 4281 | /* OK: get the data in raw format. */ |
e11c53d2 | 4282 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4283 | error (_("can't read register %d (%s)"), |
72a155b4 | 4284 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4285 | /* pad small registers */ |
4246e332 | 4286 | for (byte = 0; |
72a155b4 UW |
4287 | byte < (mips_abi_regsize (gdbarch) |
4288 | - register_size (gdbarch, regnum)); byte++) | |
c906108c SS |
4289 | printf_filtered (" "); |
4290 | /* Now print the register value in hex, endian order. */ | |
72a155b4 | 4291 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4292 | for (byte = |
72a155b4 UW |
4293 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4294 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4295 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4296 | else |
72a155b4 | 4297 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4298 | byte >= 0; byte--) |
47a35522 | 4299 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4300 | fprintf_filtered (file, " "); |
c906108c SS |
4301 | col++; |
4302 | } | |
c5aa993b | 4303 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4304 | fprintf_filtered (file, "\n"); |
c906108c SS |
4305 | |
4306 | return regnum; | |
4307 | } | |
4308 | ||
4309 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4310 | ||
bf1f5b4c | 4311 | static void |
e11c53d2 AC |
4312 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4313 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4314 | { |
c5aa993b | 4315 | if (regnum != -1) /* do one specified register */ |
c906108c | 4316 | { |
72a155b4 UW |
4317 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4318 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4319 | error (_("Not a valid register for the current processor type")); |
c906108c | 4320 | |
0cc93a06 | 4321 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4322 | fprintf_filtered (file, "\n"); |
c906108c | 4323 | } |
c5aa993b JM |
4324 | else |
4325 | /* do all (or most) registers */ | |
c906108c | 4326 | { |
72a155b4 UW |
4327 | regnum = gdbarch_num_regs (gdbarch); |
4328 | while (regnum < gdbarch_num_regs (gdbarch) | |
4329 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4330 | { |
7b9ee6a8 | 4331 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4332 | TYPE_CODE_FLT) |
e11c53d2 AC |
4333 | { |
4334 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4335 | regnum = print_fp_register_row (file, frame, regnum); | |
4336 | else | |
4337 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4338 | } | |
c906108c | 4339 | else |
e11c53d2 | 4340 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4341 | } |
4342 | } | |
4343 | } | |
4344 | ||
c906108c SS |
4345 | /* Is this a branch with a delay slot? */ |
4346 | ||
c906108c | 4347 | static int |
acdb74a0 | 4348 | is_delayed (unsigned long insn) |
c906108c SS |
4349 | { |
4350 | int i; | |
4351 | for (i = 0; i < NUMOPCODES; ++i) | |
4352 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4353 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4354 | break; | |
4355 | return (i < NUMOPCODES | |
4356 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4357 | | INSN_COND_BRANCH_DELAY | |
4358 | | INSN_COND_BRANCH_LIKELY))); | |
4359 | } | |
4360 | ||
4361 | int | |
3352ef37 AC |
4362 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4363 | struct frame_info *frame) | |
c906108c | 4364 | { |
3352ef37 | 4365 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4366 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4367 | |
4368 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4369 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4370 | return 0; |
4371 | ||
06648491 MK |
4372 | if (!breakpoint_here_p (pc + 4)) |
4373 | return 0; | |
4374 | ||
3352ef37 AC |
4375 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4376 | /* If error reading memory, guess that it is not a delayed | |
4377 | branch. */ | |
c906108c | 4378 | return 0; |
4c7d22cb | 4379 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4380 | } |
4381 | ||
6d82d43b AC |
4382 | /* To skip prologues, I use this predicate. Returns either PC itself |
4383 | if the code at PC does not look like a function prologue; otherwise | |
4384 | returns an address that (if we're lucky) follows the prologue. If | |
4385 | LENIENT, then we must skip everything which is involved in setting | |
4386 | up the frame (it's OK to skip more, just so long as we don't skip | |
4387 | anything which might clobber the registers which are being saved. | |
4388 | We must skip more in the case where part of the prologue is in the | |
4389 | delay slot of a non-prologue instruction). */ | |
4390 | ||
4391 | static CORE_ADDR | |
4392 | mips_skip_prologue (CORE_ADDR pc) | |
4393 | { | |
8b622e6a AC |
4394 | CORE_ADDR limit_pc; |
4395 | CORE_ADDR func_addr; | |
4396 | ||
6d82d43b AC |
4397 | /* See if we can determine the end of the prologue via the symbol table. |
4398 | If so, then return either PC, or the PC after the prologue, whichever | |
4399 | is greater. */ | |
8b622e6a AC |
4400 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4401 | { | |
4402 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4403 | if (post_prologue_pc != 0) | |
4404 | return max (pc, post_prologue_pc); | |
4405 | } | |
6d82d43b AC |
4406 | |
4407 | /* Can't determine prologue from the symbol table, need to examine | |
4408 | instructions. */ | |
4409 | ||
98b4dd94 JB |
4410 | /* Find an upper limit on the function prologue using the debug |
4411 | information. If the debug information could not be used to provide | |
4412 | that bound, then use an arbitrary large number as the upper bound. */ | |
4413 | limit_pc = skip_prologue_using_sal (pc); | |
4414 | if (limit_pc == 0) | |
4415 | limit_pc = pc + 100; /* Magic. */ | |
4416 | ||
0fe7e7c8 | 4417 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4418 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4419 | else |
a65bbe44 | 4420 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4421 | } |
4422 | ||
97ab0fdd MR |
4423 | /* Check whether the PC is in a function epilogue (32-bit version). |
4424 | This is a helper function for mips_in_function_epilogue_p. */ | |
4425 | static int | |
4426 | mips32_in_function_epilogue_p (CORE_ADDR pc) | |
4427 | { | |
4428 | CORE_ADDR func_addr = 0, func_end = 0; | |
4429 | ||
4430 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4431 | { | |
4432 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4433 | CORE_ADDR addr = func_end - 12; | |
4434 | ||
4435 | if (addr < func_addr + 4) | |
4436 | addr = func_addr + 4; | |
4437 | if (pc < addr) | |
4438 | return 0; | |
4439 | ||
4440 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4441 | { | |
4442 | unsigned long high_word; | |
4443 | unsigned long inst; | |
4444 | ||
4445 | inst = mips_fetch_instruction (pc); | |
4446 | high_word = (inst >> 16) & 0xffff; | |
4447 | ||
4448 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4449 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4450 | && inst != 0x03e00008 /* jr $ra */ | |
4451 | && inst != 0x00000000) /* nop */ | |
4452 | return 0; | |
4453 | } | |
4454 | ||
4455 | return 1; | |
4456 | } | |
4457 | ||
4458 | return 0; | |
4459 | } | |
4460 | ||
4461 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4462 | This is a helper function for mips_in_function_epilogue_p. */ | |
4463 | static int | |
4464 | mips16_in_function_epilogue_p (CORE_ADDR pc) | |
4465 | { | |
4466 | CORE_ADDR func_addr = 0, func_end = 0; | |
4467 | ||
4468 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4469 | { | |
4470 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4471 | CORE_ADDR addr = func_end - 12; | |
4472 | ||
4473 | if (addr < func_addr + 4) | |
4474 | addr = func_addr + 4; | |
4475 | if (pc < addr) | |
4476 | return 0; | |
4477 | ||
4478 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4479 | { | |
4480 | unsigned short inst; | |
4481 | ||
4482 | inst = mips_fetch_instruction (pc); | |
4483 | ||
4484 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4485 | continue; | |
4486 | ||
4487 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4488 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4489 | && inst != 0xe820 /* jr $ra */ | |
4490 | && inst != 0xe8a0 /* jrc $ra */ | |
4491 | && inst != 0x6500) /* nop */ | |
4492 | return 0; | |
4493 | } | |
4494 | ||
4495 | return 1; | |
4496 | } | |
4497 | ||
4498 | return 0; | |
4499 | } | |
4500 | ||
4501 | /* The epilogue is defined here as the area at the end of a function, | |
4502 | after an instruction which destroys the function's stack frame. */ | |
4503 | static int | |
4504 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4505 | { | |
4506 | if (mips_pc_is_mips16 (pc)) | |
4507 | return mips16_in_function_epilogue_p (pc); | |
4508 | else | |
4509 | return mips32_in_function_epilogue_p (pc); | |
4510 | } | |
4511 | ||
a5ea2558 AC |
4512 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4513 | used for all MIPS-specific commands. */ | |
4514 | ||
a5ea2558 | 4515 | static void |
acdb74a0 | 4516 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4517 | { |
4518 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4519 | } | |
4520 | ||
a5ea2558 | 4521 | static void |
acdb74a0 | 4522 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4523 | { |
6d82d43b AC |
4524 | printf_unfiltered |
4525 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4526 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4527 | } | |
4528 | ||
c906108c SS |
4529 | /* Commands to show/set the MIPS FPU type. */ |
4530 | ||
c906108c | 4531 | static void |
acdb74a0 | 4532 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4533 | { |
c906108c SS |
4534 | char *fpu; |
4535 | switch (MIPS_FPU_TYPE) | |
4536 | { | |
4537 | case MIPS_FPU_SINGLE: | |
4538 | fpu = "single-precision"; | |
4539 | break; | |
4540 | case MIPS_FPU_DOUBLE: | |
4541 | fpu = "double-precision"; | |
4542 | break; | |
4543 | case MIPS_FPU_NONE: | |
4544 | fpu = "absent (none)"; | |
4545 | break; | |
93d56215 | 4546 | default: |
e2e0b3e5 | 4547 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4548 | } |
4549 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4550 | printf_unfiltered |
4551 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4552 | fpu); | |
c906108c | 4553 | else |
6d82d43b AC |
4554 | printf_unfiltered |
4555 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4556 | } |
4557 | ||
4558 | ||
c906108c | 4559 | static void |
acdb74a0 | 4560 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4561 | { |
6d82d43b AC |
4562 | printf_unfiltered |
4563 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4564 | show_mipsfpu_command (args, from_tty); |
4565 | } | |
4566 | ||
c906108c | 4567 | static void |
acdb74a0 | 4568 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4569 | { |
8d5838b5 AC |
4570 | struct gdbarch_info info; |
4571 | gdbarch_info_init (&info); | |
c906108c SS |
4572 | mips_fpu_type = MIPS_FPU_SINGLE; |
4573 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4574 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4575 | instead of relying on globals. Doing that would let generic code | |
4576 | handle the search for this specific architecture. */ | |
4577 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4578 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4579 | } |
4580 | ||
c906108c | 4581 | static void |
acdb74a0 | 4582 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4583 | { |
8d5838b5 AC |
4584 | struct gdbarch_info info; |
4585 | gdbarch_info_init (&info); | |
c906108c SS |
4586 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4587 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4588 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4589 | instead of relying on globals. Doing that would let generic code | |
4590 | handle the search for this specific architecture. */ | |
4591 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4592 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4593 | } |
4594 | ||
c906108c | 4595 | static void |
acdb74a0 | 4596 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4597 | { |
8d5838b5 AC |
4598 | struct gdbarch_info info; |
4599 | gdbarch_info_init (&info); | |
c906108c SS |
4600 | mips_fpu_type = MIPS_FPU_NONE; |
4601 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4602 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4603 | instead of relying on globals. Doing that would let generic code | |
4604 | handle the search for this specific architecture. */ | |
4605 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4606 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4607 | } |
4608 | ||
c906108c | 4609 | static void |
acdb74a0 | 4610 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4611 | { |
4612 | mips_fpu_type_auto = 1; | |
4613 | } | |
4614 | ||
c906108c | 4615 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4616 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4617 | the relevant processor still exists (it dates back to '94) and | |
4618 | secondly this is not the way to do this. The processor type should | |
4619 | be set by forcing an architecture change. */ | |
c906108c | 4620 | |
691c0433 AC |
4621 | void |
4622 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4623 | { |
691c0433 | 4624 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
a9614958 | 4625 | ULONGEST prid; |
c906108c | 4626 | |
594f7785 | 4627 | regcache_cooked_read_unsigned (get_current_regcache (), |
a9614958 | 4628 | MIPS_PRID_REGNUM, &prid); |
c906108c | 4629 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4630 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4631 | } |
4632 | ||
4633 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4634 | callable as an sfunc. */ | |
4635 | ||
4636 | static void | |
acdb74a0 AC |
4637 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4638 | struct cmd_list_element *c) | |
c906108c SS |
4639 | { |
4640 | reinit_frame_cache (); | |
4641 | } | |
4642 | ||
a89aa300 AC |
4643 | static int |
4644 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4645 | { |
e5ab0dce | 4646 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4647 | |
d31431ed AC |
4648 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4649 | disassembler needs to be able to locally determine the ISA, and | |
4650 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4651 | work. */ | |
ec4045ea AC |
4652 | if (mips_pc_is_mips16 (memaddr)) |
4653 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4654 | |
4655 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4656 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4657 | |
e5ab0dce | 4658 | /* Set the disassembler options. */ |
6d82d43b | 4659 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4660 | { |
4661 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4662 | register names from libopcodes. */ |
e5ab0dce AC |
4663 | if (tdep->mips_abi == MIPS_ABI_N32) |
4664 | info->disassembler_options = "gpr-names=n32"; | |
4665 | else | |
4666 | info->disassembler_options = "gpr-names=64"; | |
4667 | info->flavour = bfd_target_elf_flavour; | |
4668 | } | |
4669 | else | |
4670 | /* This string is not recognized explicitly by the disassembler, | |
4671 | but it tells the disassembler to not try to guess the ABI from | |
4672 | the bfd elf headers, such that, if the user overrides the ABI | |
4673 | of a program linked as NewABI, the disassembly will follow the | |
4674 | register naming conventions specified by the user. */ | |
4675 | info->disassembler_options = "gpr-names=32"; | |
4676 | ||
c906108c | 4677 | /* Call the appropriate disassembler based on the target endian-ness. */ |
4c6b5505 | 4678 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
4679 | return print_insn_big_mips (memaddr, info); |
4680 | else | |
4681 | return print_insn_little_mips (memaddr, info); | |
4682 | } | |
4683 | ||
3b3b875c UW |
4684 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4685 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4686 | It returns a pointer to a string of bytes that encode a breakpoint | |
4687 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4688 | necessary) to point to the actual memory location where the breakpoint | |
4689 | should be inserted. */ | |
c906108c | 4690 | |
47a35522 | 4691 | static const gdb_byte * |
6d82d43b | 4692 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4693 | { |
4c6b5505 | 4694 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 4695 | { |
0fe7e7c8 | 4696 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4697 | { |
47a35522 | 4698 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4699 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4700 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4701 | return mips16_big_breakpoint; |
4702 | } | |
4703 | else | |
4704 | { | |
aaab4dba AC |
4705 | /* The IDT board uses an unusual breakpoint value, and |
4706 | sometimes gets confused when it sees the usual MIPS | |
4707 | breakpoint instruction. */ | |
47a35522 MK |
4708 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4709 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4710 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4711 | |
c5aa993b | 4712 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4713 | |
4714 | if (strcmp (target_shortname, "mips") == 0) | |
4715 | return idt_big_breakpoint; | |
4716 | else if (strcmp (target_shortname, "ddb") == 0 | |
4717 | || strcmp (target_shortname, "pmon") == 0 | |
4718 | || strcmp (target_shortname, "lsi") == 0) | |
4719 | return pmon_big_breakpoint; | |
4720 | else | |
4721 | return big_breakpoint; | |
4722 | } | |
4723 | } | |
4724 | else | |
4725 | { | |
0fe7e7c8 | 4726 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4727 | { |
47a35522 | 4728 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4729 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4730 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4731 | return mips16_little_breakpoint; |
4732 | } | |
4733 | else | |
4734 | { | |
47a35522 MK |
4735 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4736 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4737 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4738 | |
c5aa993b | 4739 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4740 | |
4741 | if (strcmp (target_shortname, "mips") == 0) | |
4742 | return idt_little_breakpoint; | |
4743 | else if (strcmp (target_shortname, "ddb") == 0 | |
4744 | || strcmp (target_shortname, "pmon") == 0 | |
4745 | || strcmp (target_shortname, "lsi") == 0) | |
4746 | return pmon_little_breakpoint; | |
4747 | else | |
4748 | return little_breakpoint; | |
4749 | } | |
4750 | } | |
4751 | } | |
4752 | ||
4753 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4754 | PC, which is either the callee or the caller. There are several | |
4755 | cases which must be handled: | |
4756 | ||
4757 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4758 | target PC is in $31 ($ra). |
c906108c | 4759 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4760 | and the target PC is in $2. |
c906108c | 4761 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4762 | before the jal instruction, this is effectively a call stub |
4763 | and the the target PC is in $2. Otherwise this is effectively | |
4764 | a return stub and the target PC is in $18. | |
c906108c SS |
4765 | |
4766 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4767 | gory details. */ |
c906108c | 4768 | |
757a7cc6 | 4769 | static CORE_ADDR |
52f729a7 | 4770 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c SS |
4771 | { |
4772 | char *name; | |
4773 | CORE_ADDR start_addr; | |
4774 | ||
4775 | /* Find the starting address and name of the function containing the PC. */ | |
4776 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4777 | return 0; | |
4778 | ||
4779 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4780 | target PC is in $31 ($ra). */ | |
4781 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4782 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 4783 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
4784 | |
4785 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4786 | { | |
4787 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4788 | and the target PC is in $2. */ | |
4789 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 4790 | return get_frame_register_signed (frame, 2); |
c906108c SS |
4791 | |
4792 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4793 | before the jal instruction, this is effectively a call stub |
4794 | and the the target PC is in $2. Otherwise this is effectively | |
4795 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4796 | else if (name[19] == 's' || name[19] == 'd') |
4797 | { | |
4798 | if (pc == start_addr) | |
4799 | { | |
4800 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4801 | stub. Such a stub for a function bar might have a name |
4802 | like __fn_stub_bar, and might look like this: | |
4803 | mfc1 $4,$f13 | |
4804 | mfc1 $5,$f12 | |
4805 | mfc1 $6,$f15 | |
4806 | mfc1 $7,$f14 | |
4807 | la $1,bar (becomes a lui/addiu pair) | |
4808 | jr $1 | |
4809 | So scan down to the lui/addi and extract the target | |
4810 | address from those two instructions. */ | |
c906108c | 4811 | |
52f729a7 | 4812 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 4813 | ULONGEST inst; |
c906108c SS |
4814 | int i; |
4815 | ||
4816 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4817 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4818 | 0) | |
c906108c SS |
4819 | return target_pc; |
4820 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4821 | && strcmp (name, "etext") != 0 | |
4822 | && strcmp (name, "_etext") != 0) | |
4823 | return target_pc; | |
4824 | ||
4825 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4826 | The limit on the search is arbitrarily set to 20 |
4827 | instructions. FIXME. */ | |
95ac2dcf | 4828 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 4829 | { |
c5aa993b JM |
4830 | inst = mips_fetch_instruction (target_pc); |
4831 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4832 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4833 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4834 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4835 | } |
4836 | ||
4837 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4838 | return target_pc; | |
4839 | } | |
4840 | else | |
4841 | /* This is the 'return' part of a call stub. The return | |
4842 | address is in $r18. */ | |
52f729a7 | 4843 | return get_frame_register_signed (frame, 18); |
c906108c SS |
4844 | } |
4845 | } | |
c5aa993b | 4846 | return 0; /* not a stub */ |
c906108c SS |
4847 | } |
4848 | ||
a4b8ebc8 | 4849 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 4850 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4851 | |
4852 | static int | |
4853 | mips_stab_reg_to_regnum (int num) | |
4854 | { | |
a4b8ebc8 | 4855 | int regnum; |
2f38ef89 | 4856 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4857 | regnum = num; |
2f38ef89 | 4858 | else if (num >= 38 && num < 70) |
56cea623 | 4859 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4860 | else if (num == 70) |
56cea623 | 4861 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4862 | else if (num == 71) |
56cea623 | 4863 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4864 | else |
a4b8ebc8 AC |
4865 | /* This will hopefully (eventually) provoke a warning. Should |
4866 | we be calling complaint() here? */ | |
f57d151a UW |
4867 | return gdbarch_num_regs (current_gdbarch) |
4868 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4869 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
88c72b7d AC |
4870 | } |
4871 | ||
2f38ef89 | 4872 | |
a4b8ebc8 | 4873 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 4874 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4875 | |
4876 | static int | |
2f38ef89 | 4877 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4878 | { |
a4b8ebc8 | 4879 | int regnum; |
2f38ef89 | 4880 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4881 | regnum = num; |
2f38ef89 | 4882 | else if (num >= 32 && num < 64) |
56cea623 | 4883 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4884 | else if (num == 64) |
56cea623 | 4885 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4886 | else if (num == 65) |
56cea623 | 4887 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4888 | else |
a4b8ebc8 AC |
4889 | /* This will hopefully (eventually) provoke a warning. Should we |
4890 | be calling complaint() here? */ | |
f57d151a UW |
4891 | return gdbarch_num_regs (current_gdbarch) |
4892 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4893 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
a4b8ebc8 AC |
4894 | } |
4895 | ||
4896 | static int | |
4897 | mips_register_sim_regno (int regnum) | |
4898 | { | |
4899 | /* Only makes sense to supply raw registers. */ | |
f57d151a | 4900 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)); |
a4b8ebc8 AC |
4901 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
4902 | decide if it is valid. Should instead define a standard sim/gdb | |
4903 | register numbering scheme. */ | |
c9f4d572 UW |
4904 | if (gdbarch_register_name (current_gdbarch, |
4905 | gdbarch_num_regs | |
4906 | (current_gdbarch) + regnum) != NULL | |
4907 | && gdbarch_register_name (current_gdbarch, | |
4908 | gdbarch_num_regs | |
4909 | (current_gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
4910 | return regnum; |
4911 | else | |
6d82d43b | 4912 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4913 | } |
4914 | ||
2f38ef89 | 4915 | |
4844f454 CV |
4916 | /* Convert an integer into an address. Extracting the value signed |
4917 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
4918 | |
4919 | static CORE_ADDR | |
79dd2d24 | 4920 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 4921 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 4922 | { |
4844f454 | 4923 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
4924 | } |
4925 | ||
82e91389 DJ |
4926 | /* Dummy virtual frame pointer method. This is no more or less accurate |
4927 | than most other architectures; we just need to be explicit about it, | |
4928 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
4929 | an assertion failure. */ | |
4930 | ||
4931 | static void | |
4932 | mips_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset) | |
4933 | { | |
4934 | *reg = MIPS_SP_REGNUM; | |
4935 | *offset = 0; | |
4936 | } | |
4937 | ||
caaa3122 DJ |
4938 | static void |
4939 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4940 | { | |
4941 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4942 | const char *name = bfd_get_section_name (abfd, sect); | |
4943 | ||
4944 | if (*abip != MIPS_ABI_UNKNOWN) | |
4945 | return; | |
4946 | ||
4947 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4948 | return; | |
4949 | ||
4950 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4951 | *abip = MIPS_ABI_O32; | |
4952 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4953 | *abip = MIPS_ABI_N32; | |
62a49b2c | 4954 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 4955 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
4956 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4957 | *abip = MIPS_ABI_O64; | |
4958 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4959 | *abip = MIPS_ABI_EABI32; | |
4960 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4961 | *abip = MIPS_ABI_EABI64; | |
4962 | else | |
8a3fe4f8 | 4963 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
4964 | } |
4965 | ||
22e47e37 FF |
4966 | static void |
4967 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
4968 | { | |
4969 | int *lbp = (int *) obj; | |
4970 | const char *name = bfd_get_section_name (abfd, sect); | |
4971 | ||
4972 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
4973 | *lbp = 32; | |
4974 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
4975 | *lbp = 64; | |
4976 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
4977 | warning (_("unrecognized .gcc_compiled_longXX")); | |
4978 | } | |
4979 | ||
2e4ebe70 DJ |
4980 | static enum mips_abi |
4981 | global_mips_abi (void) | |
4982 | { | |
4983 | int i; | |
4984 | ||
4985 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4986 | if (mips_abi_strings[i] == mips_abi_string) | |
4987 | return (enum mips_abi) i; | |
4988 | ||
e2e0b3e5 | 4989 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
4990 | } |
4991 | ||
29709017 DJ |
4992 | static void |
4993 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
4994 | { | |
29709017 DJ |
4995 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
4996 | assume that's what we've got. */ | |
4eb0ad19 DJ |
4997 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
4998 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
4999 | |
5000 | /* If the size matches the full set of registers GDB traditionally | |
5001 | knows about, including floating point, for either 32-bit or | |
5002 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5003 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5004 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5005 | |
5006 | /* Otherwise we don't have a useful guess. */ | |
5007 | } | |
5008 | ||
f8b73d13 DJ |
5009 | static struct value * |
5010 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5011 | { | |
5012 | const int *reg_p = baton; | |
5013 | return value_of_register (*reg_p, frame); | |
5014 | } | |
5015 | ||
c2d11a7d | 5016 | static struct gdbarch * |
6d82d43b | 5017 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5018 | { |
c2d11a7d JM |
5019 | struct gdbarch *gdbarch; |
5020 | struct gdbarch_tdep *tdep; | |
5021 | int elf_flags; | |
2e4ebe70 | 5022 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5023 | int i, num_regs; |
8d5838b5 | 5024 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5025 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5026 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5027 | |
5028 | /* Check any target description for validity. */ | |
5029 | if (tdesc_has_registers (info.target_desc)) | |
5030 | { | |
5031 | static const char *const mips_gprs[] = { | |
5032 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5033 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5034 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5035 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5036 | }; | |
5037 | static const char *const mips_fprs[] = { | |
5038 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5039 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5040 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5041 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5042 | }; | |
5043 | ||
5044 | const struct tdesc_feature *feature; | |
5045 | int valid_p; | |
5046 | ||
5047 | feature = tdesc_find_feature (info.target_desc, | |
5048 | "org.gnu.gdb.mips.cpu"); | |
5049 | if (feature == NULL) | |
5050 | return NULL; | |
5051 | ||
5052 | tdesc_data = tdesc_data_alloc (); | |
5053 | ||
5054 | valid_p = 1; | |
5055 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5056 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5057 | mips_gprs[i]); | |
5058 | ||
5059 | ||
5060 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5061 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5062 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5063 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5064 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5065 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5066 | ||
5067 | if (!valid_p) | |
5068 | { | |
5069 | tdesc_data_cleanup (tdesc_data); | |
5070 | return NULL; | |
5071 | } | |
5072 | ||
5073 | feature = tdesc_find_feature (info.target_desc, | |
5074 | "org.gnu.gdb.mips.cp0"); | |
5075 | if (feature == NULL) | |
5076 | { | |
5077 | tdesc_data_cleanup (tdesc_data); | |
5078 | return NULL; | |
5079 | } | |
5080 | ||
5081 | valid_p = 1; | |
5082 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5083 | MIPS_EMBED_BADVADDR_REGNUM, | |
5084 | "badvaddr"); | |
5085 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5086 | MIPS_PS_REGNUM, "status"); | |
5087 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5088 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5089 | ||
5090 | if (!valid_p) | |
5091 | { | |
5092 | tdesc_data_cleanup (tdesc_data); | |
5093 | return NULL; | |
5094 | } | |
5095 | ||
5096 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5097 | backend is not prepared for that, though. */ | |
5098 | feature = tdesc_find_feature (info.target_desc, | |
5099 | "org.gnu.gdb.mips.fpu"); | |
5100 | if (feature == NULL) | |
5101 | { | |
5102 | tdesc_data_cleanup (tdesc_data); | |
5103 | return NULL; | |
5104 | } | |
5105 | ||
5106 | valid_p = 1; | |
5107 | for (i = 0; i < 32; i++) | |
5108 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5109 | i + MIPS_EMBED_FP0_REGNUM, | |
5110 | mips_fprs[i]); | |
5111 | ||
5112 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5113 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5114 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5115 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5116 | ||
5117 | if (!valid_p) | |
5118 | { | |
5119 | tdesc_data_cleanup (tdesc_data); | |
5120 | return NULL; | |
5121 | } | |
5122 | ||
5123 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5124 | when only 32-bit registers are provided. */ | |
5125 | } | |
c2d11a7d | 5126 | |
ec03c1ac AC |
5127 | /* First of all, extract the elf_flags, if available. */ |
5128 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5129 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5130 | else if (arches != NULL) |
5131 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5132 | else |
5133 | elf_flags = 0; | |
5134 | if (gdbarch_debug) | |
5135 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5136 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5137 | |
102182a9 | 5138 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5139 | switch ((elf_flags & EF_MIPS_ABI)) |
5140 | { | |
5141 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5142 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5143 | break; |
5144 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5145 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5146 | break; |
5147 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5148 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5149 | break; |
5150 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5151 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5152 | break; |
5153 | default: | |
acdb74a0 | 5154 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5155 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5156 | else |
ec03c1ac | 5157 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5158 | break; |
5159 | } | |
acdb74a0 | 5160 | |
caaa3122 | 5161 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5162 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5163 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5164 | |
dc305454 | 5165 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5166 | MIPS architecture (if there is one). */ |
5167 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5168 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5169 | |
32a6503c | 5170 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5171 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5172 | && info.bfd_arch_info != NULL |
5173 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5174 | { | |
5175 | switch (info.bfd_arch_info->mach) | |
5176 | { | |
5177 | case bfd_mach_mips3900: | |
ec03c1ac | 5178 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5179 | break; |
5180 | case bfd_mach_mips4100: | |
5181 | case bfd_mach_mips5000: | |
ec03c1ac | 5182 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5183 | break; |
1d06468c EZ |
5184 | case bfd_mach_mips8000: |
5185 | case bfd_mach_mips10000: | |
32a6503c KB |
5186 | /* On Irix, ELF64 executables use the N64 ABI. The |
5187 | pseudo-sections which describe the ABI aren't present | |
5188 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5189 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5190 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5191 | found_abi = MIPS_ABI_N64; |
28d169de | 5192 | else |
ec03c1ac | 5193 | found_abi = MIPS_ABI_N32; |
1d06468c | 5194 | break; |
bf64bfd6 AC |
5195 | } |
5196 | } | |
2e4ebe70 | 5197 | |
26c53e50 DJ |
5198 | /* Default 64-bit objects to N64 instead of O32. */ |
5199 | if (found_abi == MIPS_ABI_UNKNOWN | |
5200 | && info.abfd != NULL | |
5201 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5202 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5203 | found_abi = MIPS_ABI_N64; | |
5204 | ||
ec03c1ac AC |
5205 | if (gdbarch_debug) |
5206 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5207 | found_abi); | |
5208 | ||
5209 | /* What has the user specified from the command line? */ | |
5210 | wanted_abi = global_mips_abi (); | |
5211 | if (gdbarch_debug) | |
5212 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5213 | wanted_abi); | |
2e4ebe70 DJ |
5214 | |
5215 | /* Now that we have found what the ABI for this binary would be, | |
5216 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5217 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5218 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5219 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5220 | mips_abi = found_abi; | |
5221 | else | |
5222 | mips_abi = MIPS_ABI_O32; | |
5223 | if (gdbarch_debug) | |
5224 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5225 | mips_abi); | |
2e4ebe70 | 5226 | |
ec03c1ac | 5227 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5228 | if (gdbarch_debug) |
ec03c1ac AC |
5229 | fprintf_unfiltered (gdb_stdlog, |
5230 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5231 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5232 | |
8d5838b5 | 5233 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5234 | #ifdef HAVE_ELF |
5235 | if (info.abfd | |
5236 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5237 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5238 | Tag_GNU_MIPS_ABI_FP); | |
5239 | #endif /* HAVE_ELF */ | |
5240 | ||
8d5838b5 AC |
5241 | if (!mips_fpu_type_auto) |
5242 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5243 | else if (elf_fpu_type != 0) |
5244 | { | |
5245 | switch (elf_fpu_type) | |
5246 | { | |
5247 | case 1: | |
5248 | fpu_type = MIPS_FPU_DOUBLE; | |
5249 | break; | |
5250 | case 2: | |
5251 | fpu_type = MIPS_FPU_SINGLE; | |
5252 | break; | |
5253 | case 3: | |
5254 | default: | |
5255 | /* Soft float or unknown. */ | |
5256 | fpu_type = MIPS_FPU_NONE; | |
5257 | break; | |
5258 | } | |
5259 | } | |
8d5838b5 AC |
5260 | else if (info.bfd_arch_info != NULL |
5261 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5262 | switch (info.bfd_arch_info->mach) | |
5263 | { | |
5264 | case bfd_mach_mips3900: | |
5265 | case bfd_mach_mips4100: | |
5266 | case bfd_mach_mips4111: | |
a9d61c86 | 5267 | case bfd_mach_mips4120: |
8d5838b5 AC |
5268 | fpu_type = MIPS_FPU_NONE; |
5269 | break; | |
5270 | case bfd_mach_mips4650: | |
5271 | fpu_type = MIPS_FPU_SINGLE; | |
5272 | break; | |
5273 | default: | |
5274 | fpu_type = MIPS_FPU_DOUBLE; | |
5275 | break; | |
5276 | } | |
5277 | else if (arches != NULL) | |
5278 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5279 | else | |
5280 | fpu_type = MIPS_FPU_DOUBLE; | |
5281 | if (gdbarch_debug) | |
5282 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5283 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5284 | |
29709017 DJ |
5285 | /* Check for blatant incompatibilities. */ |
5286 | ||
5287 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5288 | ABI. */ | |
5289 | if (info.target_desc | |
5290 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5291 | && mips_abi != MIPS_ABI_EABI32 | |
5292 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5293 | { |
5294 | if (tdesc_data != NULL) | |
5295 | tdesc_data_cleanup (tdesc_data); | |
5296 | return NULL; | |
5297 | } | |
29709017 | 5298 | |
c2d11a7d JM |
5299 | /* try to find a pre-existing architecture */ |
5300 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5301 | arches != NULL; | |
5302 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5303 | { | |
5304 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5305 | using. */ |
9103eae0 | 5306 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5307 | continue; |
9103eae0 | 5308 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5309 | continue; |
719ec221 AC |
5310 | /* Need to be pedantic about which register virtual size is |
5311 | used. */ | |
5312 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5313 | != mips64_transfers_32bit_regs_p) | |
5314 | continue; | |
8d5838b5 AC |
5315 | /* Be pedantic about which FPU is selected. */ |
5316 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5317 | continue; | |
f8b73d13 DJ |
5318 | |
5319 | if (tdesc_data != NULL) | |
5320 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5321 | return arches->gdbarch; |
c2d11a7d JM |
5322 | } |
5323 | ||
102182a9 | 5324 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5325 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5326 | gdbarch = gdbarch_alloc (&info, tdep); | |
5327 | tdep->elf_flags = elf_flags; | |
719ec221 | 5328 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5329 | tdep->found_abi = found_abi; |
5330 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5331 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5332 | tdep->register_size_valid_p = 0; |
5333 | tdep->register_size = 0; | |
5334 | ||
5335 | if (info.target_desc) | |
5336 | { | |
5337 | /* Some useful properties can be inferred from the target. */ | |
5338 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5339 | { | |
5340 | tdep->register_size_valid_p = 1; | |
5341 | tdep->register_size = 4; | |
5342 | } | |
5343 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5344 | { | |
5345 | tdep->register_size_valid_p = 1; | |
5346 | tdep->register_size = 8; | |
5347 | } | |
5348 | } | |
c2d11a7d | 5349 | |
102182a9 | 5350 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5351 | set_gdbarch_short_bit (gdbarch, 16); |
5352 | set_gdbarch_int_bit (gdbarch, 32); | |
5353 | set_gdbarch_float_bit (gdbarch, 32); | |
5354 | set_gdbarch_double_bit (gdbarch, 64); | |
5355 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5356 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5357 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5358 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5359 | |
6d82d43b | 5360 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5361 | mips_elf_make_msymbol_special); |
5362 | ||
16e109ca | 5363 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5364 | { |
16e109ca | 5365 | const char **reg_names; |
56cea623 AC |
5366 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5367 | struct mips_regnum); | |
f8b73d13 DJ |
5368 | if (tdesc_has_registers (info.target_desc)) |
5369 | { | |
5370 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5371 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5372 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5373 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5374 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5375 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5376 | regnum->fp_control_status = 70; | |
5377 | regnum->fp_implementation_revision = 71; | |
5378 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5379 | reg_names = NULL; | |
5380 | } | |
5381 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5382 | { |
5383 | regnum->fp0 = 32; | |
5384 | regnum->pc = 64; | |
5385 | regnum->cause = 65; | |
5386 | regnum->badvaddr = 66; | |
5387 | regnum->hi = 67; | |
5388 | regnum->lo = 68; | |
5389 | regnum->fp_control_status = 69; | |
5390 | regnum->fp_implementation_revision = 70; | |
5391 | num_regs = 71; | |
16e109ca | 5392 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5393 | } |
5394 | else | |
5395 | { | |
5396 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5397 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5398 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5399 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5400 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5401 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5402 | regnum->fp_control_status = 70; | |
5403 | regnum->fp_implementation_revision = 71; | |
5404 | num_regs = 90; | |
16e109ca AC |
5405 | if (info.bfd_arch_info != NULL |
5406 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5407 | reg_names = mips_tx39_reg_names; | |
5408 | else | |
5409 | reg_names = mips_generic_reg_names; | |
56cea623 | 5410 | } |
3e8c568d | 5411 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
56cea623 | 5412 | replaced by read_pc? */ |
f10683bb MH |
5413 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5414 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5415 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5416 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5417 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5418 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5419 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5420 | tdep->mips_processor_reg_names = reg_names; |
5421 | tdep->regnum = regnum; | |
56cea623 | 5422 | } |
fe29b929 | 5423 | |
0dadbba0 | 5424 | switch (mips_abi) |
c2d11a7d | 5425 | { |
0dadbba0 | 5426 | case MIPS_ABI_O32: |
25ab4790 | 5427 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5428 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5429 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5430 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5431 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5432 | set_gdbarch_long_bit (gdbarch, 32); |
5433 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5434 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5435 | break; | |
0dadbba0 | 5436 | case MIPS_ABI_O64: |
25ab4790 | 5437 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5438 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5439 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5440 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5441 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5442 | set_gdbarch_long_bit (gdbarch, 32); |
5443 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5444 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5445 | break; | |
0dadbba0 | 5446 | case MIPS_ABI_EABI32: |
25ab4790 | 5447 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5448 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5449 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5450 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5451 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5452 | set_gdbarch_long_bit (gdbarch, 32); |
5453 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5454 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5455 | break; | |
0dadbba0 | 5456 | case MIPS_ABI_EABI64: |
25ab4790 | 5457 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5458 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5459 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5460 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5461 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5462 | set_gdbarch_long_bit (gdbarch, 64); |
5463 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5464 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5465 | break; | |
0dadbba0 | 5466 | case MIPS_ABI_N32: |
25ab4790 | 5467 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5468 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5469 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5470 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5471 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5472 | set_gdbarch_long_bit (gdbarch, 32); |
5473 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5474 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5475 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5476 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
28d169de KB |
5477 | break; |
5478 | case MIPS_ABI_N64: | |
25ab4790 | 5479 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5480 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5481 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5482 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5483 | tdep->default_mask_address_p = 0; |
5484 | set_gdbarch_long_bit (gdbarch, 64); | |
5485 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5486 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5487 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5488 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
0dadbba0 | 5489 | break; |
c2d11a7d | 5490 | default: |
e2e0b3e5 | 5491 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5492 | } |
5493 | ||
22e47e37 FF |
5494 | /* GCC creates a pseudo-section whose name specifies the size of |
5495 | longs, since -mlong32 or -mlong64 may be used independent of | |
5496 | other options. How those options affect pointer sizes is ABI and | |
5497 | architecture dependent, so use them to override the default sizes | |
5498 | set by the ABI. This table shows the relationship between ABI, | |
5499 | -mlongXX, and size of pointers: | |
5500 | ||
5501 | ABI -mlongXX ptr bits | |
5502 | --- -------- -------- | |
5503 | o32 32 32 | |
5504 | o32 64 32 | |
5505 | n32 32 32 | |
5506 | n32 64 64 | |
5507 | o64 32 32 | |
5508 | o64 64 64 | |
5509 | n64 32 32 | |
5510 | n64 64 64 | |
5511 | eabi32 32 32 | |
5512 | eabi32 64 32 | |
5513 | eabi64 32 32 | |
5514 | eabi64 64 64 | |
5515 | ||
5516 | Note that for o32 and eabi32, pointers are always 32 bits | |
5517 | regardless of any -mlongXX option. For all others, pointers and | |
5518 | longs are the same, as set by -mlongXX or set by defaults. | |
5519 | */ | |
5520 | ||
5521 | if (info.abfd != NULL) | |
5522 | { | |
5523 | int long_bit = 0; | |
5524 | ||
5525 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5526 | if (long_bit) | |
5527 | { | |
5528 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5529 | switch (mips_abi) | |
5530 | { | |
5531 | case MIPS_ABI_O32: | |
5532 | case MIPS_ABI_EABI32: | |
5533 | break; | |
5534 | case MIPS_ABI_N32: | |
5535 | case MIPS_ABI_O64: | |
5536 | case MIPS_ABI_N64: | |
5537 | case MIPS_ABI_EABI64: | |
5538 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5539 | break; | |
5540 | default: | |
5541 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5542 | } | |
5543 | } | |
5544 | } | |
5545 | ||
a5ea2558 AC |
5546 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5547 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5548 | comment: | |
5549 | ||
5550 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5551 | flag in object files because to do so would make it impossible to | |
102182a9 | 5552 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5553 | unnecessarily restrictive. |
361d1df0 | 5554 | |
a5ea2558 AC |
5555 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5556 | but to set this flag before gcc is built with such multilibs will | |
5557 | break too many systems.'' | |
5558 | ||
5559 | But even more unhelpfully, the default linker output target for | |
5560 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5561 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5562 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5563 | this flag to detect 32-bit mode would do the wrong thing given |
5564 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5565 | as 32-bit programs by default. */ |
a5ea2558 | 5566 | |
6c997a34 | 5567 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5568 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5569 | |
102182a9 MS |
5570 | /* Add/remove bits from an address. The MIPS needs be careful to |
5571 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5572 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5573 | ||
58dfe9ff AC |
5574 | /* Unwind the frame. */ |
5575 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5576 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
edfae063 | 5577 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5578 | |
102182a9 | 5579 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5580 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5581 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5582 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5583 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5584 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5585 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5586 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5587 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5588 | |
c2d11a7d JM |
5589 | /* MIPS version of CALL_DUMMY */ |
5590 | ||
9710e734 AC |
5591 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5592 | replaced by a command, and all targets will default to on stack | |
5593 | (regardless of the stack's execute status). */ | |
5594 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5595 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5596 | |
87783b8b AC |
5597 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5598 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5599 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5600 | ||
f7b9e9fc AC |
5601 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5602 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5603 | |
5604 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5605 | |
97ab0fdd MR |
5606 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
5607 | ||
fc0c74b1 AC |
5608 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5609 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5610 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5611 | |
a4b8ebc8 | 5612 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5613 | |
e11c53d2 | 5614 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5615 | |
e5ab0dce AC |
5616 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5617 | ||
3a3bc038 AC |
5618 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5619 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5620 | need to all be folded into the target vector. Since they are | |
5621 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5622 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5623 | is sitting on? */ | |
5624 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5625 | ||
e7d6a6d2 | 5626 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5627 | |
3352ef37 AC |
5628 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5629 | ||
0d5de010 DJ |
5630 | /* Virtual tables. */ |
5631 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
5632 | ||
29709017 DJ |
5633 | mips_register_g_packet_guesses (gdbarch); |
5634 | ||
6de918a6 | 5635 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 5636 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 5637 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 5638 | |
5792a79b | 5639 | /* Unwind the frame. */ |
2bd0c3d7 | 5640 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eec63939 | 5641 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5642 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5643 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
2bd0c3d7 | 5644 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 5645 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5646 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5647 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5648 | |
f8b73d13 DJ |
5649 | if (tdesc_data) |
5650 | { | |
5651 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
5652 | tdesc_use_registers (gdbarch, tdesc_data); | |
5653 | ||
5654 | /* Override the normal target description methods to handle our | |
5655 | dual real and pseudo registers. */ | |
5656 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
5657 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
5658 | ||
5659 | num_regs = gdbarch_num_regs (gdbarch); | |
5660 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5661 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
5662 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
5663 | } | |
5664 | ||
5665 | /* Add ABI-specific aliases for the registers. */ | |
5666 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5667 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
5668 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
5669 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
5670 | else | |
5671 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
5672 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
5673 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
5674 | ||
5675 | /* Add some other standard aliases. */ | |
5676 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
5677 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
5678 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
5679 | ||
4b9b3959 AC |
5680 | return gdbarch; |
5681 | } | |
5682 | ||
2e4ebe70 | 5683 | static void |
6d82d43b | 5684 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5685 | { |
5686 | struct gdbarch_info info; | |
5687 | ||
5688 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5689 | mips_gdbarch_init will take care of the rest. */ | |
5690 | gdbarch_info_init (&info); | |
5691 | gdbarch_update_p (info); | |
5692 | } | |
5693 | ||
ad188201 KB |
5694 | /* Print out which MIPS ABI is in use. */ |
5695 | ||
5696 | static void | |
1f8ca57c JB |
5697 | show_mips_abi (struct ui_file *file, |
5698 | int from_tty, | |
5699 | struct cmd_list_element *ignored_cmd, | |
5700 | const char *ignored_value) | |
ad188201 KB |
5701 | { |
5702 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
1f8ca57c JB |
5703 | fprintf_filtered |
5704 | (file, | |
5705 | "The MIPS ABI is unknown because the current architecture " | |
5706 | "is not MIPS.\n"); | |
ad188201 KB |
5707 | else |
5708 | { | |
5709 | enum mips_abi global_abi = global_mips_abi (); | |
5710 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5711 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5712 | ||
5713 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5714 | fprintf_filtered |
5715 | (file, | |
5716 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5717 | actual_abi_str); |
ad188201 | 5718 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5719 | fprintf_filtered |
5720 | (file, | |
5721 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5722 | actual_abi_str); |
ad188201 KB |
5723 | else |
5724 | { | |
5725 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
5726 | fprintf_filtered |
5727 | (file, | |
5728 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 5729 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
5730 | } |
5731 | } | |
5732 | } | |
5733 | ||
4b9b3959 | 5734 | static void |
72a155b4 | 5735 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 5736 | { |
72a155b4 | 5737 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 5738 | if (tdep != NULL) |
c2d11a7d | 5739 | { |
acdb74a0 AC |
5740 | int ef_mips_arch; |
5741 | int ef_mips_32bitmode; | |
f49e4e6d | 5742 | /* Determine the ISA. */ |
acdb74a0 AC |
5743 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
5744 | { | |
5745 | case E_MIPS_ARCH_1: | |
5746 | ef_mips_arch = 1; | |
5747 | break; | |
5748 | case E_MIPS_ARCH_2: | |
5749 | ef_mips_arch = 2; | |
5750 | break; | |
5751 | case E_MIPS_ARCH_3: | |
5752 | ef_mips_arch = 3; | |
5753 | break; | |
5754 | case E_MIPS_ARCH_4: | |
93d56215 | 5755 | ef_mips_arch = 4; |
acdb74a0 AC |
5756 | break; |
5757 | default: | |
93d56215 | 5758 | ef_mips_arch = 0; |
acdb74a0 AC |
5759 | break; |
5760 | } | |
f49e4e6d | 5761 | /* Determine the size of a pointer. */ |
acdb74a0 | 5762 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
5763 | fprintf_unfiltered (file, |
5764 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5765 | tdep->elf_flags); |
4b9b3959 | 5766 | fprintf_unfiltered (file, |
acdb74a0 AC |
5767 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5768 | ef_mips_32bitmode); | |
5769 | fprintf_unfiltered (file, | |
5770 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5771 | ef_mips_arch); | |
5772 | fprintf_unfiltered (file, | |
5773 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5774 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5775 | fprintf_unfiltered (file, |
5776 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5777 | mips_mask_address_p (tdep), |
4014092b | 5778 | tdep->default_mask_address_p); |
c2d11a7d | 5779 | } |
4b9b3959 AC |
5780 | fprintf_unfiltered (file, |
5781 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5782 | MIPS_DEFAULT_FPU_TYPE, | |
5783 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5784 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5785 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5786 | : "???")); | |
6d82d43b | 5787 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5788 | fprintf_unfiltered (file, |
5789 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5790 | MIPS_FPU_TYPE, | |
5791 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5792 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5793 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5794 | : "???")); | |
c2d11a7d JM |
5795 | } |
5796 | ||
6d82d43b | 5797 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5798 | |
c906108c | 5799 | void |
acdb74a0 | 5800 | _initialize_mips_tdep (void) |
c906108c SS |
5801 | { |
5802 | static struct cmd_list_element *mipsfpulist = NULL; | |
5803 | struct cmd_list_element *c; | |
5804 | ||
6d82d43b | 5805 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5806 | if (MIPS_ABI_LAST + 1 |
5807 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 5808 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 5809 | |
4b9b3959 | 5810 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5811 | |
8d5f9dcb DJ |
5812 | mips_pdr_data = register_objfile_data (); |
5813 | ||
4eb0ad19 DJ |
5814 | /* Create feature sets with the appropriate properties. The values |
5815 | are not important. */ | |
5816 | mips_tdesc_gp32 = allocate_target_description (); | |
5817 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
5818 | ||
5819 | mips_tdesc_gp64 = allocate_target_description (); | |
5820 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
5821 | ||
a5ea2558 AC |
5822 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5823 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 5824 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5825 | &setmipscmdlist, "set mips ", 0, &setlist); |
5826 | ||
5827 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 5828 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5829 | &showmipscmdlist, "show mips ", 0, &showlist); |
5830 | ||
2e4ebe70 | 5831 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
5832 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
5833 | &mips_abi_string, _("\ | |
5834 | Set the MIPS ABI used by this program."), _("\ | |
5835 | Show the MIPS ABI used by this program."), _("\ | |
5836 | This option can be set to one of:\n\ | |
5837 | auto - the default ABI associated with the current binary\n\ | |
5838 | o32\n\ | |
5839 | o64\n\ | |
5840 | n32\n\ | |
5841 | n64\n\ | |
5842 | eabi32\n\ | |
5843 | eabi64"), | |
5844 | mips_abi_update, | |
5845 | show_mips_abi, | |
5846 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 5847 | |
c906108c SS |
5848 | /* Let the user turn off floating point and set the fence post for |
5849 | heuristic_proc_start. */ | |
5850 | ||
5851 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 5852 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
5853 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
5854 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 5855 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
5856 | &mipsfpulist); |
5857 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 5858 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
5859 | &mipsfpulist); |
5860 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5861 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5862 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5863 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 5864 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
5865 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5866 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5867 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5868 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 5869 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
5870 | &mipsfpulist); |
5871 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 5872 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
5873 | &showlist); |
5874 | ||
c906108c SS |
5875 | /* We really would like to have both "0" and "unlimited" work, but |
5876 | command.c doesn't deal with that. So make it a var_zinteger | |
5877 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 5878 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
5879 | &heuristic_fence_post, _("\ |
5880 | Set the distance searched for the start of a function."), _("\ | |
5881 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
5882 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5883 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 5884 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 5885 | reinit_frame_cache_sfunc, |
7915a72c | 5886 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 5887 | &setlist, &showlist); |
c906108c SS |
5888 | |
5889 | /* Allow the user to control whether the upper bits of 64-bit | |
5890 | addresses should be zeroed. */ | |
7915a72c AC |
5891 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
5892 | &mask_address_var, _("\ | |
5893 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
5894 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 5895 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 5896 | allow GDB to determine the correct value."), |
08546159 AC |
5897 | NULL, show_mask_address, |
5898 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5899 | |
5900 | /* Allow the user to control the size of 32 bit registers within the | |
5901 | raw remote packet. */ | |
b3f42336 | 5902 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
5903 | &mips64_transfers_32bit_regs_p, _("\ |
5904 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5905 | _("\ | |
5906 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5907 | _("\ | |
719ec221 AC |
5908 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5909 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 5910 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 5911 | set_mips64_transfers_32bit_regs, |
7915a72c | 5912 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 5913 | &setlist, &showlist); |
9ace0497 AC |
5914 | |
5915 | /* Debug this files internals. */ | |
6bcadd06 | 5916 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
5917 | &mips_debug, _("\ |
5918 | Set mips debugging."), _("\ | |
5919 | Show mips debugging."), _("\ | |
5920 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 5921 | NULL, |
7915a72c | 5922 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 5923 | &setdebuglist, &showdebuglist); |
c906108c | 5924 | } |