Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
53a5351d | 2 | Copyright 1988-1999, Free Software Foundation, Inc. |
c906108c SS |
3 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
4 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
5 | ||
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "gdb_string.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "value.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "language.h" | |
31 | #include "gdbcore.h" | |
32 | #include "symfile.h" | |
33 | #include "objfiles.h" | |
34 | #include "gdbtypes.h" | |
35 | #include "target.h" | |
28d069e6 | 36 | #include "arch-utils.h" |
c906108c SS |
37 | |
38 | #include "opcode/mips.h" | |
c2d11a7d JM |
39 | #include "elf/mips.h" |
40 | #include "elf-bfd.h" | |
41 | ||
c906108c | 42 | |
0dadbba0 AC |
43 | /* All the possible MIPS ABIs. */ |
44 | ||
45 | enum mips_abi | |
46 | { | |
47 | MIPS_ABI_UNKNOWN, | |
48 | MIPS_ABI_N32, | |
49 | MIPS_ABI_O32, | |
50 | MIPS_ABI_O64, | |
51 | MIPS_ABI_EABI32, | |
52 | MIPS_ABI_EABI64 | |
53 | }; | |
54 | ||
cce74817 | 55 | struct frame_extra_info |
c5aa993b JM |
56 | { |
57 | mips_extra_func_info_t proc_desc; | |
58 | int num_args; | |
59 | }; | |
cce74817 | 60 | |
d929b26f AC |
61 | /* Various MIPS ISA options (related to stack analysis) can be |
62 | overridden dynamically. Establish an enum/array for managing | |
63 | them. */ | |
64 | ||
65 | static char size_auto[] = "auto"; | |
66 | static char size_32[] = "32"; | |
67 | static char size_64[] = "64"; | |
68 | ||
69 | static char *size_enums[] = { | |
70 | size_auto, | |
71 | size_32, | |
72 | size_64, | |
a5ea2558 AC |
73 | 0 |
74 | }; | |
75 | ||
7a292a7a SS |
76 | /* Some MIPS boards don't support floating point while others only |
77 | support single-precision floating-point operations. See also | |
78 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
79 | |
80 | enum mips_fpu_type | |
c5aa993b JM |
81 | { |
82 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
83 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
84 | MIPS_FPU_NONE /* No floating point. */ | |
85 | }; | |
c906108c SS |
86 | |
87 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
88 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
89 | #endif | |
90 | static int mips_fpu_type_auto = 1; | |
91 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
92 | #define MIPS_FPU_TYPE mips_fpu_type | |
93 | ||
c906108c | 94 | /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */ |
7a292a7a | 95 | #ifndef FP_REGISTER_DOUBLE |
c906108c | 96 | #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8) |
7a292a7a SS |
97 | #endif |
98 | ||
99 | ||
c2d11a7d JM |
100 | /* MIPS specific per-architecture information */ |
101 | struct gdbarch_tdep | |
102 | { | |
103 | /* from the elf header */ | |
104 | int elf_flags; | |
105 | /* mips options */ | |
0dadbba0 | 106 | enum mips_abi mips_abi; |
c2d11a7d JM |
107 | enum mips_fpu_type mips_fpu_type; |
108 | int mips_last_arg_regnum; | |
109 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 110 | int mips_default_saved_regsize; |
c2d11a7d | 111 | int mips_fp_register_double; |
d929b26f AC |
112 | int mips_regs_have_home_p; |
113 | int mips_default_stack_argsize; | |
c2d11a7d JM |
114 | }; |
115 | ||
116 | #if GDB_MULTI_ARCH | |
117 | #undef MIPS_EABI | |
0dadbba0 | 118 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 119 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d JM |
120 | #endif |
121 | ||
122 | #if GDB_MULTI_ARCH | |
123 | #undef MIPS_LAST_FP_ARG_REGNUM | |
124 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) | |
125 | #endif | |
126 | ||
127 | #if GDB_MULTI_ARCH | |
128 | #undef MIPS_LAST_ARG_REGNUM | |
129 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) | |
130 | #endif | |
131 | ||
132 | #if GDB_MULTI_ARCH | |
133 | #undef MIPS_FPU_TYPE | |
134 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) | |
135 | #endif | |
136 | ||
d929b26f AC |
137 | /* Return the currently configured (or set) saved register size. */ |
138 | ||
c2d11a7d | 139 | #if GDB_MULTI_ARCH |
a5ea2558 AC |
140 | #undef MIPS_DEFAULT_SAVED_REGSIZE |
141 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) | |
d929b26f AC |
142 | #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE) |
143 | #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE | |
c2d11a7d JM |
144 | #endif |
145 | ||
d929b26f AC |
146 | static char *mips_saved_regsize_string = size_auto; |
147 | ||
148 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
149 | ||
150 | static unsigned int | |
151 | mips_saved_regsize () | |
152 | { | |
153 | if (mips_saved_regsize_string == size_auto) | |
154 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
155 | else if (mips_saved_regsize_string == size_64) | |
156 | return 8; | |
157 | else /* if (mips_saved_regsize_string == size_32) */ | |
158 | return 4; | |
159 | } | |
160 | ||
c2d11a7d JM |
161 | /* Indicate that the ABI makes use of double-precision registers |
162 | provided by the FPU (rather than combining pairs of registers to | |
163 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
164 | determine if the ABI is using double-precision registers. See also | |
165 | MIPS_FPU_TYPE. */ | |
166 | #if GDB_MULTI_ARCH | |
167 | #undef FP_REGISTER_DOUBLE | |
168 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) | |
169 | #endif | |
170 | ||
d929b26f AC |
171 | /* Does the caller allocate a ``home'' for each register used in the |
172 | function call? The N32 ABI and MIPS_EABI do not, the others do. */ | |
173 | ||
174 | #if GDB_MULTI_ARCH | |
175 | #undef MIPS_REGS_HAVE_HOME_P | |
176 | #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p) | |
177 | #elif !defined (MIPS_REGS_HAVE_HOME_P) | |
178 | #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI) | |
179 | #endif | |
180 | ||
181 | /* The amount of space reserved on the stack for registers. This is | |
182 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
183 | data allocated after the registers have run out. */ | |
184 | ||
185 | #if GDB_MULTI_ARCH | |
186 | #undef MIPS_DEFAULT_STACK_ARGSIZE | |
0dadbba0 | 187 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
188 | #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE) |
189 | #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE) | |
190 | #endif | |
191 | ||
192 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
193 | ||
194 | static char *mips_stack_argsize_string = size_auto; | |
195 | ||
196 | static unsigned int | |
197 | mips_stack_argsize (void) | |
198 | { | |
199 | if (mips_stack_argsize_string == size_auto) | |
200 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
201 | else if (mips_stack_argsize_string == size_64) | |
202 | return 8; | |
203 | else /* if (mips_stack_argsize_string == size_32) */ | |
204 | return 4; | |
205 | } | |
206 | ||
207 | ||
c2d11a7d | 208 | |
7a292a7a | 209 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c SS |
210 | |
211 | #if 0 | |
a14ed312 | 212 | static int mips_in_lenient_prologue (CORE_ADDR, CORE_ADDR); |
c906108c SS |
213 | #endif |
214 | ||
a14ed312 | 215 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 216 | |
a14ed312 | 217 | static void mips_print_register (int, int); |
c906108c SS |
218 | |
219 | static mips_extra_func_info_t | |
a14ed312 | 220 | heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *); |
c906108c | 221 | |
a14ed312 | 222 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 223 | |
a14ed312 | 224 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 225 | |
a14ed312 | 226 | int mips_set_processor_type (char *); |
c906108c | 227 | |
a14ed312 | 228 | static void mips_show_processor_type_command (char *, int); |
c906108c | 229 | |
a14ed312 | 230 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c SS |
231 | |
232 | static mips_extra_func_info_t | |
a14ed312 | 233 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame); |
c906108c | 234 | |
a14ed312 KB |
235 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
236 | mips_extra_func_info_t proc_desc); | |
c906108c SS |
237 | |
238 | /* This value is the model of MIPS in use. It is derived from the value | |
239 | of the PrID register. */ | |
240 | ||
241 | char *mips_processor_type; | |
242 | ||
243 | char *tmp_mips_processor_type; | |
244 | ||
245 | /* A set of original names, to be used when restoring back to generic | |
246 | registers from a specific set. */ | |
247 | ||
cce74817 JM |
248 | char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
249 | char **mips_processor_reg_names = mips_generic_reg_names; | |
250 | ||
a5ea2558 AC |
251 | /* The list of available "set mips " and "show mips " commands */ |
252 | static struct cmd_list_element *setmipscmdlist = NULL; | |
253 | static struct cmd_list_element *showmipscmdlist = NULL; | |
254 | ||
cce74817 JM |
255 | char * |
256 | mips_register_name (i) | |
257 | int i; | |
258 | { | |
259 | return mips_processor_reg_names[i]; | |
260 | } | |
9846de1b | 261 | /* *INDENT-OFF* */ |
c906108c SS |
262 | /* Names of IDT R3041 registers. */ |
263 | ||
264 | char *mips_r3041_reg_names[] = { | |
265 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
266 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
267 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
268 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
269 | "sr", "lo", "hi", "bad", "cause","pc", | |
270 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
271 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
272 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
273 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
274 | "fsr", "fir", "fp", "", | |
275 | "", "", "bus", "ccfg", "", "", "", "", | |
276 | "", "", "port", "cmp", "", "", "epc", "prid", | |
277 | }; | |
278 | ||
279 | /* Names of IDT R3051 registers. */ | |
280 | ||
281 | char *mips_r3051_reg_names[] = { | |
282 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
283 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
284 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
285 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
286 | "sr", "lo", "hi", "bad", "cause","pc", | |
287 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
288 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
289 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
290 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
291 | "fsr", "fir", "fp", "", | |
292 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
293 | "", "", "ehi", "", "", "", "epc", "prid", | |
294 | }; | |
295 | ||
296 | /* Names of IDT R3081 registers. */ | |
297 | ||
298 | char *mips_r3081_reg_names[] = { | |
299 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
300 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
301 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
302 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
303 | "sr", "lo", "hi", "bad", "cause","pc", | |
304 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
305 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
306 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
307 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
308 | "fsr", "fir", "fp", "", | |
309 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
310 | "", "", "ehi", "", "", "", "epc", "prid", | |
311 | }; | |
312 | ||
313 | /* Names of LSI 33k registers. */ | |
314 | ||
315 | char *mips_lsi33k_reg_names[] = { | |
316 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
317 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
318 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
319 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
320 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
321 | "dcic", "bpc", "bda", "", "", "", "", "", | |
322 | "", "", "", "", "", "", "", "", | |
323 | "", "", "", "", "", "", "", "", | |
324 | "", "", "", "", "", "", "", "", | |
325 | "", "", "", "", | |
326 | "", "", "", "", "", "", "", "", | |
327 | "", "", "", "", "", "", "", "", | |
328 | }; | |
329 | ||
330 | struct { | |
331 | char *name; | |
332 | char **regnames; | |
333 | } mips_processor_type_table[] = { | |
334 | { "generic", mips_generic_reg_names }, | |
335 | { "r3041", mips_r3041_reg_names }, | |
336 | { "r3051", mips_r3051_reg_names }, | |
337 | { "r3071", mips_r3081_reg_names }, | |
338 | { "r3081", mips_r3081_reg_names }, | |
339 | { "lsi33k", mips_lsi33k_reg_names }, | |
340 | { NULL, NULL } | |
341 | }; | |
9846de1b | 342 | /* *INDENT-ON* */ |
c906108c | 343 | |
c5aa993b JM |
344 | |
345 | ||
346 | ||
c906108c | 347 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
348 | static int mips16_to_32_reg[8] = |
349 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
350 | |
351 | /* Heuristic_proc_start may hunt through the text section for a long | |
352 | time across a 2400 baud serial line. Allows the user to limit this | |
353 | search. */ | |
354 | ||
355 | static unsigned int heuristic_fence_post = 0; | |
356 | ||
c5aa993b JM |
357 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
358 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
359 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
360 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
361 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
362 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
363 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
364 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
365 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
366 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
367 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
368 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
369 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
370 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
371 | ||
372 | struct linked_proc_info | |
c5aa993b JM |
373 | { |
374 | struct mips_extra_func_info info; | |
375 | struct linked_proc_info *next; | |
376 | } | |
377 | *linked_proc_desc_table = NULL; | |
c906108c | 378 | |
cce74817 JM |
379 | void |
380 | mips_print_extra_frame_info (fi) | |
381 | struct frame_info *fi; | |
382 | { | |
383 | if (fi | |
384 | && fi->extra_info | |
385 | && fi->extra_info->proc_desc | |
386 | && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 387 | printf_filtered (" frame pointer is at %s+%s\n", |
cce74817 | 388 | REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), |
d4f3574e | 389 | paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); |
cce74817 | 390 | } |
c906108c | 391 | |
43e526b9 JM |
392 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
393 | defines the remote-gdb packet. */ | |
394 | ||
395 | static int mips64_transfers_32bit_regs_p = 0; | |
396 | ||
397 | int | |
398 | mips_register_raw_size (reg_nr) | |
399 | int reg_nr; | |
400 | { | |
401 | if (mips64_transfers_32bit_regs_p) | |
402 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
403 | else | |
404 | return MIPS_REGSIZE; | |
405 | } | |
406 | ||
407 | int | |
408 | mips_register_convertible (reg_nr) | |
409 | int reg_nr; | |
410 | { | |
411 | if (mips64_transfers_32bit_regs_p) | |
412 | return 0; | |
413 | else | |
414 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
415 | } | |
416 | ||
417 | void | |
418 | mips_register_convert_to_virtual (n, virtual_type, raw_buf, virt_buf) | |
419 | int n; | |
420 | struct type *virtual_type; | |
421 | char *raw_buf; | |
422 | char *virt_buf; | |
423 | { | |
424 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
425 | memcpy (virt_buf, | |
426 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
427 | TYPE_LENGTH (virtual_type)); | |
428 | else | |
429 | memcpy (virt_buf, | |
430 | raw_buf, | |
431 | TYPE_LENGTH (virtual_type)); | |
432 | } | |
433 | ||
434 | void | |
435 | mips_register_convert_to_raw (virtual_type, n, virt_buf, raw_buf) | |
436 | struct type *virtual_type; | |
437 | int n; | |
438 | char *virt_buf; | |
439 | char *raw_buf; | |
440 | { | |
441 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
442 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
443 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
444 | virt_buf, | |
445 | TYPE_LENGTH (virtual_type)); | |
446 | else | |
447 | memcpy (raw_buf, | |
448 | virt_buf, | |
449 | TYPE_LENGTH (virtual_type)); | |
450 | } | |
451 | ||
c906108c SS |
452 | /* Should the upper word of 64-bit addresses be zeroed? */ |
453 | static int mask_address_p = 1; | |
454 | ||
455 | /* Should call_function allocate stack space for a struct return? */ | |
456 | int | |
457 | mips_use_struct_convention (gcc_p, type) | |
458 | int gcc_p; | |
459 | struct type *type; | |
460 | { | |
461 | if (MIPS_EABI) | |
7a292a7a | 462 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
c906108c | 463 | else |
c5aa993b | 464 | return 1; /* Structures are returned by ref in extra arg0 */ |
c906108c SS |
465 | } |
466 | ||
467 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ | |
468 | ||
469 | static int | |
470 | pc_is_mips16 (bfd_vma memaddr) | |
471 | { | |
472 | struct minimal_symbol *sym; | |
473 | ||
474 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
475 | if (IS_MIPS16_ADDR (memaddr)) | |
476 | return 1; | |
477 | ||
478 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
479 | the high bit of the info field. Use this to decide if the function is | |
480 | MIPS16 or normal MIPS. */ | |
481 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
482 | if (sym) | |
483 | return MSYMBOL_IS_SPECIAL (sym); | |
484 | else | |
485 | return 0; | |
486 | } | |
487 | ||
488 | ||
489 | /* This returns the PC of the first inst after the prologue. If we can't | |
490 | find the prologue, then return 0. */ | |
491 | ||
492 | static CORE_ADDR | |
493 | after_prologue (pc, proc_desc) | |
494 | CORE_ADDR pc; | |
495 | mips_extra_func_info_t proc_desc; | |
496 | { | |
497 | struct symtab_and_line sal; | |
498 | CORE_ADDR func_addr, func_end; | |
499 | ||
500 | if (!proc_desc) | |
501 | proc_desc = find_proc_desc (pc, NULL); | |
502 | ||
503 | if (proc_desc) | |
504 | { | |
505 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 506 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
507 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
508 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
509 | return 0; | |
510 | } | |
511 | ||
512 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
513 | return 0; /* Unknown */ | |
514 | ||
515 | sal = find_pc_line (func_addr, 0); | |
516 | ||
517 | if (sal.end < func_end) | |
518 | return sal.end; | |
519 | ||
520 | /* The line after the prologue is after the end of the function. In this | |
521 | case, tell the caller to find the prologue the hard way. */ | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
527 | set the appropriate bit in the general register mask or float register mask | |
528 | to indicate which register is saved. This is a helper function | |
529 | for mips_find_saved_regs. */ | |
530 | ||
531 | static void | |
532 | mips32_decode_reg_save (inst, gen_mask, float_mask) | |
533 | t_inst inst; | |
534 | unsigned long *gen_mask; | |
535 | unsigned long *float_mask; | |
536 | { | |
537 | int reg; | |
538 | ||
539 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
540 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
541 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
542 | { | |
543 | /* It might be possible to use the instruction to | |
c5aa993b JM |
544 | find the offset, rather than the code below which |
545 | is based on things being in a certain order in the | |
546 | frame, but figuring out what the instruction's offset | |
547 | is relative to might be a little tricky. */ | |
c906108c SS |
548 | reg = (inst & 0x001f0000) >> 16; |
549 | *gen_mask |= (1 << reg); | |
550 | } | |
551 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
552 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
553 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
554 | |
555 | { | |
556 | reg = ((inst & 0x001f0000) >> 16); | |
557 | *float_mask |= (1 << reg); | |
558 | } | |
559 | } | |
560 | ||
561 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
562 | set the appropriate bit in the general register or float register mask | |
563 | to indicate which register is saved. This is a helper function | |
564 | for mips_find_saved_regs. */ | |
565 | ||
566 | static void | |
567 | mips16_decode_reg_save (inst, gen_mask) | |
568 | t_inst inst; | |
569 | unsigned long *gen_mask; | |
570 | { | |
c5aa993b | 571 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
572 | { |
573 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
574 | *gen_mask |= (1 << reg); | |
575 | } | |
c5aa993b | 576 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
577 | { |
578 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
579 | *gen_mask |= (1 << reg); | |
580 | } | |
c5aa993b | 581 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
582 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
583 | *gen_mask |= (1 << RA_REGNUM); | |
584 | } | |
585 | ||
586 | ||
587 | /* Fetch and return instruction from the specified location. If the PC | |
588 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
589 | ||
590 | static t_inst | |
591 | mips_fetch_instruction (addr) | |
c5aa993b | 592 | CORE_ADDR addr; |
c906108c SS |
593 | { |
594 | char buf[MIPS_INSTLEN]; | |
595 | int instlen; | |
596 | int status; | |
597 | ||
598 | if (pc_is_mips16 (addr)) | |
599 | { | |
600 | instlen = MIPS16_INSTLEN; | |
601 | addr = UNMAKE_MIPS16_ADDR (addr); | |
602 | } | |
603 | else | |
c5aa993b | 604 | instlen = MIPS_INSTLEN; |
c906108c SS |
605 | status = read_memory_nobpt (addr, buf, instlen); |
606 | if (status) | |
607 | memory_error (status, addr); | |
608 | return extract_unsigned_integer (buf, instlen); | |
609 | } | |
610 | ||
611 | ||
612 | /* These the fields of 32 bit mips instructions */ | |
613 | #define mips32_op(x) (x >> 25) | |
614 | #define itype_op(x) (x >> 25) | |
615 | #define itype_rs(x) ((x >> 21)& 0x1f) | |
616 | #define itype_rt(x) ((x >> 16) & 0x1f) | |
617 | #define itype_immediate(x) ( x & 0xffff) | |
618 | ||
619 | #define jtype_op(x) (x >> 25) | |
620 | #define jtype_target(x) ( x & 0x03fffff) | |
621 | ||
622 | #define rtype_op(x) (x >>25) | |
623 | #define rtype_rs(x) ((x>>21) & 0x1f) | |
624 | #define rtype_rt(x) ((x>>16) & 0x1f) | |
c5aa993b | 625 | #define rtype_rd(x) ((x>>11) & 0x1f) |
c906108c SS |
626 | #define rtype_shamt(x) ((x>>6) & 0x1f) |
627 | #define rtype_funct(x) (x & 0x3f ) | |
628 | ||
629 | static CORE_ADDR | |
c5aa993b JM |
630 | mips32_relative_offset (unsigned long inst) |
631 | { | |
632 | long x; | |
633 | x = itype_immediate (inst); | |
634 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 635 | { |
c5aa993b | 636 | x |= 0xffff0000; /* sign extension */ |
c906108c | 637 | } |
c5aa993b JM |
638 | x = x << 2; |
639 | return x; | |
c906108c SS |
640 | } |
641 | ||
642 | /* Determine whate to set a single step breakpoint while considering | |
643 | branch prediction */ | |
644 | CORE_ADDR | |
c5aa993b JM |
645 | mips32_next_pc (CORE_ADDR pc) |
646 | { | |
647 | unsigned long inst; | |
648 | int op; | |
649 | inst = mips_fetch_instruction (pc); | |
650 | if ((inst & 0xe0000000) != 0) /* Not a special, junp or branch instruction */ | |
651 | { | |
652 | if ((inst >> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */ | |
653 | { | |
654 | op = ((inst >> 25) & 0x03); | |
c906108c SS |
655 | switch (op) |
656 | { | |
c5aa993b JM |
657 | case 0: |
658 | goto equal_branch; /* BEQL */ | |
659 | case 1: | |
660 | goto neq_branch; /* BNEZ */ | |
661 | case 2: | |
662 | goto less_branch; /* BLEZ */ | |
663 | case 3: | |
664 | goto greater_branch; /* BGTZ */ | |
665 | default: | |
666 | pc += 4; | |
c906108c SS |
667 | } |
668 | } | |
c5aa993b JM |
669 | else |
670 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
671 | } |
672 | else | |
c5aa993b JM |
673 | { /* This gets way messy */ |
674 | ||
c906108c | 675 | /* Further subdivide into SPECIAL, REGIMM and other */ |
c5aa993b | 676 | switch (op = ((inst >> 26) & 0x07)) /* extract bits 28,27,26 */ |
c906108c | 677 | { |
c5aa993b JM |
678 | case 0: /* SPECIAL */ |
679 | op = rtype_funct (inst); | |
680 | switch (op) | |
681 | { | |
682 | case 8: /* JR */ | |
683 | case 9: /* JALR */ | |
684 | pc = read_register (rtype_rs (inst)); /* Set PC to that address */ | |
685 | break; | |
686 | default: | |
687 | pc += 4; | |
688 | } | |
689 | ||
690 | break; /* end special */ | |
691 | case 1: /* REGIMM */ | |
c906108c | 692 | { |
c5aa993b JM |
693 | op = jtype_op (inst); /* branch condition */ |
694 | switch (jtype_op (inst)) | |
c906108c | 695 | { |
c5aa993b JM |
696 | case 0: /* BLTZ */ |
697 | case 2: /* BLTXL */ | |
698 | case 16: /* BLTZALL */ | |
699 | case 18: /* BLTZALL */ | |
c906108c | 700 | less_branch: |
c5aa993b JM |
701 | if (read_register (itype_rs (inst)) < 0) |
702 | pc += mips32_relative_offset (inst) + 4; | |
703 | else | |
704 | pc += 8; /* after the delay slot */ | |
705 | break; | |
706 | case 1: /* GEZ */ | |
707 | case 3: /* BGEZL */ | |
708 | case 17: /* BGEZAL */ | |
709 | case 19: /* BGEZALL */ | |
c906108c | 710 | greater_equal_branch: |
c5aa993b JM |
711 | if (read_register (itype_rs (inst)) >= 0) |
712 | pc += mips32_relative_offset (inst) + 4; | |
713 | else | |
714 | pc += 8; /* after the delay slot */ | |
715 | break; | |
716 | /* All of the other intructions in the REGIMM catagory */ | |
717 | default: | |
718 | pc += 4; | |
c906108c SS |
719 | } |
720 | } | |
c5aa993b JM |
721 | break; /* end REGIMM */ |
722 | case 2: /* J */ | |
723 | case 3: /* JAL */ | |
724 | { | |
725 | unsigned long reg; | |
726 | reg = jtype_target (inst) << 2; | |
727 | pc = reg + ((pc + 4) & 0xf0000000); | |
c906108c SS |
728 | /* Whats this mysterious 0xf000000 adjustment ??? */ |
729 | } | |
c5aa993b JM |
730 | break; |
731 | /* FIXME case JALX : */ | |
732 | { | |
733 | unsigned long reg; | |
734 | reg = jtype_target (inst) << 2; | |
735 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
736 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
737 | } | |
c5aa993b JM |
738 | break; /* The new PC will be alternate mode */ |
739 | case 4: /* BEQ , BEQL */ | |
740 | equal_branch: | |
741 | if (read_register (itype_rs (inst)) == | |
742 | read_register (itype_rt (inst))) | |
743 | pc += mips32_relative_offset (inst) + 4; | |
744 | else | |
745 | pc += 8; | |
746 | break; | |
747 | case 5: /* BNE , BNEL */ | |
748 | neq_branch: | |
749 | if (read_register (itype_rs (inst)) != | |
750 | read_register (itype_rs (inst))) | |
751 | pc += mips32_relative_offset (inst) + 4; | |
752 | else | |
753 | pc += 8; | |
754 | break; | |
755 | case 6: /* BLEZ , BLEZL */ | |
c906108c | 756 | less_zero_branch: |
c5aa993b JM |
757 | if (read_register (itype_rs (inst) <= 0)) |
758 | pc += mips32_relative_offset (inst) + 4; | |
759 | else | |
760 | pc += 8; | |
761 | break; | |
762 | case 7: | |
763 | greater_branch: /* BGTZ BGTZL */ | |
764 | if (read_register (itype_rs (inst) > 0)) | |
765 | pc += mips32_relative_offset (inst) + 4; | |
766 | else | |
767 | pc += 8; | |
768 | break; | |
769 | default: | |
770 | pc += 8; | |
771 | } /* switch */ | |
772 | } /* else */ | |
773 | return pc; | |
774 | } /* mips32_next_pc */ | |
c906108c SS |
775 | |
776 | /* Decoding the next place to set a breakpoint is irregular for the | |
777 | mips 16 variant, but fortunatly, there fewer instructions. We have to cope | |
778 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. | |
779 | We dont want to set a single step instruction on the extend instruction | |
780 | either. | |
c5aa993b | 781 | */ |
c906108c SS |
782 | |
783 | /* Lots of mips16 instruction formats */ | |
784 | /* Predicting jumps requires itype,ritype,i8type | |
785 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 786 | */ |
c906108c SS |
787 | enum mips16_inst_fmts |
788 | { | |
c5aa993b JM |
789 | itype, /* 0 immediate 5,10 */ |
790 | ritype, /* 1 5,3,8 */ | |
791 | rrtype, /* 2 5,3,3,5 */ | |
792 | rritype, /* 3 5,3,3,5 */ | |
793 | rrrtype, /* 4 5,3,3,3,2 */ | |
794 | rriatype, /* 5 5,3,3,1,4 */ | |
795 | shifttype, /* 6 5,3,3,3,2 */ | |
796 | i8type, /* 7 5,3,8 */ | |
797 | i8movtype, /* 8 5,3,3,5 */ | |
798 | i8mov32rtype, /* 9 5,3,5,3 */ | |
799 | i64type, /* 10 5,3,8 */ | |
800 | ri64type, /* 11 5,3,3,5 */ | |
801 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
802 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
803 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
804 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
805 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
806 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
807 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
808 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
809 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
810 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
811 | }; | |
c906108c SS |
812 | /* I am heaping all the fields of the formats into one structure and then, |
813 | only the fields which are involved in instruction extension */ | |
814 | struct upk_mips16 | |
c5aa993b JM |
815 | { |
816 | unsigned short inst; | |
817 | enum mips16_inst_fmts fmt; | |
818 | unsigned long offset; | |
819 | unsigned int regx; /* Function in i8 type */ | |
820 | unsigned int regy; | |
821 | }; | |
c906108c SS |
822 | |
823 | ||
824 | ||
c5aa993b JM |
825 | static void |
826 | print_unpack (char *comment, | |
827 | struct upk_mips16 *u) | |
c906108c | 828 | { |
d4f3574e SS |
829 | printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n", |
830 | comment, u->inst, u->fmt, paddr (u->offset), u->regx, u->regy); | |
c906108c SS |
831 | } |
832 | ||
833 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same | |
834 | format for the bits which make up the immediatate extension. | |
c5aa993b | 835 | */ |
c906108c | 836 | static unsigned long |
c5aa993b | 837 | extended_offset (unsigned long extension) |
c906108c | 838 | { |
c5aa993b JM |
839 | unsigned long value; |
840 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ | |
841 | value = value << 6; | |
842 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
843 | value = value << 5; | |
844 | value |= extension & 0x01f; /* extract 4:0 */ | |
845 | return value; | |
c906108c SS |
846 | } |
847 | ||
848 | /* Only call this function if you know that this is an extendable | |
849 | instruction, It wont malfunction, but why make excess remote memory references? | |
850 | If the immediate operands get sign extended or somthing, do it after | |
851 | the extension is performed. | |
c5aa993b | 852 | */ |
c906108c SS |
853 | /* FIXME: Every one of these cases needs to worry about sign extension |
854 | when the offset is to be used in relative addressing */ | |
855 | ||
856 | ||
c5aa993b JM |
857 | static unsigned short |
858 | fetch_mips_16 (CORE_ADDR pc) | |
c906108c | 859 | { |
c5aa993b JM |
860 | char buf[8]; |
861 | pc &= 0xfffffffe; /* clear the low order bit */ | |
862 | target_read_memory (pc, buf, 2); | |
863 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
864 | } |
865 | ||
866 | static void | |
c5aa993b JM |
867 | unpack_mips16 (CORE_ADDR pc, |
868 | struct upk_mips16 *upk) | |
c906108c | 869 | { |
c5aa993b JM |
870 | CORE_ADDR extpc; |
871 | unsigned long extension; | |
872 | int extended; | |
873 | extpc = (pc - 4) & ~0x01; /* Extensions are 32 bit instructions */ | |
c906108c SS |
874 | /* Decrement to previous address and loose the 16bit mode flag */ |
875 | /* return if the instruction was extendable, but not actually extended */ | |
c5aa993b JM |
876 | extended = ((mips32_op (extension) == 30) ? 1 : 0); |
877 | if (extended) | |
878 | { | |
879 | extension = mips_fetch_instruction (extpc); | |
880 | } | |
c906108c SS |
881 | switch (upk->fmt) |
882 | { | |
c5aa993b | 883 | case itype: |
c906108c | 884 | { |
c5aa993b | 885 | unsigned long value; |
c906108c | 886 | if (extended) |
c5aa993b JM |
887 | { |
888 | value = extended_offset (extension); | |
889 | value = value << 11; /* rom for the original value */ | |
890 | value |= upk->inst & 0x7ff; /* eleven bits from instruction */ | |
c906108c SS |
891 | } |
892 | else | |
c5aa993b JM |
893 | { |
894 | value = upk->inst & 0x7ff; | |
895 | /* FIXME : Consider sign extension */ | |
c906108c | 896 | } |
c5aa993b | 897 | upk->offset = value; |
c906108c | 898 | } |
c5aa993b JM |
899 | break; |
900 | case ritype: | |
901 | case i8type: | |
902 | { /* A register identifier and an offset */ | |
c906108c SS |
903 | /* Most of the fields are the same as I type but the |
904 | immediate value is of a different length */ | |
c5aa993b | 905 | unsigned long value; |
c906108c SS |
906 | if (extended) |
907 | { | |
c5aa993b JM |
908 | value = extended_offset (extension); |
909 | value = value << 8; /* from the original instruction */ | |
910 | value |= upk->inst & 0xff; /* eleven bits from instruction */ | |
911 | upk->regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
912 | if (value & 0x4000) /* test the sign bit , bit 26 */ | |
913 | { | |
914 | value &= ~0x3fff; /* remove the sign bit */ | |
915 | value = -value; | |
c906108c SS |
916 | } |
917 | } | |
c5aa993b JM |
918 | else |
919 | { | |
920 | value = upk->inst & 0xff; /* 8 bits */ | |
921 | upk->regx = (upk->inst >> 8) & 0x07; /* or i8 funct */ | |
922 | /* FIXME: Do sign extension , this format needs it */ | |
923 | if (value & 0x80) /* THIS CONFUSES ME */ | |
924 | { | |
925 | value &= 0xef; /* remove the sign bit */ | |
926 | value = -value; | |
927 | } | |
928 | ||
929 | } | |
930 | upk->offset = value; | |
931 | break; | |
c906108c | 932 | } |
c5aa993b | 933 | case jalxtype: |
c906108c | 934 | { |
c5aa993b JM |
935 | unsigned long value; |
936 | unsigned short nexthalf; | |
937 | value = ((upk->inst & 0x1f) << 5) | ((upk->inst >> 5) & 0x1f); | |
938 | value = value << 16; | |
939 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
940 | value |= nexthalf; | |
941 | upk->offset = value; | |
942 | break; | |
c906108c SS |
943 | } |
944 | default: | |
c5aa993b JM |
945 | printf_filtered ("Decoding unimplemented instruction format type\n"); |
946 | break; | |
c906108c SS |
947 | } |
948 | /* print_unpack("UPK",upk) ; */ | |
949 | } | |
950 | ||
951 | ||
952 | #define mips16_op(x) (x >> 11) | |
953 | ||
954 | /* This is a map of the opcodes which ae known to perform branches */ | |
955 | static unsigned char map16[32] = | |
c5aa993b JM |
956 | {0, 0, 1, 1, 1, 1, 0, 0, |
957 | 0, 0, 0, 0, 1, 0, 0, 0, | |
958 | 0, 0, 0, 0, 0, 0, 0, 0, | |
959 | 0, 0, 0, 0, 0, 1, 1, 0 | |
960 | }; | |
c906108c | 961 | |
c5aa993b JM |
962 | static CORE_ADDR |
963 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 964 | { |
c5aa993b JM |
965 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
966 | ||
c906108c SS |
967 | } |
968 | ||
969 | ||
970 | ||
c5aa993b | 971 | static struct upk_mips16 upk; |
c906108c | 972 | |
c5aa993b JM |
973 | CORE_ADDR |
974 | mips16_next_pc (CORE_ADDR pc) | |
c906108c | 975 | { |
c5aa993b JM |
976 | int op; |
977 | t_inst inst; | |
c906108c | 978 | /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */ |
c5aa993b JM |
979 | inst = fetch_mips_16 (pc); |
980 | upk.inst = inst; | |
981 | op = mips16_op (upk.inst); | |
c906108c SS |
982 | if (map16[op]) |
983 | { | |
c5aa993b | 984 | int reg; |
c906108c SS |
985 | switch (op) |
986 | { | |
c5aa993b JM |
987 | case 2: /* Branch */ |
988 | upk.fmt = itype; | |
989 | unpack_mips16 (pc, &upk); | |
990 | { | |
991 | long offset; | |
992 | offset = upk.offset; | |
c906108c | 993 | if (offset & 0x800) |
c5aa993b JM |
994 | { |
995 | offset &= 0xeff; | |
996 | offset = -offset; | |
c906108c | 997 | } |
c5aa993b | 998 | pc += (offset << 1) + 2; |
c906108c | 999 | } |
c5aa993b JM |
1000 | break; |
1001 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1002 | upk.fmt = jalxtype; | |
1003 | unpack_mips16 (pc, &upk); | |
1004 | pc = add_offset_16 (pc, upk.offset); | |
1005 | if ((upk.inst >> 10) & 0x01) /* Exchange mode */ | |
1006 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1007 | else | |
1008 | pc |= 0x01; | |
1009 | break; | |
1010 | case 4: /* beqz */ | |
1011 | upk.fmt = ritype; | |
1012 | unpack_mips16 (pc, &upk); | |
1013 | reg = read_register (upk.regx); | |
1014 | if (reg == 0) | |
1015 | pc += (upk.offset << 1) + 2; | |
1016 | else | |
1017 | pc += 2; | |
1018 | break; | |
1019 | case 5: /* bnez */ | |
1020 | upk.fmt = ritype; | |
1021 | unpack_mips16 (pc, &upk); | |
1022 | reg = read_register (upk.regx); | |
1023 | if (reg != 0) | |
1024 | pc += (upk.offset << 1) + 2; | |
1025 | else | |
1026 | pc += 2; | |
1027 | break; | |
1028 | case 12: /* I8 Formats btez btnez */ | |
1029 | upk.fmt = i8type; | |
1030 | unpack_mips16 (pc, &upk); | |
1031 | /* upk.regx contains the opcode */ | |
1032 | reg = read_register (24); /* Test register is 24 */ | |
1033 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1034 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1035 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1036 | pc += (upk.offset << 1) + 2; | |
1037 | else | |
1038 | pc += 2; | |
1039 | break; | |
1040 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1041 | upk.fmt = rrtype; | |
1042 | op = upk.inst & 0x1f; | |
c906108c | 1043 | if (op == 0) |
c5aa993b JM |
1044 | { |
1045 | upk.regx = (upk.inst >> 8) & 0x07; | |
1046 | upk.regy = (upk.inst >> 5) & 0x07; | |
c906108c SS |
1047 | switch (upk.regy) |
1048 | { | |
c5aa993b JM |
1049 | case 0: |
1050 | reg = upk.regx; | |
1051 | break; | |
1052 | case 1: | |
1053 | reg = 31; | |
1054 | break; /* Function return instruction */ | |
1055 | case 2: | |
1056 | reg = upk.regx; | |
1057 | break; | |
1058 | default: | |
1059 | reg = 31; | |
1060 | break; /* BOGUS Guess */ | |
c906108c | 1061 | } |
c5aa993b | 1062 | pc = read_register (reg); |
c906108c | 1063 | } |
c5aa993b JM |
1064 | else |
1065 | pc += 2; | |
1066 | break; | |
1067 | case 30: /* This is an extend instruction */ | |
1068 | pc += 4; /* Dont be setting breakpints on the second half */ | |
1069 | break; | |
1070 | default: | |
1071 | printf ("Filtered - next PC probably incorrrect due to jump inst\n"); | |
1072 | pc += 2; | |
1073 | break; | |
c906108c SS |
1074 | } |
1075 | } | |
c5aa993b JM |
1076 | else |
1077 | pc += 2; /* just a good old instruction */ | |
c906108c SS |
1078 | /* See if we CAN actually break on the next instruction */ |
1079 | /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */ | |
c5aa993b JM |
1080 | return pc; |
1081 | } /* mips16_next_pc */ | |
c906108c SS |
1082 | |
1083 | /* The mips_next_pc function supports single_tep when the remote target monitor or | |
1084 | stub is not developed enough to so a single_step. | |
1085 | It works by decoding the current instruction and predicting where a branch | |
1086 | will go. This isnt hard because all the data is available. | |
1087 | The MIPS32 and MIPS16 variants are quite different | |
c5aa993b JM |
1088 | */ |
1089 | CORE_ADDR | |
1090 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1091 | { |
c5aa993b | 1092 | t_inst inst; |
c906108c SS |
1093 | /* inst = mips_fetch_instruction(pc) ; */ |
1094 | /* if (pc_is_mips16) <----- This is failing */ | |
c5aa993b JM |
1095 | if (pc & 0x01) |
1096 | return mips16_next_pc (pc); | |
1097 | else | |
1098 | return mips32_next_pc (pc); | |
1099 | } /* mips_next_pc */ | |
c906108c SS |
1100 | |
1101 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it | |
1102 | NULL). */ | |
1103 | ||
1104 | void | |
1105 | mips_find_saved_regs (fci) | |
1106 | struct frame_info *fci; | |
1107 | { | |
1108 | int ireg; | |
1109 | CORE_ADDR reg_position; | |
1110 | /* r0 bit means kernel trap */ | |
1111 | int kernel_trap; | |
1112 | /* What registers have been saved? Bitmasks. */ | |
1113 | unsigned long gen_mask, float_mask; | |
1114 | mips_extra_func_info_t proc_desc; | |
1115 | t_inst inst; | |
1116 | ||
1117 | frame_saved_regs_zalloc (fci); | |
1118 | ||
1119 | /* If it is the frame for sigtramp, the saved registers are located | |
1120 | in a sigcontext structure somewhere on the stack. | |
1121 | If the stack layout for sigtramp changes we might have to change these | |
1122 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
1123 | #ifndef SIGFRAME_BASE | |
1124 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
1125 | above the sigtramp frame. */ | |
1126 | #define SIGFRAME_BASE MIPS_REGSIZE | |
1127 | /* FIXME! Are these correct?? */ | |
1128 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1129 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1130 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1131 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1132 | #endif | |
1133 | #ifndef SIGFRAME_REG_SIZE | |
1134 | /* FIXME! Is this correct?? */ | |
1135 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
1136 | #endif | |
1137 | if (fci->signal_handler_caller) | |
1138 | { | |
1139 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1140 | { | |
c5aa993b JM |
1141 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF |
1142 | + ireg * SIGFRAME_REG_SIZE; | |
1143 | fci->saved_regs[ireg] = reg_position; | |
c906108c SS |
1144 | } |
1145 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1146 | { | |
c5aa993b JM |
1147 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF |
1148 | + ireg * SIGFRAME_REG_SIZE; | |
1149 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; | |
c906108c SS |
1150 | } |
1151 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
1152 | return; | |
1153 | } | |
1154 | ||
cce74817 | 1155 | proc_desc = fci->extra_info->proc_desc; |
c906108c SS |
1156 | if (proc_desc == NULL) |
1157 | /* I'm not sure how/whether this can happen. Normally when we can't | |
1158 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
1159 | and set the saved_regs right away. */ | |
1160 | return; | |
1161 | ||
c5aa993b JM |
1162 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1163 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1164 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1165 | |
c5aa993b JM |
1166 | if ( /* In any frame other than the innermost or a frame interrupted by |
1167 | a signal, we assume that all registers have been saved. | |
1168 | This assumes that all register saves in a function happen before | |
1169 | the first function call. */ | |
1170 | (fci->next == NULL || fci->next->signal_handler_caller) | |
c906108c | 1171 | |
c5aa993b JM |
1172 | /* In a dummy frame we know exactly where things are saved. */ |
1173 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
c906108c | 1174 | |
c5aa993b JM |
1175 | /* Don't bother unless we are inside a function prologue. Outside the |
1176 | prologue, we know where everything is. */ | |
c906108c | 1177 | |
c5aa993b | 1178 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) |
c906108c | 1179 | |
c5aa993b JM |
1180 | /* Not sure exactly what kernel_trap means, but if it means |
1181 | the kernel saves the registers without a prologue doing it, | |
1182 | we better not examine the prologue to see whether registers | |
1183 | have been saved yet. */ | |
1184 | && !kernel_trap) | |
c906108c SS |
1185 | { |
1186 | /* We need to figure out whether the registers that the proc_desc | |
c5aa993b | 1187 | claims are saved have been saved yet. */ |
c906108c SS |
1188 | |
1189 | CORE_ADDR addr; | |
1190 | ||
1191 | /* Bitmasks; set if we have found a save for the register. */ | |
1192 | unsigned long gen_save_found = 0; | |
1193 | unsigned long float_save_found = 0; | |
1194 | int instlen; | |
1195 | ||
1196 | /* If the address is odd, assume this is MIPS16 code. */ | |
1197 | addr = PROC_LOW_ADDR (proc_desc); | |
1198 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1199 | ||
1200 | /* Scan through this function's instructions preceding the current | |
1201 | PC, and look for those that save registers. */ | |
1202 | while (addr < fci->pc) | |
1203 | { | |
1204 | inst = mips_fetch_instruction (addr); | |
1205 | if (pc_is_mips16 (addr)) | |
1206 | mips16_decode_reg_save (inst, &gen_save_found); | |
1207 | else | |
1208 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1209 | addr += instlen; | |
1210 | } | |
1211 | gen_mask = gen_save_found; | |
1212 | float_mask = float_save_found; | |
1213 | } | |
1214 | ||
1215 | /* Fill in the offsets for the registers which gen_mask says | |
1216 | were saved. */ | |
1217 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
c5aa993b | 1218 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
c906108c SS |
1219 | if (gen_mask & 0x80000000) |
1220 | { | |
1221 | fci->saved_regs[ireg] = reg_position; | |
7a292a7a | 1222 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1223 | } |
1224 | ||
1225 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
1226 | of that normally used by gcc. Therefore, we have to fetch the first | |
1227 | instruction of the function, and if it's an entry instruction that | |
1228 | saves $s0 or $s1, correct their saved addresses. */ | |
1229 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1230 | { | |
1231 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
c5aa993b | 1232 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
c906108c SS |
1233 | { |
1234 | int reg; | |
1235 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1236 | |
c906108c SS |
1237 | /* Check if the ra register was pushed on the stack. */ |
1238 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
1239 | if (inst & 0x20) | |
7a292a7a | 1240 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1241 | |
1242 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c5aa993b | 1243 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c SS |
1244 | { |
1245 | fci->saved_regs[reg] = reg_position; | |
7a292a7a | 1246 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1247 | } |
1248 | } | |
1249 | } | |
1250 | ||
1251 | /* Fill in the offsets for the registers which float_mask says | |
1252 | were saved. */ | |
1253 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
1254 | ||
1255 | /* The freg_offset points to where the first *double* register | |
1256 | is saved. So skip to the high-order word. */ | |
c5aa993b | 1257 | if (!GDB_TARGET_IS_MIPS64) |
7a292a7a | 1258 | reg_position += MIPS_SAVED_REGSIZE; |
c906108c SS |
1259 | |
1260 | /* Fill in the offsets for the float registers which float_mask says | |
1261 | were saved. */ | |
c5aa993b | 1262 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) |
c906108c SS |
1263 | if (float_mask & 0x80000000) |
1264 | { | |
c5aa993b | 1265 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
7a292a7a | 1266 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1267 | } |
1268 | ||
1269 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; | |
1270 | } | |
1271 | ||
1272 | static CORE_ADDR | |
c5aa993b | 1273 | read_next_frame_reg (fi, regno) |
c906108c SS |
1274 | struct frame_info *fi; |
1275 | int regno; | |
1276 | { | |
1277 | for (; fi; fi = fi->next) | |
1278 | { | |
1279 | /* We have to get the saved sp from the sigcontext | |
c5aa993b | 1280 | if it is a signal handler frame. */ |
c906108c SS |
1281 | if (regno == SP_REGNUM && !fi->signal_handler_caller) |
1282 | return fi->frame; | |
1283 | else | |
1284 | { | |
1285 | if (fi->saved_regs == NULL) | |
1286 | mips_find_saved_regs (fi); | |
1287 | if (fi->saved_regs[regno]) | |
2acceee2 | 1288 | return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE); |
c906108c SS |
1289 | } |
1290 | } | |
1291 | return read_register (regno); | |
1292 | } | |
1293 | ||
1294 | /* mips_addr_bits_remove - remove useless address bits */ | |
1295 | ||
1296 | CORE_ADDR | |
1297 | mips_addr_bits_remove (addr) | |
c5aa993b | 1298 | CORE_ADDR addr; |
c906108c SS |
1299 | { |
1300 | #if GDB_TARGET_IS_MIPS64 | |
c5aa993b | 1301 | if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
c906108c SS |
1302 | { |
1303 | /* This hack is a work-around for existing boards using PMON, | |
c5aa993b JM |
1304 | the simulator, and any other 64-bit targets that doesn't have |
1305 | true 64-bit addressing. On these targets, the upper 32 bits | |
1306 | of addresses are ignored by the hardware. Thus, the PC or SP | |
1307 | are likely to have been sign extended to all 1s by instruction | |
1308 | sequences that load 32-bit addresses. For example, a typical | |
1309 | piece of code that loads an address is this: | |
1310 | lui $r2, <upper 16 bits> | |
1311 | ori $r2, <lower 16 bits> | |
1312 | But the lui sign-extends the value such that the upper 32 bits | |
1313 | may be all 1s. The workaround is simply to mask off these bits. | |
1314 | In the future, gcc may be changed to support true 64-bit | |
1315 | addressing, and this masking will have to be disabled. */ | |
1316 | addr &= (CORE_ADDR) 0xffffffff; | |
c906108c SS |
1317 | } |
1318 | #else | |
1319 | /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf), | |
1320 | BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits. | |
1321 | So we still have to mask off useless bits from addresses. */ | |
c5aa993b | 1322 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c SS |
1323 | #endif |
1324 | ||
1325 | return addr; | |
1326 | } | |
1327 | ||
1328 | void | |
1329 | mips_init_frame_pc_first (fromleaf, prev) | |
1330 | int fromleaf; | |
1331 | struct frame_info *prev; | |
1332 | { | |
1333 | CORE_ADDR pc, tmp; | |
1334 | ||
1335 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
c5aa993b | 1336 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); |
c906108c | 1337 | tmp = mips_skip_stub (pc); |
c5aa993b | 1338 | prev->pc = tmp ? tmp : pc; |
c906108c SS |
1339 | } |
1340 | ||
1341 | ||
1342 | CORE_ADDR | |
c5aa993b | 1343 | mips_frame_saved_pc (frame) |
c906108c SS |
1344 | struct frame_info *frame; |
1345 | { | |
1346 | CORE_ADDR saved_pc; | |
cce74817 | 1347 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c SS |
1348 | /* We have to get the saved pc from the sigcontext |
1349 | if it is a signal handler frame. */ | |
1350 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
c5aa993b | 1351 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1352 | |
c5aa993b | 1353 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
7a292a7a | 1354 | saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1355 | else |
7a292a7a | 1356 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1357 | |
1358 | return ADDR_BITS_REMOVE (saved_pc); | |
1359 | } | |
1360 | ||
1361 | static struct mips_extra_func_info temp_proc_desc; | |
cce74817 | 1362 | static CORE_ADDR temp_saved_regs[NUM_REGS]; |
c906108c SS |
1363 | |
1364 | /* Set a register's saved stack address in temp_saved_regs. If an address | |
1365 | has already been set for this register, do nothing; this way we will | |
1366 | only recognize the first save of a given register in a function prologue. | |
1367 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ | |
1368 | ||
1369 | static void | |
1370 | set_reg_offset (regno, offset) | |
1371 | int regno; | |
1372 | CORE_ADDR offset; | |
1373 | { | |
cce74817 JM |
1374 | if (temp_saved_regs[regno] == 0) |
1375 | temp_saved_regs[regno] = offset; | |
c906108c SS |
1376 | } |
1377 | ||
1378 | ||
1379 | /* Test whether the PC points to the return instruction at the | |
1380 | end of a function. */ | |
1381 | ||
c5aa993b | 1382 | static int |
c906108c SS |
1383 | mips_about_to_return (pc) |
1384 | CORE_ADDR pc; | |
1385 | { | |
1386 | if (pc_is_mips16 (pc)) | |
1387 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1388 | generates a "jr $ra"; other times it generates code to load | |
1389 | the return address from the stack to an accessible register (such | |
1390 | as $a3), then a "jr" using that register. This second case | |
1391 | is almost impossible to distinguish from an indirect jump | |
1392 | used for switch statements, so we don't even try. */ | |
1393 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1394 | else | |
1395 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1396 | } | |
1397 | ||
1398 | ||
1399 | /* This fencepost looks highly suspicious to me. Removing it also | |
1400 | seems suspicious as it could affect remote debugging across serial | |
1401 | lines. */ | |
1402 | ||
1403 | static CORE_ADDR | |
1404 | heuristic_proc_start (pc) | |
c5aa993b | 1405 | CORE_ADDR pc; |
c906108c | 1406 | { |
c5aa993b JM |
1407 | CORE_ADDR start_pc; |
1408 | CORE_ADDR fence; | |
1409 | int instlen; | |
1410 | int seen_adjsp = 0; | |
c906108c | 1411 | |
c5aa993b JM |
1412 | pc = ADDR_BITS_REMOVE (pc); |
1413 | start_pc = pc; | |
1414 | fence = start_pc - heuristic_fence_post; | |
1415 | if (start_pc == 0) | |
1416 | return 0; | |
c906108c | 1417 | |
c5aa993b JM |
1418 | if (heuristic_fence_post == UINT_MAX |
1419 | || fence < VM_MIN_ADDRESS) | |
1420 | fence = VM_MIN_ADDRESS; | |
c906108c | 1421 | |
c5aa993b | 1422 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1423 | |
c5aa993b JM |
1424 | /* search back for previous return */ |
1425 | for (start_pc -= instlen;; start_pc -= instlen) | |
1426 | if (start_pc < fence) | |
1427 | { | |
1428 | /* It's not clear to me why we reach this point when | |
1429 | stop_soon_quietly, but with this test, at least we | |
1430 | don't print out warnings for every child forked (eg, on | |
1431 | decstation). 22apr93 rich@cygnus.com. */ | |
1432 | if (!stop_soon_quietly) | |
c906108c | 1433 | { |
c5aa993b JM |
1434 | static int blurb_printed = 0; |
1435 | ||
1436 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1437 | paddr_nz (pc)); | |
1438 | ||
1439 | if (!blurb_printed) | |
c906108c | 1440 | { |
c5aa993b JM |
1441 | /* This actually happens frequently in embedded |
1442 | development, when you first connect to a board | |
1443 | and your stack pointer and pc are nowhere in | |
1444 | particular. This message needs to give people | |
1445 | in that situation enough information to | |
1446 | determine that it's no big deal. */ | |
1447 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1448 | GDB is unable to find the start of the function at 0x%s\n\ |
1449 | and thus can't determine the size of that function's stack frame.\n\ | |
1450 | This means that GDB may be unable to access that stack frame, or\n\ | |
1451 | the frames below it.\n\ | |
1452 | This problem is most likely caused by an invalid program counter or\n\ | |
1453 | stack pointer.\n\ | |
1454 | However, if you think GDB should simply search farther back\n\ | |
1455 | from 0x%s for code which looks like the beginning of a\n\ | |
1456 | function, you can increase the range of the search using the `set\n\ | |
1457 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1458 | paddr_nz (pc), paddr_nz (pc)); |
1459 | blurb_printed = 1; | |
c906108c | 1460 | } |
c906108c SS |
1461 | } |
1462 | ||
c5aa993b JM |
1463 | return 0; |
1464 | } | |
1465 | else if (pc_is_mips16 (start_pc)) | |
1466 | { | |
1467 | unsigned short inst; | |
1468 | ||
1469 | /* On MIPS16, any one of the following is likely to be the | |
1470 | start of a function: | |
1471 | entry | |
1472 | addiu sp,-n | |
1473 | daddiu sp,-n | |
1474 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1475 | inst = mips_fetch_instruction (start_pc); | |
1476 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1477 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1478 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1479 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1480 | break; | |
1481 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1482 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1483 | seen_adjsp = 1; | |
1484 | else | |
1485 | seen_adjsp = 0; | |
1486 | } | |
1487 | else if (mips_about_to_return (start_pc)) | |
1488 | { | |
1489 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1490 | break; | |
1491 | } | |
1492 | ||
c906108c | 1493 | #if 0 |
c5aa993b JM |
1494 | /* skip nops (usually 1) 0 - is this */ |
1495 | while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) | |
1496 | start_pc += MIPS_INSTLEN; | |
c906108c | 1497 | #endif |
c5aa993b | 1498 | return start_pc; |
c906108c SS |
1499 | } |
1500 | ||
1501 | /* Fetch the immediate value from a MIPS16 instruction. | |
1502 | If the previous instruction was an EXTEND, use it to extend | |
1503 | the upper bits of the immediate value. This is a helper function | |
1504 | for mips16_heuristic_proc_desc. */ | |
1505 | ||
1506 | static int | |
1507 | mips16_get_imm (prev_inst, inst, nbits, scale, is_signed) | |
c5aa993b JM |
1508 | unsigned short prev_inst; /* previous instruction */ |
1509 | unsigned short inst; /* current instruction */ | |
1510 | int nbits; /* number of bits in imm field */ | |
1511 | int scale; /* scale factor to be applied to imm */ | |
1512 | int is_signed; /* is the imm field signed? */ | |
c906108c SS |
1513 | { |
1514 | int offset; | |
1515 | ||
1516 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1517 | { | |
1518 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1519 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1520 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1521 | return offset | (inst & 0x1f); | |
1522 | } | |
1523 | else | |
1524 | { | |
1525 | int max_imm = 1 << nbits; | |
1526 | int mask = max_imm - 1; | |
1527 | int sign_bit = max_imm >> 1; | |
1528 | ||
1529 | offset = inst & mask; | |
1530 | if (is_signed && (offset & sign_bit)) | |
1531 | offset = 0 - (max_imm - offset); | |
1532 | return offset * scale; | |
1533 | } | |
1534 | } | |
1535 | ||
1536 | ||
1537 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1538 | stream from start_pc to limit_pc. */ | |
1539 | ||
1540 | static void | |
c5aa993b JM |
1541 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp) |
1542 | CORE_ADDR start_pc, limit_pc; | |
1543 | struct frame_info *next_frame; | |
1544 | CORE_ADDR sp; | |
c906108c SS |
1545 | { |
1546 | CORE_ADDR cur_pc; | |
1547 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1548 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1549 | unsigned inst = 0; /* current instruction */ | |
1550 | unsigned entry_inst = 0; /* the entry instruction */ | |
1551 | int reg, offset; | |
1552 | ||
c5aa993b JM |
1553 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1554 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1555 | |
1556 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1557 | { | |
1558 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1559 | the immediate offset extension from it in mips16_get_imm. */ | |
1560 | prev_inst = inst; | |
1561 | ||
1562 | /* Fetch and decode the instruction. */ | |
1563 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1564 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1565 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1566 | { | |
1567 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1568 | if (offset < 0) /* negative stack adjustment? */ |
1569 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1570 | else |
1571 | /* Exit loop if a positive stack adjustment is found, which | |
1572 | usually means that the stack cleanup code in the function | |
1573 | epilogue is reached. */ | |
1574 | break; | |
1575 | } | |
1576 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1577 | { | |
1578 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1579 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1580 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1581 | set_reg_offset (reg, sp + offset); |
1582 | } | |
1583 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1584 | { | |
1585 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1586 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1587 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1588 | set_reg_offset (reg, sp + offset); |
1589 | } | |
1590 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1591 | { | |
1592 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 1593 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1594 | set_reg_offset (RA_REGNUM, sp + offset); |
1595 | } | |
1596 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1597 | { | |
1598 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 1599 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1600 | set_reg_offset (RA_REGNUM, sp + offset); |
1601 | } | |
c5aa993b | 1602 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
1603 | { |
1604 | frame_addr = sp; | |
1605 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1606 | } | |
1607 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1608 | { | |
1609 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1610 | frame_addr = sp + offset; | |
1611 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1612 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
1613 | } | |
1614 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1615 | { | |
1616 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1617 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1618 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1619 | set_reg_offset (reg, frame_addr + offset); |
1620 | } | |
1621 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1622 | { | |
1623 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1624 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1625 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1626 | set_reg_offset (reg, frame_addr + offset); |
1627 | } | |
c5aa993b JM |
1628 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
1629 | entry_inst = inst; /* save for later processing */ | |
c906108c | 1630 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 1631 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
1632 | } |
1633 | ||
c5aa993b JM |
1634 | /* The entry instruction is typically the first instruction in a function, |
1635 | and it stores registers at offsets relative to the value of the old SP | |
1636 | (before the prologue). But the value of the sp parameter to this | |
1637 | function is the new SP (after the prologue has been executed). So we | |
1638 | can't calculate those offsets until we've seen the entire prologue, | |
1639 | and can calculate what the old SP must have been. */ | |
1640 | if (entry_inst != 0) | |
1641 | { | |
1642 | int areg_count = (entry_inst >> 8) & 7; | |
1643 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 1644 | |
c5aa993b JM |
1645 | /* The entry instruction always subtracts 32 from the SP. */ |
1646 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 1647 | |
c5aa993b JM |
1648 | /* Now we can calculate what the SP must have been at the |
1649 | start of the function prologue. */ | |
1650 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 1651 | |
c5aa993b JM |
1652 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
1653 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1654 | { | |
1655 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1656 | set_reg_offset (reg, sp + offset); | |
1657 | offset += MIPS_SAVED_REGSIZE; | |
1658 | } | |
c906108c | 1659 | |
c5aa993b JM |
1660 | /* Check if the ra register was pushed on the stack. */ |
1661 | offset = -4; | |
1662 | if (entry_inst & 0x20) | |
1663 | { | |
1664 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
1665 | set_reg_offset (RA_REGNUM, sp + offset); | |
1666 | offset -= MIPS_SAVED_REGSIZE; | |
1667 | } | |
c906108c | 1668 | |
c5aa993b JM |
1669 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
1670 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1671 | { | |
1672 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1673 | set_reg_offset (reg, sp + offset); | |
1674 | offset -= MIPS_SAVED_REGSIZE; | |
1675 | } | |
1676 | } | |
c906108c SS |
1677 | } |
1678 | ||
1679 | static void | |
c5aa993b JM |
1680 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp) |
1681 | CORE_ADDR start_pc, limit_pc; | |
1682 | struct frame_info *next_frame; | |
1683 | CORE_ADDR sp; | |
c906108c SS |
1684 | { |
1685 | CORE_ADDR cur_pc; | |
c5aa993b | 1686 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 1687 | restart: |
cce74817 | 1688 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 1689 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
1690 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
1691 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
1692 | { | |
1693 | unsigned long inst, high_word, low_word; | |
1694 | int reg; | |
1695 | ||
1696 | /* Fetch the instruction. */ | |
1697 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
1698 | ||
1699 | /* Save some code by pre-extracting some useful fields. */ | |
1700 | high_word = (inst >> 16) & 0xffff; | |
1701 | low_word = inst & 0xffff; | |
1702 | reg = high_word & 0x1f; | |
1703 | ||
c5aa993b | 1704 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
1705 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
1706 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1707 | { | |
1708 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 1709 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
1710 | else |
1711 | /* Exit loop if a positive stack adjustment is found, which | |
1712 | usually means that the stack cleanup code in the function | |
1713 | epilogue is reached. */ | |
1714 | break; | |
1715 | } | |
1716 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1717 | { | |
c5aa993b | 1718 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1719 | set_reg_offset (reg, sp + low_word); |
1720 | } | |
1721 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1722 | { | |
1723 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
1724 | but the register size used is only 32 bits. Make the address | |
1725 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 1726 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1727 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
1728 | } | |
c5aa993b | 1729 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
1730 | { |
1731 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
1732 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
1733 | frame_addr = sp + low_word; | |
c906108c SS |
1734 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
1735 | { | |
1736 | unsigned alloca_adjust; | |
1737 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1738 | frame_addr = read_next_frame_reg (next_frame, 30); |
1739 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
1740 | if (alloca_adjust > 0) |
1741 | { | |
1742 | /* FP > SP + frame_size. This may be because | |
1743 | * of an alloca or somethings similar. | |
1744 | * Fix sp to "pre-alloca" value, and try again. | |
1745 | */ | |
1746 | sp += alloca_adjust; | |
1747 | goto restart; | |
1748 | } | |
1749 | } | |
1750 | } | |
c5aa993b JM |
1751 | /* move $30,$sp. With different versions of gas this will be either |
1752 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1753 | Accept any one of these. */ | |
c906108c SS |
1754 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
1755 | { | |
1756 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1757 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
1758 | { | |
1759 | unsigned alloca_adjust; | |
1760 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1761 | frame_addr = read_next_frame_reg (next_frame, 30); |
1762 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
1763 | if (alloca_adjust > 0) |
1764 | { | |
1765 | /* FP > SP + frame_size. This may be because | |
1766 | * of an alloca or somethings similar. | |
1767 | * Fix sp to "pre-alloca" value, and try again. | |
1768 | */ | |
1769 | sp += alloca_adjust; | |
1770 | goto restart; | |
1771 | } | |
1772 | } | |
1773 | } | |
c5aa993b | 1774 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 1775 | { |
c5aa993b | 1776 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1777 | set_reg_offset (reg, frame_addr + low_word); |
1778 | } | |
1779 | } | |
1780 | } | |
1781 | ||
1782 | static mips_extra_func_info_t | |
c5aa993b JM |
1783 | heuristic_proc_desc (start_pc, limit_pc, next_frame) |
1784 | CORE_ADDR start_pc, limit_pc; | |
1785 | struct frame_info *next_frame; | |
c906108c SS |
1786 | { |
1787 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
1788 | ||
c5aa993b JM |
1789 | if (start_pc == 0) |
1790 | return NULL; | |
1791 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
cce74817 | 1792 | memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
1793 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
1794 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
1795 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
1796 | ||
1797 | if (start_pc + 200 < limit_pc) | |
1798 | limit_pc = start_pc + 200; | |
1799 | if (pc_is_mips16 (start_pc)) | |
1800 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1801 | else | |
1802 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1803 | return &temp_proc_desc; | |
1804 | } | |
1805 | ||
1806 | static mips_extra_func_info_t | |
1807 | non_heuristic_proc_desc (pc, addrptr) | |
1808 | CORE_ADDR pc; | |
1809 | CORE_ADDR *addrptr; | |
1810 | { | |
1811 | CORE_ADDR startaddr; | |
1812 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 1813 | struct block *b = block_for_pc (pc); |
c906108c SS |
1814 | struct symbol *sym; |
1815 | ||
1816 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
1817 | if (addrptr) | |
1818 | *addrptr = startaddr; | |
1819 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) | |
1820 | sym = NULL; | |
1821 | else | |
1822 | { | |
1823 | if (startaddr > BLOCK_START (b)) | |
1824 | /* This is the "pathological" case referred to in a comment in | |
1825 | print_frame_info. It might be better to move this check into | |
1826 | symbol reading. */ | |
1827 | sym = NULL; | |
1828 | else | |
1829 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); | |
1830 | } | |
1831 | ||
1832 | /* If we never found a PDR for this function in symbol reading, then | |
1833 | examine prologues to find the information. */ | |
1834 | if (sym) | |
1835 | { | |
1836 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
1837 | if (PROC_FRAME_REG (proc_desc) == -1) | |
1838 | return NULL; | |
1839 | else | |
1840 | return proc_desc; | |
1841 | } | |
1842 | else | |
1843 | return NULL; | |
1844 | } | |
1845 | ||
1846 | ||
1847 | static mips_extra_func_info_t | |
1848 | find_proc_desc (pc, next_frame) | |
1849 | CORE_ADDR pc; | |
1850 | struct frame_info *next_frame; | |
1851 | { | |
1852 | mips_extra_func_info_t proc_desc; | |
1853 | CORE_ADDR startaddr; | |
1854 | ||
1855 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1856 | ||
1857 | if (proc_desc) | |
1858 | { | |
1859 | /* IF this is the topmost frame AND | |
1860 | * (this proc does not have debugging information OR | |
1861 | * the PC is in the procedure prologue) | |
1862 | * THEN create a "heuristic" proc_desc (by analyzing | |
1863 | * the actual code) to replace the "official" proc_desc. | |
1864 | */ | |
1865 | if (next_frame == NULL) | |
1866 | { | |
1867 | struct symtab_and_line val; | |
1868 | struct symbol *proc_symbol = | |
c5aa993b | 1869 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
1870 | |
1871 | if (proc_symbol) | |
1872 | { | |
1873 | val = find_pc_line (BLOCK_START | |
c5aa993b | 1874 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
1875 | 0); |
1876 | val.pc = val.end ? val.end : pc; | |
1877 | } | |
1878 | if (!proc_symbol || pc < val.pc) | |
1879 | { | |
1880 | mips_extra_func_info_t found_heuristic = | |
c5aa993b JM |
1881 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
1882 | pc, next_frame); | |
c906108c SS |
1883 | if (found_heuristic) |
1884 | proc_desc = found_heuristic; | |
1885 | } | |
1886 | } | |
1887 | } | |
1888 | else | |
1889 | { | |
1890 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
1891 | by procedure call dummys. However, the procedures being called ought |
1892 | to have their own proc_descs, and even if they don't, | |
1893 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
1894 | |
1895 | register struct linked_proc_info *link; | |
1896 | ||
1897 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
1898 | if (PROC_LOW_ADDR (&link->info) <= pc |
1899 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
1900 | return &link->info; |
1901 | ||
1902 | if (startaddr == 0) | |
1903 | startaddr = heuristic_proc_start (pc); | |
1904 | ||
1905 | proc_desc = | |
1906 | heuristic_proc_desc (startaddr, pc, next_frame); | |
1907 | } | |
1908 | return proc_desc; | |
1909 | } | |
1910 | ||
1911 | static CORE_ADDR | |
c5aa993b JM |
1912 | get_frame_pointer (frame, proc_desc) |
1913 | struct frame_info *frame; | |
1914 | mips_extra_func_info_t proc_desc; | |
c906108c SS |
1915 | { |
1916 | return ADDR_BITS_REMOVE ( | |
c5aa993b JM |
1917 | read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) + |
1918 | PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
1919 | } |
1920 | ||
1921 | mips_extra_func_info_t cached_proc_desc; | |
1922 | ||
1923 | CORE_ADDR | |
c5aa993b JM |
1924 | mips_frame_chain (frame) |
1925 | struct frame_info *frame; | |
c906108c SS |
1926 | { |
1927 | mips_extra_func_info_t proc_desc; | |
1928 | CORE_ADDR tmp; | |
c5aa993b | 1929 | CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); |
c906108c SS |
1930 | |
1931 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
1932 | return 0; | |
1933 | ||
1934 | /* Check if the PC is inside a call stub. If it is, fetch the | |
1935 | PC of the caller of that stub. */ | |
1936 | if ((tmp = mips_skip_stub (saved_pc)) != 0) | |
1937 | saved_pc = tmp; | |
1938 | ||
1939 | /* Look up the procedure descriptor for this PC. */ | |
c5aa993b | 1940 | proc_desc = find_proc_desc (saved_pc, frame); |
c906108c SS |
1941 | if (!proc_desc) |
1942 | return 0; | |
1943 | ||
1944 | cached_proc_desc = proc_desc; | |
1945 | ||
1946 | /* If no frame pointer and frame size is zero, we must be at end | |
1947 | of stack (or otherwise hosed). If we don't check frame size, | |
1948 | we loop forever if we see a zero size frame. */ | |
1949 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
1950 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
c5aa993b JM |
1951 | /* The previous frame from a sigtramp frame might be frameless |
1952 | and have frame size zero. */ | |
c906108c SS |
1953 | && !frame->signal_handler_caller) |
1954 | return 0; | |
1955 | else | |
1956 | return get_frame_pointer (frame, proc_desc); | |
1957 | } | |
1958 | ||
1959 | void | |
c5aa993b | 1960 | mips_init_extra_frame_info (fromleaf, fci) |
cce74817 | 1961 | int fromleaf; |
c906108c SS |
1962 | struct frame_info *fci; |
1963 | { | |
1964 | int regnum; | |
1965 | ||
1966 | /* Use proc_desc calculated in frame_chain */ | |
1967 | mips_extra_func_info_t proc_desc = | |
c5aa993b | 1968 | fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next); |
c906108c | 1969 | |
cce74817 JM |
1970 | fci->extra_info = (struct frame_extra_info *) |
1971 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1972 | ||
c906108c | 1973 | fci->saved_regs = NULL; |
cce74817 | 1974 | fci->extra_info->proc_desc = |
c906108c SS |
1975 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
1976 | if (proc_desc) | |
1977 | { | |
1978 | /* Fixup frame-pointer - only needed for top frame */ | |
1979 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
1980 | Get the value of the frame relative sp, procedure might have been |
1981 | interrupted by a signal at it's very start. */ | |
c906108c SS |
1982 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
1983 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
1984 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
1985 | else | |
1986 | fci->frame = get_frame_pointer (fci->next, proc_desc); | |
1987 | ||
1988 | if (proc_desc == &temp_proc_desc) | |
1989 | { | |
1990 | char *name; | |
1991 | ||
1992 | /* Do not set the saved registers for a sigtramp frame, | |
1993 | mips_find_saved_registers will do that for us. | |
1994 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
1995 | find_pc_partial_function (fci->pc, &name, | |
c5aa993b | 1996 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
c906108c SS |
1997 | if (!IN_SIGTRAMP (fci->pc, name)) |
1998 | { | |
c5aa993b | 1999 | frame_saved_regs_zalloc (fci); |
cce74817 | 2000 | memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2001 | fci->saved_regs[PC_REGNUM] |
2002 | = fci->saved_regs[RA_REGNUM]; | |
2003 | } | |
2004 | } | |
2005 | ||
2006 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 JM |
2007 | /* assume we can't tell how many args for now */ |
2008 | fci->extra_info->num_args = -1; | |
c906108c SS |
2009 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2010 | { | |
c5aa993b | 2011 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2012 | { |
cce74817 | 2013 | fci->extra_info->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2014 | break; |
2015 | } | |
c5aa993b | 2016 | } |
c906108c SS |
2017 | } |
2018 | } | |
2019 | ||
2020 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2021 | we basically have to look at symbol information for the function | |
2022 | that we stopped in, which tells us *which* register (if any) is | |
2023 | the base of the frame pointer, and what offset from that register | |
2024 | the frame itself is at. | |
2025 | ||
2026 | This presents a problem when trying to examine a stack in memory | |
2027 | (that isn't executing at the moment), using the "frame" command. We | |
2028 | don't have a PC, nor do we have any registers except SP. | |
2029 | ||
2030 | This routine takes two arguments, SP and PC, and tries to make the | |
2031 | cached frames look as if these two arguments defined a frame on the | |
2032 | cache. This allows the rest of info frame to extract the important | |
2033 | arguments without difficulty. */ | |
2034 | ||
2035 | struct frame_info * | |
2036 | setup_arbitrary_frame (argc, argv) | |
2037 | int argc; | |
2038 | CORE_ADDR *argv; | |
2039 | { | |
2040 | if (argc != 2) | |
2041 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2042 | ||
2043 | return create_new_frame (argv[0], argv[1]); | |
2044 | } | |
2045 | ||
c906108c | 2046 | CORE_ADDR |
c5aa993b | 2047 | mips_push_arguments (nargs, args, sp, struct_return, struct_addr) |
c906108c SS |
2048 | int nargs; |
2049 | value_ptr *args; | |
2050 | CORE_ADDR sp; | |
2051 | int struct_return; | |
2052 | CORE_ADDR struct_addr; | |
2053 | { | |
2054 | int argreg; | |
2055 | int float_argreg; | |
2056 | int argnum; | |
2057 | int len = 0; | |
2058 | int stack_offset = 0; | |
2059 | ||
2060 | /* Macros to round N up or down to the next A boundary; A must be | |
2061 | a power of two. */ | |
2062 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2063 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
c5aa993b | 2064 | |
c906108c SS |
2065 | /* First ensure that the stack and structure return address (if any) |
2066 | are properly aligned. The stack has to be at least 64-bit aligned | |
2067 | even on 32-bit machines, because doubles must be 64-bit aligned. | |
2068 | On at least one MIPS variant, stack frames need to be 128-bit | |
2069 | aligned, so we round to this widest known alignment. */ | |
2070 | sp = ROUND_DOWN (sp, 16); | |
7a292a7a | 2071 | struct_addr = ROUND_DOWN (struct_addr, MIPS_SAVED_REGSIZE); |
c5aa993b | 2072 | |
c906108c SS |
2073 | /* Now make space on the stack for the args. We allocate more |
2074 | than necessary for EABI, because the first few arguments are | |
2075 | passed in registers, but that's OK. */ | |
2076 | for (argnum = 0; argnum < nargs; argnum++) | |
c5aa993b | 2077 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_SAVED_REGSIZE); |
c906108c SS |
2078 | sp -= ROUND_UP (len, 16); |
2079 | ||
2080 | /* Initialize the integer and float register pointers. */ | |
2081 | argreg = A0_REGNUM; | |
2082 | float_argreg = FPA0_REGNUM; | |
2083 | ||
2084 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
2085 | if (struct_return) | |
c5aa993b | 2086 | write_register (argreg++, struct_addr); |
c906108c SS |
2087 | |
2088 | /* Now load as many as possible of the first arguments into | |
2089 | registers, and push the rest onto the stack. Loop thru args | |
2090 | from first to last. */ | |
2091 | for (argnum = 0; argnum < nargs; argnum++) | |
2092 | { | |
2093 | char *val; | |
2094 | char valbuf[MAX_REGISTER_RAW_SIZE]; | |
2095 | value_ptr arg = args[argnum]; | |
2096 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
2097 | int len = TYPE_LENGTH (arg_type); | |
2098 | enum type_code typecode = TYPE_CODE (arg_type); | |
2099 | ||
2100 | /* The EABI passes structures that do not fit in a register by | |
c5aa993b | 2101 | reference. In all other cases, pass the structure by value. */ |
7a292a7a | 2102 | if (MIPS_EABI && len > MIPS_SAVED_REGSIZE && |
c906108c SS |
2103 | (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
2104 | { | |
7a292a7a | 2105 | store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2106 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2107 | len = MIPS_SAVED_REGSIZE; |
c906108c SS |
2108 | val = valbuf; |
2109 | } | |
2110 | else | |
c5aa993b | 2111 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2112 | |
2113 | /* 32-bit ABIs always start floating point arguments in an | |
2114 | even-numbered floating point register. */ | |
2115 | if (!FP_REGISTER_DOUBLE && typecode == TYPE_CODE_FLT | |
c5aa993b | 2116 | && (float_argreg & 1)) |
c906108c SS |
2117 | float_argreg++; |
2118 | ||
2119 | /* Floating point arguments passed in registers have to be | |
2120 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2121 | are passed in register pairs; the even register gets |
2122 | the low word, and the odd register gets the high word. | |
2123 | On non-EABI processors, the first two floating point arguments are | |
2124 | also copied to general registers, because MIPS16 functions | |
2125 | don't use float registers for arguments. This duplication of | |
2126 | arguments in general registers can't hurt non-MIPS16 functions | |
2127 | because those registers are normally skipped. */ | |
c906108c SS |
2128 | if (typecode == TYPE_CODE_FLT |
2129 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM | |
2130 | && MIPS_FPU_TYPE != MIPS_FPU_NONE) | |
2131 | { | |
2132 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2133 | { | |
2134 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; | |
2135 | unsigned long regval; | |
2136 | ||
2137 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2138 | regval = extract_unsigned_integer (val + low_offset, 4); |
c906108c SS |
2139 | write_register (float_argreg++, regval); |
2140 | if (!MIPS_EABI) | |
c5aa993b | 2141 | write_register (argreg + 1, regval); |
c906108c SS |
2142 | |
2143 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2144 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
c906108c SS |
2145 | write_register (float_argreg++, regval); |
2146 | if (!MIPS_EABI) | |
c5aa993b | 2147 | { |
c906108c SS |
2148 | write_register (argreg, regval); |
2149 | argreg += 2; | |
2150 | } | |
2151 | ||
2152 | } | |
2153 | else | |
2154 | { | |
2155 | /* This is a floating point value that fits entirely | |
2156 | in a single register. */ | |
53a5351d JM |
2157 | /* On 32 bit ABI's the float_argreg is further adjusted |
2158 | above to ensure that it is even register aligned. */ | |
c906108c SS |
2159 | CORE_ADDR regval = extract_address (val, len); |
2160 | write_register (float_argreg++, regval); | |
2161 | if (!MIPS_EABI) | |
c5aa993b | 2162 | { |
53a5351d JM |
2163 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
2164 | registers for each argument. The below is (my | |
2165 | guess) to ensure that the corresponding integer | |
2166 | register has reserved the same space. */ | |
c906108c SS |
2167 | write_register (argreg, regval); |
2168 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
2169 | } | |
2170 | } | |
2171 | } | |
2172 | else | |
2173 | { | |
2174 | /* Copy the argument to general registers or the stack in | |
2175 | register-sized pieces. Large arguments are split between | |
2176 | registers and stack. */ | |
2177 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2178 | are treated specially: Irix cc passes them in registers | |
2179 | where gcc sometimes puts them on the stack. For maximum | |
2180 | compatibility, we will put them in both places. */ | |
2181 | ||
c5aa993b | 2182 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2183 | (len % MIPS_SAVED_REGSIZE != 0)); |
c906108c SS |
2184 | while (len > 0) |
2185 | { | |
7a292a7a | 2186 | int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; |
c906108c SS |
2187 | |
2188 | if (argreg > MIPS_LAST_ARG_REGNUM || odd_sized_struct) | |
2189 | { | |
2190 | /* Write this portion of the argument to the stack. */ | |
2191 | /* Should shorter than int integer values be | |
2192 | promoted to int before being stored? */ | |
2193 | ||
2194 | int longword_offset = 0; | |
2195 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
7a292a7a | 2196 | { |
d929b26f | 2197 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2198 | (typecode == TYPE_CODE_INT || |
2199 | typecode == TYPE_CODE_PTR || | |
2200 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2201 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2202 | else if ((typecode == TYPE_CODE_STRUCT || |
2203 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2204 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2205 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2206 | } |
c5aa993b JM |
2207 | |
2208 | write_memory (sp + stack_offset + longword_offset, | |
c906108c SS |
2209 | val, partial_len); |
2210 | } | |
2211 | ||
2212 | /* Note!!! This is NOT an else clause. | |
c5aa993b | 2213 | Odd sized structs may go thru BOTH paths. */ |
c906108c SS |
2214 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
2215 | { | |
2216 | CORE_ADDR regval = extract_address (val, partial_len); | |
2217 | ||
2218 | /* A non-floating-point argument being passed in a | |
2219 | general register. If a struct or union, and if | |
2220 | the remaining length is smaller than the register | |
2221 | size, we have to adjust the register value on | |
2222 | big endian targets. | |
2223 | ||
2224 | It does not seem to be necessary to do the | |
2225 | same for integral types. | |
2226 | ||
2227 | Also don't do this adjustment on EABI and O64 | |
2228 | binaries. */ | |
2229 | ||
2230 | if (!MIPS_EABI | |
7a292a7a | 2231 | && MIPS_SAVED_REGSIZE < 8 |
c906108c | 2232 | && TARGET_BYTE_ORDER == BIG_ENDIAN |
7a292a7a | 2233 | && partial_len < MIPS_SAVED_REGSIZE |
c906108c SS |
2234 | && (typecode == TYPE_CODE_STRUCT || |
2235 | typecode == TYPE_CODE_UNION)) | |
c5aa993b | 2236 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * |
c906108c SS |
2237 | TARGET_CHAR_BIT); |
2238 | ||
2239 | write_register (argreg, regval); | |
2240 | argreg++; | |
c5aa993b | 2241 | |
c906108c SS |
2242 | /* If this is the old ABI, prevent subsequent floating |
2243 | point arguments from being passed in floating point | |
2244 | registers. */ | |
2245 | if (!MIPS_EABI) | |
2246 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
2247 | } | |
c5aa993b | 2248 | |
c906108c SS |
2249 | len -= partial_len; |
2250 | val += partial_len; | |
2251 | ||
2252 | /* The offset onto the stack at which we will start | |
c5aa993b JM |
2253 | copying parameters (after the registers are used up) |
2254 | begins at (4 * MIPS_REGSIZE) in the old ABI. This | |
2255 | leaves room for the "home" area for register parameters. | |
c906108c | 2256 | |
c5aa993b JM |
2257 | In the new EABI (and the NABI32), the 8 register parameters |
2258 | do not have "home" stack space reserved for them, so the | |
2259 | stack offset does not get incremented until after | |
2260 | we have used up the 8 parameter registers. */ | |
c906108c | 2261 | |
d929b26f AC |
2262 | if (MIPS_REGS_HAVE_HOME_P || argnum >= 8) |
2263 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
c906108c SS |
2264 | } |
2265 | } | |
2266 | } | |
2267 | ||
0f71a2f6 JM |
2268 | /* Return adjusted stack pointer. */ |
2269 | return sp; | |
2270 | } | |
2271 | ||
2272 | CORE_ADDR | |
2273 | mips_push_return_address (pc, sp) | |
2274 | CORE_ADDR pc; | |
2275 | CORE_ADDR sp; | |
2276 | { | |
c906108c SS |
2277 | /* Set the return address register to point to the entry |
2278 | point of the program, where a breakpoint lies in wait. */ | |
c5aa993b | 2279 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); |
c906108c SS |
2280 | return sp; |
2281 | } | |
2282 | ||
2283 | static void | |
c5aa993b | 2284 | mips_push_register (CORE_ADDR * sp, int regno) |
c906108c SS |
2285 | { |
2286 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
7a292a7a SS |
2287 | int regsize; |
2288 | int offset; | |
2289 | if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) | |
2290 | { | |
2291 | regsize = MIPS_SAVED_REGSIZE; | |
2292 | offset = (TARGET_BYTE_ORDER == BIG_ENDIAN | |
2293 | ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE | |
2294 | : 0); | |
2295 | } | |
2296 | else | |
2297 | { | |
2298 | regsize = REGISTER_RAW_SIZE (regno); | |
2299 | offset = 0; | |
2300 | } | |
c906108c SS |
2301 | *sp -= regsize; |
2302 | read_register_gen (regno, buffer); | |
7a292a7a | 2303 | write_memory (*sp, buffer + offset, regsize); |
c906108c SS |
2304 | } |
2305 | ||
2306 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
2307 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) | |
2308 | ||
2309 | void | |
7a292a7a | 2310 | mips_push_dummy_frame () |
c906108c SS |
2311 | { |
2312 | int ireg; | |
c5aa993b JM |
2313 | struct linked_proc_info *link = (struct linked_proc_info *) |
2314 | xmalloc (sizeof (struct linked_proc_info)); | |
c906108c SS |
2315 | mips_extra_func_info_t proc_desc = &link->info; |
2316 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM)); | |
2317 | CORE_ADDR old_sp = sp; | |
2318 | link->next = linked_proc_desc_table; | |
2319 | linked_proc_desc_table = link; | |
2320 | ||
2321 | /* FIXME! are these correct ? */ | |
c5aa993b | 2322 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
c906108c SS |
2323 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
2324 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
2325 | #define FLOAT_SINGLE_REG_SAVE_MASK \ | |
2326 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
2327 | /* | |
2328 | * The registers we must save are all those not preserved across | |
2329 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
2330 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI | |
2331 | * and FP Control/Status registers. | |
2332 | * | |
2333 | * | |
2334 | * Dummy frame layout: | |
2335 | * (high memory) | |
c5aa993b JM |
2336 | * Saved PC |
2337 | * Saved MMHI, MMLO, FPC_CSR | |
2338 | * Saved R31 | |
2339 | * Saved R28 | |
2340 | * ... | |
2341 | * Saved R1 | |
c906108c SS |
2342 | * Saved D18 (i.e. F19, F18) |
2343 | * ... | |
2344 | * Saved D0 (i.e. F1, F0) | |
c5aa993b | 2345 | * Argument build area and stack arguments written via mips_push_arguments |
c906108c SS |
2346 | * (low memory) |
2347 | */ | |
2348 | ||
2349 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
c5aa993b JM |
2350 | PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; |
2351 | PROC_FRAME_OFFSET (proc_desc) = 0; | |
2352 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
c906108c SS |
2353 | mips_push_register (&sp, PC_REGNUM); |
2354 | mips_push_register (&sp, HI_REGNUM); | |
2355 | mips_push_register (&sp, LO_REGNUM); | |
2356 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
2357 | ||
2358 | /* Save general CPU registers */ | |
c5aa993b | 2359 | PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; |
c906108c | 2360 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
c5aa993b JM |
2361 | PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; |
2362 | for (ireg = 32; --ireg >= 0;) | |
2363 | if (PROC_REG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2364 | mips_push_register (&sp, ireg); |
2365 | ||
2366 | /* Save floating point registers starting with high order word */ | |
c5aa993b | 2367 | PROC_FREG_MASK (proc_desc) = |
c906108c SS |
2368 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
2369 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
2370 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register | |
2371 | from FP. */ | |
c5aa993b JM |
2372 | PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; |
2373 | for (ireg = 32; --ireg >= 0;) | |
2374 | if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2375 | mips_push_register (&sp, ireg + FP0_REGNUM); |
2376 | ||
2377 | /* Update the frame pointer for the call dummy and the stack pointer. | |
2378 | Set the procedure's starting and ending addresses to point to the | |
2379 | call dummy address at the entry point. */ | |
2380 | write_register (PUSH_FP_REGNUM, old_sp); | |
2381 | write_register (SP_REGNUM, sp); | |
c5aa993b JM |
2382 | PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); |
2383 | PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; | |
2384 | SET_PROC_DESC_IS_DUMMY (proc_desc); | |
2385 | PROC_PC_REG (proc_desc) = RA_REGNUM; | |
c906108c SS |
2386 | } |
2387 | ||
2388 | void | |
c5aa993b | 2389 | mips_pop_frame () |
c906108c SS |
2390 | { |
2391 | register int regnum; | |
2392 | struct frame_info *frame = get_current_frame (); | |
2393 | CORE_ADDR new_sp = FRAME_FP (frame); | |
2394 | ||
cce74817 | 2395 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c | 2396 | |
c5aa993b | 2397 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
c906108c SS |
2398 | if (frame->saved_regs == NULL) |
2399 | mips_find_saved_regs (frame); | |
2400 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
2401 | { | |
2402 | if (regnum != SP_REGNUM && regnum != PC_REGNUM | |
2403 | && frame->saved_regs[regnum]) | |
2404 | write_register (regnum, | |
2405 | read_memory_integer (frame->saved_regs[regnum], | |
c5aa993b | 2406 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2407 | } |
2408 | write_register (SP_REGNUM, new_sp); | |
2409 | flush_cached_frames (); | |
2410 | ||
c5aa993b | 2411 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
2412 | { |
2413 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
2414 | ||
2415 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
2416 | pi_ptr != NULL; | |
2417 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
2418 | { | |
2419 | if (&pi_ptr->info == proc_desc) | |
2420 | break; | |
2421 | } | |
2422 | ||
2423 | if (pi_ptr == NULL) | |
2424 | error ("Can't locate dummy extra frame info\n"); | |
2425 | ||
2426 | if (prev_ptr != NULL) | |
2427 | prev_ptr->next = pi_ptr->next; | |
2428 | else | |
2429 | linked_proc_desc_table = pi_ptr->next; | |
2430 | ||
2431 | free (pi_ptr); | |
2432 | ||
2433 | write_register (HI_REGNUM, | |
c5aa993b | 2434 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2435 | MIPS_SAVED_REGSIZE)); |
c906108c | 2436 | write_register (LO_REGNUM, |
c5aa993b | 2437 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2438 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2439 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
2440 | write_register (FCRCS_REGNUM, | |
c5aa993b | 2441 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2442 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2443 | } |
2444 | } | |
2445 | ||
2446 | static void | |
2447 | mips_print_register (regnum, all) | |
2448 | int regnum, all; | |
2449 | { | |
2450 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2451 | ||
2452 | /* Get the data in raw format. */ | |
2453 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
2454 | { | |
2455 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); | |
2456 | return; | |
2457 | } | |
2458 | ||
2459 | /* If an even floating point register, also print as double. */ | |
2460 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT | |
c5aa993b JM |
2461 | && !((regnum - FP0_REGNUM) & 1)) |
2462 | if (REGISTER_RAW_SIZE (regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */ | |
c906108c | 2463 | { |
c5aa993b | 2464 | char dbuffer[2 * MAX_REGISTER_RAW_SIZE]; |
c906108c SS |
2465 | |
2466 | read_relative_register_raw_bytes (regnum, dbuffer); | |
c5aa993b | 2467 | read_relative_register_raw_bytes (regnum + 1, dbuffer + MIPS_REGSIZE); |
c906108c SS |
2468 | REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer); |
2469 | ||
c5aa993b | 2470 | printf_filtered ("(d%d: ", regnum - FP0_REGNUM); |
c906108c SS |
2471 | val_print (builtin_type_double, dbuffer, 0, 0, |
2472 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2473 | printf_filtered ("); "); | |
2474 | } | |
2475 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
2476 | ||
2477 | /* The problem with printing numeric register names (r26, etc.) is that | |
2478 | the user can't use them on input. Probably the best solution is to | |
2479 | fix it so that either the numeric or the funky (a2, etc.) names | |
2480 | are accepted on input. */ | |
2481 | if (regnum < MIPS_NUMREGS) | |
2482 | printf_filtered ("(r%d): ", regnum); | |
2483 | else | |
2484 | printf_filtered (": "); | |
2485 | ||
2486 | /* If virtual format is floating, print it that way. */ | |
2487 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
2488 | if (FP_REGISTER_DOUBLE) | |
c5aa993b | 2489 | { /* show 8-byte floats as float AND double: */ |
c906108c SS |
2490 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
2491 | ||
2492 | printf_filtered (" (float) "); | |
2493 | val_print (builtin_type_float, raw_buffer + offset, 0, 0, | |
2494 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2495 | printf_filtered (", (double) "); | |
2496 | val_print (builtin_type_double, raw_buffer, 0, 0, | |
2497 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2498 | } | |
2499 | else | |
2500 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
2501 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2502 | /* Else print as integer in hex. */ | |
2503 | else | |
ed9a39eb JM |
2504 | { |
2505 | int offset; | |
2506 | ||
2507 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2508 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); | |
2509 | else | |
2510 | offset = 0; | |
2511 | ||
2512 | print_scalar_formatted (raw_buffer + offset, | |
2513 | REGISTER_VIRTUAL_TYPE (regnum), | |
2514 | 'x', 0, gdb_stdout); | |
2515 | } | |
c906108c SS |
2516 | } |
2517 | ||
2518 | /* Replacement for generic do_registers_info. | |
2519 | Print regs in pretty columns. */ | |
2520 | ||
2521 | static int | |
2522 | do_fp_register_row (regnum) | |
2523 | int regnum; | |
c5aa993b | 2524 | { /* do values for FP (float) regs */ |
c906108c SS |
2525 | char *raw_buffer[2]; |
2526 | char *dbl_buffer; | |
2527 | /* use HI and LO to control the order of combining two flt regs */ | |
2528 | int HI = (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
2529 | int LO = (TARGET_BYTE_ORDER != BIG_ENDIAN); | |
2530 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ | |
2531 | int inv1, inv2, inv3; | |
c5aa993b | 2532 | |
c906108c SS |
2533 | raw_buffer[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); |
2534 | raw_buffer[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2535 | dbl_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2536 | ||
2537 | /* Get the data in raw format. */ | |
2538 | if (read_relative_register_raw_bytes (regnum, raw_buffer[HI])) | |
2539 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
c5aa993b | 2540 | if (REGISTER_RAW_SIZE (regnum) == 4) |
c906108c SS |
2541 | { |
2542 | /* 4-byte registers: we can fit two registers per row. */ | |
2543 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
2544 | if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO])) | |
c5aa993b | 2545 | error ("can't read register %d (%s)", |
c906108c SS |
2546 | regnum + 1, REGISTER_NAME (regnum + 1)); |
2547 | ||
2548 | /* copy the two floats into one double, and unpack both */ | |
65edb64b | 2549 | memcpy (dbl_buffer, raw_buffer, 2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c5aa993b JM |
2550 | flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1); |
2551 | flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2); | |
2552 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); | |
2553 | ||
2554 | printf_filtered (inv1 ? " %-5s: <invalid float>" : | |
2555 | " %-5s%-17.9g", REGISTER_NAME (regnum), flt1); | |
2556 | printf_filtered (inv2 ? " %-5s: <invalid float>" : | |
c906108c | 2557 | " %-5s%-17.9g", REGISTER_NAME (regnum + 1), flt2); |
c5aa993b | 2558 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : |
c906108c SS |
2559 | " dbl: %-24.17g\n", doub); |
2560 | /* may want to do hex display here (future enhancement) */ | |
c5aa993b | 2561 | regnum += 2; |
c906108c SS |
2562 | } |
2563 | else | |
c5aa993b | 2564 | { /* eight byte registers: print each one as float AND as double. */ |
c906108c SS |
2565 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
2566 | ||
65edb64b | 2567 | memcpy (dbl_buffer, raw_buffer[HI], 2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c5aa993b | 2568 | flt1 = unpack_double (builtin_type_float, |
c906108c | 2569 | &raw_buffer[HI][offset], &inv1); |
c5aa993b | 2570 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); |
c906108c | 2571 | |
c5aa993b | 2572 | printf_filtered (inv1 ? " %-5s: <invalid float>" : |
c906108c | 2573 | " %-5s flt: %-17.9g", REGISTER_NAME (regnum), flt1); |
c5aa993b | 2574 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : |
c906108c SS |
2575 | " dbl: %-24.17g\n", doub); |
2576 | /* may want to do hex display here (future enhancement) */ | |
2577 | regnum++; | |
2578 | } | |
2579 | return regnum; | |
2580 | } | |
2581 | ||
2582 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
2583 | ||
2584 | static int | |
2585 | do_gp_register_row (regnum) | |
2586 | int regnum; | |
2587 | { | |
2588 | /* do values for GP (int) regs */ | |
2589 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2590 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ | |
2591 | int col, byte; | |
2592 | int start_regnum = regnum; | |
2593 | int numregs = NUM_REGS; | |
2594 | ||
2595 | ||
2596 | /* For GP registers, we print a separate row of names above the vals */ | |
2597 | printf_filtered (" "); | |
2598 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
2599 | { | |
2600 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 2601 | continue; /* unused register */ |
c906108c | 2602 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b JM |
2603 | break; /* end the row: reached FP register */ |
2604 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
c906108c SS |
2605 | REGISTER_NAME (regnum)); |
2606 | col++; | |
2607 | } | |
c5aa993b | 2608 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", |
c906108c SS |
2609 | start_regnum); /* print the R0 to R31 names */ |
2610 | ||
2611 | regnum = start_regnum; /* go back to start of row */ | |
2612 | /* now print the values in hex, 4 or 8 to the row */ | |
2613 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
2614 | { | |
2615 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 2616 | continue; /* unused register */ |
c906108c | 2617 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 2618 | break; /* end row: reached FP register */ |
c906108c SS |
2619 | /* OK: get the data in raw format. */ |
2620 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
2621 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
2622 | /* pad small registers */ | |
43e526b9 | 2623 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
2624 | printf_filtered (" "); |
2625 | /* Now print the register value in hex, endian order. */ | |
2626 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
43e526b9 JM |
2627 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
2628 | byte < REGISTER_RAW_SIZE (regnum); | |
2629 | byte++) | |
c906108c SS |
2630 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
2631 | else | |
43e526b9 JM |
2632 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
2633 | byte >= 0; | |
2634 | byte--) | |
c906108c SS |
2635 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
2636 | printf_filtered (" "); | |
2637 | col++; | |
2638 | } | |
c5aa993b | 2639 | if (col > 0) /* ie. if we actually printed anything... */ |
c906108c SS |
2640 | printf_filtered ("\n"); |
2641 | ||
2642 | return regnum; | |
2643 | } | |
2644 | ||
2645 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
2646 | ||
2647 | void | |
2648 | mips_do_registers_info (regnum, fpregs) | |
2649 | int regnum; | |
2650 | int fpregs; | |
2651 | { | |
c5aa993b | 2652 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
2653 | { |
2654 | if (*(REGISTER_NAME (regnum)) == '\0') | |
2655 | error ("Not a valid register for the current processor type"); | |
2656 | ||
2657 | mips_print_register (regnum, 0); | |
2658 | printf_filtered ("\n"); | |
2659 | } | |
c5aa993b JM |
2660 | else |
2661 | /* do all (or most) registers */ | |
c906108c SS |
2662 | { |
2663 | regnum = 0; | |
2664 | while (regnum < NUM_REGS) | |
2665 | { | |
c5aa993b JM |
2666 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
2667 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
c906108c SS |
2668 | regnum = do_fp_register_row (regnum); /* FP regs */ |
2669 | else | |
2670 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
2671 | else | |
2672 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ | |
2673 | } | |
2674 | } | |
2675 | } | |
2676 | ||
2677 | /* Return number of args passed to a frame. described by FIP. | |
2678 | Can return -1, meaning no way to tell. */ | |
2679 | ||
2680 | int | |
2681 | mips_frame_num_args (frame) | |
c5aa993b | 2682 | struct frame_info *frame; |
c906108c | 2683 | { |
c5aa993b | 2684 | #if 0 /* FIXME Use or lose this! */ |
c906108c SS |
2685 | struct chain_info_t *p; |
2686 | ||
2687 | p = mips_find_cached_frame (FRAME_FP (frame)); | |
2688 | if (p->valid) | |
2689 | return p->the_info.numargs; | |
2690 | #endif | |
2691 | return -1; | |
2692 | } | |
2693 | ||
2694 | /* Is this a branch with a delay slot? */ | |
2695 | ||
a14ed312 | 2696 | static int is_delayed (unsigned long); |
c906108c SS |
2697 | |
2698 | static int | |
2699 | is_delayed (insn) | |
2700 | unsigned long insn; | |
2701 | { | |
2702 | int i; | |
2703 | for (i = 0; i < NUMOPCODES; ++i) | |
2704 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
2705 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
2706 | break; | |
2707 | return (i < NUMOPCODES | |
2708 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2709 | | INSN_COND_BRANCH_DELAY | |
2710 | | INSN_COND_BRANCH_LIKELY))); | |
2711 | } | |
2712 | ||
2713 | int | |
2714 | mips_step_skips_delay (pc) | |
2715 | CORE_ADDR pc; | |
2716 | { | |
2717 | char buf[MIPS_INSTLEN]; | |
2718 | ||
2719 | /* There is no branch delay slot on MIPS16. */ | |
2720 | if (pc_is_mips16 (pc)) | |
2721 | return 0; | |
2722 | ||
2723 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
2724 | /* If error reading memory, guess that it is not a delayed branch. */ | |
2725 | return 0; | |
c5aa993b | 2726 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
2727 | } |
2728 | ||
2729 | ||
2730 | /* Skip the PC past function prologue instructions (32-bit version). | |
2731 | This is a helper function for mips_skip_prologue. */ | |
2732 | ||
2733 | static CORE_ADDR | |
2734 | mips32_skip_prologue (pc, lenient) | |
c5aa993b | 2735 | CORE_ADDR pc; /* starting PC to search from */ |
c906108c SS |
2736 | int lenient; |
2737 | { | |
c5aa993b JM |
2738 | t_inst inst; |
2739 | CORE_ADDR end_pc; | |
2740 | int seen_sp_adjust = 0; | |
2741 | int load_immediate_bytes = 0; | |
2742 | ||
2743 | /* Skip the typical prologue instructions. These are the stack adjustment | |
2744 | instruction and the instructions that save registers on the stack | |
2745 | or in the gcc frame. */ | |
2746 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
2747 | { | |
2748 | unsigned long high_word; | |
c906108c | 2749 | |
c5aa993b JM |
2750 | inst = mips_fetch_instruction (pc); |
2751 | high_word = (inst >> 16) & 0xffff; | |
c906108c SS |
2752 | |
2753 | #if 0 | |
c5aa993b JM |
2754 | if (lenient && is_delayed (inst)) |
2755 | continue; | |
c906108c SS |
2756 | #endif |
2757 | ||
c5aa993b JM |
2758 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
2759 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
2760 | seen_sp_adjust = 1; | |
2761 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
2762 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
2763 | seen_sp_adjust = 1; | |
2764 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
2765 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
2766 | && (inst & 0x001F0000)) /* reg != $zero */ | |
2767 | continue; | |
2768 | ||
2769 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
2770 | continue; | |
2771 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
2772 | /* sx reg,n($s8) */ | |
2773 | continue; /* reg != $zero */ | |
2774 | ||
2775 | /* move $s8,$sp. With different versions of gas this will be either | |
2776 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
2777 | Accept any one of these. */ | |
2778 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2779 | continue; | |
2780 | ||
2781 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
2782 | continue; | |
2783 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
2784 | continue; | |
2785 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
2786 | continue; | |
2787 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2788 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
2789 | continue; | |
2790 | /* The following instructions load $at or $t0 with an immediate | |
2791 | value in preparation for a stack adjustment via | |
2792 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
2793 | a local variable, so we accept them only before a stack adjustment | |
2794 | instruction was seen. */ | |
2795 | else if (!seen_sp_adjust) | |
2796 | { | |
2797 | if (high_word == 0x3c01 || /* lui $at,n */ | |
2798 | high_word == 0x3c08) /* lui $t0,n */ | |
2799 | { | |
2800 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
2801 | continue; | |
2802 | } | |
2803 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
2804 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
2805 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
2806 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
2807 | { | |
2808 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
2809 | continue; | |
2810 | } | |
2811 | else | |
2812 | break; | |
2813 | } | |
2814 | else | |
2815 | break; | |
c906108c SS |
2816 | } |
2817 | ||
c5aa993b JM |
2818 | /* In a frameless function, we might have incorrectly |
2819 | skipped some load immediate instructions. Undo the skipping | |
2820 | if the load immediate was not followed by a stack adjustment. */ | |
2821 | if (load_immediate_bytes && !seen_sp_adjust) | |
2822 | pc -= load_immediate_bytes; | |
2823 | return pc; | |
c906108c SS |
2824 | } |
2825 | ||
2826 | /* Skip the PC past function prologue instructions (16-bit version). | |
2827 | This is a helper function for mips_skip_prologue. */ | |
2828 | ||
2829 | static CORE_ADDR | |
2830 | mips16_skip_prologue (pc, lenient) | |
c5aa993b | 2831 | CORE_ADDR pc; /* starting PC to search from */ |
c906108c SS |
2832 | int lenient; |
2833 | { | |
c5aa993b JM |
2834 | CORE_ADDR end_pc; |
2835 | int extend_bytes = 0; | |
2836 | int prev_extend_bytes; | |
c906108c | 2837 | |
c5aa993b JM |
2838 | /* Table of instructions likely to be found in a function prologue. */ |
2839 | static struct | |
c906108c SS |
2840 | { |
2841 | unsigned short inst; | |
2842 | unsigned short mask; | |
c5aa993b JM |
2843 | } |
2844 | table[] = | |
2845 | { | |
c906108c | 2846 | { |
c5aa993b JM |
2847 | 0x6300, 0xff00 |
2848 | } | |
2849 | , /* addiu $sp,offset */ | |
2850 | { | |
2851 | 0xfb00, 0xff00 | |
2852 | } | |
2853 | , /* daddiu $sp,offset */ | |
2854 | { | |
2855 | 0xd000, 0xf800 | |
2856 | } | |
2857 | , /* sw reg,n($sp) */ | |
2858 | { | |
2859 | 0xf900, 0xff00 | |
2860 | } | |
2861 | , /* sd reg,n($sp) */ | |
2862 | { | |
2863 | 0x6200, 0xff00 | |
2864 | } | |
2865 | , /* sw $ra,n($sp) */ | |
2866 | { | |
2867 | 0xfa00, 0xff00 | |
2868 | } | |
2869 | , /* sd $ra,n($sp) */ | |
2870 | { | |
2871 | 0x673d, 0xffff | |
2872 | } | |
2873 | , /* move $s1,sp */ | |
2874 | { | |
2875 | 0xd980, 0xff80 | |
2876 | } | |
2877 | , /* sw $a0-$a3,n($s1) */ | |
2878 | { | |
2879 | 0x6704, 0xff1c | |
2880 | } | |
2881 | , /* move reg,$a0-$a3 */ | |
2882 | { | |
2883 | 0xe809, 0xf81f | |
2884 | } | |
2885 | , /* entry pseudo-op */ | |
2886 | { | |
2887 | 0x0100, 0xff00 | |
2888 | } | |
2889 | , /* addiu $s1,$sp,n */ | |
2890 | { | |
2891 | 0, 0 | |
2892 | } /* end of table marker */ | |
2893 | }; | |
2894 | ||
2895 | /* Skip the typical prologue instructions. These are the stack adjustment | |
2896 | instruction and the instructions that save registers on the stack | |
2897 | or in the gcc frame. */ | |
2898 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
2899 | { | |
2900 | unsigned short inst; | |
2901 | int i; | |
c906108c | 2902 | |
c5aa993b | 2903 | inst = mips_fetch_instruction (pc); |
c906108c | 2904 | |
c5aa993b JM |
2905 | /* Normally we ignore an extend instruction. However, if it is |
2906 | not followed by a valid prologue instruction, we must adjust | |
2907 | the pc back over the extend so that it won't be considered | |
2908 | part of the prologue. */ | |
2909 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2910 | { | |
2911 | extend_bytes = MIPS16_INSTLEN; | |
2912 | continue; | |
2913 | } | |
2914 | prev_extend_bytes = extend_bytes; | |
2915 | extend_bytes = 0; | |
c906108c | 2916 | |
c5aa993b JM |
2917 | /* Check for other valid prologue instructions besides extend. */ |
2918 | for (i = 0; table[i].mask != 0; i++) | |
2919 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
2920 | break; | |
2921 | if (table[i].mask != 0) /* it was in table? */ | |
2922 | continue; /* ignore it */ | |
2923 | else | |
2924 | /* non-prologue */ | |
2925 | { | |
2926 | /* Return the current pc, adjusted backwards by 2 if | |
2927 | the previous instruction was an extend. */ | |
2928 | return pc - prev_extend_bytes; | |
2929 | } | |
c906108c SS |
2930 | } |
2931 | return pc; | |
2932 | } | |
2933 | ||
2934 | /* To skip prologues, I use this predicate. Returns either PC itself | |
2935 | if the code at PC does not look like a function prologue; otherwise | |
2936 | returns an address that (if we're lucky) follows the prologue. If | |
2937 | LENIENT, then we must skip everything which is involved in setting | |
2938 | up the frame (it's OK to skip more, just so long as we don't skip | |
2939 | anything which might clobber the registers which are being saved. | |
2940 | We must skip more in the case where part of the prologue is in the | |
2941 | delay slot of a non-prologue instruction). */ | |
2942 | ||
2943 | CORE_ADDR | |
2944 | mips_skip_prologue (pc, lenient) | |
2945 | CORE_ADDR pc; | |
2946 | int lenient; | |
2947 | { | |
2948 | /* See if we can determine the end of the prologue via the symbol table. | |
2949 | If so, then return either PC, or the PC after the prologue, whichever | |
2950 | is greater. */ | |
2951 | ||
2952 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
2953 | ||
2954 | if (post_prologue_pc != 0) | |
2955 | return max (pc, post_prologue_pc); | |
2956 | ||
2957 | /* Can't determine prologue from the symbol table, need to examine | |
2958 | instructions. */ | |
2959 | ||
2960 | if (pc_is_mips16 (pc)) | |
2961 | return mips16_skip_prologue (pc, lenient); | |
2962 | else | |
2963 | return mips32_skip_prologue (pc, lenient); | |
2964 | } | |
2965 | ||
2966 | #if 0 | |
2967 | /* The lenient prologue stuff should be superseded by the code in | |
2968 | init_extra_frame_info which looks to see whether the stores mentioned | |
2969 | in the proc_desc have actually taken place. */ | |
2970 | ||
2971 | /* Is address PC in the prologue (loosely defined) for function at | |
2972 | STARTADDR? */ | |
2973 | ||
2974 | static int | |
2975 | mips_in_lenient_prologue (startaddr, pc) | |
2976 | CORE_ADDR startaddr; | |
2977 | CORE_ADDR pc; | |
2978 | { | |
2979 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
2980 | return pc >= startaddr && pc < end_prologue; | |
2981 | } | |
2982 | #endif | |
2983 | ||
7a292a7a SS |
2984 | /* Determine how a return value is stored within the MIPS register |
2985 | file, given the return type `valtype'. */ | |
2986 | ||
2987 | struct return_value_word | |
2988 | { | |
2989 | int len; | |
2990 | int reg; | |
2991 | int reg_offset; | |
2992 | int buf_offset; | |
2993 | }; | |
2994 | ||
a14ed312 KB |
2995 | static void return_value_location (struct type *, struct return_value_word *, |
2996 | struct return_value_word *); | |
7a292a7a SS |
2997 | |
2998 | static void | |
2999 | return_value_location (valtype, hi, lo) | |
3000 | struct type *valtype; | |
3001 | struct return_value_word *hi; | |
3002 | struct return_value_word *lo; | |
3003 | { | |
3004 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 3005 | |
7a292a7a SS |
3006 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
3007 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
3008 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
3009 | { | |
3010 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3011 | { | |
3012 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 3013 | spread them across a floating-point register pair. */ |
7a292a7a SS |
3014 | lo->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; |
3015 | hi->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 0 : 4; | |
3016 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN | |
3017 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) | |
3018 | ? 4 : 0); | |
3019 | hi->reg_offset = lo->reg_offset; | |
3020 | lo->reg = FP0_REGNUM + 0; | |
3021 | hi->reg = FP0_REGNUM + 1; | |
3022 | lo->len = 4; | |
3023 | hi->len = 4; | |
3024 | } | |
3025 | else | |
3026 | { | |
3027 | /* The floating point value fits in a single floating-point | |
c5aa993b | 3028 | register. */ |
7a292a7a SS |
3029 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN |
3030 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 | |
3031 | && len == 4) | |
3032 | ? 4 : 0); | |
3033 | lo->reg = FP0_REGNUM; | |
3034 | lo->len = len; | |
3035 | lo->buf_offset = 0; | |
3036 | hi->len = 0; | |
3037 | hi->reg_offset = 0; | |
3038 | hi->buf_offset = 0; | |
3039 | hi->reg = 0; | |
3040 | } | |
3041 | } | |
3042 | else | |
3043 | { | |
3044 | /* Locate a result possibly spread across two registers. */ | |
3045 | int regnum = 2; | |
3046 | lo->reg = regnum + 0; | |
3047 | hi->reg = regnum + 1; | |
3048 | if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3049 | && len < MIPS_SAVED_REGSIZE) | |
3050 | { | |
3051 | /* "un-left-justify" the value in the low register */ | |
3052 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
3053 | lo->len = len; | |
3054 | hi->reg_offset = 0; | |
3055 | hi->len = 0; | |
3056 | } | |
3057 | else if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3058 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ | |
3059 | && len < MIPS_SAVED_REGSIZE * 2 | |
3060 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
3061 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3062 | { | |
3063 | /* "un-left-justify" the value spread across two registers. */ | |
3064 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
3065 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
3066 | hi->reg_offset = 0; | |
3067 | hi->len = len - lo->len; | |
3068 | } | |
3069 | else | |
3070 | { | |
3071 | /* Only perform a partial copy of the second register. */ | |
3072 | lo->reg_offset = 0; | |
3073 | hi->reg_offset = 0; | |
3074 | if (len > MIPS_SAVED_REGSIZE) | |
3075 | { | |
3076 | lo->len = MIPS_SAVED_REGSIZE; | |
3077 | hi->len = len - MIPS_SAVED_REGSIZE; | |
3078 | } | |
3079 | else | |
3080 | { | |
3081 | lo->len = len; | |
3082 | hi->len = 0; | |
3083 | } | |
3084 | } | |
3085 | if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3086 | && REGISTER_RAW_SIZE (regnum) == 8 | |
3087 | && MIPS_SAVED_REGSIZE == 4) | |
3088 | { | |
3089 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 3090 | of the register is being used */ |
7a292a7a SS |
3091 | lo->reg_offset += 4; |
3092 | hi->reg_offset += 4; | |
3093 | } | |
3094 | lo->buf_offset = 0; | |
3095 | hi->buf_offset = lo->len; | |
3096 | } | |
3097 | } | |
3098 | ||
3099 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
3100 | copy its value into `valbuf'. */ | |
3101 | ||
c906108c SS |
3102 | void |
3103 | mips_extract_return_value (valtype, regbuf, valbuf) | |
c5aa993b JM |
3104 | struct type *valtype; |
3105 | char regbuf[REGISTER_BYTES]; | |
3106 | char *valbuf; | |
c906108c | 3107 | { |
7a292a7a SS |
3108 | struct return_value_word lo; |
3109 | struct return_value_word hi; | |
3110 | return_value_location (valtype, &lo, &hi); | |
3111 | ||
3112 | memcpy (valbuf + lo.buf_offset, | |
3113 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
3114 | lo.len); | |
3115 | ||
3116 | if (hi.len > 0) | |
3117 | memcpy (valbuf + hi.buf_offset, | |
3118 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
3119 | hi.len); | |
3120 | ||
3121 | #if 0 | |
c906108c SS |
3122 | int regnum; |
3123 | int offset = 0; | |
3124 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 3125 | |
c906108c SS |
3126 | regnum = 2; |
3127 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
3128 | && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE | |
3129 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE | |
3130 | && len <= MIPS_FPU_SINGLE_REGSIZE))) | |
3131 | regnum = FP0_REGNUM; | |
3132 | ||
3133 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b | 3134 | { /* "un-left-justify" the value from the register */ |
c906108c SS |
3135 | if (len < REGISTER_RAW_SIZE (regnum)) |
3136 | offset = REGISTER_RAW_SIZE (regnum) - len; | |
c5aa993b | 3137 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ |
c906108c SS |
3138 | len < REGISTER_RAW_SIZE (regnum) * 2 && |
3139 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
3140 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3141 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
3142 | } | |
3143 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, len); | |
3144 | REGISTER_CONVERT_TO_TYPE (regnum, valtype, valbuf); | |
7a292a7a | 3145 | #endif |
c906108c SS |
3146 | } |
3147 | ||
7a292a7a SS |
3148 | /* Given a return value in `valbuf' with a type `valtype', write it's |
3149 | value into the appropriate register. */ | |
3150 | ||
c906108c SS |
3151 | void |
3152 | mips_store_return_value (valtype, valbuf) | |
c5aa993b JM |
3153 | struct type *valtype; |
3154 | char *valbuf; | |
c906108c | 3155 | { |
7a292a7a SS |
3156 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
3157 | struct return_value_word lo; | |
3158 | struct return_value_word hi; | |
3159 | return_value_location (valtype, &lo, &hi); | |
3160 | ||
3161 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3162 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3163 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
3164 | raw_buffer, | |
3165 | REGISTER_RAW_SIZE (lo.reg)); | |
c5aa993b | 3166 | |
7a292a7a SS |
3167 | if (hi.len > 0) |
3168 | { | |
3169 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3170 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3171 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
3172 | raw_buffer, | |
3173 | REGISTER_RAW_SIZE (hi.reg)); | |
3174 | } | |
3175 | ||
3176 | #if 0 | |
c906108c SS |
3177 | int regnum; |
3178 | int offset = 0; | |
3179 | int len = TYPE_LENGTH (valtype); | |
3180 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
c5aa993b | 3181 | |
c906108c SS |
3182 | regnum = 2; |
3183 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
3184 | && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE | |
3185 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE | |
3186 | && len <= MIPS_REGSIZE))) | |
3187 | regnum = FP0_REGNUM; | |
3188 | ||
3189 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b | 3190 | { /* "left-justify" the value in the register */ |
c906108c SS |
3191 | if (len < REGISTER_RAW_SIZE (regnum)) |
3192 | offset = REGISTER_RAW_SIZE (regnum) - len; | |
c5aa993b | 3193 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ |
c906108c SS |
3194 | len < REGISTER_RAW_SIZE (regnum) * 2 && |
3195 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
3196 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3197 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
3198 | } | |
c5aa993b JM |
3199 | memcpy (raw_buffer + offset, valbuf, len); |
3200 | REGISTER_CONVERT_FROM_TYPE (regnum, valtype, raw_buffer); | |
3201 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, | |
3202 | len > REGISTER_RAW_SIZE (regnum) ? | |
3203 | len : REGISTER_RAW_SIZE (regnum)); | |
7a292a7a | 3204 | #endif |
c906108c SS |
3205 | } |
3206 | ||
3207 | /* Exported procedure: Is PC in the signal trampoline code */ | |
3208 | ||
3209 | int | |
3210 | in_sigtramp (pc, ignore) | |
3211 | CORE_ADDR pc; | |
3212 | char *ignore; /* function name */ | |
3213 | { | |
3214 | if (sigtramp_address == 0) | |
3215 | fixup_sigtramp (); | |
3216 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
3217 | } | |
3218 | ||
a5ea2558 AC |
3219 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
3220 | used for all MIPS-specific commands. */ | |
3221 | ||
a14ed312 | 3222 | static void show_mips_command (char *, int); |
a5ea2558 AC |
3223 | static void |
3224 | show_mips_command (args, from_tty) | |
3225 | char *args; | |
3226 | int from_tty; | |
3227 | { | |
3228 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
3229 | } | |
3230 | ||
a14ed312 | 3231 | static void set_mips_command (char *, int); |
a5ea2558 AC |
3232 | static void |
3233 | set_mips_command (args, from_tty) | |
3234 | char *args; | |
3235 | int from_tty; | |
3236 | { | |
3237 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
3238 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
3239 | } | |
3240 | ||
c906108c SS |
3241 | /* Commands to show/set the MIPS FPU type. */ |
3242 | ||
a14ed312 | 3243 | static void show_mipsfpu_command (char *, int); |
c906108c SS |
3244 | static void |
3245 | show_mipsfpu_command (args, from_tty) | |
3246 | char *args; | |
3247 | int from_tty; | |
3248 | { | |
3249 | char *msg; | |
3250 | char *fpu; | |
3251 | switch (MIPS_FPU_TYPE) | |
3252 | { | |
3253 | case MIPS_FPU_SINGLE: | |
3254 | fpu = "single-precision"; | |
3255 | break; | |
3256 | case MIPS_FPU_DOUBLE: | |
3257 | fpu = "double-precision"; | |
3258 | break; | |
3259 | case MIPS_FPU_NONE: | |
3260 | fpu = "absent (none)"; | |
3261 | break; | |
3262 | } | |
3263 | if (mips_fpu_type_auto) | |
3264 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
3265 | fpu); | |
3266 | else | |
3267 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
3268 | fpu); | |
3269 | } | |
3270 | ||
3271 | ||
a14ed312 | 3272 | static void set_mipsfpu_command (char *, int); |
c906108c SS |
3273 | static void |
3274 | set_mipsfpu_command (args, from_tty) | |
3275 | char *args; | |
3276 | int from_tty; | |
3277 | { | |
3278 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
3279 | show_mipsfpu_command (args, from_tty); | |
3280 | } | |
3281 | ||
a14ed312 | 3282 | static void set_mipsfpu_single_command (char *, int); |
c906108c SS |
3283 | static void |
3284 | set_mipsfpu_single_command (args, from_tty) | |
3285 | char *args; | |
3286 | int from_tty; | |
3287 | { | |
3288 | mips_fpu_type = MIPS_FPU_SINGLE; | |
3289 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3290 | if (GDB_MULTI_ARCH) |
3291 | { | |
3292 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; | |
3293 | } | |
c906108c SS |
3294 | } |
3295 | ||
a14ed312 | 3296 | static void set_mipsfpu_double_command (char *, int); |
c906108c SS |
3297 | static void |
3298 | set_mipsfpu_double_command (args, from_tty) | |
3299 | char *args; | |
3300 | int from_tty; | |
3301 | { | |
3302 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
3303 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3304 | if (GDB_MULTI_ARCH) |
3305 | { | |
3306 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; | |
3307 | } | |
c906108c SS |
3308 | } |
3309 | ||
a14ed312 | 3310 | static void set_mipsfpu_none_command (char *, int); |
c906108c SS |
3311 | static void |
3312 | set_mipsfpu_none_command (args, from_tty) | |
3313 | char *args; | |
3314 | int from_tty; | |
3315 | { | |
3316 | mips_fpu_type = MIPS_FPU_NONE; | |
3317 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3318 | if (GDB_MULTI_ARCH) |
3319 | { | |
3320 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; | |
3321 | } | |
c906108c SS |
3322 | } |
3323 | ||
a14ed312 | 3324 | static void set_mipsfpu_auto_command (char *, int); |
c906108c SS |
3325 | static void |
3326 | set_mipsfpu_auto_command (args, from_tty) | |
3327 | char *args; | |
3328 | int from_tty; | |
3329 | { | |
3330 | mips_fpu_type_auto = 1; | |
3331 | } | |
3332 | ||
3333 | /* Command to set the processor type. */ | |
3334 | ||
3335 | void | |
3336 | mips_set_processor_type_command (args, from_tty) | |
3337 | char *args; | |
3338 | int from_tty; | |
3339 | { | |
3340 | int i; | |
3341 | ||
3342 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
3343 | { | |
3344 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
3345 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3346 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
3347 | ||
3348 | /* Restore the value. */ | |
3349 | tmp_mips_processor_type = strsave (mips_processor_type); | |
3350 | ||
3351 | return; | |
3352 | } | |
c5aa993b | 3353 | |
c906108c SS |
3354 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
3355 | { | |
3356 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
3357 | /* Restore its value. */ | |
3358 | tmp_mips_processor_type = strsave (mips_processor_type); | |
3359 | } | |
3360 | } | |
3361 | ||
3362 | static void | |
3363 | mips_show_processor_type_command (args, from_tty) | |
3364 | char *args; | |
3365 | int from_tty; | |
3366 | { | |
3367 | } | |
3368 | ||
3369 | /* Modify the actual processor type. */ | |
3370 | ||
3371 | int | |
3372 | mips_set_processor_type (str) | |
3373 | char *str; | |
3374 | { | |
3375 | int i, j; | |
3376 | ||
3377 | if (str == NULL) | |
3378 | return 0; | |
3379 | ||
3380 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3381 | { | |
3382 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
3383 | { | |
3384 | mips_processor_type = str; | |
cce74817 | 3385 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 3386 | return 1; |
c906108c SS |
3387 | /* FIXME tweak fpu flag too */ |
3388 | } | |
3389 | } | |
3390 | ||
3391 | return 0; | |
3392 | } | |
3393 | ||
3394 | /* Attempt to identify the particular processor model by reading the | |
3395 | processor id. */ | |
3396 | ||
3397 | char * | |
3398 | mips_read_processor_type () | |
3399 | { | |
3400 | CORE_ADDR prid; | |
3401 | ||
3402 | prid = read_register (PRID_REGNUM); | |
3403 | ||
3404 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 3405 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
3406 | |
3407 | return NULL; | |
3408 | } | |
3409 | ||
3410 | /* Just like reinit_frame_cache, but with the right arguments to be | |
3411 | callable as an sfunc. */ | |
3412 | ||
3413 | static void | |
3414 | reinit_frame_cache_sfunc (args, from_tty, c) | |
3415 | char *args; | |
3416 | int from_tty; | |
3417 | struct cmd_list_element *c; | |
3418 | { | |
3419 | reinit_frame_cache (); | |
3420 | } | |
3421 | ||
3422 | int | |
3423 | gdb_print_insn_mips (memaddr, info) | |
3424 | bfd_vma memaddr; | |
3425 | disassemble_info *info; | |
3426 | { | |
3427 | mips_extra_func_info_t proc_desc; | |
3428 | ||
3429 | /* Search for the function containing this address. Set the low bit | |
3430 | of the address when searching, in case we were given an even address | |
3431 | that is the start of a 16-bit function. If we didn't do this, | |
3432 | the search would fail because the symbol table says the function | |
3433 | starts at an odd address, i.e. 1 byte past the given address. */ | |
3434 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
3435 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
3436 | ||
3437 | /* Make an attempt to determine if this is a 16-bit function. If | |
3438 | the procedure descriptor exists and the address therein is odd, | |
3439 | it's definitely a 16-bit function. Otherwise, we have to just | |
3440 | guess that if the address passed in is odd, it's 16-bits. */ | |
3441 | if (proc_desc) | |
3442 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? 16 : TM_PRINT_INSN_MACH; | |
3443 | else | |
3444 | info->mach = pc_is_mips16 (memaddr) ? 16 : TM_PRINT_INSN_MACH; | |
3445 | ||
3446 | /* Round down the instruction address to the appropriate boundary. */ | |
3447 | memaddr &= (info->mach == 16 ? ~1 : ~3); | |
c5aa993b | 3448 | |
c906108c SS |
3449 | /* Call the appropriate disassembler based on the target endian-ness. */ |
3450 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
3451 | return print_insn_big_mips (memaddr, info); | |
3452 | else | |
3453 | return print_insn_little_mips (memaddr, info); | |
3454 | } | |
3455 | ||
3456 | /* Old-style breakpoint macros. | |
3457 | The IDT board uses an unusual breakpoint value, and sometimes gets | |
3458 | confused when it sees the usual MIPS breakpoint instruction. */ | |
3459 | ||
3460 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} | |
3461 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} | |
3462 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} | |
3463 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} | |
3464 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} | |
3465 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} | |
3466 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} | |
3467 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} | |
3468 | ||
3469 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
3470 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
3471 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
3472 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
3473 | (if necessary) to point to the actual memory location where the | |
3474 | breakpoint should be inserted. */ | |
3475 | ||
c5aa993b JM |
3476 | unsigned char * |
3477 | mips_breakpoint_from_pc (pcptr, lenptr) | |
c906108c SS |
3478 | CORE_ADDR *pcptr; |
3479 | int *lenptr; | |
3480 | { | |
3481 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
3482 | { | |
3483 | if (pc_is_mips16 (*pcptr)) | |
3484 | { | |
3485 | static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT; | |
3486 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); | |
c5aa993b | 3487 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
3488 | return mips16_big_breakpoint; |
3489 | } | |
3490 | else | |
3491 | { | |
3492 | static char big_breakpoint[] = BIG_BREAKPOINT; | |
3493 | static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; | |
3494 | static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
3495 | ||
c5aa993b | 3496 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
3497 | |
3498 | if (strcmp (target_shortname, "mips") == 0) | |
3499 | return idt_big_breakpoint; | |
3500 | else if (strcmp (target_shortname, "ddb") == 0 | |
3501 | || strcmp (target_shortname, "pmon") == 0 | |
3502 | || strcmp (target_shortname, "lsi") == 0) | |
3503 | return pmon_big_breakpoint; | |
3504 | else | |
3505 | return big_breakpoint; | |
3506 | } | |
3507 | } | |
3508 | else | |
3509 | { | |
3510 | if (pc_is_mips16 (*pcptr)) | |
3511 | { | |
3512 | static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT; | |
3513 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); | |
c5aa993b | 3514 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
3515 | return mips16_little_breakpoint; |
3516 | } | |
3517 | else | |
3518 | { | |
3519 | static char little_breakpoint[] = LITTLE_BREAKPOINT; | |
3520 | static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT; | |
3521 | static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT; | |
3522 | ||
c5aa993b | 3523 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
3524 | |
3525 | if (strcmp (target_shortname, "mips") == 0) | |
3526 | return idt_little_breakpoint; | |
3527 | else if (strcmp (target_shortname, "ddb") == 0 | |
3528 | || strcmp (target_shortname, "pmon") == 0 | |
3529 | || strcmp (target_shortname, "lsi") == 0) | |
3530 | return pmon_little_breakpoint; | |
3531 | else | |
3532 | return little_breakpoint; | |
3533 | } | |
3534 | } | |
3535 | } | |
3536 | ||
3537 | /* If PC is in a mips16 call or return stub, return the address of the target | |
3538 | PC, which is either the callee or the caller. There are several | |
3539 | cases which must be handled: | |
3540 | ||
3541 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 3542 | target PC is in $31 ($ra). |
c906108c | 3543 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 3544 | and the target PC is in $2. |
c906108c | 3545 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
3546 | before the jal instruction, this is effectively a call stub |
3547 | and the the target PC is in $2. Otherwise this is effectively | |
3548 | a return stub and the target PC is in $18. | |
c906108c SS |
3549 | |
3550 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
3551 | gory details. | |
3552 | ||
3553 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 3554 | */ |
c906108c SS |
3555 | |
3556 | CORE_ADDR | |
3557 | mips_skip_stub (pc) | |
3558 | CORE_ADDR pc; | |
3559 | { | |
3560 | char *name; | |
3561 | CORE_ADDR start_addr; | |
3562 | ||
3563 | /* Find the starting address and name of the function containing the PC. */ | |
3564 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
3565 | return 0; | |
3566 | ||
3567 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
3568 | target PC is in $31 ($ra). */ | |
3569 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3570 | || strcmp (name, "__mips16_ret_df") == 0) | |
3571 | return read_register (RA_REGNUM); | |
3572 | ||
3573 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3574 | { | |
3575 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
3576 | and the target PC is in $2. */ | |
3577 | if (name[19] >= '0' && name[19] <= '9') | |
3578 | return read_register (2); | |
3579 | ||
3580 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
3581 | before the jal instruction, this is effectively a call stub |
3582 | and the the target PC is in $2. Otherwise this is effectively | |
3583 | a return stub and the target PC is in $18. */ | |
c906108c SS |
3584 | else if (name[19] == 's' || name[19] == 'd') |
3585 | { | |
3586 | if (pc == start_addr) | |
3587 | { | |
3588 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
3589 | stub. Such a stub for a function bar might have a name |
3590 | like __fn_stub_bar, and might look like this: | |
3591 | mfc1 $4,$f13 | |
3592 | mfc1 $5,$f12 | |
3593 | mfc1 $6,$f15 | |
3594 | mfc1 $7,$f14 | |
3595 | la $1,bar (becomes a lui/addiu pair) | |
3596 | jr $1 | |
3597 | So scan down to the lui/addi and extract the target | |
3598 | address from those two instructions. */ | |
c906108c SS |
3599 | |
3600 | CORE_ADDR target_pc = read_register (2); | |
3601 | t_inst inst; | |
3602 | int i; | |
3603 | ||
3604 | /* See if the name of the target function is __fn_stub_*. */ | |
3605 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
3606 | return target_pc; | |
3607 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
3608 | && strcmp (name, "etext") != 0 | |
3609 | && strcmp (name, "_etext") != 0) | |
3610 | return target_pc; | |
3611 | ||
3612 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
3613 | The limit on the search is arbitrarily set to 20 |
3614 | instructions. FIXME. */ | |
c906108c SS |
3615 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
3616 | { | |
c5aa993b JM |
3617 | inst = mips_fetch_instruction (target_pc); |
3618 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
3619 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
3620 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
3621 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
3622 | } |
3623 | ||
3624 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
3625 | return target_pc; | |
3626 | } | |
3627 | else | |
3628 | /* This is the 'return' part of a call stub. The return | |
3629 | address is in $r18. */ | |
3630 | return read_register (18); | |
3631 | } | |
3632 | } | |
c5aa993b | 3633 | return 0; /* not a stub */ |
c906108c SS |
3634 | } |
3635 | ||
3636 | ||
3637 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
3638 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
3639 | ||
3640 | int | |
3641 | mips_in_call_stub (pc, name) | |
3642 | CORE_ADDR pc; | |
3643 | char *name; | |
3644 | { | |
3645 | CORE_ADDR start_addr; | |
3646 | ||
3647 | /* Find the starting address of the function containing the PC. If the | |
3648 | caller didn't give us a name, look it up at the same time. */ | |
3649 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
3650 | return 0; | |
3651 | ||
3652 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3653 | { | |
3654 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
3655 | if (name[19] >= '0' && name[19] <= '9') | |
3656 | return 1; | |
3657 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 3658 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
3659 | else if (name[19] == 's' || name[19] == 'd') |
3660 | return pc == start_addr; | |
3661 | } | |
3662 | ||
c5aa993b | 3663 | return 0; /* not a stub */ |
c906108c SS |
3664 | } |
3665 | ||
3666 | ||
3667 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
3668 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
3669 | ||
3670 | int | |
3671 | mips_in_return_stub (pc, name) | |
3672 | CORE_ADDR pc; | |
3673 | char *name; | |
3674 | { | |
3675 | CORE_ADDR start_addr; | |
3676 | ||
3677 | /* Find the starting address of the function containing the PC. */ | |
3678 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
3679 | return 0; | |
3680 | ||
3681 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
3682 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3683 | || strcmp (name, "__mips16_ret_df") == 0) | |
3684 | return 1; | |
3685 | ||
3686 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 3687 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
3688 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
3689 | && (name[19] == 's' || name[19] == 'd') | |
3690 | && pc != start_addr) | |
3691 | return 1; | |
3692 | ||
c5aa993b | 3693 | return 0; /* not a stub */ |
c906108c SS |
3694 | } |
3695 | ||
3696 | ||
3697 | /* Return non-zero if the PC is in a library helper function that should | |
3698 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
3699 | ||
3700 | int | |
3701 | mips_ignore_helper (pc) | |
3702 | CORE_ADDR pc; | |
3703 | { | |
3704 | char *name; | |
3705 | ||
3706 | /* Find the starting address and name of the function containing the PC. */ | |
3707 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
3708 | return 0; | |
3709 | ||
3710 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
3711 | that we want to ignore. */ | |
3712 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
3713 | || strcmp (name, "__mips16_ret_df") == 0); | |
3714 | } | |
3715 | ||
3716 | ||
3717 | /* Return a location where we can set a breakpoint that will be hit | |
3718 | when an inferior function call returns. This is normally the | |
3719 | program's entry point. Executables that don't have an entry | |
3720 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
3721 | whose address is the location where the breakpoint should be placed. */ | |
3722 | ||
3723 | CORE_ADDR | |
3724 | mips_call_dummy_address () | |
3725 | { | |
3726 | struct minimal_symbol *sym; | |
3727 | ||
3728 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
3729 | if (sym) | |
3730 | return SYMBOL_VALUE_ADDRESS (sym); | |
3731 | else | |
3732 | return entry_point_address (); | |
3733 | } | |
3734 | ||
3735 | ||
b9a8e3bf JB |
3736 | /* If the current gcc for for this target does not produce correct debugging |
3737 | information for float parameters, both prototyped and unprototyped, then | |
3738 | define this macro. This forces gdb to always assume that floats are | |
3739 | passed as doubles and then converted in the callee. | |
3740 | ||
3741 | For the mips chip, it appears that the debug info marks the parameters as | |
3742 | floats regardless of whether the function is prototyped, but the actual | |
3743 | values are passed as doubles for the non-prototyped case and floats for | |
3744 | the prototyped case. Thus we choose to make the non-prototyped case work | |
3745 | for C and break the prototyped case, since the non-prototyped case is | |
3746 | probably much more common. (FIXME). */ | |
3747 | ||
3748 | static int | |
3749 | mips_coerce_float_to_double (struct type *formal, struct type *actual) | |
3750 | { | |
3751 | return current_language->la_language == language_c; | |
3752 | } | |
3753 | ||
47a8d4ba AC |
3754 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
3755 | the register stored on the stack (32) is different to its real raw | |
3756 | size (64). The below ensures that registers are fetched from the | |
3757 | stack using their ABI size and then stored into the RAW_BUFFER | |
3758 | using their raw size. | |
3759 | ||
3760 | The alternative to adding this function would be to add an ABI | |
3761 | macro - REGISTER_STACK_SIZE(). */ | |
3762 | ||
3763 | static void | |
3764 | mips_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval) | |
3765 | char *raw_buffer; | |
3766 | int *optimized; | |
3767 | CORE_ADDR *addrp; | |
3768 | struct frame_info *frame; | |
3769 | int regnum; | |
3770 | enum lval_type *lval; | |
3771 | { | |
3772 | CORE_ADDR addr; | |
3773 | ||
3774 | if (!target_has_registers) | |
3775 | error ("No registers."); | |
3776 | ||
3777 | /* Normal systems don't optimize out things with register numbers. */ | |
3778 | if (optimized != NULL) | |
3779 | *optimized = 0; | |
3780 | addr = find_saved_register (frame, regnum); | |
3781 | if (addr != 0) | |
3782 | { | |
3783 | if (lval != NULL) | |
3784 | *lval = lval_memory; | |
3785 | if (regnum == SP_REGNUM) | |
3786 | { | |
3787 | if (raw_buffer != NULL) | |
3788 | { | |
3789 | /* Put it back in target format. */ | |
3790 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
3791 | (LONGEST) addr); | |
3792 | } | |
3793 | if (addrp != NULL) | |
3794 | *addrp = 0; | |
3795 | return; | |
3796 | } | |
3797 | if (raw_buffer != NULL) | |
3798 | { | |
3799 | LONGEST val; | |
3800 | if (regnum < 32) | |
3801 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
3802 | saved. */ | |
3803 | val = read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
3804 | else | |
3805 | val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum)); | |
3806 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); | |
3807 | } | |
3808 | } | |
3809 | else | |
3810 | { | |
3811 | if (lval != NULL) | |
3812 | *lval = lval_register; | |
3813 | addr = REGISTER_BYTE (regnum); | |
3814 | if (raw_buffer != NULL) | |
3815 | read_register_gen (regnum, raw_buffer); | |
3816 | } | |
3817 | if (addrp != NULL) | |
3818 | *addrp = addr; | |
3819 | } | |
2acceee2 | 3820 | |
c2d11a7d JM |
3821 | static gdbarch_init_ftype mips_gdbarch_init; |
3822 | static struct gdbarch * | |
3823 | mips_gdbarch_init (info, arches) | |
3824 | struct gdbarch_info info; | |
3825 | struct gdbarch_list *arches; | |
3826 | { | |
3827 | static LONGEST mips_call_dummy_words[] = | |
3828 | {0}; | |
3829 | struct gdbarch *gdbarch; | |
3830 | struct gdbarch_tdep *tdep; | |
3831 | int elf_flags; | |
3832 | char *ef_mips_abi; | |
3833 | int ef_mips_bitptrs; | |
3834 | int ef_mips_arch; | |
0dadbba0 | 3835 | enum mips_abi mips_abi; |
c2d11a7d JM |
3836 | |
3837 | /* Extract the elf_flags if available */ | |
3838 | if (info.abfd != NULL | |
3839 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
3840 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
3841 | else | |
3842 | elf_flags = 0; | |
3843 | ||
0dadbba0 AC |
3844 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
3845 | switch ((elf_flags & EF_MIPS_ABI)) | |
3846 | { | |
3847 | case E_MIPS_ABI_O32: | |
3848 | mips_abi = MIPS_ABI_O32; | |
3849 | break; | |
3850 | case E_MIPS_ABI_O64: | |
3851 | mips_abi = MIPS_ABI_O64; | |
3852 | break; | |
3853 | case E_MIPS_ABI_EABI32: | |
3854 | mips_abi = MIPS_ABI_EABI32; | |
3855 | break; | |
3856 | case E_MIPS_ABI_EABI64: | |
3857 | mips_abi = MIPS_ABI_EABI32; | |
3858 | break; | |
3859 | default: | |
3860 | mips_abi = MIPS_ABI_UNKNOWN; | |
3861 | break; | |
3862 | } | |
3863 | #ifdef MIPS_DEFAULT_ABI | |
3864 | if (mips_abi == MIPS_ABI_UNKNOWN) | |
3865 | mips_abi = MIPS_DEFAULT_ABI; | |
3866 | #endif | |
3867 | ||
c2d11a7d JM |
3868 | /* try to find a pre-existing architecture */ |
3869 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3870 | arches != NULL; | |
3871 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3872 | { | |
3873 | /* MIPS needs to be pedantic about which ABI the object is | |
3874 | using. */ | |
3875 | if (gdbarch_tdep (current_gdbarch)->elf_flags != elf_flags) | |
3876 | continue; | |
0dadbba0 AC |
3877 | if (gdbarch_tdep (current_gdbarch)->mips_abi != mips_abi) |
3878 | continue; | |
c2d11a7d JM |
3879 | return arches->gdbarch; |
3880 | } | |
3881 | ||
3882 | /* Need a new architecture. Fill in a target specific vector. */ | |
3883 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
3884 | gdbarch = gdbarch_alloc (&info, tdep); | |
3885 | tdep->elf_flags = elf_flags; | |
3886 | ||
3887 | /* Initially set everything according to the ABI. */ | |
3888 | set_gdbarch_short_bit (gdbarch, 16); | |
3889 | set_gdbarch_int_bit (gdbarch, 32); | |
3890 | set_gdbarch_float_bit (gdbarch, 32); | |
3891 | set_gdbarch_double_bit (gdbarch, 64); | |
3892 | set_gdbarch_long_double_bit (gdbarch, 64); | |
0dadbba0 AC |
3893 | tdep->mips_abi = mips_abi; |
3894 | switch (mips_abi) | |
c2d11a7d | 3895 | { |
0dadbba0 | 3896 | case MIPS_ABI_O32: |
c2d11a7d | 3897 | ef_mips_abi = "o32"; |
a5ea2558 | 3898 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 3899 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 3900 | tdep->mips_fp_register_double = 0; |
0dadbba0 AC |
3901 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 7; |
3902 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15; | |
3903 | tdep->mips_regs_have_home_p = 1; | |
c2d11a7d JM |
3904 | set_gdbarch_long_bit (gdbarch, 32); |
3905 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3906 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3907 | break; | |
0dadbba0 | 3908 | case MIPS_ABI_O64: |
c2d11a7d | 3909 | ef_mips_abi = "o64"; |
a5ea2558 | 3910 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 3911 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 3912 | tdep->mips_fp_register_double = 1; |
0dadbba0 AC |
3913 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 7; |
3914 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15; | |
3915 | tdep->mips_regs_have_home_p = 1; | |
c2d11a7d JM |
3916 | set_gdbarch_long_bit (gdbarch, 32); |
3917 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3918 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3919 | break; | |
0dadbba0 | 3920 | case MIPS_ABI_EABI32: |
c2d11a7d | 3921 | ef_mips_abi = "eabi32"; |
a5ea2558 | 3922 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 3923 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 3924 | tdep->mips_fp_register_double = 0; |
0dadbba0 AC |
3925 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 11; |
3926 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; | |
3927 | tdep->mips_regs_have_home_p = 0; | |
c2d11a7d JM |
3928 | set_gdbarch_long_bit (gdbarch, 32); |
3929 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3930 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3931 | break; | |
0dadbba0 | 3932 | case MIPS_ABI_EABI64: |
c2d11a7d | 3933 | ef_mips_abi = "eabi64"; |
a5ea2558 | 3934 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 3935 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 3936 | tdep->mips_fp_register_double = 1; |
0dadbba0 AC |
3937 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 11; |
3938 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; | |
3939 | tdep->mips_regs_have_home_p = 0; | |
c2d11a7d JM |
3940 | set_gdbarch_long_bit (gdbarch, 64); |
3941 | set_gdbarch_ptr_bit (gdbarch, 64); | |
3942 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3943 | break; | |
0dadbba0 AC |
3944 | case MIPS_ABI_N32: |
3945 | ef_mips_abi = "n32"; | |
3946 | tdep->mips_default_saved_regsize = 4; | |
3947 | tdep->mips_default_stack_argsize = 8; | |
3948 | tdep->mips_fp_register_double = 1; | |
3949 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 11; | |
3950 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; | |
3951 | tdep->mips_regs_have_home_p = 0; | |
3952 | set_gdbarch_long_bit (gdbarch, 32); | |
3953 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3954 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3955 | break; | |
c2d11a7d JM |
3956 | default: |
3957 | ef_mips_abi = "default"; | |
a5ea2558 | 3958 | tdep->mips_default_saved_regsize = MIPS_REGSIZE; |
0dadbba0 | 3959 | tdep->mips_default_stack_argsize = MIPS_REGSIZE; |
c2d11a7d | 3960 | tdep->mips_fp_register_double = (REGISTER_VIRTUAL_SIZE (FP0_REGNUM) == 8); |
0dadbba0 AC |
3961 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 11; |
3962 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; | |
3963 | tdep->mips_regs_have_home_p = 1; | |
c2d11a7d JM |
3964 | set_gdbarch_long_bit (gdbarch, 32); |
3965 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3966 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3967 | break; | |
3968 | } | |
3969 | ||
a5ea2558 AC |
3970 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
3971 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
3972 | comment: | |
3973 | ||
3974 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
3975 | flag in object files because to do so would make it impossible to | |
3976 | link with libraries compiled without "-gp32". This is | |
3977 | unnecessarily restrictive. | |
3978 | ||
3979 | We could solve this problem by adding "-gp32" multilibs to gcc, | |
3980 | but to set this flag before gcc is built with such multilibs will | |
3981 | break too many systems.'' | |
3982 | ||
3983 | But even more unhelpfully, the default linker output target for | |
3984 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
3985 | for 64-bit programs - you need to change the ABI to change this, | |
3986 | and not all gcc targets support that currently. Therefore using | |
3987 | this flag to detect 32-bit mode would do the wrong thing given | |
3988 | the current gcc - it would make GDB treat these 64-bit programs | |
3989 | as 32-bit programs by default. */ | |
3990 | ||
c2d11a7d JM |
3991 | /* determine the ISA */ |
3992 | switch (elf_flags & EF_MIPS_ARCH) | |
3993 | { | |
3994 | case E_MIPS_ARCH_1: | |
3995 | ef_mips_arch = 1; | |
3996 | break; | |
3997 | case E_MIPS_ARCH_2: | |
3998 | ef_mips_arch = 2; | |
3999 | break; | |
4000 | case E_MIPS_ARCH_3: | |
4001 | ef_mips_arch = 3; | |
4002 | break; | |
4003 | case E_MIPS_ARCH_4: | |
4004 | ef_mips_arch = 0; | |
4005 | break; | |
4006 | default: | |
4007 | break; | |
4008 | } | |
4009 | ||
4010 | #if 0 | |
4011 | /* determine the size of a pointer */ | |
4012 | if ((elf_flags & EF_MIPS_32BITPTRS)) | |
4013 | { | |
4014 | ef_mips_bitptrs = 32; | |
4015 | } | |
4016 | else if ((elf_flags & EF_MIPS_64BITPTRS)) | |
4017 | { | |
4018 | ef_mips_bitptrs = 64; | |
4019 | } | |
4020 | else | |
4021 | { | |
4022 | ef_mips_bitptrs = 0; | |
4023 | } | |
4024 | #endif | |
4025 | ||
c2d11a7d JM |
4026 | /* enable/disable the MIPS FPU */ |
4027 | if (!mips_fpu_type_auto) | |
4028 | tdep->mips_fpu_type = mips_fpu_type; | |
4029 | else if (info.bfd_arch_info != NULL | |
4030 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4031 | switch (info.bfd_arch_info->mach) | |
4032 | { | |
4033 | case bfd_mach_mips4100: | |
ed9a39eb | 4034 | case bfd_mach_mips4111: |
c2d11a7d JM |
4035 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
4036 | break; | |
4037 | default: | |
4038 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4039 | break; | |
4040 | } | |
4041 | else | |
4042 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4043 | ||
4044 | /* MIPS version of register names. NOTE: At present the MIPS | |
4045 | register name management is part way between the old - | |
4046 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
4047 | Further work on it is required. */ | |
4048 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
4049 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); | |
4050 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
4051 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
4052 | set_gdbarch_write_fp (gdbarch, generic_target_write_fp); | |
4053 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); | |
4054 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
4055 | ||
4056 | /* Initialize a frame */ | |
4057 | set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); | |
4058 | ||
4059 | /* MIPS version of CALL_DUMMY */ | |
4060 | ||
4061 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
4062 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
4063 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); | |
4064 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
4065 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); | |
4066 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
4067 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
4068 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
4069 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
4070 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); | |
4071 | set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); | |
4072 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); | |
4073 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); | |
4074 | set_gdbarch_push_arguments (gdbarch, mips_push_arguments); | |
4075 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); | |
b9a8e3bf | 4076 | set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double); |
c2d11a7d | 4077 | |
c4093a6a | 4078 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
47a8d4ba | 4079 | set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d JM |
4080 | |
4081 | if (gdbarch_debug) | |
4082 | { | |
0dadbba0 | 4083 | fprintf_unfiltered (gdb_stdlog, |
c2d11a7d JM |
4084 | "mips_gdbarch_init: (info)ef_mips_abi = %s\n", |
4085 | ef_mips_abi); | |
0dadbba0 | 4086 | fprintf_unfiltered (gdb_stdlog, |
c2d11a7d JM |
4087 | "mips_gdbarch_init: (info)ef_mips_arch = %d\n", |
4088 | ef_mips_arch); | |
0dadbba0 | 4089 | fprintf_unfiltered (gdb_stdlog, |
c2d11a7d JM |
4090 | "mips_gdbarch_init: (info)ef_mips_bitptrs = %d\n", |
4091 | ef_mips_bitptrs); | |
0dadbba0 AC |
4092 | fprintf_unfiltered (gdb_stdlog, |
4093 | "mips_gdbarch_init: MIPS_REGSIZE = %d\n", | |
4094 | MIPS_REGSIZE); | |
4095 | fprintf_unfiltered (gdb_stdlog, | |
4096 | "mips_gdbarch_init: tdep->elf_flags = 0x%x\n", | |
4097 | tdep->elf_flags); | |
4098 | fprintf_unfiltered (gdb_stdlog, | |
4099 | "mips_gdbarch_init: tdep->mips_abi = %d\n", | |
4100 | tdep->mips_abi); | |
4101 | fprintf_unfiltered (gdb_stdlog, | |
4102 | "mips_gdbarch_init: tdep->mips_fpu_type = %d (%s)\n", | |
c2d11a7d JM |
4103 | tdep->mips_fpu_type, |
4104 | (tdep->mips_fpu_type == MIPS_FPU_NONE ? "none" | |
0dadbba0 AC |
4105 | : tdep->mips_fpu_type == MIPS_FPU_SINGLE ? "single" |
4106 | : tdep->mips_fpu_type == MIPS_FPU_DOUBLE ? "double" | |
c2d11a7d | 4107 | : "???")); |
0dadbba0 AC |
4108 | fprintf_unfiltered (gdb_stdlog, |
4109 | "mips_gdbarch_init: tdep->mips_last_arg_regnum = %d\n", | |
4110 | tdep->mips_last_arg_regnum); | |
4111 | fprintf_unfiltered (gdb_stdlog, | |
4112 | "mips_gdbarch_init: tdep->mips_last_fp_arg_regnum = %d (%d)\n", | |
4113 | tdep->mips_last_fp_arg_regnum, | |
4114 | tdep->mips_last_fp_arg_regnum - FP0_REGNUM); | |
4115 | fprintf_unfiltered (gdb_stdlog, | |
4116 | "mips_gdbarch_init: tdep->mips_default_saved_regsize = %d\n", | |
a5ea2558 | 4117 | tdep->mips_default_saved_regsize); |
0dadbba0 AC |
4118 | fprintf_unfiltered (gdb_stdlog, |
4119 | "mips_gdbarch_init: tdep->mips_fp_register_double = %d (%s)\n", | |
c2d11a7d | 4120 | tdep->mips_fp_register_double, |
0dadbba0 AC |
4121 | (tdep->mips_fp_register_double ? "true" : "false")); |
4122 | fprintf_unfiltered (gdb_stdlog, | |
4123 | "mips_gdbarch_init: tdep->mips_regs_have_home_p = %d\n", | |
4124 | tdep->mips_regs_have_home_p); | |
4125 | fprintf_unfiltered (gdb_stdlog, | |
4126 | "mips_gdbarch_init: tdep->mips_default_stack_argsize = %d\n", | |
4127 | tdep->mips_default_stack_argsize); | |
c2d11a7d JM |
4128 | } |
4129 | ||
4130 | return gdbarch; | |
4131 | } | |
4132 | ||
4133 | ||
c906108c SS |
4134 | void |
4135 | _initialize_mips_tdep () | |
4136 | { | |
4137 | static struct cmd_list_element *mipsfpulist = NULL; | |
4138 | struct cmd_list_element *c; | |
4139 | ||
c2d11a7d JM |
4140 | if (GDB_MULTI_ARCH) |
4141 | register_gdbarch_init (bfd_arch_mips, mips_gdbarch_init); | |
c5aa993b | 4142 | if (!tm_print_insn) /* Someone may have already set it */ |
c906108c SS |
4143 | tm_print_insn = gdb_print_insn_mips; |
4144 | ||
a5ea2558 AC |
4145 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
4146 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
4147 | "Various MIPS specific commands.", | |
4148 | &setmipscmdlist, "set mips ", 0, &setlist); | |
4149 | ||
4150 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
4151 | "Various MIPS specific commands.", | |
4152 | &showmipscmdlist, "show mips ", 0, &showlist); | |
4153 | ||
4154 | /* Allow the user to override the saved register size. */ | |
4155 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
4156 | class_obscure, |
4157 | size_enums, | |
4158 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
4159 | Set size of general purpose registers saved on the stack.\n\ |
4160 | This option can be set to one of:\n\ | |
4161 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
4162 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
4163 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
4164 | saved GP register size from information contained in the executable.\n\ | |
4165 | (default: auto)", | |
1ed2a135 | 4166 | &setmipscmdlist), |
a5ea2558 AC |
4167 | &showmipscmdlist); |
4168 | ||
d929b26f AC |
4169 | /* Allow the user to override the argument stack size. */ |
4170 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
4171 | class_obscure, | |
4172 | size_enums, | |
1ed2a135 | 4173 | &mips_stack_argsize_string, "\ |
d929b26f AC |
4174 | Set the amount of stack space reserved for each argument.\n\ |
4175 | This option can be set to one of:\n\ | |
4176 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
4177 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
4178 | auto - Allow GDB to determine the correct setting from the current\n\ | |
4179 | target and executable (default)", | |
4180 | &setmipscmdlist), | |
4181 | &showmipscmdlist); | |
4182 | ||
c906108c SS |
4183 | /* Let the user turn off floating point and set the fence post for |
4184 | heuristic_proc_start. */ | |
4185 | ||
4186 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
4187 | "Set use of MIPS floating-point coprocessor.", | |
4188 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
4189 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
4190 | "Select single-precision MIPS floating-point coprocessor.", | |
4191 | &mipsfpulist); | |
4192 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
4193 | "Select double-precision MIPS floating-point coprocessor .", | |
4194 | &mipsfpulist); | |
4195 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
4196 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
4197 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
4198 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
4199 | "Select no MIPS floating-point coprocessor.", | |
4200 | &mipsfpulist); | |
4201 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
4202 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
4203 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
4204 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
4205 | "Select MIPS floating-point coprocessor automatically.", | |
4206 | &mipsfpulist); | |
4207 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
4208 | "Show current use of MIPS floating-point coprocessor target.", | |
4209 | &showlist); | |
4210 | ||
c2d11a7d | 4211 | #if !GDB_MULTI_ARCH |
c906108c SS |
4212 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
4213 | (char *) &tmp_mips_processor_type, | |
4214 | "Set the type of MIPS processor in use.\n\ | |
4215 | Set this to be able to access processor-type-specific registers.\n\ | |
4216 | ", | |
4217 | &setlist); | |
4218 | c->function.cfunc = mips_set_processor_type_command; | |
4219 | c = add_show_from_set (c, &showlist); | |
4220 | c->function.cfunc = mips_show_processor_type_command; | |
4221 | ||
4222 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
4223 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
c2d11a7d | 4224 | #endif |
c906108c SS |
4225 | |
4226 | /* We really would like to have both "0" and "unlimited" work, but | |
4227 | command.c doesn't deal with that. So make it a var_zinteger | |
4228 | because the user can always use "999999" or some such for unlimited. */ | |
4229 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
4230 | (char *) &heuristic_fence_post, | |
4231 | "\ | |
4232 | Set the distance searched for the start of a function.\n\ | |
4233 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
4234 | program for the start of a function. This command sets the distance of the\n\ | |
4235 | search. The only need to set it is when debugging a stripped executable.", | |
4236 | &setlist); | |
4237 | /* We need to throw away the frame cache when we set this, since it | |
4238 | might change our ability to get backtraces. */ | |
4239 | c->function.sfunc = reinit_frame_cache_sfunc; | |
4240 | add_show_from_set (c, &showlist); | |
4241 | ||
4242 | /* Allow the user to control whether the upper bits of 64-bit | |
4243 | addresses should be zeroed. */ | |
4244 | add_show_from_set | |
c5aa993b JM |
4245 | (add_set_cmd ("mask-address", no_class, var_boolean, (char *) &mask_address_p, |
4246 | "Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
c906108c SS |
4247 | Use \"on\" to enable the masking, and \"off\" to disable it.\n\ |
4248 | Without an argument, zeroing of upper address bits is enabled.", &setlist), | |
4249 | &showlist); | |
43e526b9 JM |
4250 | |
4251 | /* Allow the user to control the size of 32 bit registers within the | |
4252 | raw remote packet. */ | |
4253 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
4254 | class_obscure, | |
4255 | var_boolean, | |
4256 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
4257 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
4258 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
4259 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
4260 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
4261 | &setlist), | |
4262 | &showlist); | |
c906108c | 4263 | } |