Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
c906108c | 53 | |
e0f7ec59 | 54 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 55 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 56 | |
dd824b04 DJ |
57 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
58 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
59 | #define ST0_FR (1 << 26) | |
60 | ||
b0069a17 AC |
61 | /* The sizes of floating point registers. */ |
62 | ||
63 | enum | |
64 | { | |
65 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
66 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
67 | }; | |
68 | ||
0dadbba0 | 69 | |
2e4ebe70 DJ |
70 | static const char *mips_abi_string; |
71 | ||
72 | static const char *mips_abi_strings[] = { | |
73 | "auto", | |
74 | "n32", | |
75 | "o32", | |
28d169de | 76 | "n64", |
2e4ebe70 DJ |
77 | "o64", |
78 | "eabi32", | |
79 | "eabi64", | |
80 | NULL | |
81 | }; | |
82 | ||
cce74817 | 83 | struct frame_extra_info |
c5aa993b JM |
84 | { |
85 | mips_extra_func_info_t proc_desc; | |
86 | int num_args; | |
87 | }; | |
cce74817 | 88 | |
d929b26f AC |
89 | /* Various MIPS ISA options (related to stack analysis) can be |
90 | overridden dynamically. Establish an enum/array for managing | |
91 | them. */ | |
92 | ||
53904c9e AC |
93 | static const char size_auto[] = "auto"; |
94 | static const char size_32[] = "32"; | |
95 | static const char size_64[] = "64"; | |
d929b26f | 96 | |
53904c9e | 97 | static const char *size_enums[] = { |
d929b26f AC |
98 | size_auto, |
99 | size_32, | |
100 | size_64, | |
a5ea2558 AC |
101 | 0 |
102 | }; | |
103 | ||
7a292a7a SS |
104 | /* Some MIPS boards don't support floating point while others only |
105 | support single-precision floating-point operations. See also | |
106 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
107 | |
108 | enum mips_fpu_type | |
c5aa993b JM |
109 | { |
110 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
111 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
112 | MIPS_FPU_NONE /* No floating point. */ | |
113 | }; | |
c906108c SS |
114 | |
115 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
116 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
117 | #endif | |
118 | static int mips_fpu_type_auto = 1; | |
119 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 120 | |
9ace0497 | 121 | static int mips_debug = 0; |
7a292a7a | 122 | |
c2d11a7d JM |
123 | /* MIPS specific per-architecture information */ |
124 | struct gdbarch_tdep | |
125 | { | |
126 | /* from the elf header */ | |
127 | int elf_flags; | |
70f80edf | 128 | |
c2d11a7d | 129 | /* mips options */ |
0dadbba0 | 130 | enum mips_abi mips_abi; |
2e4ebe70 | 131 | enum mips_abi found_abi; |
c2d11a7d JM |
132 | enum mips_fpu_type mips_fpu_type; |
133 | int mips_last_arg_regnum; | |
134 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 135 | int mips_default_saved_regsize; |
c2d11a7d | 136 | int mips_fp_register_double; |
d929b26f | 137 | int mips_default_stack_argsize; |
4014092b | 138 | int default_mask_address_p; |
719ec221 AC |
139 | /* Is the target using 64-bit raw integer registers but only |
140 | storing a left-aligned 32-bit value in each? */ | |
141 | int mips64_transfers_32bit_regs_p; | |
56cea623 AC |
142 | /* Indexes for various registers. IRIX and embedded have |
143 | different values. This contains the "public" fields. Don't | |
144 | add any that do not need to be public. */ | |
145 | const struct mips_regnum *regnum; | |
691c0433 AC |
146 | /* Register names table for the current register set. */ |
147 | const char **mips_processor_reg_names; | |
c2d11a7d JM |
148 | }; |
149 | ||
56cea623 AC |
150 | const struct mips_regnum * |
151 | mips_regnum (struct gdbarch *gdbarch) | |
152 | { | |
153 | return gdbarch_tdep (gdbarch)->regnum; | |
154 | } | |
155 | ||
156 | static int | |
157 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
158 | { | |
159 | return mips_regnum (gdbarch)->fp0 + 12; | |
160 | } | |
161 | ||
0dadbba0 | 162 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 163 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 164 | |
c2d11a7d | 165 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 166 | |
c2d11a7d | 167 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 168 | |
c2d11a7d | 169 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 170 | |
95404a3e AC |
171 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
172 | functions to test, set, or clear bit 0 of addresses. */ | |
173 | ||
174 | static CORE_ADDR | |
175 | is_mips16_addr (CORE_ADDR addr) | |
176 | { | |
177 | return ((addr) & 1); | |
178 | } | |
179 | ||
180 | static CORE_ADDR | |
181 | make_mips16_addr (CORE_ADDR addr) | |
182 | { | |
183 | return ((addr) | 1); | |
184 | } | |
185 | ||
186 | static CORE_ADDR | |
187 | unmake_mips16_addr (CORE_ADDR addr) | |
188 | { | |
189 | return ((addr) & ~1); | |
190 | } | |
191 | ||
22540ece AC |
192 | /* Return the contents of register REGNUM as a signed integer. */ |
193 | ||
194 | static LONGEST | |
195 | read_signed_register (int regnum) | |
196 | { | |
719ec221 | 197 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 198 | deprecated_read_register_gen (regnum, buf); |
719ec221 | 199 | return (extract_signed_integer (buf, register_size (current_gdbarch, regnum))); |
22540ece AC |
200 | } |
201 | ||
202 | static LONGEST | |
203 | read_signed_register_pid (int regnum, ptid_t ptid) | |
204 | { | |
205 | ptid_t save_ptid; | |
206 | LONGEST retval; | |
207 | ||
208 | if (ptid_equal (ptid, inferior_ptid)) | |
209 | return read_signed_register (regnum); | |
210 | ||
211 | save_ptid = inferior_ptid; | |
212 | ||
213 | inferior_ptid = ptid; | |
214 | ||
215 | retval = read_signed_register (regnum); | |
216 | ||
217 | inferior_ptid = save_ptid; | |
218 | ||
219 | return retval; | |
220 | } | |
221 | ||
d1973055 KB |
222 | /* Return the MIPS ABI associated with GDBARCH. */ |
223 | enum mips_abi | |
224 | mips_abi (struct gdbarch *gdbarch) | |
225 | { | |
226 | return gdbarch_tdep (gdbarch)->mips_abi; | |
227 | } | |
228 | ||
4246e332 AC |
229 | int |
230 | mips_regsize (struct gdbarch *gdbarch) | |
231 | { | |
232 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
233 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
234 | } | |
235 | ||
480d3dd2 AC |
236 | /* Return the currently configured (or set) saved register size. */ |
237 | ||
238 | static const char *mips_saved_regsize_string = size_auto; | |
239 | ||
d929b26f | 240 | static unsigned int |
480d3dd2 | 241 | mips_saved_regsize (struct gdbarch_tdep *tdep) |
d929b26f AC |
242 | { |
243 | if (mips_saved_regsize_string == size_auto) | |
480d3dd2 | 244 | return tdep->mips_default_saved_regsize; |
d929b26f AC |
245 | else if (mips_saved_regsize_string == size_64) |
246 | return 8; | |
247 | else /* if (mips_saved_regsize_string == size_32) */ | |
248 | return 4; | |
249 | } | |
250 | ||
71b8ef93 | 251 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 252 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 253 | "info" field is used for this purpose. |
5a89d8aa MS |
254 | |
255 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
256 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
257 | minimal symbol to mark it as a 16-bit function | |
258 | ||
f594e5e9 | 259 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 260 | |
5a89d8aa MS |
261 | static void |
262 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
263 | { | |
264 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
265 | { | |
266 | MSYMBOL_INFO (msym) = (char *) | |
267 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
268 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
269 | } | |
270 | } | |
271 | ||
71b8ef93 MS |
272 | static int |
273 | msymbol_is_special (struct minimal_symbol *msym) | |
274 | { | |
275 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
276 | } | |
277 | ||
88658117 AC |
278 | /* XFER a value from the big/little/left end of the register. |
279 | Depending on the size of the value it might occupy the entire | |
280 | register or just part of it. Make an allowance for this, aligning | |
281 | things accordingly. */ | |
282 | ||
283 | static void | |
284 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
285 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
286 | int buf_offset) | |
287 | { | |
d9d9c31f | 288 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 | 289 | int reg_offset = 0; |
a4b8ebc8 | 290 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
291 | /* Need to transfer the left or right part of the register, based on |
292 | the targets byte order. */ | |
88658117 AC |
293 | switch (endian) |
294 | { | |
295 | case BFD_ENDIAN_BIG: | |
719ec221 | 296 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
297 | break; |
298 | case BFD_ENDIAN_LITTLE: | |
299 | reg_offset = 0; | |
300 | break; | |
301 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
302 | reg_offset = 0; | |
303 | break; | |
304 | default: | |
305 | internal_error (__FILE__, __LINE__, "bad switch"); | |
306 | } | |
307 | if (mips_debug) | |
cb1d2653 AC |
308 | fprintf_unfiltered (gdb_stderr, |
309 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
310 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
311 | if (mips_debug && out != NULL) |
312 | { | |
313 | int i; | |
cb1d2653 | 314 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 315 | for (i = 0; i < length; i++) |
cb1d2653 | 316 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
317 | } |
318 | if (in != NULL) | |
a4b8ebc8 | 319 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); |
88658117 | 320 | if (out != NULL) |
a4b8ebc8 | 321 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
322 | if (mips_debug && in != NULL) |
323 | { | |
324 | int i; | |
cb1d2653 | 325 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 326 | for (i = 0; i < length; i++) |
cb1d2653 | 327 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
328 | } |
329 | if (mips_debug) | |
330 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
331 | } | |
332 | ||
dd824b04 DJ |
333 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
334 | compatiblity mode. A return value of 1 means that we have | |
335 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
336 | ||
337 | static int | |
338 | mips2_fp_compat (void) | |
339 | { | |
340 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
341 | meaningful. */ | |
56cea623 | 342 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 4) |
dd824b04 DJ |
343 | return 0; |
344 | ||
345 | #if 0 | |
346 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
347 | in all the places we deal with FP registers. PR gdb/413. */ | |
348 | /* Otherwise check the FR bit in the status register - it controls | |
349 | the FP compatiblity mode. If it is clear we are in compatibility | |
350 | mode. */ | |
351 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
352 | return 1; | |
353 | #endif | |
361d1df0 | 354 | |
dd824b04 DJ |
355 | return 0; |
356 | } | |
357 | ||
c2d11a7d JM |
358 | /* Indicate that the ABI makes use of double-precision registers |
359 | provided by the FPU (rather than combining pairs of registers to | |
8fa9cfa1 | 360 | form double-precision values). See also MIPS_FPU_TYPE. */ |
c2d11a7d | 361 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 362 | |
d929b26f AC |
363 | /* The amount of space reserved on the stack for registers. This is |
364 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
365 | data allocated after the registers have run out. */ | |
366 | ||
53904c9e | 367 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
368 | |
369 | static unsigned int | |
480d3dd2 | 370 | mips_stack_argsize (struct gdbarch_tdep *tdep) |
d929b26f AC |
371 | { |
372 | if (mips_stack_argsize_string == size_auto) | |
480d3dd2 | 373 | return tdep->mips_default_stack_argsize; |
d929b26f AC |
374 | else if (mips_stack_argsize_string == size_64) |
375 | return 8; | |
376 | else /* if (mips_stack_argsize_string == size_32) */ | |
377 | return 4; | |
378 | } | |
379 | ||
7a292a7a | 380 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 381 | |
570b8f7c AC |
382 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
383 | struct frame_info *, int); | |
c906108c | 384 | |
a14ed312 | 385 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 386 | |
a14ed312 | 387 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 388 | |
a14ed312 | 389 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 390 | |
570b8f7c AC |
391 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
392 | struct frame_info *next_frame, | |
393 | int cur_frame); | |
c906108c | 394 | |
a14ed312 KB |
395 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
396 | mips_extra_func_info_t proc_desc); | |
c906108c | 397 | |
67b2c998 DJ |
398 | static struct type *mips_float_register_type (void); |
399 | static struct type *mips_double_register_type (void); | |
400 | ||
acdb74a0 AC |
401 | /* The list of available "set mips " and "show mips " commands */ |
402 | ||
403 | static struct cmd_list_element *setmipscmdlist = NULL; | |
404 | static struct cmd_list_element *showmipscmdlist = NULL; | |
405 | ||
5e2e9765 KB |
406 | /* Integer registers 0 thru 31 are handled explicitly by |
407 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
408 | are listed in the followign tables. */ |
409 | ||
410 | enum { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
411 | ||
412 | /* Generic MIPS. */ | |
413 | ||
414 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
415 | "sr", "lo", "hi", "bad", "cause","pc", | |
416 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
417 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
418 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
419 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
420 | "fsr", "fir", ""/*"fp"*/, "", | |
421 | "", "", "", "", "", "", "", "", | |
422 | "", "", "", "", "", "", "", "", | |
423 | }; | |
424 | ||
425 | /* Names of IDT R3041 registers. */ | |
426 | ||
427 | static const char *mips_r3041_reg_names[] = { | |
428 | "sr", "lo", "hi", "bad", "cause","pc", | |
429 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
430 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
431 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
432 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
433 | "fsr", "fir", "",/*"fp"*/ "", | |
434 | "", "", "bus", "ccfg", "", "", "", "", | |
435 | "", "", "port", "cmp", "", "", "epc", "prid", | |
436 | }; | |
437 | ||
438 | /* Names of tx39 registers. */ | |
439 | ||
440 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
441 | "sr", "lo", "hi", "bad", "cause","pc", | |
442 | "", "", "", "", "", "", "", "", | |
443 | "", "", "", "", "", "", "", "", | |
444 | "", "", "", "", "", "", "", "", | |
445 | "", "", "", "", "", "", "", "", | |
446 | "", "", "", "", | |
447 | "", "", "", "", "", "", "", "", | |
448 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
449 | }; | |
450 | ||
451 | /* Names of IRIX registers. */ | |
452 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
453 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
454 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
455 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
456 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
457 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
458 | }; | |
459 | ||
cce74817 | 460 | |
5e2e9765 | 461 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 462 | static const char * |
5e2e9765 | 463 | mips_register_name (int regno) |
cce74817 | 464 | { |
691c0433 | 465 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
466 | /* GPR names for all ABIs other than n32/n64. */ |
467 | static char *mips_gpr_names[] = { | |
468 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
469 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
470 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
471 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
472 | }; | |
473 | ||
474 | /* GPR names for n32 and n64 ABIs. */ | |
475 | static char *mips_n32_n64_gpr_names[] = { | |
476 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
477 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
478 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
479 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
480 | }; | |
481 | ||
482 | enum mips_abi abi = mips_abi (current_gdbarch); | |
483 | ||
a4b8ebc8 AC |
484 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
485 | don't make the raw register names visible. */ | |
486 | int rawnum = regno % NUM_REGS; | |
487 | if (regno < NUM_REGS) | |
488 | return ""; | |
489 | ||
5e2e9765 KB |
490 | /* The MIPS integer registers are always mapped from 0 to 31. The |
491 | names of the registers (which reflects the conventions regarding | |
492 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 493 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
494 | { |
495 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 496 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 497 | else |
a4b8ebc8 | 498 | return mips_gpr_names[rawnum]; |
5e2e9765 | 499 | } |
a4b8ebc8 | 500 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
501 | { |
502 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
503 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
504 | } | |
5e2e9765 KB |
505 | else |
506 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 507 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 508 | } |
5e2e9765 | 509 | |
a4b8ebc8 | 510 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 511 | |
a4b8ebc8 AC |
512 | static int |
513 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
514 | struct reggroup *reggroup) | |
515 | { | |
516 | int vector_p; | |
517 | int float_p; | |
518 | int raw_p; | |
519 | int rawnum = regnum % NUM_REGS; | |
520 | int pseudo = regnum / NUM_REGS; | |
521 | if (reggroup == all_reggroup) | |
522 | return pseudo; | |
523 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
524 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
525 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
526 | (gdbarch), as not all architectures are multi-arch. */ | |
527 | raw_p = rawnum < NUM_REGS; | |
528 | if (REGISTER_NAME (regnum) == NULL | |
529 | || REGISTER_NAME (regnum)[0] == '\0') | |
530 | return 0; | |
531 | if (reggroup == float_reggroup) | |
532 | return float_p && pseudo; | |
533 | if (reggroup == vector_reggroup) | |
534 | return vector_p && pseudo; | |
535 | if (reggroup == general_reggroup) | |
536 | return (!vector_p && !float_p) && pseudo; | |
537 | /* Save the pseudo registers. Need to make certain that any code | |
538 | extracting register values from a saved register cache also uses | |
539 | pseudo registers. */ | |
540 | if (reggroup == save_reggroup) | |
541 | return raw_p && pseudo; | |
542 | /* Restore the same pseudo register. */ | |
543 | if (reggroup == restore_reggroup) | |
544 | return raw_p && pseudo; | |
545 | return 0; | |
546 | } | |
547 | ||
548 | /* Map the symbol table registers which live in the range [1 * | |
549 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 550 | registers. Take care of alignment and size problems. */ |
c5aa993b | 551 | |
a4b8ebc8 AC |
552 | static void |
553 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
554 | int cookednum, void *buf) | |
555 | { | |
47ebcfbe | 556 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 557 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe AC |
558 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
559 | return regcache_raw_read (regcache, rawnum, buf); | |
560 | else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum)) | |
561 | { | |
562 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
563 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
564 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
565 | else | |
566 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
567 | } | |
568 | else | |
569 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
570 | } |
571 | ||
572 | static void | |
573 | mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
574 | int cookednum, const void *buf) | |
575 | { | |
47ebcfbe | 576 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 577 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe AC |
578 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
579 | return regcache_raw_write (regcache, rawnum, buf); | |
580 | else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum)) | |
581 | { | |
582 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
583 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
584 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
585 | else | |
586 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
587 | } | |
588 | else | |
589 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 590 | } |
c5aa993b | 591 | |
c906108c | 592 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
593 | static int mips16_to_32_reg[8] = |
594 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
595 | |
596 | /* Heuristic_proc_start may hunt through the text section for a long | |
597 | time across a 2400 baud serial line. Allows the user to limit this | |
598 | search. */ | |
599 | ||
600 | static unsigned int heuristic_fence_post = 0; | |
601 | ||
c5aa993b JM |
602 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
603 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
604 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
605 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
606 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
607 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
608 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
609 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
610 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
611 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
612 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
613 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
614 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
615 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
616 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
617 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
618 | ||
619 | struct linked_proc_info | |
c5aa993b JM |
620 | { |
621 | struct mips_extra_func_info info; | |
622 | struct linked_proc_info *next; | |
623 | } | |
624 | *linked_proc_desc_table = NULL; | |
c906108c | 625 | |
46cd78fb | 626 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
627 | register N. NOTE: This defines the pseudo register type so need to |
628 | rebuild the architecture vector. */ | |
43e526b9 JM |
629 | |
630 | static int mips64_transfers_32bit_regs_p = 0; | |
631 | ||
719ec221 AC |
632 | static void |
633 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
634 | struct cmd_list_element *c) | |
43e526b9 | 635 | { |
719ec221 AC |
636 | struct gdbarch_info info; |
637 | gdbarch_info_init (&info); | |
638 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
639 | instead of relying on globals. Doing that would let generic code | |
640 | handle the search for this specific architecture. */ | |
641 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 642 | { |
719ec221 AC |
643 | mips64_transfers_32bit_regs_p = 0; |
644 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 645 | } |
a4b8ebc8 AC |
646 | } |
647 | ||
47ebcfbe | 648 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 649 | |
ff2e87ac AC |
650 | static int |
651 | mips_convert_register_p (int regnum, struct type *type) | |
652 | { | |
653 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 654 | && register_size (current_gdbarch, regnum) == 4 |
56cea623 | 655 | && (regnum) >= mips_regnum (current_gdbarch)->fp0 && (regnum) < mips_regnum (current_gdbarch)->fp0 + 32 |
ff2e87ac AC |
656 | && TYPE_CODE(type) == TYPE_CODE_FLT |
657 | && TYPE_LENGTH(type) == 8); | |
658 | } | |
659 | ||
42c466d7 | 660 | static void |
ff2e87ac AC |
661 | mips_register_to_value (struct frame_info *frame, int regnum, |
662 | struct type *type, void *to) | |
102182a9 | 663 | { |
7f5f525d AC |
664 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
665 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
666 | } |
667 | ||
42c466d7 | 668 | static void |
ff2e87ac AC |
669 | mips_value_to_register (struct frame_info *frame, int regnum, |
670 | struct type *type, const void *from) | |
102182a9 | 671 | { |
ff2e87ac AC |
672 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
673 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
674 | } |
675 | ||
a4b8ebc8 AC |
676 | /* Return the GDB type object for the "standard" data type of data in |
677 | register REG. */ | |
78fde5f8 KB |
678 | |
679 | static struct type * | |
a4b8ebc8 AC |
680 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
681 | { | |
5ef80fb0 | 682 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
683 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
684 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 685 | { |
5ef80fb0 AC |
686 | /* The floating-point registers raw, or cooked, always match |
687 | mips_regsize(), and also map 1:1, byte for byte. */ | |
688 | switch (gdbarch_byte_order (gdbarch)) | |
689 | { | |
690 | case BFD_ENDIAN_BIG: | |
691 | if (mips_regsize (gdbarch) == 4) | |
692 | return builtin_type_ieee_single_big; | |
693 | else | |
694 | return builtin_type_ieee_double_big; | |
695 | case BFD_ENDIAN_LITTLE: | |
696 | if (mips_regsize (gdbarch) == 4) | |
697 | return builtin_type_ieee_single_little; | |
698 | else | |
699 | return builtin_type_ieee_double_little; | |
700 | case BFD_ENDIAN_UNKNOWN: | |
701 | default: | |
702 | internal_error (__FILE__, __LINE__, "bad switch"); | |
703 | } | |
a6425924 | 704 | } |
56cea623 | 705 | else if (regnum >= (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status) |
5ef80fb0 AC |
706 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) |
707 | /* The pseudo/cooked view of the embedded registers is always | |
708 | 32-bit. The raw view is handled below. */ | |
709 | return builtin_type_int32; | |
719ec221 AC |
710 | else if (regnum >= NUM_REGS && mips_regsize (gdbarch) |
711 | && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
712 | /* The target, while using a 64-bit register buffer, is only | |
713 | transfering 32-bits of each integer register. Reflect this in | |
714 | the cooked/pseudo register value. */ | |
715 | return builtin_type_int32; | |
5ef80fb0 AC |
716 | else if (mips_regsize (gdbarch) == 8) |
717 | /* 64-bit ISA. */ | |
718 | return builtin_type_int64; | |
78fde5f8 | 719 | else |
5ef80fb0 AC |
720 | /* 32-bit ISA. */ |
721 | return builtin_type_int32; | |
78fde5f8 KB |
722 | } |
723 | ||
bcb0cc15 MS |
724 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
725 | ||
726 | static CORE_ADDR | |
727 | mips_read_sp (void) | |
728 | { | |
e227b13c | 729 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
730 | } |
731 | ||
c906108c | 732 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 733 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
734 | |
735 | static int | |
480d3dd2 | 736 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
737 | { |
738 | switch (mask_address_var) | |
739 | { | |
7f19b9a2 | 740 | case AUTO_BOOLEAN_TRUE: |
4014092b | 741 | return 1; |
7f19b9a2 | 742 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
743 | return 0; |
744 | break; | |
7f19b9a2 | 745 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 746 | return tdep->default_mask_address_p; |
4014092b | 747 | default: |
8e65ff28 AC |
748 | internal_error (__FILE__, __LINE__, |
749 | "mips_mask_address_p: bad switch"); | |
4014092b | 750 | return -1; |
361d1df0 | 751 | } |
4014092b AC |
752 | } |
753 | ||
754 | static void | |
e9e68a56 | 755 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 756 | { |
480d3dd2 | 757 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
758 | switch (mask_address_var) |
759 | { | |
7f19b9a2 | 760 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
761 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
762 | break; | |
7f19b9a2 | 763 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
764 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
765 | break; | |
7f19b9a2 | 766 | case AUTO_BOOLEAN_AUTO: |
4014092b | 767 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
480d3dd2 | 768 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); |
4014092b AC |
769 | break; |
770 | default: | |
8e65ff28 AC |
771 | internal_error (__FILE__, __LINE__, |
772 | "show_mask_address: bad switch"); | |
4014092b | 773 | break; |
361d1df0 | 774 | } |
4014092b | 775 | } |
c906108c SS |
776 | |
777 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 778 | |
f7ab6ec6 | 779 | static int |
cb811fe7 | 780 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 781 | { |
480d3dd2 AC |
782 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
783 | return (TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep)); | |
cb811fe7 MS |
784 | } |
785 | ||
8b389c40 MS |
786 | /* Should call_function pass struct by reference? |
787 | For each architecture, structs are passed either by | |
788 | value or by reference, depending on their size. */ | |
789 | ||
790 | static int | |
791 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
792 | { | |
793 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
794 | int len = TYPE_LENGTH (check_typedef (type)); | |
480d3dd2 | 795 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
8b389c40 MS |
796 | |
797 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
480d3dd2 | 798 | return (len > mips_saved_regsize (tdep)); |
8b389c40 MS |
799 | |
800 | return 0; | |
801 | } | |
802 | ||
c906108c SS |
803 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
804 | ||
805 | static int | |
806 | pc_is_mips16 (bfd_vma memaddr) | |
807 | { | |
808 | struct minimal_symbol *sym; | |
809 | ||
810 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 811 | if (is_mips16_addr (memaddr)) |
c906108c SS |
812 | return 1; |
813 | ||
814 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
815 | the high bit of the info field. Use this to decide if the function is | |
816 | MIPS16 or normal MIPS. */ | |
817 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
818 | if (sym) | |
71b8ef93 | 819 | return msymbol_is_special (sym); |
c906108c SS |
820 | else |
821 | return 0; | |
822 | } | |
823 | ||
6c997a34 AC |
824 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
825 | all registers should be sign extended for simplicity? */ | |
826 | ||
827 | static CORE_ADDR | |
39f77062 | 828 | mips_read_pc (ptid_t ptid) |
6c997a34 | 829 | { |
39f77062 | 830 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 831 | } |
c906108c SS |
832 | |
833 | /* This returns the PC of the first inst after the prologue. If we can't | |
834 | find the prologue, then return 0. */ | |
835 | ||
836 | static CORE_ADDR | |
acdb74a0 AC |
837 | after_prologue (CORE_ADDR pc, |
838 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
839 | { |
840 | struct symtab_and_line sal; | |
841 | CORE_ADDR func_addr, func_end; | |
842 | ||
479412cd DJ |
843 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
844 | to read the stack pointer from the current machine state, because | |
845 | the current machine state has nothing to do with the information | |
846 | we need from the proc_desc; and the process may or may not exist | |
847 | right now. */ | |
c906108c | 848 | if (!proc_desc) |
479412cd | 849 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
850 | |
851 | if (proc_desc) | |
852 | { | |
853 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 854 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
855 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
856 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
857 | return 0; | |
858 | } | |
859 | ||
860 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
861 | return 0; /* Unknown */ | |
862 | ||
863 | sal = find_pc_line (func_addr, 0); | |
864 | ||
865 | if (sal.end < func_end) | |
866 | return sal.end; | |
867 | ||
868 | /* The line after the prologue is after the end of the function. In this | |
869 | case, tell the caller to find the prologue the hard way. */ | |
870 | ||
871 | return 0; | |
872 | } | |
873 | ||
874 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
875 | set the appropriate bit in the general register mask or float register mask | |
876 | to indicate which register is saved. This is a helper function | |
877 | for mips_find_saved_regs. */ | |
878 | ||
879 | static void | |
acdb74a0 AC |
880 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
881 | unsigned long *float_mask) | |
c906108c SS |
882 | { |
883 | int reg; | |
884 | ||
885 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
886 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
887 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
888 | { | |
889 | /* It might be possible to use the instruction to | |
c5aa993b JM |
890 | find the offset, rather than the code below which |
891 | is based on things being in a certain order in the | |
892 | frame, but figuring out what the instruction's offset | |
893 | is relative to might be a little tricky. */ | |
c906108c SS |
894 | reg = (inst & 0x001f0000) >> 16; |
895 | *gen_mask |= (1 << reg); | |
896 | } | |
897 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
898 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
899 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
900 | |
901 | { | |
902 | reg = ((inst & 0x001f0000) >> 16); | |
903 | *float_mask |= (1 << reg); | |
904 | } | |
905 | } | |
906 | ||
907 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
908 | set the appropriate bit in the general register or float register mask | |
909 | to indicate which register is saved. This is a helper function | |
910 | for mips_find_saved_regs. */ | |
911 | ||
912 | static void | |
acdb74a0 | 913 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 914 | { |
c5aa993b | 915 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
916 | { |
917 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
918 | *gen_mask |= (1 << reg); | |
919 | } | |
c5aa993b | 920 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
921 | { |
922 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
923 | *gen_mask |= (1 << reg); | |
924 | } | |
c5aa993b | 925 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
926 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
927 | *gen_mask |= (1 << RA_REGNUM); | |
928 | } | |
929 | ||
930 | ||
931 | /* Fetch and return instruction from the specified location. If the PC | |
932 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
933 | ||
934 | static t_inst | |
acdb74a0 | 935 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
936 | { |
937 | char buf[MIPS_INSTLEN]; | |
938 | int instlen; | |
939 | int status; | |
940 | ||
941 | if (pc_is_mips16 (addr)) | |
942 | { | |
943 | instlen = MIPS16_INSTLEN; | |
95404a3e | 944 | addr = unmake_mips16_addr (addr); |
c906108c SS |
945 | } |
946 | else | |
c5aa993b | 947 | instlen = MIPS_INSTLEN; |
c906108c SS |
948 | status = read_memory_nobpt (addr, buf, instlen); |
949 | if (status) | |
950 | memory_error (status, addr); | |
951 | return extract_unsigned_integer (buf, instlen); | |
952 | } | |
953 | ||
954 | ||
955 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
956 | #define mips32_op(x) (x >> 26) |
957 | #define itype_op(x) (x >> 26) | |
958 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 959 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 960 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 961 | |
e135b889 DJ |
962 | #define jtype_op(x) (x >> 26) |
963 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 964 | |
e135b889 DJ |
965 | #define rtype_op(x) (x >> 26) |
966 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
967 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
968 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
969 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
970 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
971 | |
972 | static CORE_ADDR | |
c5aa993b JM |
973 | mips32_relative_offset (unsigned long inst) |
974 | { | |
975 | long x; | |
976 | x = itype_immediate (inst); | |
977 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 978 | { |
c5aa993b | 979 | x |= 0xffff0000; /* sign extension */ |
c906108c | 980 | } |
c5aa993b JM |
981 | x = x << 2; |
982 | return x; | |
c906108c SS |
983 | } |
984 | ||
985 | /* Determine whate to set a single step breakpoint while considering | |
986 | branch prediction */ | |
5a89d8aa | 987 | static CORE_ADDR |
c5aa993b JM |
988 | mips32_next_pc (CORE_ADDR pc) |
989 | { | |
990 | unsigned long inst; | |
991 | int op; | |
992 | inst = mips_fetch_instruction (pc); | |
e135b889 | 993 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 994 | { |
e135b889 DJ |
995 | if (itype_op (inst) >> 2 == 5) |
996 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 997 | { |
e135b889 | 998 | op = (itype_op (inst) & 0x03); |
c906108c SS |
999 | switch (op) |
1000 | { | |
e135b889 DJ |
1001 | case 0: /* BEQL */ |
1002 | goto equal_branch; | |
1003 | case 1: /* BNEL */ | |
1004 | goto neq_branch; | |
1005 | case 2: /* BLEZL */ | |
1006 | goto less_branch; | |
1007 | case 3: /* BGTZ */ | |
1008 | goto greater_branch; | |
c5aa993b JM |
1009 | default: |
1010 | pc += 4; | |
c906108c SS |
1011 | } |
1012 | } | |
e135b889 DJ |
1013 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
1014 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
1015 | { | |
1016 | int tf = itype_rt (inst) & 0x01; | |
1017 | int cnum = itype_rt (inst) >> 2; | |
56cea623 | 1018 | int fcrcs = read_signed_register (mips_regnum (current_gdbarch)->fp_control_status); |
e135b889 DJ |
1019 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1020 | ||
1021 | if (((cond >> cnum) & 0x01) == tf) | |
1022 | pc += mips32_relative_offset (inst) + 4; | |
1023 | else | |
1024 | pc += 8; | |
1025 | } | |
c5aa993b JM |
1026 | else |
1027 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1028 | } |
1029 | else | |
c5aa993b JM |
1030 | { /* This gets way messy */ |
1031 | ||
c906108c | 1032 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1033 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1034 | { |
c5aa993b JM |
1035 | case 0: /* SPECIAL */ |
1036 | op = rtype_funct (inst); | |
1037 | switch (op) | |
1038 | { | |
1039 | case 8: /* JR */ | |
1040 | case 9: /* JALR */ | |
6c997a34 AC |
1041 | /* Set PC to that address */ |
1042 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1043 | break; |
1044 | default: | |
1045 | pc += 4; | |
1046 | } | |
1047 | ||
e135b889 | 1048 | break; /* end SPECIAL */ |
c5aa993b | 1049 | case 1: /* REGIMM */ |
c906108c | 1050 | { |
e135b889 DJ |
1051 | op = itype_rt (inst); /* branch condition */ |
1052 | switch (op) | |
c906108c | 1053 | { |
c5aa993b | 1054 | case 0: /* BLTZ */ |
e135b889 DJ |
1055 | case 2: /* BLTZL */ |
1056 | case 16: /* BLTZAL */ | |
c5aa993b | 1057 | case 18: /* BLTZALL */ |
c906108c | 1058 | less_branch: |
6c997a34 | 1059 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1060 | pc += mips32_relative_offset (inst) + 4; |
1061 | else | |
1062 | pc += 8; /* after the delay slot */ | |
1063 | break; | |
e135b889 | 1064 | case 1: /* BGEZ */ |
c5aa993b JM |
1065 | case 3: /* BGEZL */ |
1066 | case 17: /* BGEZAL */ | |
1067 | case 19: /* BGEZALL */ | |
6c997a34 | 1068 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1069 | pc += mips32_relative_offset (inst) + 4; |
1070 | else | |
1071 | pc += 8; /* after the delay slot */ | |
1072 | break; | |
e135b889 | 1073 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1074 | default: |
1075 | pc += 4; | |
c906108c SS |
1076 | } |
1077 | } | |
e135b889 | 1078 | break; /* end REGIMM */ |
c5aa993b JM |
1079 | case 2: /* J */ |
1080 | case 3: /* JAL */ | |
1081 | { | |
1082 | unsigned long reg; | |
1083 | reg = jtype_target (inst) << 2; | |
e135b889 | 1084 | /* Upper four bits get never changed... */ |
c5aa993b | 1085 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1086 | } |
c5aa993b JM |
1087 | break; |
1088 | /* FIXME case JALX : */ | |
1089 | { | |
1090 | unsigned long reg; | |
1091 | reg = jtype_target (inst) << 2; | |
1092 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1093 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1094 | } | |
c5aa993b | 1095 | break; /* The new PC will be alternate mode */ |
e135b889 | 1096 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1097 | equal_branch: |
6c997a34 AC |
1098 | if (read_signed_register (itype_rs (inst)) == |
1099 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1100 | pc += mips32_relative_offset (inst) + 4; |
1101 | else | |
1102 | pc += 8; | |
1103 | break; | |
e135b889 | 1104 | case 5: /* BNE, BNEL */ |
c5aa993b | 1105 | neq_branch: |
6c997a34 | 1106 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1107 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1108 | pc += mips32_relative_offset (inst) + 4; |
1109 | else | |
1110 | pc += 8; | |
1111 | break; | |
e135b889 | 1112 | case 6: /* BLEZ, BLEZL */ |
6c997a34 | 1113 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1114 | pc += mips32_relative_offset (inst) + 4; |
1115 | else | |
1116 | pc += 8; | |
1117 | break; | |
1118 | case 7: | |
e135b889 DJ |
1119 | default: |
1120 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1121 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1122 | pc += mips32_relative_offset (inst) + 4; |
1123 | else | |
1124 | pc += 8; | |
1125 | break; | |
c5aa993b JM |
1126 | } /* switch */ |
1127 | } /* else */ | |
1128 | return pc; | |
1129 | } /* mips32_next_pc */ | |
c906108c SS |
1130 | |
1131 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1132 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1133 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1134 | We dont want to set a single step instruction on the extend instruction | |
1135 | either. | |
c5aa993b | 1136 | */ |
c906108c SS |
1137 | |
1138 | /* Lots of mips16 instruction formats */ | |
1139 | /* Predicting jumps requires itype,ritype,i8type | |
1140 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1141 | */ |
c906108c SS |
1142 | enum mips16_inst_fmts |
1143 | { | |
c5aa993b JM |
1144 | itype, /* 0 immediate 5,10 */ |
1145 | ritype, /* 1 5,3,8 */ | |
1146 | rrtype, /* 2 5,3,3,5 */ | |
1147 | rritype, /* 3 5,3,3,5 */ | |
1148 | rrrtype, /* 4 5,3,3,3,2 */ | |
1149 | rriatype, /* 5 5,3,3,1,4 */ | |
1150 | shifttype, /* 6 5,3,3,3,2 */ | |
1151 | i8type, /* 7 5,3,8 */ | |
1152 | i8movtype, /* 8 5,3,3,5 */ | |
1153 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1154 | i64type, /* 10 5,3,8 */ | |
1155 | ri64type, /* 11 5,3,3,5 */ | |
1156 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1157 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1158 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1159 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1160 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1161 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1162 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1163 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1164 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1165 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1166 | }; | |
12f02c2a AC |
1167 | /* I am heaping all the fields of the formats into one structure and |
1168 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1169 | struct upk_mips16 |
c5aa993b | 1170 | { |
12f02c2a | 1171 | CORE_ADDR offset; |
c5aa993b JM |
1172 | unsigned int regx; /* Function in i8 type */ |
1173 | unsigned int regy; | |
1174 | }; | |
c906108c SS |
1175 | |
1176 | ||
12f02c2a AC |
1177 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1178 | for the bits which make up the immediatate extension. */ | |
c906108c | 1179 | |
12f02c2a AC |
1180 | static CORE_ADDR |
1181 | extended_offset (unsigned int extension) | |
c906108c | 1182 | { |
12f02c2a | 1183 | CORE_ADDR value; |
c5aa993b JM |
1184 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1185 | value = value << 6; | |
1186 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1187 | value = value << 5; | |
1188 | value |= extension & 0x01f; /* extract 4:0 */ | |
1189 | return value; | |
c906108c SS |
1190 | } |
1191 | ||
1192 | /* Only call this function if you know that this is an extendable | |
1193 | instruction, It wont malfunction, but why make excess remote memory references? | |
1194 | If the immediate operands get sign extended or somthing, do it after | |
1195 | the extension is performed. | |
c5aa993b | 1196 | */ |
c906108c SS |
1197 | /* FIXME: Every one of these cases needs to worry about sign extension |
1198 | when the offset is to be used in relative addressing */ | |
1199 | ||
1200 | ||
12f02c2a | 1201 | static unsigned int |
c5aa993b | 1202 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1203 | { |
c5aa993b JM |
1204 | char buf[8]; |
1205 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1206 | target_read_memory (pc, buf, 2); | |
1207 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1208 | } |
1209 | ||
1210 | static void | |
c5aa993b | 1211 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1212 | unsigned int extension, |
1213 | unsigned int inst, | |
1214 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1215 | struct upk_mips16 *upk) |
c906108c | 1216 | { |
12f02c2a AC |
1217 | CORE_ADDR offset; |
1218 | int regx; | |
1219 | int regy; | |
1220 | switch (insn_format) | |
c906108c | 1221 | { |
c5aa993b | 1222 | case itype: |
c906108c | 1223 | { |
12f02c2a AC |
1224 | CORE_ADDR value; |
1225 | if (extension) | |
c5aa993b JM |
1226 | { |
1227 | value = extended_offset (extension); | |
1228 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1229 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1230 | } |
1231 | else | |
c5aa993b | 1232 | { |
12f02c2a | 1233 | value = inst & 0x7ff; |
c5aa993b | 1234 | /* FIXME : Consider sign extension */ |
c906108c | 1235 | } |
12f02c2a AC |
1236 | offset = value; |
1237 | regx = -1; | |
1238 | regy = -1; | |
c906108c | 1239 | } |
c5aa993b JM |
1240 | break; |
1241 | case ritype: | |
1242 | case i8type: | |
1243 | { /* A register identifier and an offset */ | |
c906108c SS |
1244 | /* Most of the fields are the same as I type but the |
1245 | immediate value is of a different length */ | |
12f02c2a AC |
1246 | CORE_ADDR value; |
1247 | if (extension) | |
c906108c | 1248 | { |
c5aa993b JM |
1249 | value = extended_offset (extension); |
1250 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1251 | value |= inst & 0xff; /* eleven bits from instruction */ |
1252 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1253 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1254 | { | |
1255 | value &= ~0x3fff; /* remove the sign bit */ | |
1256 | value = -value; | |
c906108c SS |
1257 | } |
1258 | } | |
c5aa993b JM |
1259 | else |
1260 | { | |
12f02c2a AC |
1261 | value = inst & 0xff; /* 8 bits */ |
1262 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1263 | /* FIXME: Do sign extension , this format needs it */ |
1264 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1265 | { | |
1266 | value &= 0xef; /* remove the sign bit */ | |
1267 | value = -value; | |
1268 | } | |
c5aa993b | 1269 | } |
12f02c2a AC |
1270 | offset = value; |
1271 | regy = -1; | |
c5aa993b | 1272 | break; |
c906108c | 1273 | } |
c5aa993b | 1274 | case jalxtype: |
c906108c | 1275 | { |
c5aa993b | 1276 | unsigned long value; |
12f02c2a AC |
1277 | unsigned int nexthalf; |
1278 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1279 | value = value << 16; |
1280 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1281 | value |= nexthalf; | |
12f02c2a AC |
1282 | offset = value; |
1283 | regx = -1; | |
1284 | regy = -1; | |
c5aa993b | 1285 | break; |
c906108c SS |
1286 | } |
1287 | default: | |
8e65ff28 AC |
1288 | internal_error (__FILE__, __LINE__, |
1289 | "bad switch"); | |
c906108c | 1290 | } |
12f02c2a AC |
1291 | upk->offset = offset; |
1292 | upk->regx = regx; | |
1293 | upk->regy = regy; | |
c906108c SS |
1294 | } |
1295 | ||
1296 | ||
c5aa993b JM |
1297 | static CORE_ADDR |
1298 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1299 | { |
c5aa993b | 1300 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1301 | } |
1302 | ||
12f02c2a AC |
1303 | static CORE_ADDR |
1304 | extended_mips16_next_pc (CORE_ADDR pc, | |
1305 | unsigned int extension, | |
1306 | unsigned int insn) | |
c906108c | 1307 | { |
12f02c2a AC |
1308 | int op = (insn >> 11); |
1309 | switch (op) | |
c906108c | 1310 | { |
12f02c2a AC |
1311 | case 2: /* Branch */ |
1312 | { | |
1313 | CORE_ADDR offset; | |
1314 | struct upk_mips16 upk; | |
1315 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1316 | offset = upk.offset; | |
1317 | if (offset & 0x800) | |
1318 | { | |
1319 | offset &= 0xeff; | |
1320 | offset = -offset; | |
1321 | } | |
1322 | pc += (offset << 1) + 2; | |
1323 | break; | |
1324 | } | |
1325 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1326 | { | |
1327 | struct upk_mips16 upk; | |
1328 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1329 | pc = add_offset_16 (pc, upk.offset); | |
1330 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1331 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1332 | else | |
1333 | pc |= 0x01; | |
1334 | break; | |
1335 | } | |
1336 | case 4: /* beqz */ | |
1337 | { | |
1338 | struct upk_mips16 upk; | |
1339 | int reg; | |
1340 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1341 | reg = read_signed_register (upk.regx); | |
1342 | if (reg == 0) | |
1343 | pc += (upk.offset << 1) + 2; | |
1344 | else | |
1345 | pc += 2; | |
1346 | break; | |
1347 | } | |
1348 | case 5: /* bnez */ | |
1349 | { | |
1350 | struct upk_mips16 upk; | |
1351 | int reg; | |
1352 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1353 | reg = read_signed_register (upk.regx); | |
1354 | if (reg != 0) | |
1355 | pc += (upk.offset << 1) + 2; | |
1356 | else | |
1357 | pc += 2; | |
1358 | break; | |
1359 | } | |
1360 | case 12: /* I8 Formats btez btnez */ | |
1361 | { | |
1362 | struct upk_mips16 upk; | |
1363 | int reg; | |
1364 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1365 | /* upk.regx contains the opcode */ | |
1366 | reg = read_signed_register (24); /* Test register is 24 */ | |
1367 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1368 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1369 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1370 | pc += (upk.offset << 1) + 2; | |
1371 | else | |
1372 | pc += 2; | |
1373 | break; | |
1374 | } | |
1375 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1376 | { | |
1377 | struct upk_mips16 upk; | |
1378 | /* upk.fmt = rrtype; */ | |
1379 | op = insn & 0x1f; | |
1380 | if (op == 0) | |
c5aa993b | 1381 | { |
12f02c2a AC |
1382 | int reg; |
1383 | upk.regx = (insn >> 8) & 0x07; | |
1384 | upk.regy = (insn >> 5) & 0x07; | |
1385 | switch (upk.regy) | |
c5aa993b | 1386 | { |
12f02c2a AC |
1387 | case 0: |
1388 | reg = upk.regx; | |
1389 | break; | |
1390 | case 1: | |
1391 | reg = 31; | |
1392 | break; /* Function return instruction */ | |
1393 | case 2: | |
1394 | reg = upk.regx; | |
1395 | break; | |
1396 | default: | |
1397 | reg = 31; | |
1398 | break; /* BOGUS Guess */ | |
c906108c | 1399 | } |
12f02c2a | 1400 | pc = read_signed_register (reg); |
c906108c | 1401 | } |
12f02c2a | 1402 | else |
c5aa993b | 1403 | pc += 2; |
12f02c2a AC |
1404 | break; |
1405 | } | |
1406 | case 30: | |
1407 | /* This is an instruction extension. Fetch the real instruction | |
1408 | (which follows the extension) and decode things based on | |
1409 | that. */ | |
1410 | { | |
1411 | pc += 2; | |
1412 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1413 | break; | |
1414 | } | |
1415 | default: | |
1416 | { | |
1417 | pc += 2; | |
1418 | break; | |
1419 | } | |
c906108c | 1420 | } |
c5aa993b | 1421 | return pc; |
12f02c2a | 1422 | } |
c906108c | 1423 | |
5a89d8aa | 1424 | static CORE_ADDR |
12f02c2a AC |
1425 | mips16_next_pc (CORE_ADDR pc) |
1426 | { | |
1427 | unsigned int insn = fetch_mips_16 (pc); | |
1428 | return extended_mips16_next_pc (pc, 0, insn); | |
1429 | } | |
1430 | ||
1431 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1432 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1433 | It works by decoding the current instruction and predicting where a |
1434 | branch will go. This isnt hard because all the data is available. | |
1435 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1436 | CORE_ADDR |
1437 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1438 | { |
c5aa993b JM |
1439 | if (pc & 0x01) |
1440 | return mips16_next_pc (pc); | |
1441 | else | |
1442 | return mips32_next_pc (pc); | |
12f02c2a | 1443 | } |
c906108c | 1444 | |
e0f7ec59 AC |
1445 | /* Set up the 'saved_regs' array. This is a data structure containing |
1446 | the addresses on the stack where each register has been saved, for | |
1447 | each stack frame. Registers that have not been saved will have | |
1448 | zero here. The stack pointer register is special: rather than the | |
1449 | address where the stack register has been saved, | |
1450 | saved_regs[SP_REGNUM] will have the actual value of the previous | |
1451 | frame's stack register. */ | |
c906108c | 1452 | |
d28e01f4 | 1453 | static void |
acdb74a0 | 1454 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1455 | { |
1456 | int ireg; | |
c906108c SS |
1457 | /* r0 bit means kernel trap */ |
1458 | int kernel_trap; | |
1459 | /* What registers have been saved? Bitmasks. */ | |
1460 | unsigned long gen_mask, float_mask; | |
1461 | mips_extra_func_info_t proc_desc; | |
1462 | t_inst inst; | |
e0f7ec59 | 1463 | CORE_ADDR *saved_regs; |
480d3dd2 | 1464 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1465 | |
1b1d3794 | 1466 | if (deprecated_get_frame_saved_regs (fci) != NULL) |
e0f7ec59 AC |
1467 | return; |
1468 | saved_regs = frame_saved_regs_zalloc (fci); | |
c906108c SS |
1469 | |
1470 | /* If it is the frame for sigtramp, the saved registers are located | |
e0f7ec59 AC |
1471 | in a sigcontext structure somewhere on the stack. If the stack |
1472 | layout for sigtramp changes we might have to change these | |
1473 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
c906108c | 1474 | #ifndef SIGFRAME_BASE |
e0f7ec59 AC |
1475 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
1476 | above the sigtramp frame. */ | |
4246e332 | 1477 | #define SIGFRAME_BASE mips_regsize (current_gdbarch) |
c906108c | 1478 | /* FIXME! Are these correct?? */ |
4246e332 AC |
1479 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch)) |
1480 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch)) | |
c906108c | 1481 | #define SIGFRAME_FPREGSAVE_OFF \ |
4246e332 | 1482 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch)) |
c906108c | 1483 | #endif |
5a203e44 | 1484 | if ((get_frame_type (fci) == SIGTRAMP_FRAME)) |
c906108c SS |
1485 | { |
1486 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1487 | { | |
e0f7ec59 | 1488 | CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF |
10a08821 | 1489 | + ireg * mips_regsize (current_gdbarch)); |
e0f7ec59 | 1490 | set_reg_offset (saved_regs, ireg, reg_position); |
c906108c SS |
1491 | } |
1492 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1493 | { | |
e0f7ec59 AC |
1494 | CORE_ADDR reg_position = (get_frame_base (fci) |
1495 | + SIGFRAME_FPREGSAVE_OFF | |
10a08821 | 1496 | + ireg * mips_regsize (current_gdbarch)); |
56cea623 | 1497 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
c906108c | 1498 | } |
e0f7ec59 AC |
1499 | |
1500 | set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF); | |
1501 | /* SP_REGNUM, contains the value and not the address. */ | |
1502 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
c906108c SS |
1503 | return; |
1504 | } | |
1505 | ||
da50a4b7 | 1506 | proc_desc = get_frame_extra_info (fci)->proc_desc; |
c906108c | 1507 | if (proc_desc == NULL) |
e0f7ec59 AC |
1508 | /* I'm not sure how/whether this can happen. Normally when we |
1509 | can't find a proc_desc, we "synthesize" one using | |
1510 | heuristic_proc_desc and set the saved_regs right away. */ | |
c906108c SS |
1511 | return; |
1512 | ||
c5aa993b JM |
1513 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1514 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1515 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1516 | |
e0f7ec59 AC |
1517 | if (/* In any frame other than the innermost or a frame interrupted |
1518 | by a signal, we assume that all registers have been saved. | |
1519 | This assumes that all register saves in a function happen | |
1520 | before the first function call. */ | |
11c02a10 AC |
1521 | (get_next_frame (fci) == NULL |
1522 | || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) | |
c906108c | 1523 | |
e0f7ec59 | 1524 | /* In a dummy frame we know exactly where things are saved. */ |
c5aa993b | 1525 | && !PROC_DESC_IS_DUMMY (proc_desc) |
c906108c | 1526 | |
e0f7ec59 AC |
1527 | /* Don't bother unless we are inside a function prologue. |
1528 | Outside the prologue, we know where everything is. */ | |
c906108c | 1529 | |
50abf9e5 | 1530 | && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc)) |
c906108c | 1531 | |
e0f7ec59 AC |
1532 | /* Not sure exactly what kernel_trap means, but if it means the |
1533 | kernel saves the registers without a prologue doing it, we | |
1534 | better not examine the prologue to see whether registers | |
1535 | have been saved yet. */ | |
c5aa993b | 1536 | && !kernel_trap) |
c906108c | 1537 | { |
e0f7ec59 AC |
1538 | /* We need to figure out whether the registers that the |
1539 | proc_desc claims are saved have been saved yet. */ | |
c906108c SS |
1540 | |
1541 | CORE_ADDR addr; | |
1542 | ||
1543 | /* Bitmasks; set if we have found a save for the register. */ | |
1544 | unsigned long gen_save_found = 0; | |
1545 | unsigned long float_save_found = 0; | |
1546 | int instlen; | |
1547 | ||
1548 | /* If the address is odd, assume this is MIPS16 code. */ | |
1549 | addr = PROC_LOW_ADDR (proc_desc); | |
1550 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1551 | ||
e0f7ec59 AC |
1552 | /* Scan through this function's instructions preceding the |
1553 | current PC, and look for those that save registers. */ | |
50abf9e5 | 1554 | while (addr < get_frame_pc (fci)) |
c906108c SS |
1555 | { |
1556 | inst = mips_fetch_instruction (addr); | |
1557 | if (pc_is_mips16 (addr)) | |
1558 | mips16_decode_reg_save (inst, &gen_save_found); | |
1559 | else | |
1560 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1561 | addr += instlen; | |
1562 | } | |
1563 | gen_mask = gen_save_found; | |
1564 | float_mask = float_save_found; | |
1565 | } | |
1566 | ||
e0f7ec59 AC |
1567 | /* Fill in the offsets for the registers which gen_mask says were |
1568 | saved. */ | |
1569 | { | |
1570 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1571 | + PROC_REG_OFFSET (proc_desc)); | |
1572 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1573 | if (gen_mask & 0x80000000) | |
1574 | { | |
1575 | set_reg_offset (saved_regs, ireg, reg_position); | |
480d3dd2 | 1576 | reg_position -= mips_saved_regsize (tdep); |
e0f7ec59 AC |
1577 | } |
1578 | } | |
c906108c | 1579 | |
e0f7ec59 AC |
1580 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse |
1581 | order of that normally used by gcc. Therefore, we have to fetch | |
1582 | the first instruction of the function, and if it's an entry | |
1583 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
c906108c SS |
1584 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
1585 | { | |
1586 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
e0f7ec59 AC |
1587 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) |
1588 | /* entry */ | |
c906108c SS |
1589 | { |
1590 | int reg; | |
1591 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1592 | |
c906108c | 1593 | /* Check if the ra register was pushed on the stack. */ |
e0f7ec59 AC |
1594 | CORE_ADDR reg_position = (get_frame_base (fci) |
1595 | + PROC_REG_OFFSET (proc_desc)); | |
c906108c | 1596 | if (inst & 0x20) |
480d3dd2 | 1597 | reg_position -= mips_saved_regsize (tdep); |
c906108c | 1598 | |
e0f7ec59 AC |
1599 | /* Check if the s0 and s1 registers were pushed on the |
1600 | stack. */ | |
c5aa993b | 1601 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c | 1602 | { |
e0f7ec59 | 1603 | set_reg_offset (saved_regs, reg, reg_position); |
480d3dd2 | 1604 | reg_position -= mips_saved_regsize (tdep); |
c906108c SS |
1605 | } |
1606 | } | |
1607 | } | |
1608 | ||
e0f7ec59 AC |
1609 | /* Fill in the offsets for the registers which float_mask says were |
1610 | saved. */ | |
1611 | { | |
1612 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1613 | + PROC_FREG_OFFSET (proc_desc)); | |
6acdf5c7 | 1614 | |
e0f7ec59 AC |
1615 | /* Fill in the offsets for the float registers which float_mask |
1616 | says were saved. */ | |
1617 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1618 | if (float_mask & 0x80000000) | |
1619 | { | |
480d3dd2 AC |
1620 | if (mips_saved_regsize (tdep) == 4 |
1621 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
c57bb9fa AC |
1622 | { |
1623 | /* On a big endian 32 bit ABI, floating point registers | |
1624 | are paired to form doubles such that the most | |
1625 | significant part is in $f[N+1] and the least | |
1626 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1627 | registers are also spilled as a pair and stored as a | |
1628 | double. | |
1629 | ||
1630 | When little-endian the least significant part is | |
1631 | stored first leading to the memory order $f[N] and | |
1632 | then $f[N+1]. | |
1633 | ||
ce2826aa | 1634 | Unfortunately, when big-endian the most significant |
c57bb9fa AC |
1635 | part of the double is stored first, and the least |
1636 | significant is stored second. This leads to the | |
1637 | registers being ordered in memory as firt $f[N+1] and | |
1638 | then $f[N]. | |
1639 | ||
1640 | For the big-endian case make certain that the | |
1641 | addresses point at the correct (swapped) locations | |
1642 | $f[N] and $f[N+1] pair (keep in mind that | |
1643 | reg_position is decremented each time through the | |
1644 | loop). */ | |
1645 | if ((ireg & 1)) | |
56cea623 | 1646 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
480d3dd2 | 1647 | reg_position - mips_saved_regsize (tdep)); |
c57bb9fa | 1648 | else |
56cea623 | 1649 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
480d3dd2 | 1650 | reg_position + mips_saved_regsize (tdep)); |
c57bb9fa AC |
1651 | } |
1652 | else | |
56cea623 | 1653 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
480d3dd2 | 1654 | reg_position -= mips_saved_regsize (tdep); |
e0f7ec59 | 1655 | } |
c906108c | 1656 | |
e0f7ec59 AC |
1657 | set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]); |
1658 | } | |
d28e01f4 | 1659 | |
e0f7ec59 AC |
1660 | /* SP_REGNUM, contains the value and not the address. */ |
1661 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
d28e01f4 KB |
1662 | } |
1663 | ||
c906108c | 1664 | static CORE_ADDR |
acdb74a0 | 1665 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1666 | { |
a4b8ebc8 AC |
1667 | /* Always a pseudo. */ |
1668 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 1669 | if (fi == NULL) |
c906108c | 1670 | { |
a4b8ebc8 AC |
1671 | LONGEST val; |
1672 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
1673 | return val; | |
f796e4be | 1674 | } |
a4b8ebc8 AC |
1675 | else if ((regno % NUM_REGS) == SP_REGNUM) |
1676 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
1677 | In fact, it is so special that it can even only be fetched | |
1678 | using a raw register number! Once this code as been converted | |
1679 | to frame-unwind the problem goes away. */ | |
1680 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 1681 | else |
a4b8ebc8 | 1682 | return frame_unwind_register_signed (fi, regno); |
64159455 | 1683 | |
c906108c SS |
1684 | } |
1685 | ||
1686 | /* mips_addr_bits_remove - remove useless address bits */ | |
1687 | ||
875e1767 | 1688 | static CORE_ADDR |
acdb74a0 | 1689 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1690 | { |
480d3dd2 AC |
1691 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1692 | if (mips_mask_address_p (tdep) | |
8fa9cfa1 AC |
1693 | && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
1694 | /* This hack is a work-around for existing boards using PMON, the | |
1695 | simulator, and any other 64-bit targets that doesn't have true | |
1696 | 64-bit addressing. On these targets, the upper 32 bits of | |
1697 | addresses are ignored by the hardware. Thus, the PC or SP are | |
1698 | likely to have been sign extended to all 1s by instruction | |
1699 | sequences that load 32-bit addresses. For example, a typical | |
1700 | piece of code that loads an address is this: | |
1701 | ||
1702 | lui $r2, <upper 16 bits> | |
1703 | ori $r2, <lower 16 bits> | |
1704 | ||
1705 | But the lui sign-extends the value such that the upper 32 bits | |
1706 | may be all 1s. The workaround is simply to mask off these | |
1707 | bits. In the future, gcc may be changed to support true 64-bit | |
1708 | addressing, and this masking will have to be disabled. */ | |
1709 | return addr &= 0xffffffffUL; | |
1710 | else | |
1711 | return addr; | |
c906108c SS |
1712 | } |
1713 | ||
9022177c DJ |
1714 | /* mips_software_single_step() is called just before we want to resume |
1715 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1716 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1717 | the target of the coming instruction and breakpoint it. |
1718 | ||
1719 | single_step is also called just after the inferior stops. If we had | |
1720 | set up a simulated single-step, we undo our damage. */ | |
1721 | ||
1722 | void | |
1723 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1724 | { | |
1725 | static CORE_ADDR next_pc; | |
1726 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1727 | static binsn_quantum break_mem; | |
1728 | CORE_ADDR pc; | |
1729 | ||
1730 | if (insert_breakpoints_p) | |
1731 | { | |
1732 | pc = read_register (PC_REGNUM); | |
1733 | next_pc = mips_next_pc (pc); | |
1734 | ||
1735 | target_insert_breakpoint (next_pc, break_mem); | |
1736 | } | |
1737 | else | |
1738 | target_remove_breakpoint (next_pc, break_mem); | |
1739 | } | |
1740 | ||
97f46953 | 1741 | static CORE_ADDR |
acdb74a0 | 1742 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1743 | { |
1744 | CORE_ADDR pc, tmp; | |
1745 | ||
11c02a10 | 1746 | pc = ((fromleaf) |
6913c89a | 1747 | ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) |
11c02a10 | 1748 | : get_next_frame (prev) |
8bedc050 | 1749 | ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) |
11c02a10 | 1750 | : read_pc ()); |
5a89d8aa | 1751 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
97f46953 | 1752 | return tmp ? tmp : pc; |
c906108c SS |
1753 | } |
1754 | ||
1755 | ||
f7ab6ec6 | 1756 | static CORE_ADDR |
acdb74a0 | 1757 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1758 | { |
1759 | CORE_ADDR saved_pc; | |
480d3dd2 | 1760 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1761 | |
50abf9e5 | 1762 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 | 1763 | { |
a4b8ebc8 | 1764 | /* Always unwind the cooked PC register value. */ |
dd3ecc14 | 1765 | saved_pc = frame_unwind_register_signed (frame, NUM_REGS + PC_REGNUM); |
cedea778 | 1766 | } |
c906108c | 1767 | else |
a4b8ebc8 AC |
1768 | { |
1769 | mips_extra_func_info_t proc_desc | |
1770 | = get_frame_extra_info (frame)->proc_desc; | |
1771 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) | |
480d3dd2 AC |
1772 | saved_pc = read_memory_integer ((get_frame_base (frame) |
1773 | - mips_saved_regsize (tdep)) | |
1774 | , mips_saved_regsize (tdep)); | |
a4b8ebc8 AC |
1775 | else |
1776 | { | |
1777 | /* We have to get the saved pc from the sigcontext if it is | |
1778 | a signal handler frame. */ | |
1779 | int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME ? PC_REGNUM | |
1780 | : proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); | |
1781 | saved_pc = read_next_frame_reg (frame, NUM_REGS + pcreg); | |
1782 | } | |
1783 | } | |
c906108c SS |
1784 | return ADDR_BITS_REMOVE (saved_pc); |
1785 | } | |
1786 | ||
1787 | static struct mips_extra_func_info temp_proc_desc; | |
fe29b929 KB |
1788 | |
1789 | /* This hack will go away once the get_prev_frame() code has been | |
1790 | modified to set the frame's type first. That is BEFORE init extra | |
1791 | frame info et.al. is called. This is because it will become | |
1792 | possible to skip the init extra info call for sigtramp and dummy | |
1793 | frames. */ | |
1794 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1795 | |
e0f7ec59 AC |
1796 | /* Set a register's saved stack address in temp_saved_regs. If an |
1797 | address has already been set for this register, do nothing; this | |
1798 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
1799 | function prologue. |
1800 | ||
1801 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
1802 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1803 | is used as it is only second range (the ABI instead of ISA | |
1804 | registers) that comes into play when finding saved registers in a | |
1805 | frame. */ | |
c906108c SS |
1806 | |
1807 | static void | |
e0f7ec59 | 1808 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1809 | { |
e0f7ec59 | 1810 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
1811 | { |
1812 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
1813 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
1814 | } | |
c906108c SS |
1815 | } |
1816 | ||
1817 | ||
1818 | /* Test whether the PC points to the return instruction at the | |
1819 | end of a function. */ | |
1820 | ||
c5aa993b | 1821 | static int |
acdb74a0 | 1822 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1823 | { |
1824 | if (pc_is_mips16 (pc)) | |
1825 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1826 | generates a "jr $ra"; other times it generates code to load | |
1827 | the return address from the stack to an accessible register (such | |
1828 | as $a3), then a "jr" using that register. This second case | |
1829 | is almost impossible to distinguish from an indirect jump | |
1830 | used for switch statements, so we don't even try. */ | |
1831 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1832 | else | |
1833 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1834 | } | |
1835 | ||
1836 | ||
1837 | /* This fencepost looks highly suspicious to me. Removing it also | |
1838 | seems suspicious as it could affect remote debugging across serial | |
1839 | lines. */ | |
1840 | ||
1841 | static CORE_ADDR | |
acdb74a0 | 1842 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1843 | { |
c5aa993b JM |
1844 | CORE_ADDR start_pc; |
1845 | CORE_ADDR fence; | |
1846 | int instlen; | |
1847 | int seen_adjsp = 0; | |
c906108c | 1848 | |
c5aa993b JM |
1849 | pc = ADDR_BITS_REMOVE (pc); |
1850 | start_pc = pc; | |
1851 | fence = start_pc - heuristic_fence_post; | |
1852 | if (start_pc == 0) | |
1853 | return 0; | |
c906108c | 1854 | |
c5aa993b JM |
1855 | if (heuristic_fence_post == UINT_MAX |
1856 | || fence < VM_MIN_ADDRESS) | |
1857 | fence = VM_MIN_ADDRESS; | |
c906108c | 1858 | |
c5aa993b | 1859 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1860 | |
c5aa993b JM |
1861 | /* search back for previous return */ |
1862 | for (start_pc -= instlen;; start_pc -= instlen) | |
1863 | if (start_pc < fence) | |
1864 | { | |
1865 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1866 | stop_soon, but with this test, at least we |
c5aa993b JM |
1867 | don't print out warnings for every child forked (eg, on |
1868 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1869 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1870 | { |
c5aa993b JM |
1871 | static int blurb_printed = 0; |
1872 | ||
1873 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1874 | paddr_nz (pc)); | |
1875 | ||
1876 | if (!blurb_printed) | |
c906108c | 1877 | { |
c5aa993b JM |
1878 | /* This actually happens frequently in embedded |
1879 | development, when you first connect to a board | |
1880 | and your stack pointer and pc are nowhere in | |
1881 | particular. This message needs to give people | |
1882 | in that situation enough information to | |
1883 | determine that it's no big deal. */ | |
1884 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1885 | GDB is unable to find the start of the function at 0x%s\n\ |
1886 | and thus can't determine the size of that function's stack frame.\n\ | |
1887 | This means that GDB may be unable to access that stack frame, or\n\ | |
1888 | the frames below it.\n\ | |
1889 | This problem is most likely caused by an invalid program counter or\n\ | |
1890 | stack pointer.\n\ | |
1891 | However, if you think GDB should simply search farther back\n\ | |
1892 | from 0x%s for code which looks like the beginning of a\n\ | |
1893 | function, you can increase the range of the search using the `set\n\ | |
1894 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1895 | paddr_nz (pc), paddr_nz (pc)); |
1896 | blurb_printed = 1; | |
c906108c | 1897 | } |
c906108c SS |
1898 | } |
1899 | ||
c5aa993b JM |
1900 | return 0; |
1901 | } | |
1902 | else if (pc_is_mips16 (start_pc)) | |
1903 | { | |
1904 | unsigned short inst; | |
1905 | ||
1906 | /* On MIPS16, any one of the following is likely to be the | |
1907 | start of a function: | |
1908 | entry | |
1909 | addiu sp,-n | |
1910 | daddiu sp,-n | |
1911 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1912 | inst = mips_fetch_instruction (start_pc); | |
1913 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1914 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1915 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1916 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1917 | break; | |
1918 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1919 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1920 | seen_adjsp = 1; | |
1921 | else | |
1922 | seen_adjsp = 0; | |
1923 | } | |
1924 | else if (mips_about_to_return (start_pc)) | |
1925 | { | |
1926 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1927 | break; | |
1928 | } | |
1929 | ||
c5aa993b | 1930 | return start_pc; |
c906108c SS |
1931 | } |
1932 | ||
1933 | /* Fetch the immediate value from a MIPS16 instruction. | |
1934 | If the previous instruction was an EXTEND, use it to extend | |
1935 | the upper bits of the immediate value. This is a helper function | |
1936 | for mips16_heuristic_proc_desc. */ | |
1937 | ||
1938 | static int | |
acdb74a0 AC |
1939 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1940 | unsigned short inst, /* current instruction */ | |
1941 | int nbits, /* number of bits in imm field */ | |
1942 | int scale, /* scale factor to be applied to imm */ | |
1943 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1944 | { |
1945 | int offset; | |
1946 | ||
1947 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1948 | { | |
1949 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1950 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1951 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1952 | return offset | (inst & 0x1f); | |
1953 | } | |
1954 | else | |
1955 | { | |
1956 | int max_imm = 1 << nbits; | |
1957 | int mask = max_imm - 1; | |
1958 | int sign_bit = max_imm >> 1; | |
1959 | ||
1960 | offset = inst & mask; | |
1961 | if (is_signed && (offset & sign_bit)) | |
1962 | offset = 0 - (max_imm - offset); | |
1963 | return offset * scale; | |
1964 | } | |
1965 | } | |
1966 | ||
1967 | ||
1968 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1969 | stream from start_pc to limit_pc. */ | |
1970 | ||
1971 | static void | |
acdb74a0 AC |
1972 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1973 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1974 | { |
1975 | CORE_ADDR cur_pc; | |
1976 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1977 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1978 | unsigned inst = 0; /* current instruction */ | |
1979 | unsigned entry_inst = 0; /* the entry instruction */ | |
1980 | int reg, offset; | |
480d3dd2 | 1981 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1982 | |
c5aa993b JM |
1983 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1984 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1985 | |
1986 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1987 | { | |
1988 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1989 | the immediate offset extension from it in mips16_get_imm. */ | |
1990 | prev_inst = inst; | |
1991 | ||
1992 | /* Fetch and decode the instruction. */ | |
1993 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1994 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1995 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1996 | { | |
1997 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1998 | if (offset < 0) /* negative stack adjustment? */ |
1999 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2000 | else |
2001 | /* Exit loop if a positive stack adjustment is found, which | |
2002 | usually means that the stack cleanup code in the function | |
2003 | epilogue is reached. */ | |
2004 | break; | |
2005 | } | |
2006 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2007 | { | |
2008 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2009 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2010 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2011 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2012 | } |
2013 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2014 | { | |
2015 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2016 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2017 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2018 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2019 | } |
2020 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2021 | { | |
2022 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2023 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2024 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2025 | } |
2026 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2027 | { | |
2028 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2029 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2030 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2031 | } |
c5aa993b | 2032 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2033 | { |
2034 | frame_addr = sp; | |
2035 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2036 | } | |
2037 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2038 | { | |
2039 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2040 | frame_addr = sp + offset; | |
2041 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2042 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2043 | } | |
2044 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2045 | { | |
2046 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2047 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2048 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2049 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2050 | } |
2051 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2052 | { | |
2053 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2054 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2055 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2056 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2057 | } |
c5aa993b JM |
2058 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2059 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2060 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2061 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2062 | } |
2063 | ||
c5aa993b JM |
2064 | /* The entry instruction is typically the first instruction in a function, |
2065 | and it stores registers at offsets relative to the value of the old SP | |
2066 | (before the prologue). But the value of the sp parameter to this | |
2067 | function is the new SP (after the prologue has been executed). So we | |
2068 | can't calculate those offsets until we've seen the entire prologue, | |
2069 | and can calculate what the old SP must have been. */ | |
2070 | if (entry_inst != 0) | |
2071 | { | |
2072 | int areg_count = (entry_inst >> 8) & 7; | |
2073 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2074 | |
c5aa993b JM |
2075 | /* The entry instruction always subtracts 32 from the SP. */ |
2076 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2077 | |
c5aa993b JM |
2078 | /* Now we can calculate what the SP must have been at the |
2079 | start of the function prologue. */ | |
2080 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2081 | |
c5aa993b JM |
2082 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2083 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2084 | { | |
2085 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2086 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
480d3dd2 | 2087 | offset += mips_saved_regsize (tdep); |
c5aa993b | 2088 | } |
c906108c | 2089 | |
c5aa993b JM |
2090 | /* Check if the ra register was pushed on the stack. */ |
2091 | offset = -4; | |
2092 | if (entry_inst & 0x20) | |
2093 | { | |
2094 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2095 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
480d3dd2 | 2096 | offset -= mips_saved_regsize (tdep); |
c5aa993b | 2097 | } |
c906108c | 2098 | |
c5aa993b JM |
2099 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2100 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2101 | { | |
2102 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2103 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
480d3dd2 | 2104 | offset -= mips_saved_regsize (tdep); |
c5aa993b JM |
2105 | } |
2106 | } | |
c906108c SS |
2107 | } |
2108 | ||
2109 | static void | |
fba45db2 KB |
2110 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2111 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2112 | { |
2113 | CORE_ADDR cur_pc; | |
c5aa993b | 2114 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2115 | restart: |
fe29b929 | 2116 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2117 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2118 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2119 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2120 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2121 | { | |
2122 | unsigned long inst, high_word, low_word; | |
2123 | int reg; | |
2124 | ||
2125 | /* Fetch the instruction. */ | |
2126 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2127 | ||
2128 | /* Save some code by pre-extracting some useful fields. */ | |
2129 | high_word = (inst >> 16) & 0xffff; | |
2130 | low_word = inst & 0xffff; | |
2131 | reg = high_word & 0x1f; | |
2132 | ||
c5aa993b | 2133 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2134 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2135 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2136 | { | |
2137 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2138 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2139 | else |
2140 | /* Exit loop if a positive stack adjustment is found, which | |
2141 | usually means that the stack cleanup code in the function | |
2142 | epilogue is reached. */ | |
2143 | break; | |
2144 | } | |
2145 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2146 | { | |
c5aa993b | 2147 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2148 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2149 | } |
2150 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2151 | { | |
2152 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2153 | but the register size used is only 32 bits. Make the address | |
2154 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2155 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
4246e332 | 2156 | set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - mips_regsize (current_gdbarch)); |
c906108c | 2157 | } |
c5aa993b | 2158 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2159 | { |
2160 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2161 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2162 | frame_addr = sp + low_word; | |
c906108c SS |
2163 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2164 | { | |
2165 | unsigned alloca_adjust; | |
2166 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2167 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2168 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2169 | if (alloca_adjust > 0) |
2170 | { | |
2171 | /* FP > SP + frame_size. This may be because | |
2172 | * of an alloca or somethings similar. | |
2173 | * Fix sp to "pre-alloca" value, and try again. | |
2174 | */ | |
2175 | sp += alloca_adjust; | |
2176 | goto restart; | |
2177 | } | |
2178 | } | |
2179 | } | |
c5aa993b JM |
2180 | /* move $30,$sp. With different versions of gas this will be either |
2181 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2182 | Accept any one of these. */ | |
c906108c SS |
2183 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2184 | { | |
2185 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2186 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2187 | { | |
2188 | unsigned alloca_adjust; | |
2189 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2190 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2191 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2192 | if (alloca_adjust > 0) |
2193 | { | |
2194 | /* FP > SP + frame_size. This may be because | |
2195 | * of an alloca or somethings similar. | |
2196 | * Fix sp to "pre-alloca" value, and try again. | |
2197 | */ | |
2198 | sp += alloca_adjust; | |
2199 | goto restart; | |
2200 | } | |
2201 | } | |
2202 | } | |
c5aa993b | 2203 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2204 | { |
c5aa993b | 2205 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2206 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2207 | } |
2208 | } | |
2209 | } | |
2210 | ||
2211 | static mips_extra_func_info_t | |
acdb74a0 | 2212 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2213 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2214 | { |
479412cd DJ |
2215 | CORE_ADDR sp; |
2216 | ||
2217 | if (cur_frame) | |
a4b8ebc8 | 2218 | sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); |
479412cd DJ |
2219 | else |
2220 | sp = 0; | |
c906108c | 2221 | |
c5aa993b JM |
2222 | if (start_pc == 0) |
2223 | return NULL; | |
2224 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2225 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2226 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2227 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2228 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2229 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2230 | ||
2231 | if (start_pc + 200 < limit_pc) | |
2232 | limit_pc = start_pc + 200; | |
2233 | if (pc_is_mips16 (start_pc)) | |
2234 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2235 | else | |
2236 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2237 | return &temp_proc_desc; | |
2238 | } | |
2239 | ||
6c0d6680 DJ |
2240 | struct mips_objfile_private |
2241 | { | |
2242 | bfd_size_type size; | |
2243 | char *contents; | |
2244 | }; | |
2245 | ||
2246 | /* Global used to communicate between non_heuristic_proc_desc and | |
2247 | compare_pdr_entries within qsort (). */ | |
2248 | static bfd *the_bfd; | |
2249 | ||
2250 | static int | |
2251 | compare_pdr_entries (const void *a, const void *b) | |
2252 | { | |
2253 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2254 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2255 | ||
2256 | if (lhs < rhs) | |
2257 | return -1; | |
2258 | else if (lhs == rhs) | |
2259 | return 0; | |
2260 | else | |
2261 | return 1; | |
2262 | } | |
2263 | ||
c906108c | 2264 | static mips_extra_func_info_t |
acdb74a0 | 2265 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2266 | { |
2267 | CORE_ADDR startaddr; | |
2268 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2269 | struct block *b = block_for_pc (pc); |
c906108c | 2270 | struct symbol *sym; |
6c0d6680 DJ |
2271 | struct obj_section *sec; |
2272 | struct mips_objfile_private *priv; | |
2273 | ||
ae45cd16 | 2274 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2275 | return NULL; |
c906108c SS |
2276 | |
2277 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2278 | if (addrptr) | |
2279 | *addrptr = startaddr; | |
6c0d6680 DJ |
2280 | |
2281 | priv = NULL; | |
2282 | ||
2283 | sec = find_pc_section (pc); | |
2284 | if (sec != NULL) | |
c906108c | 2285 | { |
6c0d6680 DJ |
2286 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2287 | ||
2288 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2289 | the information normally found in ECOFF PDRs. */ | |
2290 | ||
2291 | the_bfd = sec->objfile->obfd; | |
2292 | if (priv == NULL | |
2293 | && (the_bfd->format == bfd_object | |
2294 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2295 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2296 | { | |
2297 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2298 | This means that we should not bother with this method on 64-bit | |
2299 | targets (until that is fixed). */ | |
2300 | ||
2301 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2302 | sizeof (struct mips_objfile_private)); | |
2303 | priv->size = 0; | |
2304 | sec->objfile->obj_private = priv; | |
2305 | } | |
2306 | else if (priv == NULL) | |
2307 | { | |
2308 | asection *bfdsec; | |
2309 | ||
2310 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2311 | sizeof (struct mips_objfile_private)); | |
2312 | ||
2313 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2314 | if (bfdsec != NULL) | |
2315 | { | |
2316 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2317 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2318 | priv->size); | |
2319 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2320 | priv->contents, 0, priv->size); | |
2321 | ||
2322 | /* In general, the .pdr section is sorted. However, in the | |
2323 | presence of multiple code sections (and other corner cases) | |
2324 | it can become unsorted. Sort it so that we can use a faster | |
2325 | binary search. */ | |
2326 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2327 | } | |
2328 | else | |
2329 | priv->size = 0; | |
2330 | ||
2331 | sec->objfile->obj_private = priv; | |
2332 | } | |
2333 | the_bfd = NULL; | |
2334 | ||
2335 | if (priv->size != 0) | |
2336 | { | |
2337 | int low, mid, high; | |
2338 | char *ptr; | |
2339 | ||
2340 | low = 0; | |
2341 | high = priv->size / 32; | |
2342 | ||
2343 | do | |
2344 | { | |
2345 | CORE_ADDR pdr_pc; | |
2346 | ||
2347 | mid = (low + high) / 2; | |
2348 | ||
2349 | ptr = priv->contents + mid * 32; | |
2350 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2351 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2352 | SECT_OFF_TEXT (sec->objfile)); | |
2353 | if (pdr_pc == startaddr) | |
2354 | break; | |
2355 | if (pdr_pc > startaddr) | |
2356 | high = mid; | |
2357 | else | |
2358 | low = mid + 1; | |
2359 | } | |
2360 | while (low != high); | |
2361 | ||
2362 | if (low != high) | |
2363 | { | |
2364 | struct symbol *sym = find_pc_function (pc); | |
2365 | ||
2366 | /* Fill in what we need of the proc_desc. */ | |
2367 | proc_desc = (mips_extra_func_info_t) | |
2368 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2369 | sizeof (struct mips_extra_func_info)); | |
2370 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2371 | ||
2372 | /* Only used for dummy frames. */ | |
2373 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2374 | ||
2375 | PROC_FRAME_OFFSET (proc_desc) | |
2376 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2377 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2378 | ptr + 24); | |
2379 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2380 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2381 | ptr + 4); | |
2382 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2383 | ptr + 12); | |
2384 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2385 | ptr + 8); | |
2386 | PROC_FREG_OFFSET (proc_desc) | |
2387 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2388 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2389 | ptr + 28); | |
2390 | proc_desc->pdr.isym = (long) sym; | |
2391 | ||
2392 | return proc_desc; | |
2393 | } | |
2394 | } | |
c906108c SS |
2395 | } |
2396 | ||
6c0d6680 DJ |
2397 | if (b == NULL) |
2398 | return NULL; | |
2399 | ||
2400 | if (startaddr > BLOCK_START (b)) | |
2401 | { | |
2402 | /* This is the "pathological" case referred to in a comment in | |
2403 | print_frame_info. It might be better to move this check into | |
2404 | symbol reading. */ | |
2405 | return NULL; | |
2406 | } | |
2407 | ||
176620f1 | 2408 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2409 | |
c906108c SS |
2410 | /* If we never found a PDR for this function in symbol reading, then |
2411 | examine prologues to find the information. */ | |
2412 | if (sym) | |
2413 | { | |
2414 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2415 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2416 | return NULL; | |
2417 | else | |
2418 | return proc_desc; | |
2419 | } | |
2420 | else | |
2421 | return NULL; | |
2422 | } | |
2423 | ||
2424 | ||
2425 | static mips_extra_func_info_t | |
479412cd | 2426 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2427 | { |
2428 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2429 | CORE_ADDR startaddr = 0; |
c906108c SS |
2430 | |
2431 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2432 | ||
2433 | if (proc_desc) | |
2434 | { | |
2435 | /* IF this is the topmost frame AND | |
2436 | * (this proc does not have debugging information OR | |
2437 | * the PC is in the procedure prologue) | |
2438 | * THEN create a "heuristic" proc_desc (by analyzing | |
2439 | * the actual code) to replace the "official" proc_desc. | |
2440 | */ | |
2441 | if (next_frame == NULL) | |
2442 | { | |
2443 | struct symtab_and_line val; | |
2444 | struct symbol *proc_symbol = | |
c86b5b38 | 2445 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2446 | |
2447 | if (proc_symbol) | |
2448 | { | |
2449 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2450 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2451 | 0); |
2452 | val.pc = val.end ? val.end : pc; | |
2453 | } | |
2454 | if (!proc_symbol || pc < val.pc) | |
2455 | { | |
2456 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2457 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2458 | pc, next_frame, cur_frame); | |
c906108c SS |
2459 | if (found_heuristic) |
2460 | proc_desc = found_heuristic; | |
2461 | } | |
2462 | } | |
2463 | } | |
2464 | else | |
2465 | { | |
2466 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2467 | by procedure call dummys. However, the procedures being called ought |
2468 | to have their own proc_descs, and even if they don't, | |
2469 | heuristic_proc_desc knows how to create them! */ | |
c906108c | 2470 | |
aa1ee363 | 2471 | struct linked_proc_info *link; |
c906108c SS |
2472 | |
2473 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2474 | if (PROC_LOW_ADDR (&link->info) <= pc |
2475 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2476 | return &link->info; |
2477 | ||
2478 | if (startaddr == 0) | |
2479 | startaddr = heuristic_proc_start (pc); | |
2480 | ||
2481 | proc_desc = | |
479412cd | 2482 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2483 | } |
2484 | return proc_desc; | |
2485 | } | |
2486 | ||
2487 | static CORE_ADDR | |
acdb74a0 AC |
2488 | get_frame_pointer (struct frame_info *frame, |
2489 | mips_extra_func_info_t proc_desc) | |
c906108c | 2490 | { |
a4b8ebc8 | 2491 | return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) |
e227b13c AC |
2492 | + PROC_FRAME_OFFSET (proc_desc) |
2493 | - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2494 | } |
2495 | ||
5a89d8aa | 2496 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2497 | |
f7ab6ec6 | 2498 | static CORE_ADDR |
acdb74a0 | 2499 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2500 | { |
2501 | mips_extra_func_info_t proc_desc; | |
2502 | CORE_ADDR tmp; | |
8bedc050 | 2503 | CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); |
c906108c | 2504 | |
c906108c SS |
2505 | /* Check if the PC is inside a call stub. If it is, fetch the |
2506 | PC of the caller of that stub. */ | |
5a89d8aa | 2507 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2508 | saved_pc = tmp; |
2509 | ||
ae45cd16 | 2510 | if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0)) |
cedea778 AC |
2511 | { |
2512 | /* A dummy frame, uses SP not FP. Get the old SP value. If all | |
2513 | is well, frame->frame the bottom of the current frame will | |
2514 | contain that value. */ | |
1e2330ba | 2515 | return get_frame_base (frame); |
cedea778 AC |
2516 | } |
2517 | ||
c906108c | 2518 | /* Look up the procedure descriptor for this PC. */ |
479412cd | 2519 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2520 | if (!proc_desc) |
2521 | return 0; | |
2522 | ||
2523 | cached_proc_desc = proc_desc; | |
2524 | ||
2525 | /* If no frame pointer and frame size is zero, we must be at end | |
2526 | of stack (or otherwise hosed). If we don't check frame size, | |
2527 | we loop forever if we see a zero size frame. */ | |
2528 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2529 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2530 | /* The previous frame from a sigtramp frame might be frameless |
2531 | and have frame size zero. */ | |
5a203e44 | 2532 | && !(get_frame_type (frame) == SIGTRAMP_FRAME) |
cedea778 AC |
2533 | /* For a generic dummy frame, let get_frame_pointer() unwind a |
2534 | register value saved as part of the dummy frame call. */ | |
50abf9e5 | 2535 | && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))) |
c906108c SS |
2536 | return 0; |
2537 | else | |
2538 | return get_frame_pointer (frame, proc_desc); | |
2539 | } | |
2540 | ||
f7ab6ec6 | 2541 | static void |
acdb74a0 | 2542 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2543 | { |
2544 | int regnum; | |
f2c16bd6 KB |
2545 | mips_extra_func_info_t proc_desc; |
2546 | ||
2547 | if (get_frame_type (fci) == DUMMY_FRAME) | |
2548 | return; | |
c906108c | 2549 | |
f796e4be KB |
2550 | /* Use proc_desc calculated in frame_chain. When there is no |
2551 | next frame, i.e, get_next_frame (fci) == NULL, we call | |
2552 | find_proc_desc () to calculate it, passing an explicit | |
2553 | NULL as the frame parameter. */ | |
f2c16bd6 | 2554 | proc_desc = |
11c02a10 AC |
2555 | get_next_frame (fci) |
2556 | ? cached_proc_desc | |
f796e4be KB |
2557 | : find_proc_desc (get_frame_pc (fci), |
2558 | NULL /* i.e, get_next_frame (fci) */, | |
2559 | 1); | |
c906108c | 2560 | |
a00a19e9 | 2561 | frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); |
cce74817 | 2562 | |
da50a4b7 | 2563 | get_frame_extra_info (fci)->proc_desc = |
c906108c SS |
2564 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2565 | if (proc_desc) | |
2566 | { | |
2567 | /* Fixup frame-pointer - only needed for top frame */ | |
2568 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2569 | Get the value of the frame relative sp, procedure might have been |
2570 | interrupted by a signal at it's very start. */ | |
50abf9e5 | 2571 | if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) |
c906108c | 2572 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
a4b8ebc8 | 2573 | deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), NUM_REGS + SP_REGNUM)); |
50abf9e5 | 2574 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) |
cedea778 AC |
2575 | /* Do not ``fix'' fci->frame. It will have the value of the |
2576 | generic dummy frame's top-of-stack (since the draft | |
2577 | fci->frame is obtained by returning the unwound stack | |
2578 | pointer) and that is what we want. That way the fci->frame | |
2579 | value will match the top-of-stack value that was saved as | |
2580 | part of the dummy frames data. */ | |
2581 | /* Do nothing. */; | |
c906108c | 2582 | else |
11c02a10 | 2583 | deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc)); |
c906108c SS |
2584 | |
2585 | if (proc_desc == &temp_proc_desc) | |
2586 | { | |
2587 | char *name; | |
2588 | ||
2589 | /* Do not set the saved registers for a sigtramp frame, | |
5a203e44 AC |
2590 | mips_find_saved_registers will do that for us. We can't |
2591 | use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not | |
2592 | yet set. */ | |
2593 | /* FIXME: cagney/2002-11-18: This problem will go away once | |
2594 | frame.c:get_prev_frame() is modified to set the frame's | |
2595 | type before calling functions like this. */ | |
50abf9e5 | 2596 | find_pc_partial_function (get_frame_pc (fci), &name, |
c5aa993b | 2597 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
50abf9e5 | 2598 | if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name)) |
c906108c | 2599 | { |
c5aa993b | 2600 | frame_saved_regs_zalloc (fci); |
e0f7ec59 AC |
2601 | /* Set value of previous frame's stack pointer. |
2602 | Remember that saved_regs[SP_REGNUM] is special in | |
2603 | that it contains the value of the stack pointer | |
2604 | register. The other saved_regs values are addresses | |
2605 | (in the inferior) at which a given register's value | |
2606 | may be found. */ | |
2607 | set_reg_offset (temp_saved_regs, SP_REGNUM, | |
2608 | get_frame_base (fci)); | |
2609 | set_reg_offset (temp_saved_regs, PC_REGNUM, | |
2610 | temp_saved_regs[RA_REGNUM]); | |
1b1d3794 | 2611 | memcpy (deprecated_get_frame_saved_regs (fci), temp_saved_regs, |
e0f7ec59 | 2612 | SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2613 | } |
2614 | } | |
2615 | ||
2616 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 | 2617 | /* assume we can't tell how many args for now */ |
da50a4b7 | 2618 | get_frame_extra_info (fci)->num_args = -1; |
c906108c SS |
2619 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2620 | { | |
c5aa993b | 2621 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2622 | { |
da50a4b7 | 2623 | get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2624 | break; |
2625 | } | |
c5aa993b | 2626 | } |
c906108c SS |
2627 | } |
2628 | } | |
2629 | ||
2630 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2631 | we basically have to look at symbol information for the function | |
2632 | that we stopped in, which tells us *which* register (if any) is | |
2633 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2634 | the frame itself is at. |
c906108c SS |
2635 | |
2636 | This presents a problem when trying to examine a stack in memory | |
2637 | (that isn't executing at the moment), using the "frame" command. We | |
2638 | don't have a PC, nor do we have any registers except SP. | |
2639 | ||
2640 | This routine takes two arguments, SP and PC, and tries to make the | |
2641 | cached frames look as if these two arguments defined a frame on the | |
2642 | cache. This allows the rest of info frame to extract the important | |
2643 | arguments without difficulty. */ | |
2644 | ||
2645 | struct frame_info * | |
acdb74a0 | 2646 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2647 | { |
2648 | if (argc != 2) | |
2649 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2650 | ||
2651 | return create_new_frame (argv[0], argv[1]); | |
2652 | } | |
2653 | ||
f09ded24 AC |
2654 | /* According to the current ABI, should the type be passed in a |
2655 | floating-point register (assuming that there is space)? When there | |
2656 | is no FPU, FP are not even considered as possibile candidates for | |
2657 | FP registers and, consequently this returns false - forces FP | |
2658 | arguments into integer registers. */ | |
2659 | ||
2660 | static int | |
2661 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2662 | { | |
2663 | return ((typecode == TYPE_CODE_FLT | |
2664 | || (MIPS_EABI | |
2665 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2666 | && TYPE_NFIELDS (arg_type) == 1 | |
2667 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2668 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2669 | } |
2670 | ||
49e790b0 DJ |
2671 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2672 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2673 | ||
2674 | static int | |
2675 | mips_type_needs_double_align (struct type *type) | |
2676 | { | |
2677 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2678 | |
49e790b0 DJ |
2679 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2680 | return 1; | |
2681 | else if (typecode == TYPE_CODE_STRUCT) | |
2682 | { | |
2683 | if (TYPE_NFIELDS (type) < 1) | |
2684 | return 0; | |
2685 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2686 | } | |
2687 | else if (typecode == TYPE_CODE_UNION) | |
2688 | { | |
361d1df0 | 2689 | int i, n; |
49e790b0 DJ |
2690 | |
2691 | n = TYPE_NFIELDS (type); | |
2692 | for (i = 0; i < n; i++) | |
2693 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2694 | return 1; | |
2695 | return 0; | |
2696 | } | |
2697 | return 0; | |
2698 | } | |
2699 | ||
dc604539 AC |
2700 | /* Adjust the address downward (direction of stack growth) so that it |
2701 | is correctly aligned for a new stack frame. */ | |
2702 | static CORE_ADDR | |
2703 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2704 | { | |
5b03f266 | 2705 | return align_down (addr, 16); |
dc604539 AC |
2706 | } |
2707 | ||
f7ab6ec6 | 2708 | static CORE_ADDR |
25ab4790 AC |
2709 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2710 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2711 | struct value **args, CORE_ADDR sp, int struct_return, | |
2712 | CORE_ADDR struct_addr) | |
c906108c SS |
2713 | { |
2714 | int argreg; | |
2715 | int float_argreg; | |
2716 | int argnum; | |
2717 | int len = 0; | |
2718 | int stack_offset = 0; | |
480d3dd2 | 2719 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c906108c | 2720 | |
25ab4790 AC |
2721 | /* For shared libraries, "t9" needs to point at the function |
2722 | address. */ | |
2723 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2724 | ||
2725 | /* Set the return address register to point to the entry point of | |
2726 | the program, where a breakpoint lies in wait. */ | |
2727 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2728 | ||
c906108c | 2729 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2730 | are properly aligned. The stack has to be at least 64-bit |
2731 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2732 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2733 | aligned, so we round to this widest known alignment. */ | |
2734 | ||
5b03f266 AC |
2735 | sp = align_down (sp, 16); |
2736 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2737 | |
46e0f506 | 2738 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2739 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2740 | passed in registers, but that's OK. */ |
c906108c | 2741 | for (argnum = 0; argnum < nargs; argnum++) |
5b03f266 | 2742 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 2743 | mips_stack_argsize (tdep)); |
5b03f266 | 2744 | sp -= align_up (len, 16); |
c906108c | 2745 | |
9ace0497 | 2746 | if (mips_debug) |
46e0f506 | 2747 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2748 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2749 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2750 | |
c906108c SS |
2751 | /* Initialize the integer and float register pointers. */ |
2752 | argreg = A0_REGNUM; | |
56cea623 | 2753 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2754 | |
46e0f506 | 2755 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2756 | if (struct_return) |
9ace0497 AC |
2757 | { |
2758 | if (mips_debug) | |
2759 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2760 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2761 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2762 | write_register (argreg++, struct_addr); |
2763 | } | |
c906108c SS |
2764 | |
2765 | /* Now load as many as possible of the first arguments into | |
2766 | registers, and push the rest onto the stack. Loop thru args | |
2767 | from first to last. */ | |
2768 | for (argnum = 0; argnum < nargs; argnum++) | |
2769 | { | |
2770 | char *val; | |
d9d9c31f | 2771 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2772 | struct value *arg = args[argnum]; |
c906108c SS |
2773 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2774 | int len = TYPE_LENGTH (arg_type); | |
2775 | enum type_code typecode = TYPE_CODE (arg_type); | |
2776 | ||
9ace0497 AC |
2777 | if (mips_debug) |
2778 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2779 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2780 | argnum + 1, len, (int) typecode); |
9ace0497 | 2781 | |
c906108c | 2782 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2783 | reference. */ |
480d3dd2 | 2784 | if (len > mips_saved_regsize (tdep) |
9ace0497 | 2785 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2786 | { |
480d3dd2 AC |
2787 | store_unsigned_integer (valbuf, mips_saved_regsize (tdep), |
2788 | VALUE_ADDRESS (arg)); | |
c906108c | 2789 | typecode = TYPE_CODE_PTR; |
480d3dd2 | 2790 | len = mips_saved_regsize (tdep); |
c906108c | 2791 | val = valbuf; |
9ace0497 AC |
2792 | if (mips_debug) |
2793 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2794 | } |
2795 | else | |
c5aa993b | 2796 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2797 | |
2798 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2799 | even-numbered floating point register. Round the FP register |
2800 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2801 | left. Non MIPS_EABI targets also pass the FP in the integer |
2802 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2803 | if (!FP_REGISTER_DOUBLE |
2804 | && fp_register_arg_p (typecode, arg_type)) | |
2805 | { | |
2806 | if ((float_argreg & 1)) | |
2807 | float_argreg++; | |
2808 | } | |
c906108c SS |
2809 | |
2810 | /* Floating point arguments passed in registers have to be | |
2811 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2812 | are passed in register pairs; the even register gets |
2813 | the low word, and the odd register gets the high word. | |
2814 | On non-EABI processors, the first two floating point arguments are | |
2815 | also copied to general registers, because MIPS16 functions | |
2816 | don't use float registers for arguments. This duplication of | |
2817 | arguments in general registers can't hurt non-MIPS16 functions | |
2818 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2819 | /* MIPS_EABI squeezes a struct that contains a single floating |
2820 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2821 | stack. */ |
f09ded24 AC |
2822 | if (fp_register_arg_p (typecode, arg_type) |
2823 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2824 | { |
2825 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2826 | { | |
d7449b42 | 2827 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2828 | unsigned long regval; |
2829 | ||
2830 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2831 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2832 | if (mips_debug) |
acdb74a0 | 2833 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2834 | float_argreg, phex (regval, 4)); |
c906108c | 2835 | write_register (float_argreg++, regval); |
c906108c SS |
2836 | |
2837 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2838 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2839 | if (mips_debug) |
acdb74a0 | 2840 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2841 | float_argreg, phex (regval, 4)); |
c906108c | 2842 | write_register (float_argreg++, regval); |
c906108c SS |
2843 | } |
2844 | else | |
2845 | { | |
2846 | /* This is a floating point value that fits entirely | |
2847 | in a single register. */ | |
53a5351d | 2848 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2849 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2850 | LONGEST regval = extract_unsigned_integer (val, len); |
2851 | if (mips_debug) | |
acdb74a0 | 2852 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2853 | float_argreg, phex (regval, len)); |
c906108c | 2854 | write_register (float_argreg++, regval); |
c906108c SS |
2855 | } |
2856 | } | |
2857 | else | |
2858 | { | |
2859 | /* Copy the argument to general registers or the stack in | |
2860 | register-sized pieces. Large arguments are split between | |
2861 | registers and stack. */ | |
4246e332 AC |
2862 | /* Note: structs whose size is not a multiple of |
2863 | mips_regsize() are treated specially: Irix cc passes them | |
2864 | in registers where gcc sometimes puts them on the stack. | |
2865 | For maximum compatibility, we will put them in both | |
2866 | places. */ | |
480d3dd2 AC |
2867 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
2868 | && (len % mips_saved_regsize (tdep) != 0)); | |
46e0f506 | 2869 | |
f09ded24 | 2870 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2871 | register are only written to memory. */ |
c906108c SS |
2872 | while (len > 0) |
2873 | { | |
ebafbe83 | 2874 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2875 | int stack_used_p = 0; |
480d3dd2 AC |
2876 | int partial_len = (len < mips_saved_regsize (tdep) |
2877 | ? len : mips_saved_regsize (tdep)); | |
c906108c | 2878 | |
acdb74a0 AC |
2879 | if (mips_debug) |
2880 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2881 | partial_len); | |
2882 | ||
566f0f7a | 2883 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2884 | if (argreg > MIPS_LAST_ARG_REGNUM |
2885 | || odd_sized_struct | |
2886 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2887 | { |
c906108c SS |
2888 | /* Should shorter than int integer values be |
2889 | promoted to int before being stored? */ | |
c906108c | 2890 | int longword_offset = 0; |
9ace0497 | 2891 | CORE_ADDR addr; |
566f0f7a | 2892 | stack_used_p = 1; |
d7449b42 | 2893 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2894 | { |
480d3dd2 AC |
2895 | if (mips_stack_argsize (tdep) == 8 |
2896 | && (typecode == TYPE_CODE_INT | |
2897 | || typecode == TYPE_CODE_PTR | |
2898 | || typecode == TYPE_CODE_FLT) | |
2899 | && len <= 4) | |
2900 | longword_offset = mips_stack_argsize (tdep) - len; | |
2901 | else if ((typecode == TYPE_CODE_STRUCT | |
2902 | || typecode == TYPE_CODE_UNION) | |
2903 | && (TYPE_LENGTH (arg_type) | |
2904 | < mips_stack_argsize (tdep))) | |
2905 | longword_offset = mips_stack_argsize (tdep) - len; | |
7a292a7a | 2906 | } |
c5aa993b | 2907 | |
9ace0497 AC |
2908 | if (mips_debug) |
2909 | { | |
cb3d25d1 MS |
2910 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2911 | paddr_nz (stack_offset)); | |
2912 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2913 | paddr_nz (longword_offset)); | |
9ace0497 | 2914 | } |
361d1df0 | 2915 | |
9ace0497 AC |
2916 | addr = sp + stack_offset + longword_offset; |
2917 | ||
2918 | if (mips_debug) | |
2919 | { | |
2920 | int i; | |
cb3d25d1 MS |
2921 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2922 | paddr_nz (addr)); | |
9ace0497 AC |
2923 | for (i = 0; i < partial_len; i++) |
2924 | { | |
cb3d25d1 MS |
2925 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2926 | val[i] & 0xff); | |
9ace0497 AC |
2927 | } |
2928 | } | |
2929 | write_memory (addr, val, partial_len); | |
c906108c SS |
2930 | } |
2931 | ||
f09ded24 AC |
2932 | /* Note!!! This is NOT an else clause. Odd sized |
2933 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2934 | arguments will not. */ |
566f0f7a | 2935 | /* Write this portion of the argument to a general |
46e0f506 | 2936 | purpose register. */ |
f09ded24 AC |
2937 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2938 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2939 | { |
9ace0497 | 2940 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2941 | |
9ace0497 | 2942 | if (mips_debug) |
acdb74a0 | 2943 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2944 | argreg, |
480d3dd2 | 2945 | phex (regval, mips_saved_regsize (tdep))); |
c906108c SS |
2946 | write_register (argreg, regval); |
2947 | argreg++; | |
c906108c | 2948 | } |
c5aa993b | 2949 | |
c906108c SS |
2950 | len -= partial_len; |
2951 | val += partial_len; | |
2952 | ||
566f0f7a AC |
2953 | /* Compute the the offset into the stack at which we |
2954 | will copy the next parameter. | |
2955 | ||
566f0f7a | 2956 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2957 | only needs to be adjusted when it has been used. */ |
c906108c | 2958 | |
46e0f506 | 2959 | if (stack_used_p) |
480d3dd2 AC |
2960 | stack_offset += align_up (partial_len, |
2961 | mips_stack_argsize (tdep)); | |
c906108c SS |
2962 | } |
2963 | } | |
9ace0497 AC |
2964 | if (mips_debug) |
2965 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2966 | } |
2967 | ||
310e9b6a AC |
2968 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
2969 | ||
0f71a2f6 JM |
2970 | /* Return adjusted stack pointer. */ |
2971 | return sp; | |
2972 | } | |
2973 | ||
25ab4790 | 2974 | /* N32/N64 version of push_dummy_call. */ |
ebafbe83 | 2975 | |
f7ab6ec6 | 2976 | static CORE_ADDR |
25ab4790 AC |
2977 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2978 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2979 | struct value **args, CORE_ADDR sp, int struct_return, | |
2980 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2981 | { |
2982 | int argreg; | |
2983 | int float_argreg; | |
2984 | int argnum; | |
2985 | int len = 0; | |
2986 | int stack_offset = 0; | |
480d3dd2 | 2987 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cb3d25d1 | 2988 | |
25ab4790 AC |
2989 | /* For shared libraries, "t9" needs to point at the function |
2990 | address. */ | |
2991 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2992 | ||
2993 | /* Set the return address register to point to the entry point of | |
2994 | the program, where a breakpoint lies in wait. */ | |
2995 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2996 | ||
cb3d25d1 MS |
2997 | /* First ensure that the stack and structure return address (if any) |
2998 | are properly aligned. The stack has to be at least 64-bit | |
2999 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3000 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3001 | aligned, so we round to this widest known alignment. */ | |
3002 | ||
5b03f266 AC |
3003 | sp = align_down (sp, 16); |
3004 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3005 | |
3006 | /* Now make space on the stack for the args. */ | |
3007 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3008 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 3009 | mips_stack_argsize (tdep)); |
5b03f266 | 3010 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3011 | |
3012 | if (mips_debug) | |
3013 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3014 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3015 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3016 | |
3017 | /* Initialize the integer and float register pointers. */ | |
3018 | argreg = A0_REGNUM; | |
56cea623 | 3019 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3020 | |
46e0f506 | 3021 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3022 | if (struct_return) |
3023 | { | |
3024 | if (mips_debug) | |
3025 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3026 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3027 | argreg, paddr_nz (struct_addr)); |
3028 | write_register (argreg++, struct_addr); | |
3029 | } | |
3030 | ||
3031 | /* Now load as many as possible of the first arguments into | |
3032 | registers, and push the rest onto the stack. Loop thru args | |
3033 | from first to last. */ | |
3034 | for (argnum = 0; argnum < nargs; argnum++) | |
3035 | { | |
3036 | char *val; | |
d9d9c31f | 3037 | char valbuf[MAX_REGISTER_SIZE]; |
cb3d25d1 MS |
3038 | struct value *arg = args[argnum]; |
3039 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3040 | int len = TYPE_LENGTH (arg_type); | |
3041 | enum type_code typecode = TYPE_CODE (arg_type); | |
3042 | ||
3043 | if (mips_debug) | |
3044 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3045 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3046 | argnum + 1, len, (int) typecode); |
3047 | ||
3048 | val = (char *) VALUE_CONTENTS (arg); | |
3049 | ||
3050 | if (fp_register_arg_p (typecode, arg_type) | |
3051 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3052 | { | |
3053 | /* This is a floating point value that fits entirely | |
3054 | in a single register. */ | |
3055 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3056 | above to ensure that it is even register aligned. */ | |
3057 | LONGEST regval = extract_unsigned_integer (val, len); | |
3058 | if (mips_debug) | |
3059 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3060 | float_argreg, phex (regval, len)); | |
3061 | write_register (float_argreg++, regval); | |
3062 | ||
3063 | if (mips_debug) | |
3064 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3065 | argreg, phex (regval, len)); | |
3066 | write_register (argreg, regval); | |
3067 | argreg += 1; | |
3068 | } | |
3069 | else | |
3070 | { | |
3071 | /* Copy the argument to general registers or the stack in | |
3072 | register-sized pieces. Large arguments are split between | |
3073 | registers and stack. */ | |
4246e332 AC |
3074 | /* Note: structs whose size is not a multiple of |
3075 | mips_regsize() are treated specially: Irix cc passes them | |
3076 | in registers where gcc sometimes puts them on the stack. | |
3077 | For maximum compatibility, we will put them in both | |
3078 | places. */ | |
480d3dd2 AC |
3079 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
3080 | && (len % mips_saved_regsize (tdep) != 0)); | |
cb3d25d1 MS |
3081 | /* Note: Floating-point values that didn't fit into an FP |
3082 | register are only written to memory. */ | |
3083 | while (len > 0) | |
3084 | { | |
3085 | /* Rememer if the argument was written to the stack. */ | |
3086 | int stack_used_p = 0; | |
480d3dd2 AC |
3087 | int partial_len = (len < mips_saved_regsize (tdep) |
3088 | ? len : mips_saved_regsize (tdep)); | |
cb3d25d1 MS |
3089 | |
3090 | if (mips_debug) | |
3091 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3092 | partial_len); | |
3093 | ||
3094 | /* Write this portion of the argument to the stack. */ | |
3095 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3096 | || odd_sized_struct | |
3097 | || fp_register_arg_p (typecode, arg_type)) | |
3098 | { | |
3099 | /* Should shorter than int integer values be | |
3100 | promoted to int before being stored? */ | |
3101 | int longword_offset = 0; | |
3102 | CORE_ADDR addr; | |
3103 | stack_used_p = 1; | |
3104 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3105 | { | |
480d3dd2 AC |
3106 | if (mips_stack_argsize (tdep) == 8 |
3107 | && (typecode == TYPE_CODE_INT | |
3108 | || typecode == TYPE_CODE_PTR | |
3109 | || typecode == TYPE_CODE_FLT) | |
3110 | && len <= 4) | |
3111 | longword_offset = mips_stack_argsize (tdep) - len; | |
cb3d25d1 MS |
3112 | } |
3113 | ||
3114 | if (mips_debug) | |
3115 | { | |
3116 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3117 | paddr_nz (stack_offset)); | |
3118 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3119 | paddr_nz (longword_offset)); | |
3120 | } | |
3121 | ||
3122 | addr = sp + stack_offset + longword_offset; | |
3123 | ||
3124 | if (mips_debug) | |
3125 | { | |
3126 | int i; | |
3127 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3128 | paddr_nz (addr)); | |
3129 | for (i = 0; i < partial_len; i++) | |
3130 | { | |
3131 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3132 | val[i] & 0xff); | |
3133 | } | |
3134 | } | |
3135 | write_memory (addr, val, partial_len); | |
3136 | } | |
3137 | ||
3138 | /* Note!!! This is NOT an else clause. Odd sized | |
3139 | structs may go thru BOTH paths. Floating point | |
3140 | arguments will not. */ | |
3141 | /* Write this portion of the argument to a general | |
3142 | purpose register. */ | |
3143 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3144 | && !fp_register_arg_p (typecode, arg_type)) | |
3145 | { | |
3146 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
3147 | ||
3148 | /* A non-floating-point argument being passed in a | |
3149 | general register. If a struct or union, and if | |
3150 | the remaining length is smaller than the register | |
3151 | size, we have to adjust the register value on | |
3152 | big endian targets. | |
3153 | ||
3154 | It does not seem to be necessary to do the | |
3155 | same for integral types. | |
3156 | ||
3157 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3158 | outputting LE O32 with sizeof (struct) < | |
480d3dd2 | 3159 | mips_saved_regsize(), generates a left shift as |
cb3d25d1 MS |
3160 | part of storing the argument in a register a |
3161 | register (the left shift isn't generated when | |
480d3dd2 AC |
3162 | sizeof (struct) >= mips_saved_regsize()). Since |
3163 | it is quite possible that this is GCC | |
3164 | contradicting the LE/O32 ABI, GDB has not been | |
3165 | adjusted to accommodate this. Either someone | |
3166 | needs to demonstrate that the LE/O32 ABI | |
3167 | specifies such a left shift OR this new ABI gets | |
3168 | identified as such and GDB gets tweaked | |
3169 | accordingly. */ | |
cb3d25d1 MS |
3170 | |
3171 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
480d3dd2 | 3172 | && partial_len < mips_saved_regsize (tdep) |
cb3d25d1 MS |
3173 | && (typecode == TYPE_CODE_STRUCT || |
3174 | typecode == TYPE_CODE_UNION)) | |
480d3dd2 | 3175 | regval <<= ((mips_saved_regsize (tdep) - partial_len) * |
cb3d25d1 MS |
3176 | TARGET_CHAR_BIT); |
3177 | ||
3178 | if (mips_debug) | |
3179 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3180 | argreg, | |
480d3dd2 | 3181 | phex (regval, mips_saved_regsize (tdep))); |
cb3d25d1 MS |
3182 | write_register (argreg, regval); |
3183 | argreg++; | |
3184 | } | |
3185 | ||
3186 | len -= partial_len; | |
3187 | val += partial_len; | |
3188 | ||
3189 | /* Compute the the offset into the stack at which we | |
3190 | will copy the next parameter. | |
3191 | ||
3192 | In N32 (N64?), the stack_offset only needs to be | |
3193 | adjusted when it has been used. */ | |
3194 | ||
3195 | if (stack_used_p) | |
480d3dd2 AC |
3196 | stack_offset += align_up (partial_len, |
3197 | mips_stack_argsize (tdep)); | |
cb3d25d1 MS |
3198 | } |
3199 | } | |
3200 | if (mips_debug) | |
3201 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3202 | } | |
3203 | ||
310e9b6a AC |
3204 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3205 | ||
cb3d25d1 MS |
3206 | /* Return adjusted stack pointer. */ |
3207 | return sp; | |
3208 | } | |
3209 | ||
25ab4790 | 3210 | /* O32 version of push_dummy_call. */ |
ebafbe83 | 3211 | |
46cac009 | 3212 | static CORE_ADDR |
25ab4790 AC |
3213 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3214 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3215 | struct value **args, CORE_ADDR sp, int struct_return, | |
3216 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3217 | { |
3218 | int argreg; | |
3219 | int float_argreg; | |
3220 | int argnum; | |
3221 | int len = 0; | |
3222 | int stack_offset = 0; | |
480d3dd2 | 3223 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ebafbe83 | 3224 | |
25ab4790 AC |
3225 | /* For shared libraries, "t9" needs to point at the function |
3226 | address. */ | |
3227 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3228 | ||
3229 | /* Set the return address register to point to the entry point of | |
3230 | the program, where a breakpoint lies in wait. */ | |
3231 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3232 | ||
ebafbe83 MS |
3233 | /* First ensure that the stack and structure return address (if any) |
3234 | are properly aligned. The stack has to be at least 64-bit | |
3235 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3236 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3237 | aligned, so we round to this widest known alignment. */ | |
3238 | ||
5b03f266 AC |
3239 | sp = align_down (sp, 16); |
3240 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3241 | |
3242 | /* Now make space on the stack for the args. */ | |
3243 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3244 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 3245 | mips_stack_argsize (tdep)); |
5b03f266 | 3246 | sp -= align_up (len, 16); |
ebafbe83 MS |
3247 | |
3248 | if (mips_debug) | |
3249 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3250 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3251 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3252 | |
3253 | /* Initialize the integer and float register pointers. */ | |
3254 | argreg = A0_REGNUM; | |
56cea623 | 3255 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3256 | |
bcb0cc15 | 3257 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3258 | if (struct_return) |
3259 | { | |
3260 | if (mips_debug) | |
3261 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3262 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3263 | argreg, paddr_nz (struct_addr)); |
3264 | write_register (argreg++, struct_addr); | |
480d3dd2 | 3265 | stack_offset += mips_stack_argsize (tdep); |
ebafbe83 MS |
3266 | } |
3267 | ||
3268 | /* Now load as many as possible of the first arguments into | |
3269 | registers, and push the rest onto the stack. Loop thru args | |
3270 | from first to last. */ | |
3271 | for (argnum = 0; argnum < nargs; argnum++) | |
3272 | { | |
3273 | char *val; | |
d9d9c31f | 3274 | char valbuf[MAX_REGISTER_SIZE]; |
ebafbe83 MS |
3275 | struct value *arg = args[argnum]; |
3276 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3277 | int len = TYPE_LENGTH (arg_type); | |
3278 | enum type_code typecode = TYPE_CODE (arg_type); | |
3279 | ||
3280 | if (mips_debug) | |
3281 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3282 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3283 | argnum + 1, len, (int) typecode); |
3284 | ||
3285 | val = (char *) VALUE_CONTENTS (arg); | |
3286 | ||
3287 | /* 32-bit ABIs always start floating point arguments in an | |
3288 | even-numbered floating point register. Round the FP register | |
3289 | up before the check to see if there are any FP registers | |
3290 | left. O32/O64 targets also pass the FP in the integer | |
3291 | registers so also round up normal registers. */ | |
3292 | if (!FP_REGISTER_DOUBLE | |
3293 | && fp_register_arg_p (typecode, arg_type)) | |
3294 | { | |
3295 | if ((float_argreg & 1)) | |
3296 | float_argreg++; | |
3297 | } | |
3298 | ||
3299 | /* Floating point arguments passed in registers have to be | |
3300 | treated specially. On 32-bit architectures, doubles | |
3301 | are passed in register pairs; the even register gets | |
3302 | the low word, and the odd register gets the high word. | |
3303 | On O32/O64, the first two floating point arguments are | |
3304 | also copied to general registers, because MIPS16 functions | |
3305 | don't use float registers for arguments. This duplication of | |
3306 | arguments in general registers can't hurt non-MIPS16 functions | |
3307 | because those registers are normally skipped. */ | |
3308 | ||
3309 | if (fp_register_arg_p (typecode, arg_type) | |
3310 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3311 | { | |
3312 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3313 | { | |
3314 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3315 | unsigned long regval; | |
3316 | ||
3317 | /* Write the low word of the double to the even register(s). */ | |
3318 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3319 | if (mips_debug) | |
3320 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3321 | float_argreg, phex (regval, 4)); | |
3322 | write_register (float_argreg++, regval); | |
3323 | if (mips_debug) | |
3324 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3325 | argreg, phex (regval, 4)); | |
3326 | write_register (argreg++, regval); | |
3327 | ||
3328 | /* Write the high word of the double to the odd register(s). */ | |
3329 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3330 | if (mips_debug) | |
3331 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3332 | float_argreg, phex (regval, 4)); | |
3333 | write_register (float_argreg++, regval); | |
3334 | ||
3335 | if (mips_debug) | |
3336 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3337 | argreg, phex (regval, 4)); | |
3338 | write_register (argreg++, regval); | |
3339 | } | |
3340 | else | |
3341 | { | |
3342 | /* This is a floating point value that fits entirely | |
3343 | in a single register. */ | |
3344 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3345 | above to ensure that it is even register aligned. */ | |
3346 | LONGEST regval = extract_unsigned_integer (val, len); | |
3347 | if (mips_debug) | |
3348 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3349 | float_argreg, phex (regval, len)); | |
3350 | write_register (float_argreg++, regval); | |
3351 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3352 | registers for each argument. The below is (my | |
3353 | guess) to ensure that the corresponding integer | |
3354 | register has reserved the same space. */ | |
3355 | if (mips_debug) | |
3356 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3357 | argreg, phex (regval, len)); | |
3358 | write_register (argreg, regval); | |
3359 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3360 | } | |
3361 | /* Reserve space for the FP register. */ | |
480d3dd2 | 3362 | stack_offset += align_up (len, mips_stack_argsize (tdep)); |
46cac009 AC |
3363 | } |
3364 | else | |
3365 | { | |
3366 | /* Copy the argument to general registers or the stack in | |
3367 | register-sized pieces. Large arguments are split between | |
3368 | registers and stack. */ | |
4246e332 AC |
3369 | /* Note: structs whose size is not a multiple of |
3370 | mips_regsize() are treated specially: Irix cc passes them | |
3371 | in registers where gcc sometimes puts them on the stack. | |
3372 | For maximum compatibility, we will put them in both | |
3373 | places. */ | |
480d3dd2 AC |
3374 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
3375 | && (len % mips_saved_regsize (tdep) != 0)); | |
46cac009 AC |
3376 | /* Structures should be aligned to eight bytes (even arg registers) |
3377 | on MIPS_ABI_O32, if their first member has double precision. */ | |
480d3dd2 | 3378 | if (mips_saved_regsize (tdep) < 8 |
46cac009 AC |
3379 | && mips_type_needs_double_align (arg_type)) |
3380 | { | |
3381 | if ((argreg & 1)) | |
3382 | argreg++; | |
3383 | } | |
3384 | /* Note: Floating-point values that didn't fit into an FP | |
3385 | register are only written to memory. */ | |
3386 | while (len > 0) | |
3387 | { | |
3388 | /* Remember if the argument was written to the stack. */ | |
3389 | int stack_used_p = 0; | |
480d3dd2 AC |
3390 | int partial_len = (len < mips_saved_regsize (tdep) |
3391 | ? len : mips_saved_regsize (tdep)); | |
46cac009 AC |
3392 | |
3393 | if (mips_debug) | |
3394 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3395 | partial_len); | |
3396 | ||
3397 | /* Write this portion of the argument to the stack. */ | |
3398 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3399 | || odd_sized_struct | |
3400 | || fp_register_arg_p (typecode, arg_type)) | |
3401 | { | |
3402 | /* Should shorter than int integer values be | |
3403 | promoted to int before being stored? */ | |
3404 | int longword_offset = 0; | |
3405 | CORE_ADDR addr; | |
3406 | stack_used_p = 1; | |
3407 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3408 | { | |
480d3dd2 AC |
3409 | if (mips_stack_argsize (tdep) == 8 |
3410 | && (typecode == TYPE_CODE_INT | |
3411 | || typecode == TYPE_CODE_PTR | |
3412 | || typecode == TYPE_CODE_FLT) | |
3413 | && len <= 4) | |
3414 | longword_offset = mips_stack_argsize (tdep) - len; | |
46cac009 AC |
3415 | } |
3416 | ||
3417 | if (mips_debug) | |
3418 | { | |
3419 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3420 | paddr_nz (stack_offset)); | |
3421 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3422 | paddr_nz (longword_offset)); | |
3423 | } | |
3424 | ||
3425 | addr = sp + stack_offset + longword_offset; | |
3426 | ||
3427 | if (mips_debug) | |
3428 | { | |
3429 | int i; | |
3430 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3431 | paddr_nz (addr)); | |
3432 | for (i = 0; i < partial_len; i++) | |
3433 | { | |
3434 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3435 | val[i] & 0xff); | |
3436 | } | |
3437 | } | |
3438 | write_memory (addr, val, partial_len); | |
3439 | } | |
3440 | ||
3441 | /* Note!!! This is NOT an else clause. Odd sized | |
3442 | structs may go thru BOTH paths. Floating point | |
3443 | arguments will not. */ | |
3444 | /* Write this portion of the argument to a general | |
3445 | purpose register. */ | |
3446 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3447 | && !fp_register_arg_p (typecode, arg_type)) | |
3448 | { | |
3449 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3450 | /* Value may need to be sign extended, because |
480d3dd2 | 3451 | mips_regsize() != mips_saved_regsize(). */ |
46cac009 AC |
3452 | |
3453 | /* A non-floating-point argument being passed in a | |
3454 | general register. If a struct or union, and if | |
3455 | the remaining length is smaller than the register | |
3456 | size, we have to adjust the register value on | |
3457 | big endian targets. | |
3458 | ||
3459 | It does not seem to be necessary to do the | |
3460 | same for integral types. | |
3461 | ||
3462 | Also don't do this adjustment on O64 binaries. | |
3463 | ||
3464 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3465 | outputting LE O32 with sizeof (struct) < | |
480d3dd2 | 3466 | mips_saved_regsize(), generates a left shift as |
46cac009 AC |
3467 | part of storing the argument in a register a |
3468 | register (the left shift isn't generated when | |
480d3dd2 AC |
3469 | sizeof (struct) >= mips_saved_regsize()). Since |
3470 | it is quite possible that this is GCC | |
3471 | contradicting the LE/O32 ABI, GDB has not been | |
3472 | adjusted to accommodate this. Either someone | |
3473 | needs to demonstrate that the LE/O32 ABI | |
3474 | specifies such a left shift OR this new ABI gets | |
3475 | identified as such and GDB gets tweaked | |
3476 | accordingly. */ | |
3477 | ||
3478 | if (mips_saved_regsize (tdep) < 8 | |
46cac009 | 3479 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
480d3dd2 | 3480 | && partial_len < mips_saved_regsize (tdep) |
46cac009 AC |
3481 | && (typecode == TYPE_CODE_STRUCT || |
3482 | typecode == TYPE_CODE_UNION)) | |
480d3dd2 | 3483 | regval <<= ((mips_saved_regsize (tdep) - partial_len) * |
46cac009 AC |
3484 | TARGET_CHAR_BIT); |
3485 | ||
3486 | if (mips_debug) | |
3487 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3488 | argreg, | |
480d3dd2 | 3489 | phex (regval, mips_saved_regsize (tdep))); |
46cac009 AC |
3490 | write_register (argreg, regval); |
3491 | argreg++; | |
3492 | ||
3493 | /* Prevent subsequent floating point arguments from | |
3494 | being passed in floating point registers. */ | |
3495 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3496 | } | |
3497 | ||
3498 | len -= partial_len; | |
3499 | val += partial_len; | |
3500 | ||
3501 | /* Compute the the offset into the stack at which we | |
3502 | will copy the next parameter. | |
3503 | ||
3504 | In older ABIs, the caller reserved space for | |
3505 | registers that contained arguments. This was loosely | |
3506 | refered to as their "home". Consequently, space is | |
3507 | always allocated. */ | |
3508 | ||
480d3dd2 AC |
3509 | stack_offset += align_up (partial_len, |
3510 | mips_stack_argsize (tdep)); | |
46cac009 AC |
3511 | } |
3512 | } | |
3513 | if (mips_debug) | |
3514 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3515 | } | |
3516 | ||
310e9b6a AC |
3517 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3518 | ||
46cac009 AC |
3519 | /* Return adjusted stack pointer. */ |
3520 | return sp; | |
3521 | } | |
3522 | ||
25ab4790 | 3523 | /* O64 version of push_dummy_call. */ |
46cac009 AC |
3524 | |
3525 | static CORE_ADDR | |
25ab4790 AC |
3526 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3527 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3528 | struct value **args, CORE_ADDR sp, int struct_return, | |
3529 | CORE_ADDR struct_addr) | |
46cac009 AC |
3530 | { |
3531 | int argreg; | |
3532 | int float_argreg; | |
3533 | int argnum; | |
3534 | int len = 0; | |
3535 | int stack_offset = 0; | |
480d3dd2 | 3536 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
46cac009 | 3537 | |
25ab4790 AC |
3538 | /* For shared libraries, "t9" needs to point at the function |
3539 | address. */ | |
3540 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3541 | ||
3542 | /* Set the return address register to point to the entry point of | |
3543 | the program, where a breakpoint lies in wait. */ | |
3544 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3545 | ||
46cac009 AC |
3546 | /* First ensure that the stack and structure return address (if any) |
3547 | are properly aligned. The stack has to be at least 64-bit | |
3548 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3549 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3550 | aligned, so we round to this widest known alignment. */ | |
3551 | ||
5b03f266 AC |
3552 | sp = align_down (sp, 16); |
3553 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3554 | |
3555 | /* Now make space on the stack for the args. */ | |
3556 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3557 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 3558 | mips_stack_argsize (tdep)); |
5b03f266 | 3559 | sp -= align_up (len, 16); |
46cac009 AC |
3560 | |
3561 | if (mips_debug) | |
3562 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3563 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3564 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3565 | |
3566 | /* Initialize the integer and float register pointers. */ | |
3567 | argreg = A0_REGNUM; | |
56cea623 | 3568 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3569 | |
3570 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3571 | if (struct_return) | |
3572 | { | |
3573 | if (mips_debug) | |
3574 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3575 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3576 | argreg, paddr_nz (struct_addr)); |
3577 | write_register (argreg++, struct_addr); | |
480d3dd2 | 3578 | stack_offset += mips_stack_argsize (tdep); |
46cac009 AC |
3579 | } |
3580 | ||
3581 | /* Now load as many as possible of the first arguments into | |
3582 | registers, and push the rest onto the stack. Loop thru args | |
3583 | from first to last. */ | |
3584 | for (argnum = 0; argnum < nargs; argnum++) | |
3585 | { | |
3586 | char *val; | |
d9d9c31f | 3587 | char valbuf[MAX_REGISTER_SIZE]; |
46cac009 AC |
3588 | struct value *arg = args[argnum]; |
3589 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3590 | int len = TYPE_LENGTH (arg_type); | |
3591 | enum type_code typecode = TYPE_CODE (arg_type); | |
3592 | ||
3593 | if (mips_debug) | |
3594 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3595 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3596 | argnum + 1, len, (int) typecode); |
3597 | ||
3598 | val = (char *) VALUE_CONTENTS (arg); | |
3599 | ||
3600 | /* 32-bit ABIs always start floating point arguments in an | |
3601 | even-numbered floating point register. Round the FP register | |
3602 | up before the check to see if there are any FP registers | |
3603 | left. O32/O64 targets also pass the FP in the integer | |
3604 | registers so also round up normal registers. */ | |
3605 | if (!FP_REGISTER_DOUBLE | |
3606 | && fp_register_arg_p (typecode, arg_type)) | |
3607 | { | |
3608 | if ((float_argreg & 1)) | |
3609 | float_argreg++; | |
3610 | } | |
3611 | ||
3612 | /* Floating point arguments passed in registers have to be | |
3613 | treated specially. On 32-bit architectures, doubles | |
3614 | are passed in register pairs; the even register gets | |
3615 | the low word, and the odd register gets the high word. | |
3616 | On O32/O64, the first two floating point arguments are | |
3617 | also copied to general registers, because MIPS16 functions | |
3618 | don't use float registers for arguments. This duplication of | |
3619 | arguments in general registers can't hurt non-MIPS16 functions | |
3620 | because those registers are normally skipped. */ | |
3621 | ||
3622 | if (fp_register_arg_p (typecode, arg_type) | |
3623 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3624 | { | |
3625 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3626 | { | |
3627 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3628 | unsigned long regval; | |
3629 | ||
3630 | /* Write the low word of the double to the even register(s). */ | |
3631 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3632 | if (mips_debug) | |
3633 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3634 | float_argreg, phex (regval, 4)); | |
3635 | write_register (float_argreg++, regval); | |
3636 | if (mips_debug) | |
3637 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3638 | argreg, phex (regval, 4)); | |
3639 | write_register (argreg++, regval); | |
3640 | ||
3641 | /* Write the high word of the double to the odd register(s). */ | |
3642 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3643 | if (mips_debug) | |
3644 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3645 | float_argreg, phex (regval, 4)); | |
3646 | write_register (float_argreg++, regval); | |
3647 | ||
3648 | if (mips_debug) | |
3649 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3650 | argreg, phex (regval, 4)); | |
3651 | write_register (argreg++, regval); | |
3652 | } | |
3653 | else | |
3654 | { | |
3655 | /* This is a floating point value that fits entirely | |
3656 | in a single register. */ | |
3657 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3658 | above to ensure that it is even register aligned. */ | |
3659 | LONGEST regval = extract_unsigned_integer (val, len); | |
3660 | if (mips_debug) | |
3661 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3662 | float_argreg, phex (regval, len)); | |
3663 | write_register (float_argreg++, regval); | |
3664 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3665 | registers for each argument. The below is (my | |
3666 | guess) to ensure that the corresponding integer | |
3667 | register has reserved the same space. */ | |
3668 | if (mips_debug) | |
3669 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3670 | argreg, phex (regval, len)); | |
3671 | write_register (argreg, regval); | |
3672 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3673 | } | |
3674 | /* Reserve space for the FP register. */ | |
480d3dd2 | 3675 | stack_offset += align_up (len, mips_stack_argsize (tdep)); |
ebafbe83 MS |
3676 | } |
3677 | else | |
3678 | { | |
3679 | /* Copy the argument to general registers or the stack in | |
3680 | register-sized pieces. Large arguments are split between | |
3681 | registers and stack. */ | |
4246e332 AC |
3682 | /* Note: structs whose size is not a multiple of |
3683 | mips_regsize() are treated specially: Irix cc passes them | |
3684 | in registers where gcc sometimes puts them on the stack. | |
3685 | For maximum compatibility, we will put them in both | |
3686 | places. */ | |
480d3dd2 AC |
3687 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
3688 | && (len % mips_saved_regsize (tdep) != 0)); | |
ebafbe83 MS |
3689 | /* Structures should be aligned to eight bytes (even arg registers) |
3690 | on MIPS_ABI_O32, if their first member has double precision. */ | |
480d3dd2 | 3691 | if (mips_saved_regsize (tdep) < 8 |
ebafbe83 MS |
3692 | && mips_type_needs_double_align (arg_type)) |
3693 | { | |
3694 | if ((argreg & 1)) | |
3695 | argreg++; | |
3696 | } | |
3697 | /* Note: Floating-point values that didn't fit into an FP | |
3698 | register are only written to memory. */ | |
3699 | while (len > 0) | |
3700 | { | |
3701 | /* Remember if the argument was written to the stack. */ | |
3702 | int stack_used_p = 0; | |
480d3dd2 AC |
3703 | int partial_len = (len < mips_saved_regsize (tdep) |
3704 | ? len : mips_saved_regsize (tdep)); | |
ebafbe83 MS |
3705 | |
3706 | if (mips_debug) | |
3707 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3708 | partial_len); | |
3709 | ||
3710 | /* Write this portion of the argument to the stack. */ | |
3711 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3712 | || odd_sized_struct | |
3713 | || fp_register_arg_p (typecode, arg_type)) | |
3714 | { | |
3715 | /* Should shorter than int integer values be | |
3716 | promoted to int before being stored? */ | |
3717 | int longword_offset = 0; | |
3718 | CORE_ADDR addr; | |
3719 | stack_used_p = 1; | |
3720 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3721 | { | |
480d3dd2 AC |
3722 | if (mips_stack_argsize (tdep) == 8 |
3723 | && (typecode == TYPE_CODE_INT | |
3724 | || typecode == TYPE_CODE_PTR | |
3725 | || typecode == TYPE_CODE_FLT) | |
3726 | && len <= 4) | |
3727 | longword_offset = mips_stack_argsize (tdep) - len; | |
ebafbe83 MS |
3728 | } |
3729 | ||
3730 | if (mips_debug) | |
3731 | { | |
3732 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3733 | paddr_nz (stack_offset)); | |
3734 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3735 | paddr_nz (longword_offset)); | |
3736 | } | |
3737 | ||
3738 | addr = sp + stack_offset + longword_offset; | |
3739 | ||
3740 | if (mips_debug) | |
3741 | { | |
3742 | int i; | |
3743 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3744 | paddr_nz (addr)); | |
3745 | for (i = 0; i < partial_len; i++) | |
3746 | { | |
3747 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3748 | val[i] & 0xff); | |
3749 | } | |
3750 | } | |
3751 | write_memory (addr, val, partial_len); | |
3752 | } | |
3753 | ||
3754 | /* Note!!! This is NOT an else clause. Odd sized | |
3755 | structs may go thru BOTH paths. Floating point | |
3756 | arguments will not. */ | |
3757 | /* Write this portion of the argument to a general | |
3758 | purpose register. */ | |
3759 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3760 | && !fp_register_arg_p (typecode, arg_type)) | |
3761 | { | |
3762 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3763 | /* Value may need to be sign extended, because |
480d3dd2 | 3764 | mips_regsize() != mips_saved_regsize(). */ |
ebafbe83 MS |
3765 | |
3766 | /* A non-floating-point argument being passed in a | |
3767 | general register. If a struct or union, and if | |
3768 | the remaining length is smaller than the register | |
3769 | size, we have to adjust the register value on | |
3770 | big endian targets. | |
3771 | ||
3772 | It does not seem to be necessary to do the | |
3773 | same for integral types. | |
3774 | ||
3775 | Also don't do this adjustment on O64 binaries. | |
3776 | ||
3777 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3778 | outputting LE O32 with sizeof (struct) < | |
480d3dd2 | 3779 | mips_saved_regsize(), generates a left shift as |
ebafbe83 MS |
3780 | part of storing the argument in a register a |
3781 | register (the left shift isn't generated when | |
480d3dd2 AC |
3782 | sizeof (struct) >= mips_saved_regsize()). Since |
3783 | it is quite possible that this is GCC | |
3784 | contradicting the LE/O32 ABI, GDB has not been | |
3785 | adjusted to accommodate this. Either someone | |
3786 | needs to demonstrate that the LE/O32 ABI | |
3787 | specifies such a left shift OR this new ABI gets | |
3788 | identified as such and GDB gets tweaked | |
3789 | accordingly. */ | |
3790 | ||
3791 | if (mips_saved_regsize (tdep) < 8 | |
ebafbe83 | 3792 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
480d3dd2 | 3793 | && partial_len < mips_saved_regsize (tdep) |
ebafbe83 MS |
3794 | && (typecode == TYPE_CODE_STRUCT || |
3795 | typecode == TYPE_CODE_UNION)) | |
480d3dd2 | 3796 | regval <<= ((mips_saved_regsize (tdep) - partial_len) * |
ebafbe83 MS |
3797 | TARGET_CHAR_BIT); |
3798 | ||
3799 | if (mips_debug) | |
3800 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3801 | argreg, | |
480d3dd2 | 3802 | phex (regval, mips_saved_regsize (tdep))); |
ebafbe83 MS |
3803 | write_register (argreg, regval); |
3804 | argreg++; | |
3805 | ||
3806 | /* Prevent subsequent floating point arguments from | |
3807 | being passed in floating point registers. */ | |
3808 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3809 | } | |
3810 | ||
3811 | len -= partial_len; | |
3812 | val += partial_len; | |
3813 | ||
3814 | /* Compute the the offset into the stack at which we | |
3815 | will copy the next parameter. | |
3816 | ||
3817 | In older ABIs, the caller reserved space for | |
3818 | registers that contained arguments. This was loosely | |
3819 | refered to as their "home". Consequently, space is | |
3820 | always allocated. */ | |
3821 | ||
480d3dd2 AC |
3822 | stack_offset += align_up (partial_len, |
3823 | mips_stack_argsize (tdep)); | |
ebafbe83 MS |
3824 | } |
3825 | } | |
3826 | if (mips_debug) | |
3827 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3828 | } | |
3829 | ||
310e9b6a AC |
3830 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3831 | ||
ebafbe83 MS |
3832 | /* Return adjusted stack pointer. */ |
3833 | return sp; | |
3834 | } | |
3835 | ||
f7ab6ec6 | 3836 | static void |
acdb74a0 | 3837 | mips_pop_frame (void) |
c906108c | 3838 | { |
52f0bd74 | 3839 | int regnum; |
c906108c | 3840 | struct frame_info *frame = get_current_frame (); |
c193f6ac | 3841 | CORE_ADDR new_sp = get_frame_base (frame); |
e227b13c | 3842 | mips_extra_func_info_t proc_desc; |
480d3dd2 | 3843 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 3844 | |
50abf9e5 | 3845 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
3846 | { |
3847 | generic_pop_dummy_frame (); | |
3848 | flush_cached_frames (); | |
3849 | return; | |
3850 | } | |
3851 | ||
e227b13c | 3852 | proc_desc = get_frame_extra_info (frame)->proc_desc; |
8bedc050 | 3853 | write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
e0f7ec59 | 3854 | mips_find_saved_regs (frame); |
c906108c | 3855 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
21f87145 | 3856 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1b1d3794 | 3857 | && deprecated_get_frame_saved_regs (frame)[regnum]) |
21f87145 | 3858 | { |
480d3dd2 AC |
3859 | /* Floating point registers must not be sign extended, in case |
3860 | mips_saved_regsize() = 4 but sizeof (FP0_REGNUM) == 8. */ | |
21f87145 | 3861 | |
56cea623 | 3862 | if (mips_regnum (current_gdbarch)->fp0 <= regnum && regnum < mips_regnum (current_gdbarch)->fp0 + 32) |
21f87145 | 3863 | write_register (regnum, |
1b1d3794 | 3864 | read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
480d3dd2 | 3865 | mips_saved_regsize (tdep))); |
21f87145 MS |
3866 | else |
3867 | write_register (regnum, | |
1b1d3794 | 3868 | read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
480d3dd2 | 3869 | mips_saved_regsize (tdep))); |
21f87145 | 3870 | } |
757a7cc6 | 3871 | |
c906108c SS |
3872 | write_register (SP_REGNUM, new_sp); |
3873 | flush_cached_frames (); | |
3874 | ||
c5aa993b | 3875 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3876 | { |
3877 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3878 | ||
3879 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3880 | pi_ptr != NULL; | |
3881 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3882 | { | |
3883 | if (&pi_ptr->info == proc_desc) | |
3884 | break; | |
3885 | } | |
3886 | ||
3887 | if (pi_ptr == NULL) | |
3888 | error ("Can't locate dummy extra frame info\n"); | |
3889 | ||
3890 | if (prev_ptr != NULL) | |
3891 | prev_ptr->next = pi_ptr->next; | |
3892 | else | |
3893 | linked_proc_desc_table = pi_ptr->next; | |
3894 | ||
b8c9b27d | 3895 | xfree (pi_ptr); |
c906108c | 3896 | |
56cea623 | 3897 | write_register (mips_regnum (current_gdbarch)->hi, |
480d3dd2 AC |
3898 | read_memory_integer ((new_sp |
3899 | - 2 * mips_saved_regsize (tdep)), | |
3900 | mips_saved_regsize (tdep))); | |
56cea623 | 3901 | write_register (mips_regnum (current_gdbarch)->lo, |
480d3dd2 AC |
3902 | read_memory_integer ((new_sp |
3903 | - 3 * mips_saved_regsize (tdep)), | |
3904 | mips_saved_regsize (tdep))); | |
c906108c | 3905 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
56cea623 | 3906 | write_register (mips_regnum (current_gdbarch)->fp_control_status, |
480d3dd2 AC |
3907 | read_memory_integer ((new_sp |
3908 | - 4 * mips_saved_regsize (tdep)), | |
3909 | mips_saved_regsize (tdep))); | |
c906108c SS |
3910 | } |
3911 | } | |
3912 | ||
dd824b04 DJ |
3913 | /* Floating point register management. |
3914 | ||
3915 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3916 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3917 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3918 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3919 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3920 | double precision floats into two 32-bit chunks and store them in | |
3921 | consecutive fp regs. To display 64-bit floats stored in this | |
3922 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3923 | Throw in user-configurable endianness and you have a real mess. | |
3924 | ||
3925 | The way this works is: | |
3926 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3927 | double-precision value will be split across two logical registers. | |
3928 | The lower-numbered logical register will hold the low-order bits, | |
3929 | regardless of the processor's endianness. | |
3930 | - If we are on a 64-bit processor, and we are looking for a | |
3931 | single-precision value, it will be in the low ordered bits | |
3932 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3933 | save slot in memory. | |
3934 | - If we are in 64-bit mode, everything is straightforward. | |
3935 | ||
3936 | Note that this code only deals with "live" registers at the top of the | |
3937 | stack. We will attempt to deal with saved registers later, when | |
3938 | the raw/cooked register interface is in place. (We need a general | |
3939 | interface that can deal with dynamic saved register sizes -- fp | |
3940 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3941 | and below). */ | |
3942 | ||
67b2c998 DJ |
3943 | static struct type * |
3944 | mips_float_register_type (void) | |
3945 | { | |
361d1df0 | 3946 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3947 | return builtin_type_ieee_single_big; |
3948 | else | |
3949 | return builtin_type_ieee_single_little; | |
3950 | } | |
3951 | ||
3952 | static struct type * | |
3953 | mips_double_register_type (void) | |
3954 | { | |
361d1df0 | 3955 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3956 | return builtin_type_ieee_double_big; |
3957 | else | |
3958 | return builtin_type_ieee_double_little; | |
3959 | } | |
3960 | ||
dd824b04 DJ |
3961 | /* Copy a 32-bit single-precision value from the current frame |
3962 | into rare_buffer. */ | |
3963 | ||
3964 | static void | |
e11c53d2 AC |
3965 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
3966 | char *rare_buffer) | |
dd824b04 | 3967 | { |
719ec221 | 3968 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3969 | char *raw_buffer = alloca (raw_size); |
3970 | ||
e11c53d2 | 3971 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
3972 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3973 | if (raw_size == 8) | |
3974 | { | |
3975 | /* We have a 64-bit value for this register. Find the low-order | |
3976 | 32 bits. */ | |
3977 | int offset; | |
3978 | ||
3979 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3980 | offset = 4; | |
3981 | else | |
3982 | offset = 0; | |
3983 | ||
3984 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3985 | } | |
3986 | else | |
3987 | { | |
3988 | memcpy (rare_buffer, raw_buffer, 4); | |
3989 | } | |
3990 | } | |
3991 | ||
3992 | /* Copy a 64-bit double-precision value from the current frame into | |
3993 | rare_buffer. This may include getting half of it from the next | |
3994 | register. */ | |
3995 | ||
3996 | static void | |
e11c53d2 AC |
3997 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
3998 | char *rare_buffer) | |
dd824b04 | 3999 | { |
719ec221 | 4000 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4001 | |
4002 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4003 | { | |
4004 | /* We have a 64-bit value for this register, and we should use | |
4005 | all 64 bits. */ | |
e11c53d2 | 4006 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4007 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4008 | } | |
4009 | else | |
4010 | { | |
56cea623 | 4011 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4012 | internal_error (__FILE__, __LINE__, |
4013 | "mips_read_fp_register_double: bad access to " | |
4014 | "odd-numbered FP register"); | |
4015 | ||
4016 | /* mips_read_fp_register_single will find the correct 32 bits from | |
4017 | each register. */ | |
4018 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4019 | { | |
e11c53d2 AC |
4020 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4021 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4022 | } |
361d1df0 | 4023 | else |
dd824b04 | 4024 | { |
e11c53d2 AC |
4025 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4026 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4027 | } |
4028 | } | |
4029 | } | |
4030 | ||
c906108c | 4031 | static void |
e11c53d2 AC |
4032 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4033 | int regnum) | |
c5aa993b | 4034 | { /* do values for FP (float) regs */ |
dd824b04 | 4035 | char *raw_buffer; |
c906108c | 4036 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
f0ef6b29 | 4037 | int inv1, inv2, namelen; |
c5aa993b | 4038 | |
56cea623 | 4039 | raw_buffer = (char *) alloca (2 * register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0)); |
c906108c | 4040 | |
e11c53d2 AC |
4041 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4042 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4043 | ""); | |
f0ef6b29 | 4044 | |
719ec221 | 4045 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4046 | { |
f0ef6b29 KB |
4047 | /* 4-byte registers: Print hex and floating. Also print even |
4048 | numbered registers as doubles. */ | |
e11c53d2 | 4049 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4050 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4051 | |
e11c53d2 | 4052 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file); |
dd824b04 | 4053 | |
e11c53d2 | 4054 | fprintf_filtered (file, " flt: "); |
1adad886 | 4055 | if (inv1) |
e11c53d2 | 4056 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4057 | else |
e11c53d2 | 4058 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4059 | |
f0ef6b29 KB |
4060 | if (regnum % 2 == 0) |
4061 | { | |
e11c53d2 | 4062 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4063 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
4064 | &inv2); | |
1adad886 | 4065 | |
e11c53d2 | 4066 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4067 | if (inv2) |
e11c53d2 | 4068 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4069 | else |
e11c53d2 | 4070 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4071 | } |
c906108c SS |
4072 | } |
4073 | else | |
dd824b04 | 4074 | { |
f0ef6b29 | 4075 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4076 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4077 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4078 | |
e11c53d2 | 4079 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4080 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4081 | ||
361d1df0 | 4082 | |
e11c53d2 | 4083 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file); |
f0ef6b29 | 4084 | |
e11c53d2 | 4085 | fprintf_filtered (file, " flt: "); |
1adad886 | 4086 | if (inv1) |
e11c53d2 | 4087 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4088 | else |
e11c53d2 | 4089 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4090 | |
e11c53d2 | 4091 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4092 | if (inv2) |
e11c53d2 | 4093 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4094 | else |
e11c53d2 | 4095 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4096 | } |
4097 | } | |
4098 | ||
4099 | static void | |
e11c53d2 AC |
4100 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4101 | int regnum, int all) | |
f0ef6b29 | 4102 | { |
a4b8ebc8 | 4103 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4104 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4105 | int offset; |
1adad886 | 4106 | |
a4b8ebc8 | 4107 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4108 | { |
e11c53d2 | 4109 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4110 | return; |
4111 | } | |
4112 | ||
4113 | /* Get the data in raw format. */ | |
e11c53d2 | 4114 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4115 | { |
e11c53d2 | 4116 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4117 | return; |
c906108c | 4118 | } |
f0ef6b29 | 4119 | |
e11c53d2 | 4120 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4121 | |
4122 | /* The problem with printing numeric register names (r26, etc.) is that | |
4123 | the user can't use them on input. Probably the best solution is to | |
4124 | fix it so that either the numeric or the funky (a2, etc.) names | |
4125 | are accepted on input. */ | |
4126 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4127 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4128 | else |
e11c53d2 | 4129 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4130 | |
4131 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
719ec221 | 4132 | offset = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
f0ef6b29 KB |
4133 | else |
4134 | offset = 0; | |
4135 | ||
a4b8ebc8 | 4136 | print_scalar_formatted (raw_buffer + offset, gdbarch_register_type (gdbarch, regnum), |
e11c53d2 | 4137 | 'x', 0, file); |
c906108c SS |
4138 | } |
4139 | ||
f0ef6b29 KB |
4140 | /* Replacement for generic do_registers_info. |
4141 | Print regs in pretty columns. */ | |
4142 | ||
4143 | static int | |
e11c53d2 AC |
4144 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4145 | int regnum) | |
f0ef6b29 | 4146 | { |
e11c53d2 AC |
4147 | fprintf_filtered (file, " "); |
4148 | mips_print_fp_register (file, frame, regnum); | |
4149 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4150 | return regnum + 1; |
4151 | } | |
4152 | ||
4153 | ||
c906108c SS |
4154 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4155 | ||
4156 | static int | |
e11c53d2 | 4157 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4158 | int start_regnum) |
c906108c | 4159 | { |
a4b8ebc8 | 4160 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4161 | /* do values for GP (int) regs */ |
d9d9c31f | 4162 | char raw_buffer[MAX_REGISTER_SIZE]; |
4246e332 | 4163 | int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4164 | int col, byte; |
a4b8ebc8 | 4165 | int regnum; |
c906108c SS |
4166 | |
4167 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4168 | fprintf_filtered (file, " "); |
a4b8ebc8 AC |
4169 | for (col = 0, regnum = start_regnum; |
4170 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4171 | regnum++) | |
c906108c SS |
4172 | { |
4173 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4174 | continue; /* unused register */ |
a4b8ebc8 | 4175 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4176 | break; /* end the row: reached FP register */ |
4246e332 | 4177 | fprintf_filtered (file, mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4178 | REGISTER_NAME (regnum)); |
c906108c SS |
4179 | col++; |
4180 | } | |
a4b8ebc8 | 4181 | /* print the R0 to R31 names */ |
20e6603c AC |
4182 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4183 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4184 | else | |
4185 | fprintf_filtered (file, "\n "); | |
c906108c | 4186 | |
c906108c | 4187 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 AC |
4188 | for (col = 0, regnum = start_regnum; |
4189 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4190 | regnum++) | |
c906108c SS |
4191 | { |
4192 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4193 | continue; /* unused register */ |
a4b8ebc8 | 4194 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4195 | break; /* end row: reached FP register */ |
c906108c | 4196 | /* OK: get the data in raw format. */ |
e11c53d2 | 4197 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4198 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4199 | /* pad small registers */ | |
4246e332 AC |
4200 | for (byte = 0; |
4201 | byte < (mips_regsize (current_gdbarch) | |
c73e8f27 | 4202 | - register_size (current_gdbarch, regnum)); |
4246e332 | 4203 | byte++) |
c906108c SS |
4204 | printf_filtered (" "); |
4205 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4206 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
719ec221 AC |
4207 | for (byte = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
4208 | byte < register_size (current_gdbarch, regnum); | |
43e526b9 | 4209 | byte++) |
e11c53d2 | 4210 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4211 | else |
c73e8f27 | 4212 | for (byte = register_size (current_gdbarch, regnum) - 1; |
43e526b9 JM |
4213 | byte >= 0; |
4214 | byte--) | |
e11c53d2 AC |
4215 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4216 | fprintf_filtered (file, " "); | |
c906108c SS |
4217 | col++; |
4218 | } | |
c5aa993b | 4219 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4220 | fprintf_filtered (file, "\n"); |
c906108c SS |
4221 | |
4222 | return regnum; | |
4223 | } | |
4224 | ||
4225 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4226 | ||
bf1f5b4c | 4227 | static void |
e11c53d2 AC |
4228 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4229 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4230 | { |
c5aa993b | 4231 | if (regnum != -1) /* do one specified register */ |
c906108c | 4232 | { |
a4b8ebc8 | 4233 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4234 | if (*(REGISTER_NAME (regnum)) == '\0') |
4235 | error ("Not a valid register for the current processor type"); | |
4236 | ||
e11c53d2 AC |
4237 | mips_print_register (file, frame, regnum, 0); |
4238 | fprintf_filtered (file, "\n"); | |
c906108c | 4239 | } |
c5aa993b JM |
4240 | else |
4241 | /* do all (or most) registers */ | |
c906108c | 4242 | { |
a4b8ebc8 AC |
4243 | regnum = NUM_REGS; |
4244 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4245 | { |
a4b8ebc8 | 4246 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
e11c53d2 AC |
4247 | { |
4248 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4249 | regnum = print_fp_register_row (file, frame, regnum); | |
4250 | else | |
4251 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4252 | } | |
c906108c | 4253 | else |
e11c53d2 | 4254 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4255 | } |
4256 | } | |
4257 | } | |
4258 | ||
c906108c SS |
4259 | /* Is this a branch with a delay slot? */ |
4260 | ||
a14ed312 | 4261 | static int is_delayed (unsigned long); |
c906108c SS |
4262 | |
4263 | static int | |
acdb74a0 | 4264 | is_delayed (unsigned long insn) |
c906108c SS |
4265 | { |
4266 | int i; | |
4267 | for (i = 0; i < NUMOPCODES; ++i) | |
4268 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4269 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4270 | break; | |
4271 | return (i < NUMOPCODES | |
4272 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4273 | | INSN_COND_BRANCH_DELAY | |
4274 | | INSN_COND_BRANCH_LIKELY))); | |
4275 | } | |
4276 | ||
4277 | int | |
acdb74a0 | 4278 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4279 | { |
4280 | char buf[MIPS_INSTLEN]; | |
4281 | ||
4282 | /* There is no branch delay slot on MIPS16. */ | |
4283 | if (pc_is_mips16 (pc)) | |
4284 | return 0; | |
4285 | ||
4286 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4287 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4288 | return 0; | |
c5aa993b | 4289 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4290 | } |
4291 | ||
4292 | ||
74da7425 AC |
4293 | /* Given PC at the function's start address, attempt to find the |
4294 | prologue end using SAL information. Return zero if the skip fails. | |
4295 | ||
4296 | A non-optimized prologue traditionally has one SAL for the function | |
4297 | and a second for the function body. A single line function has | |
4298 | them both pointing at the same line. | |
4299 | ||
4300 | An optimized prologue is similar but the prologue may contain | |
4301 | instructions (SALs) from the instruction body. Need to skip those | |
4302 | while not getting into the function body. | |
4303 | ||
4304 | The functions end point and an increasing SAL line are used as | |
4305 | indicators of the prologue's endpoint. | |
4306 | ||
4307 | This code is based on the function refine_prologue_limit (versions | |
4308 | found in both ia64 and ppc). */ | |
4309 | ||
4310 | static CORE_ADDR | |
4311 | skip_prologue_using_sal (CORE_ADDR func_addr) | |
4312 | { | |
4313 | struct symtab_and_line prologue_sal; | |
4314 | CORE_ADDR start_pc; | |
4315 | CORE_ADDR end_pc; | |
4316 | ||
4317 | /* Get an initial range for the function. */ | |
4318 | find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc); | |
4319 | start_pc += FUNCTION_START_OFFSET; | |
4320 | ||
4321 | prologue_sal = find_pc_line (start_pc, 0); | |
4322 | if (prologue_sal.line != 0) | |
4323 | { | |
4324 | while (prologue_sal.end < end_pc) | |
4325 | { | |
4326 | struct symtab_and_line sal; | |
4327 | ||
4328 | sal = find_pc_line (prologue_sal.end, 0); | |
4329 | if (sal.line == 0) | |
4330 | break; | |
4331 | /* Assume that a consecutive SAL for the same (or larger) | |
4332 | line mark the prologue -> body transition. */ | |
4333 | if (sal.line >= prologue_sal.line) | |
4334 | break; | |
4335 | /* The case in which compiler's optimizer/scheduler has | |
4336 | moved instructions into the prologue. We look ahead in | |
4337 | the function looking for address ranges whose | |
4338 | corresponding line number is less the first one that we | |
4339 | found for the function. This is more conservative then | |
4340 | refine_prologue_limit which scans a large number of SALs | |
4341 | looking for any in the prologue */ | |
4342 | prologue_sal = sal; | |
4343 | } | |
4344 | } | |
4345 | return prologue_sal.end; | |
4346 | } | |
4347 | ||
c906108c SS |
4348 | /* Skip the PC past function prologue instructions (32-bit version). |
4349 | This is a helper function for mips_skip_prologue. */ | |
4350 | ||
4351 | static CORE_ADDR | |
f7b9e9fc | 4352 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4353 | { |
c5aa993b JM |
4354 | t_inst inst; |
4355 | CORE_ADDR end_pc; | |
4356 | int seen_sp_adjust = 0; | |
4357 | int load_immediate_bytes = 0; | |
4358 | ||
74da7425 AC |
4359 | /* Find an upper bound on the prologue. */ |
4360 | end_pc = skip_prologue_using_sal (pc); | |
4361 | if (end_pc == 0) | |
4362 | end_pc = pc + 100; /* Magic. */ | |
4363 | ||
c5aa993b JM |
4364 | /* Skip the typical prologue instructions. These are the stack adjustment |
4365 | instruction and the instructions that save registers on the stack | |
4366 | or in the gcc frame. */ | |
74da7425 | 4367 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
4368 | { |
4369 | unsigned long high_word; | |
c906108c | 4370 | |
c5aa993b JM |
4371 | inst = mips_fetch_instruction (pc); |
4372 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4373 | |
c5aa993b JM |
4374 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4375 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4376 | seen_sp_adjust = 1; | |
4377 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4378 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4379 | seen_sp_adjust = 1; | |
4380 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4381 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4382 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4383 | continue; | |
4384 | ||
4385 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4386 | continue; | |
4387 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4388 | /* sx reg,n($s8) */ | |
4389 | continue; /* reg != $zero */ | |
4390 | ||
4391 | /* move $s8,$sp. With different versions of gas this will be either | |
4392 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4393 | Accept any one of these. */ | |
4394 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4395 | continue; | |
4396 | ||
4397 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4398 | continue; | |
4399 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4400 | continue; | |
4401 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4402 | continue; | |
4403 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4404 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4405 | continue; | |
4406 | /* The following instructions load $at or $t0 with an immediate | |
4407 | value in preparation for a stack adjustment via | |
4408 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4409 | a local variable, so we accept them only before a stack adjustment | |
4410 | instruction was seen. */ | |
4411 | else if (!seen_sp_adjust) | |
4412 | { | |
4413 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4414 | high_word == 0x3c08) /* lui $t0,n */ | |
4415 | { | |
4416 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4417 | continue; | |
4418 | } | |
4419 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4420 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4421 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4422 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4423 | { | |
4424 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4425 | continue; | |
4426 | } | |
4427 | else | |
4428 | break; | |
4429 | } | |
4430 | else | |
4431 | break; | |
c906108c SS |
4432 | } |
4433 | ||
c5aa993b JM |
4434 | /* In a frameless function, we might have incorrectly |
4435 | skipped some load immediate instructions. Undo the skipping | |
4436 | if the load immediate was not followed by a stack adjustment. */ | |
4437 | if (load_immediate_bytes && !seen_sp_adjust) | |
4438 | pc -= load_immediate_bytes; | |
4439 | return pc; | |
c906108c SS |
4440 | } |
4441 | ||
4442 | /* Skip the PC past function prologue instructions (16-bit version). | |
4443 | This is a helper function for mips_skip_prologue. */ | |
4444 | ||
4445 | static CORE_ADDR | |
f7b9e9fc | 4446 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4447 | { |
c5aa993b JM |
4448 | CORE_ADDR end_pc; |
4449 | int extend_bytes = 0; | |
4450 | int prev_extend_bytes; | |
c906108c | 4451 | |
c5aa993b JM |
4452 | /* Table of instructions likely to be found in a function prologue. */ |
4453 | static struct | |
c906108c SS |
4454 | { |
4455 | unsigned short inst; | |
4456 | unsigned short mask; | |
c5aa993b JM |
4457 | } |
4458 | table[] = | |
4459 | { | |
c906108c | 4460 | { |
c5aa993b JM |
4461 | 0x6300, 0xff00 |
4462 | } | |
4463 | , /* addiu $sp,offset */ | |
4464 | { | |
4465 | 0xfb00, 0xff00 | |
4466 | } | |
4467 | , /* daddiu $sp,offset */ | |
4468 | { | |
4469 | 0xd000, 0xf800 | |
4470 | } | |
4471 | , /* sw reg,n($sp) */ | |
4472 | { | |
4473 | 0xf900, 0xff00 | |
4474 | } | |
4475 | , /* sd reg,n($sp) */ | |
4476 | { | |
4477 | 0x6200, 0xff00 | |
4478 | } | |
4479 | , /* sw $ra,n($sp) */ | |
4480 | { | |
4481 | 0xfa00, 0xff00 | |
4482 | } | |
4483 | , /* sd $ra,n($sp) */ | |
4484 | { | |
4485 | 0x673d, 0xffff | |
4486 | } | |
4487 | , /* move $s1,sp */ | |
4488 | { | |
4489 | 0xd980, 0xff80 | |
4490 | } | |
4491 | , /* sw $a0-$a3,n($s1) */ | |
4492 | { | |
4493 | 0x6704, 0xff1c | |
4494 | } | |
4495 | , /* move reg,$a0-$a3 */ | |
4496 | { | |
4497 | 0xe809, 0xf81f | |
4498 | } | |
4499 | , /* entry pseudo-op */ | |
4500 | { | |
4501 | 0x0100, 0xff00 | |
4502 | } | |
4503 | , /* addiu $s1,$sp,n */ | |
4504 | { | |
4505 | 0, 0 | |
4506 | } /* end of table marker */ | |
4507 | }; | |
4508 | ||
74da7425 AC |
4509 | /* Find an upper bound on the prologue. */ |
4510 | end_pc = skip_prologue_using_sal (pc); | |
4511 | if (end_pc == 0) | |
4512 | end_pc = pc + 100; /* Magic. */ | |
4513 | ||
c5aa993b JM |
4514 | /* Skip the typical prologue instructions. These are the stack adjustment |
4515 | instruction and the instructions that save registers on the stack | |
4516 | or in the gcc frame. */ | |
74da7425 | 4517 | for (; pc < end_pc; pc += MIPS16_INSTLEN) |
c5aa993b JM |
4518 | { |
4519 | unsigned short inst; | |
4520 | int i; | |
c906108c | 4521 | |
c5aa993b | 4522 | inst = mips_fetch_instruction (pc); |
c906108c | 4523 | |
c5aa993b JM |
4524 | /* Normally we ignore an extend instruction. However, if it is |
4525 | not followed by a valid prologue instruction, we must adjust | |
4526 | the pc back over the extend so that it won't be considered | |
4527 | part of the prologue. */ | |
4528 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4529 | { | |
4530 | extend_bytes = MIPS16_INSTLEN; | |
4531 | continue; | |
4532 | } | |
4533 | prev_extend_bytes = extend_bytes; | |
4534 | extend_bytes = 0; | |
c906108c | 4535 | |
c5aa993b JM |
4536 | /* Check for other valid prologue instructions besides extend. */ |
4537 | for (i = 0; table[i].mask != 0; i++) | |
4538 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4539 | break; | |
4540 | if (table[i].mask != 0) /* it was in table? */ | |
4541 | continue; /* ignore it */ | |
4542 | else | |
4543 | /* non-prologue */ | |
4544 | { | |
4545 | /* Return the current pc, adjusted backwards by 2 if | |
4546 | the previous instruction was an extend. */ | |
4547 | return pc - prev_extend_bytes; | |
4548 | } | |
c906108c SS |
4549 | } |
4550 | return pc; | |
4551 | } | |
4552 | ||
4553 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4554 | if the code at PC does not look like a function prologue; otherwise | |
4555 | returns an address that (if we're lucky) follows the prologue. If | |
4556 | LENIENT, then we must skip everything which is involved in setting | |
4557 | up the frame (it's OK to skip more, just so long as we don't skip | |
4558 | anything which might clobber the registers which are being saved. | |
4559 | We must skip more in the case where part of the prologue is in the | |
4560 | delay slot of a non-prologue instruction). */ | |
4561 | ||
f7ab6ec6 | 4562 | static CORE_ADDR |
f7b9e9fc | 4563 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4564 | { |
4565 | /* See if we can determine the end of the prologue via the symbol table. | |
4566 | If so, then return either PC, or the PC after the prologue, whichever | |
4567 | is greater. */ | |
4568 | ||
4569 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4570 | ||
4571 | if (post_prologue_pc != 0) | |
4572 | return max (pc, post_prologue_pc); | |
4573 | ||
4574 | /* Can't determine prologue from the symbol table, need to examine | |
4575 | instructions. */ | |
4576 | ||
4577 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4578 | return mips16_skip_prologue (pc); |
c906108c | 4579 | else |
f7b9e9fc | 4580 | return mips32_skip_prologue (pc); |
c906108c | 4581 | } |
c906108c | 4582 | |
7a292a7a SS |
4583 | /* Determine how a return value is stored within the MIPS register |
4584 | file, given the return type `valtype'. */ | |
4585 | ||
4586 | struct return_value_word | |
4587 | { | |
4588 | int len; | |
4589 | int reg; | |
4590 | int reg_offset; | |
4591 | int buf_offset; | |
4592 | }; | |
4593 | ||
7a292a7a | 4594 | static void |
acdb74a0 AC |
4595 | return_value_location (struct type *valtype, |
4596 | struct return_value_word *hi, | |
4597 | struct return_value_word *lo) | |
7a292a7a SS |
4598 | { |
4599 | int len = TYPE_LENGTH (valtype); | |
480d3dd2 | 4600 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c5aa993b | 4601 | |
7a292a7a SS |
4602 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4603 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4604 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4605 | { | |
4606 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4607 | { | |
4608 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4609 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4610 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4611 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4612 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
56cea623 | 4613 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8) |
7a292a7a SS |
4614 | ? 4 : 0); |
4615 | hi->reg_offset = lo->reg_offset; | |
56cea623 AC |
4616 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; |
4617 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
7a292a7a SS |
4618 | lo->len = 4; |
4619 | hi->len = 4; | |
4620 | } | |
4621 | else | |
4622 | { | |
4623 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4624 | register. */ |
d7449b42 | 4625 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
56cea623 | 4626 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8 |
7a292a7a SS |
4627 | && len == 4) |
4628 | ? 4 : 0); | |
56cea623 | 4629 | lo->reg = mips_regnum (current_gdbarch)->fp0; |
7a292a7a SS |
4630 | lo->len = len; |
4631 | lo->buf_offset = 0; | |
4632 | hi->len = 0; | |
4633 | hi->reg_offset = 0; | |
4634 | hi->buf_offset = 0; | |
4635 | hi->reg = 0; | |
4636 | } | |
4637 | } | |
4638 | else | |
4639 | { | |
4640 | /* Locate a result possibly spread across two registers. */ | |
4641 | int regnum = 2; | |
4642 | lo->reg = regnum + 0; | |
4643 | hi->reg = regnum + 1; | |
d7449b42 | 4644 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
480d3dd2 | 4645 | && len < mips_saved_regsize (tdep)) |
7a292a7a | 4646 | { |
bf1f5b4c | 4647 | /* "un-left-justify" the value in the low register */ |
480d3dd2 | 4648 | lo->reg_offset = mips_saved_regsize (tdep) - len; |
bcb0cc15 | 4649 | lo->len = len; |
bf1f5b4c | 4650 | hi->reg_offset = 0; |
7a292a7a SS |
4651 | hi->len = 0; |
4652 | } | |
d7449b42 | 4653 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
480d3dd2 AC |
4654 | && len > mips_saved_regsize (tdep) /* odd-size structs */ |
4655 | && len < mips_saved_regsize (tdep) * 2 | |
7a292a7a SS |
4656 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || |
4657 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4658 | { | |
4659 | /* "un-left-justify" the value spread across two registers. */ | |
480d3dd2 AC |
4660 | lo->reg_offset = 2 * mips_saved_regsize (tdep) - len; |
4661 | lo->len = mips_saved_regsize (tdep) - lo->reg_offset; | |
7a292a7a SS |
4662 | hi->reg_offset = 0; |
4663 | hi->len = len - lo->len; | |
4664 | } | |
4665 | else | |
4666 | { | |
4667 | /* Only perform a partial copy of the second register. */ | |
4668 | lo->reg_offset = 0; | |
4669 | hi->reg_offset = 0; | |
480d3dd2 | 4670 | if (len > mips_saved_regsize (tdep)) |
7a292a7a | 4671 | { |
480d3dd2 AC |
4672 | lo->len = mips_saved_regsize (tdep); |
4673 | hi->len = len - mips_saved_regsize (tdep); | |
7a292a7a SS |
4674 | } |
4675 | else | |
4676 | { | |
4677 | lo->len = len; | |
4678 | hi->len = 0; | |
4679 | } | |
4680 | } | |
d7449b42 | 4681 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
719ec221 | 4682 | && register_size (current_gdbarch, regnum) == 8 |
480d3dd2 | 4683 | && mips_saved_regsize (tdep) == 4) |
7a292a7a SS |
4684 | { |
4685 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4686 | of the register is being used */ |
7a292a7a SS |
4687 | lo->reg_offset += 4; |
4688 | hi->reg_offset += 4; | |
4689 | } | |
4690 | lo->buf_offset = 0; | |
4691 | hi->buf_offset = lo->len; | |
4692 | } | |
4693 | } | |
4694 | ||
4695 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4696 | copy its value into `valbuf'. */ | |
4697 | ||
46cac009 AC |
4698 | static void |
4699 | mips_eabi_extract_return_value (struct type *valtype, | |
b8b527c5 | 4700 | char regbuf[], |
46cac009 AC |
4701 | char *valbuf) |
4702 | { | |
4703 | struct return_value_word lo; | |
4704 | struct return_value_word hi; | |
4705 | return_value_location (valtype, &hi, &lo); | |
4706 | ||
4707 | memcpy (valbuf + lo.buf_offset, | |
78c63a3b | 4708 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + lo.reg_offset, |
46cac009 AC |
4709 | lo.len); |
4710 | ||
4711 | if (hi.len > 0) | |
4712 | memcpy (valbuf + hi.buf_offset, | |
78c63a3b | 4713 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + hi.reg_offset, |
46cac009 AC |
4714 | hi.len); |
4715 | } | |
4716 | ||
46cac009 AC |
4717 | static void |
4718 | mips_o64_extract_return_value (struct type *valtype, | |
b8b527c5 | 4719 | char regbuf[], |
46cac009 AC |
4720 | char *valbuf) |
4721 | { | |
4722 | struct return_value_word lo; | |
4723 | struct return_value_word hi; | |
4724 | return_value_location (valtype, &hi, &lo); | |
4725 | ||
4726 | memcpy (valbuf + lo.buf_offset, | |
78c63a3b | 4727 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + lo.reg_offset, |
46cac009 AC |
4728 | lo.len); |
4729 | ||
4730 | if (hi.len > 0) | |
4731 | memcpy (valbuf + hi.buf_offset, | |
78c63a3b | 4732 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + hi.reg_offset, |
46cac009 AC |
4733 | hi.len); |
4734 | } | |
4735 | ||
7a292a7a SS |
4736 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4737 | value into the appropriate register. */ | |
4738 | ||
46cac009 AC |
4739 | static void |
4740 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4741 | { | |
d9d9c31f | 4742 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4743 | struct return_value_word lo; |
4744 | struct return_value_word hi; | |
4745 | return_value_location (valtype, &hi, &lo); | |
4746 | ||
4747 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4748 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4749 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4750 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4751 | |
4752 | if (hi.len > 0) | |
4753 | { | |
4754 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4755 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4756 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4757 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4758 | } |
4759 | } | |
4760 | ||
4761 | static void | |
cb1d2653 | 4762 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 | 4763 | { |
d9d9c31f | 4764 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4765 | struct return_value_word lo; |
4766 | struct return_value_word hi; | |
4767 | return_value_location (valtype, &hi, &lo); | |
4768 | ||
4769 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4770 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4771 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4772 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4773 | |
4774 | if (hi.len > 0) | |
4775 | { | |
4776 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4777 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4778 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4779 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4780 | } |
4781 | } | |
4782 | ||
cb1d2653 AC |
4783 | /* O32 ABI stuff. */ |
4784 | ||
29dfb2ac AC |
4785 | static enum return_value_convention |
4786 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
4787 | struct regcache *regcache, | |
4788 | void *readbuf, const void *writebuf) | |
46cac009 | 4789 | { |
cb1d2653 | 4790 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
29dfb2ac AC |
4791 | |
4792 | if (TYPE_CODE (type)== TYPE_CODE_STRUCT | |
4793 | || TYPE_CODE (type)== TYPE_CODE_UNION | |
4794 | || TYPE_CODE (type)== TYPE_CODE_ARRAY) | |
4795 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4796 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4797 | && TYPE_LENGTH (type) == 4 | |
4798 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4799 | { |
cb1d2653 AC |
4800 | /* A single-precision floating-point value. It fits in the |
4801 | least significant part of FP0. */ | |
4802 | if (mips_debug) | |
4803 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
29dfb2ac AC |
4804 | mips_xfer_register (regcache, |
4805 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4806 | TYPE_LENGTH (type), | |
4807 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4808 | return RETURN_VALUE_REGISTER_CONVENTION; | |
cb1d2653 AC |
4809 | } |
4810 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4811 | && TYPE_LENGTH (type) == 8 | |
4812 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4813 | { | |
a4b8ebc8 AC |
4814 | /* A double-precision floating-point value. The most |
4815 | significant part goes in FP1, and the least significant in | |
4816 | FP0. */ | |
cb1d2653 | 4817 | if (mips_debug) |
a4b8ebc8 | 4818 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); |
cb1d2653 AC |
4819 | switch (TARGET_BYTE_ORDER) |
4820 | { | |
4821 | case BFD_ENDIAN_LITTLE: | |
29dfb2ac AC |
4822 | mips_xfer_register (regcache, |
4823 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, | |
4824 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4825 | mips_xfer_register (regcache, | |
4826 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, | |
4827 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
cb1d2653 AC |
4828 | break; |
4829 | case BFD_ENDIAN_BIG: | |
29dfb2ac AC |
4830 | mips_xfer_register (regcache, |
4831 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, | |
4832 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4833 | mips_xfer_register (regcache, | |
4834 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, | |
4835 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
cb1d2653 AC |
4836 | break; |
4837 | default: | |
4838 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4839 | } | |
29dfb2ac | 4840 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4841 | } |
4842 | #if 0 | |
4843 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4844 | && TYPE_NFIELDS (type) <= 2 | |
4845 | && TYPE_NFIELDS (type) >= 1 | |
4846 | && ((TYPE_NFIELDS (type) == 1 | |
4847 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4848 | == TYPE_CODE_FLT)) | |
4849 | || (TYPE_NFIELDS (type) == 2 | |
4850 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4851 | == TYPE_CODE_FLT) | |
4852 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4853 | == TYPE_CODE_FLT))) | |
4854 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4855 | { | |
4856 | /* A struct that contains one or two floats. Each value is part | |
4857 | in the least significant part of their floating point | |
4858 | register.. */ | |
d9d9c31f | 4859 | bfd_byte reg[MAX_REGISTER_SIZE]; |
cb1d2653 AC |
4860 | int regnum; |
4861 | int field; | |
56cea623 | 4862 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
cb1d2653 AC |
4863 | field < TYPE_NFIELDS (type); |
4864 | field++, regnum += 2) | |
4865 | { | |
4866 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4867 | / TARGET_CHAR_BIT); | |
4868 | if (mips_debug) | |
4869 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4870 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4871 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
29dfb2ac | 4872 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
cb1d2653 | 4873 | } |
29dfb2ac | 4874 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4875 | } |
4876 | #endif | |
4877 | #if 0 | |
4878 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4879 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4880 | { | |
4881 | /* A structure or union. Extract the left justified value, | |
4882 | regardless of the byte order. I.e. DO NOT USE | |
4883 | mips_xfer_lower. */ | |
4884 | int offset; | |
4885 | int regnum; | |
4886 | for (offset = 0, regnum = V0_REGNUM; | |
4887 | offset < TYPE_LENGTH (type); | |
719ec221 | 4888 | offset += register_size (current_gdbarch, regnum), regnum++) |
cb1d2653 | 4889 | { |
719ec221 | 4890 | int xfer = register_size (current_gdbarch, regnum); |
cb1d2653 AC |
4891 | if (offset + xfer > TYPE_LENGTH (type)) |
4892 | xfer = TYPE_LENGTH (type) - offset; | |
4893 | if (mips_debug) | |
4894 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4895 | offset, xfer, regnum); | |
a4b8ebc8 | 4896 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4897 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
cb1d2653 | 4898 | } |
29dfb2ac | 4899 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4900 | } |
4901 | #endif | |
4902 | else | |
4903 | { | |
4904 | /* A scalar extract each part but least-significant-byte | |
4905 | justified. o32 thinks registers are 4 byte, regardless of | |
4906 | the ISA. mips_stack_argsize controls this. */ | |
4907 | int offset; | |
4908 | int regnum; | |
4909 | for (offset = 0, regnum = V0_REGNUM; | |
4910 | offset < TYPE_LENGTH (type); | |
480d3dd2 | 4911 | offset += mips_stack_argsize (tdep), regnum++) |
cb1d2653 | 4912 | { |
480d3dd2 | 4913 | int xfer = mips_stack_argsize (tdep); |
cb1d2653 AC |
4914 | int pos = 0; |
4915 | if (offset + xfer > TYPE_LENGTH (type)) | |
4916 | xfer = TYPE_LENGTH (type) - offset; | |
4917 | if (mips_debug) | |
4918 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4919 | offset, xfer, regnum); | |
a4b8ebc8 | 4920 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4921 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
cb1d2653 | 4922 | } |
29dfb2ac | 4923 | return RETURN_VALUE_REGISTER_CONVENTION; |
46cac009 AC |
4924 | } |
4925 | } | |
4926 | ||
cb1d2653 AC |
4927 | /* N32/N44 ABI stuff. */ |
4928 | ||
29dfb2ac AC |
4929 | static enum return_value_convention |
4930 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
4931 | struct type *type, struct regcache *regcache, | |
4932 | void *readbuf, const void *writebuf) | |
c906108c | 4933 | { |
88658117 | 4934 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
29dfb2ac AC |
4935 | if (TYPE_CODE (type)== TYPE_CODE_STRUCT |
4936 | || TYPE_CODE (type)== TYPE_CODE_UNION | |
4937 | || TYPE_CODE (type)== TYPE_CODE_ARRAY | |
480d3dd2 | 4938 | || TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep)) |
29dfb2ac AC |
4939 | return RETURN_VALUE_STRUCT_CONVENTION; |
4940 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4941 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4942 | { |
88658117 AC |
4943 | /* A floating-point value belongs in the least significant part |
4944 | of FP0. */ | |
4945 | if (mips_debug) | |
4946 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
29dfb2ac AC |
4947 | mips_xfer_register (regcache, |
4948 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4949 | TYPE_LENGTH (type), | |
4950 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4951 | return RETURN_VALUE_REGISTER_CONVENTION; | |
88658117 AC |
4952 | } |
4953 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4954 | && TYPE_NFIELDS (type) <= 2 | |
4955 | && TYPE_NFIELDS (type) >= 1 | |
4956 | && ((TYPE_NFIELDS (type) == 1 | |
4957 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4958 | == TYPE_CODE_FLT)) | |
4959 | || (TYPE_NFIELDS (type) == 2 | |
4960 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4961 | == TYPE_CODE_FLT) | |
4962 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4963 | == TYPE_CODE_FLT))) | |
4964 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4965 | { | |
4966 | /* A struct that contains one or two floats. Each value is part | |
4967 | in the least significant part of their floating point | |
4968 | register.. */ | |
d9d9c31f | 4969 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 AC |
4970 | int regnum; |
4971 | int field; | |
56cea623 | 4972 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
88658117 AC |
4973 | field < TYPE_NFIELDS (type); |
4974 | field++, regnum += 2) | |
4975 | { | |
4976 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4977 | / TARGET_CHAR_BIT); | |
4978 | if (mips_debug) | |
4979 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4980 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4981 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
29dfb2ac | 4982 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
88658117 | 4983 | } |
29dfb2ac | 4984 | return RETURN_VALUE_REGISTER_CONVENTION; |
7a292a7a | 4985 | } |
88658117 AC |
4986 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4987 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4988 | { | |
4989 | /* A structure or union. Extract the left justified value, | |
4990 | regardless of the byte order. I.e. DO NOT USE | |
4991 | mips_xfer_lower. */ | |
4992 | int offset; | |
4993 | int regnum; | |
4994 | for (offset = 0, regnum = V0_REGNUM; | |
4995 | offset < TYPE_LENGTH (type); | |
719ec221 | 4996 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 4997 | { |
719ec221 | 4998 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
4999 | if (offset + xfer > TYPE_LENGTH (type)) |
5000 | xfer = TYPE_LENGTH (type) - offset; | |
5001 | if (mips_debug) | |
5002 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5003 | offset, xfer, regnum); | |
a4b8ebc8 | 5004 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 5005 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
88658117 | 5006 | } |
29dfb2ac | 5007 | return RETURN_VALUE_REGISTER_CONVENTION; |
88658117 AC |
5008 | } |
5009 | else | |
5010 | { | |
5011 | /* A scalar extract each part but least-significant-byte | |
5012 | justified. */ | |
5013 | int offset; | |
5014 | int regnum; | |
5015 | for (offset = 0, regnum = V0_REGNUM; | |
5016 | offset < TYPE_LENGTH (type); | |
719ec221 | 5017 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 5018 | { |
719ec221 | 5019 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
5020 | int pos = 0; |
5021 | if (offset + xfer > TYPE_LENGTH (type)) | |
5022 | xfer = TYPE_LENGTH (type) - offset; | |
5023 | if (mips_debug) | |
5024 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5025 | offset, xfer, regnum); | |
a4b8ebc8 | 5026 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 5027 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
88658117 | 5028 | } |
29dfb2ac | 5029 | return RETURN_VALUE_REGISTER_CONVENTION; |
88658117 AC |
5030 | } |
5031 | } | |
5032 | ||
c906108c SS |
5033 | /* Exported procedure: Is PC in the signal trampoline code */ |
5034 | ||
102182a9 MS |
5035 | static int |
5036 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
5037 | { |
5038 | if (sigtramp_address == 0) | |
5039 | fixup_sigtramp (); | |
5040 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
5041 | } | |
5042 | ||
a5ea2558 AC |
5043 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5044 | used for all MIPS-specific commands. */ | |
5045 | ||
a5ea2558 | 5046 | static void |
acdb74a0 | 5047 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5048 | { |
5049 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5050 | } | |
5051 | ||
a5ea2558 | 5052 | static void |
acdb74a0 | 5053 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5054 | { |
5055 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
5056 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
5057 | } | |
5058 | ||
c906108c SS |
5059 | /* Commands to show/set the MIPS FPU type. */ |
5060 | ||
c906108c | 5061 | static void |
acdb74a0 | 5062 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5063 | { |
c906108c SS |
5064 | char *fpu; |
5065 | switch (MIPS_FPU_TYPE) | |
5066 | { | |
5067 | case MIPS_FPU_SINGLE: | |
5068 | fpu = "single-precision"; | |
5069 | break; | |
5070 | case MIPS_FPU_DOUBLE: | |
5071 | fpu = "double-precision"; | |
5072 | break; | |
5073 | case MIPS_FPU_NONE: | |
5074 | fpu = "absent (none)"; | |
5075 | break; | |
93d56215 AC |
5076 | default: |
5077 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5078 | } |
5079 | if (mips_fpu_type_auto) | |
5080 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5081 | fpu); | |
5082 | else | |
5083 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
5084 | fpu); | |
5085 | } | |
5086 | ||
5087 | ||
c906108c | 5088 | static void |
acdb74a0 | 5089 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
5090 | { |
5091 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
5092 | show_mipsfpu_command (args, from_tty); | |
5093 | } | |
5094 | ||
c906108c | 5095 | static void |
acdb74a0 | 5096 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5097 | { |
8d5838b5 AC |
5098 | struct gdbarch_info info; |
5099 | gdbarch_info_init (&info); | |
c906108c SS |
5100 | mips_fpu_type = MIPS_FPU_SINGLE; |
5101 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5102 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5103 | instead of relying on globals. Doing that would let generic code | |
5104 | handle the search for this specific architecture. */ | |
5105 | if (!gdbarch_update_p (info)) | |
5106 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5107 | } |
5108 | ||
c906108c | 5109 | static void |
acdb74a0 | 5110 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5111 | { |
8d5838b5 AC |
5112 | struct gdbarch_info info; |
5113 | gdbarch_info_init (&info); | |
c906108c SS |
5114 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5115 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5116 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5117 | instead of relying on globals. Doing that would let generic code | |
5118 | handle the search for this specific architecture. */ | |
5119 | if (!gdbarch_update_p (info)) | |
5120 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5121 | } |
5122 | ||
c906108c | 5123 | static void |
acdb74a0 | 5124 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5125 | { |
8d5838b5 AC |
5126 | struct gdbarch_info info; |
5127 | gdbarch_info_init (&info); | |
c906108c SS |
5128 | mips_fpu_type = MIPS_FPU_NONE; |
5129 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5130 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5131 | instead of relying on globals. Doing that would let generic code | |
5132 | handle the search for this specific architecture. */ | |
5133 | if (!gdbarch_update_p (info)) | |
5134 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5135 | } |
5136 | ||
c906108c | 5137 | static void |
acdb74a0 | 5138 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5139 | { |
5140 | mips_fpu_type_auto = 1; | |
5141 | } | |
5142 | ||
c906108c | 5143 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5144 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5145 | the relevant processor still exists (it dates back to '94) and | |
5146 | secondly this is not the way to do this. The processor type should | |
5147 | be set by forcing an architecture change. */ | |
c906108c | 5148 | |
691c0433 AC |
5149 | void |
5150 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5151 | { |
691c0433 | 5152 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5153 | CORE_ADDR prid; |
5154 | ||
5155 | prid = read_register (PRID_REGNUM); | |
5156 | ||
5157 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 5158 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5159 | } |
5160 | ||
5161 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5162 | callable as an sfunc. */ | |
5163 | ||
5164 | static void | |
acdb74a0 AC |
5165 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5166 | struct cmd_list_element *c) | |
c906108c SS |
5167 | { |
5168 | reinit_frame_cache (); | |
5169 | } | |
5170 | ||
a89aa300 AC |
5171 | static int |
5172 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5173 | { |
e5ab0dce | 5174 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5175 | mips_extra_func_info_t proc_desc; |
5176 | ||
5177 | /* Search for the function containing this address. Set the low bit | |
5178 | of the address when searching, in case we were given an even address | |
5179 | that is the start of a 16-bit function. If we didn't do this, | |
5180 | the search would fail because the symbol table says the function | |
5181 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5182 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5183 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5184 | |
5185 | /* Make an attempt to determine if this is a 16-bit function. If | |
5186 | the procedure descriptor exists and the address therein is odd, | |
5187 | it's definitely a 16-bit function. Otherwise, we have to just | |
5188 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5189 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5190 | disassembler needs to be able to locally determine the ISA, and | |
5191 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5192 | work. */ | |
c906108c | 5193 | if (proc_desc) |
d31431ed AC |
5194 | { |
5195 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
5196 | info->mach = bfd_mach_mips16; | |
5197 | } | |
c906108c | 5198 | else |
d31431ed AC |
5199 | { |
5200 | if (pc_is_mips16 (memaddr)) | |
5201 | info->mach = bfd_mach_mips16; | |
5202 | } | |
c906108c SS |
5203 | |
5204 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5205 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5206 | |
e5ab0dce AC |
5207 | /* Set the disassembler options. */ |
5208 | if (tdep->mips_abi == MIPS_ABI_N32 | |
5209 | || tdep->mips_abi == MIPS_ABI_N64) | |
5210 | { | |
5211 | /* Set up the disassembler info, so that we get the right | |
5212 | register names from libopcodes. */ | |
5213 | if (tdep->mips_abi == MIPS_ABI_N32) | |
5214 | info->disassembler_options = "gpr-names=n32"; | |
5215 | else | |
5216 | info->disassembler_options = "gpr-names=64"; | |
5217 | info->flavour = bfd_target_elf_flavour; | |
5218 | } | |
5219 | else | |
5220 | /* This string is not recognized explicitly by the disassembler, | |
5221 | but it tells the disassembler to not try to guess the ABI from | |
5222 | the bfd elf headers, such that, if the user overrides the ABI | |
5223 | of a program linked as NewABI, the disassembly will follow the | |
5224 | register naming conventions specified by the user. */ | |
5225 | info->disassembler_options = "gpr-names=32"; | |
5226 | ||
c906108c | 5227 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5228 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5229 | return print_insn_big_mips (memaddr, info); |
5230 | else | |
5231 | return print_insn_little_mips (memaddr, info); | |
5232 | } | |
5233 | ||
c906108c SS |
5234 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5235 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5236 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5237 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5238 | (if necessary) to point to the actual memory location where the | |
5239 | breakpoint should be inserted. */ | |
5240 | ||
f7ab6ec6 | 5241 | static const unsigned char * |
acdb74a0 | 5242 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5243 | { |
d7449b42 | 5244 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5245 | { |
5246 | if (pc_is_mips16 (*pcptr)) | |
5247 | { | |
aaab4dba | 5248 | static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5}; |
95404a3e | 5249 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5250 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5251 | return mips16_big_breakpoint; |
5252 | } | |
5253 | else | |
5254 | { | |
aaab4dba AC |
5255 | /* The IDT board uses an unusual breakpoint value, and |
5256 | sometimes gets confused when it sees the usual MIPS | |
5257 | breakpoint instruction. */ | |
5258 | static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd}; | |
5259 | static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd}; | |
5260 | static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd}; | |
c906108c | 5261 | |
c5aa993b | 5262 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5263 | |
5264 | if (strcmp (target_shortname, "mips") == 0) | |
5265 | return idt_big_breakpoint; | |
5266 | else if (strcmp (target_shortname, "ddb") == 0 | |
5267 | || strcmp (target_shortname, "pmon") == 0 | |
5268 | || strcmp (target_shortname, "lsi") == 0) | |
5269 | return pmon_big_breakpoint; | |
5270 | else | |
5271 | return big_breakpoint; | |
5272 | } | |
5273 | } | |
5274 | else | |
5275 | { | |
5276 | if (pc_is_mips16 (*pcptr)) | |
5277 | { | |
aaab4dba | 5278 | static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8}; |
95404a3e | 5279 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5280 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5281 | return mips16_little_breakpoint; |
5282 | } | |
5283 | else | |
5284 | { | |
aaab4dba AC |
5285 | static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0}; |
5286 | static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0}; | |
5287 | static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0}; | |
c906108c | 5288 | |
c5aa993b | 5289 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5290 | |
5291 | if (strcmp (target_shortname, "mips") == 0) | |
5292 | return idt_little_breakpoint; | |
5293 | else if (strcmp (target_shortname, "ddb") == 0 | |
5294 | || strcmp (target_shortname, "pmon") == 0 | |
5295 | || strcmp (target_shortname, "lsi") == 0) | |
5296 | return pmon_little_breakpoint; | |
5297 | else | |
5298 | return little_breakpoint; | |
5299 | } | |
5300 | } | |
5301 | } | |
5302 | ||
5303 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5304 | PC, which is either the callee or the caller. There are several | |
5305 | cases which must be handled: | |
5306 | ||
5307 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5308 | target PC is in $31 ($ra). |
c906108c | 5309 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5310 | and the target PC is in $2. |
c906108c | 5311 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5312 | before the jal instruction, this is effectively a call stub |
5313 | and the the target PC is in $2. Otherwise this is effectively | |
5314 | a return stub and the target PC is in $18. | |
c906108c SS |
5315 | |
5316 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5317 | gory details. | |
5318 | ||
5319 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5320 | */ |
c906108c | 5321 | |
757a7cc6 | 5322 | static CORE_ADDR |
acdb74a0 | 5323 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5324 | { |
5325 | char *name; | |
5326 | CORE_ADDR start_addr; | |
5327 | ||
5328 | /* Find the starting address and name of the function containing the PC. */ | |
5329 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5330 | return 0; | |
5331 | ||
5332 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5333 | target PC is in $31 ($ra). */ | |
5334 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5335 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5336 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5337 | |
5338 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5339 | { | |
5340 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5341 | and the target PC is in $2. */ | |
5342 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5343 | return read_signed_register (2); |
c906108c SS |
5344 | |
5345 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5346 | before the jal instruction, this is effectively a call stub |
5347 | and the the target PC is in $2. Otherwise this is effectively | |
5348 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5349 | else if (name[19] == 's' || name[19] == 'd') |
5350 | { | |
5351 | if (pc == start_addr) | |
5352 | { | |
5353 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5354 | stub. Such a stub for a function bar might have a name |
5355 | like __fn_stub_bar, and might look like this: | |
5356 | mfc1 $4,$f13 | |
5357 | mfc1 $5,$f12 | |
5358 | mfc1 $6,$f15 | |
5359 | mfc1 $7,$f14 | |
5360 | la $1,bar (becomes a lui/addiu pair) | |
5361 | jr $1 | |
5362 | So scan down to the lui/addi and extract the target | |
5363 | address from those two instructions. */ | |
c906108c | 5364 | |
6c997a34 | 5365 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5366 | t_inst inst; |
5367 | int i; | |
5368 | ||
5369 | /* See if the name of the target function is __fn_stub_*. */ | |
5370 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5371 | return target_pc; | |
5372 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5373 | && strcmp (name, "etext") != 0 | |
5374 | && strcmp (name, "_etext") != 0) | |
5375 | return target_pc; | |
5376 | ||
5377 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5378 | The limit on the search is arbitrarily set to 20 |
5379 | instructions. FIXME. */ | |
c906108c SS |
5380 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5381 | { | |
c5aa993b JM |
5382 | inst = mips_fetch_instruction (target_pc); |
5383 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5384 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5385 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5386 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5387 | } |
5388 | ||
5389 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5390 | return target_pc; | |
5391 | } | |
5392 | else | |
5393 | /* This is the 'return' part of a call stub. The return | |
5394 | address is in $r18. */ | |
6c997a34 | 5395 | return read_signed_register (18); |
c906108c SS |
5396 | } |
5397 | } | |
c5aa993b | 5398 | return 0; /* not a stub */ |
c906108c SS |
5399 | } |
5400 | ||
5401 | ||
5402 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5403 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5404 | ||
757a7cc6 | 5405 | static int |
acdb74a0 | 5406 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5407 | { |
5408 | CORE_ADDR start_addr; | |
5409 | ||
5410 | /* Find the starting address of the function containing the PC. If the | |
5411 | caller didn't give us a name, look it up at the same time. */ | |
5412 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5413 | return 0; | |
5414 | ||
5415 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5416 | { | |
5417 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5418 | if (name[19] >= '0' && name[19] <= '9') | |
5419 | return 1; | |
5420 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5421 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5422 | else if (name[19] == 's' || name[19] == 'd') |
5423 | return pc == start_addr; | |
5424 | } | |
5425 | ||
c5aa993b | 5426 | return 0; /* not a stub */ |
c906108c SS |
5427 | } |
5428 | ||
5429 | ||
5430 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5431 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5432 | ||
e41b17f0 | 5433 | static int |
acdb74a0 | 5434 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5435 | { |
5436 | CORE_ADDR start_addr; | |
5437 | ||
5438 | /* Find the starting address of the function containing the PC. */ | |
5439 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5440 | return 0; | |
5441 | ||
5442 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5443 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5444 | || strcmp (name, "__mips16_ret_df") == 0) | |
5445 | return 1; | |
5446 | ||
5447 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5448 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5449 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5450 | && (name[19] == 's' || name[19] == 'd') | |
5451 | && pc != start_addr) | |
5452 | return 1; | |
5453 | ||
c5aa993b | 5454 | return 0; /* not a stub */ |
c906108c SS |
5455 | } |
5456 | ||
5457 | ||
5458 | /* Return non-zero if the PC is in a library helper function that should | |
5459 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5460 | ||
5461 | int | |
acdb74a0 | 5462 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5463 | { |
5464 | char *name; | |
5465 | ||
5466 | /* Find the starting address and name of the function containing the PC. */ | |
5467 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5468 | return 0; | |
5469 | ||
5470 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5471 | that we want to ignore. */ | |
5472 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5473 | || strcmp (name, "__mips16_ret_df") == 0); | |
5474 | } | |
5475 | ||
5476 | ||
47a8d4ba AC |
5477 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5478 | the register stored on the stack (32) is different to its real raw | |
5479 | size (64). The below ensures that registers are fetched from the | |
5480 | stack using their ABI size and then stored into the RAW_BUFFER | |
5481 | using their raw size. | |
5482 | ||
5483 | The alternative to adding this function would be to add an ABI | |
5484 | macro - REGISTER_STACK_SIZE(). */ | |
5485 | ||
5486 | static void | |
acdb74a0 | 5487 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5488 | int *optimizedp, |
acdb74a0 AC |
5489 | CORE_ADDR *addrp, |
5490 | struct frame_info *frame, | |
5491 | int regnum, | |
795e1e11 | 5492 | enum lval_type *lvalp) |
47a8d4ba | 5493 | { |
795e1e11 AC |
5494 | CORE_ADDR addrx; |
5495 | enum lval_type lvalx; | |
5496 | int optimizedx; | |
6e51443a | 5497 | int realnumx; |
47a8d4ba | 5498 | |
a4b8ebc8 AC |
5499 | /* Always a pseudo. */ |
5500 | gdb_assert (regnum >= NUM_REGS); | |
47a8d4ba | 5501 | |
795e1e11 AC |
5502 | /* Make certain that all needed parameters are present. */ |
5503 | if (addrp == NULL) | |
5504 | addrp = &addrx; | |
5505 | if (lvalp == NULL) | |
5506 | lvalp = &lvalx; | |
5507 | if (optimizedp == NULL) | |
5508 | optimizedp = &optimizedx; | |
a4b8ebc8 AC |
5509 | |
5510 | if ((regnum % NUM_REGS) == SP_REGNUM) | |
5511 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
5512 | In fact, it is so special that it can even only be fetched | |
5513 | using a raw register number! Once this code as been converted | |
5514 | to frame-unwind the problem goes away. */ | |
5515 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5516 | regnum % NUM_REGS, optimizedp, lvalp, addrp, | |
5517 | &realnumx, raw_buffer); | |
5518 | else | |
5519 | /* Get it from the next frame. */ | |
5520 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5521 | regnum, optimizedp, lvalp, addrp, | |
5522 | &realnumx, raw_buffer); | |
47a8d4ba | 5523 | } |
2acceee2 | 5524 | |
f7b9e9fc AC |
5525 | /* Immediately after a function call, return the saved pc. |
5526 | Can't always go through the frames for this because on some machines | |
5527 | the new frame is not set up until the new function executes | |
5528 | some instructions. */ | |
5529 | ||
5530 | static CORE_ADDR | |
5531 | mips_saved_pc_after_call (struct frame_info *frame) | |
5532 | { | |
6c997a34 | 5533 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5534 | } |
5535 | ||
5536 | ||
a4b8ebc8 AC |
5537 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5538 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5539 | |
5540 | static int | |
5541 | mips_stab_reg_to_regnum (int num) | |
5542 | { | |
a4b8ebc8 | 5543 | int regnum; |
2f38ef89 | 5544 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5545 | regnum = num; |
2f38ef89 | 5546 | else if (num >= 38 && num < 70) |
56cea623 | 5547 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5548 | else if (num == 70) |
56cea623 | 5549 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5550 | else if (num == 71) |
56cea623 | 5551 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5552 | else |
a4b8ebc8 AC |
5553 | /* This will hopefully (eventually) provoke a warning. Should |
5554 | we be calling complaint() here? */ | |
5555 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5556 | return NUM_REGS + regnum; | |
88c72b7d AC |
5557 | } |
5558 | ||
2f38ef89 | 5559 | |
a4b8ebc8 AC |
5560 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5561 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5562 | |
5563 | static int | |
2f38ef89 | 5564 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5565 | { |
a4b8ebc8 | 5566 | int regnum; |
2f38ef89 | 5567 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5568 | regnum = num; |
2f38ef89 | 5569 | else if (num >= 32 && num < 64) |
56cea623 | 5570 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5571 | else if (num == 64) |
56cea623 | 5572 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5573 | else if (num == 65) |
56cea623 | 5574 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5575 | else |
a4b8ebc8 AC |
5576 | /* This will hopefully (eventually) provoke a warning. Should we |
5577 | be calling complaint() here? */ | |
5578 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5579 | return NUM_REGS + regnum; | |
5580 | } | |
5581 | ||
5582 | static int | |
5583 | mips_register_sim_regno (int regnum) | |
5584 | { | |
5585 | /* Only makes sense to supply raw registers. */ | |
5586 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5587 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5588 | decide if it is valid. Should instead define a standard sim/gdb | |
5589 | register numbering scheme. */ | |
5590 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5591 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5592 | return regnum; | |
5593 | else | |
5594 | return LEGACY_SIM_REGNO_IGNORE; | |
88c72b7d AC |
5595 | } |
5596 | ||
2f38ef89 | 5597 | |
fc0c74b1 AC |
5598 | /* Convert an integer into an address. By first converting the value |
5599 | into a pointer and then extracting it signed, the address is | |
5600 | guarenteed to be correctly sign extended. */ | |
5601 | ||
5602 | static CORE_ADDR | |
5603 | mips_integer_to_address (struct type *type, void *buf) | |
5604 | { | |
5605 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5606 | LONGEST val = unpack_long (type, buf); | |
5607 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5608 | return extract_signed_integer (tmp, | |
5609 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5610 | } | |
5611 | ||
caaa3122 DJ |
5612 | static void |
5613 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5614 | { | |
5615 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5616 | const char *name = bfd_get_section_name (abfd, sect); | |
5617 | ||
5618 | if (*abip != MIPS_ABI_UNKNOWN) | |
5619 | return; | |
5620 | ||
5621 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5622 | return; | |
5623 | ||
5624 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5625 | *abip = MIPS_ABI_O32; | |
5626 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5627 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5628 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5629 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5630 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5631 | *abip = MIPS_ABI_O64; | |
5632 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5633 | *abip = MIPS_ABI_EABI32; | |
5634 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5635 | *abip = MIPS_ABI_EABI64; | |
5636 | else | |
5637 | warning ("unsupported ABI %s.", name + 8); | |
5638 | } | |
5639 | ||
2e4ebe70 DJ |
5640 | static enum mips_abi |
5641 | global_mips_abi (void) | |
5642 | { | |
5643 | int i; | |
5644 | ||
5645 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5646 | if (mips_abi_strings[i] == mips_abi_string) | |
5647 | return (enum mips_abi) i; | |
5648 | ||
5649 | internal_error (__FILE__, __LINE__, | |
5650 | "unknown ABI string"); | |
5651 | } | |
5652 | ||
c2d11a7d | 5653 | static struct gdbarch * |
acdb74a0 AC |
5654 | mips_gdbarch_init (struct gdbarch_info info, |
5655 | struct gdbarch_list *arches) | |
c2d11a7d | 5656 | { |
c2d11a7d JM |
5657 | struct gdbarch *gdbarch; |
5658 | struct gdbarch_tdep *tdep; | |
5659 | int elf_flags; | |
2e4ebe70 | 5660 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5661 | int num_regs; |
8d5838b5 | 5662 | enum mips_fpu_type fpu_type; |
c2d11a7d | 5663 | |
ec03c1ac AC |
5664 | /* First of all, extract the elf_flags, if available. */ |
5665 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5666 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5667 | else if (arches != NULL) |
5668 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5669 | else |
5670 | elf_flags = 0; | |
5671 | if (gdbarch_debug) | |
5672 | fprintf_unfiltered (gdb_stdlog, | |
5673 | "mips_gdbarch_init: elf_flags = 0x%08x\n", | |
5674 | elf_flags); | |
c2d11a7d | 5675 | |
102182a9 | 5676 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5677 | switch ((elf_flags & EF_MIPS_ABI)) |
5678 | { | |
5679 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5680 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5681 | break; |
5682 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5683 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5684 | break; |
5685 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5686 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5687 | break; |
5688 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5689 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5690 | break; |
5691 | default: | |
acdb74a0 | 5692 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5693 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5694 | else |
ec03c1ac | 5695 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5696 | break; |
5697 | } | |
acdb74a0 | 5698 | |
caaa3122 | 5699 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5700 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5701 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5702 | |
ec03c1ac AC |
5703 | /* If we have no usefu BFD information, use the ABI from the last |
5704 | MIPS architecture (if there is one). */ | |
5705 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5706 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5707 | |
32a6503c | 5708 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5709 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5710 | && info.bfd_arch_info != NULL |
5711 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5712 | { | |
5713 | switch (info.bfd_arch_info->mach) | |
5714 | { | |
5715 | case bfd_mach_mips3900: | |
ec03c1ac | 5716 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5717 | break; |
5718 | case bfd_mach_mips4100: | |
5719 | case bfd_mach_mips5000: | |
ec03c1ac | 5720 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5721 | break; |
1d06468c EZ |
5722 | case bfd_mach_mips8000: |
5723 | case bfd_mach_mips10000: | |
32a6503c KB |
5724 | /* On Irix, ELF64 executables use the N64 ABI. The |
5725 | pseudo-sections which describe the ABI aren't present | |
5726 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5727 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5728 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5729 | found_abi = MIPS_ABI_N64; |
28d169de | 5730 | else |
ec03c1ac | 5731 | found_abi = MIPS_ABI_N32; |
1d06468c | 5732 | break; |
bf64bfd6 AC |
5733 | } |
5734 | } | |
2e4ebe70 | 5735 | |
ec03c1ac AC |
5736 | if (gdbarch_debug) |
5737 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5738 | found_abi); | |
5739 | ||
5740 | /* What has the user specified from the command line? */ | |
5741 | wanted_abi = global_mips_abi (); | |
5742 | if (gdbarch_debug) | |
5743 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5744 | wanted_abi); | |
2e4ebe70 DJ |
5745 | |
5746 | /* Now that we have found what the ABI for this binary would be, | |
5747 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5748 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5749 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5750 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5751 | mips_abi = found_abi; | |
5752 | else | |
5753 | mips_abi = MIPS_ABI_O32; | |
5754 | if (gdbarch_debug) | |
5755 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5756 | mips_abi); | |
2e4ebe70 | 5757 | |
ec03c1ac | 5758 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5759 | if (gdbarch_debug) |
ec03c1ac AC |
5760 | fprintf_unfiltered (gdb_stdlog, |
5761 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5762 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5763 | |
8d5838b5 AC |
5764 | /* Determine the MIPS FPU type. */ |
5765 | if (!mips_fpu_type_auto) | |
5766 | fpu_type = mips_fpu_type; | |
5767 | else if (info.bfd_arch_info != NULL | |
5768 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5769 | switch (info.bfd_arch_info->mach) | |
5770 | { | |
5771 | case bfd_mach_mips3900: | |
5772 | case bfd_mach_mips4100: | |
5773 | case bfd_mach_mips4111: | |
5774 | fpu_type = MIPS_FPU_NONE; | |
5775 | break; | |
5776 | case bfd_mach_mips4650: | |
5777 | fpu_type = MIPS_FPU_SINGLE; | |
5778 | break; | |
5779 | default: | |
5780 | fpu_type = MIPS_FPU_DOUBLE; | |
5781 | break; | |
5782 | } | |
5783 | else if (arches != NULL) | |
5784 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5785 | else | |
5786 | fpu_type = MIPS_FPU_DOUBLE; | |
5787 | if (gdbarch_debug) | |
5788 | fprintf_unfiltered (gdb_stdlog, | |
5789 | "mips_gdbarch_init: fpu_type = %d\n", | |
5790 | fpu_type); | |
5791 | ||
c2d11a7d JM |
5792 | /* try to find a pre-existing architecture */ |
5793 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5794 | arches != NULL; | |
5795 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5796 | { | |
5797 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5798 | using. */ |
9103eae0 | 5799 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5800 | continue; |
9103eae0 | 5801 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5802 | continue; |
719ec221 AC |
5803 | /* Need to be pedantic about which register virtual size is |
5804 | used. */ | |
5805 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5806 | != mips64_transfers_32bit_regs_p) | |
5807 | continue; | |
8d5838b5 AC |
5808 | /* Be pedantic about which FPU is selected. */ |
5809 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5810 | continue; | |
4be87837 | 5811 | return arches->gdbarch; |
c2d11a7d JM |
5812 | } |
5813 | ||
102182a9 | 5814 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5815 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5816 | gdbarch = gdbarch_alloc (&info, tdep); | |
5817 | tdep->elf_flags = elf_flags; | |
719ec221 | 5818 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5819 | tdep->found_abi = found_abi; |
5820 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5821 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 5822 | |
102182a9 | 5823 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5824 | set_gdbarch_short_bit (gdbarch, 16); |
5825 | set_gdbarch_int_bit (gdbarch, 32); | |
5826 | set_gdbarch_float_bit (gdbarch, 32); | |
5827 | set_gdbarch_double_bit (gdbarch, 64); | |
5828 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5829 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5830 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5831 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5832 | |
f7ab6ec6 MS |
5833 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5834 | mips_elf_make_msymbol_special); | |
5835 | ||
16e109ca | 5836 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5837 | { |
16e109ca | 5838 | const char **reg_names; |
56cea623 AC |
5839 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5840 | struct mips_regnum); | |
56cea623 AC |
5841 | if (info.osabi == GDB_OSABI_IRIX) |
5842 | { | |
5843 | regnum->fp0 = 32; | |
5844 | regnum->pc = 64; | |
5845 | regnum->cause = 65; | |
5846 | regnum->badvaddr = 66; | |
5847 | regnum->hi = 67; | |
5848 | regnum->lo = 68; | |
5849 | regnum->fp_control_status = 69; | |
5850 | regnum->fp_implementation_revision = 70; | |
5851 | num_regs = 71; | |
16e109ca | 5852 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5853 | } |
5854 | else | |
5855 | { | |
5856 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5857 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5858 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5859 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5860 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5861 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5862 | regnum->fp_control_status = 70; | |
5863 | regnum->fp_implementation_revision = 71; | |
5864 | num_regs = 90; | |
16e109ca AC |
5865 | if (info.bfd_arch_info != NULL |
5866 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5867 | reg_names = mips_tx39_reg_names; | |
5868 | else | |
5869 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5870 | } |
5871 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5872 | replaced by read_pc? */ | |
5873 | set_gdbarch_pc_regnum (gdbarch, regnum->pc); | |
5874 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); | |
5875 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5876 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5877 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5878 | tdep->mips_processor_reg_names = reg_names; | |
5879 | tdep->regnum = regnum; | |
56cea623 | 5880 | } |
fe29b929 | 5881 | |
0dadbba0 | 5882 | switch (mips_abi) |
c2d11a7d | 5883 | { |
0dadbba0 | 5884 | case MIPS_ABI_O32: |
25ab4790 | 5885 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5886 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
a5ea2558 | 5887 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5888 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5889 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5890 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5891 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5892 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5893 | set_gdbarch_long_bit (gdbarch, 32); |
5894 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5895 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5896 | break; | |
0dadbba0 | 5897 | case MIPS_ABI_O64: |
25ab4790 | 5898 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
ebba8386 | 5899 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5900 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5901 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5902 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5903 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5904 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5905 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5906 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5907 | set_gdbarch_long_bit (gdbarch, 32); |
5908 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5909 | set_gdbarch_long_long_bit (gdbarch, 64); | |
b060cbea | 5910 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 5911 | break; |
0dadbba0 | 5912 | case MIPS_ABI_EABI32: |
25ab4790 | 5913 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5914 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5915 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5916 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5917 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5918 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5919 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5920 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5921 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5922 | set_gdbarch_long_bit (gdbarch, 32); |
5923 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5924 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5925 | set_gdbarch_deprecated_reg_struct_has_addr |
5926 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5927 | set_gdbarch_use_struct_convention (gdbarch, |
5928 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5929 | break; |
0dadbba0 | 5930 | case MIPS_ABI_EABI64: |
25ab4790 | 5931 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5932 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5933 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5934 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5935 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5936 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5937 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5938 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5939 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5940 | set_gdbarch_long_bit (gdbarch, 64); |
5941 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5942 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5943 | set_gdbarch_deprecated_reg_struct_has_addr |
5944 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5945 | set_gdbarch_use_struct_convention (gdbarch, |
5946 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5947 | break; |
0dadbba0 | 5948 | case MIPS_ABI_N32: |
25ab4790 | 5949 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5950 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
63db5580 | 5951 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5952 | tdep->mips_default_stack_argsize = 8; |
5953 | tdep->mips_fp_register_double = 1; | |
acdb74a0 | 5954 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5955 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5956 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5957 | set_gdbarch_long_bit (gdbarch, 32); |
5958 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5959 | set_gdbarch_long_long_bit (gdbarch, 64); | |
28d169de KB |
5960 | break; |
5961 | case MIPS_ABI_N64: | |
25ab4790 | 5962 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5963 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de KB |
5964 | tdep->mips_default_saved_regsize = 8; |
5965 | tdep->mips_default_stack_argsize = 8; | |
5966 | tdep->mips_fp_register_double = 1; | |
5967 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
56cea623 | 5968 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5969 | tdep->default_mask_address_p = 0; |
5970 | set_gdbarch_long_bit (gdbarch, 64); | |
5971 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5972 | set_gdbarch_long_long_bit (gdbarch, 64); | |
0dadbba0 | 5973 | break; |
c2d11a7d | 5974 | default: |
2e4ebe70 DJ |
5975 | internal_error (__FILE__, __LINE__, |
5976 | "unknown ABI in switch"); | |
c2d11a7d JM |
5977 | } |
5978 | ||
a5ea2558 AC |
5979 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5980 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5981 | comment: | |
5982 | ||
5983 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5984 | flag in object files because to do so would make it impossible to | |
102182a9 | 5985 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5986 | unnecessarily restrictive. |
361d1df0 | 5987 | |
a5ea2558 AC |
5988 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5989 | but to set this flag before gcc is built with such multilibs will | |
5990 | break too many systems.'' | |
5991 | ||
5992 | But even more unhelpfully, the default linker output target for | |
5993 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5994 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5995 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5996 | this flag to detect 32-bit mode would do the wrong thing given |
5997 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5998 | as 32-bit programs by default. */ |
a5ea2558 | 5999 | |
6c997a34 | 6000 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d | 6001 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
0ba6dca9 | 6002 | set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ |
bcb0cc15 | 6003 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 6004 | |
102182a9 MS |
6005 | /* Add/remove bits from an address. The MIPS needs be careful to |
6006 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6007 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6008 | ||
10312cc4 | 6009 | /* There's a mess in stack frame creation. See comments in |
2ca6c561 AC |
6010 | blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */ |
6011 | set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
10312cc4 | 6012 | |
102182a9 | 6013 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6014 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
2f38ef89 KB |
6015 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
6016 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6017 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6018 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6019 | |
c2d11a7d | 6020 | /* Initialize a frame */ |
e0f7ec59 | 6021 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs); |
e9582e71 | 6022 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); |
c2d11a7d JM |
6023 | |
6024 | /* MIPS version of CALL_DUMMY */ | |
6025 | ||
9710e734 AC |
6026 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6027 | replaced by a command, and all targets will default to on stack | |
6028 | (regardless of the stack's execute status). */ | |
6029 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
749b82f6 | 6030 | set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); |
dc604539 | 6031 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
a59fe496 | 6032 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
d05285fa | 6033 | |
618ce49f | 6034 | set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); |
b5d1566e MS |
6035 | set_gdbarch_frameless_function_invocation (gdbarch, |
6036 | generic_frameless_function_invocation_not); | |
8bedc050 | 6037 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); |
b5d1566e MS |
6038 | set_gdbarch_frame_args_skip (gdbarch, 0); |
6039 | ||
129c1cd6 | 6040 | set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 6041 | |
f7b9e9fc AC |
6042 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6043 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
6044 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
6045 | |
6046 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
6913c89a | 6047 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); |
f7b9e9fc | 6048 | |
fc0c74b1 AC |
6049 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6050 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6051 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6052 | |
102182a9 MS |
6053 | set_gdbarch_function_start_offset (gdbarch, 0); |
6054 | ||
a4b8ebc8 | 6055 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6056 | |
e11c53d2 | 6057 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 6058 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 6059 | |
e5ab0dce AC |
6060 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6061 | ||
3a3bc038 AC |
6062 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6063 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6064 | need to all be folded into the target vector. Since they are | |
6065 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6066 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6067 | is sitting on? */ | |
6068 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6069 | ||
70f80edf | 6070 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 6071 | gdbarch_init_osabi (info, gdbarch); |
70f80edf | 6072 | |
757a7cc6 MS |
6073 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); |
6074 | ||
6075 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 6076 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 6077 | |
4b9b3959 AC |
6078 | return gdbarch; |
6079 | } | |
6080 | ||
2e4ebe70 DJ |
6081 | static void |
6082 | mips_abi_update (char *ignore_args, int from_tty, | |
6083 | struct cmd_list_element *c) | |
6084 | { | |
6085 | struct gdbarch_info info; | |
6086 | ||
6087 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6088 | mips_gdbarch_init will take care of the rest. */ | |
6089 | gdbarch_info_init (&info); | |
6090 | gdbarch_update_p (info); | |
6091 | } | |
6092 | ||
ad188201 KB |
6093 | /* Print out which MIPS ABI is in use. */ |
6094 | ||
6095 | static void | |
6096 | show_mips_abi (char *ignore_args, int from_tty) | |
6097 | { | |
6098 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6099 | printf_filtered ( | |
6100 | "The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
6101 | else | |
6102 | { | |
6103 | enum mips_abi global_abi = global_mips_abi (); | |
6104 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6105 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6106 | ||
6107 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6108 | printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6109 | actual_abi_str); | |
6110 | else if (global_abi == actual_abi) | |
6111 | printf_filtered ( | |
6112 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6113 | actual_abi_str); | |
6114 | else | |
6115 | { | |
6116 | /* Probably shouldn't happen... */ | |
6117 | printf_filtered ( | |
6118 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6119 | actual_abi_str, | |
6120 | mips_abi_strings[global_abi]); | |
6121 | } | |
6122 | } | |
6123 | } | |
6124 | ||
4b9b3959 AC |
6125 | static void |
6126 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6127 | { | |
6128 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6129 | if (tdep != NULL) | |
c2d11a7d | 6130 | { |
acdb74a0 AC |
6131 | int ef_mips_arch; |
6132 | int ef_mips_32bitmode; | |
6133 | /* determine the ISA */ | |
6134 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6135 | { | |
6136 | case E_MIPS_ARCH_1: | |
6137 | ef_mips_arch = 1; | |
6138 | break; | |
6139 | case E_MIPS_ARCH_2: | |
6140 | ef_mips_arch = 2; | |
6141 | break; | |
6142 | case E_MIPS_ARCH_3: | |
6143 | ef_mips_arch = 3; | |
6144 | break; | |
6145 | case E_MIPS_ARCH_4: | |
93d56215 | 6146 | ef_mips_arch = 4; |
acdb74a0 AC |
6147 | break; |
6148 | default: | |
93d56215 | 6149 | ef_mips_arch = 0; |
acdb74a0 AC |
6150 | break; |
6151 | } | |
6152 | /* determine the size of a pointer */ | |
6153 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6154 | fprintf_unfiltered (file, |
6155 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6156 | tdep->elf_flags); |
4b9b3959 | 6157 | fprintf_unfiltered (file, |
acdb74a0 AC |
6158 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6159 | ef_mips_32bitmode); | |
6160 | fprintf_unfiltered (file, | |
6161 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6162 | ef_mips_arch); | |
6163 | fprintf_unfiltered (file, | |
6164 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6165 | tdep->mips_abi, | |
2e4ebe70 | 6166 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6167 | fprintf_unfiltered (file, |
6168 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6169 | mips_mask_address_p (tdep), |
4014092b | 6170 | tdep->default_mask_address_p); |
c2d11a7d | 6171 | } |
4b9b3959 AC |
6172 | fprintf_unfiltered (file, |
6173 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6174 | FP_REGISTER_DOUBLE); | |
6175 | fprintf_unfiltered (file, | |
6176 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6177 | MIPS_DEFAULT_FPU_TYPE, | |
6178 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6179 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6180 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6181 | : "???")); | |
6182 | fprintf_unfiltered (file, | |
6183 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6184 | MIPS_EABI); | |
4b9b3959 AC |
6185 | fprintf_unfiltered (file, |
6186 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6187 | MIPS_FPU_TYPE, | |
6188 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6189 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6190 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6191 | : "???")); | |
4b9b3959 AC |
6192 | fprintf_unfiltered (file, |
6193 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6194 | FP_REGISTER_DOUBLE); | |
4b9b3959 | 6195 | fprintf_unfiltered (file, |
480d3dd2 AC |
6196 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
6197 | mips_stack_argsize (tdep)); | |
2475bac3 AC |
6198 | fprintf_unfiltered (file, |
6199 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6200 | A0_REGNUM); | |
6201 | fprintf_unfiltered (file, | |
6202 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6203 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6204 | fprintf_unfiltered (file, | |
6205 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6206 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6207 | fprintf_unfiltered (file, |
6208 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6209 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6210 | fprintf_unfiltered (file, | |
6211 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6212 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6213 | fprintf_unfiltered (file, |
6214 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6215 | FIRST_EMBED_REGNUM); | |
2475bac3 AC |
6216 | fprintf_unfiltered (file, |
6217 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6218 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6219 | fprintf_unfiltered (file, |
6220 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6221 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6222 | fprintf_unfiltered (file, | |
6223 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6224 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6225 | fprintf_unfiltered (file, |
6226 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6227 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6228 | #ifdef MACHINE_CPROC_FP_OFFSET |
6229 | fprintf_unfiltered (file, | |
6230 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6231 | MACHINE_CPROC_FP_OFFSET); | |
6232 | #endif | |
6233 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6234 | fprintf_unfiltered (file, | |
6235 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6236 | MACHINE_CPROC_PC_OFFSET); | |
6237 | #endif | |
6238 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6239 | fprintf_unfiltered (file, | |
6240 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6241 | MACHINE_CPROC_SP_OFFSET); | |
6242 | #endif | |
2475bac3 AC |
6243 | fprintf_unfiltered (file, |
6244 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6245 | MIPS16_INSTLEN); | |
2475bac3 AC |
6246 | fprintf_unfiltered (file, |
6247 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6248 | fprintf_unfiltered (file, | |
6249 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6250 | fprintf_unfiltered (file, | |
6251 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6252 | MIPS_INSTLEN); | |
6253 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6254 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6255 | MIPS_LAST_ARG_REGNUM, | |
6256 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6257 | fprintf_unfiltered (file, |
6258 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6259 | MIPS_NUMREGS); | |
2475bac3 | 6260 | fprintf_unfiltered (file, |
480d3dd2 AC |
6261 | "mips_dump_tdep: mips_saved_regsize() = %d\n", |
6262 | mips_saved_regsize (tdep)); | |
2475bac3 AC |
6263 | fprintf_unfiltered (file, |
6264 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6265 | PRID_REGNUM); | |
2475bac3 AC |
6266 | fprintf_unfiltered (file, |
6267 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6268 | fprintf_unfiltered (file, | |
6269 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6270 | fprintf_unfiltered (file, | |
6271 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6272 | fprintf_unfiltered (file, | |
6273 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6274 | fprintf_unfiltered (file, | |
6275 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6276 | fprintf_unfiltered (file, | |
6277 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6278 | fprintf_unfiltered (file, | |
6279 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6280 | fprintf_unfiltered (file, | |
6281 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6282 | fprintf_unfiltered (file, | |
6283 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6284 | fprintf_unfiltered (file, | |
6285 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6286 | fprintf_unfiltered (file, | |
6287 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6288 | fprintf_unfiltered (file, | |
6289 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6290 | fprintf_unfiltered (file, | |
6291 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6292 | PS_REGNUM); | |
2475bac3 AC |
6293 | fprintf_unfiltered (file, |
6294 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6295 | RA_REGNUM); | |
2475bac3 AC |
6296 | #ifdef SAVED_BYTES |
6297 | fprintf_unfiltered (file, | |
6298 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6299 | SAVED_BYTES); | |
6300 | #endif | |
6301 | #ifdef SAVED_FP | |
6302 | fprintf_unfiltered (file, | |
6303 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6304 | SAVED_FP); | |
6305 | #endif | |
6306 | #ifdef SAVED_PC | |
6307 | fprintf_unfiltered (file, | |
6308 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6309 | SAVED_PC); | |
6310 | #endif | |
6311 | fprintf_unfiltered (file, | |
6312 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6313 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6314 | fprintf_unfiltered (file, | |
6315 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6316 | fprintf_unfiltered (file, | |
6317 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6318 | SIGFRAME_BASE); | |
6319 | fprintf_unfiltered (file, | |
6320 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6321 | SIGFRAME_FPREGSAVE_OFF); | |
6322 | fprintf_unfiltered (file, | |
6323 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6324 | SIGFRAME_PC_OFF); | |
6325 | fprintf_unfiltered (file, | |
6326 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6327 | SIGFRAME_REGSAVE_OFF); | |
2475bac3 AC |
6328 | fprintf_unfiltered (file, |
6329 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6330 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6331 | fprintf_unfiltered (file, | |
6332 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6333 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6334 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6335 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6336 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6337 | fprintf_unfiltered (file, |
6338 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6339 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6340 | #ifdef STACK_END_ADDR | |
6341 | fprintf_unfiltered (file, | |
6342 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6343 | STACK_END_ADDR); | |
6344 | #endif | |
6345 | fprintf_unfiltered (file, | |
6346 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6347 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6348 | fprintf_unfiltered (file, | |
6349 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6350 | STEP_SKIPS_DELAY_P); | |
6351 | fprintf_unfiltered (file, | |
6352 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6353 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6354 | fprintf_unfiltered (file, | |
6355 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6356 | T9_REGNUM); | |
6357 | fprintf_unfiltered (file, | |
6358 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6359 | fprintf_unfiltered (file, | |
6360 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6361 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6362 | fprintf_unfiltered (file, | |
6363 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6364 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6365 | #ifdef TRACE_CLEAR |
6366 | fprintf_unfiltered (file, | |
6367 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6368 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6369 | #endif | |
6370 | #ifdef TRACE_FLAVOR | |
6371 | fprintf_unfiltered (file, | |
6372 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6373 | TRACE_FLAVOR); | |
6374 | #endif | |
6375 | #ifdef TRACE_FLAVOR_SIZE | |
6376 | fprintf_unfiltered (file, | |
6377 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6378 | TRACE_FLAVOR_SIZE); | |
6379 | #endif | |
6380 | #ifdef TRACE_SET | |
6381 | fprintf_unfiltered (file, | |
6382 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6383 | XSTRING (TRACE_SET (X,STATE))); | |
6384 | #endif | |
2475bac3 AC |
6385 | #ifdef UNUSED_REGNUM |
6386 | fprintf_unfiltered (file, | |
6387 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6388 | UNUSED_REGNUM); | |
6389 | #endif | |
6390 | fprintf_unfiltered (file, | |
6391 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6392 | V0_REGNUM); | |
6393 | fprintf_unfiltered (file, | |
6394 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6395 | (long) VM_MIN_ADDRESS); | |
2475bac3 AC |
6396 | fprintf_unfiltered (file, |
6397 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6398 | ZERO_REGNUM); | |
6399 | fprintf_unfiltered (file, | |
6400 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6401 | _PROC_MAGIC_); | |
c2d11a7d JM |
6402 | } |
6403 | ||
a78f21af AC |
6404 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
6405 | ||
c906108c | 6406 | void |
acdb74a0 | 6407 | _initialize_mips_tdep (void) |
c906108c SS |
6408 | { |
6409 | static struct cmd_list_element *mipsfpulist = NULL; | |
6410 | struct cmd_list_element *c; | |
6411 | ||
2e4ebe70 DJ |
6412 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6413 | if (MIPS_ABI_LAST + 1 | |
6414 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6415 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6416 | ||
4b9b3959 | 6417 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6418 | |
a5ea2558 AC |
6419 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6420 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6421 | "Various MIPS specific commands.", | |
6422 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6423 | ||
6424 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6425 | "Various MIPS specific commands.", | |
6426 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6427 | ||
6428 | /* Allow the user to override the saved register size. */ | |
6429 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6430 | class_obscure, |
6431 | size_enums, | |
6432 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6433 | Set size of general purpose registers saved on the stack.\n\ |
6434 | This option can be set to one of:\n\ | |
6435 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6436 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6437 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6438 | saved GP register size from information contained in the executable.\n\ | |
6439 | (default: auto)", | |
1ed2a135 | 6440 | &setmipscmdlist), |
a5ea2558 AC |
6441 | &showmipscmdlist); |
6442 | ||
d929b26f AC |
6443 | /* Allow the user to override the argument stack size. */ |
6444 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6445 | class_obscure, | |
6446 | size_enums, | |
1ed2a135 | 6447 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6448 | Set the amount of stack space reserved for each argument.\n\ |
6449 | This option can be set to one of:\n\ | |
6450 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6451 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6452 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6453 | target and executable (default)", | |
6454 | &setmipscmdlist), | |
6455 | &showmipscmdlist); | |
6456 | ||
2e4ebe70 DJ |
6457 | /* Allow the user to override the ABI. */ |
6458 | c = add_set_enum_cmd | |
6459 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6460 | "Set the ABI used by this program.\n" | |
6461 | "This option can be set to one of:\n" | |
6462 | " auto - the default ABI associated with the current binary\n" | |
6463 | " o32\n" | |
6464 | " o64\n" | |
6465 | " n32\n" | |
f3a7b3a5 | 6466 | " n64\n" |
2e4ebe70 DJ |
6467 | " eabi32\n" |
6468 | " eabi64", | |
6469 | &setmipscmdlist); | |
2e4ebe70 | 6470 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 KB |
6471 | add_cmd ("abi", class_obscure, show_mips_abi, |
6472 | "Show ABI in use by MIPS target", &showmipscmdlist); | |
2e4ebe70 | 6473 | |
c906108c SS |
6474 | /* Let the user turn off floating point and set the fence post for |
6475 | heuristic_proc_start. */ | |
6476 | ||
6477 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6478 | "Set use of MIPS floating-point coprocessor.", | |
6479 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6480 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6481 | "Select single-precision MIPS floating-point coprocessor.", | |
6482 | &mipsfpulist); | |
6483 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6484 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6485 | &mipsfpulist); |
6486 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6487 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6488 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6489 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6490 | "Select no MIPS floating-point coprocessor.", | |
6491 | &mipsfpulist); | |
6492 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6493 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6494 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6495 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6496 | "Select MIPS floating-point coprocessor automatically.", | |
6497 | &mipsfpulist); | |
6498 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6499 | "Show current use of MIPS floating-point coprocessor target.", | |
6500 | &showlist); | |
6501 | ||
c906108c SS |
6502 | /* We really would like to have both "0" and "unlimited" work, but |
6503 | command.c doesn't deal with that. So make it a var_zinteger | |
6504 | because the user can always use "999999" or some such for unlimited. */ | |
6505 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6506 | (char *) &heuristic_fence_post, | |
6507 | "\ | |
6508 | Set the distance searched for the start of a function.\n\ | |
6509 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6510 | program for the start of a function. This command sets the distance of the\n\ | |
6511 | search. The only need to set it is when debugging a stripped executable.", | |
6512 | &setlist); | |
6513 | /* We need to throw away the frame cache when we set this, since it | |
6514 | might change our ability to get backtraces. */ | |
9f60d481 | 6515 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6516 | add_show_from_set (c, &showlist); |
6517 | ||
6518 | /* Allow the user to control whether the upper bits of 64-bit | |
6519 | addresses should be zeroed. */ | |
e9e68a56 AC |
6520 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6521 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6522 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6523 | allow GDB to determine the correct value.\n", "\ | |
6524 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6525 | NULL, show_mask_address, | |
6526 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6527 | |
6528 | /* Allow the user to control the size of 32 bit registers within the | |
6529 | raw remote packet. */ | |
719ec221 AC |
6530 | add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6531 | var_boolean, &mips64_transfers_32bit_regs_p, "\ | |
6532 | Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
6533 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6534 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6535 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ | |
6536 | Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
43e526b9 JM |
6537 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6538 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6539 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
719ec221 AC |
6540 | set_mips64_transfers_32bit_regs, NULL, |
6541 | &setlist, &showlist); | |
9ace0497 AC |
6542 | |
6543 | /* Debug this files internals. */ | |
6544 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6545 | &mips_debug, "Set mips debugging.\n\ | |
6546 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6547 | &showdebuglist); | |
c906108c | 6548 | } |