Commit | Line | Data |
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7d9884b9 | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
97e091b2 | 2 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996 |
0434c1a0 | 3 | Free Software Foundation, Inc. |
bd5635a1 RP |
4 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
5 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
361bf6ee | 9 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 10 | it under the terms of the GNU General Public License as published by |
361bf6ee JG |
11 | the Free Software Foundation; either version 2 of the License, or |
12 | (at your option) any later version. | |
bd5635a1 | 13 | |
361bf6ee | 14 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
361bf6ee | 20 | along with this program; if not, write to the Free Software |
09af5868 | 21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
bd5635a1 | 22 | |
bd5635a1 | 23 | #include "defs.h" |
09af5868 | 24 | #include "gdb_string.h" |
bd5635a1 RP |
25 | #include "frame.h" |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "value.h" | |
29 | #include "gdbcmd.h" | |
ef08856f | 30 | #include "language.h" |
bd5635a1 | 31 | #include "gdbcore.h" |
62a469e1 SG |
32 | #include "symfile.h" |
33 | #include "objfiles.h" | |
3fed1c4a | 34 | #include "gdbtypes.h" |
28444bf3 | 35 | #include "target.h" |
bd5635a1 | 36 | |
ee5fb959 JK |
37 | #include "opcode/mips.h" |
38 | ||
28444bf3 | 39 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
70126bf9 KH |
40 | |
41 | /* FIXME: Put this declaration in frame.h. */ | |
42 | extern struct obstack frame_cache_obstack; | |
28444bf3 | 43 | |
002a422b | 44 | #if 0 |
ee5fb959 | 45 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
002a422b | 46 | #endif |
ee5fb959 | 47 | |
28444bf3 DP |
48 | static int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *)); |
49 | ||
f2bf454e FF |
50 | static void mips_print_register PARAMS ((int, int)); |
51 | ||
52 | static mips_extra_func_info_t | |
53 | heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *)); | |
54 | ||
55 | static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR)); | |
56 | ||
28444bf3 | 57 | static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int)); |
f2bf454e | 58 | |
e4dbd248 PS |
59 | static void mips_set_fpu_command PARAMS ((char *, int, |
60 | struct cmd_list_element *)); | |
61 | ||
62 | static void mips_show_fpu_command PARAMS ((char *, int, | |
63 | struct cmd_list_element *)); | |
64 | ||
9f9f94aa SS |
65 | void mips_set_processor_type_command PARAMS ((char *, int)); |
66 | ||
1d9489c1 JK |
67 | int mips_set_processor_type PARAMS ((char *)); |
68 | ||
69 | static void mips_show_processor_type_command PARAMS ((char *, int)); | |
70 | ||
9f9f94aa SS |
71 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, |
72 | struct cmd_list_element *)); | |
73 | ||
f2bf454e FF |
74 | static mips_extra_func_info_t |
75 | find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info *next_frame)); | |
76 | ||
77 | static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc, | |
78 | mips_extra_func_info_t proc_desc)); | |
79 | ||
9f9f94aa SS |
80 | /* This value is the model of MIPS in use. It is derived from the value |
81 | of the PrID register. */ | |
82 | ||
83 | char *mips_processor_type; | |
84 | ||
85 | char *tmp_mips_processor_type; | |
86 | ||
c2a0f1cb ILT |
87 | /* Some MIPS boards don't support floating point, so we permit the |
88 | user to turn it off. */ | |
9f9f94aa | 89 | |
e4dbd248 PS |
90 | enum mips_fpu_type mips_fpu; |
91 | ||
92 | static char *mips_fpu_string; | |
c2a0f1cb | 93 | |
9f9f94aa SS |
94 | /* A set of original names, to be used when restoring back to generic |
95 | registers from a specific set. */ | |
96 | ||
97 | char *mips_generic_reg_names[] = REGISTER_NAMES; | |
98 | ||
99 | /* Names of IDT R3041 registers. */ | |
100 | ||
101 | char *mips_r3041_reg_names[] = { | |
102 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
103 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
104 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
105 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
106 | "sr", "lo", "hi", "bad", "cause","pc", | |
107 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
108 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
109 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
110 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
111 | "fsr", "fir", "fp", "", | |
112 | "", "", "bus", "ccfg", "", "", "", "", | |
113 | "", "", "port", "cmp", "", "", "epc", "prid", | |
114 | }; | |
115 | ||
116 | /* Names of IDT R3051 registers. */ | |
117 | ||
118 | char *mips_r3051_reg_names[] = { | |
119 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
120 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
121 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
122 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
123 | "sr", "lo", "hi", "bad", "cause","pc", | |
124 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
125 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
126 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
127 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
128 | "fsr", "fir", "fp", "", | |
129 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
130 | "", "", "ehi", "", "", "", "epc", "prid", | |
131 | }; | |
132 | ||
133 | /* Names of IDT R3081 registers. */ | |
134 | ||
135 | char *mips_r3081_reg_names[] = { | |
136 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
137 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
138 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
139 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
140 | "sr", "lo", "hi", "bad", "cause","pc", | |
141 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
142 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
143 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
144 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
145 | "fsr", "fir", "fp", "", | |
146 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
147 | "", "", "ehi", "", "", "", "epc", "prid", | |
148 | }; | |
149 | ||
e4dbd248 PS |
150 | /* Names of LSI 33k registers. */ |
151 | ||
152 | char *mips_lsi33k_reg_names[] = { | |
153 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
154 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
155 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
156 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
157 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
158 | "dcic", "bpc", "bda", "", "", "", "", "", | |
159 | "", "", "", "", "", "", "", "", | |
160 | "", "", "", "", "", "", "", "", | |
161 | "", "", "", "", "", "", "", "", | |
162 | "", "", "", "", | |
163 | "", "", "", "", "", "", "", "", | |
164 | "", "", "", "", "", "", "", "", | |
165 | }; | |
166 | ||
9f9f94aa SS |
167 | struct { |
168 | char *name; | |
169 | char **regnames; | |
170 | } mips_processor_type_table[] = { | |
171 | { "generic", mips_generic_reg_names }, | |
172 | { "r3041", mips_r3041_reg_names }, | |
173 | { "r3051", mips_r3051_reg_names }, | |
174 | { "r3071", mips_r3081_reg_names }, | |
175 | { "r3081", mips_r3081_reg_names }, | |
e4dbd248 | 176 | { "lsi33k", mips_lsi33k_reg_names }, |
9f9f94aa SS |
177 | { NULL, NULL } |
178 | }; | |
179 | ||
f9f8c14b MA |
180 | /* Table to translate MIPS16 register field to actual register number. */ |
181 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; | |
182 | ||
3127785a RP |
183 | /* Heuristic_proc_start may hunt through the text section for a long |
184 | time across a 2400 baud serial line. Allows the user to limit this | |
185 | search. */ | |
9f9f94aa | 186 | |
3127785a RP |
187 | static unsigned int heuristic_fence_post = 0; |
188 | ||
0f552c5f | 189 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
28444bf3 | 190 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ |
0f552c5f JG |
191 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
192 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
193 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
194 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
195 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
196 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
197 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
198 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
bd5635a1 | 199 | #define _PROC_MAGIC_ 0x0F0F0F0F |
0f552c5f JG |
200 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
201 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
bd5635a1 RP |
202 | |
203 | struct linked_proc_info | |
204 | { | |
205 | struct mips_extra_func_info info; | |
206 | struct linked_proc_info *next; | |
dac4929a | 207 | } *linked_proc_desc_table = NULL; |
bd5635a1 | 208 | |
f2bf454e | 209 | |
899c4021 MA |
210 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
211 | ||
212 | static int | |
213 | pc_is_mips16 (bfd_vma memaddr) | |
214 | { | |
215 | struct minimal_symbol *sym; | |
216 | ||
217 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
218 | if (IS_MIPS16_ADDR (memaddr)) | |
219 | return 1; | |
220 | ||
221 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
222 | the high bit of the info field. Use this to decide if the function is | |
223 | MIPS16 or normal MIPS. */ | |
224 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
225 | if (sym) | |
226 | return MSYMBOL_IS_SPECIAL (sym); | |
227 | else | |
228 | return 0; | |
229 | } | |
230 | ||
231 | ||
f2bf454e FF |
232 | /* This returns the PC of the first inst after the prologue. If we can't |
233 | find the prologue, then return 0. */ | |
234 | ||
235 | static CORE_ADDR | |
236 | after_prologue (pc, proc_desc) | |
237 | CORE_ADDR pc; | |
238 | mips_extra_func_info_t proc_desc; | |
239 | { | |
240 | struct symtab_and_line sal; | |
241 | CORE_ADDR func_addr, func_end; | |
242 | ||
243 | if (!proc_desc) | |
244 | proc_desc = find_proc_desc (pc, NULL); | |
245 | ||
246 | if (proc_desc) | |
247 | { | |
248 | /* If function is frameless, then we need to do it the hard way. I | |
249 | strongly suspect that frameless always means prologueless... */ | |
250 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
251 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
252 | return 0; | |
253 | } | |
254 | ||
255 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
256 | return 0; /* Unknown */ | |
257 | ||
258 | sal = find_pc_line (func_addr, 0); | |
259 | ||
260 | if (sal.end < func_end) | |
261 | return sal.end; | |
262 | ||
263 | /* The line after the prologue is after the end of the function. In this | |
264 | case, tell the caller to find the prologue the hard way. */ | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
f9f8c14b MA |
269 | /* Decode a MIPS32 instruction that saves a register in the stack, and |
270 | set the appropriate bit in the general register mask or float register mask | |
271 | to indicate which register is saved. This is a helper function | |
272 | for mips_find_saved_regs. */ | |
273 | ||
274 | static void | |
275 | mips32_decode_reg_save (inst, gen_mask, float_mask) | |
276 | t_inst inst; | |
277 | unsigned long *gen_mask; | |
278 | unsigned long *float_mask; | |
279 | { | |
280 | int reg; | |
281 | ||
282 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
283 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
284 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
285 | { | |
286 | /* It might be possible to use the instruction to | |
287 | find the offset, rather than the code below which | |
288 | is based on things being in a certain order in the | |
289 | frame, but figuring out what the instruction's offset | |
290 | is relative to might be a little tricky. */ | |
291 | reg = (inst & 0x001f0000) >> 16; | |
292 | *gen_mask |= (1 << reg); | |
293 | } | |
294 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
295 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ | |
296 | || (inst & 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */ | |
297 | ||
298 | { | |
299 | reg = ((inst & 0x001f0000) >> 16); | |
300 | *float_mask |= (1 << reg); | |
301 | } | |
302 | } | |
303 | ||
304 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
305 | set the appropriate bit in the general register or float register mask | |
306 | to indicate which register is saved. This is a helper function | |
307 | for mips_find_saved_regs. */ | |
308 | ||
309 | static void | |
310 | mips16_decode_reg_save (inst, gen_mask) | |
311 | t_inst inst; | |
312 | unsigned long *gen_mask; | |
313 | { | |
b348b9fd | 314 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
f9f8c14b | 315 | { |
b348b9fd MA |
316 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; |
317 | *gen_mask |= (1 << reg); | |
318 | } | |
319 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
320 | { | |
321 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
f9f8c14b MA |
322 | *gen_mask |= (1 << reg); |
323 | } | |
324 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ | |
325 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
326 | *gen_mask |= (1 << 31); | |
327 | } | |
328 | ||
c81a76b3 MA |
329 | |
330 | /* Fetch and return instruction from the specified location. If the PC | |
331 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
332 | ||
333 | static t_inst | |
334 | mips_fetch_instruction (addr) | |
335 | CORE_ADDR addr; | |
336 | { | |
337 | char buf[MIPS_INSTLEN]; | |
338 | int instlen; | |
339 | int status; | |
340 | ||
899c4021 | 341 | if (pc_is_mips16 (addr)) |
c81a76b3 MA |
342 | { |
343 | instlen = MIPS16_INSTLEN; | |
344 | addr = UNMAKE_MIPS16_ADDR (addr); | |
345 | } | |
346 | else | |
347 | instlen = MIPS_INSTLEN; | |
348 | status = read_memory_nobpt (addr, buf, instlen); | |
349 | if (status) | |
350 | memory_error (status, addr); | |
351 | return extract_unsigned_integer (buf, instlen); | |
352 | } | |
353 | ||
354 | ||
70126bf9 KH |
355 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
356 | NULL). */ | |
357 | ||
358 | void | |
359 | mips_find_saved_regs (fci) | |
9f9f94aa | 360 | struct frame_info *fci; |
70126bf9 KH |
361 | { |
362 | int ireg; | |
363 | CORE_ADDR reg_position; | |
364 | /* r0 bit means kernel trap */ | |
365 | int kernel_trap; | |
366 | /* What registers have been saved? Bitmasks. */ | |
367 | unsigned long gen_mask, float_mask; | |
368 | mips_extra_func_info_t proc_desc; | |
c81a76b3 | 369 | t_inst inst; |
70126bf9 KH |
370 | |
371 | fci->saved_regs = (struct frame_saved_regs *) | |
372 | obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs)); | |
373 | memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs)); | |
374 | ||
e4dbd248 PS |
375 | /* If it is the frame for sigtramp, the saved registers are located |
376 | in a sigcontext structure somewhere on the stack. | |
377 | If the stack layout for sigtramp changes we might have to change these | |
378 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
379 | #ifndef SIGFRAME_BASE | |
380 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
381 | above the sigtramp frame. */ | |
28444bf3 DP |
382 | #define SIGFRAME_BASE MIPS_REGSIZE |
383 | /* FIXME! Are these correct?? */ | |
384 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
385 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
386 | #define SIGFRAME_FPREGSAVE_OFF \ | |
387 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
e4dbd248 PS |
388 | #endif |
389 | #ifndef SIGFRAME_REG_SIZE | |
28444bf3 DP |
390 | /* FIXME! Is this correct?? */ |
391 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
e4dbd248 PS |
392 | #endif |
393 | if (fci->signal_handler_caller) | |
394 | { | |
28444bf3 | 395 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
396 | { |
397 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF | |
398 | + ireg * SIGFRAME_REG_SIZE; | |
399 | fci->saved_regs->regs[ireg] = reg_position; | |
400 | } | |
28444bf3 | 401 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
402 | { |
403 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF | |
404 | + ireg * SIGFRAME_REG_SIZE; | |
405 | fci->saved_regs->regs[FP0_REGNUM + ireg] = reg_position; | |
406 | } | |
407 | fci->saved_regs->regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
408 | return; | |
409 | } | |
410 | ||
70126bf9 KH |
411 | proc_desc = fci->proc_desc; |
412 | if (proc_desc == NULL) | |
413 | /* I'm not sure how/whether this can happen. Normally when we can't | |
414 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
415 | and set the saved_regs right away. */ | |
416 | return; | |
417 | ||
418 | kernel_trap = PROC_REG_MASK(proc_desc) & 1; | |
419 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); | |
420 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); | |
421 | ||
f9f8c14b MA |
422 | if (/* In any frame other than the innermost or a frame interrupted by |
423 | a signal, we assume that all registers have been saved. | |
424 | This assumes that all register saves in a function happen before | |
425 | the first function call. */ | |
426 | (fci->next == NULL || fci->next->signal_handler_caller) | |
70126bf9 KH |
427 | |
428 | /* In a dummy frame we know exactly where things are saved. */ | |
429 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
430 | ||
f2bf454e FF |
431 | /* Don't bother unless we are inside a function prologue. Outside the |
432 | prologue, we know where everything is. */ | |
433 | ||
434 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) | |
435 | ||
70126bf9 KH |
436 | /* Not sure exactly what kernel_trap means, but if it means |
437 | the kernel saves the registers without a prologue doing it, | |
438 | we better not examine the prologue to see whether registers | |
439 | have been saved yet. */ | |
440 | && !kernel_trap) | |
441 | { | |
442 | /* We need to figure out whether the registers that the proc_desc | |
443 | claims are saved have been saved yet. */ | |
444 | ||
445 | CORE_ADDR addr; | |
70126bf9 KH |
446 | |
447 | /* Bitmasks; set if we have found a save for the register. */ | |
448 | unsigned long gen_save_found = 0; | |
449 | unsigned long float_save_found = 0; | |
c81a76b3 | 450 | int instlen; |
70126bf9 | 451 | |
c1fc0935 MA |
452 | /* If the address is odd, assume this is MIPS16 code. */ |
453 | addr = PROC_LOW_ADDR (proc_desc); | |
899c4021 | 454 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
f9f8c14b | 455 | |
20fa0902 MA |
456 | /* Scan through this function's instructions preceding the current |
457 | PC, and look for those that save registers. */ | |
f9f8c14b MA |
458 | while (addr < fci->pc) |
459 | { | |
c81a76b3 | 460 | inst = mips_fetch_instruction (addr); |
899c4021 | 461 | if (pc_is_mips16 (addr)) |
f9f8c14b MA |
462 | mips16_decode_reg_save (inst, &gen_save_found); |
463 | else | |
464 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
465 | addr += instlen; | |
70126bf9 KH |
466 | } |
467 | gen_mask = gen_save_found; | |
468 | float_mask = float_save_found; | |
469 | } | |
470 | ||
471 | /* Fill in the offsets for the registers which gen_mask says | |
472 | were saved. */ | |
473 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
28444bf3 | 474 | for (ireg= MIPS_NUMREGS-1; gen_mask; --ireg, gen_mask <<= 1) |
70126bf9 KH |
475 | if (gen_mask & 0x80000000) |
476 | { | |
477 | fci->saved_regs->regs[ireg] = reg_position; | |
478 | reg_position -= MIPS_REGSIZE; | |
479 | } | |
c81a76b3 MA |
480 | |
481 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
482 | of that normally used by gcc. Therefore, we have to fetch the first | |
483 | instruction of the function, and if it's an entry instruction that | |
484 | saves $s0 or $s1, correct their saved addresses. */ | |
899c4021 | 485 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
c81a76b3 MA |
486 | { |
487 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
488 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
489 | { | |
490 | int reg; | |
491 | int sreg_count = (inst >> 6) & 3; | |
492 | ||
493 | /* Check if the ra register was pushed on the stack. */ | |
494 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
495 | if (inst & 0x20) | |
496 | reg_position -= MIPS_REGSIZE; | |
497 | ||
498 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
499 | for (reg = 16; reg < sreg_count+16; reg++) | |
500 | { | |
501 | fci->saved_regs->regs[reg] = reg_position; | |
502 | reg_position -= MIPS_REGSIZE; | |
503 | } | |
504 | } | |
505 | } | |
506 | ||
70126bf9 KH |
507 | /* Fill in the offsets for the registers which float_mask says |
508 | were saved. */ | |
509 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
510 | ||
511 | /* The freg_offset points to where the first *double* register | |
512 | is saved. So skip to the high-order word. */ | |
28444bf3 | 513 | if (! GDB_TARGET_IS_MIPS64) |
c81a76b3 | 514 | reg_position += MIPS_REGSIZE; |
28444bf3 | 515 | |
20fa0902 MA |
516 | /* Fill in the offsets for the float registers which float_mask says |
517 | were saved. */ | |
28444bf3 | 518 | for (ireg = MIPS_NUMREGS-1; float_mask; --ireg, float_mask <<= 1) |
70126bf9 KH |
519 | if (float_mask & 0x80000000) |
520 | { | |
521 | fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position; | |
522 | reg_position -= MIPS_REGSIZE; | |
523 | } | |
524 | ||
525 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; | |
526 | } | |
bd5635a1 | 527 | |
28444bf3 | 528 | static CORE_ADDR |
bd5635a1 | 529 | read_next_frame_reg(fi, regno) |
9f9f94aa | 530 | struct frame_info *fi; |
bd5635a1 RP |
531 | int regno; |
532 | { | |
bd5635a1 | 533 | for (; fi; fi = fi->next) |
70126bf9 | 534 | { |
e4dbd248 PS |
535 | /* We have to get the saved sp from the sigcontext |
536 | if it is a signal handler frame. */ | |
537 | if (regno == SP_REGNUM && !fi->signal_handler_caller) | |
538 | return fi->frame; | |
70126bf9 KH |
539 | else |
540 | { | |
541 | if (fi->saved_regs == NULL) | |
542 | mips_find_saved_regs (fi); | |
543 | if (fi->saved_regs->regs[regno]) | |
544 | return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE); | |
545 | } | |
546 | } | |
547 | return read_register (regno); | |
bd5635a1 RP |
548 | } |
549 | ||
96431497 MA |
550 | /* mips_addr_bits_remove - remove useless address bits */ |
551 | ||
552 | CORE_ADDR | |
553 | mips_addr_bits_remove (addr) | |
554 | CORE_ADDR addr; | |
555 | { | |
97e091b2 MA |
556 | #if GDB_TARGET_IS_MIPS64 |
557 | if ((addr >> 32 == (CORE_ADDR)0xffffffff) | |
f781fe93 MA |
558 | && (strcmp (target_shortname,"pmon")==0 |
559 | || strcmp (target_shortname,"ddb")==0 | |
560 | || strcmp (target_shortname,"sim")==0)) | |
96431497 MA |
561 | { |
562 | /* This hack is a work-around for existing boards using PMON, | |
563 | the simulator, and any other 64-bit targets that doesn't have | |
564 | true 64-bit addressing. On these targets, the upper 32 bits | |
565 | of addresses are ignored by the hardware. Thus, the PC or SP | |
566 | are likely to have been sign extended to all 1s by instruction | |
567 | sequences that load 32-bit addresses. For example, a typical | |
568 | piece of code that loads an address is this: | |
569 | lui $r2, <upper 16 bits> | |
570 | ori $r2, <lower 16 bits> | |
571 | But the lui sign-extends the value such that the upper 32 bits | |
572 | may be all 1s. The workaround is simply to mask off these bits. | |
573 | In the future, gcc may be changed to support true 64-bit | |
574 | addressing, and this masking will have to be disabled. */ | |
575 | addr &= (CORE_ADDR)0xffffffff; | |
576 | } | |
f9f8c14b MA |
577 | #else |
578 | /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf), | |
579 | BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits. | |
580 | So we still have to mask off useless bits from addresses. */ | |
581 | addr &= (CORE_ADDR)0xffffffff; | |
97e091b2 | 582 | #endif |
96431497 MA |
583 | |
584 | return addr; | |
585 | } | |
586 | ||
f781fe93 MA |
587 | void |
588 | mips_init_frame_pc_first (fromleaf, prev) | |
589 | int fromleaf; | |
590 | struct frame_info *prev; | |
591 | { | |
592 | CORE_ADDR pc, tmp; | |
593 | ||
594 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
595 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); | |
596 | tmp = mips_skip_stub (pc); | |
597 | prev->pc = tmp ? tmp : pc; | |
598 | } | |
599 | ||
600 | ||
28444bf3 | 601 | CORE_ADDR |
bd5635a1 | 602 | mips_frame_saved_pc(frame) |
9f9f94aa | 603 | struct frame_info *frame; |
bd5635a1 | 604 | { |
28444bf3 | 605 | CORE_ADDR saved_pc; |
0f552c5f | 606 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
0434c1a0 PS |
607 | /* We have to get the saved pc from the sigcontext |
608 | if it is a signal handler frame. */ | |
609 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
610 | : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); | |
0f552c5f | 611 | |
bd5635a1 | 612 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
28444bf3 DP |
613 | saved_pc = read_memory_integer(frame->frame - MIPS_REGSIZE, MIPS_REGSIZE); |
614 | else | |
615 | saved_pc = read_next_frame_reg(frame, pcreg); | |
0f552c5f | 616 | |
96431497 | 617 | return ADDR_BITS_REMOVE (saved_pc); |
bd5635a1 RP |
618 | } |
619 | ||
620 | static struct mips_extra_func_info temp_proc_desc; | |
621 | static struct frame_saved_regs temp_saved_regs; | |
622 | ||
a8172eea RP |
623 | /* This fencepost looks highly suspicious to me. Removing it also |
624 | seems suspicious as it could affect remote debugging across serial | |
3127785a | 625 | lines. */ |
a8172eea | 626 | |
0f552c5f JG |
627 | static CORE_ADDR |
628 | heuristic_proc_start(pc) | |
bd5635a1 RP |
629 | CORE_ADDR pc; |
630 | { | |
32dab603 MA |
631 | CORE_ADDR start_pc; |
632 | CORE_ADDR fence; | |
20fa0902 | 633 | int instlen; |
b348b9fd | 634 | int seen_adjsp = 0; |
0f552c5f | 635 | |
32dab603 MA |
636 | pc = ADDR_BITS_REMOVE (pc); |
637 | start_pc = pc; | |
638 | fence = start_pc - heuristic_fence_post; | |
0f552c5f | 639 | if (start_pc == 0) return 0; |
3127785a RP |
640 | |
641 | if (heuristic_fence_post == UINT_MAX | |
642 | || fence < VM_MIN_ADDRESS) | |
643 | fence = VM_MIN_ADDRESS; | |
0f552c5f | 644 | |
899c4021 | 645 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
20fa0902 | 646 | |
bd5635a1 | 647 | /* search back for previous return */ |
20fa0902 | 648 | for (start_pc -= instlen; ; start_pc -= instlen) |
a8172eea RP |
649 | if (start_pc < fence) |
650 | { | |
3127785a RP |
651 | /* It's not clear to me why we reach this point when |
652 | stop_soon_quietly, but with this test, at least we | |
653 | don't print out warnings for every child forked (eg, on | |
654 | decstation). 22apr93 rich@cygnus.com. */ | |
655 | if (!stop_soon_quietly) | |
656 | { | |
23d35572 JK |
657 | static int blurb_printed = 0; |
658 | ||
3127785a RP |
659 | if (fence == VM_MIN_ADDRESS) |
660 | warning("Hit beginning of text section without finding"); | |
661 | else | |
662 | warning("Hit heuristic-fence-post without finding"); | |
663 | ||
f781fe93 | 664 | warning("enclosing function for address 0x%s", paddr_nz (pc)); |
23d35572 JK |
665 | if (!blurb_printed) |
666 | { | |
667 | printf_filtered ("\ | |
668 | This warning occurs if you are debugging a function without any symbols\n\ | |
669 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
670 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
671 | \n\ | |
672 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
673 | (more likely) you have encountered a bug in GDB.\n"); | |
674 | blurb_printed = 1; | |
675 | } | |
3127785a RP |
676 | } |
677 | ||
a8172eea RP |
678 | return 0; |
679 | } | |
899c4021 | 680 | else if (pc_is_mips16 (start_pc)) |
20fa0902 | 681 | { |
c1fc0935 MA |
682 | unsigned short inst; |
683 | ||
b348b9fd MA |
684 | /* On MIPS16, any one of the following is likely to be the |
685 | start of a function: | |
686 | entry | |
687 | addiu sp,-n | |
688 | daddiu sp,-n | |
689 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
c81a76b3 | 690 | inst = mips_fetch_instruction (start_pc); |
b348b9fd MA |
691 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
692 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
693 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
694 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
695 | break; | |
696 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
697 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
698 | seen_adjsp = 1; | |
699 | else | |
700 | seen_adjsp = 0; | |
20fa0902 | 701 | } |
bd5635a1 | 702 | else if (ABOUT_TO_RETURN(start_pc)) |
20fa0902 MA |
703 | { |
704 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
bd5635a1 | 705 | break; |
20fa0902 | 706 | } |
bd5635a1 | 707 | |
bd5635a1 RP |
708 | #if 0 |
709 | /* skip nops (usually 1) 0 - is this */ | |
28444bf3 DP |
710 | while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) |
711 | start_pc += MIPS_INSTLEN; | |
bd5635a1 RP |
712 | #endif |
713 | return start_pc; | |
714 | } | |
715 | ||
c81a76b3 | 716 | /* Fetch the immediate value from a MIPS16 instruction. |
b348b9fd MA |
717 | If the previous instruction was an EXTEND, use it to extend |
718 | the upper bits of the immediate value. This is a helper function | |
719 | for mips16_heuristic_proc_desc. */ | |
720 | ||
721 | static int | |
722 | mips16_get_imm (prev_inst, inst, nbits, scale, is_signed) | |
723 | unsigned short prev_inst; /* previous instruction */ | |
724 | unsigned short inst; /* current current instruction */ | |
725 | int nbits; /* number of bits in imm field */ | |
726 | int scale; /* scale factor to be applied to imm */ | |
727 | int is_signed; /* is the imm field signed? */ | |
728 | { | |
729 | int offset; | |
730 | ||
731 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
732 | { | |
7d9e8fac | 733 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); |
b348b9fd MA |
734 | if (offset & 0x8000) /* check for negative extend */ |
735 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
736 | return offset | (inst & 0x1f); | |
737 | } | |
738 | else | |
739 | { | |
740 | int max_imm = 1 << nbits; | |
741 | int mask = max_imm - 1; | |
742 | int sign_bit = max_imm >> 1; | |
743 | ||
744 | offset = inst & mask; | |
745 | if (is_signed && (offset & sign_bit)) | |
746 | offset = 0 - (max_imm - offset); | |
747 | return offset * scale; | |
748 | } | |
749 | } | |
750 | ||
751 | ||
752 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
753 | stream from start_pc to limit_pc. */ | |
754 | ||
755 | static void | |
756 | mips16_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp) | |
bd5635a1 | 757 | CORE_ADDR start_pc, limit_pc; |
9f9f94aa | 758 | struct frame_info *next_frame; |
b348b9fd | 759 | CORE_ADDR sp; |
bd5635a1 | 760 | { |
b348b9fd MA |
761 | CORE_ADDR cur_pc; |
762 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
763 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
764 | unsigned inst = 0; /* current instruction */ | |
bd5635a1 | 765 | |
b348b9fd | 766 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; |
34df79fc | 767 | |
b348b9fd MA |
768 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) |
769 | { | |
c81a76b3 | 770 | int reg, offset; |
b348b9fd MA |
771 | |
772 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
773 | the immediate offset extension from it in mips16_get_imm. */ | |
774 | prev_inst = inst; | |
775 | ||
c81a76b3 MA |
776 | /* Fetch and decode the instruction. */ |
777 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
b348b9fd MA |
778 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
779 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
780 | { | |
781 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
782 | if (offset < 0) /* negative stack adjustment? */ | |
783 | PROC_FRAME_OFFSET(&temp_proc_desc) -= offset; | |
784 | else | |
785 | /* Exit loop if a positive stack adjustment is found, which | |
786 | usually means that the stack cleanup code in the function | |
787 | epilogue is reached. */ | |
788 | break; | |
789 | } | |
790 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
791 | { | |
792 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
793 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
794 | PROC_REG_MASK(&temp_proc_desc) |= (1 << reg); | |
795 | temp_saved_regs.regs[reg] = sp + offset; | |
796 | } | |
797 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
798 | { | |
799 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
800 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
801 | PROC_REG_MASK(&temp_proc_desc) |= (1 << reg); | |
802 | temp_saved_regs.regs[reg] = sp + offset; | |
803 | } | |
804 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
805 | { | |
806 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
807 | PROC_REG_MASK(&temp_proc_desc) |= (1 << 31); | |
808 | temp_saved_regs.regs[31] = sp + offset; | |
97e091b2 | 809 | } |
b348b9fd MA |
810 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
811 | { | |
812 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
813 | PROC_REG_MASK(&temp_proc_desc) |= (1 << 31); | |
814 | temp_saved_regs.regs[31] = sp + offset; | |
bd5635a1 | 815 | } |
b348b9fd MA |
816 | else if (inst == 0x673d) /* move $s1, $sp */ |
817 | { | |
818 | frame_addr = read_next_frame_reg(next_frame, 30); | |
819 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
97e091b2 | 820 | } |
32dab603 MA |
821 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ |
822 | { | |
823 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
824 | frame_addr = sp + offset; | |
825 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
826 | } | |
b348b9fd MA |
827 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ |
828 | { | |
829 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
830 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
831 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
832 | temp_saved_regs.regs[reg] = frame_addr + offset; | |
833 | } | |
834 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
835 | { | |
836 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
837 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
838 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
839 | temp_saved_regs.regs[reg] = frame_addr + offset; | |
840 | } | |
841 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
842 | { | |
843 | int areg_count = (inst >> 8) & 7; | |
844 | int sreg_count = (inst >> 6) & 3; | |
845 | ||
846 | /* The entry instruction always subtracts 32 from the SP. */ | |
847 | PROC_FRAME_OFFSET(&temp_proc_desc) += 32; | |
848 | ||
849 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
c81a76b3 | 850 | for (reg = 4, offset = 32; reg < areg_count+4; reg++) |
b348b9fd MA |
851 | { |
852 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
853 | temp_saved_regs.regs[reg] = sp + offset; | |
c81a76b3 | 854 | offset -= MIPS_REGSIZE; |
b348b9fd MA |
855 | } |
856 | ||
857 | /* Check if the ra register was pushed on the stack. */ | |
858 | offset = 28; | |
859 | if (inst & 0x20) | |
860 | { | |
861 | PROC_REG_MASK(&temp_proc_desc) |= 1 << 31; | |
862 | temp_saved_regs.regs[31] = sp + offset; | |
c81a76b3 | 863 | offset -= MIPS_REGSIZE; |
b348b9fd MA |
864 | } |
865 | ||
866 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c81a76b3 | 867 | for (reg = 16; reg < sreg_count+16; reg++) |
b348b9fd MA |
868 | { |
869 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
870 | temp_saved_regs.regs[reg] = sp + offset; | |
c81a76b3 | 871 | offset -= MIPS_REGSIZE; |
b348b9fd MA |
872 | } |
873 | } | |
7d9e8fac MA |
874 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
875 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ | |
b348b9fd MA |
876 | } |
877 | } | |
878 | ||
879 | static void | |
880 | mips32_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp) | |
881 | CORE_ADDR start_pc, limit_pc; | |
882 | struct frame_info *next_frame; | |
883 | CORE_ADDR sp; | |
884 | { | |
885 | CORE_ADDR cur_pc; | |
886 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
887 | restart: | |
888 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; | |
889 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
890 | { | |
b348b9fd | 891 | unsigned long inst, high_word, low_word; |
c81a76b3 | 892 | int reg; |
b348b9fd MA |
893 | |
894 | /* Fetch the instruction. */ | |
c81a76b3 | 895 | inst = (unsigned long) mips_fetch_instruction (cur_pc); |
b348b9fd MA |
896 | |
897 | /* Save some code by pre-extracting some useful fields. */ | |
898 | high_word = (inst >> 16) & 0xffff; | |
899 | low_word = inst & 0xffff; | |
900 | reg = high_word & 0x1f; | |
901 | ||
902 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ | |
903 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
904 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
905 | { | |
906 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
907 | PROC_FRAME_OFFSET(&temp_proc_desc) += 0x10000 - low_word; | |
908 | else | |
909 | /* Exit loop if a positive stack adjustment is found, which | |
910 | usually means that the stack cleanup code in the function | |
911 | epilogue is reached. */ | |
912 | break; | |
913 | } | |
914 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
915 | { | |
916 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
917 | temp_saved_regs.regs[reg] = sp + low_word; | |
918 | } | |
919 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
920 | { | |
921 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
922 | but the register size used is only 32 bits. Make the address | |
923 | for the saved register point to the lower 32 bits. */ | |
924 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
925 | temp_saved_regs.regs[reg] = sp + low_word + 8 - MIPS_REGSIZE; | |
926 | } | |
927 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
928 | { | |
929 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
32dab603 | 930 | if ((long)low_word != PROC_FRAME_OFFSET(&temp_proc_desc)) |
b348b9fd MA |
931 | frame_addr = sp + low_word; |
932 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
933 | { | |
934 | unsigned alloca_adjust; | |
935 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
936 | frame_addr = read_next_frame_reg(next_frame, 30); | |
937 | alloca_adjust = (unsigned)(frame_addr - (sp + low_word)); | |
938 | if (alloca_adjust > 0) | |
939 | { | |
940 | /* FP > SP + frame_size. This may be because | |
941 | * of an alloca or somethings similar. | |
942 | * Fix sp to "pre-alloca" value, and try again. | |
943 | */ | |
944 | sp += alloca_adjust; | |
945 | goto restart; | |
bd5635a1 RP |
946 | } |
947 | } | |
948 | } | |
b348b9fd MA |
949 | /* move $30,$sp. With different versions of gas this will be either |
950 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
951 | Accept any one of these. */ | |
952 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
953 | { | |
954 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
955 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
956 | { | |
957 | unsigned alloca_adjust; | |
958 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
959 | frame_addr = read_next_frame_reg(next_frame, 30); | |
960 | alloca_adjust = (unsigned)(frame_addr - sp); | |
961 | if (alloca_adjust > 0) | |
962 | { | |
963 | /* FP > SP + frame_size. This may be because | |
964 | * of an alloca or somethings similar. | |
965 | * Fix sp to "pre-alloca" value, and try again. | |
966 | */ | |
967 | sp += alloca_adjust; | |
968 | goto restart; | |
97e091b2 MA |
969 | } |
970 | } | |
971 | } | |
b348b9fd MA |
972 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
973 | { | |
974 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
975 | temp_saved_regs.regs[reg] = frame_addr + low_word; | |
bd5635a1 RP |
976 | } |
977 | } | |
b348b9fd MA |
978 | } |
979 | ||
980 | static mips_extra_func_info_t | |
981 | heuristic_proc_desc(start_pc, limit_pc, next_frame) | |
982 | CORE_ADDR start_pc, limit_pc; | |
983 | struct frame_info *next_frame; | |
984 | { | |
985 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
986 | ||
987 | if (start_pc == 0) return NULL; | |
988 | memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); | |
989 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); | |
990 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; | |
991 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
992 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
993 | ||
994 | if (start_pc + 200 < limit_pc) | |
995 | limit_pc = start_pc + 200; | |
899c4021 | 996 | if (pc_is_mips16 (start_pc)) |
b348b9fd MA |
997 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); |
998 | else | |
999 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1000 | return &temp_proc_desc; | |
bd5635a1 RP |
1001 | } |
1002 | ||
0f552c5f | 1003 | static mips_extra_func_info_t |
c1fc0935 | 1004 | non_heuristic_proc_desc (pc, addrptr) |
9f9f94aa | 1005 | CORE_ADDR pc; |
c1fc0935 | 1006 | CORE_ADDR *addrptr; |
bd5635a1 | 1007 | { |
c1fc0935 | 1008 | CORE_ADDR startaddr; |
bd5635a1 | 1009 | mips_extra_func_info_t proc_desc; |
0f552c5f | 1010 | struct block *b = block_for_pc(pc); |
48be4c35 | 1011 | struct symbol *sym; |
48be4c35 JK |
1012 | |
1013 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
c1fc0935 MA |
1014 | if (addrptr) |
1015 | *addrptr = startaddr; | |
97e091b2 | 1016 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) |
48be4c35 JK |
1017 | sym = NULL; |
1018 | else | |
1019 | { | |
1020 | if (startaddr > BLOCK_START (b)) | |
1021 | /* This is the "pathological" case referred to in a comment in | |
1022 | print_frame_info. It might be better to move this check into | |
1023 | symbol reading. */ | |
1024 | sym = NULL; | |
1025 | else | |
c1fc0935 | 1026 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); |
48be4c35 | 1027 | } |
0f552c5f | 1028 | |
e4dbd248 PS |
1029 | /* If we never found a PDR for this function in symbol reading, then |
1030 | examine prologues to find the information. */ | |
0f552c5f | 1031 | if (sym) |
bd5635a1 | 1032 | { |
c1fc0935 MA |
1033 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
1034 | if (PROC_FRAME_REG (proc_desc) == -1) | |
1035 | return NULL; | |
1036 | else | |
1037 | return proc_desc; | |
1038 | } | |
1039 | else | |
1040 | return NULL; | |
1041 | } | |
1042 | ||
1043 | ||
1044 | static mips_extra_func_info_t | |
1045 | find_proc_desc (pc, next_frame) | |
1046 | CORE_ADDR pc; | |
1047 | struct frame_info *next_frame; | |
1048 | { | |
1049 | mips_extra_func_info_t proc_desc; | |
1050 | CORE_ADDR startaddr; | |
1051 | ||
1052 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1053 | ||
1054 | if (proc_desc) | |
1055 | { | |
1056 | /* IF this is the topmost frame AND | |
1057 | * (this proc does not have debugging information OR | |
1058 | * the PC is in the procedure prologue) | |
1059 | * THEN create a "heuristic" proc_desc (by analyzing | |
1060 | * the actual code) to replace the "official" proc_desc. | |
1061 | */ | |
1062 | if (next_frame == NULL) | |
1063 | { | |
1064 | struct symtab_and_line val; | |
1065 | struct symbol *proc_symbol = | |
1066 | PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); | |
1067 | ||
1068 | if (proc_symbol) | |
1069 | { | |
1070 | val = find_pc_line (BLOCK_START | |
1071 | (SYMBOL_BLOCK_VALUE(proc_symbol)), | |
1072 | 0); | |
1073 | val.pc = val.end ? val.end : pc; | |
bd5635a1 | 1074 | } |
c1fc0935 MA |
1075 | if (!proc_symbol || pc < val.pc) |
1076 | { | |
1077 | mips_extra_func_info_t found_heuristic = | |
1078 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), | |
1079 | pc, next_frame); | |
1080 | if (found_heuristic) | |
1081 | proc_desc = found_heuristic; | |
bd5635a1 RP |
1082 | } |
1083 | } | |
1084 | } | |
1085 | else | |
1086 | { | |
0f552c5f JG |
1087 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
1088 | by procedure call dummys. However, the procedures being called ought | |
1089 | to have their own proc_descs, and even if they don't, | |
1090 | heuristic_proc_desc knows how to create them! */ | |
1091 | ||
bd5635a1 | 1092 | register struct linked_proc_info *link; |
9f9f94aa | 1093 | |
bd5635a1 | 1094 | for (link = linked_proc_desc_table; link; link = link->next) |
9f9f94aa SS |
1095 | if (PROC_LOW_ADDR(&link->info) <= pc |
1096 | && PROC_HIGH_ADDR(&link->info) > pc) | |
1097 | return &link->info; | |
23d35572 | 1098 | |
48be4c35 JK |
1099 | if (startaddr == 0) |
1100 | startaddr = heuristic_proc_start (pc); | |
1101 | ||
bd5635a1 | 1102 | proc_desc = |
48be4c35 | 1103 | heuristic_proc_desc (startaddr, pc, next_frame); |
bd5635a1 RP |
1104 | } |
1105 | return proc_desc; | |
1106 | } | |
1107 | ||
96431497 MA |
1108 | static CORE_ADDR |
1109 | get_frame_pointer(frame, proc_desc) | |
1110 | struct frame_info *frame; | |
1111 | mips_extra_func_info_t proc_desc; | |
1112 | { | |
1113 | return ADDR_BITS_REMOVE (read_next_frame_reg (frame, | |
1114 | PROC_FRAME_REG(proc_desc)) + PROC_FRAME_OFFSET(proc_desc)); | |
1115 | } | |
1116 | ||
bd5635a1 RP |
1117 | mips_extra_func_info_t cached_proc_desc; |
1118 | ||
9f9f94aa | 1119 | CORE_ADDR |
0f552c5f | 1120 | mips_frame_chain(frame) |
9f9f94aa | 1121 | struct frame_info *frame; |
bd5635a1 | 1122 | { |
f781fe93 MA |
1123 | mips_extra_func_info_t proc_desc; |
1124 | CORE_ADDR tmp; | |
1125 | CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); | |
1126 | ||
1127 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
1128 | return 0; | |
1129 | ||
1130 | /* Check if the PC is inside a call stub. If it is, fetch the | |
1131 | PC of the caller of that stub. */ | |
1132 | if ((tmp = mips_skip_stub (saved_pc)) != 0) | |
1133 | saved_pc = tmp; | |
1134 | ||
1135 | /* Look up the procedure descriptor for this PC. */ | |
1136 | proc_desc = find_proc_desc(saved_pc, frame); | |
1137 | if (!proc_desc) | |
1138 | return 0; | |
1139 | ||
1140 | cached_proc_desc = proc_desc; | |
1141 | ||
1142 | /* If no frame pointer and frame size is zero, we must be at end | |
1143 | of stack (or otherwise hosed). If we don't check frame size, | |
1144 | we loop forever if we see a zero size frame. */ | |
1145 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
1146 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
1147 | /* The previous frame from a sigtramp frame might be frameless | |
1148 | and have frame size zero. */ | |
1149 | && !frame->signal_handler_caller) | |
1150 | return 0; | |
1151 | else | |
1152 | return get_frame_pointer (frame, proc_desc); | |
bd5635a1 RP |
1153 | } |
1154 | ||
1155 | void | |
1156 | init_extra_frame_info(fci) | |
1157 | struct frame_info *fci; | |
1158 | { | |
96431497 MA |
1159 | int regnum; |
1160 | ||
bd5635a1 | 1161 | /* Use proc_desc calculated in frame_chain */ |
ee5fb959 JK |
1162 | mips_extra_func_info_t proc_desc = |
1163 | fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); | |
0f552c5f | 1164 | |
70126bf9 | 1165 | fci->saved_regs = NULL; |
bd5635a1 | 1166 | fci->proc_desc = |
ee5fb959 | 1167 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
bd5635a1 RP |
1168 | if (proc_desc) |
1169 | { | |
c2a0f1cb | 1170 | /* Fixup frame-pointer - only needed for top frame */ |
5efd597b PS |
1171 | /* This may not be quite right, if proc has a real frame register. |
1172 | Get the value of the frame relative sp, procedure might have been | |
1173 | interrupted by a signal at it's very start. */ | |
70126bf9 KH |
1174 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
1175 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
1176 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
c2a0f1cb | 1177 | else |
96431497 | 1178 | fci->frame = get_frame_pointer (fci->next, proc_desc); |
bd5635a1 | 1179 | |
48be4c35 | 1180 | if (proc_desc == &temp_proc_desc) |
ee5fb959 | 1181 | { |
09af5868 PS |
1182 | char *name; |
1183 | ||
1184 | /* Do not set the saved registers for a sigtramp frame, | |
1185 | mips_find_saved_registers will do that for us. | |
1186 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
1187 | find_pc_partial_function (fci->pc, &name, | |
1188 | (CORE_ADDR *)NULL,(CORE_ADDR *)NULL); | |
1189 | if (!IN_SIGTRAMP (fci->pc, name)) | |
1190 | { | |
1191 | fci->saved_regs = (struct frame_saved_regs*) | |
1192 | obstack_alloc (&frame_cache_obstack, | |
1193 | sizeof (struct frame_saved_regs)); | |
1194 | *fci->saved_regs = temp_saved_regs; | |
1195 | fci->saved_regs->regs[PC_REGNUM] | |
1196 | = fci->saved_regs->regs[RA_REGNUM]; | |
1197 | } | |
ee5fb959 | 1198 | } |
bd5635a1 RP |
1199 | |
1200 | /* hack: if argument regs are saved, guess these contain args */ | |
96431497 MA |
1201 | fci->num_args = -1; /* assume we can't tell how many args for now */ |
1202 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) | |
1203 | { | |
1204 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) | |
1205 | { | |
1206 | fci->num_args = regnum - A0_REGNUM + 1; | |
1207 | break; | |
1208 | } | |
1209 | } | |
bd5635a1 | 1210 | } |
bd5635a1 RP |
1211 | } |
1212 | ||
a70dc898 RP |
1213 | /* MIPS stack frames are almost impenetrable. When execution stops, |
1214 | we basically have to look at symbol information for the function | |
1215 | that we stopped in, which tells us *which* register (if any) is | |
1216 | the base of the frame pointer, and what offset from that register | |
1217 | the frame itself is at. | |
1218 | ||
1219 | This presents a problem when trying to examine a stack in memory | |
1220 | (that isn't executing at the moment), using the "frame" command. We | |
1221 | don't have a PC, nor do we have any registers except SP. | |
1222 | ||
1223 | This routine takes two arguments, SP and PC, and tries to make the | |
1224 | cached frames look as if these two arguments defined a frame on the | |
1225 | cache. This allows the rest of info frame to extract the important | |
1226 | arguments without difficulty. */ | |
1227 | ||
9f9f94aa | 1228 | struct frame_info * |
c2a0f1cb ILT |
1229 | setup_arbitrary_frame (argc, argv) |
1230 | int argc; | |
9f9f94aa | 1231 | CORE_ADDR *argv; |
a70dc898 | 1232 | { |
c2a0f1cb ILT |
1233 | if (argc != 2) |
1234 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
1235 | ||
1236 | return create_new_frame (argv[0], argv[1]); | |
a70dc898 RP |
1237 | } |
1238 | ||
0f552c5f JG |
1239 | CORE_ADDR |
1240 | mips_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
97e091b2 MA |
1241 | int nargs; |
1242 | value_ptr *args; | |
1243 | CORE_ADDR sp; | |
1244 | int struct_return; | |
1245 | CORE_ADDR struct_addr; | |
bd5635a1 | 1246 | { |
97e091b2 MA |
1247 | int argreg; |
1248 | int float_argreg; | |
1249 | int argnum; | |
1250 | int len = 0; | |
781a59b2 | 1251 | int stack_offset = 0; |
97e091b2 MA |
1252 | |
1253 | /* Macros to round N up or down to the next A boundary; A must be | |
1254 | a power of two. */ | |
1255 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
1256 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
28444bf3 DP |
1257 | |
1258 | /* First ensure that the stack and structure return address (if any) | |
97e091b2 MA |
1259 | are properly aligned. The stack has to be 64-bit aligned even |
1260 | on 32-bit machines, because doubles must be 64-bit aligned. */ | |
1261 | sp = ROUND_DOWN (sp, 8); | |
1262 | struct_addr = ROUND_DOWN (struct_addr, MIPS_REGSIZE); | |
28444bf3 | 1263 | |
97e091b2 MA |
1264 | /* Now make space on the stack for the args. We allocate more |
1265 | than necessary for EABI, because the first few arguments are | |
1266 | passed in registers, but that's OK. */ | |
1267 | for (argnum = 0; argnum < nargs; argnum++) | |
1268 | len += ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args[argnum])), MIPS_REGSIZE); | |
61d2d19a | 1269 | sp -= ROUND_UP (len, 8); |
97e091b2 MA |
1270 | |
1271 | /* Initialize the integer and float register pointers. */ | |
1272 | argreg = A0_REGNUM; | |
1273 | float_argreg = FPA0_REGNUM; | |
1274 | ||
1275 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
5efd597b | 1276 | if (struct_return) |
97e091b2 MA |
1277 | write_register (argreg++, struct_addr); |
1278 | ||
97e091b2 MA |
1279 | /* Now load as many as possible of the first arguments into |
1280 | registers, and push the rest onto the stack. Loop thru args | |
1281 | from first to last. */ | |
1282 | for (argnum = 0; argnum < nargs; argnum++) | |
5efd597b | 1283 | { |
97e091b2 MA |
1284 | char *val; |
1285 | char valbuf[REGISTER_RAW_SIZE(A0_REGNUM)]; | |
1286 | value_ptr arg = args[argnum]; | |
1287 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
1288 | int len = TYPE_LENGTH (arg_type); | |
1289 | enum type_code typecode = TYPE_CODE (arg_type); | |
1290 | ||
61d2d19a PS |
1291 | /* The EABI passes structures that do not fit in a register by |
1292 | reference. In all other cases, pass the structure by value. */ | |
781a59b2 MS |
1293 | if (MIPS_EABI && len > MIPS_REGSIZE && |
1294 | (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
97e091b2 MA |
1295 | { |
1296 | store_address (valbuf, MIPS_REGSIZE, VALUE_ADDRESS (arg)); | |
08d8f995 | 1297 | typecode = TYPE_CODE_PTR; |
97e091b2 MA |
1298 | len = MIPS_REGSIZE; |
1299 | val = valbuf; | |
1300 | } | |
1301 | else | |
1302 | val = (char *)VALUE_CONTENTS (arg); | |
1303 | ||
1304 | /* 32-bit ABIs always start floating point arguments in an | |
1305 | even-numbered floating point register. */ | |
1306 | if (!GDB_TARGET_IS_MIPS64 && typecode == TYPE_CODE_FLT | |
1307 | && (float_argreg & 1)) | |
1308 | float_argreg++; | |
1309 | ||
1310 | /* Floating point arguments passed in registers have to be | |
1311 | treated specially. On 32-bit architectures, doubles | |
1312 | are passed in register pairs; the even register gets | |
c81a76b3 MA |
1313 | the low word, and the odd register gets the high word. |
1314 | On non-EABI processors, the first two floating point arguments are | |
1315 | also copied to general registers, because MIPS16 functions | |
1316 | don't use float registers for arguments. This duplication of | |
1317 | arguments in general registers can't hurt non-MIPS16 functions | |
1318 | because those registers are normally skipped. */ | |
97e091b2 MA |
1319 | if (typecode == TYPE_CODE_FLT |
1320 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM | |
1321 | && mips_fpu != MIPS_FPU_NONE) | |
1322 | { | |
1323 | if (!GDB_TARGET_IS_MIPS64 && len == 8) | |
1324 | { | |
1325 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; | |
1326 | unsigned long regval; | |
1327 | ||
c81a76b3 | 1328 | /* Write the low word of the double to the even register(s). */ |
97e091b2 | 1329 | regval = extract_unsigned_integer (val+low_offset, 4); |
c81a76b3 MA |
1330 | write_register (float_argreg++, regval); |
1331 | if (!MIPS_EABI) | |
1332 | write_register (argreg+1, regval); | |
1333 | ||
1334 | /* Write the high word of the double to the odd register(s). */ | |
97e091b2 | 1335 | regval = extract_unsigned_integer (val+4-low_offset, 4); |
c81a76b3 MA |
1336 | write_register (float_argreg++, regval); |
1337 | if (!MIPS_EABI) | |
1338 | { | |
1339 | write_register (argreg, regval); | |
1340 | argreg += 2; | |
1341 | } | |
97e091b2 MA |
1342 | |
1343 | } | |
1344 | else | |
1345 | { | |
c81a76b3 MA |
1346 | /* This is a floating point value that fits entirely |
1347 | in a single register. */ | |
97e091b2 MA |
1348 | CORE_ADDR regval = extract_address (val, len); |
1349 | write_register (float_argreg++, regval); | |
c81a76b3 MA |
1350 | if (!MIPS_EABI) |
1351 | { | |
1352 | write_register (argreg, regval); | |
1353 | argreg += GDB_TARGET_IS_MIPS64 ? 1 : 2; | |
1354 | } | |
97e091b2 | 1355 | } |
97e091b2 MA |
1356 | } |
1357 | else | |
1358 | { | |
1359 | /* Copy the argument to general registers or the stack in | |
1360 | register-sized pieces. Large arguments are split between | |
1361 | registers and stack. */ | |
781a59b2 MS |
1362 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE |
1363 | are treated specially: Irix cc passes them in registers | |
1364 | where gcc sometimes puts them on the stack. For maximum | |
1365 | compatibility, we will put them in both places. */ | |
1366 | ||
1367 | int odd_sized_struct = ((len > MIPS_REGSIZE) && | |
1368 | (len % MIPS_REGSIZE != 0)); | |
97e091b2 MA |
1369 | while (len > 0) |
1370 | { | |
1371 | int partial_len = len < MIPS_REGSIZE ? len : MIPS_REGSIZE; | |
61d2d19a | 1372 | |
781a59b2 MS |
1373 | if (argreg > MIPS_LAST_ARG_REGNUM || odd_sized_struct) |
1374 | { | |
1375 | /* Write this portion of the argument to the stack. */ | |
1376 | int longword_offset; | |
1377 | ||
1378 | longword_offset = 0; | |
1379 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1380 | if (MIPS_REGSIZE == 8 && | |
1381 | (typecode == TYPE_CODE_INT || | |
1382 | typecode == TYPE_CODE_PTR || | |
1383 | typecode == TYPE_CODE_FLT) && len <= 4) | |
1384 | longword_offset = 4; | |
1385 | else if ((typecode == TYPE_CODE_STRUCT || | |
1386 | typecode == TYPE_CODE_UNION) && | |
1387 | TYPE_LENGTH (arg_type) < MIPS_REGSIZE) | |
1388 | longword_offset = MIPS_REGSIZE - len; | |
1389 | ||
1390 | write_memory (sp + stack_offset + longword_offset, | |
1391 | val, partial_len); | |
1392 | } | |
1393 | ||
1394 | /* Note!!! This is NOT an else clause. | |
1395 | Odd sized structs may go thru BOTH paths. */ | |
97e091b2 MA |
1396 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
1397 | { | |
61d2d19a PS |
1398 | CORE_ADDR regval = extract_address (val, partial_len); |
1399 | ||
c430260c MS |
1400 | /* A non-floating-point argument being passed in a |
1401 | general register. If a struct or union, and if | |
1402 | small enough for a single register, we have to | |
1403 | adjust the alignment. | |
158bda58 | 1404 | |
c430260c MS |
1405 | It does not seem to be necessary to do the |
1406 | same for integral types. | |
158bda58 | 1407 | |
c430260c | 1408 | Also don't do this adjustment on EABI targets. */ |
158bda58 MS |
1409 | |
1410 | if (!MIPS_EABI && | |
1411 | TYPE_LENGTH (arg_type) < MIPS_REGSIZE && | |
c430260c | 1412 | (typecode == TYPE_CODE_STRUCT || |
158bda58 MS |
1413 | typecode == TYPE_CODE_UNION)) |
1414 | regval <<= ((MIPS_REGSIZE - partial_len) * | |
1415 | TARGET_CHAR_BIT); | |
1416 | ||
97e091b2 MA |
1417 | write_register (argreg, regval); |
1418 | argreg++; | |
1419 | ||
1420 | /* If this is the old ABI, prevent subsequent floating | |
1421 | point arguments from being passed in floating point | |
1422 | registers. */ | |
1423 | if (!MIPS_EABI) | |
1424 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
1425 | } | |
97e091b2 MA |
1426 | |
1427 | len -= partial_len; | |
1428 | val += partial_len; | |
781a59b2 MS |
1429 | |
1430 | /* The offset onto the stack at which we will start | |
1431 | copying parameters (after the registers are used up) | |
1432 | begins at (4 * MIPS_REGSIZE) in the old ABI. This | |
1433 | leaves room for the "home" area for register parameters. | |
1434 | ||
1435 | In the new EABI, the 8 register parameters do not | |
1436 | have "home" stack space reserved for them, so the | |
1437 | stack offset does not get incremented until after | |
1438 | we have used up the 8 parameter registers. */ | |
1439 | if (!(MIPS_EABI && argnum < 8)) | |
1440 | stack_offset += ROUND_UP (partial_len, MIPS_REGSIZE); | |
97e091b2 MA |
1441 | } |
1442 | } | |
5efd597b | 1443 | } |
97e091b2 MA |
1444 | |
1445 | /* Set the return address register to point to the entry | |
1446 | point of the program, where a breakpoint lies in wait. */ | |
1447 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS()); | |
1448 | ||
1449 | /* Return adjusted stack pointer. */ | |
bd5635a1 RP |
1450 | return sp; |
1451 | } | |
1452 | ||
c81a76b3 | 1453 | static void |
28444bf3 DP |
1454 | mips_push_register(CORE_ADDR *sp, int regno) |
1455 | { | |
1456 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
1457 | int regsize = REGISTER_RAW_SIZE (regno); | |
1458 | ||
1459 | *sp -= regsize; | |
1460 | read_register_gen (regno, buffer); | |
1461 | write_memory (*sp, buffer, regsize); | |
1462 | } | |
1463 | ||
1464 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
e03c0cc6 | 1465 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
bd5635a1 RP |
1466 | |
1467 | void | |
1468 | mips_push_dummy_frame() | |
1469 | { | |
1470 | int ireg; | |
1471 | struct linked_proc_info *link = (struct linked_proc_info*) | |
1472 | xmalloc(sizeof(struct linked_proc_info)); | |
1473 | mips_extra_func_info_t proc_desc = &link->info; | |
96431497 | 1474 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM)); |
28444bf3 | 1475 | CORE_ADDR old_sp = sp; |
bd5635a1 RP |
1476 | link->next = linked_proc_desc_table; |
1477 | linked_proc_desc_table = link; | |
28444bf3 DP |
1478 | |
1479 | /* FIXME! are these correct ? */ | |
bd5635a1 | 1480 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
28444bf3 | 1481 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
bd5635a1 | 1482 | #define FLOAT_REG_SAVE_MASK MASK(0,19) |
e4dbd248 PS |
1483 | #define FLOAT_SINGLE_REG_SAVE_MASK \ |
1484 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
bd5635a1 RP |
1485 | /* |
1486 | * The registers we must save are all those not preserved across | |
1487 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
28444bf3 DP |
1488 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI |
1489 | * and FP Control/Status registers. | |
1490 | * | |
bd5635a1 RP |
1491 | * |
1492 | * Dummy frame layout: | |
1493 | * (high memory) | |
1494 | * Saved PC | |
1495 | * Saved MMHI, MMLO, FPC_CSR | |
1496 | * Saved R31 | |
1497 | * Saved R28 | |
1498 | * ... | |
1499 | * Saved R1 | |
1500 | * Saved D18 (i.e. F19, F18) | |
1501 | * ... | |
1502 | * Saved D0 (i.e. F1, F0) | |
f9f8c14b | 1503 | * Argument build area and stack arguments written via mips_push_arguments |
bd5635a1 RP |
1504 | * (low memory) |
1505 | */ | |
28444bf3 DP |
1506 | |
1507 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
28444bf3 DP |
1508 | PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; |
1509 | PROC_FRAME_OFFSET(proc_desc) = 0; | |
1510 | mips_push_register (&sp, PC_REGNUM); | |
1511 | mips_push_register (&sp, HI_REGNUM); | |
1512 | mips_push_register (&sp, LO_REGNUM); | |
1513 | mips_push_register (&sp, mips_fpu == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
1514 | ||
1515 | /* Save general CPU registers */ | |
bd5635a1 | 1516 | PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; |
28444bf3 | 1517 | PROC_REG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved R31) from FP */ |
bd5635a1 RP |
1518 | for (ireg = 32; --ireg >= 0; ) |
1519 | if (PROC_REG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1520 | mips_push_register (&sp, ireg); |
3fed1c4a | 1521 | |
28444bf3 DP |
1522 | /* Save floating point registers starting with high order word */ |
1523 | PROC_FREG_MASK(proc_desc) = | |
1524 | mips_fpu == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK | |
1525 | : mips_fpu == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
1526 | PROC_FREG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved D18) from FP */ | |
bd5635a1 RP |
1527 | for (ireg = 32; --ireg >= 0; ) |
1528 | if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1529 | mips_push_register (&sp, ireg + FP0_REGNUM); |
3fed1c4a | 1530 | |
f9f8c14b MA |
1531 | /* Update the frame pointer for the call dummy and the stack pointer. |
1532 | Set the procedure's starting and ending addresses to point to the | |
1533 | call dummy address at the entry point. */ | |
1534 | write_register (PUSH_FP_REGNUM, old_sp); | |
bd5635a1 | 1535 | write_register (SP_REGNUM, sp); |
97e091b2 MA |
1536 | PROC_LOW_ADDR(proc_desc) = CALL_DUMMY_ADDRESS(); |
1537 | PROC_HIGH_ADDR(proc_desc) = CALL_DUMMY_ADDRESS() + 4; | |
bd5635a1 RP |
1538 | SET_PROC_DESC_IS_DUMMY(proc_desc); |
1539 | PROC_PC_REG(proc_desc) = RA_REGNUM; | |
1540 | } | |
1541 | ||
1542 | void | |
1543 | mips_pop_frame() | |
dac4929a SG |
1544 | { |
1545 | register int regnum; | |
9f9f94aa SS |
1546 | struct frame_info *frame = get_current_frame (); |
1547 | CORE_ADDR new_sp = FRAME_FP (frame); | |
dac4929a | 1548 | |
a70dc898 | 1549 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
dac4929a SG |
1550 | |
1551 | write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); | |
70126bf9 KH |
1552 | if (frame->saved_regs == NULL) |
1553 | mips_find_saved_regs (frame); | |
61d2d19a | 1554 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
dac4929a | 1555 | { |
61d2d19a PS |
1556 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1557 | && frame->saved_regs->regs[regnum]) | |
1558 | write_register (regnum, | |
1559 | read_memory_integer (frame->saved_regs->regs[regnum], | |
1560 | MIPS_REGSIZE)); | |
dac4929a SG |
1561 | } |
1562 | write_register (SP_REGNUM, new_sp); | |
1563 | flush_cached_frames (); | |
dac4929a | 1564 | |
199b2450 | 1565 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
bd5635a1 | 1566 | { |
dac4929a SG |
1567 | struct linked_proc_info *pi_ptr, *prev_ptr; |
1568 | ||
1569 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
1570 | pi_ptr != NULL; | |
1571 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
1572 | { | |
1573 | if (&pi_ptr->info == proc_desc) | |
1574 | break; | |
1575 | } | |
1576 | ||
1577 | if (pi_ptr == NULL) | |
1578 | error ("Can't locate dummy extra frame info\n"); | |
1579 | ||
1580 | if (prev_ptr != NULL) | |
1581 | prev_ptr->next = pi_ptr->next; | |
1582 | else | |
1583 | linked_proc_desc_table = pi_ptr->next; | |
1584 | ||
1585 | free (pi_ptr); | |
1586 | ||
28444bf3 DP |
1587 | write_register (HI_REGNUM, |
1588 | read_memory_integer (new_sp - 2*MIPS_REGSIZE, MIPS_REGSIZE)); | |
1589 | write_register (LO_REGNUM, | |
1590 | read_memory_integer (new_sp - 3*MIPS_REGSIZE, MIPS_REGSIZE)); | |
e4dbd248 | 1591 | if (mips_fpu != MIPS_FPU_NONE) |
28444bf3 DP |
1592 | write_register (FCRCS_REGNUM, |
1593 | read_memory_integer (new_sp - 4*MIPS_REGSIZE, MIPS_REGSIZE)); | |
bd5635a1 | 1594 | } |
bd5635a1 RP |
1595 | } |
1596 | ||
0f552c5f | 1597 | static void |
a70dc898 | 1598 | mips_print_register (regnum, all) |
bd5635a1 RP |
1599 | int regnum, all; |
1600 | { | |
e4dbd248 | 1601 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
bd5635a1 | 1602 | |
48be4c35 JK |
1603 | /* Get the data in raw format. */ |
1604 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
1605 | { | |
1606 | printf_filtered ("%s: [Invalid]", reg_names[regnum]); | |
1607 | return; | |
1608 | } | |
1609 | ||
781a59b2 | 1610 | /* If an even floating point register, also print as double. */ |
899c4021 | 1611 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT |
e4dbd248 | 1612 | && !((regnum-FP0_REGNUM) & 1)) |
899c4021 MA |
1613 | if (REGISTER_RAW_SIZE(regnum) == 4) /* this would be silly on MIPS64 */ |
1614 | { | |
1615 | char dbuffer[2 * MAX_REGISTER_RAW_SIZE]; | |
48be4c35 | 1616 | |
899c4021 MA |
1617 | read_relative_register_raw_bytes (regnum, dbuffer); |
1618 | read_relative_register_raw_bytes (regnum+1, dbuffer+MIPS_REGSIZE); | |
1619 | REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer); | |
c81a76b3 | 1620 | |
899c4021 MA |
1621 | printf_filtered ("(d%d: ", regnum-FP0_REGNUM); |
1622 | val_print (builtin_type_double, dbuffer, 0, | |
1623 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
1624 | printf_filtered ("); "); | |
1625 | } | |
199b2450 | 1626 | fputs_filtered (reg_names[regnum], gdb_stdout); |
48be4c35 JK |
1627 | |
1628 | /* The problem with printing numeric register names (r26, etc.) is that | |
1629 | the user can't use them on input. Probably the best solution is to | |
1630 | fix it so that either the numeric or the funky (a2, etc.) names | |
1631 | are accepted on input. */ | |
28444bf3 | 1632 | if (regnum < MIPS_NUMREGS) |
48be4c35 JK |
1633 | printf_filtered ("(r%d): ", regnum); |
1634 | else | |
1635 | printf_filtered (": "); | |
bd5635a1 | 1636 | |
48be4c35 | 1637 | /* If virtual format is floating, print it that way. */ |
ac57e5ad | 1638 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
899c4021 MA |
1639 | if (REGISTER_RAW_SIZE(regnum) == 8) |
1640 | { /* show 8-byte floats as float AND double: */ | |
1641 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
1642 | ||
1643 | printf_filtered (" (float) "); | |
1644 | val_print (builtin_type_float, raw_buffer + offset, 0, | |
1645 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
1646 | printf_filtered (", (double) "); | |
1647 | val_print (builtin_type_double, raw_buffer, 0, | |
1648 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
1649 | } | |
1650 | else | |
1651 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, | |
1652 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
48be4c35 JK |
1653 | /* Else print as integer in hex. */ |
1654 | else | |
ac57e5ad SS |
1655 | print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), |
1656 | 'x', 0, gdb_stdout); | |
bd5635a1 RP |
1657 | } |
1658 | ||
899c4021 MA |
1659 | /* Replacement for generic do_registers_info. |
1660 | Print regs in pretty columns. */ | |
1661 | ||
1662 | static int | |
1663 | do_fp_register_row (regnum) | |
1664 | int regnum; | |
1665 | { /* do values for FP (float) regs */ | |
1666 | char raw_buffer[2] [REGISTER_RAW_SIZE(FP0_REGNUM)]; | |
1667 | char dbl_buffer[2 * REGISTER_RAW_SIZE(FP0_REGNUM)]; | |
1668 | /* use HI and LO to control the order of combining two flt regs */ | |
1669 | int HI = (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
1670 | int LO = (TARGET_BYTE_ORDER != BIG_ENDIAN); | |
1671 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ | |
1672 | int inv1, inv2, inv3; | |
1673 | ||
1674 | /* Get the data in raw format. */ | |
1675 | if (read_relative_register_raw_bytes (regnum, raw_buffer[HI])) | |
1676 | error ("can't read register %d (%s)", regnum, reg_names[regnum]); | |
1677 | if (REGISTER_RAW_SIZE(regnum) == 4) | |
1678 | { | |
1679 | /* 4-byte registers: we can fit two registers per row. */ | |
1680 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
1681 | if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO])) | |
1682 | error ("can't read register %d (%s)", | |
1683 | regnum + 1, reg_names[regnum + 1]); | |
1684 | ||
1685 | /* copy the two floats into one double, and unpack both */ | |
1686 | memcpy (dbl_buffer, raw_buffer, sizeof(dbl_buffer)); | |
1687 | flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1); | |
1688 | flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2); | |
1689 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); | |
1690 | ||
1691 | printf_filtered (inv1 ? " %-5s: <invalid float>" : | |
1692 | " %-5s%-17.9g", reg_names[regnum], flt1); | |
1693 | printf_filtered (inv2 ? " %-5s: <invalid float>" : | |
1694 | " %-5s%-17.9g", reg_names[regnum + 1], flt2); | |
1695 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : | |
1696 | " dbl: %-24.17g\n", doub); | |
1697 | /* may want to do hex display here (future enhancement) */ | |
1698 | regnum +=2; | |
1699 | } | |
1700 | else | |
1701 | { /* eight byte registers: print each one as float AND as double. */ | |
1702 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
1703 | ||
1704 | memcpy (dbl_buffer, raw_buffer[HI], sizeof(dbl_buffer)); | |
1705 | flt1 = unpack_double (builtin_type_float, | |
1706 | &raw_buffer[HI][offset], &inv1); | |
1707 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); | |
1708 | ||
1709 | printf_filtered (inv1 ? " %-5s: <invalid float>" : | |
1710 | " %-5s flt: %-17.9g", reg_names[regnum], flt1); | |
1711 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : | |
1712 | " dbl: %-24.17g\n", doub); | |
1713 | /* may want to do hex display here (future enhancement) */ | |
1714 | regnum++; | |
1715 | } | |
1716 | return regnum; | |
1717 | } | |
1718 | ||
1719 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
1720 | ||
1721 | static int | |
1722 | do_gp_register_row (regnum) | |
1723 | int regnum; | |
1724 | { /* do values for GP (int) regs */ | |
1725 | char raw_buffer[REGISTER_RAW_SIZE(0)]; | |
1726 | int ncols = MIPS_REGSIZE == 8 ? 4 : 8; /* display cols per row */ | |
1727 | int col, byte, start_regnum = regnum; | |
1728 | ||
1729 | /* For GP registers, we print a separate row of names above the vals */ | |
1730 | printf_filtered (" "); | |
1731 | for (col = 0; col < ncols && regnum < NUM_REGS; regnum++) | |
1732 | { | |
1733 | if (*reg_names[regnum] == '\0') | |
1734 | continue; /* unused register */ | |
1735 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
1736 | break; /* end the row: reached FP register */ | |
1737 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
1738 | reg_names[regnum]); | |
1739 | col++; | |
1740 | } | |
1741 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", | |
1742 | start_regnum); /* print the R0 to R31 names */ | |
1743 | ||
1744 | regnum = start_regnum; /* go back to start of row */ | |
1745 | /* now print the values in hex, 4 or 8 to the row */ | |
1746 | for (col = 0; col < ncols && regnum < NUM_REGS; regnum++) | |
1747 | { | |
1748 | if (*reg_names[regnum] == '\0') | |
1749 | continue; /* unused register */ | |
1750 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
1751 | break; /* end row: reached FP register */ | |
1752 | /* OK: get the data in raw format. */ | |
1753 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
1754 | error ("can't read register %d (%s)", regnum, reg_names[regnum]); | |
1755 | /* Now print the register value in hex, endian order. */ | |
1756 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1757 | for (byte = 0; byte < REGISTER_RAW_SIZE (regnum); byte++) | |
1758 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); | |
1759 | else | |
1760 | for (byte = REGISTER_RAW_SIZE (regnum) - 1; byte >= 0; byte--) | |
1761 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); | |
1762 | printf_filtered (" "); | |
1763 | col++; | |
1764 | } | |
1765 | if (col > 0) /* ie. if we actually printed anything... */ | |
1766 | printf_filtered ("\n"); | |
1767 | ||
1768 | return regnum; | |
1769 | } | |
1770 | ||
1771 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
9f9f94aa | 1772 | |
0f552c5f | 1773 | void |
361bf6ee | 1774 | mips_do_registers_info (regnum, fpregs) |
bd5635a1 | 1775 | int regnum; |
361bf6ee | 1776 | int fpregs; |
bd5635a1 | 1777 | { |
899c4021 | 1778 | if (regnum != -1) /* do one specified register */ |
9f9f94aa SS |
1779 | { |
1780 | if (*(reg_names[regnum]) == '\0') | |
1781 | error ("Not a valid register for the current processor type"); | |
1782 | ||
bd5635a1 RP |
1783 | mips_print_register (regnum, 0); |
1784 | printf_filtered ("\n"); | |
9f9f94aa | 1785 | } |
899c4021 | 1786 | else /* do all (or most) registers */ |
9f9f94aa | 1787 | { |
899c4021 MA |
1788 | regnum = 0; |
1789 | while (regnum < NUM_REGS) | |
1790 | if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
1791 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
1792 | regnum = do_fp_register_row (regnum); /* FP regs */ | |
1793 | else | |
1794 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
1795 | else | |
1796 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ | |
9f9f94aa | 1797 | } |
bd5635a1 | 1798 | } |
9f9f94aa | 1799 | |
bd5635a1 RP |
1800 | /* Return number of args passed to a frame. described by FIP. |
1801 | Can return -1, meaning no way to tell. */ | |
1802 | ||
0f552c5f | 1803 | int |
9f9f94aa SS |
1804 | mips_frame_num_args (frame) |
1805 | struct frame_info *frame; | |
bd5635a1 | 1806 | { |
9f9f94aa SS |
1807 | #if 0 /* FIXME Use or lose this! */ |
1808 | struct chain_info_t *p; | |
bd5635a1 | 1809 | |
9f9f94aa SS |
1810 | p = mips_find_cached_frame (FRAME_FP (frame)); |
1811 | if (p->valid) | |
1812 | return p->the_info.numargs; | |
bd5635a1 | 1813 | #endif |
9f9f94aa | 1814 | return -1; |
bd5635a1 | 1815 | } |
96431497 | 1816 | |
427fec5d | 1817 | /* Is this a branch with a delay slot? */ |
9f9f94aa | 1818 | |
b5aff268 JK |
1819 | static int is_delayed PARAMS ((unsigned long)); |
1820 | ||
ee5fb959 JK |
1821 | static int |
1822 | is_delayed (insn) | |
1823 | unsigned long insn; | |
1824 | { | |
1825 | int i; | |
1826 | for (i = 0; i < NUMOPCODES; ++i) | |
1827 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
1828 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
1829 | break; | |
427fec5d JK |
1830 | return (i < NUMOPCODES |
1831 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
1832 | | INSN_COND_BRANCH_DELAY | |
1833 | | INSN_COND_BRANCH_LIKELY))); | |
ee5fb959 | 1834 | } |
b5aff268 JK |
1835 | |
1836 | int | |
1837 | mips_step_skips_delay (pc) | |
1838 | CORE_ADDR pc; | |
1839 | { | |
96431497 | 1840 | char buf[MIPS_INSTLEN]; |
b5aff268 | 1841 | |
f9f8c14b | 1842 | /* There is no branch delay slot on MIPS16. */ |
899c4021 | 1843 | if (pc_is_mips16 (pc)) |
f9f8c14b MA |
1844 | return 0; |
1845 | ||
96431497 | 1846 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) |
b5aff268 JK |
1847 | /* If error reading memory, guess that it is not a delayed branch. */ |
1848 | return 0; | |
96431497 | 1849 | return is_delayed ((unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN)); |
b5aff268 | 1850 | } |
ee5fb959 | 1851 | |
bd5635a1 | 1852 | |
20fa0902 MA |
1853 | /* Skip the PC past function prologue instructions (32-bit version). |
1854 | This is a helper function for mips_skip_prologue. */ | |
1855 | ||
1856 | static CORE_ADDR | |
1857 | mips32_skip_prologue (pc, lenient) | |
1858 | CORE_ADDR pc; /* starting PC to search from */ | |
ee5fb959 | 1859 | int lenient; |
bd5635a1 | 1860 | { |
28444bf3 | 1861 | t_inst inst; |
20fa0902 | 1862 | CORE_ADDR end_pc; |
0b0d6c3f | 1863 | int seen_sp_adjust = 0; |
ac57e5ad | 1864 | int load_immediate_bytes = 0; |
bd5635a1 | 1865 | |
e157305c PS |
1866 | /* Skip the typical prologue instructions. These are the stack adjustment |
1867 | instruction and the instructions that save registers on the stack | |
1868 | or in the gcc frame. */ | |
20fa0902 | 1869 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) |
ee5fb959 | 1870 | { |
b348b9fd | 1871 | unsigned long high_word; |
ee5fb959 | 1872 | |
c81a76b3 | 1873 | inst = mips_fetch_instruction (pc); |
b348b9fd | 1874 | high_word = (inst >> 16) & 0xffff; |
ee5fb959 | 1875 | |
002a422b | 1876 | #if 0 |
ee5fb959 JK |
1877 | if (lenient && is_delayed (inst)) |
1878 | continue; | |
002a422b | 1879 | #endif |
ee5fb959 | 1880 | |
b348b9fd MA |
1881 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
1882 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
0b0d6c3f | 1883 | seen_sp_adjust = 1; |
ac57e5ad SS |
1884 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
1885 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
1886 | seen_sp_adjust = 1; | |
97e091b2 MA |
1887 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ |
1888 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
1889 | && (inst & 0x001F0000)) /* reg != $zero */ | |
1890 | continue; | |
1891 | ||
e157305c PS |
1892 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ |
1893 | continue; | |
1894 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
1895 | /* sx reg,n($s8) */ | |
1896 | continue; /* reg != $zero */ | |
1d9489c1 JK |
1897 | |
1898 | /* move $s8,$sp. With different versions of gas this will be either | |
20fa0902 MA |
1899 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. |
1900 | Accept any one of these. */ | |
1901 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
0b0d6c3f | 1902 | continue; |
1d9489c1 | 1903 | |
1b71de8e PS |
1904 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
1905 | continue; | |
b348b9fd | 1906 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
e03c0cc6 | 1907 | continue; |
b348b9fd | 1908 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ |
e03c0cc6 ILT |
1909 | continue; |
1910 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1911 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
1912 | continue; | |
ac57e5ad SS |
1913 | /* The following instructions load $at or $t0 with an immediate |
1914 | value in preparation for a stack adjustment via | |
1915 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
1916 | a local variable, so we accept them only before a stack adjustment | |
1917 | instruction was seen. */ | |
1918 | else if (!seen_sp_adjust) | |
1919 | { | |
b348b9fd MA |
1920 | if (high_word == 0x3c01 || /* lui $at,n */ |
1921 | high_word == 0x3c08) /* lui $t0,n */ | |
ac57e5ad | 1922 | { |
28444bf3 | 1923 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1924 | continue; |
1925 | } | |
b348b9fd MA |
1926 | else if (high_word == 0x3421 || /* ori $at,$at,n */ |
1927 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
1928 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
1929 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
ac57e5ad | 1930 | { |
28444bf3 | 1931 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1932 | continue; |
1933 | } | |
1934 | else | |
1935 | break; | |
1936 | } | |
0b0d6c3f | 1937 | else |
ac57e5ad | 1938 | break; |
d747e0af | 1939 | } |
e157305c | 1940 | |
ac57e5ad SS |
1941 | /* In a frameless function, we might have incorrectly |
1942 | skipped some load immediate instructions. Undo the skipping | |
1943 | if the load immediate was not followed by a stack adjustment. */ | |
1944 | if (load_immediate_bytes && !seen_sp_adjust) | |
20fa0902 MA |
1945 | pc -= load_immediate_bytes; |
1946 | return pc; | |
1947 | } | |
1948 | ||
1949 | /* Skip the PC past function prologue instructions (16-bit version). | |
1950 | This is a helper function for mips_skip_prologue. */ | |
1951 | ||
1952 | static CORE_ADDR | |
1953 | mips16_skip_prologue (pc, lenient) | |
1954 | CORE_ADDR pc; /* starting PC to search from */ | |
1955 | int lenient; | |
1956 | { | |
1957 | CORE_ADDR end_pc; | |
c81a76b3 MA |
1958 | int extend_bytes = 0; |
1959 | int prev_extend_bytes; | |
20fa0902 MA |
1960 | |
1961 | /* Table of instructions likely to be found in a function prologue. */ | |
1962 | static struct | |
1963 | { | |
1964 | unsigned short inst; | |
1965 | unsigned short mask; | |
1966 | } table[] = | |
1967 | { | |
1968 | { 0x6300, 0xff00 }, /* addiu $sp,offset */ | |
1969 | { 0xfb00, 0xff00 }, /* daddiu $sp,offset */ | |
1970 | { 0xd000, 0xf800 }, /* sw reg,n($sp) */ | |
1971 | { 0xf900, 0xff00 }, /* sd reg,n($sp) */ | |
1972 | { 0x6200, 0xff00 }, /* sw $ra,n($sp) */ | |
1973 | { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */ | |
1974 | { 0x673d, 0xffff }, /* move $s1,sp */ | |
1975 | { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */ | |
1976 | { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */ | |
1977 | { 0xe809, 0xf81f }, /* entry pseudo-op */ | |
32dab603 | 1978 | { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */ |
20fa0902 MA |
1979 | { 0, 0 } /* end of table marker */ |
1980 | }; | |
1981 | ||
1982 | /* Skip the typical prologue instructions. These are the stack adjustment | |
1983 | instruction and the instructions that save registers on the stack | |
1984 | or in the gcc frame. */ | |
1985 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
1986 | { | |
20fa0902 | 1987 | unsigned short inst; |
20fa0902 MA |
1988 | int i; |
1989 | ||
c81a76b3 | 1990 | inst = mips_fetch_instruction (pc); |
20fa0902 MA |
1991 | |
1992 | /* Normally we ignore an extend instruction. However, if it is | |
1993 | not followed by a valid prologue instruction, we must adjust | |
1994 | the pc back over the extend so that it won't be considered | |
1995 | part of the prologue. */ | |
1996 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1997 | { | |
1998 | extend_bytes = MIPS16_INSTLEN; | |
1999 | continue; | |
2000 | } | |
2001 | prev_extend_bytes = extend_bytes; | |
2002 | extend_bytes = 0; | |
2003 | ||
2004 | /* Check for other valid prologue instructions besides extend. */ | |
2005 | for (i = 0; table[i].mask != 0; i++) | |
2006 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
2007 | break; | |
2008 | if (table[i].mask != 0) /* it was in table? */ | |
32dab603 | 2009 | continue; /* ignore it */ |
20fa0902 MA |
2010 | else /* non-prologue */ |
2011 | { | |
2012 | /* Return the current pc, adjusted backwards by 2 if | |
2013 | the previous instruction was an extend. */ | |
2014 | return pc - prev_extend_bytes; | |
2015 | } | |
2016 | } | |
32dab603 | 2017 | return pc; |
20fa0902 MA |
2018 | } |
2019 | ||
2020 | /* To skip prologues, I use this predicate. Returns either PC itself | |
2021 | if the code at PC does not look like a function prologue; otherwise | |
2022 | returns an address that (if we're lucky) follows the prologue. If | |
2023 | LENIENT, then we must skip everything which is involved in setting | |
2024 | up the frame (it's OK to skip more, just so long as we don't skip | |
2025 | anything which might clobber the registers which are being saved. | |
2026 | We must skip more in the case where part of the prologue is in the | |
2027 | delay slot of a non-prologue instruction). */ | |
2028 | ||
2029 | CORE_ADDR | |
2030 | mips_skip_prologue (pc, lenient) | |
2031 | CORE_ADDR pc; | |
2032 | int lenient; | |
2033 | { | |
2034 | /* See if we can determine the end of the prologue via the symbol table. | |
2035 | If so, then return either PC, or the PC after the prologue, whichever | |
2036 | is greater. */ | |
2037 | ||
2038 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
2039 | ||
2040 | if (post_prologue_pc != 0) | |
2041 | return max (pc, post_prologue_pc); | |
2042 | ||
2043 | /* Can't determine prologue from the symbol table, need to examine | |
2044 | instructions. */ | |
2045 | ||
899c4021 | 2046 | if (pc_is_mips16 (pc)) |
20fa0902 MA |
2047 | return mips16_skip_prologue (pc, lenient); |
2048 | else | |
2049 | return mips32_skip_prologue (pc, lenient); | |
bd5635a1 | 2050 | } |
c2a0f1cb | 2051 | |
002a422b | 2052 | #if 0 |
20fa0902 | 2053 | /* The lenient prologue stuff should be superseded by the code in |
002a422b JK |
2054 | init_extra_frame_info which looks to see whether the stores mentioned |
2055 | in the proc_desc have actually taken place. */ | |
2056 | ||
ee5fb959 JK |
2057 | /* Is address PC in the prologue (loosely defined) for function at |
2058 | STARTADDR? */ | |
2059 | ||
2060 | static int | |
2061 | mips_in_lenient_prologue (startaddr, pc) | |
2062 | CORE_ADDR startaddr; | |
2063 | CORE_ADDR pc; | |
2064 | { | |
2065 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
2066 | return pc >= startaddr && pc < end_prologue; | |
2067 | } | |
002a422b | 2068 | #endif |
ee5fb959 | 2069 | |
ac8cf67d PS |
2070 | /* Given a return value in `regbuf' with a type `valtype', |
2071 | extract and copy its value into `valbuf'. */ | |
2072 | void | |
2073 | mips_extract_return_value (valtype, regbuf, valbuf) | |
2074 | struct type *valtype; | |
2075 | char regbuf[REGISTER_BYTES]; | |
2076 | char *valbuf; | |
2077 | { | |
2078 | int regnum; | |
92a6d600 | 2079 | int offset = 0; |
c81a76b3 | 2080 | int len = TYPE_LENGTH (valtype); |
ac8cf67d | 2081 | |
e4dbd248 PS |
2082 | regnum = 2; |
2083 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
0af60e03 MS |
2084 | && (mips_fpu == MIPS_FPU_DOUBLE |
2085 | || (mips_fpu == MIPS_FPU_SINGLE && len <= MIPS_REGSIZE))) | |
f781fe93 | 2086 | regnum = FP0_REGNUM; |
ac8cf67d | 2087 | |
0af60e03 MS |
2088 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
2089 | { /* "un-left-justify" the value from the register */ | |
87910097 | 2090 | if (len < REGISTER_RAW_SIZE (regnum)) |
0af60e03 MS |
2091 | offset = REGISTER_RAW_SIZE (regnum) - len; |
2092 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ | |
2093 | len < REGISTER_RAW_SIZE (regnum) * 2 && | |
2094 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
2095 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
2096 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
2097 | } | |
c81a76b3 | 2098 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, len); |
f781fe93 | 2099 | REGISTER_CONVERT_TO_TYPE (regnum, valtype, valbuf); |
ac8cf67d PS |
2100 | } |
2101 | ||
2102 | /* Given a return value in `regbuf' with a type `valtype', | |
2103 | write it's value into the appropriate register. */ | |
2104 | void | |
2105 | mips_store_return_value (valtype, valbuf) | |
2106 | struct type *valtype; | |
2107 | char *valbuf; | |
2108 | { | |
2109 | int regnum; | |
0af60e03 MS |
2110 | int offset = 0; |
2111 | int len = TYPE_LENGTH (valtype); | |
ac8cf67d PS |
2112 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
2113 | ||
e4dbd248 PS |
2114 | regnum = 2; |
2115 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
0af60e03 MS |
2116 | && (mips_fpu == MIPS_FPU_DOUBLE |
2117 | || (mips_fpu == MIPS_FPU_SINGLE && len <= MIPS_REGSIZE))) | |
e4dbd248 PS |
2118 | regnum = FP0_REGNUM; |
2119 | ||
0af60e03 MS |
2120 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
2121 | { /* "left-justify" the value in the register */ | |
2122 | if (len < REGISTER_RAW_SIZE (regnum)) | |
2123 | offset = REGISTER_RAW_SIZE (regnum) - len; | |
2124 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ | |
2125 | len < REGISTER_RAW_SIZE (regnum) * 2 && | |
2126 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
2127 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
2128 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
2129 | } | |
2130 | memcpy(raw_buffer + offset, valbuf, len); | |
ac8cf67d | 2131 | REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); |
0af60e03 MS |
2132 | write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, |
2133 | len > REGISTER_RAW_SIZE (regnum) ? | |
2134 | len : REGISTER_RAW_SIZE (regnum)); | |
ac8cf67d PS |
2135 | } |
2136 | ||
e03c0cc6 ILT |
2137 | /* Exported procedure: Is PC in the signal trampoline code */ |
2138 | ||
2139 | int | |
2140 | in_sigtramp (pc, ignore) | |
2141 | CORE_ADDR pc; | |
2142 | char *ignore; /* function name */ | |
2143 | { | |
2144 | if (sigtramp_address == 0) | |
2145 | fixup_sigtramp (); | |
2146 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
2147 | } | |
2148 | ||
e4dbd248 PS |
2149 | /* Command to set FPU type. mips_fpu_string will have been set to the |
2150 | user's argument. Set mips_fpu based on mips_fpu_string, and then | |
2151 | canonicalize mips_fpu_string. */ | |
2152 | ||
2153 | /*ARGSUSED*/ | |
2154 | static void | |
2155 | mips_set_fpu_command (args, from_tty, c) | |
2156 | char *args; | |
2157 | int from_tty; | |
2158 | struct cmd_list_element *c; | |
2159 | { | |
2160 | char *err = NULL; | |
2161 | ||
2162 | if (mips_fpu_string == NULL || *mips_fpu_string == '\0') | |
2163 | mips_fpu = MIPS_FPU_DOUBLE; | |
2164 | else if (strcasecmp (mips_fpu_string, "double") == 0 | |
2165 | || strcasecmp (mips_fpu_string, "on") == 0 | |
2166 | || strcasecmp (mips_fpu_string, "1") == 0 | |
2167 | || strcasecmp (mips_fpu_string, "yes") == 0) | |
2168 | mips_fpu = MIPS_FPU_DOUBLE; | |
2169 | else if (strcasecmp (mips_fpu_string, "none") == 0 | |
2170 | || strcasecmp (mips_fpu_string, "off") == 0 | |
2171 | || strcasecmp (mips_fpu_string, "0") == 0 | |
2172 | || strcasecmp (mips_fpu_string, "no") == 0) | |
2173 | mips_fpu = MIPS_FPU_NONE; | |
2174 | else if (strcasecmp (mips_fpu_string, "single") == 0) | |
2175 | mips_fpu = MIPS_FPU_SINGLE; | |
2176 | else | |
2177 | err = strsave (mips_fpu_string); | |
2178 | ||
2179 | if (mips_fpu_string != NULL) | |
2180 | free (mips_fpu_string); | |
2181 | ||
2182 | switch (mips_fpu) | |
2183 | { | |
2184 | case MIPS_FPU_DOUBLE: | |
2185 | mips_fpu_string = strsave ("double"); | |
2186 | break; | |
2187 | case MIPS_FPU_SINGLE: | |
2188 | mips_fpu_string = strsave ("single"); | |
2189 | break; | |
2190 | case MIPS_FPU_NONE: | |
2191 | mips_fpu_string = strsave ("none"); | |
2192 | break; | |
2193 | } | |
2194 | ||
2195 | if (err != NULL) | |
2196 | { | |
2197 | struct cleanup *cleanups = make_cleanup (free, err); | |
2198 | error ("Unknown FPU type `%s'. Use `double', `none', or `single'.", | |
2199 | err); | |
2200 | do_cleanups (cleanups); | |
2201 | } | |
2202 | } | |
2203 | ||
2204 | static void | |
2205 | mips_show_fpu_command (args, from_tty, c) | |
2206 | char *args; | |
2207 | int from_tty; | |
2208 | struct cmd_list_element *c; | |
2209 | { | |
2210 | } | |
2211 | ||
9f9f94aa SS |
2212 | /* Command to set the processor type. */ |
2213 | ||
2214 | void | |
2215 | mips_set_processor_type_command (args, from_tty) | |
2216 | char *args; | |
2217 | int from_tty; | |
2218 | { | |
2219 | int i; | |
2220 | ||
2221 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
2222 | { | |
2223 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
2224 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
2225 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
2226 | ||
2227 | /* Restore the value. */ | |
2228 | tmp_mips_processor_type = strsave (mips_processor_type); | |
2229 | ||
2230 | return; | |
2231 | } | |
2232 | ||
2233 | if (!mips_set_processor_type (tmp_mips_processor_type)) | |
2234 | { | |
2235 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
2236 | /* Restore its value. */ | |
2237 | tmp_mips_processor_type = strsave (mips_processor_type); | |
2238 | } | |
2239 | } | |
2240 | ||
2241 | static void | |
2242 | mips_show_processor_type_command (args, from_tty) | |
2243 | char *args; | |
2244 | int from_tty; | |
2245 | { | |
2246 | } | |
2247 | ||
2248 | /* Modify the actual processor type. */ | |
2249 | ||
2250 | int | |
2251 | mips_set_processor_type (str) | |
2252 | char *str; | |
2253 | { | |
2254 | int i, j; | |
2255 | ||
2256 | if (str == NULL) | |
1d9489c1 | 2257 | return 0; |
9f9f94aa SS |
2258 | |
2259 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
2260 | { | |
2261 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
2262 | { | |
2263 | mips_processor_type = str; | |
2264 | ||
2265 | for (j = 0; j < NUM_REGS; ++j) | |
2266 | reg_names[j] = mips_processor_type_table[i].regnames[j]; | |
2267 | ||
2268 | return 1; | |
2269 | ||
2270 | /* FIXME tweak fpu flag too */ | |
2271 | } | |
2272 | } | |
2273 | ||
2274 | return 0; | |
2275 | } | |
2276 | ||
2277 | /* Attempt to identify the particular processor model by reading the | |
2278 | processor id. */ | |
2279 | ||
2280 | char * | |
2281 | mips_read_processor_type () | |
2282 | { | |
28444bf3 | 2283 | CORE_ADDR prid; |
9f9f94aa SS |
2284 | |
2285 | prid = read_register (PRID_REGNUM); | |
2286 | ||
80e0e92a | 2287 | if ((prid & ~0xf) == 0x700) |
9f9f94aa SS |
2288 | return savestring ("r3041", strlen("r3041")); |
2289 | ||
2290 | return NULL; | |
2291 | } | |
427fec5d JK |
2292 | |
2293 | /* Just like reinit_frame_cache, but with the right arguments to be | |
2294 | callable as an sfunc. */ | |
9f9f94aa | 2295 | |
427fec5d JK |
2296 | static void |
2297 | reinit_frame_cache_sfunc (args, from_tty, c) | |
2298 | char *args; | |
2299 | int from_tty; | |
2300 | struct cmd_list_element *c; | |
2301 | { | |
2302 | reinit_frame_cache (); | |
2303 | } | |
c2a0f1cb | 2304 | |
28444bf3 | 2305 | static int |
18b46e7c SS |
2306 | gdb_print_insn_mips (memaddr, info) |
2307 | bfd_vma memaddr; | |
2308 | disassemble_info *info; | |
2309 | { | |
f9f8c14b MA |
2310 | mips_extra_func_info_t proc_desc; |
2311 | ||
2312 | /* Search for the function containing this address. Set the low bit | |
2313 | of the address when searching, in case we were given an even address | |
2314 | that is the start of a 16-bit function. If we didn't do this, | |
2315 | the search would fail because the symbol table says the function | |
2316 | starts at an odd address, i.e. 1 byte past the given address. */ | |
c1fc0935 MA |
2317 | memaddr = ADDR_BITS_REMOVE (memaddr); |
2318 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
f9f8c14b MA |
2319 | |
2320 | /* Make an attempt to determine if this is a 16-bit function. If | |
2321 | the procedure descriptor exists and the address therein is odd, | |
2322 | it's definitely a 16-bit function. Otherwise, we have to just | |
2323 | guess that if the address passed in is odd, it's 16-bits. */ | |
2324 | if (proc_desc) | |
899c4021 | 2325 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? 16 : 0; |
f9f8c14b | 2326 | else |
899c4021 | 2327 | info->mach = pc_is_mips16 (memaddr) ? 16 : 0; |
f9f8c14b | 2328 | |
c1fc0935 | 2329 | /* Round down the instruction address to the appropriate boundary. */ |
f9f8c14b MA |
2330 | memaddr &= (info->mach == 16 ? ~1 : ~3); |
2331 | ||
2332 | /* Call the appropriate disassembler based on the target endian-ness. */ | |
18b46e7c SS |
2333 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
2334 | return print_insn_big_mips (memaddr, info); | |
2335 | else | |
2336 | return print_insn_little_mips (memaddr, info); | |
2337 | } | |
2338 | ||
f9f8c14b MA |
2339 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
2340 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
2341 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
2342 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
2343 | (if necessary) to point to the actual memory location where the | |
2344 | breakpoint should be inserted. */ | |
2345 | ||
2346 | unsigned char *mips_breakpoint_from_pc (pcptr, lenptr) | |
2347 | CORE_ADDR *pcptr; | |
2348 | int *lenptr; | |
2349 | { | |
2350 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2351 | { | |
899c4021 | 2352 | if (pc_is_mips16 (*pcptr)) |
f9f8c14b MA |
2353 | { |
2354 | static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT; | |
c1fc0935 | 2355 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
f9f8c14b MA |
2356 | *lenptr = sizeof(mips16_big_breakpoint); |
2357 | return mips16_big_breakpoint; | |
2358 | } | |
2359 | else | |
2360 | { | |
2361 | static char big_breakpoint[] = BIG_BREAKPOINT; | |
f781fe93 MA |
2362 | static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; |
2363 | static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
2364 | ||
f9f8c14b | 2365 | *lenptr = sizeof(big_breakpoint); |
f781fe93 MA |
2366 | |
2367 | if (strcmp (target_shortname, "mips") == 0) | |
2368 | return idt_big_breakpoint; | |
2369 | else if (strcmp (target_shortname, "ddb") == 0 | |
2370 | || strcmp (target_shortname, "pmon") == 0 | |
2371 | || strcmp (target_shortname, "lsi") == 0) | |
2372 | return pmon_big_breakpoint; | |
2373 | else | |
2374 | return big_breakpoint; | |
f9f8c14b MA |
2375 | } |
2376 | } | |
2377 | else | |
2378 | { | |
899c4021 | 2379 | if (pc_is_mips16 (*pcptr)) |
f9f8c14b MA |
2380 | { |
2381 | static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT; | |
c1fc0935 | 2382 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
f9f8c14b MA |
2383 | *lenptr = sizeof(mips16_little_breakpoint); |
2384 | return mips16_little_breakpoint; | |
2385 | } | |
2386 | else | |
2387 | { | |
2388 | static char little_breakpoint[] = LITTLE_BREAKPOINT; | |
f781fe93 MA |
2389 | static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT; |
2390 | static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT; | |
2391 | ||
f9f8c14b | 2392 | *lenptr = sizeof(little_breakpoint); |
f781fe93 MA |
2393 | |
2394 | if (strcmp (target_shortname, "mips") == 0) | |
2395 | return idt_little_breakpoint; | |
2396 | else if (strcmp (target_shortname, "ddb") == 0 | |
2397 | || strcmp (target_shortname, "pmon") == 0 | |
2398 | || strcmp (target_shortname, "lsi") == 0) | |
2399 | return pmon_little_breakpoint; | |
2400 | else | |
2401 | return little_breakpoint; | |
f9f8c14b MA |
2402 | } |
2403 | } | |
2404 | } | |
2405 | ||
2406 | /* Test whether the PC points to the return instruction at the | |
2407 | end of a function. This implements the ABOUT_TO_RETURN macro. */ | |
2408 | ||
2409 | int | |
2410 | mips_about_to_return (pc) | |
2411 | CORE_ADDR pc; | |
2412 | { | |
899c4021 | 2413 | if (pc_is_mips16 (pc)) |
f9f8c14b MA |
2414 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2415 | generates a "jr $ra"; other times it generates code to load | |
2416 | the return address from the stack to an accessible register (such | |
2417 | as $a3), then a "jr" using that register. This second case | |
2418 | is almost impossible to distinguish from an indirect jump | |
2419 | used for switch statements, so we don't even try. */ | |
c81a76b3 | 2420 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ |
f9f8c14b | 2421 | else |
c81a76b3 | 2422 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ |
f9f8c14b MA |
2423 | } |
2424 | ||
2425 | ||
f781fe93 MA |
2426 | /* If PC is in a mips16 call or return stub, return the address of the target |
2427 | PC, which is either the callee or the caller. There are several | |
2428 | cases which must be handled: | |
2429 | ||
2430 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
2431 | target PC is in $31 ($ra). | |
2432 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
2433 | and the target PC is in $2. | |
2434 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
2435 | before the jal instruction, this is effectively a call stub | |
2436 | and the the target PC is in $2. Otherwise this is effectively | |
2437 | a return stub and the target PC is in $18. | |
2438 | ||
2439 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
2440 | gory details. | |
2441 | ||
2442 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
2443 | */ | |
2444 | ||
2445 | CORE_ADDR | |
2446 | mips_skip_stub (pc) | |
2447 | CORE_ADDR pc; | |
2448 | { | |
2449 | char *name; | |
2450 | CORE_ADDR start_addr; | |
2451 | ||
2452 | /* Find the starting address and name of the function containing the PC. */ | |
2453 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2454 | return 0; | |
2455 | ||
2456 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
2457 | target PC is in $31 ($ra). */ | |
2458 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
2459 | || strcmp (name, "__mips16_ret_df") == 0) | |
2460 | return read_register (RA_REGNUM); | |
2461 | ||
2462 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
2463 | { | |
2464 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
2465 | and the target PC is in $2. */ | |
2466 | if (name[19] >= '0' && name[19] <= '9') | |
2467 | return read_register (2); | |
2468 | ||
2469 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
2470 | before the jal instruction, this is effectively a call stub | |
2471 | and the the target PC is in $2. Otherwise this is effectively | |
2472 | a return stub and the target PC is in $18. */ | |
2473 | else if (name[19] == 's' || name[19] == 'd') | |
2474 | { | |
2475 | if (pc == start_addr) | |
2476 | { | |
2477 | /* Check if the target of the stub is a compiler-generated | |
2478 | stub. Such a stub for a function bar might have a name | |
2479 | like __fn_stub_bar, and might look like this: | |
2480 | mfc1 $4,$f13 | |
2481 | mfc1 $5,$f12 | |
2482 | mfc1 $6,$f15 | |
2483 | mfc1 $7,$f14 | |
2484 | la $1,bar (becomes a lui/addiu pair) | |
2485 | jr $1 | |
2486 | So scan down to the lui/addi and extract the target | |
2487 | address from those two instructions. */ | |
2488 | ||
2489 | CORE_ADDR target_pc = read_register (2); | |
2490 | t_inst inst; | |
2491 | int i; | |
2492 | ||
2493 | /* See if the name of the target function is __fn_stub_*. */ | |
2494 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
2495 | return target_pc; | |
2496 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
2497 | && strcmp (name, "etext") != 0 | |
2498 | && strcmp (name, "_etext") != 0) | |
2499 | return target_pc; | |
2500 | ||
2501 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
2502 | The limit on the search is arbitrarily set to 20 | |
2503 | instructions. FIXME. */ | |
2504 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) | |
2505 | { | |
2506 | inst = mips_fetch_instruction (target_pc); | |
2507 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
2508 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
2509 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
2510 | return pc | (inst & 0xffff); /* low word */ | |
2511 | } | |
2512 | ||
2513 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
2514 | return target_pc; | |
2515 | } | |
2516 | else | |
2517 | /* This is the 'return' part of a call stub. The return | |
2518 | address is in $r18. */ | |
2519 | return read_register (18); | |
2520 | } | |
2521 | } | |
2522 | return 0; /* not a stub */ | |
2523 | } | |
2524 | ||
2525 | ||
2526 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
2527 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
2528 | ||
2529 | int | |
2530 | mips_in_call_stub (pc, name) | |
2531 | CORE_ADDR pc; | |
2532 | char *name; | |
2533 | { | |
2534 | CORE_ADDR start_addr; | |
2535 | ||
2536 | /* Find the starting address of the function containing the PC. If the | |
2537 | caller didn't give us a name, look it up at the same time. */ | |
2538 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
2539 | return 0; | |
2540 | ||
2541 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
2542 | { | |
2543 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
2544 | if (name[19] >= '0' && name[19] <= '9') | |
2545 | return 1; | |
2546 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
2547 | before the jal instruction, this is effectively a call stub. */ | |
2548 | else if (name[19] == 's' || name[19] == 'd') | |
2549 | return pc == start_addr; | |
2550 | } | |
2551 | ||
2552 | return 0; /* not a stub */ | |
2553 | } | |
2554 | ||
2555 | ||
2556 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
2557 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
2558 | ||
2559 | int | |
2560 | mips_in_return_stub (pc, name) | |
2561 | CORE_ADDR pc; | |
2562 | char *name; | |
2563 | { | |
2564 | CORE_ADDR start_addr; | |
2565 | ||
2566 | /* Find the starting address of the function containing the PC. */ | |
2567 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
2568 | return 0; | |
2569 | ||
2570 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
2571 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
2572 | || strcmp (name, "__mips16_ret_df") == 0) | |
2573 | return 1; | |
2574 | ||
2575 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
2576 | i.e. after the jal instruction, this is effectively a return stub. */ | |
2577 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 | |
2578 | && (name[19] == 's' || name[19] == 'd') | |
2579 | && pc != start_addr) | |
2580 | return 1; | |
2581 | ||
2582 | return 0; /* not a stub */ | |
2583 | } | |
2584 | ||
2585 | ||
2586 | /* Return non-zero if the PC is in a library helper function that should | |
2587 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
2588 | ||
2589 | int | |
2590 | mips_ignore_helper (pc) | |
2591 | CORE_ADDR pc; | |
2592 | { | |
2593 | char *name; | |
2594 | ||
2595 | /* Find the starting address and name of the function containing the PC. */ | |
2596 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
2597 | return 0; | |
2598 | ||
2599 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
2600 | that we want to ignore. */ | |
2601 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
2602 | || strcmp (name, "__mips16_ret_df") == 0); | |
2603 | } | |
2604 | ||
2605 | ||
c2a0f1cb ILT |
2606 | void |
2607 | _initialize_mips_tdep () | |
2608 | { | |
427fec5d JK |
2609 | struct cmd_list_element *c; |
2610 | ||
18b46e7c SS |
2611 | tm_print_insn = gdb_print_insn_mips; |
2612 | ||
427fec5d JK |
2613 | /* Let the user turn off floating point and set the fence post for |
2614 | heuristic_proc_start. */ | |
2615 | ||
e4dbd248 PS |
2616 | c = add_set_cmd ("mipsfpu", class_support, var_string_noescape, |
2617 | (char *) &mips_fpu_string, | |
2618 | "Set use of floating point coprocessor.\n\ | |
2619 | Set to `none' to avoid using floating point instructions when calling\n\ | |
2620 | functions or dealing with return values. Set to `single' to use only\n\ | |
2621 | single precision floating point as on the R4650. Set to `double' for\n\ | |
2622 | normal floating point support.", | |
2623 | &setlist); | |
2624 | c->function.sfunc = mips_set_fpu_command; | |
2625 | c = add_show_from_set (c, &showlist); | |
2626 | c->function.sfunc = mips_show_fpu_command; | |
2627 | ||
2628 | mips_fpu = MIPS_FPU_DOUBLE; | |
2629 | mips_fpu_string = strsave ("double"); | |
3127785a | 2630 | |
9f9f94aa SS |
2631 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
2632 | (char *) &tmp_mips_processor_type, | |
2633 | "Set the type of MIPS processor in use.\n\ | |
2634 | Set this to be able to access processor-type-specific registers.\n\ | |
2635 | ", | |
2636 | &setlist); | |
2637 | c->function.cfunc = mips_set_processor_type_command; | |
2638 | c = add_show_from_set (c, &showlist); | |
2639 | c->function.cfunc = mips_show_processor_type_command; | |
2640 | ||
2641 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
2642 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
2643 | ||
bdef72d2 JK |
2644 | /* We really would like to have both "0" and "unlimited" work, but |
2645 | command.c doesn't deal with that. So make it a var_zinteger | |
2646 | because the user can always use "999999" or some such for unlimited. */ | |
2647 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
427fec5d JK |
2648 | (char *) &heuristic_fence_post, |
2649 | "\ | |
23d35572 JK |
2650 | Set the distance searched for the start of a function.\n\ |
2651 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
2652 | program for the start of a function. This command sets the distance of the\n\ | |
2653 | search. The only need to set it is when debugging a stripped executable.", | |
427fec5d JK |
2654 | &setlist); |
2655 | /* We need to throw away the frame cache when we set this, since it | |
2656 | might change our ability to get backtraces. */ | |
2657 | c->function.sfunc = reinit_frame_cache_sfunc; | |
2658 | add_show_from_set (c, &showlist); | |
c2a0f1cb | 2659 | } |