Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
dd824b04 DJ |
63 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
64 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
65 | #define ST0_FR (1 << 26) | |
66 | ||
b0069a17 AC |
67 | /* The sizes of floating point registers. */ |
68 | ||
69 | enum | |
70 | { | |
71 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
72 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
73 | }; | |
74 | ||
0dadbba0 | 75 | |
2e4ebe70 DJ |
76 | static const char *mips_abi_string; |
77 | ||
78 | static const char *mips_abi_strings[] = { | |
79 | "auto", | |
80 | "n32", | |
81 | "o32", | |
28d169de | 82 | "n64", |
2e4ebe70 DJ |
83 | "o64", |
84 | "eabi32", | |
85 | "eabi64", | |
86 | NULL | |
87 | }; | |
88 | ||
cce74817 | 89 | struct frame_extra_info |
6d82d43b AC |
90 | { |
91 | mips_extra_func_info_t proc_desc; | |
92 | int num_args; | |
93 | }; | |
cce74817 | 94 | |
d929b26f AC |
95 | /* Various MIPS ISA options (related to stack analysis) can be |
96 | overridden dynamically. Establish an enum/array for managing | |
97 | them. */ | |
98 | ||
53904c9e AC |
99 | static const char size_auto[] = "auto"; |
100 | static const char size_32[] = "32"; | |
101 | static const char size_64[] = "64"; | |
d929b26f | 102 | |
53904c9e | 103 | static const char *size_enums[] = { |
d929b26f AC |
104 | size_auto, |
105 | size_32, | |
106 | size_64, | |
a5ea2558 AC |
107 | 0 |
108 | }; | |
109 | ||
7a292a7a | 110 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 111 | support single-precision floating-point operations. */ |
c906108c SS |
112 | |
113 | enum mips_fpu_type | |
6d82d43b AC |
114 | { |
115 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
116 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
117 | MIPS_FPU_NONE /* No floating point. */ | |
118 | }; | |
c906108c SS |
119 | |
120 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
121 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
122 | #endif | |
123 | static int mips_fpu_type_auto = 1; | |
124 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 125 | |
9ace0497 | 126 | static int mips_debug = 0; |
7a292a7a | 127 | |
c2d11a7d JM |
128 | /* MIPS specific per-architecture information */ |
129 | struct gdbarch_tdep | |
6d82d43b AC |
130 | { |
131 | /* from the elf header */ | |
132 | int elf_flags; | |
133 | ||
134 | /* mips options */ | |
135 | enum mips_abi mips_abi; | |
136 | enum mips_abi found_abi; | |
137 | enum mips_fpu_type mips_fpu_type; | |
138 | int mips_last_arg_regnum; | |
139 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
140 | int default_mask_address_p; |
141 | /* Is the target using 64-bit raw integer registers but only | |
142 | storing a left-aligned 32-bit value in each? */ | |
143 | int mips64_transfers_32bit_regs_p; | |
144 | /* Indexes for various registers. IRIX and embedded have | |
145 | different values. This contains the "public" fields. Don't | |
146 | add any that do not need to be public. */ | |
147 | const struct mips_regnum *regnum; | |
148 | /* Register names table for the current register set. */ | |
149 | const char **mips_processor_reg_names; | |
150 | }; | |
c2d11a7d | 151 | |
fed7ba43 JB |
152 | static int |
153 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
154 | const char *from) | |
155 | { | |
156 | return 1; | |
157 | } | |
158 | ||
159 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
160 | They are implemented as a pair of 64bit doubles where the high | |
161 | part holds the result of the operation rounded to double, and | |
162 | the low double holds the difference between the exact result and | |
163 | the rounded result. So "high" + "low" contains the result with | |
164 | added precision. Unfortunately, the floatformat structure used | |
165 | by GDB is not powerful enough to describe this format. As a temporary | |
166 | measure, we define a 128bit floatformat that only uses the high part. | |
167 | We lose a bit of precision but that's probably the best we can do | |
168 | for now with the current infrastructure. */ | |
169 | ||
170 | static const struct floatformat floatformat_n32n64_long_double_big = | |
171 | { | |
172 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
173 | floatformat_intbit_no, | |
174 | "floatformat_ieee_double_big", | |
175 | n32n64_floatformat_always_valid | |
176 | }; | |
177 | ||
56cea623 AC |
178 | const struct mips_regnum * |
179 | mips_regnum (struct gdbarch *gdbarch) | |
180 | { | |
181 | return gdbarch_tdep (gdbarch)->regnum; | |
182 | } | |
183 | ||
184 | static int | |
185 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
186 | { | |
187 | return mips_regnum (gdbarch)->fp0 + 12; | |
188 | } | |
189 | ||
0dadbba0 | 190 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 191 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 192 | |
c2d11a7d | 193 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 194 | |
c2d11a7d | 195 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 196 | |
c2d11a7d | 197 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 198 | |
95404a3e AC |
199 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
200 | functions to test, set, or clear bit 0 of addresses. */ | |
201 | ||
202 | static CORE_ADDR | |
203 | is_mips16_addr (CORE_ADDR addr) | |
204 | { | |
205 | return ((addr) & 1); | |
206 | } | |
207 | ||
208 | static CORE_ADDR | |
209 | make_mips16_addr (CORE_ADDR addr) | |
210 | { | |
211 | return ((addr) | 1); | |
212 | } | |
213 | ||
214 | static CORE_ADDR | |
215 | unmake_mips16_addr (CORE_ADDR addr) | |
216 | { | |
217 | return ((addr) & ~1); | |
218 | } | |
219 | ||
22540ece AC |
220 | /* Return the contents of register REGNUM as a signed integer. */ |
221 | ||
222 | static LONGEST | |
223 | read_signed_register (int regnum) | |
224 | { | |
719ec221 | 225 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 226 | deprecated_read_register_gen (regnum, buf); |
6d82d43b AC |
227 | return (extract_signed_integer |
228 | (buf, register_size (current_gdbarch, regnum))); | |
22540ece AC |
229 | } |
230 | ||
231 | static LONGEST | |
232 | read_signed_register_pid (int regnum, ptid_t ptid) | |
233 | { | |
234 | ptid_t save_ptid; | |
235 | LONGEST retval; | |
236 | ||
237 | if (ptid_equal (ptid, inferior_ptid)) | |
238 | return read_signed_register (regnum); | |
239 | ||
240 | save_ptid = inferior_ptid; | |
241 | ||
242 | inferior_ptid = ptid; | |
243 | ||
244 | retval = read_signed_register (regnum); | |
245 | ||
246 | inferior_ptid = save_ptid; | |
247 | ||
248 | return retval; | |
249 | } | |
250 | ||
d1973055 KB |
251 | /* Return the MIPS ABI associated with GDBARCH. */ |
252 | enum mips_abi | |
253 | mips_abi (struct gdbarch *gdbarch) | |
254 | { | |
255 | return gdbarch_tdep (gdbarch)->mips_abi; | |
256 | } | |
257 | ||
4246e332 | 258 | int |
1b13c4f6 | 259 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 AC |
260 | { |
261 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
262 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
263 | } | |
264 | ||
480d3dd2 AC |
265 | /* Return the currently configured (or set) saved register size. */ |
266 | ||
1b13c4f6 | 267 | static const char *mips_abi_regsize_string = size_auto; |
480d3dd2 | 268 | |
d929b26f | 269 | static unsigned int |
13326b4e | 270 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 271 | { |
1b13c4f6 | 272 | if (mips_abi_regsize_string == size_auto) |
13326b4e AC |
273 | switch (mips_abi (gdbarch)) |
274 | { | |
275 | case MIPS_ABI_EABI32: | |
276 | case MIPS_ABI_O32: | |
277 | return 4; | |
278 | case MIPS_ABI_N32: | |
279 | case MIPS_ABI_N64: | |
280 | case MIPS_ABI_O64: | |
281 | case MIPS_ABI_EABI64: | |
282 | return 8; | |
283 | case MIPS_ABI_UNKNOWN: | |
284 | case MIPS_ABI_LAST: | |
285 | default: | |
286 | internal_error (__FILE__, __LINE__, "bad switch"); | |
287 | } | |
1b13c4f6 | 288 | else if (mips_abi_regsize_string == size_64) |
d929b26f | 289 | return 8; |
1b13c4f6 | 290 | else /* if (mips_abi_regsize_string == size_32) */ |
d929b26f AC |
291 | return 4; |
292 | } | |
293 | ||
71b8ef93 | 294 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 295 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 296 | "info" field is used for this purpose. |
5a89d8aa MS |
297 | |
298 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
299 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
300 | minimal symbol to mark it as a 16-bit function | |
301 | ||
f594e5e9 | 302 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 303 | |
5a89d8aa | 304 | static void |
6d82d43b AC |
305 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
306 | { | |
307 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
308 | { | |
309 | MSYMBOL_INFO (msym) = (char *) | |
310 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
311 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
312 | } | |
5a89d8aa MS |
313 | } |
314 | ||
71b8ef93 MS |
315 | static int |
316 | msymbol_is_special (struct minimal_symbol *msym) | |
317 | { | |
318 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
319 | } | |
320 | ||
88658117 AC |
321 | /* XFER a value from the big/little/left end of the register. |
322 | Depending on the size of the value it might occupy the entire | |
323 | register or just part of it. Make an allowance for this, aligning | |
324 | things accordingly. */ | |
325 | ||
326 | static void | |
327 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
328 | enum bfd_endian endian, bfd_byte * in, |
329 | const bfd_byte * out, int buf_offset) | |
88658117 | 330 | { |
88658117 | 331 | int reg_offset = 0; |
a4b8ebc8 | 332 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
333 | /* Need to transfer the left or right part of the register, based on |
334 | the targets byte order. */ | |
88658117 AC |
335 | switch (endian) |
336 | { | |
337 | case BFD_ENDIAN_BIG: | |
719ec221 | 338 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
339 | break; |
340 | case BFD_ENDIAN_LITTLE: | |
341 | reg_offset = 0; | |
342 | break; | |
6d82d43b | 343 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
344 | reg_offset = 0; |
345 | break; | |
346 | default: | |
347 | internal_error (__FILE__, __LINE__, "bad switch"); | |
348 | } | |
349 | if (mips_debug) | |
cb1d2653 AC |
350 | fprintf_unfiltered (gdb_stderr, |
351 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
352 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
353 | if (mips_debug && out != NULL) |
354 | { | |
355 | int i; | |
cb1d2653 | 356 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 357 | for (i = 0; i < length; i++) |
cb1d2653 | 358 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
359 | } |
360 | if (in != NULL) | |
6d82d43b AC |
361 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
362 | in + buf_offset); | |
88658117 | 363 | if (out != NULL) |
6d82d43b AC |
364 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
365 | out + buf_offset); | |
88658117 AC |
366 | if (mips_debug && in != NULL) |
367 | { | |
368 | int i; | |
cb1d2653 | 369 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 370 | for (i = 0; i < length; i++) |
cb1d2653 | 371 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
372 | } |
373 | if (mips_debug) | |
374 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
375 | } | |
376 | ||
dd824b04 DJ |
377 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
378 | compatiblity mode. A return value of 1 means that we have | |
379 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
380 | ||
381 | static int | |
382 | mips2_fp_compat (void) | |
383 | { | |
384 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
385 | meaningful. */ | |
6d82d43b AC |
386 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
387 | 4) | |
dd824b04 DJ |
388 | return 0; |
389 | ||
390 | #if 0 | |
391 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
392 | in all the places we deal with FP registers. PR gdb/413. */ | |
393 | /* Otherwise check the FR bit in the status register - it controls | |
394 | the FP compatiblity mode. If it is clear we are in compatibility | |
395 | mode. */ | |
396 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
397 | return 1; | |
398 | #endif | |
361d1df0 | 399 | |
dd824b04 DJ |
400 | return 0; |
401 | } | |
402 | ||
d929b26f | 403 | /* The amount of space reserved on the stack for registers. This is |
1b13c4f6 | 404 | different to MIPS_ABI_REGSIZE as it determines the alignment of |
d929b26f AC |
405 | data allocated after the registers have run out. */ |
406 | ||
53904c9e | 407 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
408 | |
409 | static unsigned int | |
13326b4e | 410 | mips_stack_argsize (struct gdbarch *gdbarch) |
d929b26f AC |
411 | { |
412 | if (mips_stack_argsize_string == size_auto) | |
13326b4e | 413 | return mips_abi_regsize (gdbarch); |
d929b26f AC |
414 | else if (mips_stack_argsize_string == size_64) |
415 | return 8; | |
6d82d43b | 416 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
417 | return 4; |
418 | } | |
419 | ||
7a292a7a | 420 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 421 | |
c9343fd1 | 422 | struct mips_frame_cache; |
570b8f7c | 423 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
c9343fd1 AC |
424 | struct frame_info *, |
425 | struct mips_frame_cache *); | |
eec63939 AC |
426 | static mips_extra_func_info_t non_heuristic_proc_desc (CORE_ADDR pc, |
427 | CORE_ADDR *addrptr); | |
c906108c | 428 | |
a14ed312 | 429 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 430 | |
a14ed312 | 431 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 432 | |
a14ed312 | 433 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 434 | |
177f84a3 | 435 | static CORE_ADDR after_prologue (CORE_ADDR pc); |
c906108c | 436 | |
67b2c998 DJ |
437 | static struct type *mips_float_register_type (void); |
438 | static struct type *mips_double_register_type (void); | |
439 | ||
acdb74a0 AC |
440 | /* The list of available "set mips " and "show mips " commands */ |
441 | ||
442 | static struct cmd_list_element *setmipscmdlist = NULL; | |
443 | static struct cmd_list_element *showmipscmdlist = NULL; | |
444 | ||
5e2e9765 KB |
445 | /* Integer registers 0 thru 31 are handled explicitly by |
446 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
447 | are listed in the followign tables. */ |
448 | ||
6d82d43b AC |
449 | enum |
450 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
451 | |
452 | /* Generic MIPS. */ | |
453 | ||
454 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
455 | "sr", "lo", "hi", "bad", "cause", "pc", |
456 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
457 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
458 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
459 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
460 | "fsr", "fir", "" /*"fp" */ , "", | |
461 | "", "", "", "", "", "", "", "", | |
462 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
463 | }; |
464 | ||
465 | /* Names of IDT R3041 registers. */ | |
466 | ||
467 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
468 | "sr", "lo", "hi", "bad", "cause", "pc", |
469 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
470 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
471 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
472 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
473 | "fsr", "fir", "", /*"fp" */ "", | |
474 | "", "", "bus", "ccfg", "", "", "", "", | |
475 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
476 | }; |
477 | ||
478 | /* Names of tx39 registers. */ | |
479 | ||
480 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
481 | "sr", "lo", "hi", "bad", "cause", "pc", |
482 | "", "", "", "", "", "", "", "", | |
483 | "", "", "", "", "", "", "", "", | |
484 | "", "", "", "", "", "", "", "", | |
485 | "", "", "", "", "", "", "", "", | |
486 | "", "", "", "", | |
487 | "", "", "", "", "", "", "", "", | |
488 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
489 | }; |
490 | ||
491 | /* Names of IRIX registers. */ | |
492 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
493 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
494 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
495 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
496 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
497 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
498 | }; |
499 | ||
cce74817 | 500 | |
5e2e9765 | 501 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 502 | static const char * |
5e2e9765 | 503 | mips_register_name (int regno) |
cce74817 | 504 | { |
691c0433 | 505 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
506 | /* GPR names for all ABIs other than n32/n64. */ |
507 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
508 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
509 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
510 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
511 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
512 | }; |
513 | ||
514 | /* GPR names for n32 and n64 ABIs. */ | |
515 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
516 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
517 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
518 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
519 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
520 | }; |
521 | ||
522 | enum mips_abi abi = mips_abi (current_gdbarch); | |
523 | ||
a4b8ebc8 AC |
524 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
525 | don't make the raw register names visible. */ | |
526 | int rawnum = regno % NUM_REGS; | |
527 | if (regno < NUM_REGS) | |
528 | return ""; | |
529 | ||
5e2e9765 KB |
530 | /* The MIPS integer registers are always mapped from 0 to 31. The |
531 | names of the registers (which reflects the conventions regarding | |
532 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 533 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
534 | { |
535 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 536 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 537 | else |
a4b8ebc8 | 538 | return mips_gpr_names[rawnum]; |
5e2e9765 | 539 | } |
a4b8ebc8 | 540 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
541 | { |
542 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
543 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
544 | } | |
5e2e9765 KB |
545 | else |
546 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 547 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 548 | } |
5e2e9765 | 549 | |
a4b8ebc8 | 550 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 551 | |
a4b8ebc8 AC |
552 | static int |
553 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
554 | struct reggroup *reggroup) | |
555 | { | |
556 | int vector_p; | |
557 | int float_p; | |
558 | int raw_p; | |
559 | int rawnum = regnum % NUM_REGS; | |
560 | int pseudo = regnum / NUM_REGS; | |
561 | if (reggroup == all_reggroup) | |
562 | return pseudo; | |
563 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
564 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
565 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
566 | (gdbarch), as not all architectures are multi-arch. */ | |
567 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 568 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
569 | return 0; |
570 | if (reggroup == float_reggroup) | |
571 | return float_p && pseudo; | |
572 | if (reggroup == vector_reggroup) | |
573 | return vector_p && pseudo; | |
574 | if (reggroup == general_reggroup) | |
575 | return (!vector_p && !float_p) && pseudo; | |
576 | /* Save the pseudo registers. Need to make certain that any code | |
577 | extracting register values from a saved register cache also uses | |
578 | pseudo registers. */ | |
579 | if (reggroup == save_reggroup) | |
580 | return raw_p && pseudo; | |
581 | /* Restore the same pseudo register. */ | |
582 | if (reggroup == restore_reggroup) | |
583 | return raw_p && pseudo; | |
6d82d43b | 584 | return 0; |
a4b8ebc8 AC |
585 | } |
586 | ||
587 | /* Map the symbol table registers which live in the range [1 * | |
588 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 589 | registers. Take care of alignment and size problems. */ |
c5aa993b | 590 | |
a4b8ebc8 AC |
591 | static void |
592 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
593 | int cookednum, void *buf) | |
594 | { | |
47ebcfbe | 595 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 596 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 597 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 598 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
599 | else if (register_size (gdbarch, rawnum) > |
600 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
601 | { |
602 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
603 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
604 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
605 | else | |
606 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
607 | } | |
608 | else | |
609 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
610 | } |
611 | ||
612 | static void | |
6d82d43b AC |
613 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
614 | struct regcache *regcache, int cookednum, | |
615 | const void *buf) | |
a4b8ebc8 | 616 | { |
47ebcfbe | 617 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 618 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 619 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 620 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
621 | else if (register_size (gdbarch, rawnum) > |
622 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
623 | { |
624 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
625 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
626 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
627 | else | |
628 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
629 | } | |
630 | else | |
631 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 632 | } |
c5aa993b | 633 | |
c906108c | 634 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 635 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
636 | |
637 | /* Heuristic_proc_start may hunt through the text section for a long | |
638 | time across a 2400 baud serial line. Allows the user to limit this | |
639 | search. */ | |
640 | ||
641 | static unsigned int heuristic_fence_post = 0; | |
642 | ||
c5aa993b JM |
643 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
644 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
645 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
646 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
647 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
648 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
649 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
650 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
651 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
652 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
653 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
654 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
655 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
656 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
c906108c | 657 | |
46cd78fb | 658 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
659 | register N. NOTE: This defines the pseudo register type so need to |
660 | rebuild the architecture vector. */ | |
43e526b9 JM |
661 | |
662 | static int mips64_transfers_32bit_regs_p = 0; | |
663 | ||
719ec221 AC |
664 | static void |
665 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
666 | struct cmd_list_element *c) | |
43e526b9 | 667 | { |
719ec221 AC |
668 | struct gdbarch_info info; |
669 | gdbarch_info_init (&info); | |
670 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
671 | instead of relying on globals. Doing that would let generic code | |
672 | handle the search for this specific architecture. */ | |
673 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 674 | { |
719ec221 AC |
675 | mips64_transfers_32bit_regs_p = 0; |
676 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 677 | } |
a4b8ebc8 AC |
678 | } |
679 | ||
47ebcfbe | 680 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 681 | |
ff2e87ac AC |
682 | static int |
683 | mips_convert_register_p (int regnum, struct type *type) | |
684 | { | |
685 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 686 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
687 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
688 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 689 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
690 | } |
691 | ||
42c466d7 | 692 | static void |
ff2e87ac AC |
693 | mips_register_to_value (struct frame_info *frame, int regnum, |
694 | struct type *type, void *to) | |
102182a9 | 695 | { |
7f5f525d AC |
696 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
697 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
698 | } |
699 | ||
42c466d7 | 700 | static void |
ff2e87ac AC |
701 | mips_value_to_register (struct frame_info *frame, int regnum, |
702 | struct type *type, const void *from) | |
102182a9 | 703 | { |
ff2e87ac AC |
704 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
705 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
706 | } |
707 | ||
a4b8ebc8 AC |
708 | /* Return the GDB type object for the "standard" data type of data in |
709 | register REG. */ | |
78fde5f8 KB |
710 | |
711 | static struct type * | |
a4b8ebc8 AC |
712 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
713 | { | |
5ef80fb0 | 714 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
715 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
716 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 717 | { |
5ef80fb0 | 718 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 719 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
5ef80fb0 AC |
720 | switch (gdbarch_byte_order (gdbarch)) |
721 | { | |
722 | case BFD_ENDIAN_BIG: | |
1b13c4f6 | 723 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
724 | return builtin_type_ieee_single_big; |
725 | else | |
726 | return builtin_type_ieee_double_big; | |
727 | case BFD_ENDIAN_LITTLE: | |
1b13c4f6 | 728 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
729 | return builtin_type_ieee_single_little; |
730 | else | |
731 | return builtin_type_ieee_double_little; | |
732 | case BFD_ENDIAN_UNKNOWN: | |
733 | default: | |
734 | internal_error (__FILE__, __LINE__, "bad switch"); | |
735 | } | |
a6425924 | 736 | } |
d5ac5a39 AC |
737 | else if (regnum < NUM_REGS) |
738 | { | |
739 | /* The raw or ISA registers. These are all sized according to | |
740 | the ISA regsize. */ | |
741 | if (mips_isa_regsize (gdbarch) == 4) | |
742 | return builtin_type_int32; | |
743 | else | |
744 | return builtin_type_int64; | |
745 | } | |
78fde5f8 | 746 | else |
d5ac5a39 AC |
747 | { |
748 | /* The cooked or ABI registers. These are sized according to | |
749 | the ABI (with a few complications). */ | |
750 | if (regnum >= (NUM_REGS | |
751 | + mips_regnum (current_gdbarch)->fp_control_status) | |
752 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) | |
753 | /* The pseudo/cooked view of the embedded registers is always | |
754 | 32-bit. The raw view is handled below. */ | |
755 | return builtin_type_int32; | |
756 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
757 | /* The target, while possibly using a 64-bit register buffer, | |
758 | is only transfering 32-bits of each integer register. | |
759 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
760 | return builtin_type_int32; | |
761 | else if (mips_abi_regsize (gdbarch) == 4) | |
762 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
763 | 32- or 64-bit). */ | |
764 | return builtin_type_int32; | |
765 | else | |
766 | /* 64-bit ABI. */ | |
767 | return builtin_type_int64; | |
768 | } | |
78fde5f8 KB |
769 | } |
770 | ||
bcb0cc15 MS |
771 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
772 | ||
773 | static CORE_ADDR | |
774 | mips_read_sp (void) | |
775 | { | |
f10683bb | 776 | return read_signed_register (MIPS_SP_REGNUM); |
bcb0cc15 MS |
777 | } |
778 | ||
c906108c | 779 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 780 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
781 | |
782 | static int | |
480d3dd2 | 783 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
784 | { |
785 | switch (mask_address_var) | |
786 | { | |
7f19b9a2 | 787 | case AUTO_BOOLEAN_TRUE: |
4014092b | 788 | return 1; |
7f19b9a2 | 789 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
790 | return 0; |
791 | break; | |
7f19b9a2 | 792 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 793 | return tdep->default_mask_address_p; |
4014092b | 794 | default: |
6d82d43b | 795 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 796 | return -1; |
361d1df0 | 797 | } |
4014092b AC |
798 | } |
799 | ||
800 | static void | |
e9e68a56 | 801 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 802 | { |
480d3dd2 | 803 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
804 | switch (mask_address_var) |
805 | { | |
7f19b9a2 | 806 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
807 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
808 | break; | |
7f19b9a2 | 809 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
810 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
811 | break; | |
7f19b9a2 | 812 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
813 | printf_filtered |
814 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
815 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
816 | break; |
817 | default: | |
6d82d43b | 818 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 819 | break; |
361d1df0 | 820 | } |
4014092b | 821 | } |
c906108c | 822 | |
c906108c SS |
823 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
824 | ||
825 | static int | |
826 | pc_is_mips16 (bfd_vma memaddr) | |
827 | { | |
828 | struct minimal_symbol *sym; | |
829 | ||
830 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 831 | if (is_mips16_addr (memaddr)) |
c906108c SS |
832 | return 1; |
833 | ||
834 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
835 | the high bit of the info field. Use this to decide if the function is | |
836 | MIPS16 or normal MIPS. */ | |
837 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
838 | if (sym) | |
71b8ef93 | 839 | return msymbol_is_special (sym); |
c906108c SS |
840 | else |
841 | return 0; | |
842 | } | |
843 | ||
b2fa5097 | 844 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
845 | all registers should be sign extended for simplicity? */ |
846 | ||
847 | static CORE_ADDR | |
39f77062 | 848 | mips_read_pc (ptid_t ptid) |
6c997a34 | 849 | { |
b6cb9035 AC |
850 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
851 | } | |
852 | ||
58dfe9ff AC |
853 | static CORE_ADDR |
854 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
855 | { | |
edfae063 AC |
856 | return frame_unwind_register_signed (next_frame, |
857 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
858 | } | |
859 | ||
860 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
861 | dummy frame. The frame ID's base needs to match the TOS value | |
862 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
863 | breakpoint. */ | |
864 | ||
865 | static struct frame_id | |
866 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
867 | { | |
f10683bb | 868 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM), |
edfae063 | 869 | frame_pc_unwind (next_frame)); |
58dfe9ff AC |
870 | } |
871 | ||
b6cb9035 AC |
872 | static void |
873 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
874 | { | |
875 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 876 | } |
c906108c SS |
877 | |
878 | /* This returns the PC of the first inst after the prologue. If we can't | |
879 | find the prologue, then return 0. */ | |
880 | ||
881 | static CORE_ADDR | |
177f84a3 | 882 | after_prologue (CORE_ADDR pc) |
c906108c | 883 | { |
177f84a3 | 884 | mips_extra_func_info_t proc_desc; |
c906108c SS |
885 | struct symtab_and_line sal; |
886 | CORE_ADDR func_addr, func_end; | |
283be873 AC |
887 | CORE_ADDR startaddr = 0; |
888 | ||
889 | /* Pass a NULL next_frame to heuristic_proc_desc. We should not | |
890 | attempt to read the stack pointer from the current machine state, | |
891 | because the current machine state has nothing to do with the | |
892 | information we need from the proc_desc; and the process may or | |
893 | may not exist right now. */ | |
894 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
895 | if (proc_desc) | |
896 | { | |
897 | /* IF this is the topmost frame AND (this proc does not have | |
898 | debugging information OR the PC is in the procedure prologue) | |
899 | THEN create a "heuristic" proc_desc (by analyzing the actual | |
900 | code) to replace the "official" proc_desc. */ | |
901 | struct symtab_and_line val; | |
fb603883 | 902 | if (PROC_SYMBOL (proc_desc)) |
283be873 AC |
903 | { |
904 | val = find_pc_line (BLOCK_START | |
fb603883 AC |
905 | (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc))), |
906 | 0); | |
283be873 AC |
907 | val.pc = val.end ? val.end : pc; |
908 | } | |
fb603883 | 909 | if (!PROC_SYMBOL (proc_desc) || pc < val.pc) |
283be873 AC |
910 | { |
911 | mips_extra_func_info_t found_heuristic = | |
c9343fd1 | 912 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), pc, NULL, NULL); |
283be873 AC |
913 | if (found_heuristic) |
914 | proc_desc = found_heuristic; | |
915 | } | |
916 | } | |
917 | else | |
918 | { | |
919 | if (startaddr == 0) | |
920 | startaddr = heuristic_proc_start (pc); | |
c906108c | 921 | |
c9343fd1 | 922 | proc_desc = heuristic_proc_desc (startaddr, pc, NULL, NULL); |
283be873 | 923 | } |
c906108c SS |
924 | |
925 | if (proc_desc) | |
926 | { | |
927 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 928 | strongly suspect that frameless always means prologueless... */ |
f10683bb | 929 | if (PROC_FRAME_REG (proc_desc) == MIPS_SP_REGNUM |
c906108c SS |
930 | && PROC_FRAME_OFFSET (proc_desc) == 0) |
931 | return 0; | |
932 | } | |
933 | ||
934 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
935 | return 0; /* Unknown */ | |
936 | ||
937 | sal = find_pc_line (func_addr, 0); | |
938 | ||
939 | if (sal.end < func_end) | |
940 | return sal.end; | |
941 | ||
942 | /* The line after the prologue is after the end of the function. In this | |
943 | case, tell the caller to find the prologue the hard way. */ | |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
c906108c SS |
948 | /* Fetch and return instruction from the specified location. If the PC |
949 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
950 | ||
951 | static t_inst | |
acdb74a0 | 952 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
953 | { |
954 | char buf[MIPS_INSTLEN]; | |
955 | int instlen; | |
956 | int status; | |
957 | ||
958 | if (pc_is_mips16 (addr)) | |
959 | { | |
960 | instlen = MIPS16_INSTLEN; | |
95404a3e | 961 | addr = unmake_mips16_addr (addr); |
c906108c SS |
962 | } |
963 | else | |
c5aa993b | 964 | instlen = MIPS_INSTLEN; |
1f602b35 | 965 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
966 | if (status) |
967 | memory_error (status, addr); | |
968 | return extract_unsigned_integer (buf, instlen); | |
969 | } | |
970 | ||
edfae063 AC |
971 | static ULONGEST |
972 | mips16_fetch_instruction (CORE_ADDR addr) | |
973 | { | |
974 | char buf[MIPS_INSTLEN]; | |
975 | int instlen; | |
976 | int status; | |
977 | ||
978 | instlen = MIPS16_INSTLEN; | |
979 | addr = unmake_mips16_addr (addr); | |
1f602b35 | 980 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
edfae063 AC |
981 | if (status) |
982 | memory_error (status, addr); | |
983 | return extract_unsigned_integer (buf, instlen); | |
984 | } | |
985 | ||
c906108c | 986 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
987 | #define mips32_op(x) (x >> 26) |
988 | #define itype_op(x) (x >> 26) | |
989 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 990 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 991 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 992 | |
e135b889 DJ |
993 | #define jtype_op(x) (x >> 26) |
994 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 995 | |
e135b889 DJ |
996 | #define rtype_op(x) (x >> 26) |
997 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
998 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
999 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1000 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1001 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
1002 | |
1003 | static CORE_ADDR | |
c5aa993b JM |
1004 | mips32_relative_offset (unsigned long inst) |
1005 | { | |
1006 | long x; | |
1007 | x = itype_immediate (inst); | |
1008 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 1009 | { |
c5aa993b | 1010 | x |= 0xffff0000; /* sign extension */ |
c906108c | 1011 | } |
c5aa993b JM |
1012 | x = x << 2; |
1013 | return x; | |
c906108c SS |
1014 | } |
1015 | ||
1016 | /* Determine whate to set a single step breakpoint while considering | |
1017 | branch prediction */ | |
5a89d8aa | 1018 | static CORE_ADDR |
c5aa993b JM |
1019 | mips32_next_pc (CORE_ADDR pc) |
1020 | { | |
1021 | unsigned long inst; | |
1022 | int op; | |
1023 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1024 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1025 | { |
e135b889 | 1026 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1027 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1028 | { |
e135b889 | 1029 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1030 | switch (op) |
1031 | { | |
e135b889 DJ |
1032 | case 0: /* BEQL */ |
1033 | goto equal_branch; | |
1034 | case 1: /* BNEL */ | |
1035 | goto neq_branch; | |
1036 | case 2: /* BLEZL */ | |
1037 | goto less_branch; | |
1038 | case 3: /* BGTZ */ | |
1039 | goto greater_branch; | |
c5aa993b JM |
1040 | default: |
1041 | pc += 4; | |
c906108c SS |
1042 | } |
1043 | } | |
e135b889 | 1044 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1045 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1046 | { |
1047 | int tf = itype_rt (inst) & 0x01; | |
1048 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1049 | int fcrcs = |
1050 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1051 | fp_control_status); | |
e135b889 DJ |
1052 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1053 | ||
1054 | if (((cond >> cnum) & 0x01) == tf) | |
1055 | pc += mips32_relative_offset (inst) + 4; | |
1056 | else | |
1057 | pc += 8; | |
1058 | } | |
c5aa993b JM |
1059 | else |
1060 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1061 | } |
1062 | else | |
c5aa993b JM |
1063 | { /* This gets way messy */ |
1064 | ||
c906108c | 1065 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1066 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1067 | { |
c5aa993b JM |
1068 | case 0: /* SPECIAL */ |
1069 | op = rtype_funct (inst); | |
1070 | switch (op) | |
1071 | { | |
1072 | case 8: /* JR */ | |
1073 | case 9: /* JALR */ | |
6c997a34 AC |
1074 | /* Set PC to that address */ |
1075 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1076 | break; |
1077 | default: | |
1078 | pc += 4; | |
1079 | } | |
1080 | ||
6d82d43b | 1081 | break; /* end SPECIAL */ |
c5aa993b | 1082 | case 1: /* REGIMM */ |
c906108c | 1083 | { |
e135b889 DJ |
1084 | op = itype_rt (inst); /* branch condition */ |
1085 | switch (op) | |
c906108c | 1086 | { |
c5aa993b | 1087 | case 0: /* BLTZ */ |
e135b889 DJ |
1088 | case 2: /* BLTZL */ |
1089 | case 16: /* BLTZAL */ | |
c5aa993b | 1090 | case 18: /* BLTZALL */ |
c906108c | 1091 | less_branch: |
6c997a34 | 1092 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1093 | pc += mips32_relative_offset (inst) + 4; |
1094 | else | |
1095 | pc += 8; /* after the delay slot */ | |
1096 | break; | |
e135b889 | 1097 | case 1: /* BGEZ */ |
c5aa993b JM |
1098 | case 3: /* BGEZL */ |
1099 | case 17: /* BGEZAL */ | |
1100 | case 19: /* BGEZALL */ | |
6c997a34 | 1101 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1102 | pc += mips32_relative_offset (inst) + 4; |
1103 | else | |
1104 | pc += 8; /* after the delay slot */ | |
1105 | break; | |
e135b889 | 1106 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1107 | default: |
1108 | pc += 4; | |
c906108c SS |
1109 | } |
1110 | } | |
6d82d43b | 1111 | break; /* end REGIMM */ |
c5aa993b JM |
1112 | case 2: /* J */ |
1113 | case 3: /* JAL */ | |
1114 | { | |
1115 | unsigned long reg; | |
1116 | reg = jtype_target (inst) << 2; | |
e135b889 | 1117 | /* Upper four bits get never changed... */ |
c5aa993b | 1118 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1119 | } |
c5aa993b JM |
1120 | break; |
1121 | /* FIXME case JALX : */ | |
1122 | { | |
1123 | unsigned long reg; | |
1124 | reg = jtype_target (inst) << 2; | |
1125 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1126 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1127 | } | |
c5aa993b | 1128 | break; /* The new PC will be alternate mode */ |
e135b889 | 1129 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1130 | equal_branch: |
6c997a34 AC |
1131 | if (read_signed_register (itype_rs (inst)) == |
1132 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1133 | pc += mips32_relative_offset (inst) + 4; |
1134 | else | |
1135 | pc += 8; | |
1136 | break; | |
e135b889 | 1137 | case 5: /* BNE, BNEL */ |
c5aa993b | 1138 | neq_branch: |
6c997a34 | 1139 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1140 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1141 | pc += mips32_relative_offset (inst) + 4; |
1142 | else | |
1143 | pc += 8; | |
1144 | break; | |
e135b889 | 1145 | case 6: /* BLEZ, BLEZL */ |
1fd8cd20 | 1146 | if (read_signed_register (itype_rs (inst)) <= 0) |
c5aa993b JM |
1147 | pc += mips32_relative_offset (inst) + 4; |
1148 | else | |
1149 | pc += 8; | |
1150 | break; | |
1151 | case 7: | |
e135b889 DJ |
1152 | default: |
1153 | greater_branch: /* BGTZ, BGTZL */ | |
1fd8cd20 | 1154 | if (read_signed_register (itype_rs (inst)) > 0) |
c5aa993b JM |
1155 | pc += mips32_relative_offset (inst) + 4; |
1156 | else | |
1157 | pc += 8; | |
1158 | break; | |
c5aa993b JM |
1159 | } /* switch */ |
1160 | } /* else */ | |
1161 | return pc; | |
1162 | } /* mips32_next_pc */ | |
c906108c SS |
1163 | |
1164 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1165 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1166 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1167 | We dont want to set a single step instruction on the extend instruction | |
1168 | either. | |
c5aa993b | 1169 | */ |
c906108c SS |
1170 | |
1171 | /* Lots of mips16 instruction formats */ | |
1172 | /* Predicting jumps requires itype,ritype,i8type | |
1173 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1174 | */ |
c906108c SS |
1175 | enum mips16_inst_fmts |
1176 | { | |
c5aa993b JM |
1177 | itype, /* 0 immediate 5,10 */ |
1178 | ritype, /* 1 5,3,8 */ | |
1179 | rrtype, /* 2 5,3,3,5 */ | |
1180 | rritype, /* 3 5,3,3,5 */ | |
1181 | rrrtype, /* 4 5,3,3,3,2 */ | |
1182 | rriatype, /* 5 5,3,3,1,4 */ | |
1183 | shifttype, /* 6 5,3,3,3,2 */ | |
1184 | i8type, /* 7 5,3,8 */ | |
1185 | i8movtype, /* 8 5,3,3,5 */ | |
1186 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1187 | i64type, /* 10 5,3,8 */ | |
1188 | ri64type, /* 11 5,3,3,5 */ | |
1189 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1190 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1191 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1192 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1193 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1194 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1195 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1196 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1197 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1198 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1199 | }; | |
12f02c2a AC |
1200 | /* I am heaping all the fields of the formats into one structure and |
1201 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1202 | struct upk_mips16 |
6d82d43b AC |
1203 | { |
1204 | CORE_ADDR offset; | |
1205 | unsigned int regx; /* Function in i8 type */ | |
1206 | unsigned int regy; | |
1207 | }; | |
c906108c SS |
1208 | |
1209 | ||
12f02c2a AC |
1210 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1211 | for the bits which make up the immediatate extension. */ | |
c906108c | 1212 | |
12f02c2a AC |
1213 | static CORE_ADDR |
1214 | extended_offset (unsigned int extension) | |
c906108c | 1215 | { |
12f02c2a | 1216 | CORE_ADDR value; |
c5aa993b JM |
1217 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1218 | value = value << 6; | |
1219 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1220 | value = value << 5; | |
1221 | value |= extension & 0x01f; /* extract 4:0 */ | |
1222 | return value; | |
c906108c SS |
1223 | } |
1224 | ||
1225 | /* Only call this function if you know that this is an extendable | |
1226 | instruction, It wont malfunction, but why make excess remote memory references? | |
1227 | If the immediate operands get sign extended or somthing, do it after | |
1228 | the extension is performed. | |
c5aa993b | 1229 | */ |
c906108c SS |
1230 | /* FIXME: Every one of these cases needs to worry about sign extension |
1231 | when the offset is to be used in relative addressing */ | |
1232 | ||
1233 | ||
12f02c2a | 1234 | static unsigned int |
c5aa993b | 1235 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1236 | { |
c5aa993b JM |
1237 | char buf[8]; |
1238 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1239 | target_read_memory (pc, buf, 2); | |
1240 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1241 | } |
1242 | ||
1243 | static void | |
c5aa993b | 1244 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1245 | unsigned int extension, |
1246 | unsigned int inst, | |
6d82d43b | 1247 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1248 | { |
12f02c2a AC |
1249 | CORE_ADDR offset; |
1250 | int regx; | |
1251 | int regy; | |
1252 | switch (insn_format) | |
c906108c | 1253 | { |
c5aa993b | 1254 | case itype: |
c906108c | 1255 | { |
12f02c2a AC |
1256 | CORE_ADDR value; |
1257 | if (extension) | |
c5aa993b JM |
1258 | { |
1259 | value = extended_offset (extension); | |
1260 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1261 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1262 | } |
1263 | else | |
c5aa993b | 1264 | { |
12f02c2a | 1265 | value = inst & 0x7ff; |
c5aa993b | 1266 | /* FIXME : Consider sign extension */ |
c906108c | 1267 | } |
12f02c2a AC |
1268 | offset = value; |
1269 | regx = -1; | |
1270 | regy = -1; | |
c906108c | 1271 | } |
c5aa993b JM |
1272 | break; |
1273 | case ritype: | |
1274 | case i8type: | |
1275 | { /* A register identifier and an offset */ | |
c906108c SS |
1276 | /* Most of the fields are the same as I type but the |
1277 | immediate value is of a different length */ | |
12f02c2a AC |
1278 | CORE_ADDR value; |
1279 | if (extension) | |
c906108c | 1280 | { |
c5aa993b JM |
1281 | value = extended_offset (extension); |
1282 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1283 | value |= inst & 0xff; /* eleven bits from instruction */ |
1284 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1285 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1286 | { | |
1287 | value &= ~0x3fff; /* remove the sign bit */ | |
1288 | value = -value; | |
c906108c SS |
1289 | } |
1290 | } | |
c5aa993b JM |
1291 | else |
1292 | { | |
12f02c2a AC |
1293 | value = inst & 0xff; /* 8 bits */ |
1294 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1295 | /* FIXME: Do sign extension , this format needs it */ |
1296 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1297 | { | |
1298 | value &= 0xef; /* remove the sign bit */ | |
1299 | value = -value; | |
1300 | } | |
c5aa993b | 1301 | } |
12f02c2a AC |
1302 | offset = value; |
1303 | regy = -1; | |
c5aa993b | 1304 | break; |
c906108c | 1305 | } |
c5aa993b | 1306 | case jalxtype: |
c906108c | 1307 | { |
c5aa993b | 1308 | unsigned long value; |
12f02c2a AC |
1309 | unsigned int nexthalf; |
1310 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1311 | value = value << 16; |
1312 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1313 | value |= nexthalf; | |
12f02c2a AC |
1314 | offset = value; |
1315 | regx = -1; | |
1316 | regy = -1; | |
c5aa993b | 1317 | break; |
c906108c SS |
1318 | } |
1319 | default: | |
6d82d43b | 1320 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1321 | } |
12f02c2a AC |
1322 | upk->offset = offset; |
1323 | upk->regx = regx; | |
1324 | upk->regy = regy; | |
c906108c SS |
1325 | } |
1326 | ||
1327 | ||
c5aa993b JM |
1328 | static CORE_ADDR |
1329 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1330 | { |
c5aa993b | 1331 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1332 | } |
1333 | ||
12f02c2a AC |
1334 | static CORE_ADDR |
1335 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1336 | unsigned int extension, unsigned int insn) |
c906108c | 1337 | { |
12f02c2a AC |
1338 | int op = (insn >> 11); |
1339 | switch (op) | |
c906108c | 1340 | { |
6d82d43b | 1341 | case 2: /* Branch */ |
12f02c2a AC |
1342 | { |
1343 | CORE_ADDR offset; | |
1344 | struct upk_mips16 upk; | |
1345 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1346 | offset = upk.offset; | |
1347 | if (offset & 0x800) | |
1348 | { | |
1349 | offset &= 0xeff; | |
1350 | offset = -offset; | |
1351 | } | |
1352 | pc += (offset << 1) + 2; | |
1353 | break; | |
1354 | } | |
6d82d43b | 1355 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1356 | { |
1357 | struct upk_mips16 upk; | |
1358 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1359 | pc = add_offset_16 (pc, upk.offset); | |
1360 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1361 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1362 | else | |
1363 | pc |= 0x01; | |
1364 | break; | |
1365 | } | |
6d82d43b | 1366 | case 4: /* beqz */ |
12f02c2a AC |
1367 | { |
1368 | struct upk_mips16 upk; | |
1369 | int reg; | |
1370 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1371 | reg = read_signed_register (upk.regx); | |
1372 | if (reg == 0) | |
1373 | pc += (upk.offset << 1) + 2; | |
1374 | else | |
1375 | pc += 2; | |
1376 | break; | |
1377 | } | |
6d82d43b | 1378 | case 5: /* bnez */ |
12f02c2a AC |
1379 | { |
1380 | struct upk_mips16 upk; | |
1381 | int reg; | |
1382 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1383 | reg = read_signed_register (upk.regx); | |
1384 | if (reg != 0) | |
1385 | pc += (upk.offset << 1) + 2; | |
1386 | else | |
1387 | pc += 2; | |
1388 | break; | |
1389 | } | |
6d82d43b | 1390 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1391 | { |
1392 | struct upk_mips16 upk; | |
1393 | int reg; | |
1394 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1395 | /* upk.regx contains the opcode */ | |
1396 | reg = read_signed_register (24); /* Test register is 24 */ | |
1397 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1398 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1399 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1400 | pc += (upk.offset << 1) + 2; | |
1401 | else | |
1402 | pc += 2; | |
1403 | break; | |
1404 | } | |
6d82d43b | 1405 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1406 | { |
1407 | struct upk_mips16 upk; | |
1408 | /* upk.fmt = rrtype; */ | |
1409 | op = insn & 0x1f; | |
1410 | if (op == 0) | |
c5aa993b | 1411 | { |
12f02c2a AC |
1412 | int reg; |
1413 | upk.regx = (insn >> 8) & 0x07; | |
1414 | upk.regy = (insn >> 5) & 0x07; | |
1415 | switch (upk.regy) | |
c5aa993b | 1416 | { |
12f02c2a AC |
1417 | case 0: |
1418 | reg = upk.regx; | |
1419 | break; | |
1420 | case 1: | |
1421 | reg = 31; | |
6d82d43b | 1422 | break; /* Function return instruction */ |
12f02c2a AC |
1423 | case 2: |
1424 | reg = upk.regx; | |
1425 | break; | |
1426 | default: | |
1427 | reg = 31; | |
6d82d43b | 1428 | break; /* BOGUS Guess */ |
c906108c | 1429 | } |
12f02c2a | 1430 | pc = read_signed_register (reg); |
c906108c | 1431 | } |
12f02c2a | 1432 | else |
c5aa993b | 1433 | pc += 2; |
12f02c2a AC |
1434 | break; |
1435 | } | |
1436 | case 30: | |
1437 | /* This is an instruction extension. Fetch the real instruction | |
1438 | (which follows the extension) and decode things based on | |
1439 | that. */ | |
1440 | { | |
1441 | pc += 2; | |
1442 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1443 | break; | |
1444 | } | |
1445 | default: | |
1446 | { | |
1447 | pc += 2; | |
1448 | break; | |
1449 | } | |
c906108c | 1450 | } |
c5aa993b | 1451 | return pc; |
12f02c2a | 1452 | } |
c906108c | 1453 | |
5a89d8aa | 1454 | static CORE_ADDR |
12f02c2a AC |
1455 | mips16_next_pc (CORE_ADDR pc) |
1456 | { | |
1457 | unsigned int insn = fetch_mips_16 (pc); | |
1458 | return extended_mips16_next_pc (pc, 0, insn); | |
1459 | } | |
1460 | ||
1461 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1462 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1463 | It works by decoding the current instruction and predicting where a |
1464 | branch will go. This isnt hard because all the data is available. | |
1465 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1466 | CORE_ADDR |
1467 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1468 | { |
c5aa993b JM |
1469 | if (pc & 0x01) |
1470 | return mips16_next_pc (pc); | |
1471 | else | |
1472 | return mips32_next_pc (pc); | |
12f02c2a | 1473 | } |
c906108c | 1474 | |
edfae063 AC |
1475 | struct mips_frame_cache |
1476 | { | |
1477 | CORE_ADDR base; | |
1478 | struct trad_frame_saved_reg *saved_regs; | |
1479 | }; | |
1480 | ||
1481 | ||
1482 | static struct mips_frame_cache * | |
1483 | mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1484 | { | |
0d5febcc | 1485 | CORE_ADDR startaddr = 0; |
edfae063 AC |
1486 | mips_extra_func_info_t proc_desc; |
1487 | struct mips_frame_cache *cache; | |
1488 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1489 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1490 | /* r0 bit means kernel trap */ | |
1491 | int kernel_trap; | |
1492 | /* What registers have been saved? Bitmasks. */ | |
1493 | unsigned long gen_mask, float_mask; | |
1494 | ||
1495 | if ((*this_cache) != NULL) | |
1496 | return (*this_cache); | |
1497 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1498 | (*this_cache) = cache; | |
1499 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1500 | ||
1501 | /* Get the mdebug proc descriptor. */ | |
0d5febcc AC |
1502 | proc_desc = non_heuristic_proc_desc (frame_pc_unwind (next_frame), |
1503 | &startaddr); | |
1504 | /* Must be true. This is only called when the sniffer detected a | |
1505 | proc descriptor. */ | |
1506 | gdb_assert (proc_desc != NULL); | |
edfae063 AC |
1507 | |
1508 | /* Extract the frame's base. */ | |
1509 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1510 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1511 | ||
1512 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1513 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1514 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1515 | ||
9733cfe1 AC |
1516 | /* Must be true. The in_prologue case is left for the heuristic |
1517 | unwinder. This is always used on kernel traps. */ | |
1518 | gdb_assert (!in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1519 | || kernel_trap); | |
edfae063 AC |
1520 | |
1521 | /* Fill in the offsets for the registers which gen_mask says were | |
1522 | saved. */ | |
1523 | { | |
4fbbbd07 | 1524 | CORE_ADDR reg_position = (cache->base + PROC_REG_OFFSET (proc_desc)); |
edfae063 | 1525 | int ireg; |
4fbbbd07 | 1526 | |
edfae063 AC |
1527 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
1528 | if (gen_mask & 0x80000000) | |
1529 | { | |
1530 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
13326b4e | 1531 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1532 | } |
1533 | } | |
1534 | ||
1535 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1536 | order of that normally used by gcc. Therefore, we have to fetch | |
1537 | the first instruction of the function, and if it's an entry | |
1538 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
1539 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1540 | { | |
1541 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1542 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1543 | /* entry */ | |
1544 | { | |
1545 | int reg; | |
1546 | int sreg_count = (inst >> 6) & 3; | |
1547 | ||
1548 | /* Check if the ra register was pushed on the stack. */ | |
1549 | CORE_ADDR reg_position = (cache->base | |
1550 | + PROC_REG_OFFSET (proc_desc)); | |
1551 | if (inst & 0x20) | |
13326b4e | 1552 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1553 | |
1554 | /* Check if the s0 and s1 registers were pushed on the | |
1555 | stack. */ | |
1556 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1557 | check. */ | |
1558 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1559 | { | |
1560 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
13326b4e | 1561 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1562 | } |
1563 | } | |
1564 | } | |
1565 | ||
1566 | /* Fill in the offsets for the registers which float_mask says were | |
1567 | saved. */ | |
1568 | { | |
1569 | CORE_ADDR reg_position = (cache->base | |
1570 | + PROC_FREG_OFFSET (proc_desc)); | |
1571 | int ireg; | |
1572 | /* Fill in the offsets for the float registers which float_mask | |
1573 | says were saved. */ | |
1574 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1575 | if (float_mask & 0x80000000) | |
1576 | { | |
13326b4e | 1577 | if (mips_abi_regsize (gdbarch) == 4 |
edfae063 AC |
1578 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1579 | { | |
1580 | /* On a big endian 32 bit ABI, floating point registers | |
1581 | are paired to form doubles such that the most | |
1582 | significant part is in $f[N+1] and the least | |
1583 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1584 | registers are also spilled as a pair and stored as a | |
1585 | double. | |
1586 | ||
1587 | When little-endian the least significant part is | |
1588 | stored first leading to the memory order $f[N] and | |
1589 | then $f[N+1]. | |
1590 | ||
1591 | Unfortunately, when big-endian the most significant | |
1592 | part of the double is stored first, and the least | |
1593 | significant is stored second. This leads to the | |
1594 | registers being ordered in memory as firt $f[N+1] and | |
1595 | then $f[N]. | |
1596 | ||
1597 | For the big-endian case make certain that the | |
1598 | addresses point at the correct (swapped) locations | |
1599 | $f[N] and $f[N+1] pair (keep in mind that | |
1600 | reg_position is decremented each time through the | |
1601 | loop). */ | |
1602 | if ((ireg & 1)) | |
1603 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1604 | .addr = reg_position - mips_abi_regsize (gdbarch); |
edfae063 AC |
1605 | else |
1606 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1607 | .addr = reg_position + mips_abi_regsize (gdbarch); |
edfae063 AC |
1608 | } |
1609 | else | |
1610 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1611 | .addr = reg_position; | |
13326b4e | 1612 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1613 | } |
1614 | ||
1615 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
1616 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
1617 | } | |
1618 | ||
1619 | /* SP_REGNUM, contains the value and not the address. */ | |
f10683bb | 1620 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); |
edfae063 AC |
1621 | |
1622 | return (*this_cache); | |
1623 | } | |
1624 | ||
1625 | static void | |
1626 | mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1627 | struct frame_id *this_id) | |
1628 | { | |
1629 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1630 | this_cache); | |
1631 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1632 | } | |
1633 | ||
1634 | static void | |
1635 | mips_mdebug_frame_prev_register (struct frame_info *next_frame, | |
1636 | void **this_cache, | |
1637 | int regnum, int *optimizedp, | |
1638 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1639 | int *realnump, void *valuep) | |
1640 | { | |
1641 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1642 | this_cache); | |
1f67027d AC |
1643 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
1644 | optimizedp, lvalp, addrp, realnump, valuep); | |
edfae063 AC |
1645 | } |
1646 | ||
1647 | static const struct frame_unwind mips_mdebug_frame_unwind = | |
1648 | { | |
1649 | NORMAL_FRAME, | |
1650 | mips_mdebug_frame_this_id, | |
1651 | mips_mdebug_frame_prev_register | |
1652 | }; | |
1653 | ||
1654 | static const struct frame_unwind * | |
1655 | mips_mdebug_frame_sniffer (struct frame_info *next_frame) | |
1656 | { | |
eec63939 AC |
1657 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1658 | CORE_ADDR startaddr = 0; | |
1659 | mips_extra_func_info_t proc_desc; | |
1660 | int kernel_trap; | |
1661 | ||
1662 | /* Only use the mdebug frame unwinder on mdebug frames where all the | |
1663 | registers have been saved. Leave hard cases such as no mdebug or | |
1664 | in prologue for the heuristic unwinders. */ | |
1665 | ||
1666 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1667 | if (proc_desc == NULL) | |
1668 | return NULL; | |
1669 | ||
1670 | /* Not sure exactly what kernel_trap means, but if it means the | |
1671 | kernel saves the registers without a prologue doing it, we better | |
1672 | not examine the prologue to see whether registers have been saved | |
1673 | yet. */ | |
1674 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1675 | if (kernel_trap) | |
1676 | return &mips_mdebug_frame_unwind; | |
1677 | ||
1678 | /* In any frame other than the innermost or a frame interrupted by a | |
1679 | signal, we assume that all registers have been saved. This | |
1680 | assumes that all register saves in a function happen before the | |
1681 | first function call. */ | |
1682 | if (!in_prologue (pc, PROC_LOW_ADDR (proc_desc))) | |
1683 | return &mips_mdebug_frame_unwind; | |
1684 | ||
1685 | return NULL; | |
edfae063 AC |
1686 | } |
1687 | ||
1688 | static CORE_ADDR | |
1689 | mips_mdebug_frame_base_address (struct frame_info *next_frame, | |
1690 | void **this_cache) | |
1691 | { | |
1692 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1693 | this_cache); | |
1694 | return info->base; | |
1695 | } | |
1696 | ||
1697 | static const struct frame_base mips_mdebug_frame_base = { | |
1698 | &mips_mdebug_frame_unwind, | |
1699 | mips_mdebug_frame_base_address, | |
1700 | mips_mdebug_frame_base_address, | |
1701 | mips_mdebug_frame_base_address | |
1702 | }; | |
1703 | ||
1704 | static const struct frame_base * | |
1705 | mips_mdebug_frame_base_sniffer (struct frame_info *next_frame) | |
1706 | { | |
eec63939 AC |
1707 | if (mips_mdebug_frame_sniffer (next_frame) != NULL) |
1708 | return &mips_mdebug_frame_base; | |
1709 | else | |
1710 | return NULL; | |
1711 | } | |
1712 | ||
45c9dd44 AC |
1713 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1714 | Procedures that use the 32-bit instruction set are handled by the | |
1715 | mips_insn32 unwinder. */ | |
1716 | ||
eec63939 | 1717 | static struct mips_frame_cache * |
45c9dd44 | 1718 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) |
eec63939 | 1719 | { |
eec63939 | 1720 | struct mips_frame_cache *cache; |
eec63939 AC |
1721 | |
1722 | if ((*this_cache) != NULL) | |
1723 | return (*this_cache); | |
1724 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1725 | (*this_cache) = cache; | |
1726 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1727 | ||
c68a4142 | 1728 | /* Analyze the function prologue. */ |
0d5febcc AC |
1729 | { |
1730 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1731 | CORE_ADDR start_addr; | |
eec63939 | 1732 | |
0d5febcc AC |
1733 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1734 | if (start_addr == 0) | |
1735 | start_addr = heuristic_proc_start (pc); | |
c68a4142 JB |
1736 | /* We can't analyze the prologue if we couldn't find the begining |
1737 | of the function. */ | |
1738 | if (start_addr == 0) | |
1739 | return cache; | |
0d5febcc | 1740 | |
c68a4142 | 1741 | heuristic_proc_desc (start_addr, pc, next_frame, *this_cache); |
0d5febcc AC |
1742 | } |
1743 | ||
eec63939 AC |
1744 | /* SP_REGNUM, contains the value and not the address. */ |
1745 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
1746 | ||
1747 | return (*this_cache); | |
1748 | } | |
1749 | ||
1750 | static void | |
45c9dd44 | 1751 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
eec63939 AC |
1752 | struct frame_id *this_id) |
1753 | { | |
45c9dd44 | 1754 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
1755 | this_cache); |
1756 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1757 | } | |
1758 | ||
1759 | static void | |
45c9dd44 | 1760 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1761 | void **this_cache, |
1762 | int regnum, int *optimizedp, | |
1763 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1764 | int *realnump, void *valuep) | |
1765 | { | |
45c9dd44 | 1766 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
1767 | this_cache); |
1768 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1769 | optimizedp, lvalp, addrp, realnump, valuep); | |
1770 | } | |
1771 | ||
45c9dd44 | 1772 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1773 | { |
1774 | NORMAL_FRAME, | |
45c9dd44 AC |
1775 | mips_insn16_frame_this_id, |
1776 | mips_insn16_frame_prev_register | |
eec63939 AC |
1777 | }; |
1778 | ||
1779 | static const struct frame_unwind * | |
45c9dd44 | 1780 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
1781 | { |
1782 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1783 | if (pc_is_mips16 (pc)) | |
45c9dd44 | 1784 | return &mips_insn16_frame_unwind; |
eec63939 AC |
1785 | return NULL; |
1786 | } | |
1787 | ||
1788 | static CORE_ADDR | |
45c9dd44 | 1789 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
eec63939 AC |
1790 | void **this_cache) |
1791 | { | |
45c9dd44 | 1792 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
1793 | this_cache); |
1794 | return info->base; | |
1795 | } | |
1796 | ||
45c9dd44 | 1797 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1798 | { |
45c9dd44 AC |
1799 | &mips_insn16_frame_unwind, |
1800 | mips_insn16_frame_base_address, | |
1801 | mips_insn16_frame_base_address, | |
1802 | mips_insn16_frame_base_address | |
eec63939 AC |
1803 | }; |
1804 | ||
1805 | static const struct frame_base * | |
45c9dd44 | 1806 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1807 | { |
45c9dd44 AC |
1808 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1809 | return &mips_insn16_frame_base; | |
eec63939 AC |
1810 | else |
1811 | return NULL; | |
1812 | } | |
1813 | ||
45c9dd44 AC |
1814 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
1815 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
1816 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
1817 | unwinder. */ | |
1818 | ||
eec63939 | 1819 | static struct mips_frame_cache * |
45c9dd44 | 1820 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) |
eec63939 | 1821 | { |
eec63939 | 1822 | struct mips_frame_cache *cache; |
eec63939 AC |
1823 | |
1824 | if ((*this_cache) != NULL) | |
1825 | return (*this_cache); | |
65596487 | 1826 | |
eec63939 AC |
1827 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1828 | (*this_cache) = cache; | |
1829 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1830 | ||
c68a4142 | 1831 | /* Analyze the function prologue. */ |
a343eb3c JB |
1832 | { |
1833 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1834 | CORE_ADDR start_addr; | |
1835 | ||
1836 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
1837 | if (start_addr == 0) | |
1838 | start_addr = heuristic_proc_start (pc); | |
c68a4142 JB |
1839 | /* We can't analyze the prologue if we couldn't find the begining |
1840 | of the function. */ | |
1841 | if (start_addr == 0) | |
1842 | return cache; | |
a343eb3c | 1843 | |
c68a4142 | 1844 | heuristic_proc_desc (start_addr, pc, next_frame, *this_cache); |
a343eb3c JB |
1845 | } |
1846 | ||
eec63939 AC |
1847 | /* SP_REGNUM, contains the value and not the address. */ |
1848 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
1849 | ||
1850 | return (*this_cache); | |
1851 | } | |
1852 | ||
1853 | static void | |
45c9dd44 | 1854 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, |
eec63939 AC |
1855 | struct frame_id *this_id) |
1856 | { | |
45c9dd44 | 1857 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
1858 | this_cache); |
1859 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1860 | } | |
1861 | ||
1862 | static void | |
45c9dd44 | 1863 | mips_insn32_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1864 | void **this_cache, |
1865 | int regnum, int *optimizedp, | |
1866 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1867 | int *realnump, void *valuep) | |
1868 | { | |
45c9dd44 | 1869 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
1870 | this_cache); |
1871 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1872 | optimizedp, lvalp, addrp, realnump, valuep); | |
1873 | } | |
1874 | ||
45c9dd44 | 1875 | static const struct frame_unwind mips_insn32_frame_unwind = |
eec63939 AC |
1876 | { |
1877 | NORMAL_FRAME, | |
45c9dd44 AC |
1878 | mips_insn32_frame_this_id, |
1879 | mips_insn32_frame_prev_register | |
eec63939 AC |
1880 | }; |
1881 | ||
1882 | static const struct frame_unwind * | |
45c9dd44 | 1883 | mips_insn32_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
1884 | { |
1885 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1886 | if (! pc_is_mips16 (pc)) | |
45c9dd44 | 1887 | return &mips_insn32_frame_unwind; |
eec63939 AC |
1888 | return NULL; |
1889 | } | |
1890 | ||
1891 | static CORE_ADDR | |
45c9dd44 | 1892 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
eec63939 AC |
1893 | void **this_cache) |
1894 | { | |
45c9dd44 | 1895 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
1896 | this_cache); |
1897 | return info->base; | |
1898 | } | |
1899 | ||
45c9dd44 | 1900 | static const struct frame_base mips_insn32_frame_base = |
eec63939 | 1901 | { |
45c9dd44 AC |
1902 | &mips_insn32_frame_unwind, |
1903 | mips_insn32_frame_base_address, | |
1904 | mips_insn32_frame_base_address, | |
1905 | mips_insn32_frame_base_address | |
eec63939 AC |
1906 | }; |
1907 | ||
1908 | static const struct frame_base * | |
45c9dd44 | 1909 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1910 | { |
45c9dd44 AC |
1911 | if (mips_insn32_frame_sniffer (next_frame) != NULL) |
1912 | return &mips_insn32_frame_base; | |
eec63939 AC |
1913 | else |
1914 | return NULL; | |
1915 | } | |
1916 | ||
1917 | static struct trad_frame_cache * | |
1918 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1919 | { | |
1920 | CORE_ADDR pc; | |
1921 | CORE_ADDR start_addr; | |
1922 | CORE_ADDR stack_addr; | |
1923 | struct trad_frame_cache *this_trad_cache; | |
1924 | ||
1925 | if ((*this_cache) != NULL) | |
1926 | return (*this_cache); | |
1927 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
1928 | (*this_cache) = this_trad_cache; | |
1929 | ||
1930 | /* The return address is in the link register. */ | |
1931 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, RA_REGNUM); | |
1932 | ||
1933 | /* Frame ID, since it's a frameless / stackless function, no stack | |
1934 | space is allocated and SP on entry is the current SP. */ | |
1935 | pc = frame_pc_unwind (next_frame); | |
1936 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
1937 | stack_addr = frame_unwind_register_signed (next_frame, SP_REGNUM); | |
1938 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); | |
1939 | ||
1940 | /* Assume that the frame's base is the same as the | |
1941 | stack-pointer. */ | |
1942 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
1943 | ||
1944 | return this_trad_cache; | |
1945 | } | |
1946 | ||
1947 | static void | |
1948 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1949 | struct frame_id *this_id) | |
1950 | { | |
1951 | struct trad_frame_cache *this_trad_cache | |
1952 | = mips_stub_frame_cache (next_frame, this_cache); | |
1953 | trad_frame_get_id (this_trad_cache, this_id); | |
1954 | } | |
1955 | ||
1956 | static void | |
1957 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
1958 | void **this_cache, | |
1959 | int regnum, int *optimizedp, | |
1960 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1961 | int *realnump, void *valuep) | |
1962 | { | |
1963 | struct trad_frame_cache *this_trad_cache | |
1964 | = mips_stub_frame_cache (next_frame, this_cache); | |
1965 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
1966 | lvalp, addrp, realnump, valuep); | |
1967 | } | |
1968 | ||
1969 | static const struct frame_unwind mips_stub_frame_unwind = | |
1970 | { | |
1971 | NORMAL_FRAME, | |
1972 | mips_stub_frame_this_id, | |
1973 | mips_stub_frame_prev_register | |
1974 | }; | |
1975 | ||
1976 | static const struct frame_unwind * | |
1977 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
1978 | { | |
1979 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1980 | if (in_plt_section (pc, NULL)) | |
1981 | return &mips_stub_frame_unwind; | |
1982 | else | |
1983 | return NULL; | |
1984 | } | |
1985 | ||
1986 | static CORE_ADDR | |
1987 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
1988 | void **this_cache) | |
1989 | { | |
1990 | struct trad_frame_cache *this_trad_cache | |
1991 | = mips_stub_frame_cache (next_frame, this_cache); | |
1992 | return trad_frame_get_this_base (this_trad_cache); | |
1993 | } | |
1994 | ||
1995 | static const struct frame_base mips_stub_frame_base = | |
1996 | { | |
1997 | &mips_stub_frame_unwind, | |
1998 | mips_stub_frame_base_address, | |
1999 | mips_stub_frame_base_address, | |
2000 | mips_stub_frame_base_address | |
2001 | }; | |
2002 | ||
2003 | static const struct frame_base * | |
2004 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2005 | { | |
2006 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2007 | return &mips_stub_frame_base; | |
2008 | else | |
2009 | return NULL; | |
edfae063 AC |
2010 | } |
2011 | ||
c906108c | 2012 | static CORE_ADDR |
acdb74a0 | 2013 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 2014 | { |
a4b8ebc8 AC |
2015 | /* Always a pseudo. */ |
2016 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 2017 | if (fi == NULL) |
c906108c | 2018 | { |
a4b8ebc8 AC |
2019 | LONGEST val; |
2020 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2021 | return val; | |
f796e4be KB |
2022 | } |
2023 | else | |
a4b8ebc8 | 2024 | return frame_unwind_register_signed (fi, regno); |
64159455 | 2025 | |
c906108c SS |
2026 | } |
2027 | ||
2028 | /* mips_addr_bits_remove - remove useless address bits */ | |
2029 | ||
875e1767 | 2030 | static CORE_ADDR |
acdb74a0 | 2031 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 2032 | { |
480d3dd2 | 2033 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
6d82d43b | 2034 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
8fa9cfa1 AC |
2035 | /* This hack is a work-around for existing boards using PMON, the |
2036 | simulator, and any other 64-bit targets that doesn't have true | |
2037 | 64-bit addressing. On these targets, the upper 32 bits of | |
2038 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2039 | likely to have been sign extended to all 1s by instruction | |
2040 | sequences that load 32-bit addresses. For example, a typical | |
2041 | piece of code that loads an address is this: | |
2042 | ||
2043 | lui $r2, <upper 16 bits> | |
2044 | ori $r2, <lower 16 bits> | |
2045 | ||
2046 | But the lui sign-extends the value such that the upper 32 bits | |
2047 | may be all 1s. The workaround is simply to mask off these | |
2048 | bits. In the future, gcc may be changed to support true 64-bit | |
2049 | addressing, and this masking will have to be disabled. */ | |
2050 | return addr &= 0xffffffffUL; | |
2051 | else | |
2052 | return addr; | |
c906108c SS |
2053 | } |
2054 | ||
9022177c DJ |
2055 | /* mips_software_single_step() is called just before we want to resume |
2056 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 2057 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
2058 | the target of the coming instruction and breakpoint it. |
2059 | ||
2060 | single_step is also called just after the inferior stops. If we had | |
2061 | set up a simulated single-step, we undo our damage. */ | |
2062 | ||
2063 | void | |
2064 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
2065 | { | |
2066 | static CORE_ADDR next_pc; | |
2067 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
2068 | static binsn_quantum break_mem; | |
2069 | CORE_ADDR pc; | |
2070 | ||
2071 | if (insert_breakpoints_p) | |
2072 | { | |
b6cb9035 | 2073 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
9022177c DJ |
2074 | next_pc = mips_next_pc (pc); |
2075 | ||
2076 | target_insert_breakpoint (next_pc, break_mem); | |
2077 | } | |
2078 | else | |
2079 | target_remove_breakpoint (next_pc, break_mem); | |
2080 | } | |
2081 | ||
c906108c | 2082 | static struct mips_extra_func_info temp_proc_desc; |
fe29b929 | 2083 | |
e0f7ec59 AC |
2084 | /* Set a register's saved stack address in temp_saved_regs. If an |
2085 | address has already been set for this register, do nothing; this | |
2086 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
2087 | function prologue. |
2088 | ||
2089 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
2090 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
2091 | is used as it is only second range (the ABI instead of ISA | |
2092 | registers) that comes into play when finding saved registers in a | |
2093 | frame. */ | |
c906108c SS |
2094 | |
2095 | static void | |
c9343fd1 AC |
2096 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
2097 | CORE_ADDR offset) | |
c906108c | 2098 | { |
c9343fd1 | 2099 | if (this_cache != NULL |
65596487 | 2100 | && this_cache->saved_regs[regnum].addr == -1) |
a4b8ebc8 | 2101 | { |
c9343fd1 AC |
2102 | this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset; |
2103 | this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset; | |
a4b8ebc8 | 2104 | } |
c906108c SS |
2105 | } |
2106 | ||
2107 | ||
2108 | /* Test whether the PC points to the return instruction at the | |
2109 | end of a function. */ | |
2110 | ||
c5aa993b | 2111 | static int |
acdb74a0 | 2112 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
2113 | { |
2114 | if (pc_is_mips16 (pc)) | |
2115 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
2116 | generates a "jr $ra"; other times it generates code to load | |
2117 | the return address from the stack to an accessible register (such | |
2118 | as $a3), then a "jr" using that register. This second case | |
2119 | is almost impossible to distinguish from an indirect jump | |
2120 | used for switch statements, so we don't even try. */ | |
2121 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2122 | else | |
2123 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2124 | } | |
2125 | ||
2126 | ||
2127 | /* This fencepost looks highly suspicious to me. Removing it also | |
2128 | seems suspicious as it could affect remote debugging across serial | |
2129 | lines. */ | |
2130 | ||
2131 | static CORE_ADDR | |
acdb74a0 | 2132 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 2133 | { |
c5aa993b JM |
2134 | CORE_ADDR start_pc; |
2135 | CORE_ADDR fence; | |
2136 | int instlen; | |
2137 | int seen_adjsp = 0; | |
c906108c | 2138 | |
c5aa993b JM |
2139 | pc = ADDR_BITS_REMOVE (pc); |
2140 | start_pc = pc; | |
2141 | fence = start_pc - heuristic_fence_post; | |
2142 | if (start_pc == 0) | |
2143 | return 0; | |
c906108c | 2144 | |
6d82d43b | 2145 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
c5aa993b | 2146 | fence = VM_MIN_ADDRESS; |
c906108c | 2147 | |
c5aa993b | 2148 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 2149 | |
c5aa993b JM |
2150 | /* search back for previous return */ |
2151 | for (start_pc -= instlen;; start_pc -= instlen) | |
2152 | if (start_pc < fence) | |
2153 | { | |
2154 | /* It's not clear to me why we reach this point when | |
c0236d92 | 2155 | stop_soon, but with this test, at least we |
c5aa993b JM |
2156 | don't print out warnings for every child forked (eg, on |
2157 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 2158 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 2159 | { |
c5aa993b JM |
2160 | static int blurb_printed = 0; |
2161 | ||
dc305454 MS |
2162 | warning ("GDB can't find the start of the function at 0x%s.", |
2163 | paddr_nz (pc)); | |
c5aa993b JM |
2164 | |
2165 | if (!blurb_printed) | |
c906108c | 2166 | { |
c5aa993b JM |
2167 | /* This actually happens frequently in embedded |
2168 | development, when you first connect to a board | |
2169 | and your stack pointer and pc are nowhere in | |
2170 | particular. This message needs to give people | |
2171 | in that situation enough information to | |
2172 | determine that it's no big deal. */ | |
2173 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
2174 | GDB is unable to find the start of the function at 0x%s\n\ |
2175 | and thus can't determine the size of that function's stack frame.\n\ | |
2176 | This means that GDB may be unable to access that stack frame, or\n\ | |
2177 | the frames below it.\n\ | |
2178 | This problem is most likely caused by an invalid program counter or\n\ | |
2179 | stack pointer.\n\ | |
2180 | However, if you think GDB should simply search farther back\n\ | |
2181 | from 0x%s for code which looks like the beginning of a\n\ | |
2182 | function, you can increase the range of the search using the `set\n\ | |
6d82d43b | 2183 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); |
c5aa993b | 2184 | blurb_printed = 1; |
c906108c | 2185 | } |
c906108c SS |
2186 | } |
2187 | ||
c5aa993b JM |
2188 | return 0; |
2189 | } | |
2190 | else if (pc_is_mips16 (start_pc)) | |
2191 | { | |
2192 | unsigned short inst; | |
2193 | ||
2194 | /* On MIPS16, any one of the following is likely to be the | |
2195 | start of a function: | |
2196 | entry | |
2197 | addiu sp,-n | |
2198 | daddiu sp,-n | |
2199 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2200 | inst = mips_fetch_instruction (start_pc); | |
2201 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2202 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2203 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2204 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2205 | break; | |
2206 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2207 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2208 | seen_adjsp = 1; | |
2209 | else | |
2210 | seen_adjsp = 0; | |
2211 | } | |
2212 | else if (mips_about_to_return (start_pc)) | |
2213 | { | |
2214 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
2215 | break; | |
2216 | } | |
2217 | ||
c5aa993b | 2218 | return start_pc; |
c906108c SS |
2219 | } |
2220 | ||
2221 | /* Fetch the immediate value from a MIPS16 instruction. | |
2222 | If the previous instruction was an EXTEND, use it to extend | |
2223 | the upper bits of the immediate value. This is a helper function | |
1e05a7bf | 2224 | for mips16_scan_prologue. */ |
c906108c SS |
2225 | |
2226 | static int | |
acdb74a0 AC |
2227 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
2228 | unsigned short inst, /* current instruction */ | |
6d82d43b AC |
2229 | int nbits, /* number of bits in imm field */ |
2230 | int scale, /* scale factor to be applied to imm */ | |
2231 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
2232 | { |
2233 | int offset; | |
2234 | ||
2235 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
2236 | { | |
2237 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 2238 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
2239 | offset = 0 - (0x10000 - (offset & 0xffff)); |
2240 | return offset | (inst & 0x1f); | |
2241 | } | |
2242 | else | |
2243 | { | |
2244 | int max_imm = 1 << nbits; | |
2245 | int mask = max_imm - 1; | |
2246 | int sign_bit = max_imm >> 1; | |
2247 | ||
2248 | offset = inst & mask; | |
2249 | if (is_signed && (offset & sign_bit)) | |
2250 | offset = 0 - (max_imm - offset); | |
2251 | return offset * scale; | |
2252 | } | |
2253 | } | |
2254 | ||
2255 | ||
1e05a7bf JB |
2256 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2257 | the associated FRAME_CACHE if not null. */ | |
c906108c SS |
2258 | |
2259 | static void | |
1e05a7bf JB |
2260 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, CORE_ADDR sp, |
2261 | struct frame_info *next_frame, | |
2262 | struct mips_frame_cache *this_cache) | |
c906108c SS |
2263 | { |
2264 | CORE_ADDR cur_pc; | |
2265 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
0fce0821 JB |
2266 | long frame_offset = 0; /* Size of stack frame. */ |
2267 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2268 | int frame_reg = MIPS_SP_REGNUM; | |
c906108c SS |
2269 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ |
2270 | unsigned inst = 0; /* current instruction */ | |
2271 | unsigned entry_inst = 0; /* the entry instruction */ | |
2272 | int reg, offset; | |
c906108c SS |
2273 | |
2274 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2275 | { | |
2276 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2277 | the immediate offset extension from it in mips16_get_imm. */ | |
2278 | prev_inst = inst; | |
2279 | ||
2280 | /* Fetch and decode the instruction. */ | |
2281 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2282 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
6d82d43b | 2283 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
c906108c SS |
2284 | { |
2285 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b | 2286 | if (offset < 0) /* negative stack adjustment? */ |
0fce0821 | 2287 | frame_offset -= offset; |
c906108c SS |
2288 | else |
2289 | /* Exit loop if a positive stack adjustment is found, which | |
2290 | usually means that the stack cleanup code in the function | |
2291 | epilogue is reached. */ | |
2292 | break; | |
2293 | } | |
2294 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2295 | { | |
2296 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2297 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c9343fd1 | 2298 | set_reg_offset (this_cache, reg, sp + offset); |
c906108c SS |
2299 | } |
2300 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2301 | { | |
2302 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2303 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c9343fd1 | 2304 | set_reg_offset (this_cache, reg, sp + offset); |
c906108c SS |
2305 | } |
2306 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2307 | { | |
2308 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c9343fd1 | 2309 | set_reg_offset (this_cache, RA_REGNUM, sp + offset); |
c906108c SS |
2310 | } |
2311 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2312 | { | |
2313 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c9343fd1 | 2314 | set_reg_offset (this_cache, RA_REGNUM, sp + offset); |
c906108c | 2315 | } |
c5aa993b | 2316 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2317 | { |
2318 | frame_addr = sp; | |
0fce0821 | 2319 | frame_reg = 17; |
c906108c SS |
2320 | } |
2321 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2322 | { | |
2323 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2324 | frame_addr = sp + offset; | |
0fce0821 JB |
2325 | frame_reg = 17; |
2326 | frame_adjust = offset; | |
c906108c SS |
2327 | } |
2328 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2329 | { | |
2330 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2331 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c9343fd1 | 2332 | set_reg_offset (this_cache, reg, frame_addr + offset); |
c906108c SS |
2333 | } |
2334 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2335 | { | |
2336 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2337 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c9343fd1 | 2338 | set_reg_offset (this_cache, reg, frame_addr + offset); |
c906108c | 2339 | } |
0fce0821 JB |
2340 | else if ((inst & 0xf81f) == 0xe809 |
2341 | && (inst & 0x700) != 0x700) /* entry */ | |
c5aa993b | 2342 | entry_inst = inst; /* save for later processing */ |
c906108c | 2343 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2344 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2345 | } |
2346 | ||
c5aa993b JM |
2347 | /* The entry instruction is typically the first instruction in a function, |
2348 | and it stores registers at offsets relative to the value of the old SP | |
2349 | (before the prologue). But the value of the sp parameter to this | |
2350 | function is the new SP (after the prologue has been executed). So we | |
2351 | can't calculate those offsets until we've seen the entire prologue, | |
2352 | and can calculate what the old SP must have been. */ | |
2353 | if (entry_inst != 0) | |
2354 | { | |
2355 | int areg_count = (entry_inst >> 8) & 7; | |
2356 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2357 | |
c5aa993b | 2358 | /* The entry instruction always subtracts 32 from the SP. */ |
0fce0821 | 2359 | frame_offset += 32; |
c906108c | 2360 | |
c5aa993b JM |
2361 | /* Now we can calculate what the SP must have been at the |
2362 | start of the function prologue. */ | |
0fce0821 | 2363 | sp += frame_offset; |
c906108c | 2364 | |
c5aa993b JM |
2365 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2366 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2367 | { | |
c9343fd1 | 2368 | set_reg_offset (this_cache, reg, sp + offset); |
13326b4e | 2369 | offset += mips_abi_regsize (current_gdbarch); |
c5aa993b | 2370 | } |
c906108c | 2371 | |
c5aa993b JM |
2372 | /* Check if the ra register was pushed on the stack. */ |
2373 | offset = -4; | |
2374 | if (entry_inst & 0x20) | |
2375 | { | |
c9343fd1 | 2376 | set_reg_offset (this_cache, RA_REGNUM, sp + offset); |
13326b4e | 2377 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b | 2378 | } |
c906108c | 2379 | |
c5aa993b JM |
2380 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2381 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2382 | { | |
c9343fd1 | 2383 | set_reg_offset (this_cache, reg, sp + offset); |
13326b4e | 2384 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b JM |
2385 | } |
2386 | } | |
0fce0821 JB |
2387 | |
2388 | if (this_cache != NULL) | |
2389 | { | |
2390 | this_cache->base = | |
2391 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
2392 | + frame_offset - frame_adjust); | |
2393 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
2394 | be able to get rid of the assignment below, evetually. But it's | |
2395 | still needed for now. */ | |
2396 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
2397 | = this_cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
2398 | } | |
c906108c SS |
2399 | } |
2400 | ||
65596487 JB |
2401 | /* Mark all the registers as unset in the saved_regs array |
2402 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
2403 | ||
2404 | void | |
2405 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
2406 | { | |
2407 | if (this_cache == NULL || this_cache->saved_regs == NULL) | |
2408 | return; | |
2409 | ||
2410 | { | |
2411 | const int num_regs = NUM_REGS; | |
2412 | int i; | |
2413 | ||
2414 | for (i = 0; i < num_regs; i++) | |
2415 | { | |
2416 | this_cache->saved_regs[i].addr = -1; | |
2417 | } | |
2418 | } | |
2419 | } | |
2420 | ||
1e05a7bf JB |
2421 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2422 | the associated FRAME_CACHE if not null. */ | |
2423 | ||
c906108c | 2424 | static void |
1e05a7bf JB |
2425 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, CORE_ADDR sp, |
2426 | struct frame_info *next_frame, | |
2427 | struct mips_frame_cache *this_cache) | |
c906108c SS |
2428 | { |
2429 | CORE_ADDR cur_pc; | |
1e05a7bf | 2430 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
65596487 JB |
2431 | long frame_offset; |
2432 | int frame_reg = MIPS_SP_REGNUM; | |
2433 | ||
c906108c | 2434 | restart: |
65596487 JB |
2435 | |
2436 | frame_offset = 0; | |
c906108c SS |
2437 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) |
2438 | { | |
2439 | unsigned long inst, high_word, low_word; | |
2440 | int reg; | |
2441 | ||
2442 | /* Fetch the instruction. */ | |
2443 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2444 | ||
2445 | /* Save some code by pre-extracting some useful fields. */ | |
2446 | high_word = (inst >> 16) & 0xffff; | |
2447 | low_word = inst & 0xffff; | |
2448 | reg = high_word & 0x1f; | |
2449 | ||
c5aa993b | 2450 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2451 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2452 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2453 | { | |
2454 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
65596487 | 2455 | frame_offset += 0x10000 - low_word; |
c906108c SS |
2456 | else |
2457 | /* Exit loop if a positive stack adjustment is found, which | |
2458 | usually means that the stack cleanup code in the function | |
2459 | epilogue is reached. */ | |
2460 | break; | |
2461 | } | |
2462 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2463 | { | |
c9343fd1 | 2464 | set_reg_offset (this_cache, reg, sp + low_word); |
c906108c SS |
2465 | } |
2466 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2467 | { | |
d5ac5a39 AC |
2468 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and |
2469 | $ra. */ | |
c9343fd1 | 2470 | set_reg_offset (this_cache, reg, sp + low_word); |
c906108c | 2471 | } |
c5aa993b | 2472 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2473 | { |
2474 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
65596487 | 2475 | if ((long) low_word != frame_offset) |
c5aa993b | 2476 | frame_addr = sp + low_word; |
65596487 | 2477 | else if (frame_reg == MIPS_SP_REGNUM) |
c906108c SS |
2478 | { |
2479 | unsigned alloca_adjust; | |
65596487 JB |
2480 | |
2481 | frame_reg = 30; | |
a4b8ebc8 | 2482 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2483 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2484 | if (alloca_adjust > 0) |
2485 | { | |
65596487 JB |
2486 | /* FP > SP + frame_size. This may be because of |
2487 | an alloca or somethings similar. Fix sp to | |
2488 | "pre-alloca" value, and try again. */ | |
c906108c | 2489 | sp += alloca_adjust; |
65596487 JB |
2490 | /* Need to reset the status of all registers. Otherwise, |
2491 | we will hit a guard that prevents the new address | |
2492 | for each register to be recomputed during the second | |
2493 | pass. */ | |
2494 | reset_saved_regs (this_cache); | |
c906108c SS |
2495 | goto restart; |
2496 | } | |
2497 | } | |
2498 | } | |
c5aa993b JM |
2499 | /* move $30,$sp. With different versions of gas this will be either |
2500 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2501 | Accept any one of these. */ | |
c906108c SS |
2502 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2503 | { | |
2504 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
65596487 | 2505 | if (frame_reg == MIPS_SP_REGNUM) |
c906108c SS |
2506 | { |
2507 | unsigned alloca_adjust; | |
65596487 JB |
2508 | |
2509 | frame_reg = 30; | |
a4b8ebc8 | 2510 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2511 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c | 2512 | if (alloca_adjust > 0) |
65596487 JB |
2513 | { |
2514 | /* FP > SP + frame_size. This may be because of | |
2515 | an alloca or somethings similar. Fix sp to | |
2516 | "pre-alloca" value, and try again. */ | |
2517 | sp = frame_addr; | |
2518 | /* Need to reset the status of all registers. Otherwise, | |
2519 | we will hit a guard that prevents the new address | |
2520 | for each register to be recomputed during the second | |
2521 | pass. */ | |
2522 | reset_saved_regs (this_cache); | |
2523 | goto restart; | |
2524 | } | |
c906108c SS |
2525 | } |
2526 | } | |
c5aa993b | 2527 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2528 | { |
c9343fd1 | 2529 | set_reg_offset (this_cache, reg, frame_addr + low_word); |
c906108c SS |
2530 | } |
2531 | } | |
65596487 JB |
2532 | |
2533 | if (this_cache != NULL) | |
2534 | { | |
2535 | this_cache->base = | |
2536 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
2537 | + frame_offset); | |
2538 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2539 | this assignment below, eventually. But it's still needed | |
2540 | for now. */ | |
2541 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
2542 | = this_cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
2543 | } | |
c906108c SS |
2544 | } |
2545 | ||
2546 | static mips_extra_func_info_t | |
acdb74a0 | 2547 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
c9343fd1 AC |
2548 | struct frame_info *next_frame, |
2549 | struct mips_frame_cache *this_cache) | |
c906108c | 2550 | { |
479412cd DJ |
2551 | CORE_ADDR sp; |
2552 | ||
465f7520 AC |
2553 | /* Can be called when there's no process, and hence when there's no |
2554 | NEXT_FRAME. */ | |
2555 | if (next_frame != NULL) | |
f10683bb | 2556 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); |
479412cd DJ |
2557 | else |
2558 | sp = 0; | |
c906108c | 2559 | |
c5aa993b JM |
2560 | if (start_pc == 0) |
2561 | return NULL; | |
2562 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
c906108c | 2563 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
f10683bb | 2564 | PROC_FRAME_REG (&temp_proc_desc) = MIPS_SP_REGNUM; |
c906108c SS |
2565 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; |
2566 | ||
2567 | if (start_pc + 200 < limit_pc) | |
2568 | limit_pc = start_pc + 200; | |
2569 | if (pc_is_mips16 (start_pc)) | |
1e05a7bf | 2570 | mips16_scan_prologue (start_pc, limit_pc, sp, next_frame, this_cache); |
c906108c | 2571 | else |
1e05a7bf | 2572 | mips32_scan_prologue (start_pc, limit_pc, sp, next_frame, this_cache); |
c906108c SS |
2573 | return &temp_proc_desc; |
2574 | } | |
2575 | ||
6c0d6680 DJ |
2576 | struct mips_objfile_private |
2577 | { | |
2578 | bfd_size_type size; | |
2579 | char *contents; | |
2580 | }; | |
2581 | ||
2582 | /* Global used to communicate between non_heuristic_proc_desc and | |
2583 | compare_pdr_entries within qsort (). */ | |
2584 | static bfd *the_bfd; | |
2585 | ||
2586 | static int | |
2587 | compare_pdr_entries (const void *a, const void *b) | |
2588 | { | |
2589 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2590 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2591 | ||
2592 | if (lhs < rhs) | |
2593 | return -1; | |
2594 | else if (lhs == rhs) | |
2595 | return 0; | |
2596 | else | |
2597 | return 1; | |
2598 | } | |
2599 | ||
c906108c | 2600 | static mips_extra_func_info_t |
acdb74a0 | 2601 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2602 | { |
2603 | CORE_ADDR startaddr; | |
2604 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2605 | struct block *b = block_for_pc (pc); |
c906108c | 2606 | struct symbol *sym; |
6c0d6680 DJ |
2607 | struct obj_section *sec; |
2608 | struct mips_objfile_private *priv; | |
2609 | ||
c906108c SS |
2610 | find_pc_partial_function (pc, NULL, &startaddr, NULL); |
2611 | if (addrptr) | |
2612 | *addrptr = startaddr; | |
6c0d6680 DJ |
2613 | |
2614 | priv = NULL; | |
2615 | ||
2616 | sec = find_pc_section (pc); | |
2617 | if (sec != NULL) | |
c906108c | 2618 | { |
8d5f9dcb | 2619 | priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data); |
6c0d6680 DJ |
2620 | |
2621 | /* Search the ".pdr" section generated by GAS. This includes most of | |
6d82d43b | 2622 | the information normally found in ECOFF PDRs. */ |
6c0d6680 DJ |
2623 | |
2624 | the_bfd = sec->objfile->obfd; | |
2625 | if (priv == NULL | |
2626 | && (the_bfd->format == bfd_object | |
2627 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2628 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2629 | { | |
2630 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2631 | This means that we should not bother with this method on 64-bit | |
2632 | targets (until that is fixed). */ | |
2633 | ||
8b92e4d5 | 2634 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2635 | sizeof (struct mips_objfile_private)); |
2636 | priv->size = 0; | |
8d5f9dcb | 2637 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2638 | } |
2639 | else if (priv == NULL) | |
2640 | { | |
2641 | asection *bfdsec; | |
2642 | ||
8b92e4d5 | 2643 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2644 | sizeof (struct mips_objfile_private)); |
2645 | ||
2646 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2647 | if (bfdsec != NULL) | |
2648 | { | |
2649 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
8b92e4d5 | 2650 | priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2651 | priv->size); |
2652 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2653 | priv->contents, 0, priv->size); | |
2654 | ||
2655 | /* In general, the .pdr section is sorted. However, in the | |
6d82d43b AC |
2656 | presence of multiple code sections (and other corner cases) |
2657 | it can become unsorted. Sort it so that we can use a faster | |
2658 | binary search. */ | |
2659 | qsort (priv->contents, priv->size / 32, 32, | |
2660 | compare_pdr_entries); | |
6c0d6680 DJ |
2661 | } |
2662 | else | |
2663 | priv->size = 0; | |
2664 | ||
8d5f9dcb | 2665 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2666 | } |
2667 | the_bfd = NULL; | |
2668 | ||
2669 | if (priv->size != 0) | |
2670 | { | |
2671 | int low, mid, high; | |
2672 | char *ptr; | |
34fcf120 | 2673 | CORE_ADDR pdr_pc; |
6c0d6680 DJ |
2674 | |
2675 | low = 0; | |
2676 | high = priv->size / 32; | |
2677 | ||
34fcf120 DJ |
2678 | /* We've found a .pdr section describing this objfile. We want to |
2679 | find the entry which describes this code address. The .pdr | |
2680 | information is not very descriptive; we have only a function | |
2681 | start address. We have to look for the closest entry, because | |
2682 | the local symbol at the beginning of this function may have | |
2683 | been stripped - so if we ask the symbol table for the start | |
2684 | address we may get a preceding global function. */ | |
2685 | ||
2686 | /* First, find the last .pdr entry starting at or before PC. */ | |
6c0d6680 DJ |
2687 | do |
2688 | { | |
6c0d6680 DJ |
2689 | mid = (low + high) / 2; |
2690 | ||
2691 | ptr = priv->contents + mid * 32; | |
2692 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2693 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2694 | SECT_OFF_TEXT (sec->objfile)); | |
34fcf120 DJ |
2695 | |
2696 | if (pdr_pc > pc) | |
6c0d6680 DJ |
2697 | high = mid; |
2698 | else | |
2699 | low = mid + 1; | |
2700 | } | |
2701 | while (low != high); | |
2702 | ||
34fcf120 DJ |
2703 | /* Both low and high point one past the PDR of interest. If |
2704 | both are zero, that means this PC is before any region | |
2705 | covered by a PDR, i.e. pdr_pc for the first PDR entry is | |
2706 | greater than PC. */ | |
2707 | if (low > 0) | |
2708 | { | |
2709 | ptr = priv->contents + (low - 1) * 32; | |
2710 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2711 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2712 | SECT_OFF_TEXT (sec->objfile)); | |
2713 | } | |
2714 | ||
2715 | /* We don't have a range, so we have no way to know for sure | |
2716 | whether we're in the correct PDR or a PDR for a preceding | |
2717 | function and the current function was a stripped local | |
2718 | symbol. But if the PDR's PC is at least as great as the | |
2719 | best guess from the symbol table, assume that it does cover | |
2720 | the right area; if a .pdr section is present at all then | |
2721 | nearly every function will have an entry. The biggest exception | |
2722 | will be the dynamic linker stubs; conveniently these are | |
2723 | placed before .text instead of after. */ | |
2724 | ||
2725 | if (pc >= pdr_pc && pdr_pc >= startaddr) | |
6c0d6680 DJ |
2726 | { |
2727 | struct symbol *sym = find_pc_function (pc); | |
2728 | ||
34fcf120 DJ |
2729 | if (addrptr) |
2730 | *addrptr = pdr_pc; | |
2731 | ||
6c0d6680 DJ |
2732 | /* Fill in what we need of the proc_desc. */ |
2733 | proc_desc = (mips_extra_func_info_t) | |
8b92e4d5 | 2734 | obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 | 2735 | sizeof (struct mips_extra_func_info)); |
34fcf120 | 2736 | PROC_LOW_ADDR (proc_desc) = pdr_pc; |
6c0d6680 DJ |
2737 | |
2738 | /* Only used for dummy frames. */ | |
2739 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2740 | ||
2741 | PROC_FRAME_OFFSET (proc_desc) | |
2742 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2743 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2744 | ptr + 24); | |
2745 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2746 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2747 | ptr + 4); | |
2748 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2749 | ptr + 12); | |
2750 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2751 | ptr + 8); | |
2752 | PROC_FREG_OFFSET (proc_desc) | |
2753 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2754 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2755 | ptr + 28); | |
2756 | proc_desc->pdr.isym = (long) sym; | |
2757 | ||
2758 | return proc_desc; | |
2759 | } | |
2760 | } | |
c906108c SS |
2761 | } |
2762 | ||
6c0d6680 DJ |
2763 | if (b == NULL) |
2764 | return NULL; | |
2765 | ||
2766 | if (startaddr > BLOCK_START (b)) | |
2767 | { | |
2768 | /* This is the "pathological" case referred to in a comment in | |
6d82d43b AC |
2769 | print_frame_info. It might be better to move this check into |
2770 | symbol reading. */ | |
6c0d6680 DJ |
2771 | return NULL; |
2772 | } | |
2773 | ||
176620f1 | 2774 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2775 | |
c906108c SS |
2776 | /* If we never found a PDR for this function in symbol reading, then |
2777 | examine prologues to find the information. */ | |
2778 | if (sym) | |
2779 | { | |
2780 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2781 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2782 | return NULL; | |
2783 | else | |
2784 | return proc_desc; | |
2785 | } | |
2786 | else | |
2787 | return NULL; | |
2788 | } | |
2789 | ||
c906108c SS |
2790 | /* MIPS stack frames are almost impenetrable. When execution stops, |
2791 | we basically have to look at symbol information for the function | |
2792 | that we stopped in, which tells us *which* register (if any) is | |
2793 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2794 | the frame itself is at. |
c906108c SS |
2795 | |
2796 | This presents a problem when trying to examine a stack in memory | |
2797 | (that isn't executing at the moment), using the "frame" command. We | |
2798 | don't have a PC, nor do we have any registers except SP. | |
2799 | ||
2800 | This routine takes two arguments, SP and PC, and tries to make the | |
2801 | cached frames look as if these two arguments defined a frame on the | |
2802 | cache. This allows the rest of info frame to extract the important | |
2803 | arguments without difficulty. */ | |
2804 | ||
2805 | struct frame_info * | |
acdb74a0 | 2806 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2807 | { |
2808 | if (argc != 2) | |
2809 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2810 | ||
2811 | return create_new_frame (argv[0], argv[1]); | |
2812 | } | |
2813 | ||
f09ded24 AC |
2814 | /* According to the current ABI, should the type be passed in a |
2815 | floating-point register (assuming that there is space)? When there | |
2816 | is no FPU, FP are not even considered as possibile candidates for | |
2817 | FP registers and, consequently this returns false - forces FP | |
2818 | arguments into integer registers. */ | |
2819 | ||
2820 | static int | |
2821 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2822 | { | |
2823 | return ((typecode == TYPE_CODE_FLT | |
2824 | || (MIPS_EABI | |
6d82d43b AC |
2825 | && (typecode == TYPE_CODE_STRUCT |
2826 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
2827 | && TYPE_NFIELDS (arg_type) == 1 |
2828 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2829 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2830 | } |
2831 | ||
49e790b0 DJ |
2832 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2833 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2834 | ||
2835 | static int | |
2836 | mips_type_needs_double_align (struct type *type) | |
2837 | { | |
2838 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2839 | |
49e790b0 DJ |
2840 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2841 | return 1; | |
2842 | else if (typecode == TYPE_CODE_STRUCT) | |
2843 | { | |
2844 | if (TYPE_NFIELDS (type) < 1) | |
2845 | return 0; | |
2846 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2847 | } | |
2848 | else if (typecode == TYPE_CODE_UNION) | |
2849 | { | |
361d1df0 | 2850 | int i, n; |
49e790b0 DJ |
2851 | |
2852 | n = TYPE_NFIELDS (type); | |
2853 | for (i = 0; i < n; i++) | |
2854 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2855 | return 1; | |
2856 | return 0; | |
2857 | } | |
2858 | return 0; | |
2859 | } | |
2860 | ||
dc604539 AC |
2861 | /* Adjust the address downward (direction of stack growth) so that it |
2862 | is correctly aligned for a new stack frame. */ | |
2863 | static CORE_ADDR | |
2864 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2865 | { | |
5b03f266 | 2866 | return align_down (addr, 16); |
dc604539 AC |
2867 | } |
2868 | ||
6d82d43b AC |
2869 | /* Determine how a return value is stored within the MIPS register |
2870 | file, given the return type `valtype'. */ | |
2871 | ||
2872 | struct return_value_word | |
2873 | { | |
2874 | int len; | |
2875 | int reg; | |
2876 | int reg_offset; | |
2877 | int buf_offset; | |
2878 | }; | |
2879 | ||
2880 | static void | |
2881 | return_value_location (struct type *valtype, | |
2882 | struct return_value_word *hi, | |
2883 | struct return_value_word *lo) | |
2884 | { | |
2885 | int len = TYPE_LENGTH (valtype); | |
2886 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2887 | ||
2888 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
2889 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
2890 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
2891 | { | |
ceae6e75 | 2892 | if (mips_abi_regsize (current_gdbarch) < 8 && len == 8) |
6d82d43b AC |
2893 | { |
2894 | /* We need to break a 64bit float in two 32 bit halves and | |
ceae6e75 | 2895 | spread them across a floating-point register pair. */ |
6d82d43b AC |
2896 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
2897 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
2898 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2899 | && register_size (current_gdbarch, | |
2900 | mips_regnum (current_gdbarch)-> | |
2901 | fp0) == 8) ? 4 : 0); | |
2902 | hi->reg_offset = lo->reg_offset; | |
2903 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; | |
2904 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
2905 | lo->len = 4; | |
2906 | hi->len = 4; | |
2907 | } | |
2908 | else | |
2909 | { | |
2910 | /* The floating point value fits in a single floating-point | |
2911 | register. */ | |
2912 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2913 | && register_size (current_gdbarch, | |
2914 | mips_regnum (current_gdbarch)-> | |
2915 | fp0) == 8 | |
2916 | && len == 4) ? 4 : 0); | |
2917 | lo->reg = mips_regnum (current_gdbarch)->fp0; | |
2918 | lo->len = len; | |
2919 | lo->buf_offset = 0; | |
2920 | hi->len = 0; | |
2921 | hi->reg_offset = 0; | |
2922 | hi->buf_offset = 0; | |
2923 | hi->reg = 0; | |
2924 | } | |
2925 | } | |
2926 | else | |
2927 | { | |
2928 | /* Locate a result possibly spread across two registers. */ | |
2929 | int regnum = 2; | |
2930 | lo->reg = regnum + 0; | |
2931 | hi->reg = regnum + 1; | |
2932 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 2933 | && len < mips_abi_regsize (current_gdbarch)) |
6d82d43b AC |
2934 | { |
2935 | /* "un-left-justify" the value in the low register */ | |
13326b4e | 2936 | lo->reg_offset = mips_abi_regsize (current_gdbarch) - len; |
6d82d43b AC |
2937 | lo->len = len; |
2938 | hi->reg_offset = 0; | |
2939 | hi->len = 0; | |
2940 | } | |
13326b4e AC |
2941 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_abi_regsize (current_gdbarch) /* odd-size structs */ |
2942 | && len < mips_abi_regsize (current_gdbarch) * 2 | |
6d82d43b AC |
2943 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || |
2944 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
2945 | { | |
2946 | /* "un-left-justify" the value spread across two registers. */ | |
13326b4e AC |
2947 | lo->reg_offset = 2 * mips_abi_regsize (current_gdbarch) - len; |
2948 | lo->len = mips_abi_regsize (current_gdbarch) - lo->reg_offset; | |
6d82d43b AC |
2949 | hi->reg_offset = 0; |
2950 | hi->len = len - lo->len; | |
2951 | } | |
2952 | else | |
2953 | { | |
2954 | /* Only perform a partial copy of the second register. */ | |
2955 | lo->reg_offset = 0; | |
2956 | hi->reg_offset = 0; | |
13326b4e | 2957 | if (len > mips_abi_regsize (current_gdbarch)) |
6d82d43b | 2958 | { |
13326b4e AC |
2959 | lo->len = mips_abi_regsize (current_gdbarch); |
2960 | hi->len = len - mips_abi_regsize (current_gdbarch); | |
6d82d43b AC |
2961 | } |
2962 | else | |
2963 | { | |
2964 | lo->len = len; | |
2965 | hi->len = 0; | |
2966 | } | |
2967 | } | |
2968 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2969 | && register_size (current_gdbarch, regnum) == 8 | |
13326b4e | 2970 | && mips_abi_regsize (current_gdbarch) == 4) |
6d82d43b AC |
2971 | { |
2972 | /* Account for the fact that only the least-signficant part | |
2973 | of the register is being used */ | |
2974 | lo->reg_offset += 4; | |
2975 | hi->reg_offset += 4; | |
2976 | } | |
2977 | lo->buf_offset = 0; | |
2978 | hi->buf_offset = lo->len; | |
2979 | } | |
2980 | } | |
2981 | ||
2982 | /* Should call_function allocate stack space for a struct return? */ | |
2983 | ||
2984 | static int | |
2985 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) | |
2986 | { | |
2987 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
13326b4e | 2988 | return (TYPE_LENGTH (type) > 2 * mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
2989 | } |
2990 | ||
2991 | /* Should call_function pass struct by reference? | |
2992 | For each architecture, structs are passed either by | |
2993 | value or by reference, depending on their size. */ | |
2994 | ||
2995 | static int | |
2996 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
2997 | { | |
2998 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
2999 | int len = TYPE_LENGTH (check_typedef (type)); | |
3000 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3001 | ||
3002 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
13326b4e | 3003 | return (len > mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
3004 | |
3005 | return 0; | |
3006 | } | |
3007 | ||
f7ab6ec6 | 3008 | static CORE_ADDR |
7d9b040b | 3009 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3010 | struct regcache *regcache, CORE_ADDR bp_addr, |
3011 | int nargs, struct value **args, CORE_ADDR sp, | |
3012 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
3013 | { |
3014 | int argreg; | |
3015 | int float_argreg; | |
3016 | int argnum; | |
3017 | int len = 0; | |
3018 | int stack_offset = 0; | |
480d3dd2 | 3019 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3020 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 3021 | |
25ab4790 AC |
3022 | /* For shared libraries, "t9" needs to point at the function |
3023 | address. */ | |
3024 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3025 | ||
3026 | /* Set the return address register to point to the entry point of | |
3027 | the program, where a breakpoint lies in wait. */ | |
3028 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3029 | ||
c906108c | 3030 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
3031 | are properly aligned. The stack has to be at least 64-bit |
3032 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3033 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3034 | aligned, so we round to this widest known alignment. */ | |
3035 | ||
5b03f266 AC |
3036 | sp = align_down (sp, 16); |
3037 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 3038 | |
46e0f506 | 3039 | /* Now make space on the stack for the args. We allocate more |
c906108c | 3040 | than necessary for EABI, because the first few arguments are |
46e0f506 | 3041 | passed in registers, but that's OK. */ |
c906108c | 3042 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 3043 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3044 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3045 | sp -= align_up (len, 16); |
c906108c | 3046 | |
9ace0497 | 3047 | if (mips_debug) |
6d82d43b | 3048 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3049 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
3050 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 3051 | |
c906108c SS |
3052 | /* Initialize the integer and float register pointers. */ |
3053 | argreg = A0_REGNUM; | |
56cea623 | 3054 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 3055 | |
46e0f506 | 3056 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 3057 | if (struct_return) |
9ace0497 AC |
3058 | { |
3059 | if (mips_debug) | |
3060 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3061 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 3062 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
3063 | write_register (argreg++, struct_addr); |
3064 | } | |
c906108c SS |
3065 | |
3066 | /* Now load as many as possible of the first arguments into | |
3067 | registers, and push the rest onto the stack. Loop thru args | |
3068 | from first to last. */ | |
3069 | for (argnum = 0; argnum < nargs; argnum++) | |
3070 | { | |
3071 | char *val; | |
d9d9c31f | 3072 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 3073 | struct value *arg = args[argnum]; |
c906108c SS |
3074 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
3075 | int len = TYPE_LENGTH (arg_type); | |
3076 | enum type_code typecode = TYPE_CODE (arg_type); | |
3077 | ||
9ace0497 AC |
3078 | if (mips_debug) |
3079 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3080 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 3081 | argnum + 1, len, (int) typecode); |
9ace0497 | 3082 | |
c906108c | 3083 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 3084 | reference. */ |
13326b4e | 3085 | if (len > mips_abi_regsize (gdbarch) |
9ace0497 | 3086 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 3087 | { |
13326b4e | 3088 | store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch), |
480d3dd2 | 3089 | VALUE_ADDRESS (arg)); |
c906108c | 3090 | typecode = TYPE_CODE_PTR; |
13326b4e | 3091 | len = mips_abi_regsize (gdbarch); |
c906108c | 3092 | val = valbuf; |
9ace0497 AC |
3093 | if (mips_debug) |
3094 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3095 | } |
3096 | else | |
c5aa993b | 3097 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
3098 | |
3099 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3100 | even-numbered floating point register. Round the FP register |
3101 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3102 | left. Non MIPS_EABI targets also pass the FP in the integer |
3103 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3104 | if (mips_abi_regsize (gdbarch) < 8 |
3105 | && fp_register_arg_p (typecode, arg_type)) | |
acdb74a0 AC |
3106 | { |
3107 | if ((float_argreg & 1)) | |
3108 | float_argreg++; | |
3109 | } | |
c906108c SS |
3110 | |
3111 | /* Floating point arguments passed in registers have to be | |
3112 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3113 | are passed in register pairs; the even register gets |
3114 | the low word, and the odd register gets the high word. | |
3115 | On non-EABI processors, the first two floating point arguments are | |
3116 | also copied to general registers, because MIPS16 functions | |
3117 | don't use float registers for arguments. This duplication of | |
3118 | arguments in general registers can't hurt non-MIPS16 functions | |
3119 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3120 | /* MIPS_EABI squeezes a struct that contains a single floating |
3121 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3122 | stack. */ |
f09ded24 AC |
3123 | if (fp_register_arg_p (typecode, arg_type) |
3124 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 3125 | { |
ceae6e75 | 3126 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
c906108c | 3127 | { |
d7449b42 | 3128 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
3129 | unsigned long regval; |
3130 | ||
3131 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 3132 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 3133 | if (mips_debug) |
acdb74a0 | 3134 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3135 | float_argreg, phex (regval, 4)); |
c906108c | 3136 | write_register (float_argreg++, regval); |
c906108c SS |
3137 | |
3138 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 3139 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 3140 | if (mips_debug) |
acdb74a0 | 3141 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3142 | float_argreg, phex (regval, 4)); |
c906108c | 3143 | write_register (float_argreg++, regval); |
c906108c SS |
3144 | } |
3145 | else | |
3146 | { | |
3147 | /* This is a floating point value that fits entirely | |
3148 | in a single register. */ | |
53a5351d | 3149 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3150 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
3151 | LONGEST regval = extract_unsigned_integer (val, len); |
3152 | if (mips_debug) | |
acdb74a0 | 3153 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3154 | float_argreg, phex (regval, len)); |
c906108c | 3155 | write_register (float_argreg++, regval); |
c906108c SS |
3156 | } |
3157 | } | |
3158 | else | |
3159 | { | |
3160 | /* Copy the argument to general registers or the stack in | |
3161 | register-sized pieces. Large arguments are split between | |
3162 | registers and stack. */ | |
4246e332 | 3163 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3164 | mips_abi_regsize() are treated specially: Irix cc passes |
3165 | them in registers where gcc sometimes puts them on the | |
3166 | stack. For maximum compatibility, we will put them in | |
3167 | both places. */ | |
13326b4e AC |
3168 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3169 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46e0f506 | 3170 | |
f09ded24 | 3171 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3172 | register are only written to memory. */ |
c906108c SS |
3173 | while (len > 0) |
3174 | { | |
ebafbe83 | 3175 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3176 | int stack_used_p = 0; |
13326b4e AC |
3177 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3178 | ? len : mips_abi_regsize (gdbarch)); | |
c906108c | 3179 | |
acdb74a0 AC |
3180 | if (mips_debug) |
3181 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3182 | partial_len); | |
3183 | ||
566f0f7a | 3184 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
3185 | if (argreg > MIPS_LAST_ARG_REGNUM |
3186 | || odd_sized_struct | |
3187 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3188 | { |
c906108c SS |
3189 | /* Should shorter than int integer values be |
3190 | promoted to int before being stored? */ | |
c906108c | 3191 | int longword_offset = 0; |
9ace0497 | 3192 | CORE_ADDR addr; |
566f0f7a | 3193 | stack_used_p = 1; |
d7449b42 | 3194 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 3195 | { |
13326b4e | 3196 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3197 | && (typecode == TYPE_CODE_INT |
3198 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3199 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3200 | longword_offset = mips_stack_argsize (gdbarch) - len; |
480d3dd2 AC |
3201 | else if ((typecode == TYPE_CODE_STRUCT |
3202 | || typecode == TYPE_CODE_UNION) | |
3203 | && (TYPE_LENGTH (arg_type) | |
13326b4e AC |
3204 | < mips_stack_argsize (gdbarch))) |
3205 | longword_offset = mips_stack_argsize (gdbarch) - len; | |
7a292a7a | 3206 | } |
c5aa993b | 3207 | |
9ace0497 AC |
3208 | if (mips_debug) |
3209 | { | |
cb3d25d1 MS |
3210 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
3211 | paddr_nz (stack_offset)); | |
3212 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3213 | paddr_nz (longword_offset)); | |
9ace0497 | 3214 | } |
361d1df0 | 3215 | |
9ace0497 AC |
3216 | addr = sp + stack_offset + longword_offset; |
3217 | ||
3218 | if (mips_debug) | |
3219 | { | |
3220 | int i; | |
6d82d43b | 3221 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 3222 | paddr_nz (addr)); |
9ace0497 AC |
3223 | for (i = 0; i < partial_len; i++) |
3224 | { | |
6d82d43b | 3225 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3226 | val[i] & 0xff); |
9ace0497 AC |
3227 | } |
3228 | } | |
3229 | write_memory (addr, val, partial_len); | |
c906108c SS |
3230 | } |
3231 | ||
f09ded24 AC |
3232 | /* Note!!! This is NOT an else clause. Odd sized |
3233 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3234 | arguments will not. */ |
566f0f7a | 3235 | /* Write this portion of the argument to a general |
6d82d43b | 3236 | purpose register. */ |
f09ded24 AC |
3237 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3238 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3239 | { |
6d82d43b AC |
3240 | LONGEST regval = |
3241 | extract_unsigned_integer (val, partial_len); | |
c906108c | 3242 | |
9ace0497 | 3243 | if (mips_debug) |
acdb74a0 | 3244 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3245 | argreg, |
6d82d43b | 3246 | phex (regval, |
13326b4e | 3247 | mips_abi_regsize (gdbarch))); |
c906108c SS |
3248 | write_register (argreg, regval); |
3249 | argreg++; | |
c906108c | 3250 | } |
c5aa993b | 3251 | |
c906108c SS |
3252 | len -= partial_len; |
3253 | val += partial_len; | |
3254 | ||
566f0f7a | 3255 | /* Compute the the offset into the stack at which we |
6d82d43b | 3256 | will copy the next parameter. |
566f0f7a | 3257 | |
566f0f7a | 3258 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3259 | only needs to be adjusted when it has been used. */ |
c906108c | 3260 | |
46e0f506 | 3261 | if (stack_used_p) |
480d3dd2 | 3262 | stack_offset += align_up (partial_len, |
13326b4e | 3263 | mips_stack_argsize (gdbarch)); |
c906108c SS |
3264 | } |
3265 | } | |
9ace0497 AC |
3266 | if (mips_debug) |
3267 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3268 | } |
3269 | ||
f10683bb | 3270 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3271 | |
0f71a2f6 JM |
3272 | /* Return adjusted stack pointer. */ |
3273 | return sp; | |
3274 | } | |
3275 | ||
6d82d43b AC |
3276 | /* Given a return value in `regbuf' with a type `valtype', extract and |
3277 | copy its value into `valbuf'. */ | |
3278 | ||
3279 | static void | |
3280 | mips_eabi_extract_return_value (struct type *valtype, | |
3281 | char regbuf[], char *valbuf) | |
3282 | { | |
3283 | struct return_value_word lo; | |
3284 | struct return_value_word hi; | |
3285 | return_value_location (valtype, &hi, &lo); | |
3286 | ||
3287 | memcpy (valbuf + lo.buf_offset, | |
3288 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
3289 | lo.reg_offset, lo.len); | |
3290 | ||
3291 | if (hi.len > 0) | |
3292 | memcpy (valbuf + hi.buf_offset, | |
3293 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
3294 | hi.reg_offset, hi.len); | |
3295 | } | |
3296 | ||
3297 | /* Given a return value in `valbuf' with a type `valtype', write it's | |
3298 | value into the appropriate register. */ | |
3299 | ||
3300 | static void | |
3301 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
3302 | { | |
3303 | char raw_buffer[MAX_REGISTER_SIZE]; | |
3304 | struct return_value_word lo; | |
3305 | struct return_value_word hi; | |
3306 | return_value_location (valtype, &hi, &lo); | |
3307 | ||
3308 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3309 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3310 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
3311 | raw_buffer, register_size (current_gdbarch, | |
3312 | lo.reg)); | |
3313 | ||
3314 | if (hi.len > 0) | |
3315 | { | |
3316 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3317 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3318 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
3319 | raw_buffer, | |
3320 | register_size (current_gdbarch, | |
3321 | hi.reg)); | |
3322 | } | |
3323 | } | |
3324 | ||
3325 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3326 | |
f7ab6ec6 | 3327 | static CORE_ADDR |
7d9b040b | 3328 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3329 | struct regcache *regcache, CORE_ADDR bp_addr, |
3330 | int nargs, struct value **args, CORE_ADDR sp, | |
3331 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3332 | { |
3333 | int argreg; | |
3334 | int float_argreg; | |
3335 | int argnum; | |
3336 | int len = 0; | |
3337 | int stack_offset = 0; | |
480d3dd2 | 3338 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3339 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3340 | |
25ab4790 AC |
3341 | /* For shared libraries, "t9" needs to point at the function |
3342 | address. */ | |
3343 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3344 | ||
3345 | /* Set the return address register to point to the entry point of | |
3346 | the program, where a breakpoint lies in wait. */ | |
3347 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3348 | ||
cb3d25d1 MS |
3349 | /* First ensure that the stack and structure return address (if any) |
3350 | are properly aligned. The stack has to be at least 64-bit | |
3351 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3352 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3353 | aligned, so we round to this widest known alignment. */ | |
3354 | ||
5b03f266 AC |
3355 | sp = align_down (sp, 16); |
3356 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3357 | |
3358 | /* Now make space on the stack for the args. */ | |
3359 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3360 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3361 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3362 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3363 | |
3364 | if (mips_debug) | |
6d82d43b | 3365 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3366 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3367 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3368 | |
3369 | /* Initialize the integer and float register pointers. */ | |
3370 | argreg = A0_REGNUM; | |
56cea623 | 3371 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3372 | |
46e0f506 | 3373 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3374 | if (struct_return) |
3375 | { | |
3376 | if (mips_debug) | |
3377 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3378 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3379 | argreg, paddr_nz (struct_addr)); |
3380 | write_register (argreg++, struct_addr); | |
3381 | } | |
3382 | ||
3383 | /* Now load as many as possible of the first arguments into | |
3384 | registers, and push the rest onto the stack. Loop thru args | |
3385 | from first to last. */ | |
3386 | for (argnum = 0; argnum < nargs; argnum++) | |
3387 | { | |
3388 | char *val; | |
cb3d25d1 MS |
3389 | struct value *arg = args[argnum]; |
3390 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3391 | int len = TYPE_LENGTH (arg_type); | |
3392 | enum type_code typecode = TYPE_CODE (arg_type); | |
3393 | ||
3394 | if (mips_debug) | |
3395 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3396 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3397 | argnum + 1, len, (int) typecode); |
3398 | ||
3399 | val = (char *) VALUE_CONTENTS (arg); | |
3400 | ||
3401 | if (fp_register_arg_p (typecode, arg_type) | |
3402 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3403 | { | |
3404 | /* This is a floating point value that fits entirely | |
3405 | in a single register. */ | |
3406 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3407 | above to ensure that it is even register aligned. */ | |
3408 | LONGEST regval = extract_unsigned_integer (val, len); | |
3409 | if (mips_debug) | |
3410 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3411 | float_argreg, phex (regval, len)); | |
3412 | write_register (float_argreg++, regval); | |
3413 | ||
3414 | if (mips_debug) | |
3415 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3416 | argreg, phex (regval, len)); | |
3417 | write_register (argreg, regval); | |
3418 | argreg += 1; | |
3419 | } | |
3420 | else | |
3421 | { | |
3422 | /* Copy the argument to general registers or the stack in | |
3423 | register-sized pieces. Large arguments are split between | |
3424 | registers and stack. */ | |
4246e332 | 3425 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3426 | mips_abi_regsize() are treated specially: Irix cc passes |
3427 | them in registers where gcc sometimes puts them on the | |
3428 | stack. For maximum compatibility, we will put them in | |
3429 | both places. */ | |
13326b4e AC |
3430 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3431 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
cb3d25d1 | 3432 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3433 | register are only written to memory. */ |
cb3d25d1 MS |
3434 | while (len > 0) |
3435 | { | |
3436 | /* Rememer if the argument was written to the stack. */ | |
3437 | int stack_used_p = 0; | |
13326b4e AC |
3438 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3439 | ? len : mips_abi_regsize (gdbarch)); | |
cb3d25d1 MS |
3440 | |
3441 | if (mips_debug) | |
3442 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3443 | partial_len); | |
3444 | ||
3445 | /* Write this portion of the argument to the stack. */ | |
3446 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3447 | || odd_sized_struct | |
3448 | || fp_register_arg_p (typecode, arg_type)) | |
3449 | { | |
3450 | /* Should shorter than int integer values be | |
3451 | promoted to int before being stored? */ | |
3452 | int longword_offset = 0; | |
3453 | CORE_ADDR addr; | |
3454 | stack_used_p = 1; | |
3455 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3456 | { | |
13326b4e | 3457 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3458 | && (typecode == TYPE_CODE_INT |
3459 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3460 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3461 | longword_offset = mips_stack_argsize (gdbarch) - len; |
cb3d25d1 MS |
3462 | } |
3463 | ||
3464 | if (mips_debug) | |
3465 | { | |
3466 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3467 | paddr_nz (stack_offset)); | |
3468 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3469 | paddr_nz (longword_offset)); | |
3470 | } | |
3471 | ||
3472 | addr = sp + stack_offset + longword_offset; | |
3473 | ||
3474 | if (mips_debug) | |
3475 | { | |
3476 | int i; | |
6d82d43b | 3477 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3478 | paddr_nz (addr)); |
3479 | for (i = 0; i < partial_len; i++) | |
3480 | { | |
6d82d43b | 3481 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3482 | val[i] & 0xff); |
3483 | } | |
3484 | } | |
3485 | write_memory (addr, val, partial_len); | |
3486 | } | |
3487 | ||
3488 | /* Note!!! This is NOT an else clause. Odd sized | |
3489 | structs may go thru BOTH paths. Floating point | |
3490 | arguments will not. */ | |
3491 | /* Write this portion of the argument to a general | |
6d82d43b | 3492 | purpose register. */ |
cb3d25d1 MS |
3493 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3494 | && !fp_register_arg_p (typecode, arg_type)) | |
3495 | { | |
6d82d43b AC |
3496 | LONGEST regval = |
3497 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3498 | |
3499 | /* A non-floating-point argument being passed in a | |
3500 | general register. If a struct or union, and if | |
3501 | the remaining length is smaller than the register | |
3502 | size, we have to adjust the register value on | |
3503 | big endian targets. | |
3504 | ||
3505 | It does not seem to be necessary to do the | |
3506 | same for integral types. | |
3507 | ||
3508 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3509 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3510 | mips_abi_regsize(), generates a left shift as |
cb3d25d1 MS |
3511 | part of storing the argument in a register a |
3512 | register (the left shift isn't generated when | |
1b13c4f6 | 3513 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3514 | it is quite possible that this is GCC |
3515 | contradicting the LE/O32 ABI, GDB has not been | |
3516 | adjusted to accommodate this. Either someone | |
3517 | needs to demonstrate that the LE/O32 ABI | |
3518 | specifies such a left shift OR this new ABI gets | |
3519 | identified as such and GDB gets tweaked | |
3520 | accordingly. */ | |
cb3d25d1 MS |
3521 | |
3522 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3523 | && partial_len < mips_abi_regsize (gdbarch) |
cb3d25d1 MS |
3524 | && (typecode == TYPE_CODE_STRUCT || |
3525 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3526 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
cb3d25d1 MS |
3527 | TARGET_CHAR_BIT); |
3528 | ||
3529 | if (mips_debug) | |
3530 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3531 | argreg, | |
6d82d43b | 3532 | phex (regval, |
13326b4e | 3533 | mips_abi_regsize (gdbarch))); |
cb3d25d1 MS |
3534 | write_register (argreg, regval); |
3535 | argreg++; | |
3536 | } | |
3537 | ||
3538 | len -= partial_len; | |
3539 | val += partial_len; | |
3540 | ||
3541 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3542 | will copy the next parameter. |
cb3d25d1 MS |
3543 | |
3544 | In N32 (N64?), the stack_offset only needs to be | |
3545 | adjusted when it has been used. */ | |
3546 | ||
3547 | if (stack_used_p) | |
480d3dd2 | 3548 | stack_offset += align_up (partial_len, |
13326b4e | 3549 | mips_stack_argsize (gdbarch)); |
cb3d25d1 MS |
3550 | } |
3551 | } | |
3552 | if (mips_debug) | |
3553 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3554 | } | |
3555 | ||
f10683bb | 3556 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3557 | |
cb3d25d1 MS |
3558 | /* Return adjusted stack pointer. */ |
3559 | return sp; | |
3560 | } | |
3561 | ||
6d82d43b AC |
3562 | static enum return_value_convention |
3563 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3564 | struct type *type, struct regcache *regcache, | |
3565 | void *readbuf, const void *writebuf) | |
ebafbe83 | 3566 | { |
6d82d43b AC |
3567 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3568 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3569 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3570 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
13326b4e | 3571 | || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
6d82d43b AC |
3572 | return RETURN_VALUE_STRUCT_CONVENTION; |
3573 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3574 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3575 | { | |
3576 | /* A floating-point value belongs in the least significant part | |
3577 | of FP0. */ | |
3578 | if (mips_debug) | |
3579 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3580 | mips_xfer_register (regcache, | |
3581 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3582 | TYPE_LENGTH (type), | |
3583 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3584 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3585 | } | |
3586 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3587 | && TYPE_NFIELDS (type) <= 2 | |
3588 | && TYPE_NFIELDS (type) >= 1 | |
3589 | && ((TYPE_NFIELDS (type) == 1 | |
3590 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3591 | == TYPE_CODE_FLT)) | |
3592 | || (TYPE_NFIELDS (type) == 2 | |
3593 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3594 | == TYPE_CODE_FLT) | |
3595 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3596 | == TYPE_CODE_FLT))) | |
3597 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3598 | { | |
3599 | /* A struct that contains one or two floats. Each value is part | |
3600 | in the least significant part of their floating point | |
3601 | register.. */ | |
6d82d43b AC |
3602 | int regnum; |
3603 | int field; | |
3604 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3605 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3606 | { | |
3607 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3608 | / TARGET_CHAR_BIT); | |
3609 | if (mips_debug) | |
3610 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3611 | offset); | |
3612 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3613 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3614 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3615 | } | |
3616 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3617 | } | |
3618 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3619 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3620 | { | |
3621 | /* A structure or union. Extract the left justified value, | |
3622 | regardless of the byte order. I.e. DO NOT USE | |
3623 | mips_xfer_lower. */ | |
3624 | int offset; | |
3625 | int regnum; | |
3626 | for (offset = 0, regnum = V0_REGNUM; | |
3627 | offset < TYPE_LENGTH (type); | |
3628 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3629 | { | |
3630 | int xfer = register_size (current_gdbarch, regnum); | |
3631 | if (offset + xfer > TYPE_LENGTH (type)) | |
3632 | xfer = TYPE_LENGTH (type) - offset; | |
3633 | if (mips_debug) | |
3634 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3635 | offset, xfer, regnum); | |
3636 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3637 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3638 | } | |
3639 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3640 | } | |
3641 | else | |
3642 | { | |
3643 | /* A scalar extract each part but least-significant-byte | |
3644 | justified. */ | |
3645 | int offset; | |
3646 | int regnum; | |
3647 | for (offset = 0, regnum = V0_REGNUM; | |
3648 | offset < TYPE_LENGTH (type); | |
3649 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3650 | { | |
3651 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3652 | if (offset + xfer > TYPE_LENGTH (type)) |
3653 | xfer = TYPE_LENGTH (type) - offset; | |
3654 | if (mips_debug) | |
3655 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3656 | offset, xfer, regnum); | |
3657 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3658 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3659 | } | |
3660 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3661 | } | |
3662 | } | |
3663 | ||
3664 | /* O32 ABI stuff. */ | |
3665 | ||
3666 | static CORE_ADDR | |
7d9b040b | 3667 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3668 | struct regcache *regcache, CORE_ADDR bp_addr, |
3669 | int nargs, struct value **args, CORE_ADDR sp, | |
3670 | int struct_return, CORE_ADDR struct_addr) | |
3671 | { | |
3672 | int argreg; | |
3673 | int float_argreg; | |
3674 | int argnum; | |
3675 | int len = 0; | |
3676 | int stack_offset = 0; | |
3677 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3678 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3679 | |
3680 | /* For shared libraries, "t9" needs to point at the function | |
3681 | address. */ | |
3682 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3683 | ||
3684 | /* Set the return address register to point to the entry point of | |
3685 | the program, where a breakpoint lies in wait. */ | |
3686 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3687 | ||
3688 | /* First ensure that the stack and structure return address (if any) | |
3689 | are properly aligned. The stack has to be at least 64-bit | |
3690 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3691 | aligned. For n32 and n64, stack frames need to be 128-bit |
3692 | aligned, so we round to this widest known alignment. */ | |
3693 | ||
5b03f266 AC |
3694 | sp = align_down (sp, 16); |
3695 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3696 | |
3697 | /* Now make space on the stack for the args. */ | |
3698 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3699 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3700 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3701 | sp -= align_up (len, 16); |
ebafbe83 MS |
3702 | |
3703 | if (mips_debug) | |
6d82d43b | 3704 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3705 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3706 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3707 | |
3708 | /* Initialize the integer and float register pointers. */ | |
3709 | argreg = A0_REGNUM; | |
56cea623 | 3710 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3711 | |
bcb0cc15 | 3712 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3713 | if (struct_return) |
3714 | { | |
3715 | if (mips_debug) | |
3716 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3717 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3718 | argreg, paddr_nz (struct_addr)); |
3719 | write_register (argreg++, struct_addr); | |
13326b4e | 3720 | stack_offset += mips_stack_argsize (gdbarch); |
ebafbe83 MS |
3721 | } |
3722 | ||
3723 | /* Now load as many as possible of the first arguments into | |
3724 | registers, and push the rest onto the stack. Loop thru args | |
3725 | from first to last. */ | |
3726 | for (argnum = 0; argnum < nargs; argnum++) | |
3727 | { | |
3728 | char *val; | |
ebafbe83 MS |
3729 | struct value *arg = args[argnum]; |
3730 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3731 | int len = TYPE_LENGTH (arg_type); | |
3732 | enum type_code typecode = TYPE_CODE (arg_type); | |
3733 | ||
3734 | if (mips_debug) | |
3735 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3736 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3737 | argnum + 1, len, (int) typecode); |
3738 | ||
3739 | val = (char *) VALUE_CONTENTS (arg); | |
3740 | ||
3741 | /* 32-bit ABIs always start floating point arguments in an | |
3742 | even-numbered floating point register. Round the FP register | |
3743 | up before the check to see if there are any FP registers | |
3744 | left. O32/O64 targets also pass the FP in the integer | |
3745 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3746 | if (mips_abi_regsize (gdbarch) < 8 |
3747 | && fp_register_arg_p (typecode, arg_type)) | |
46cac009 AC |
3748 | { |
3749 | if ((float_argreg & 1)) | |
3750 | float_argreg++; | |
3751 | } | |
3752 | ||
3753 | /* Floating point arguments passed in registers have to be | |
3754 | treated specially. On 32-bit architectures, doubles | |
3755 | are passed in register pairs; the even register gets | |
3756 | the low word, and the odd register gets the high word. | |
3757 | On O32/O64, the first two floating point arguments are | |
3758 | also copied to general registers, because MIPS16 functions | |
3759 | don't use float registers for arguments. This duplication of | |
3760 | arguments in general registers can't hurt non-MIPS16 functions | |
3761 | because those registers are normally skipped. */ | |
3762 | ||
3763 | if (fp_register_arg_p (typecode, arg_type) | |
3764 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3765 | { | |
ceae6e75 | 3766 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
46cac009 AC |
3767 | { |
3768 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3769 | unsigned long regval; | |
3770 | ||
3771 | /* Write the low word of the double to the even register(s). */ | |
3772 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3773 | if (mips_debug) | |
3774 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3775 | float_argreg, phex (regval, 4)); | |
3776 | write_register (float_argreg++, regval); | |
3777 | if (mips_debug) | |
3778 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3779 | argreg, phex (regval, 4)); | |
3780 | write_register (argreg++, regval); | |
3781 | ||
3782 | /* Write the high word of the double to the odd register(s). */ | |
3783 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3784 | if (mips_debug) | |
3785 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3786 | float_argreg, phex (regval, 4)); | |
3787 | write_register (float_argreg++, regval); | |
3788 | ||
3789 | if (mips_debug) | |
3790 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3791 | argreg, phex (regval, 4)); | |
3792 | write_register (argreg++, regval); | |
3793 | } | |
3794 | else | |
3795 | { | |
3796 | /* This is a floating point value that fits entirely | |
3797 | in a single register. */ | |
3798 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3799 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3800 | LONGEST regval = extract_unsigned_integer (val, len); |
3801 | if (mips_debug) | |
3802 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3803 | float_argreg, phex (regval, len)); | |
3804 | write_register (float_argreg++, regval); | |
3805 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3806 | registers for each argument. The below is (my |
3807 | guess) to ensure that the corresponding integer | |
3808 | register has reserved the same space. */ | |
46cac009 AC |
3809 | if (mips_debug) |
3810 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3811 | argreg, phex (regval, len)); | |
3812 | write_register (argreg, regval); | |
ceae6e75 | 3813 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
46cac009 AC |
3814 | } |
3815 | /* Reserve space for the FP register. */ | |
13326b4e | 3816 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
46cac009 AC |
3817 | } |
3818 | else | |
3819 | { | |
3820 | /* Copy the argument to general registers or the stack in | |
3821 | register-sized pieces. Large arguments are split between | |
3822 | registers and stack. */ | |
4246e332 | 3823 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3824 | mips_abi_regsize() are treated specially: Irix cc passes |
3825 | them in registers where gcc sometimes puts them on the | |
3826 | stack. For maximum compatibility, we will put them in | |
3827 | both places. */ | |
13326b4e AC |
3828 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3829 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46cac009 AC |
3830 | /* Structures should be aligned to eight bytes (even arg registers) |
3831 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 3832 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 AC |
3833 | && mips_type_needs_double_align (arg_type)) |
3834 | { | |
3835 | if ((argreg & 1)) | |
6d82d43b | 3836 | argreg++; |
46cac009 AC |
3837 | } |
3838 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3839 | register are only written to memory. */ |
46cac009 AC |
3840 | while (len > 0) |
3841 | { | |
3842 | /* Remember if the argument was written to the stack. */ | |
3843 | int stack_used_p = 0; | |
13326b4e AC |
3844 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3845 | ? len : mips_abi_regsize (gdbarch)); | |
46cac009 AC |
3846 | |
3847 | if (mips_debug) | |
3848 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3849 | partial_len); | |
3850 | ||
3851 | /* Write this portion of the argument to the stack. */ | |
3852 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3853 | || odd_sized_struct | |
3854 | || fp_register_arg_p (typecode, arg_type)) | |
3855 | { | |
3856 | /* Should shorter than int integer values be | |
3857 | promoted to int before being stored? */ | |
3858 | int longword_offset = 0; | |
3859 | CORE_ADDR addr; | |
3860 | stack_used_p = 1; | |
3861 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3862 | { | |
13326b4e | 3863 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3864 | && (typecode == TYPE_CODE_INT |
3865 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3866 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3867 | longword_offset = mips_stack_argsize (gdbarch) - len; |
46cac009 AC |
3868 | } |
3869 | ||
3870 | if (mips_debug) | |
3871 | { | |
3872 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3873 | paddr_nz (stack_offset)); | |
3874 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3875 | paddr_nz (longword_offset)); | |
3876 | } | |
3877 | ||
3878 | addr = sp + stack_offset + longword_offset; | |
3879 | ||
3880 | if (mips_debug) | |
3881 | { | |
3882 | int i; | |
6d82d43b | 3883 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3884 | paddr_nz (addr)); |
3885 | for (i = 0; i < partial_len; i++) | |
3886 | { | |
6d82d43b | 3887 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3888 | val[i] & 0xff); |
3889 | } | |
3890 | } | |
3891 | write_memory (addr, val, partial_len); | |
3892 | } | |
3893 | ||
3894 | /* Note!!! This is NOT an else clause. Odd sized | |
3895 | structs may go thru BOTH paths. Floating point | |
3896 | arguments will not. */ | |
3897 | /* Write this portion of the argument to a general | |
6d82d43b | 3898 | purpose register. */ |
46cac009 AC |
3899 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3900 | && !fp_register_arg_p (typecode, arg_type)) | |
3901 | { | |
3902 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3903 | /* Value may need to be sign extended, because |
1b13c4f6 | 3904 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3905 | |
3906 | /* A non-floating-point argument being passed in a | |
3907 | general register. If a struct or union, and if | |
3908 | the remaining length is smaller than the register | |
3909 | size, we have to adjust the register value on | |
3910 | big endian targets. | |
3911 | ||
3912 | It does not seem to be necessary to do the | |
3913 | same for integral types. | |
3914 | ||
3915 | Also don't do this adjustment on O64 binaries. | |
3916 | ||
3917 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3918 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3919 | mips_abi_regsize(), generates a left shift as |
46cac009 AC |
3920 | part of storing the argument in a register a |
3921 | register (the left shift isn't generated when | |
1b13c4f6 | 3922 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3923 | it is quite possible that this is GCC |
3924 | contradicting the LE/O32 ABI, GDB has not been | |
3925 | adjusted to accommodate this. Either someone | |
3926 | needs to demonstrate that the LE/O32 ABI | |
3927 | specifies such a left shift OR this new ABI gets | |
3928 | identified as such and GDB gets tweaked | |
3929 | accordingly. */ | |
3930 | ||
13326b4e | 3931 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 | 3932 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 3933 | && partial_len < mips_abi_regsize (gdbarch) |
46cac009 AC |
3934 | && (typecode == TYPE_CODE_STRUCT || |
3935 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3936 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
46cac009 AC |
3937 | TARGET_CHAR_BIT); |
3938 | ||
3939 | if (mips_debug) | |
3940 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3941 | argreg, | |
6d82d43b | 3942 | phex (regval, |
13326b4e | 3943 | mips_abi_regsize (gdbarch))); |
46cac009 AC |
3944 | write_register (argreg, regval); |
3945 | argreg++; | |
3946 | ||
3947 | /* Prevent subsequent floating point arguments from | |
3948 | being passed in floating point registers. */ | |
3949 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3950 | } | |
3951 | ||
3952 | len -= partial_len; | |
3953 | val += partial_len; | |
3954 | ||
3955 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3956 | will copy the next parameter. |
46cac009 | 3957 | |
6d82d43b AC |
3958 | In older ABIs, the caller reserved space for |
3959 | registers that contained arguments. This was loosely | |
3960 | refered to as their "home". Consequently, space is | |
3961 | always allocated. */ | |
46cac009 | 3962 | |
480d3dd2 | 3963 | stack_offset += align_up (partial_len, |
13326b4e | 3964 | mips_stack_argsize (gdbarch)); |
46cac009 AC |
3965 | } |
3966 | } | |
3967 | if (mips_debug) | |
3968 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3969 | } | |
3970 | ||
f10683bb | 3971 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3972 | |
46cac009 AC |
3973 | /* Return adjusted stack pointer. */ |
3974 | return sp; | |
3975 | } | |
3976 | ||
6d82d43b AC |
3977 | static enum return_value_convention |
3978 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3979 | struct regcache *regcache, | |
3980 | void *readbuf, const void *writebuf) | |
3981 | { | |
3982 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3983 | ||
3984 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3985 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3986 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3987 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3988 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3989 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3990 | { | |
3991 | /* A single-precision floating-point value. It fits in the | |
3992 | least significant part of FP0. */ | |
3993 | if (mips_debug) | |
3994 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3995 | mips_xfer_register (regcache, | |
3996 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3997 | TYPE_LENGTH (type), | |
3998 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3999 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4000 | } | |
4001 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4002 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4003 | { | |
4004 | /* A double-precision floating-point value. The most | |
4005 | significant part goes in FP1, and the least significant in | |
4006 | FP0. */ | |
4007 | if (mips_debug) | |
4008 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4009 | switch (TARGET_BYTE_ORDER) | |
4010 | { | |
4011 | case BFD_ENDIAN_LITTLE: | |
4012 | mips_xfer_register (regcache, | |
4013 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4014 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4015 | mips_xfer_register (regcache, | |
4016 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4017 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
4018 | break; | |
4019 | case BFD_ENDIAN_BIG: | |
4020 | mips_xfer_register (regcache, | |
4021 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4022 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4023 | mips_xfer_register (regcache, | |
4024 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4025 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
4026 | break; | |
4027 | default: | |
4028 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4029 | } | |
4030 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4031 | } | |
4032 | #if 0 | |
4033 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4034 | && TYPE_NFIELDS (type) <= 2 | |
4035 | && TYPE_NFIELDS (type) >= 1 | |
4036 | && ((TYPE_NFIELDS (type) == 1 | |
4037 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4038 | == TYPE_CODE_FLT)) | |
4039 | || (TYPE_NFIELDS (type) == 2 | |
4040 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4041 | == TYPE_CODE_FLT) | |
4042 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4043 | == TYPE_CODE_FLT))) | |
4044 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4045 | { | |
4046 | /* A struct that contains one or two floats. Each value is part | |
4047 | in the least significant part of their floating point | |
4048 | register.. */ | |
4049 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
4050 | int regnum; | |
4051 | int field; | |
4052 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
4053 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
4054 | { | |
4055 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4056 | / TARGET_CHAR_BIT); | |
4057 | if (mips_debug) | |
4058 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4059 | offset); | |
4060 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
4061 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4062 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4063 | } | |
4064 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4065 | } | |
4066 | #endif | |
4067 | #if 0 | |
4068 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4069 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4070 | { | |
4071 | /* A structure or union. Extract the left justified value, | |
4072 | regardless of the byte order. I.e. DO NOT USE | |
4073 | mips_xfer_lower. */ | |
4074 | int offset; | |
4075 | int regnum; | |
4076 | for (offset = 0, regnum = V0_REGNUM; | |
4077 | offset < TYPE_LENGTH (type); | |
4078 | offset += register_size (current_gdbarch, regnum), regnum++) | |
4079 | { | |
4080 | int xfer = register_size (current_gdbarch, regnum); | |
4081 | if (offset + xfer > TYPE_LENGTH (type)) | |
4082 | xfer = TYPE_LENGTH (type) - offset; | |
4083 | if (mips_debug) | |
4084 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4085 | offset, xfer, regnum); | |
4086 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4087 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
4088 | } | |
4089 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4090 | } | |
4091 | #endif | |
4092 | else | |
4093 | { | |
4094 | /* A scalar extract each part but least-significant-byte | |
4095 | justified. o32 thinks registers are 4 byte, regardless of | |
4096 | the ISA. mips_stack_argsize controls this. */ | |
4097 | int offset; | |
4098 | int regnum; | |
4099 | for (offset = 0, regnum = V0_REGNUM; | |
4100 | offset < TYPE_LENGTH (type); | |
13326b4e | 4101 | offset += mips_stack_argsize (gdbarch), regnum++) |
6d82d43b | 4102 | { |
13326b4e | 4103 | int xfer = mips_stack_argsize (gdbarch); |
6d82d43b AC |
4104 | if (offset + xfer > TYPE_LENGTH (type)) |
4105 | xfer = TYPE_LENGTH (type) - offset; | |
4106 | if (mips_debug) | |
4107 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4108 | offset, xfer, regnum); | |
4109 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4110 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4111 | } | |
4112 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4113 | } | |
4114 | } | |
4115 | ||
4116 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4117 | ABI. */ | |
46cac009 AC |
4118 | |
4119 | static CORE_ADDR | |
7d9b040b | 4120 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4121 | struct regcache *regcache, CORE_ADDR bp_addr, |
4122 | int nargs, | |
4123 | struct value **args, CORE_ADDR sp, | |
4124 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4125 | { |
4126 | int argreg; | |
4127 | int float_argreg; | |
4128 | int argnum; | |
4129 | int len = 0; | |
4130 | int stack_offset = 0; | |
480d3dd2 | 4131 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 4132 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4133 | |
25ab4790 AC |
4134 | /* For shared libraries, "t9" needs to point at the function |
4135 | address. */ | |
4136 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
4137 | ||
4138 | /* Set the return address register to point to the entry point of | |
4139 | the program, where a breakpoint lies in wait. */ | |
4140 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
4141 | ||
46cac009 AC |
4142 | /* First ensure that the stack and structure return address (if any) |
4143 | are properly aligned. The stack has to be at least 64-bit | |
4144 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4145 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4146 | aligned, so we round to this widest known alignment. */ | |
4147 | ||
5b03f266 AC |
4148 | sp = align_down (sp, 16); |
4149 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4150 | |
4151 | /* Now make space on the stack for the args. */ | |
4152 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 4153 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 4154 | mips_stack_argsize (gdbarch)); |
5b03f266 | 4155 | sp -= align_up (len, 16); |
46cac009 AC |
4156 | |
4157 | if (mips_debug) | |
6d82d43b | 4158 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
4159 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
4160 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
4161 | |
4162 | /* Initialize the integer and float register pointers. */ | |
4163 | argreg = A0_REGNUM; | |
56cea623 | 4164 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
4165 | |
4166 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4167 | if (struct_return) | |
4168 | { | |
4169 | if (mips_debug) | |
4170 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4171 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
4172 | argreg, paddr_nz (struct_addr)); |
4173 | write_register (argreg++, struct_addr); | |
13326b4e | 4174 | stack_offset += mips_stack_argsize (gdbarch); |
46cac009 AC |
4175 | } |
4176 | ||
4177 | /* Now load as many as possible of the first arguments into | |
4178 | registers, and push the rest onto the stack. Loop thru args | |
4179 | from first to last. */ | |
4180 | for (argnum = 0; argnum < nargs; argnum++) | |
4181 | { | |
4182 | char *val; | |
46cac009 AC |
4183 | struct value *arg = args[argnum]; |
4184 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4185 | int len = TYPE_LENGTH (arg_type); | |
4186 | enum type_code typecode = TYPE_CODE (arg_type); | |
4187 | ||
4188 | if (mips_debug) | |
4189 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4190 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4191 | argnum + 1, len, (int) typecode); |
4192 | ||
4193 | val = (char *) VALUE_CONTENTS (arg); | |
4194 | ||
4195 | /* 32-bit ABIs always start floating point arguments in an | |
4196 | even-numbered floating point register. Round the FP register | |
4197 | up before the check to see if there are any FP registers | |
4198 | left. O32/O64 targets also pass the FP in the integer | |
4199 | registers so also round up normal registers. */ | |
ceae6e75 AC |
4200 | if (mips_abi_regsize (gdbarch) < 8 |
4201 | && fp_register_arg_p (typecode, arg_type)) | |
ebafbe83 MS |
4202 | { |
4203 | if ((float_argreg & 1)) | |
4204 | float_argreg++; | |
4205 | } | |
4206 | ||
4207 | /* Floating point arguments passed in registers have to be | |
4208 | treated specially. On 32-bit architectures, doubles | |
4209 | are passed in register pairs; the even register gets | |
4210 | the low word, and the odd register gets the high word. | |
4211 | On O32/O64, the first two floating point arguments are | |
4212 | also copied to general registers, because MIPS16 functions | |
4213 | don't use float registers for arguments. This duplication of | |
4214 | arguments in general registers can't hurt non-MIPS16 functions | |
4215 | because those registers are normally skipped. */ | |
4216 | ||
4217 | if (fp_register_arg_p (typecode, arg_type) | |
4218 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4219 | { | |
ceae6e75 | 4220 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
ebafbe83 MS |
4221 | { |
4222 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4223 | unsigned long regval; | |
4224 | ||
4225 | /* Write the low word of the double to the even register(s). */ | |
4226 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4227 | if (mips_debug) | |
4228 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4229 | float_argreg, phex (regval, 4)); | |
4230 | write_register (float_argreg++, regval); | |
4231 | if (mips_debug) | |
4232 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4233 | argreg, phex (regval, 4)); | |
4234 | write_register (argreg++, regval); | |
4235 | ||
4236 | /* Write the high word of the double to the odd register(s). */ | |
4237 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4238 | if (mips_debug) | |
4239 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4240 | float_argreg, phex (regval, 4)); | |
4241 | write_register (float_argreg++, regval); | |
4242 | ||
4243 | if (mips_debug) | |
4244 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4245 | argreg, phex (regval, 4)); | |
4246 | write_register (argreg++, regval); | |
4247 | } | |
4248 | else | |
4249 | { | |
4250 | /* This is a floating point value that fits entirely | |
4251 | in a single register. */ | |
4252 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4253 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
4254 | LONGEST regval = extract_unsigned_integer (val, len); |
4255 | if (mips_debug) | |
4256 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4257 | float_argreg, phex (regval, len)); | |
4258 | write_register (float_argreg++, regval); | |
4259 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4260 | registers for each argument. The below is (my |
4261 | guess) to ensure that the corresponding integer | |
4262 | register has reserved the same space. */ | |
ebafbe83 MS |
4263 | if (mips_debug) |
4264 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4265 | argreg, phex (regval, len)); | |
4266 | write_register (argreg, regval); | |
ceae6e75 | 4267 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
ebafbe83 MS |
4268 | } |
4269 | /* Reserve space for the FP register. */ | |
13326b4e | 4270 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4271 | } |
4272 | else | |
4273 | { | |
4274 | /* Copy the argument to general registers or the stack in | |
4275 | register-sized pieces. Large arguments are split between | |
4276 | registers and stack. */ | |
4246e332 | 4277 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4278 | mips_abi_regsize() are treated specially: Irix cc passes |
4279 | them in registers where gcc sometimes puts them on the | |
4280 | stack. For maximum compatibility, we will put them in | |
4281 | both places. */ | |
13326b4e AC |
4282 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4283 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
ebafbe83 MS |
4284 | /* Structures should be aligned to eight bytes (even arg registers) |
4285 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4286 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 MS |
4287 | && mips_type_needs_double_align (arg_type)) |
4288 | { | |
4289 | if ((argreg & 1)) | |
6d82d43b | 4290 | argreg++; |
ebafbe83 MS |
4291 | } |
4292 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4293 | register are only written to memory. */ |
ebafbe83 MS |
4294 | while (len > 0) |
4295 | { | |
4296 | /* Remember if the argument was written to the stack. */ | |
4297 | int stack_used_p = 0; | |
13326b4e AC |
4298 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4299 | ? len : mips_abi_regsize (gdbarch)); | |
ebafbe83 MS |
4300 | |
4301 | if (mips_debug) | |
4302 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4303 | partial_len); | |
4304 | ||
4305 | /* Write this portion of the argument to the stack. */ | |
4306 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4307 | || odd_sized_struct | |
4308 | || fp_register_arg_p (typecode, arg_type)) | |
4309 | { | |
4310 | /* Should shorter than int integer values be | |
4311 | promoted to int before being stored? */ | |
4312 | int longword_offset = 0; | |
4313 | CORE_ADDR addr; | |
4314 | stack_used_p = 1; | |
4315 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4316 | { | |
13326b4e | 4317 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4318 | && (typecode == TYPE_CODE_INT |
4319 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4320 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4321 | longword_offset = mips_stack_argsize (gdbarch) - len; |
ebafbe83 MS |
4322 | } |
4323 | ||
4324 | if (mips_debug) | |
4325 | { | |
4326 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4327 | paddr_nz (stack_offset)); | |
4328 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4329 | paddr_nz (longword_offset)); | |
4330 | } | |
4331 | ||
4332 | addr = sp + stack_offset + longword_offset; | |
4333 | ||
4334 | if (mips_debug) | |
4335 | { | |
4336 | int i; | |
6d82d43b | 4337 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4338 | paddr_nz (addr)); |
4339 | for (i = 0; i < partial_len; i++) | |
4340 | { | |
6d82d43b | 4341 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4342 | val[i] & 0xff); |
4343 | } | |
4344 | } | |
4345 | write_memory (addr, val, partial_len); | |
4346 | } | |
4347 | ||
4348 | /* Note!!! This is NOT an else clause. Odd sized | |
4349 | structs may go thru BOTH paths. Floating point | |
4350 | arguments will not. */ | |
4351 | /* Write this portion of the argument to a general | |
6d82d43b | 4352 | purpose register. */ |
ebafbe83 MS |
4353 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4354 | && !fp_register_arg_p (typecode, arg_type)) | |
4355 | { | |
4356 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4357 | /* Value may need to be sign extended, because |
1b13c4f6 | 4358 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4359 | |
4360 | /* A non-floating-point argument being passed in a | |
4361 | general register. If a struct or union, and if | |
4362 | the remaining length is smaller than the register | |
4363 | size, we have to adjust the register value on | |
4364 | big endian targets. | |
4365 | ||
4366 | It does not seem to be necessary to do the | |
4367 | same for integral types. | |
4368 | ||
4369 | Also don't do this adjustment on O64 binaries. | |
4370 | ||
4371 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4372 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4373 | mips_abi_regsize(), generates a left shift as |
ebafbe83 MS |
4374 | part of storing the argument in a register a |
4375 | register (the left shift isn't generated when | |
1b13c4f6 | 4376 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4377 | it is quite possible that this is GCC |
4378 | contradicting the LE/O32 ABI, GDB has not been | |
4379 | adjusted to accommodate this. Either someone | |
4380 | needs to demonstrate that the LE/O32 ABI | |
4381 | specifies such a left shift OR this new ABI gets | |
4382 | identified as such and GDB gets tweaked | |
4383 | accordingly. */ | |
4384 | ||
13326b4e | 4385 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 | 4386 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4387 | && partial_len < mips_abi_regsize (gdbarch) |
ebafbe83 MS |
4388 | && (typecode == TYPE_CODE_STRUCT || |
4389 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4390 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
ebafbe83 MS |
4391 | TARGET_CHAR_BIT); |
4392 | ||
4393 | if (mips_debug) | |
4394 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4395 | argreg, | |
6d82d43b | 4396 | phex (regval, |
13326b4e | 4397 | mips_abi_regsize (gdbarch))); |
ebafbe83 MS |
4398 | write_register (argreg, regval); |
4399 | argreg++; | |
4400 | ||
4401 | /* Prevent subsequent floating point arguments from | |
4402 | being passed in floating point registers. */ | |
4403 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4404 | } | |
4405 | ||
4406 | len -= partial_len; | |
4407 | val += partial_len; | |
4408 | ||
4409 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4410 | will copy the next parameter. |
ebafbe83 | 4411 | |
6d82d43b AC |
4412 | In older ABIs, the caller reserved space for |
4413 | registers that contained arguments. This was loosely | |
4414 | refered to as their "home". Consequently, space is | |
4415 | always allocated. */ | |
ebafbe83 | 4416 | |
480d3dd2 | 4417 | stack_offset += align_up (partial_len, |
13326b4e | 4418 | mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4419 | } |
4420 | } | |
4421 | if (mips_debug) | |
4422 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4423 | } | |
4424 | ||
f10683bb | 4425 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4426 | |
ebafbe83 MS |
4427 | /* Return adjusted stack pointer. */ |
4428 | return sp; | |
4429 | } | |
4430 | ||
f7ab6ec6 | 4431 | static void |
6d82d43b AC |
4432 | mips_o64_extract_return_value (struct type *valtype, |
4433 | char regbuf[], char *valbuf) | |
c906108c | 4434 | { |
6d82d43b AC |
4435 | struct return_value_word lo; |
4436 | struct return_value_word hi; | |
4437 | return_value_location (valtype, &hi, &lo); | |
c906108c | 4438 | |
6d82d43b AC |
4439 | memcpy (valbuf + lo.buf_offset, |
4440 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
4441 | lo.reg_offset, lo.len); | |
4442 | ||
4443 | if (hi.len > 0) | |
4444 | memcpy (valbuf + hi.buf_offset, | |
4445 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
4446 | hi.reg_offset, hi.len); | |
4447 | } | |
4448 | ||
4449 | static void | |
4450 | mips_o64_store_return_value (struct type *valtype, char *valbuf) | |
4451 | { | |
4452 | char raw_buffer[MAX_REGISTER_SIZE]; | |
4453 | struct return_value_word lo; | |
4454 | struct return_value_word hi; | |
4455 | return_value_location (valtype, &hi, &lo); | |
4456 | ||
4457 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4458 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4459 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
4460 | raw_buffer, register_size (current_gdbarch, | |
4461 | lo.reg)); | |
4462 | ||
4463 | if (hi.len > 0) | |
4464 | { | |
4465 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4466 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4467 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
4468 | raw_buffer, | |
4469 | register_size (current_gdbarch, | |
4470 | hi.reg)); | |
4471 | } | |
4472 | } | |
4473 | ||
dd824b04 DJ |
4474 | /* Floating point register management. |
4475 | ||
4476 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4477 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4478 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4479 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4480 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4481 | double precision floats into two 32-bit chunks and store them in | |
4482 | consecutive fp regs. To display 64-bit floats stored in this | |
4483 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4484 | Throw in user-configurable endianness and you have a real mess. | |
4485 | ||
4486 | The way this works is: | |
4487 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4488 | double-precision value will be split across two logical registers. | |
4489 | The lower-numbered logical register will hold the low-order bits, | |
4490 | regardless of the processor's endianness. | |
4491 | - If we are on a 64-bit processor, and we are looking for a | |
4492 | single-precision value, it will be in the low ordered bits | |
4493 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4494 | save slot in memory. | |
4495 | - If we are in 64-bit mode, everything is straightforward. | |
4496 | ||
4497 | Note that this code only deals with "live" registers at the top of the | |
4498 | stack. We will attempt to deal with saved registers later, when | |
4499 | the raw/cooked register interface is in place. (We need a general | |
4500 | interface that can deal with dynamic saved register sizes -- fp | |
4501 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4502 | and below). */ | |
4503 | ||
67b2c998 DJ |
4504 | static struct type * |
4505 | mips_float_register_type (void) | |
4506 | { | |
361d1df0 | 4507 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4508 | return builtin_type_ieee_single_big; |
4509 | else | |
4510 | return builtin_type_ieee_single_little; | |
4511 | } | |
4512 | ||
4513 | static struct type * | |
4514 | mips_double_register_type (void) | |
4515 | { | |
361d1df0 | 4516 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4517 | return builtin_type_ieee_double_big; |
4518 | else | |
4519 | return builtin_type_ieee_double_little; | |
4520 | } | |
4521 | ||
dd824b04 DJ |
4522 | /* Copy a 32-bit single-precision value from the current frame |
4523 | into rare_buffer. */ | |
4524 | ||
4525 | static void | |
e11c53d2 AC |
4526 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4527 | char *rare_buffer) | |
dd824b04 | 4528 | { |
719ec221 | 4529 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4530 | char *raw_buffer = alloca (raw_size); |
4531 | ||
e11c53d2 | 4532 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4533 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4534 | if (raw_size == 8) | |
4535 | { | |
4536 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4537 | 32 bits. */ |
dd824b04 DJ |
4538 | int offset; |
4539 | ||
4540 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4541 | offset = 4; | |
4542 | else | |
4543 | offset = 0; | |
4544 | ||
4545 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4546 | } | |
4547 | else | |
4548 | { | |
4549 | memcpy (rare_buffer, raw_buffer, 4); | |
4550 | } | |
4551 | } | |
4552 | ||
4553 | /* Copy a 64-bit double-precision value from the current frame into | |
4554 | rare_buffer. This may include getting half of it from the next | |
4555 | register. */ | |
4556 | ||
4557 | static void | |
e11c53d2 AC |
4558 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4559 | char *rare_buffer) | |
dd824b04 | 4560 | { |
719ec221 | 4561 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4562 | |
4563 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4564 | { | |
4565 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4566 | all 64 bits. */ |
e11c53d2 | 4567 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4568 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4569 | } | |
4570 | else | |
4571 | { | |
56cea623 | 4572 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4573 | internal_error (__FILE__, __LINE__, |
4574 | "mips_read_fp_register_double: bad access to " | |
4575 | "odd-numbered FP register"); | |
4576 | ||
4577 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4578 | each register. */ |
dd824b04 DJ |
4579 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
4580 | { | |
e11c53d2 AC |
4581 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4582 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4583 | } |
361d1df0 | 4584 | else |
dd824b04 | 4585 | { |
e11c53d2 AC |
4586 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4587 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4588 | } |
4589 | } | |
4590 | } | |
4591 | ||
c906108c | 4592 | static void |
e11c53d2 AC |
4593 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4594 | int regnum) | |
c5aa993b | 4595 | { /* do values for FP (float) regs */ |
dd824b04 | 4596 | char *raw_buffer; |
3903d437 AC |
4597 | double doub, flt1; /* doubles extracted from raw hex data */ |
4598 | int inv1, inv2; | |
c5aa993b | 4599 | |
6d82d43b AC |
4600 | raw_buffer = |
4601 | (char *) alloca (2 * | |
4602 | register_size (current_gdbarch, | |
4603 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4604 | |
e11c53d2 AC |
4605 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4606 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4607 | ""); | |
f0ef6b29 | 4608 | |
719ec221 | 4609 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4610 | { |
f0ef6b29 KB |
4611 | /* 4-byte registers: Print hex and floating. Also print even |
4612 | numbered registers as doubles. */ | |
e11c53d2 | 4613 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4614 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4615 | |
6d82d43b AC |
4616 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4617 | file); | |
dd824b04 | 4618 | |
e11c53d2 | 4619 | fprintf_filtered (file, " flt: "); |
1adad886 | 4620 | if (inv1) |
e11c53d2 | 4621 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4622 | else |
e11c53d2 | 4623 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4624 | |
f0ef6b29 KB |
4625 | if (regnum % 2 == 0) |
4626 | { | |
e11c53d2 | 4627 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4628 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4629 | &inv2); |
1adad886 | 4630 | |
e11c53d2 | 4631 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4632 | if (inv2) |
e11c53d2 | 4633 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4634 | else |
e11c53d2 | 4635 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4636 | } |
c906108c SS |
4637 | } |
4638 | else | |
dd824b04 | 4639 | { |
f0ef6b29 | 4640 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4641 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4642 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4643 | |
e11c53d2 | 4644 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4645 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4646 | ||
361d1df0 | 4647 | |
6d82d43b AC |
4648 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4649 | file); | |
f0ef6b29 | 4650 | |
e11c53d2 | 4651 | fprintf_filtered (file, " flt: "); |
1adad886 | 4652 | if (inv1) |
e11c53d2 | 4653 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4654 | else |
e11c53d2 | 4655 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4656 | |
e11c53d2 | 4657 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4658 | if (inv2) |
e11c53d2 | 4659 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4660 | else |
e11c53d2 | 4661 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4662 | } |
4663 | } | |
4664 | ||
4665 | static void | |
e11c53d2 AC |
4666 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4667 | int regnum, int all) | |
f0ef6b29 | 4668 | { |
a4b8ebc8 | 4669 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4670 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4671 | int offset; |
1adad886 | 4672 | |
a4b8ebc8 | 4673 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4674 | { |
e11c53d2 | 4675 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4676 | return; |
4677 | } | |
4678 | ||
4679 | /* Get the data in raw format. */ | |
e11c53d2 | 4680 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4681 | { |
e11c53d2 | 4682 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4683 | return; |
c906108c | 4684 | } |
f0ef6b29 | 4685 | |
e11c53d2 | 4686 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4687 | |
4688 | /* The problem with printing numeric register names (r26, etc.) is that | |
4689 | the user can't use them on input. Probably the best solution is to | |
4690 | fix it so that either the numeric or the funky (a2, etc.) names | |
4691 | are accepted on input. */ | |
4692 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4693 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4694 | else |
e11c53d2 | 4695 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4696 | |
4697 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
4698 | offset = |
4699 | register_size (current_gdbarch, | |
4700 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4701 | else |
4702 | offset = 0; | |
4703 | ||
6d82d43b AC |
4704 | print_scalar_formatted (raw_buffer + offset, |
4705 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
4706 | file); | |
c906108c SS |
4707 | } |
4708 | ||
f0ef6b29 KB |
4709 | /* Replacement for generic do_registers_info. |
4710 | Print regs in pretty columns. */ | |
4711 | ||
4712 | static int | |
e11c53d2 AC |
4713 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4714 | int regnum) | |
f0ef6b29 | 4715 | { |
e11c53d2 AC |
4716 | fprintf_filtered (file, " "); |
4717 | mips_print_fp_register (file, frame, regnum); | |
4718 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4719 | return regnum + 1; |
4720 | } | |
4721 | ||
4722 | ||
c906108c SS |
4723 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4724 | ||
4725 | static int | |
e11c53d2 | 4726 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4727 | int start_regnum) |
c906108c | 4728 | { |
a4b8ebc8 | 4729 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4730 | /* do values for GP (int) regs */ |
d9d9c31f | 4731 | char raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4732 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4733 | int col, byte; |
a4b8ebc8 | 4734 | int regnum; |
c906108c SS |
4735 | |
4736 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4737 | fprintf_filtered (file, " "); |
a4b8ebc8 | 4738 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4739 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4740 | { |
4741 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4742 | continue; /* unused register */ |
6d82d43b AC |
4743 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4744 | TYPE_CODE_FLT) | |
c5aa993b | 4745 | break; /* end the row: reached FP register */ |
6d82d43b | 4746 | fprintf_filtered (file, |
d5ac5a39 | 4747 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4748 | REGISTER_NAME (regnum)); |
c906108c SS |
4749 | col++; |
4750 | } | |
a4b8ebc8 | 4751 | /* print the R0 to R31 names */ |
20e6603c AC |
4752 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4753 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4754 | else | |
4755 | fprintf_filtered (file, "\n "); | |
c906108c | 4756 | |
c906108c | 4757 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4758 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4759 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4760 | { |
4761 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4762 | continue; /* unused register */ |
6d82d43b AC |
4763 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4764 | TYPE_CODE_FLT) | |
c5aa993b | 4765 | break; /* end row: reached FP register */ |
c906108c | 4766 | /* OK: get the data in raw format. */ |
e11c53d2 | 4767 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4768 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4769 | /* pad small registers */ | |
4246e332 | 4770 | for (byte = 0; |
d5ac5a39 | 4771 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4772 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4773 | printf_filtered (" "); |
4774 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4775 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
4776 | for (byte = |
4777 | register_size (current_gdbarch, | |
4778 | regnum) - register_size (current_gdbarch, regnum); | |
4779 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 4780 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4781 | else |
c73e8f27 | 4782 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4783 | byte >= 0; byte--) |
e11c53d2 AC |
4784 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4785 | fprintf_filtered (file, " "); | |
c906108c SS |
4786 | col++; |
4787 | } | |
c5aa993b | 4788 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4789 | fprintf_filtered (file, "\n"); |
c906108c SS |
4790 | |
4791 | return regnum; | |
4792 | } | |
4793 | ||
4794 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4795 | ||
bf1f5b4c | 4796 | static void |
e11c53d2 AC |
4797 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4798 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4799 | { |
c5aa993b | 4800 | if (regnum != -1) /* do one specified register */ |
c906108c | 4801 | { |
a4b8ebc8 | 4802 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4803 | if (*(REGISTER_NAME (regnum)) == '\0') |
4804 | error ("Not a valid register for the current processor type"); | |
4805 | ||
e11c53d2 AC |
4806 | mips_print_register (file, frame, regnum, 0); |
4807 | fprintf_filtered (file, "\n"); | |
c906108c | 4808 | } |
c5aa993b JM |
4809 | else |
4810 | /* do all (or most) registers */ | |
c906108c | 4811 | { |
a4b8ebc8 AC |
4812 | regnum = NUM_REGS; |
4813 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4814 | { |
6d82d43b AC |
4815 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4816 | TYPE_CODE_FLT) | |
e11c53d2 AC |
4817 | { |
4818 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4819 | regnum = print_fp_register_row (file, frame, regnum); | |
4820 | else | |
4821 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4822 | } | |
c906108c | 4823 | else |
e11c53d2 | 4824 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4825 | } |
4826 | } | |
4827 | } | |
4828 | ||
c906108c SS |
4829 | /* Is this a branch with a delay slot? */ |
4830 | ||
a14ed312 | 4831 | static int is_delayed (unsigned long); |
c906108c SS |
4832 | |
4833 | static int | |
acdb74a0 | 4834 | is_delayed (unsigned long insn) |
c906108c SS |
4835 | { |
4836 | int i; | |
4837 | for (i = 0; i < NUMOPCODES; ++i) | |
4838 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4839 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4840 | break; | |
4841 | return (i < NUMOPCODES | |
4842 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4843 | | INSN_COND_BRANCH_DELAY | |
4844 | | INSN_COND_BRANCH_LIKELY))); | |
4845 | } | |
4846 | ||
4847 | int | |
acdb74a0 | 4848 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4849 | { |
4850 | char buf[MIPS_INSTLEN]; | |
4851 | ||
4852 | /* There is no branch delay slot on MIPS16. */ | |
4853 | if (pc_is_mips16 (pc)) | |
4854 | return 0; | |
4855 | ||
4856 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4857 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4858 | return 0; | |
6d82d43b AC |
4859 | return is_delayed ((unsigned long) |
4860 | extract_unsigned_integer (buf, MIPS_INSTLEN)); | |
c906108c SS |
4861 | } |
4862 | ||
c906108c SS |
4863 | /* Skip the PC past function prologue instructions (32-bit version). |
4864 | This is a helper function for mips_skip_prologue. */ | |
4865 | ||
4866 | static CORE_ADDR | |
f7b9e9fc | 4867 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4868 | { |
c5aa993b JM |
4869 | t_inst inst; |
4870 | CORE_ADDR end_pc; | |
4871 | int seen_sp_adjust = 0; | |
4872 | int load_immediate_bytes = 0; | |
4873 | ||
74da7425 AC |
4874 | /* Find an upper bound on the prologue. */ |
4875 | end_pc = skip_prologue_using_sal (pc); | |
4876 | if (end_pc == 0) | |
6d82d43b | 4877 | end_pc = pc + 100; /* Magic. */ |
74da7425 | 4878 | |
c5aa993b JM |
4879 | /* Skip the typical prologue instructions. These are the stack adjustment |
4880 | instruction and the instructions that save registers on the stack | |
4881 | or in the gcc frame. */ | |
74da7425 | 4882 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
4883 | { |
4884 | unsigned long high_word; | |
c906108c | 4885 | |
c5aa993b JM |
4886 | inst = mips_fetch_instruction (pc); |
4887 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4888 | |
c5aa993b JM |
4889 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4890 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4891 | seen_sp_adjust = 1; | |
4892 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4893 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4894 | seen_sp_adjust = 1; | |
4895 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4896 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4897 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4898 | continue; | |
4899 | ||
4900 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4901 | continue; | |
4902 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4903 | /* sx reg,n($s8) */ | |
4904 | continue; /* reg != $zero */ | |
4905 | ||
4906 | /* move $s8,$sp. With different versions of gas this will be either | |
4907 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4908 | Accept any one of these. */ | |
4909 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4910 | continue; | |
4911 | ||
4912 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4913 | continue; | |
6d82d43b AC |
4914 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
4915 | continue; | |
4916 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4917 | continue; | |
4918 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4919 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4920 | continue; | |
4921 | /* The following instructions load $at or $t0 with an immediate | |
4922 | value in preparation for a stack adjustment via | |
4923 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4924 | a local variable, so we accept them only before a stack adjustment | |
4925 | instruction was seen. */ | |
4926 | else if (!seen_sp_adjust) | |
cb1d2653 | 4927 | { |
6d82d43b AC |
4928 | if (high_word == 0x3c01 || /* lui $at,n */ |
4929 | high_word == 0x3c08) /* lui $t0,n */ | |
4930 | { | |
4931 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4932 | continue; | |
4933 | } | |
4934 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4935 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4936 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4937 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4938 | { | |
4939 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4940 | continue; | |
4941 | } | |
4942 | else | |
4943 | break; | |
cb1d2653 | 4944 | } |
6d82d43b AC |
4945 | else |
4946 | break; | |
46cac009 | 4947 | } |
6d82d43b AC |
4948 | |
4949 | /* In a frameless function, we might have incorrectly | |
4950 | skipped some load immediate instructions. Undo the skipping | |
4951 | if the load immediate was not followed by a stack adjustment. */ | |
4952 | if (load_immediate_bytes && !seen_sp_adjust) | |
4953 | pc -= load_immediate_bytes; | |
4954 | return pc; | |
46cac009 AC |
4955 | } |
4956 | ||
6d82d43b AC |
4957 | /* Skip the PC past function prologue instructions (16-bit version). |
4958 | This is a helper function for mips_skip_prologue. */ | |
cb1d2653 | 4959 | |
6d82d43b AC |
4960 | static CORE_ADDR |
4961 | mips16_skip_prologue (CORE_ADDR pc) | |
c906108c | 4962 | { |
6d82d43b AC |
4963 | CORE_ADDR end_pc; |
4964 | int extend_bytes = 0; | |
4965 | int prev_extend_bytes; | |
4966 | ||
4967 | /* Table of instructions likely to be found in a function prologue. */ | |
4968 | static struct | |
4969 | { | |
4970 | unsigned short inst; | |
4971 | unsigned short mask; | |
4972 | } | |
4973 | table[] = | |
4974 | { | |
7a292a7a | 4975 | { |
6d82d43b AC |
4976 | 0x6300, 0xff00} |
4977 | , /* addiu $sp,offset */ | |
88658117 | 4978 | { |
6d82d43b AC |
4979 | 0xfb00, 0xff00} |
4980 | , /* daddiu $sp,offset */ | |
88658117 | 4981 | { |
6d82d43b AC |
4982 | 0xd000, 0xf800} |
4983 | , /* sw reg,n($sp) */ | |
4984 | { | |
4985 | 0xf900, 0xff00} | |
4986 | , /* sd reg,n($sp) */ | |
4987 | { | |
4988 | 0x6200, 0xff00} | |
4989 | , /* sw $ra,n($sp) */ | |
4990 | { | |
4991 | 0xfa00, 0xff00} | |
4992 | , /* sd $ra,n($sp) */ | |
4993 | { | |
4994 | 0x673d, 0xffff} | |
4995 | , /* move $s1,sp */ | |
4996 | { | |
4997 | 0xd980, 0xff80} | |
4998 | , /* sw $a0-$a3,n($s1) */ | |
4999 | { | |
5000 | 0x6704, 0xff1c} | |
5001 | , /* move reg,$a0-$a3 */ | |
5002 | { | |
5003 | 0xe809, 0xf81f} | |
5004 | , /* entry pseudo-op */ | |
5005 | { | |
5006 | 0x0100, 0xff00} | |
5007 | , /* addiu $s1,$sp,n */ | |
5008 | { | |
5009 | 0, 0} /* end of table marker */ | |
5010 | }; | |
5011 | ||
5012 | /* Find an upper bound on the prologue. */ | |
5013 | end_pc = skip_prologue_using_sal (pc); | |
5014 | if (end_pc == 0) | |
5015 | end_pc = pc + 100; /* Magic. */ | |
5016 | ||
5017 | /* Skip the typical prologue instructions. These are the stack adjustment | |
5018 | instruction and the instructions that save registers on the stack | |
5019 | or in the gcc frame. */ | |
5020 | for (; pc < end_pc; pc += MIPS16_INSTLEN) | |
5021 | { | |
5022 | unsigned short inst; | |
5023 | int i; | |
5024 | ||
5025 | inst = mips_fetch_instruction (pc); | |
5026 | ||
5027 | /* Normally we ignore an extend instruction. However, if it is | |
5028 | not followed by a valid prologue instruction, we must adjust | |
5029 | the pc back over the extend so that it won't be considered | |
5030 | part of the prologue. */ | |
5031 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
88658117 | 5032 | { |
6d82d43b AC |
5033 | extend_bytes = MIPS16_INSTLEN; |
5034 | continue; | |
88658117 | 5035 | } |
6d82d43b AC |
5036 | prev_extend_bytes = extend_bytes; |
5037 | extend_bytes = 0; | |
5038 | ||
5039 | /* Check for other valid prologue instructions besides extend. */ | |
5040 | for (i = 0; table[i].mask != 0; i++) | |
5041 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
5042 | break; | |
5043 | if (table[i].mask != 0) /* it was in table? */ | |
5044 | continue; /* ignore it */ | |
5045 | else | |
5046 | /* non-prologue */ | |
88658117 | 5047 | { |
6d82d43b AC |
5048 | /* Return the current pc, adjusted backwards by 2 if |
5049 | the previous instruction was an extend. */ | |
5050 | return pc - prev_extend_bytes; | |
88658117 AC |
5051 | } |
5052 | } | |
6d82d43b AC |
5053 | return pc; |
5054 | } | |
5055 | ||
5056 | /* To skip prologues, I use this predicate. Returns either PC itself | |
5057 | if the code at PC does not look like a function prologue; otherwise | |
5058 | returns an address that (if we're lucky) follows the prologue. If | |
5059 | LENIENT, then we must skip everything which is involved in setting | |
5060 | up the frame (it's OK to skip more, just so long as we don't skip | |
5061 | anything which might clobber the registers which are being saved. | |
5062 | We must skip more in the case where part of the prologue is in the | |
5063 | delay slot of a non-prologue instruction). */ | |
5064 | ||
5065 | static CORE_ADDR | |
5066 | mips_skip_prologue (CORE_ADDR pc) | |
5067 | { | |
5068 | /* See if we can determine the end of the prologue via the symbol table. | |
5069 | If so, then return either PC, or the PC after the prologue, whichever | |
5070 | is greater. */ | |
5071 | ||
177f84a3 | 5072 | CORE_ADDR post_prologue_pc = after_prologue (pc); |
6d82d43b AC |
5073 | |
5074 | if (post_prologue_pc != 0) | |
5075 | return max (pc, post_prologue_pc); | |
5076 | ||
5077 | /* Can't determine prologue from the symbol table, need to examine | |
5078 | instructions. */ | |
5079 | ||
5080 | if (pc_is_mips16 (pc)) | |
5081 | return mips16_skip_prologue (pc); | |
5082 | else | |
5083 | return mips32_skip_prologue (pc); | |
88658117 AC |
5084 | } |
5085 | ||
a5ea2558 AC |
5086 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5087 | used for all MIPS-specific commands. */ | |
5088 | ||
a5ea2558 | 5089 | static void |
acdb74a0 | 5090 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5091 | { |
5092 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5093 | } | |
5094 | ||
a5ea2558 | 5095 | static void |
acdb74a0 | 5096 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5097 | { |
6d82d43b AC |
5098 | printf_unfiltered |
5099 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5100 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5101 | } | |
5102 | ||
c906108c SS |
5103 | /* Commands to show/set the MIPS FPU type. */ |
5104 | ||
c906108c | 5105 | static void |
acdb74a0 | 5106 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5107 | { |
c906108c SS |
5108 | char *fpu; |
5109 | switch (MIPS_FPU_TYPE) | |
5110 | { | |
5111 | case MIPS_FPU_SINGLE: | |
5112 | fpu = "single-precision"; | |
5113 | break; | |
5114 | case MIPS_FPU_DOUBLE: | |
5115 | fpu = "double-precision"; | |
5116 | break; | |
5117 | case MIPS_FPU_NONE: | |
5118 | fpu = "absent (none)"; | |
5119 | break; | |
93d56215 AC |
5120 | default: |
5121 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5122 | } |
5123 | if (mips_fpu_type_auto) | |
6d82d43b AC |
5124 | printf_unfiltered |
5125 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5126 | fpu); | |
c906108c | 5127 | else |
6d82d43b AC |
5128 | printf_unfiltered |
5129 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5130 | } |
5131 | ||
5132 | ||
c906108c | 5133 | static void |
acdb74a0 | 5134 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5135 | { |
6d82d43b AC |
5136 | printf_unfiltered |
5137 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5138 | show_mipsfpu_command (args, from_tty); |
5139 | } | |
5140 | ||
c906108c | 5141 | static void |
acdb74a0 | 5142 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5143 | { |
8d5838b5 AC |
5144 | struct gdbarch_info info; |
5145 | gdbarch_info_init (&info); | |
c906108c SS |
5146 | mips_fpu_type = MIPS_FPU_SINGLE; |
5147 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5148 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5149 | instead of relying on globals. Doing that would let generic code | |
5150 | handle the search for this specific architecture. */ | |
5151 | if (!gdbarch_update_p (info)) | |
5152 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5153 | } |
5154 | ||
c906108c | 5155 | static void |
acdb74a0 | 5156 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5157 | { |
8d5838b5 AC |
5158 | struct gdbarch_info info; |
5159 | gdbarch_info_init (&info); | |
c906108c SS |
5160 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5161 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5162 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5163 | instead of relying on globals. Doing that would let generic code | |
5164 | handle the search for this specific architecture. */ | |
5165 | if (!gdbarch_update_p (info)) | |
5166 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5167 | } |
5168 | ||
c906108c | 5169 | static void |
acdb74a0 | 5170 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5171 | { |
8d5838b5 AC |
5172 | struct gdbarch_info info; |
5173 | gdbarch_info_init (&info); | |
c906108c SS |
5174 | mips_fpu_type = MIPS_FPU_NONE; |
5175 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5176 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5177 | instead of relying on globals. Doing that would let generic code | |
5178 | handle the search for this specific architecture. */ | |
5179 | if (!gdbarch_update_p (info)) | |
5180 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5181 | } |
5182 | ||
c906108c | 5183 | static void |
acdb74a0 | 5184 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5185 | { |
5186 | mips_fpu_type_auto = 1; | |
5187 | } | |
5188 | ||
c906108c | 5189 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5190 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5191 | the relevant processor still exists (it dates back to '94) and | |
5192 | secondly this is not the way to do this. The processor type should | |
5193 | be set by forcing an architecture change. */ | |
c906108c | 5194 | |
691c0433 AC |
5195 | void |
5196 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5197 | { |
691c0433 | 5198 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5199 | CORE_ADDR prid; |
5200 | ||
5201 | prid = read_register (PRID_REGNUM); | |
5202 | ||
5203 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 5204 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5205 | } |
5206 | ||
5207 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5208 | callable as an sfunc. */ | |
5209 | ||
5210 | static void | |
acdb74a0 AC |
5211 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5212 | struct cmd_list_element *c) | |
c906108c SS |
5213 | { |
5214 | reinit_frame_cache (); | |
5215 | } | |
5216 | ||
a89aa300 AC |
5217 | static int |
5218 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5219 | { |
e5ab0dce | 5220 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5221 | mips_extra_func_info_t proc_desc; |
5222 | ||
5223 | /* Search for the function containing this address. Set the low bit | |
5224 | of the address when searching, in case we were given an even address | |
5225 | that is the start of a 16-bit function. If we didn't do this, | |
5226 | the search would fail because the symbol table says the function | |
5227 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5228 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5229 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5230 | |
5231 | /* Make an attempt to determine if this is a 16-bit function. If | |
5232 | the procedure descriptor exists and the address therein is odd, | |
5233 | it's definitely a 16-bit function. Otherwise, we have to just | |
5234 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5235 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5236 | disassembler needs to be able to locally determine the ISA, and | |
5237 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5238 | work. */ | |
c906108c | 5239 | if (proc_desc) |
d31431ed AC |
5240 | { |
5241 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
6d82d43b | 5242 | info->mach = bfd_mach_mips16; |
d31431ed | 5243 | } |
c906108c | 5244 | else |
d31431ed AC |
5245 | { |
5246 | if (pc_is_mips16 (memaddr)) | |
6d82d43b AC |
5247 | info->mach = bfd_mach_mips16; |
5248 | } | |
c906108c SS |
5249 | |
5250 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5251 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5252 | |
e5ab0dce | 5253 | /* Set the disassembler options. */ |
6d82d43b | 5254 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
5255 | { |
5256 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 5257 | register names from libopcodes. */ |
e5ab0dce AC |
5258 | if (tdep->mips_abi == MIPS_ABI_N32) |
5259 | info->disassembler_options = "gpr-names=n32"; | |
5260 | else | |
5261 | info->disassembler_options = "gpr-names=64"; | |
5262 | info->flavour = bfd_target_elf_flavour; | |
5263 | } | |
5264 | else | |
5265 | /* This string is not recognized explicitly by the disassembler, | |
5266 | but it tells the disassembler to not try to guess the ABI from | |
5267 | the bfd elf headers, such that, if the user overrides the ABI | |
5268 | of a program linked as NewABI, the disassembly will follow the | |
5269 | register naming conventions specified by the user. */ | |
5270 | info->disassembler_options = "gpr-names=32"; | |
5271 | ||
c906108c | 5272 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5273 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5274 | return print_insn_big_mips (memaddr, info); |
5275 | else | |
5276 | return print_insn_little_mips (memaddr, info); | |
5277 | } | |
5278 | ||
c906108c SS |
5279 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5280 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5281 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5282 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5283 | (if necessary) to point to the actual memory location where the | |
5284 | breakpoint should be inserted. */ | |
5285 | ||
f7ab6ec6 | 5286 | static const unsigned char * |
6d82d43b | 5287 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5288 | { |
d7449b42 | 5289 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5290 | { |
5291 | if (pc_is_mips16 (*pcptr)) | |
5292 | { | |
6d82d43b | 5293 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5294 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5295 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5296 | return mips16_big_breakpoint; |
5297 | } | |
5298 | else | |
5299 | { | |
aaab4dba AC |
5300 | /* The IDT board uses an unusual breakpoint value, and |
5301 | sometimes gets confused when it sees the usual MIPS | |
5302 | breakpoint instruction. */ | |
6d82d43b AC |
5303 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5304 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5305 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5306 | |
c5aa993b | 5307 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5308 | |
5309 | if (strcmp (target_shortname, "mips") == 0) | |
5310 | return idt_big_breakpoint; | |
5311 | else if (strcmp (target_shortname, "ddb") == 0 | |
5312 | || strcmp (target_shortname, "pmon") == 0 | |
5313 | || strcmp (target_shortname, "lsi") == 0) | |
5314 | return pmon_big_breakpoint; | |
5315 | else | |
5316 | return big_breakpoint; | |
5317 | } | |
5318 | } | |
5319 | else | |
5320 | { | |
5321 | if (pc_is_mips16 (*pcptr)) | |
5322 | { | |
6d82d43b | 5323 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5324 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5325 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5326 | return mips16_little_breakpoint; |
5327 | } | |
5328 | else | |
5329 | { | |
6d82d43b AC |
5330 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5331 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5332 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5333 | |
c5aa993b | 5334 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5335 | |
5336 | if (strcmp (target_shortname, "mips") == 0) | |
5337 | return idt_little_breakpoint; | |
5338 | else if (strcmp (target_shortname, "ddb") == 0 | |
5339 | || strcmp (target_shortname, "pmon") == 0 | |
5340 | || strcmp (target_shortname, "lsi") == 0) | |
5341 | return pmon_little_breakpoint; | |
5342 | else | |
5343 | return little_breakpoint; | |
5344 | } | |
5345 | } | |
5346 | } | |
5347 | ||
5348 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5349 | PC, which is either the callee or the caller. There are several | |
5350 | cases which must be handled: | |
5351 | ||
5352 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5353 | target PC is in $31 ($ra). |
c906108c | 5354 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5355 | and the target PC is in $2. |
c906108c | 5356 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5357 | before the jal instruction, this is effectively a call stub |
5358 | and the the target PC is in $2. Otherwise this is effectively | |
5359 | a return stub and the target PC is in $18. | |
c906108c SS |
5360 | |
5361 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5362 | gory details. | |
5363 | ||
5364 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5365 | */ |
c906108c | 5366 | |
757a7cc6 | 5367 | static CORE_ADDR |
acdb74a0 | 5368 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5369 | { |
5370 | char *name; | |
5371 | CORE_ADDR start_addr; | |
5372 | ||
5373 | /* Find the starting address and name of the function containing the PC. */ | |
5374 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5375 | return 0; | |
5376 | ||
5377 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5378 | target PC is in $31 ($ra). */ | |
5379 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5380 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5381 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5382 | |
5383 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5384 | { | |
5385 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5386 | and the target PC is in $2. */ | |
5387 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5388 | return read_signed_register (2); |
c906108c SS |
5389 | |
5390 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5391 | before the jal instruction, this is effectively a call stub |
5392 | and the the target PC is in $2. Otherwise this is effectively | |
5393 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5394 | else if (name[19] == 's' || name[19] == 'd') |
5395 | { | |
5396 | if (pc == start_addr) | |
5397 | { | |
5398 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5399 | stub. Such a stub for a function bar might have a name |
5400 | like __fn_stub_bar, and might look like this: | |
5401 | mfc1 $4,$f13 | |
5402 | mfc1 $5,$f12 | |
5403 | mfc1 $6,$f15 | |
5404 | mfc1 $7,$f14 | |
5405 | la $1,bar (becomes a lui/addiu pair) | |
5406 | jr $1 | |
5407 | So scan down to the lui/addi and extract the target | |
5408 | address from those two instructions. */ | |
c906108c | 5409 | |
6c997a34 | 5410 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5411 | t_inst inst; |
5412 | int i; | |
5413 | ||
5414 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5415 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5416 | 0) | |
c906108c SS |
5417 | return target_pc; |
5418 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5419 | && strcmp (name, "etext") != 0 | |
5420 | && strcmp (name, "_etext") != 0) | |
5421 | return target_pc; | |
5422 | ||
5423 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5424 | The limit on the search is arbitrarily set to 20 |
5425 | instructions. FIXME. */ | |
c906108c SS |
5426 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5427 | { | |
c5aa993b JM |
5428 | inst = mips_fetch_instruction (target_pc); |
5429 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5430 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5431 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5432 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5433 | } |
5434 | ||
5435 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5436 | return target_pc; | |
5437 | } | |
5438 | else | |
5439 | /* This is the 'return' part of a call stub. The return | |
5440 | address is in $r18. */ | |
6c997a34 | 5441 | return read_signed_register (18); |
c906108c SS |
5442 | } |
5443 | } | |
c5aa993b | 5444 | return 0; /* not a stub */ |
c906108c SS |
5445 | } |
5446 | ||
5447 | ||
5448 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5449 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5450 | ||
757a7cc6 | 5451 | static int |
acdb74a0 | 5452 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5453 | { |
5454 | CORE_ADDR start_addr; | |
5455 | ||
5456 | /* Find the starting address of the function containing the PC. If the | |
5457 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
5458 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
5459 | 0) | |
c906108c SS |
5460 | return 0; |
5461 | ||
5462 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5463 | { | |
5464 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5465 | if (name[19] >= '0' && name[19] <= '9') | |
5466 | return 1; | |
5467 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5468 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5469 | else if (name[19] == 's' || name[19] == 'd') |
5470 | return pc == start_addr; | |
5471 | } | |
5472 | ||
c5aa993b | 5473 | return 0; /* not a stub */ |
c906108c SS |
5474 | } |
5475 | ||
5476 | ||
5477 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5478 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5479 | ||
e41b17f0 | 5480 | static int |
acdb74a0 | 5481 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5482 | { |
5483 | CORE_ADDR start_addr; | |
5484 | ||
5485 | /* Find the starting address of the function containing the PC. */ | |
5486 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5487 | return 0; | |
5488 | ||
5489 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5490 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5491 | || strcmp (name, "__mips16_ret_df") == 0) | |
5492 | return 1; | |
5493 | ||
5494 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5495 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 5496 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 5497 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
5498 | return 1; |
5499 | ||
c5aa993b | 5500 | return 0; /* not a stub */ |
c906108c SS |
5501 | } |
5502 | ||
5503 | ||
a53c66de AC |
5504 | /* Return non-zero if the PC is in a library helper function that |
5505 | should be ignored. This implements the | |
5506 | DEPRECATED_IGNORE_HELPER_CALL macro. */ | |
c906108c SS |
5507 | |
5508 | int | |
acdb74a0 | 5509 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5510 | { |
5511 | char *name; | |
5512 | ||
5513 | /* Find the starting address and name of the function containing the PC. */ | |
5514 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5515 | return 0; | |
5516 | ||
5517 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5518 | that we want to ignore. */ | |
5519 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5520 | || strcmp (name, "__mips16_ret_df") == 0); | |
5521 | } | |
5522 | ||
5523 | ||
a4b8ebc8 AC |
5524 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5525 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5526 | |
5527 | static int | |
5528 | mips_stab_reg_to_regnum (int num) | |
5529 | { | |
a4b8ebc8 | 5530 | int regnum; |
2f38ef89 | 5531 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5532 | regnum = num; |
2f38ef89 | 5533 | else if (num >= 38 && num < 70) |
56cea623 | 5534 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5535 | else if (num == 70) |
56cea623 | 5536 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5537 | else if (num == 71) |
56cea623 | 5538 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5539 | else |
a4b8ebc8 AC |
5540 | /* This will hopefully (eventually) provoke a warning. Should |
5541 | we be calling complaint() here? */ | |
5542 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5543 | return NUM_REGS + regnum; | |
88c72b7d AC |
5544 | } |
5545 | ||
2f38ef89 | 5546 | |
a4b8ebc8 AC |
5547 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5548 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5549 | |
5550 | static int | |
2f38ef89 | 5551 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5552 | { |
a4b8ebc8 | 5553 | int regnum; |
2f38ef89 | 5554 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5555 | regnum = num; |
2f38ef89 | 5556 | else if (num >= 32 && num < 64) |
56cea623 | 5557 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5558 | else if (num == 64) |
56cea623 | 5559 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5560 | else if (num == 65) |
56cea623 | 5561 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5562 | else |
a4b8ebc8 AC |
5563 | /* This will hopefully (eventually) provoke a warning. Should we |
5564 | be calling complaint() here? */ | |
5565 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5566 | return NUM_REGS + regnum; | |
5567 | } | |
5568 | ||
5569 | static int | |
5570 | mips_register_sim_regno (int regnum) | |
5571 | { | |
5572 | /* Only makes sense to supply raw registers. */ | |
5573 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5574 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5575 | decide if it is valid. Should instead define a standard sim/gdb | |
5576 | register numbering scheme. */ | |
5577 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5578 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5579 | return regnum; | |
5580 | else | |
6d82d43b | 5581 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5582 | } |
5583 | ||
2f38ef89 | 5584 | |
fc0c74b1 AC |
5585 | /* Convert an integer into an address. By first converting the value |
5586 | into a pointer and then extracting it signed, the address is | |
5587 | guarenteed to be correctly sign extended. */ | |
5588 | ||
5589 | static CORE_ADDR | |
5590 | mips_integer_to_address (struct type *type, void *buf) | |
5591 | { | |
5592 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5593 | LONGEST val = unpack_long (type, buf); | |
5594 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5595 | return extract_signed_integer (tmp, | |
5596 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5597 | } | |
5598 | ||
caaa3122 DJ |
5599 | static void |
5600 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5601 | { | |
5602 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5603 | const char *name = bfd_get_section_name (abfd, sect); | |
5604 | ||
5605 | if (*abip != MIPS_ABI_UNKNOWN) | |
5606 | return; | |
5607 | ||
5608 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5609 | return; | |
5610 | ||
5611 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5612 | *abip = MIPS_ABI_O32; | |
5613 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5614 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5615 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5616 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5617 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5618 | *abip = MIPS_ABI_O64; | |
5619 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5620 | *abip = MIPS_ABI_EABI32; | |
5621 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5622 | *abip = MIPS_ABI_EABI64; | |
5623 | else | |
5624 | warning ("unsupported ABI %s.", name + 8); | |
5625 | } | |
5626 | ||
2e4ebe70 DJ |
5627 | static enum mips_abi |
5628 | global_mips_abi (void) | |
5629 | { | |
5630 | int i; | |
5631 | ||
5632 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5633 | if (mips_abi_strings[i] == mips_abi_string) | |
5634 | return (enum mips_abi) i; | |
5635 | ||
6d82d43b | 5636 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
5637 | } |
5638 | ||
c2d11a7d | 5639 | static struct gdbarch * |
6d82d43b | 5640 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5641 | { |
c2d11a7d JM |
5642 | struct gdbarch *gdbarch; |
5643 | struct gdbarch_tdep *tdep; | |
5644 | int elf_flags; | |
2e4ebe70 | 5645 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5646 | int num_regs; |
8d5838b5 | 5647 | enum mips_fpu_type fpu_type; |
c2d11a7d | 5648 | |
ec03c1ac AC |
5649 | /* First of all, extract the elf_flags, if available. */ |
5650 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5651 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5652 | else if (arches != NULL) |
5653 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5654 | else |
5655 | elf_flags = 0; | |
5656 | if (gdbarch_debug) | |
5657 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5658 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5659 | |
102182a9 | 5660 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5661 | switch ((elf_flags & EF_MIPS_ABI)) |
5662 | { | |
5663 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5664 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5665 | break; |
5666 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5667 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5668 | break; |
5669 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5670 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5671 | break; |
5672 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5673 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5674 | break; |
5675 | default: | |
acdb74a0 | 5676 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5677 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5678 | else |
ec03c1ac | 5679 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5680 | break; |
5681 | } | |
acdb74a0 | 5682 | |
caaa3122 | 5683 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5684 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5685 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5686 | |
dc305454 | 5687 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5688 | MIPS architecture (if there is one). */ |
5689 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5690 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5691 | |
32a6503c | 5692 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5693 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5694 | && info.bfd_arch_info != NULL |
5695 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5696 | { | |
5697 | switch (info.bfd_arch_info->mach) | |
5698 | { | |
5699 | case bfd_mach_mips3900: | |
ec03c1ac | 5700 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5701 | break; |
5702 | case bfd_mach_mips4100: | |
5703 | case bfd_mach_mips5000: | |
ec03c1ac | 5704 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5705 | break; |
1d06468c EZ |
5706 | case bfd_mach_mips8000: |
5707 | case bfd_mach_mips10000: | |
32a6503c KB |
5708 | /* On Irix, ELF64 executables use the N64 ABI. The |
5709 | pseudo-sections which describe the ABI aren't present | |
5710 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5711 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5712 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5713 | found_abi = MIPS_ABI_N64; |
28d169de | 5714 | else |
ec03c1ac | 5715 | found_abi = MIPS_ABI_N32; |
1d06468c | 5716 | break; |
bf64bfd6 AC |
5717 | } |
5718 | } | |
2e4ebe70 | 5719 | |
ec03c1ac AC |
5720 | if (gdbarch_debug) |
5721 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5722 | found_abi); | |
5723 | ||
5724 | /* What has the user specified from the command line? */ | |
5725 | wanted_abi = global_mips_abi (); | |
5726 | if (gdbarch_debug) | |
5727 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5728 | wanted_abi); | |
2e4ebe70 DJ |
5729 | |
5730 | /* Now that we have found what the ABI for this binary would be, | |
5731 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5732 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5733 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5734 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5735 | mips_abi = found_abi; | |
5736 | else | |
5737 | mips_abi = MIPS_ABI_O32; | |
5738 | if (gdbarch_debug) | |
5739 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5740 | mips_abi); | |
2e4ebe70 | 5741 | |
ec03c1ac | 5742 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5743 | if (gdbarch_debug) |
ec03c1ac AC |
5744 | fprintf_unfiltered (gdb_stdlog, |
5745 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5746 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5747 | |
8d5838b5 AC |
5748 | /* Determine the MIPS FPU type. */ |
5749 | if (!mips_fpu_type_auto) | |
5750 | fpu_type = mips_fpu_type; | |
5751 | else if (info.bfd_arch_info != NULL | |
5752 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5753 | switch (info.bfd_arch_info->mach) | |
5754 | { | |
5755 | case bfd_mach_mips3900: | |
5756 | case bfd_mach_mips4100: | |
5757 | case bfd_mach_mips4111: | |
a9d61c86 | 5758 | case bfd_mach_mips4120: |
8d5838b5 AC |
5759 | fpu_type = MIPS_FPU_NONE; |
5760 | break; | |
5761 | case bfd_mach_mips4650: | |
5762 | fpu_type = MIPS_FPU_SINGLE; | |
5763 | break; | |
5764 | default: | |
5765 | fpu_type = MIPS_FPU_DOUBLE; | |
5766 | break; | |
5767 | } | |
5768 | else if (arches != NULL) | |
5769 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5770 | else | |
5771 | fpu_type = MIPS_FPU_DOUBLE; | |
5772 | if (gdbarch_debug) | |
5773 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5774 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5775 | |
c2d11a7d JM |
5776 | /* try to find a pre-existing architecture */ |
5777 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5778 | arches != NULL; | |
5779 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5780 | { | |
5781 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5782 | using. */ |
9103eae0 | 5783 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5784 | continue; |
9103eae0 | 5785 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5786 | continue; |
719ec221 AC |
5787 | /* Need to be pedantic about which register virtual size is |
5788 | used. */ | |
5789 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5790 | != mips64_transfers_32bit_regs_p) | |
5791 | continue; | |
8d5838b5 AC |
5792 | /* Be pedantic about which FPU is selected. */ |
5793 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5794 | continue; | |
4be87837 | 5795 | return arches->gdbarch; |
c2d11a7d JM |
5796 | } |
5797 | ||
102182a9 | 5798 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5799 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5800 | gdbarch = gdbarch_alloc (&info, tdep); | |
5801 | tdep->elf_flags = elf_flags; | |
719ec221 | 5802 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5803 | tdep->found_abi = found_abi; |
5804 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5805 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 5806 | |
102182a9 | 5807 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5808 | set_gdbarch_short_bit (gdbarch, 16); |
5809 | set_gdbarch_int_bit (gdbarch, 32); | |
5810 | set_gdbarch_float_bit (gdbarch, 32); | |
5811 | set_gdbarch_double_bit (gdbarch, 64); | |
5812 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5813 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5814 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5815 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5816 | |
6d82d43b | 5817 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5818 | mips_elf_make_msymbol_special); |
5819 | ||
16e109ca | 5820 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5821 | { |
16e109ca | 5822 | const char **reg_names; |
56cea623 AC |
5823 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5824 | struct mips_regnum); | |
56cea623 AC |
5825 | if (info.osabi == GDB_OSABI_IRIX) |
5826 | { | |
5827 | regnum->fp0 = 32; | |
5828 | regnum->pc = 64; | |
5829 | regnum->cause = 65; | |
5830 | regnum->badvaddr = 66; | |
5831 | regnum->hi = 67; | |
5832 | regnum->lo = 68; | |
5833 | regnum->fp_control_status = 69; | |
5834 | regnum->fp_implementation_revision = 70; | |
5835 | num_regs = 71; | |
16e109ca | 5836 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5837 | } |
5838 | else | |
5839 | { | |
5840 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5841 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5842 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5843 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5844 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5845 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5846 | regnum->fp_control_status = 70; | |
5847 | regnum->fp_implementation_revision = 71; | |
5848 | num_regs = 90; | |
16e109ca AC |
5849 | if (info.bfd_arch_info != NULL |
5850 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5851 | reg_names = mips_tx39_reg_names; | |
5852 | else | |
5853 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5854 | } |
5855 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5856 | replaced by read_pc? */ | |
f10683bb MH |
5857 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5858 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5859 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5860 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5861 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5862 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5863 | tdep->mips_processor_reg_names = reg_names; | |
5864 | tdep->regnum = regnum; | |
56cea623 | 5865 | } |
fe29b929 | 5866 | |
0dadbba0 | 5867 | switch (mips_abi) |
c2d11a7d | 5868 | { |
0dadbba0 | 5869 | case MIPS_ABI_O32: |
25ab4790 | 5870 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5871 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
acdb74a0 | 5872 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5873 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5874 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5875 | set_gdbarch_long_bit (gdbarch, 32); |
5876 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5877 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5878 | break; | |
0dadbba0 | 5879 | case MIPS_ABI_O64: |
25ab4790 | 5880 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
6d82d43b AC |
5881 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5882 | mips_o64_store_return_value); | |
5883 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5884 | mips_o64_extract_return_value); | |
acdb74a0 | 5885 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5886 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5887 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5888 | set_gdbarch_long_bit (gdbarch, 32); |
5889 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5890 | set_gdbarch_long_long_bit (gdbarch, 64); | |
b5622e8d | 5891 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 5892 | break; |
0dadbba0 | 5893 | case MIPS_ABI_EABI32: |
25ab4790 | 5894 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
5895 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5896 | mips_eabi_store_return_value); | |
5897 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5898 | mips_eabi_extract_return_value); | |
acdb74a0 | 5899 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5900 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5901 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5902 | set_gdbarch_long_bit (gdbarch, 32); |
5903 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5904 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5905 | set_gdbarch_deprecated_reg_struct_has_addr |
5906 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
b5622e8d | 5907 | set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention); |
c2d11a7d | 5908 | break; |
0dadbba0 | 5909 | case MIPS_ABI_EABI64: |
25ab4790 | 5910 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
5911 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5912 | mips_eabi_store_return_value); | |
5913 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5914 | mips_eabi_extract_return_value); | |
acdb74a0 | 5915 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5916 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5917 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5918 | set_gdbarch_long_bit (gdbarch, 64); |
5919 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5920 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5921 | set_gdbarch_deprecated_reg_struct_has_addr |
5922 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
b5622e8d | 5923 | set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention); |
c2d11a7d | 5924 | break; |
0dadbba0 | 5925 | case MIPS_ABI_N32: |
25ab4790 | 5926 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5927 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
acdb74a0 | 5928 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5929 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5930 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5931 | set_gdbarch_long_bit (gdbarch, 32); |
5932 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5933 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
5934 | set_gdbarch_long_double_bit (gdbarch, 128); |
5935 | set_gdbarch_long_double_format (gdbarch, | |
5936 | &floatformat_n32n64_long_double_big); | |
28d169de KB |
5937 | break; |
5938 | case MIPS_ABI_N64: | |
25ab4790 | 5939 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5940 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de | 5941 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5942 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5943 | tdep->default_mask_address_p = 0; |
5944 | set_gdbarch_long_bit (gdbarch, 64); | |
5945 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5946 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
5947 | set_gdbarch_long_double_bit (gdbarch, 128); |
5948 | set_gdbarch_long_double_format (gdbarch, | |
5949 | &floatformat_n32n64_long_double_big); | |
0dadbba0 | 5950 | break; |
c2d11a7d | 5951 | default: |
6d82d43b | 5952 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
5953 | } |
5954 | ||
a5ea2558 AC |
5955 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5956 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5957 | comment: | |
5958 | ||
5959 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5960 | flag in object files because to do so would make it impossible to | |
102182a9 | 5961 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5962 | unnecessarily restrictive. |
361d1df0 | 5963 | |
a5ea2558 AC |
5964 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5965 | but to set this flag before gcc is built with such multilibs will | |
5966 | break too many systems.'' | |
5967 | ||
5968 | But even more unhelpfully, the default linker output target for | |
5969 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5970 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5971 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5972 | this flag to detect 32-bit mode would do the wrong thing given |
5973 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5974 | as 32-bit programs by default. */ |
a5ea2558 | 5975 | |
6c997a34 | 5976 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5977 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 5978 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5979 | |
102182a9 MS |
5980 | /* Add/remove bits from an address. The MIPS needs be careful to |
5981 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5982 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5983 | ||
58dfe9ff AC |
5984 | /* Unwind the frame. */ |
5985 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 | 5986 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5987 | |
102182a9 | 5988 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5989 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5990 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5991 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5992 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5993 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5994 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5995 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5996 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5997 | |
c2d11a7d JM |
5998 | /* MIPS version of CALL_DUMMY */ |
5999 | ||
9710e734 AC |
6000 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6001 | replaced by a command, and all targets will default to on stack | |
6002 | (regardless of the stack's execute status). */ | |
6003 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6004 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6005 | |
87783b8b AC |
6006 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6007 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6008 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6009 | ||
f7b9e9fc AC |
6010 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6011 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6012 | |
6013 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6014 | |
fc0c74b1 AC |
6015 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6016 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6017 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6018 | |
a4b8ebc8 | 6019 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6020 | |
e11c53d2 | 6021 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6022 | |
e5ab0dce AC |
6023 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6024 | ||
3a3bc038 AC |
6025 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6026 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6027 | need to all be folded into the target vector. Since they are | |
6028 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6029 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6030 | is sitting on? */ | |
6031 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6032 | ||
757a7cc6 MS |
6033 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); |
6034 | ||
6de918a6 DJ |
6035 | /* NOTE drow/2004-02-11: We overload the core solib trampoline code |
6036 | to support MIPS16. This is a bad thing. Make sure not to do it | |
6037 | if we have an OS ABI that actually supports shared libraries, since | |
6038 | shared library support is more important. If we have an OS someday | |
6039 | that supports both shared libraries and MIPS16, we'll have to find | |
6040 | a better place for these. */ | |
6041 | if (info.osabi == GDB_OSABI_UNKNOWN) | |
6042 | { | |
6043 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
6044 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
6045 | } | |
6046 | ||
6047 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
6048 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 6049 | |
5792a79b | 6050 | /* Unwind the frame. */ |
eec63939 | 6051 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
5792a79b | 6052 | frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer); |
45c9dd44 AC |
6053 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
6054 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
eec63939 | 6055 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
5792a79b | 6056 | frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer); |
45c9dd44 AC |
6057 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6058 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6059 | |
4b9b3959 AC |
6060 | return gdbarch; |
6061 | } | |
6062 | ||
2e4ebe70 | 6063 | static void |
6d82d43b | 6064 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6065 | { |
6066 | struct gdbarch_info info; | |
6067 | ||
6068 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6069 | mips_gdbarch_init will take care of the rest. */ | |
6070 | gdbarch_info_init (&info); | |
6071 | gdbarch_update_p (info); | |
6072 | } | |
6073 | ||
ad188201 KB |
6074 | /* Print out which MIPS ABI is in use. */ |
6075 | ||
6076 | static void | |
6077 | show_mips_abi (char *ignore_args, int from_tty) | |
6078 | { | |
6079 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
6080 | printf_filtered |
6081 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
6082 | else |
6083 | { | |
6084 | enum mips_abi global_abi = global_mips_abi (); | |
6085 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6086 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6087 | ||
6088 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
6089 | printf_filtered |
6090 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6091 | actual_abi_str); | |
ad188201 | 6092 | else if (global_abi == actual_abi) |
6d82d43b AC |
6093 | printf_filtered |
6094 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6095 | actual_abi_str); | |
ad188201 KB |
6096 | else |
6097 | { | |
6098 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
6099 | printf_filtered |
6100 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6101 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
6102 | } |
6103 | } | |
6104 | } | |
6105 | ||
4b9b3959 AC |
6106 | static void |
6107 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6108 | { | |
6109 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6110 | if (tdep != NULL) | |
c2d11a7d | 6111 | { |
acdb74a0 AC |
6112 | int ef_mips_arch; |
6113 | int ef_mips_32bitmode; | |
6114 | /* determine the ISA */ | |
6115 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6116 | { | |
6117 | case E_MIPS_ARCH_1: | |
6118 | ef_mips_arch = 1; | |
6119 | break; | |
6120 | case E_MIPS_ARCH_2: | |
6121 | ef_mips_arch = 2; | |
6122 | break; | |
6123 | case E_MIPS_ARCH_3: | |
6124 | ef_mips_arch = 3; | |
6125 | break; | |
6126 | case E_MIPS_ARCH_4: | |
93d56215 | 6127 | ef_mips_arch = 4; |
acdb74a0 AC |
6128 | break; |
6129 | default: | |
93d56215 | 6130 | ef_mips_arch = 0; |
acdb74a0 AC |
6131 | break; |
6132 | } | |
6133 | /* determine the size of a pointer */ | |
6134 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6135 | fprintf_unfiltered (file, |
6136 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6137 | tdep->elf_flags); |
4b9b3959 | 6138 | fprintf_unfiltered (file, |
acdb74a0 AC |
6139 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6140 | ef_mips_32bitmode); | |
6141 | fprintf_unfiltered (file, | |
6142 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6143 | ef_mips_arch); | |
6144 | fprintf_unfiltered (file, | |
6145 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6146 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6147 | fprintf_unfiltered (file, |
6148 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6149 | mips_mask_address_p (tdep), |
4014092b | 6150 | tdep->default_mask_address_p); |
c2d11a7d | 6151 | } |
4b9b3959 AC |
6152 | fprintf_unfiltered (file, |
6153 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6154 | MIPS_DEFAULT_FPU_TYPE, | |
6155 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6156 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6157 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6158 | : "???")); | |
6d82d43b | 6159 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
6160 | fprintf_unfiltered (file, |
6161 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6162 | MIPS_FPU_TYPE, | |
6163 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6164 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6165 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6166 | : "???")); | |
4b9b3959 | 6167 | fprintf_unfiltered (file, |
480d3dd2 | 6168 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
13326b4e | 6169 | mips_stack_argsize (current_gdbarch)); |
6d82d43b | 6170 | fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM); |
2475bac3 AC |
6171 | fprintf_unfiltered (file, |
6172 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 6173 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
6174 | fprintf_unfiltered (file, |
6175 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6176 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6177 | fprintf_unfiltered (file, |
6178 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6179 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6180 | fprintf_unfiltered (file, | |
6181 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6182 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6183 | fprintf_unfiltered (file, |
6184 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6185 | FIRST_EMBED_REGNUM); | |
2475bac3 | 6186 | fprintf_unfiltered (file, |
a53c66de AC |
6187 | "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n", |
6188 | XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6189 | fprintf_unfiltered (file, |
6190 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6191 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6192 | fprintf_unfiltered (file, | |
6193 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6194 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6195 | fprintf_unfiltered (file, |
6196 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6197 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6198 | #ifdef MACHINE_CPROC_FP_OFFSET |
6199 | fprintf_unfiltered (file, | |
6200 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6201 | MACHINE_CPROC_FP_OFFSET); | |
6202 | #endif | |
6203 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6204 | fprintf_unfiltered (file, | |
6205 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6206 | MACHINE_CPROC_PC_OFFSET); | |
6207 | #endif | |
6208 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6209 | fprintf_unfiltered (file, | |
6210 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6211 | MACHINE_CPROC_SP_OFFSET); | |
6212 | #endif | |
2475bac3 AC |
6213 | fprintf_unfiltered (file, |
6214 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6215 | MIPS16_INSTLEN); | |
6d82d43b | 6216 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
6217 | fprintf_unfiltered (file, |
6218 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6219 | fprintf_unfiltered (file, | |
6d82d43b | 6220 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN); |
2475bac3 | 6221 | fprintf_unfiltered (file, |
acdb74a0 AC |
6222 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6223 | MIPS_LAST_ARG_REGNUM, | |
6224 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 | 6225 | fprintf_unfiltered (file, |
6d82d43b | 6226 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 6227 | fprintf_unfiltered (file, |
1b13c4f6 | 6228 | "mips_dump_tdep: mips_abi_regsize() = %d\n", |
13326b4e | 6229 | mips_abi_regsize (current_gdbarch)); |
2475bac3 | 6230 | fprintf_unfiltered (file, |
6d82d43b | 6231 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
6232 | fprintf_unfiltered (file, |
6233 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6234 | fprintf_unfiltered (file, | |
6235 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
6236 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
6237 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6238 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6239 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6240 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6241 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6242 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6243 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6244 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6245 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
6246 | fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM); | |
2475bac3 AC |
6247 | #ifdef SAVED_BYTES |
6248 | fprintf_unfiltered (file, | |
6d82d43b | 6249 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
6250 | #endif |
6251 | #ifdef SAVED_FP | |
6d82d43b | 6252 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
6253 | #endif |
6254 | #ifdef SAVED_PC | |
6d82d43b | 6255 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
6256 | #endif |
6257 | fprintf_unfiltered (file, | |
6258 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6259 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
2475bac3 AC |
6260 | fprintf_unfiltered (file, |
6261 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6262 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6263 | fprintf_unfiltered (file, | |
6264 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6265 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6266 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6267 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6268 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6269 | fprintf_unfiltered (file, |
6270 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6271 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6272 | #ifdef STACK_END_ADDR | |
6273 | fprintf_unfiltered (file, | |
6274 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6275 | STACK_END_ADDR); | |
6276 | #endif | |
6277 | fprintf_unfiltered (file, | |
6278 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6279 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6280 | fprintf_unfiltered (file, | |
6281 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6282 | STEP_SKIPS_DELAY_P); | |
6283 | fprintf_unfiltered (file, | |
6284 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6285 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6d82d43b | 6286 | fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM); |
2475bac3 AC |
6287 | fprintf_unfiltered (file, |
6288 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6289 | fprintf_unfiltered (file, | |
6290 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
6291 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
6292 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
6293 | #ifdef TRACE_CLEAR |
6294 | fprintf_unfiltered (file, | |
6295 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6296 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6297 | #endif | |
6298 | #ifdef TRACE_FLAVOR | |
6299 | fprintf_unfiltered (file, | |
6d82d43b | 6300 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
6301 | #endif |
6302 | #ifdef TRACE_FLAVOR_SIZE | |
6303 | fprintf_unfiltered (file, | |
6304 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6305 | TRACE_FLAVOR_SIZE); | |
6306 | #endif | |
6307 | #ifdef TRACE_SET | |
6308 | fprintf_unfiltered (file, | |
6309 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 6310 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 6311 | #endif |
2475bac3 AC |
6312 | #ifdef UNUSED_REGNUM |
6313 | fprintf_unfiltered (file, | |
6d82d43b | 6314 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 6315 | #endif |
6d82d43b | 6316 | fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM); |
2475bac3 AC |
6317 | fprintf_unfiltered (file, |
6318 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6319 | (long) VM_MIN_ADDRESS); | |
2475bac3 | 6320 | fprintf_unfiltered (file, |
6d82d43b | 6321 | "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM); |
c2d11a7d JM |
6322 | } |
6323 | ||
6d82d43b | 6324 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6325 | |
c906108c | 6326 | void |
acdb74a0 | 6327 | _initialize_mips_tdep (void) |
c906108c SS |
6328 | { |
6329 | static struct cmd_list_element *mipsfpulist = NULL; | |
6330 | struct cmd_list_element *c; | |
6331 | ||
6d82d43b | 6332 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6333 | if (MIPS_ABI_LAST + 1 |
6334 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6335 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6336 | ||
4b9b3959 | 6337 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6338 | |
8d5f9dcb DJ |
6339 | mips_pdr_data = register_objfile_data (); |
6340 | ||
a5ea2558 AC |
6341 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6342 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6343 | "Various MIPS specific commands.", | |
6344 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6345 | ||
6346 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6347 | "Various MIPS specific commands.", | |
6348 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6349 | ||
6350 | /* Allow the user to override the saved register size. */ | |
cb1a6d5f AC |
6351 | deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", |
6352 | class_obscure, | |
6353 | size_enums, | |
6354 | &mips_abi_regsize_string, "\ | |
a5ea2558 AC |
6355 | Set size of general purpose registers saved on the stack.\n\ |
6356 | This option can be set to one of:\n\ | |
6357 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6358 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6359 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6360 | saved GP register size from information contained in the executable.\n\ | |
6d82d43b | 6361 | (default: auto)", &setmipscmdlist), &showmipscmdlist); |
a5ea2558 | 6362 | |
d929b26f | 6363 | /* Allow the user to override the argument stack size. */ |
cb1a6d5f AC |
6364 | deprecated_add_show_from_set |
6365 | (add_set_enum_cmd ("stack-arg-size", | |
6366 | class_obscure, | |
6367 | size_enums, | |
6368 | &mips_stack_argsize_string, "\ | |
d929b26f AC |
6369 | Set the amount of stack space reserved for each argument.\n\ |
6370 | This option can be set to one of:\n\ | |
6371 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6372 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6373 | auto - Allow GDB to determine the correct setting from the current\n\ | |
cb1a6d5f AC |
6374 | target and executable (default)", &setmipscmdlist), |
6375 | &showmipscmdlist); | |
d929b26f | 6376 | |
2e4ebe70 DJ |
6377 | /* Allow the user to override the ABI. */ |
6378 | c = add_set_enum_cmd | |
6379 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6380 | "Set the ABI used by this program.\n" | |
6381 | "This option can be set to one of:\n" | |
6382 | " auto - the default ABI associated with the current binary\n" | |
6383 | " o32\n" | |
6d82d43b | 6384 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 6385 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 6386 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 6387 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 6388 | |
c906108c SS |
6389 | /* Let the user turn off floating point and set the fence post for |
6390 | heuristic_proc_start. */ | |
6391 | ||
6392 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6393 | "Set use of MIPS floating-point coprocessor.", | |
6394 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6395 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6396 | "Select single-precision MIPS floating-point coprocessor.", | |
6397 | &mipsfpulist); | |
6398 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6399 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6400 | &mipsfpulist); |
6401 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6402 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6403 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6404 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 6405 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
6406 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6407 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6408 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6409 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6410 | "Select MIPS floating-point coprocessor automatically.", | |
6411 | &mipsfpulist); | |
6412 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6413 | "Show current use of MIPS floating-point coprocessor target.", | |
6414 | &showlist); | |
6415 | ||
c906108c SS |
6416 | /* We really would like to have both "0" and "unlimited" work, but |
6417 | command.c doesn't deal with that. So make it a var_zinteger | |
6418 | because the user can always use "999999" or some such for unlimited. */ | |
6419 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6d82d43b | 6420 | (char *) &heuristic_fence_post, "\ |
c906108c SS |
6421 | Set the distance searched for the start of a function.\n\ |
6422 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6423 | program for the start of a function. This command sets the distance of the\n\ | |
6d82d43b | 6424 | search. The only need to set it is when debugging a stripped executable.", &setlist); |
c906108c SS |
6425 | /* We need to throw away the frame cache when we set this, since it |
6426 | might change our ability to get backtraces. */ | |
9f60d481 | 6427 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
cb1a6d5f | 6428 | deprecated_add_show_from_set (c, &showlist); |
c906108c SS |
6429 | |
6430 | /* Allow the user to control whether the upper bits of 64-bit | |
6431 | addresses should be zeroed. */ | |
e9e68a56 | 6432 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
3b64bf98 AC |
6433 | Set zeroing of upper 32 bits of 64-bit addresses.", "\ |
6434 | Show zeroing of upper 32 bits of 64-bit addresses.", "\ | |
e9e68a56 AC |
6435 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
6436 | allow GDB to determine the correct value.\n", "\ | |
3b64bf98 | 6437 | Zerroing of upper 32 bits of 64-bit address is %s.", |
6d82d43b | 6438 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
6439 | |
6440 | /* Allow the user to control the size of 32 bit registers within the | |
6441 | raw remote packet. */ | |
b3f42336 AC |
6442 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6443 | &mips64_transfers_32bit_regs_p, "\ | |
3b64bf98 AC |
6444 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ |
6445 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ | |
719ec221 AC |
6446 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6447 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6448 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
3b64bf98 AC |
6449 | Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.", |
6450 | set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); | |
9ace0497 AC |
6451 | |
6452 | /* Debug this files internals. */ | |
cb1a6d5f AC |
6453 | deprecated_add_show_from_set |
6454 | (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6455 | &mips_debug, "Set mips debugging.\n\ | |
6456 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6457 | &showdebuglist); | |
c906108c | 6458 | } |