Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
ecd75fc8 | 3 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "language.h" | |
30 | #include "gdbcore.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
33 | #include "gdbtypes.h" | |
34 | #include "target.h" | |
28d069e6 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
70f80edf | 37 | #include "osabi.h" |
d1973055 | 38 | #include "mips-tdep.h" |
fe898f56 | 39 | #include "block.h" |
a4b8ebc8 | 40 | #include "reggroups.h" |
c906108c | 41 | #include "opcode/mips.h" |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
a4b8ebc8 | 45 | #include "sim-regno.h" |
a89aa300 | 46 | #include "dis-asm.h" |
edfae063 AC |
47 | #include "frame-unwind.h" |
48 | #include "frame-base.h" | |
49 | #include "trad-frame.h" | |
7d9b040b | 50 | #include "infcall.h" |
fed7ba43 | 51 | #include "floatformat.h" |
29709017 DJ |
52 | #include "remote.h" |
53 | #include "target-descriptions.h" | |
2bd0c3d7 | 54 | #include "dwarf2-frame.h" |
f8b73d13 | 55 | #include "user-regs.h" |
79a45b7d | 56 | #include "valprint.h" |
175ff332 | 57 | #include "ax.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
ab50adb6 MR |
63 | static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, |
64 | ULONGEST inst); | |
65 | static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); | |
66 | static int mips16_instruction_has_delay_slot (unsigned short inst, | |
67 | int mustbe32); | |
68 | ||
69 | static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
70 | CORE_ADDR addr); | |
71 | static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
72 | CORE_ADDR addr, int mustbe32); | |
73 | static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
74 | CORE_ADDR addr, int mustbe32); | |
4cc0665f | 75 | |
24e05951 | 76 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
77 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
78 | #define ST0_FR (1 << 26) | |
79 | ||
b0069a17 AC |
80 | /* The sizes of floating point registers. */ |
81 | ||
82 | enum | |
83 | { | |
84 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
85 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
86 | }; | |
87 | ||
1a69e1e4 DJ |
88 | enum |
89 | { | |
90 | MIPS32_REGSIZE = 4, | |
91 | MIPS64_REGSIZE = 8 | |
92 | }; | |
0dadbba0 | 93 | |
2e4ebe70 DJ |
94 | static const char *mips_abi_string; |
95 | ||
40478521 | 96 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
97 | "auto", |
98 | "n32", | |
99 | "o32", | |
28d169de | 100 | "n64", |
2e4ebe70 DJ |
101 | "o64", |
102 | "eabi32", | |
103 | "eabi64", | |
104 | NULL | |
105 | }; | |
106 | ||
4cc0665f MR |
107 | /* For backwards compatibility we default to MIPS16. This flag is |
108 | overridden as soon as unambiguous ELF file flags tell us the | |
109 | compressed ISA encoding used. */ | |
110 | static const char mips_compression_mips16[] = "mips16"; | |
111 | static const char mips_compression_micromips[] = "micromips"; | |
112 | static const char *const mips_compression_strings[] = | |
113 | { | |
114 | mips_compression_mips16, | |
115 | mips_compression_micromips, | |
116 | NULL | |
117 | }; | |
118 | ||
119 | static const char *mips_compression_string = mips_compression_mips16; | |
120 | ||
f8b73d13 DJ |
121 | /* The standard register names, and all the valid aliases for them. */ |
122 | struct register_alias | |
123 | { | |
124 | const char *name; | |
125 | int regnum; | |
126 | }; | |
127 | ||
128 | /* Aliases for o32 and most other ABIs. */ | |
129 | const struct register_alias mips_o32_aliases[] = { | |
130 | { "ta0", 12 }, | |
131 | { "ta1", 13 }, | |
132 | { "ta2", 14 }, | |
133 | { "ta3", 15 } | |
134 | }; | |
135 | ||
136 | /* Aliases for n32 and n64. */ | |
137 | const struct register_alias mips_n32_n64_aliases[] = { | |
138 | { "ta0", 8 }, | |
139 | { "ta1", 9 }, | |
140 | { "ta2", 10 }, | |
141 | { "ta3", 11 } | |
142 | }; | |
143 | ||
144 | /* Aliases for ABI-independent registers. */ | |
145 | const struct register_alias mips_register_aliases[] = { | |
146 | /* The architecture manuals specify these ABI-independent names for | |
147 | the GPRs. */ | |
148 | #define R(n) { "r" #n, n } | |
149 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
150 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
151 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
152 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
153 | #undef R | |
154 | ||
155 | /* k0 and k1 are sometimes called these instead (for "kernel | |
156 | temp"). */ | |
157 | { "kt0", 26 }, | |
158 | { "kt1", 27 }, | |
159 | ||
160 | /* This is the traditional GDB name for the CP0 status register. */ | |
161 | { "sr", MIPS_PS_REGNUM }, | |
162 | ||
163 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
164 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
165 | ||
166 | /* This is the traditional GDB name for the FCSR. */ | |
167 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
168 | }; | |
169 | ||
865093a3 AR |
170 | const struct register_alias mips_numeric_register_aliases[] = { |
171 | #define R(n) { #n, n } | |
172 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
173 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
174 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
175 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
176 | #undef R | |
177 | }; | |
178 | ||
c906108c SS |
179 | #ifndef MIPS_DEFAULT_FPU_TYPE |
180 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
181 | #endif | |
182 | static int mips_fpu_type_auto = 1; | |
183 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 184 | |
ccce17b0 | 185 | static unsigned int mips_debug = 0; |
7a292a7a | 186 | |
29709017 DJ |
187 | /* Properties (for struct target_desc) describing the g/G packet |
188 | layout. */ | |
189 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
190 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
191 | ||
4eb0ad19 DJ |
192 | struct target_desc *mips_tdesc_gp32; |
193 | struct target_desc *mips_tdesc_gp64; | |
194 | ||
56cea623 AC |
195 | const struct mips_regnum * |
196 | mips_regnum (struct gdbarch *gdbarch) | |
197 | { | |
198 | return gdbarch_tdep (gdbarch)->regnum; | |
199 | } | |
200 | ||
201 | static int | |
202 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
203 | { | |
204 | return mips_regnum (gdbarch)->fp0 + 12; | |
205 | } | |
206 | ||
004159a2 MR |
207 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
208 | or cooked. Otherwise return 0. */ | |
209 | ||
210 | static int | |
211 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
212 | { | |
213 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
214 | ||
215 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
216 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
217 | } | |
218 | ||
74ed0bb4 MD |
219 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
220 | == MIPS_ABI_EABI32 \ | |
221 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 222 | |
025bb325 MS |
223 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
224 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 225 | |
025bb325 MS |
226 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
227 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 228 | |
74ed0bb4 | 229 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 230 | |
d1973055 KB |
231 | /* Return the MIPS ABI associated with GDBARCH. */ |
232 | enum mips_abi | |
233 | mips_abi (struct gdbarch *gdbarch) | |
234 | { | |
235 | return gdbarch_tdep (gdbarch)->mips_abi; | |
236 | } | |
237 | ||
4246e332 | 238 | int |
1b13c4f6 | 239 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 240 | { |
29709017 DJ |
241 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
242 | ||
243 | /* If we know how big the registers are, use that size. */ | |
244 | if (tdep->register_size_valid_p) | |
245 | return tdep->register_size; | |
246 | ||
247 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
248 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
249 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
250 | } | |
251 | ||
025bb325 | 252 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 253 | |
e6bc2e8a | 254 | unsigned int |
13326b4e | 255 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 256 | { |
1a69e1e4 DJ |
257 | switch (mips_abi (gdbarch)) |
258 | { | |
259 | case MIPS_ABI_EABI32: | |
260 | case MIPS_ABI_O32: | |
261 | return 4; | |
262 | case MIPS_ABI_N32: | |
263 | case MIPS_ABI_N64: | |
264 | case MIPS_ABI_O64: | |
265 | case MIPS_ABI_EABI64: | |
266 | return 8; | |
267 | case MIPS_ABI_UNKNOWN: | |
268 | case MIPS_ABI_LAST: | |
269 | default: | |
270 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
271 | } | |
d929b26f AC |
272 | } |
273 | ||
4cc0665f MR |
274 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
275 | are some functions to handle addresses associated with compressed | |
276 | code including but not limited to testing, setting, or clearing | |
277 | bit 0 of such addresses. */ | |
742c84f6 | 278 | |
4cc0665f MR |
279 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
280 | ||
281 | static int | |
282 | is_mips16_isa (struct gdbarch *gdbarch) | |
283 | { | |
284 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; | |
285 | } | |
286 | ||
287 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
288 | ||
289 | static int | |
290 | is_micromips_isa (struct gdbarch *gdbarch) | |
291 | { | |
292 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; | |
293 | } | |
294 | ||
295 | /* Return one iff ADDR denotes compressed code. */ | |
296 | ||
297 | static int | |
298 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
299 | { |
300 | return ((addr) & 1); | |
301 | } | |
302 | ||
4cc0665f MR |
303 | /* Return one iff ADDR denotes standard ISA code. */ |
304 | ||
305 | static int | |
306 | is_mips_addr (CORE_ADDR addr) | |
307 | { | |
308 | return !is_compact_addr (addr); | |
309 | } | |
310 | ||
311 | /* Return one iff ADDR denotes MIPS16 code. */ | |
312 | ||
313 | static int | |
314 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
315 | { | |
316 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
317 | } | |
318 | ||
319 | /* Return one iff ADDR denotes microMIPS code. */ | |
320 | ||
321 | static int | |
322 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
323 | { | |
324 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
325 | } | |
326 | ||
327 | /* Strip the ISA (compression) bit off from ADDR. */ | |
328 | ||
742c84f6 | 329 | static CORE_ADDR |
4cc0665f | 330 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
331 | { |
332 | return ((addr) & ~(CORE_ADDR) 1); | |
333 | } | |
334 | ||
4cc0665f MR |
335 | /* Add the ISA (compression) bit to ADDR. */ |
336 | ||
742c84f6 | 337 | static CORE_ADDR |
4cc0665f | 338 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
339 | { |
340 | return ((addr) | (CORE_ADDR) 1); | |
341 | } | |
342 | ||
71b8ef93 | 343 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
344 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
345 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 346 | |
4cc0665f MR |
347 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
348 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
349 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
350 | The test checks an ELF-private flag that is valid for true function | |
1bbce132 MR |
351 | symbols only; for synthetic symbols such as for PLT stubs that have |
352 | no ELF-private part at all the MIPS BFD backend arranges for this | |
353 | information to be carried in the asymbol's udata field instead. | |
5a89d8aa | 354 | |
4cc0665f MR |
355 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
356 | in a minimal symbol. */ | |
5a89d8aa | 357 | |
5a89d8aa | 358 | static void |
6d82d43b AC |
359 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
360 | { | |
4cc0665f | 361 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
1bbce132 | 362 | unsigned char st_other; |
4cc0665f | 363 | |
1bbce132 MR |
364 | if ((sym->flags & BSF_SYNTHETIC) == 0) |
365 | st_other = elfsym->internal_elf_sym.st_other; | |
366 | else if ((sym->flags & BSF_FUNCTION) != 0) | |
367 | st_other = sym->udata.i; | |
368 | else | |
4cc0665f MR |
369 | return; |
370 | ||
1bbce132 | 371 | if (ELF_ST_IS_MICROMIPS (st_other)) |
4cc0665f | 372 | MSYMBOL_TARGET_FLAG_2 (msym) = 1; |
1bbce132 | 373 | else if (ELF_ST_IS_MIPS16 (st_other)) |
4cc0665f MR |
374 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
375 | } | |
376 | ||
377 | /* Return one iff MSYM refers to standard ISA code. */ | |
378 | ||
379 | static int | |
380 | msymbol_is_mips (struct minimal_symbol *msym) | |
381 | { | |
382 | return !(MSYMBOL_TARGET_FLAG_1 (msym) | MSYMBOL_TARGET_FLAG_2 (msym)); | |
5a89d8aa MS |
383 | } |
384 | ||
4cc0665f MR |
385 | /* Return one iff MSYM refers to MIPS16 code. */ |
386 | ||
71b8ef93 | 387 | static int |
4cc0665f | 388 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 389 | { |
b887350f | 390 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
391 | } |
392 | ||
4cc0665f MR |
393 | /* Return one iff MSYM refers to microMIPS code. */ |
394 | ||
395 | static int | |
396 | msymbol_is_micromips (struct minimal_symbol *msym) | |
397 | { | |
398 | return MSYMBOL_TARGET_FLAG_2 (msym); | |
399 | } | |
400 | ||
88658117 AC |
401 | /* XFER a value from the big/little/left end of the register. |
402 | Depending on the size of the value it might occupy the entire | |
403 | register or just part of it. Make an allowance for this, aligning | |
404 | things accordingly. */ | |
405 | ||
406 | static void | |
ba32f989 DJ |
407 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
408 | int reg_num, int length, | |
870cd05e MK |
409 | enum bfd_endian endian, gdb_byte *in, |
410 | const gdb_byte *out, int buf_offset) | |
88658117 | 411 | { |
88658117 | 412 | int reg_offset = 0; |
72a155b4 UW |
413 | |
414 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
415 | /* Need to transfer the left or right part of the register, based on |
416 | the targets byte order. */ | |
88658117 AC |
417 | switch (endian) |
418 | { | |
419 | case BFD_ENDIAN_BIG: | |
72a155b4 | 420 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
421 | break; |
422 | case BFD_ENDIAN_LITTLE: | |
423 | reg_offset = 0; | |
424 | break; | |
6d82d43b | 425 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
426 | reg_offset = 0; |
427 | break; | |
428 | default: | |
e2e0b3e5 | 429 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
430 | } |
431 | if (mips_debug) | |
cb1d2653 AC |
432 | fprintf_unfiltered (gdb_stderr, |
433 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
434 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
435 | if (mips_debug && out != NULL) |
436 | { | |
437 | int i; | |
cb1d2653 | 438 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 439 | for (i = 0; i < length; i++) |
cb1d2653 | 440 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
441 | } |
442 | if (in != NULL) | |
6d82d43b AC |
443 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
444 | in + buf_offset); | |
88658117 | 445 | if (out != NULL) |
6d82d43b AC |
446 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
447 | out + buf_offset); | |
88658117 AC |
448 | if (mips_debug && in != NULL) |
449 | { | |
450 | int i; | |
cb1d2653 | 451 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 452 | for (i = 0; i < length; i++) |
cb1d2653 | 453 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
454 | } |
455 | if (mips_debug) | |
456 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
457 | } | |
458 | ||
dd824b04 DJ |
459 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
460 | compatiblity mode. A return value of 1 means that we have | |
461 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
462 | ||
463 | static int | |
9c9acae0 | 464 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 465 | { |
72a155b4 | 466 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
467 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
468 | meaningful. */ | |
72a155b4 | 469 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
470 | return 0; |
471 | ||
472 | #if 0 | |
473 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
474 | in all the places we deal with FP registers. PR gdb/413. */ | |
475 | /* Otherwise check the FR bit in the status register - it controls | |
476 | the FP compatiblity mode. If it is clear we are in compatibility | |
477 | mode. */ | |
9c9acae0 | 478 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
479 | return 1; |
480 | #endif | |
361d1df0 | 481 | |
dd824b04 DJ |
482 | return 0; |
483 | } | |
484 | ||
7a292a7a | 485 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 486 | |
74ed0bb4 | 487 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 488 | |
a14ed312 | 489 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 490 | |
025bb325 | 491 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
492 | |
493 | static struct cmd_list_element *setmipscmdlist = NULL; | |
494 | static struct cmd_list_element *showmipscmdlist = NULL; | |
495 | ||
5e2e9765 KB |
496 | /* Integer registers 0 thru 31 are handled explicitly by |
497 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 498 | are listed in the following tables. */ |
691c0433 | 499 | |
6d82d43b AC |
500 | enum |
501 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
502 | |
503 | /* Generic MIPS. */ | |
504 | ||
505 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
506 | "sr", "lo", "hi", "bad", "cause", "pc", |
507 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
508 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
509 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
510 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 511 | "fsr", "fir", |
691c0433 AC |
512 | }; |
513 | ||
514 | /* Names of IDT R3041 registers. */ | |
515 | ||
516 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
517 | "sr", "lo", "hi", "bad", "cause", "pc", |
518 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
519 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
520 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
521 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
522 | "fsr", "fir", "", /*"fp" */ "", | |
523 | "", "", "bus", "ccfg", "", "", "", "", | |
524 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
525 | }; |
526 | ||
527 | /* Names of tx39 registers. */ | |
528 | ||
529 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
530 | "sr", "lo", "hi", "bad", "cause", "pc", |
531 | "", "", "", "", "", "", "", "", | |
532 | "", "", "", "", "", "", "", "", | |
533 | "", "", "", "", "", "", "", "", | |
534 | "", "", "", "", "", "", "", "", | |
535 | "", "", "", "", | |
536 | "", "", "", "", "", "", "", "", | |
1faeff08 | 537 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
538 | }; |
539 | ||
540 | /* Names of IRIX registers. */ | |
541 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
542 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
543 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
544 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
545 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
546 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
547 | }; |
548 | ||
44099a67 | 549 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
550 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
551 | "sr", "lo", "hi", "bad", "cause", "pc", | |
552 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
553 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
554 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
555 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
556 | "fsr", "fir" | |
557 | }; | |
558 | ||
cce74817 | 559 | |
5e2e9765 | 560 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 561 | static const char * |
d93859e2 | 562 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 563 | { |
d93859e2 | 564 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
565 | /* GPR names for all ABIs other than n32/n64. */ |
566 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
567 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
568 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
569 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
570 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
571 | }; |
572 | ||
573 | /* GPR names for n32 and n64 ABIs. */ | |
574 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
575 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
576 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
577 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
578 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
579 | }; |
580 | ||
d93859e2 | 581 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 582 | |
f57d151a | 583 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
584 | but then don't make the raw register names visible. This (upper) |
585 | range of user visible register numbers are the pseudo-registers. | |
586 | ||
587 | This approach was adopted accommodate the following scenario: | |
588 | It is possible to debug a 64-bit device using a 32-bit | |
589 | programming model. In such instances, the raw registers are | |
590 | configured to be 64-bits wide, while the pseudo registers are | |
591 | configured to be 32-bits wide. The registers that the user | |
592 | sees - the pseudo registers - match the users expectations | |
593 | given the programming model being used. */ | |
d93859e2 UW |
594 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
595 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
596 | return ""; |
597 | ||
5e2e9765 KB |
598 | /* The MIPS integer registers are always mapped from 0 to 31. The |
599 | names of the registers (which reflects the conventions regarding | |
600 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 601 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
602 | { |
603 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 604 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 605 | else |
a4b8ebc8 | 606 | return mips_gpr_names[rawnum]; |
5e2e9765 | 607 | } |
d93859e2 UW |
608 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
609 | return tdesc_register_name (gdbarch, rawnum); | |
610 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
611 | { |
612 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
613 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
614 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
615 | return ""; | |
691c0433 | 616 | } |
5e2e9765 KB |
617 | else |
618 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 619 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 620 | } |
5e2e9765 | 621 | |
a4b8ebc8 | 622 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 623 | |
a4b8ebc8 AC |
624 | static int |
625 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
626 | struct reggroup *reggroup) | |
627 | { | |
628 | int vector_p; | |
629 | int float_p; | |
630 | int raw_p; | |
72a155b4 UW |
631 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
632 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
633 | if (reggroup == all_reggroup) |
634 | return pseudo; | |
635 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
636 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
637 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
638 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
639 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
640 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
641 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
642 | return 0; |
643 | if (reggroup == float_reggroup) | |
644 | return float_p && pseudo; | |
645 | if (reggroup == vector_reggroup) | |
646 | return vector_p && pseudo; | |
647 | if (reggroup == general_reggroup) | |
648 | return (!vector_p && !float_p) && pseudo; | |
649 | /* Save the pseudo registers. Need to make certain that any code | |
650 | extracting register values from a saved register cache also uses | |
651 | pseudo registers. */ | |
652 | if (reggroup == save_reggroup) | |
653 | return raw_p && pseudo; | |
654 | /* Restore the same pseudo register. */ | |
655 | if (reggroup == restore_reggroup) | |
656 | return raw_p && pseudo; | |
6d82d43b | 657 | return 0; |
a4b8ebc8 AC |
658 | } |
659 | ||
f8b73d13 DJ |
660 | /* Return the groups that a MIPS register can be categorised into. |
661 | This version is only used if we have a target description which | |
662 | describes real registers (and their groups). */ | |
663 | ||
664 | static int | |
665 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
666 | struct reggroup *reggroup) | |
667 | { | |
668 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
669 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
670 | int ret; | |
671 | ||
672 | /* Only save, restore, and display the pseudo registers. Need to | |
673 | make certain that any code extracting register values from a | |
674 | saved register cache also uses pseudo registers. | |
675 | ||
676 | Note: saving and restoring the pseudo registers is slightly | |
677 | strange; if we have 64 bits, we should save and restore all | |
678 | 64 bits. But this is hard and has little benefit. */ | |
679 | if (!pseudo) | |
680 | return 0; | |
681 | ||
682 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
683 | if (ret != -1) | |
684 | return ret; | |
685 | ||
686 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
687 | } | |
688 | ||
a4b8ebc8 | 689 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 690 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 691 | registers. Take care of alignment and size problems. */ |
c5aa993b | 692 | |
05d1431c | 693 | static enum register_status |
a4b8ebc8 | 694 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 695 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 696 | { |
72a155b4 UW |
697 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
698 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
699 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 700 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 701 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
702 | else if (register_size (gdbarch, rawnum) > |
703 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 704 | { |
8bdf35dc | 705 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 706 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 707 | else |
8bdf35dc KB |
708 | { |
709 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
710 | LONGEST regval; | |
05d1431c PA |
711 | enum register_status status; |
712 | ||
713 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
714 | if (status == REG_VALID) | |
715 | store_signed_integer (buf, 4, byte_order, regval); | |
716 | return status; | |
8bdf35dc | 717 | } |
47ebcfbe AC |
718 | } |
719 | else | |
e2e0b3e5 | 720 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
721 | } |
722 | ||
723 | static void | |
6d82d43b AC |
724 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
725 | struct regcache *regcache, int cookednum, | |
47a35522 | 726 | const gdb_byte *buf) |
a4b8ebc8 | 727 | { |
72a155b4 UW |
728 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
729 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
730 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 731 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 732 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
733 | else if (register_size (gdbarch, rawnum) > |
734 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 735 | { |
8bdf35dc | 736 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
737 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
738 | else | |
8bdf35dc KB |
739 | { |
740 | /* Sign extend the shortened version of the register prior | |
741 | to placing it in the raw register. This is required for | |
742 | some mips64 parts in order to avoid unpredictable behavior. */ | |
743 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
744 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
745 | regcache_raw_write_signed (regcache, rawnum, regval); | |
746 | } | |
47ebcfbe AC |
747 | } |
748 | else | |
e2e0b3e5 | 749 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 750 | } |
c5aa993b | 751 | |
175ff332 HZ |
752 | static int |
753 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
754 | struct agent_expr *ax, int reg) | |
755 | { | |
756 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
757 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
758 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
759 | ||
760 | ax_reg_mask (ax, rawnum); | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | static int | |
766 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
767 | struct agent_expr *ax, int reg) | |
768 | { | |
769 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
770 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
771 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
772 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
773 | { | |
774 | ax_reg (ax, rawnum); | |
775 | ||
776 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
777 | { | |
778 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
779 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
780 | { | |
781 | ax_const_l (ax, 32); | |
782 | ax_simple (ax, aop_lsh); | |
783 | } | |
784 | ax_const_l (ax, 32); | |
785 | ax_simple (ax, aop_rsh_signed); | |
786 | } | |
787 | } | |
788 | else | |
789 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
4cc0665f | 794 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 795 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
796 | |
797 | /* Heuristic_proc_start may hunt through the text section for a long | |
798 | time across a 2400 baud serial line. Allows the user to limit this | |
799 | search. */ | |
800 | ||
44096aee | 801 | static int heuristic_fence_post = 0; |
c906108c | 802 | |
46cd78fb | 803 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
804 | register N. NOTE: This defines the pseudo register type so need to |
805 | rebuild the architecture vector. */ | |
43e526b9 JM |
806 | |
807 | static int mips64_transfers_32bit_regs_p = 0; | |
808 | ||
719ec221 AC |
809 | static void |
810 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
811 | struct cmd_list_element *c) | |
43e526b9 | 812 | { |
719ec221 AC |
813 | struct gdbarch_info info; |
814 | gdbarch_info_init (&info); | |
815 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
816 | instead of relying on globals. Doing that would let generic code | |
817 | handle the search for this specific architecture. */ | |
818 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 819 | { |
719ec221 | 820 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 821 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 822 | } |
a4b8ebc8 AC |
823 | } |
824 | ||
47ebcfbe | 825 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 826 | |
ee51a8c7 KB |
827 | /* This predicate tests for the case of an 8 byte floating point |
828 | value that is being transferred to or from a pair of floating point | |
829 | registers each of which are (or are considered to be) only 4 bytes | |
830 | wide. */ | |
ff2e87ac | 831 | static int |
ee51a8c7 KB |
832 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
833 | struct type *type) | |
ff2e87ac | 834 | { |
0abe36f5 MD |
835 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
836 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 837 | && mips_float_register_p (gdbarch, regnum) |
6d82d43b | 838 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
839 | } |
840 | ||
ee51a8c7 KB |
841 | /* This predicate tests for the case of a value of less than 8 |
842 | bytes in width that is being transfered to or from an 8 byte | |
843 | general purpose register. */ | |
844 | static int | |
845 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
846 | struct type *type) | |
847 | { | |
848 | int num_regs = gdbarch_num_regs (gdbarch); | |
849 | ||
850 | return (register_size (gdbarch, regnum) == 8 | |
851 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
852 | && TYPE_LENGTH (type) < 8); | |
853 | } | |
854 | ||
855 | static int | |
025bb325 MS |
856 | mips_convert_register_p (struct gdbarch *gdbarch, |
857 | int regnum, struct type *type) | |
ee51a8c7 | 858 | { |
eaa05d59 MR |
859 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
860 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); | |
ee51a8c7 KB |
861 | } |
862 | ||
8dccd430 | 863 | static int |
ff2e87ac | 864 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
865 | struct type *type, gdb_byte *to, |
866 | int *optimizedp, int *unavailablep) | |
102182a9 | 867 | { |
ee51a8c7 KB |
868 | struct gdbarch *gdbarch = get_frame_arch (frame); |
869 | ||
870 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
871 | { | |
872 | get_frame_register (frame, regnum + 0, to + 4); | |
873 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
874 | |
875 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
876 | optimizedp, unavailablep)) | |
877 | return 0; | |
878 | ||
879 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
880 | optimizedp, unavailablep)) | |
881 | return 0; | |
882 | *optimizedp = *unavailablep = 0; | |
883 | return 1; | |
ee51a8c7 KB |
884 | } |
885 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
886 | { | |
887 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
888 | CORE_ADDR offset; |
889 | ||
890 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
891 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
892 | optimizedp, unavailablep)) | |
893 | return 0; | |
894 | ||
895 | *optimizedp = *unavailablep = 0; | |
896 | return 1; | |
ee51a8c7 KB |
897 | } |
898 | else | |
899 | { | |
900 | internal_error (__FILE__, __LINE__, | |
901 | _("mips_register_to_value: unrecognized case")); | |
902 | } | |
102182a9 MS |
903 | } |
904 | ||
42c466d7 | 905 | static void |
ff2e87ac | 906 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 907 | struct type *type, const gdb_byte *from) |
102182a9 | 908 | { |
ee51a8c7 KB |
909 | struct gdbarch *gdbarch = get_frame_arch (frame); |
910 | ||
911 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
912 | { | |
913 | put_frame_register (frame, regnum + 0, from + 4); | |
914 | put_frame_register (frame, regnum + 1, from + 0); | |
915 | } | |
916 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
917 | { | |
918 | gdb_byte fill[8]; | |
919 | int len = TYPE_LENGTH (type); | |
920 | ||
921 | /* Sign extend values, irrespective of type, that are stored to | |
922 | a 64-bit general purpose register. (32-bit unsigned values | |
923 | are stored as signed quantities within a 64-bit register. | |
924 | When performing an operation, in compiled code, that combines | |
925 | a 32-bit unsigned value with a signed 64-bit value, a type | |
926 | conversion is first performed that zeroes out the high 32 bits.) */ | |
927 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
928 | { | |
929 | if (from[0] & 0x80) | |
930 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
931 | else | |
932 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
933 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
934 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
935 | } | |
936 | else | |
937 | { | |
938 | if (from[len-1] & 0x80) | |
939 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
940 | else | |
941 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
942 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
943 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
944 | } | |
945 | } | |
946 | else | |
947 | { | |
948 | internal_error (__FILE__, __LINE__, | |
949 | _("mips_value_to_register: unrecognized case")); | |
950 | } | |
102182a9 MS |
951 | } |
952 | ||
a4b8ebc8 AC |
953 | /* Return the GDB type object for the "standard" data type of data in |
954 | register REG. */ | |
78fde5f8 KB |
955 | |
956 | static struct type * | |
a4b8ebc8 AC |
957 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
958 | { | |
72a155b4 | 959 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 960 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 961 | { |
5ef80fb0 | 962 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 963 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 964 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 965 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 966 | else |
27067745 | 967 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 968 | } |
72a155b4 | 969 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
970 | { |
971 | /* The raw or ISA registers. These are all sized according to | |
972 | the ISA regsize. */ | |
973 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 974 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 975 | else |
df4df182 | 976 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 977 | } |
78fde5f8 | 978 | else |
d5ac5a39 | 979 | { |
1faeff08 MR |
980 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
981 | ||
d5ac5a39 AC |
982 | /* The cooked or ABI registers. These are sized according to |
983 | the ABI (with a few complications). */ | |
1faeff08 MR |
984 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
985 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
986 | return builtin_type (gdbarch)->builtin_int32; | |
987 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX | |
988 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
989 | && rawnum >= MIPS_FIRST_EMBED_REGNUM | |
990 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
991 | /* The pseudo/cooked view of the embedded registers is always |
992 | 32-bit. The raw view is handled below. */ | |
df4df182 | 993 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
994 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
995 | /* The target, while possibly using a 64-bit register buffer, | |
996 | is only transfering 32-bits of each integer register. | |
997 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 998 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
999 | else if (mips_abi_regsize (gdbarch) == 4) |
1000 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
1001 | 32- or 64-bit). */ | |
df4df182 | 1002 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1003 | else |
1004 | /* 64-bit ABI. */ | |
df4df182 | 1005 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1006 | } |
78fde5f8 KB |
1007 | } |
1008 | ||
f8b73d13 DJ |
1009 | /* Return the GDB type for the pseudo register REGNUM, which is the |
1010 | ABI-level view. This function is only called if there is a target | |
1011 | description which includes registers, so we know precisely the | |
1012 | types of hardware registers. */ | |
1013 | ||
1014 | static struct type * | |
1015 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1016 | { | |
1017 | const int num_regs = gdbarch_num_regs (gdbarch); | |
f8b73d13 DJ |
1018 | int rawnum = regnum % num_regs; |
1019 | struct type *rawtype; | |
1020 | ||
1021 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1022 | ||
1023 | /* Absent registers are still absent. */ | |
1024 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
1025 | if (TYPE_LENGTH (rawtype) == 0) | |
1026 | return rawtype; | |
1027 | ||
de13fcf2 | 1028 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1029 | /* Present the floating point registers however the hardware did; |
1030 | do not try to convert between FPU layouts. */ | |
1031 | return rawtype; | |
1032 | ||
f8b73d13 DJ |
1033 | /* Use pointer types for registers if we can. For n32 we can not, |
1034 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
1035 | if (mips_abi_regsize (gdbarch) |
1036 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 1037 | { |
1faeff08 MR |
1038 | if (rawnum == MIPS_SP_REGNUM |
1039 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1040 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1041 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1042 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1043 | } |
1044 | ||
1045 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
1046 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1047 | || rawnum == mips_regnum (gdbarch)->lo | |
1048 | || rawnum == mips_regnum (gdbarch)->hi | |
1049 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1050 | || rawnum == mips_regnum (gdbarch)->cause | |
1051 | || rawnum == mips_regnum (gdbarch)->pc | |
1052 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1053 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1054 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1055 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1056 | |
1faeff08 MR |
1057 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
1058 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
1059 | && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 | |
1060 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
1061 | { | |
1062 | /* The pseudo/cooked view of embedded registers is always | |
1063 | 32-bit, even if the target transfers 64-bit values for them. | |
1064 | New targets relying on XML descriptions should only transfer | |
1065 | the necessary 32 bits, but older versions of GDB expected 64, | |
1066 | so allow the target to provide 64 bits without interfering | |
1067 | with the displayed type. */ | |
1068 | return builtin_type (gdbarch)->builtin_int32; | |
1069 | } | |
1070 | ||
f8b73d13 DJ |
1071 | /* For all other registers, pass through the hardware type. */ |
1072 | return rawtype; | |
1073 | } | |
bcb0cc15 | 1074 | |
025bb325 | 1075 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 1076 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1077 | |
1078 | static int | |
480d3dd2 | 1079 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
1080 | { |
1081 | switch (mask_address_var) | |
1082 | { | |
7f19b9a2 | 1083 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1084 | return 1; |
7f19b9a2 | 1085 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1086 | return 0; |
1087 | break; | |
7f19b9a2 | 1088 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1089 | return tdep->default_mask_address_p; |
4014092b | 1090 | default: |
025bb325 MS |
1091 | internal_error (__FILE__, __LINE__, |
1092 | _("mips_mask_address_p: bad switch")); | |
4014092b | 1093 | return -1; |
361d1df0 | 1094 | } |
4014092b AC |
1095 | } |
1096 | ||
1097 | static void | |
08546159 AC |
1098 | show_mask_address (struct ui_file *file, int from_tty, |
1099 | struct cmd_list_element *c, const char *value) | |
4014092b | 1100 | { |
f5656ead | 1101 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
08546159 AC |
1102 | |
1103 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1104 | switch (mask_address_var) |
1105 | { | |
7f19b9a2 | 1106 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1107 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1108 | break; | |
7f19b9a2 | 1109 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1110 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1111 | break; | |
7f19b9a2 | 1112 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1113 | printf_filtered |
1114 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1115 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1116 | break; |
1117 | default: | |
e2e0b3e5 | 1118 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1119 | break; |
361d1df0 | 1120 | } |
4014092b | 1121 | } |
c906108c | 1122 | |
4cc0665f MR |
1123 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1124 | function. */ | |
1125 | ||
1126 | int | |
1127 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1128 | { | |
7cbd4a93 | 1129 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1130 | |
1131 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1132 | stored by elfread.c in the high bit of the info field. Use this | |
1133 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1134 | of the address is clear, then this is a standard MIPS function. */ | |
1135 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
7cbd4a93 TT |
1136 | if (sym.minsym) |
1137 | return msymbol_is_mips (sym.minsym); | |
4cc0665f MR |
1138 | else |
1139 | return is_mips_addr (memaddr); | |
1140 | } | |
1141 | ||
c906108c SS |
1142 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1143 | ||
0fe7e7c8 | 1144 | int |
4cc0665f | 1145 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c | 1146 | { |
7cbd4a93 | 1147 | struct bound_minimal_symbol sym; |
c906108c | 1148 | |
91912e4d MR |
1149 | /* A flag indicating that this is a MIPS16 function is stored by |
1150 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1151 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1152 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
1153 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
7cbd4a93 TT |
1154 | if (sym.minsym) |
1155 | return msymbol_is_mips16 (sym.minsym); | |
4cc0665f MR |
1156 | else |
1157 | return is_mips16_addr (gdbarch, memaddr); | |
1158 | } | |
1159 | ||
1160 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1161 | ||
1162 | int | |
1163 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1164 | { | |
7cbd4a93 | 1165 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1166 | |
1167 | /* A flag indicating that this is a microMIPS function is stored by | |
1168 | elfread.c in the high bit of the info field. Use this to decide | |
1169 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1170 | is set, then ELF file flags will tell if this is a microMIPS | |
1171 | function. */ | |
1172 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
7cbd4a93 TT |
1173 | if (sym.minsym) |
1174 | return msymbol_is_micromips (sym.minsym); | |
4cc0665f MR |
1175 | else |
1176 | return is_micromips_addr (gdbarch, memaddr); | |
1177 | } | |
1178 | ||
1179 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1180 | is in. */ | |
1181 | ||
1182 | static enum mips_isa | |
1183 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1184 | { | |
7cbd4a93 | 1185 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1186 | |
1187 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1188 | is stored by elfread.c in the high bit of the info field. Use | |
1189 | this to decide if the function is MIPS16 or microMIPS or normal | |
1190 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1191 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
c906108c | 1192 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 | 1193 | if (sym.minsym) |
4cc0665f | 1194 | { |
7cbd4a93 | 1195 | if (msymbol_is_micromips (sym.minsym)) |
4cc0665f | 1196 | return ISA_MICROMIPS; |
7cbd4a93 | 1197 | else if (msymbol_is_mips16 (sym.minsym)) |
4cc0665f MR |
1198 | return ISA_MIPS16; |
1199 | else | |
1200 | return ISA_MIPS; | |
1201 | } | |
c906108c | 1202 | else |
4cc0665f MR |
1203 | { |
1204 | if (is_mips_addr (memaddr)) | |
1205 | return ISA_MIPS; | |
1206 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1207 | return ISA_MICROMIPS; | |
1208 | else | |
1209 | return ISA_MIPS16; | |
1210 | } | |
c906108c SS |
1211 | } |
1212 | ||
14132e89 MR |
1213 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1214 | ||
1215 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1216 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1217 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1218 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1219 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1220 | ||
1221 | /* This is used as a PIC thunk prefix. */ | |
1222 | ||
1223 | static const char mips_str_pic[] = ".pic."; | |
1224 | ||
1225 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1226 | trampoline) that should be treated as a temporary frame. */ | |
1227 | ||
1228 | static int | |
1229 | mips_in_frame_stub (CORE_ADDR pc) | |
1230 | { | |
1231 | CORE_ADDR start_addr; | |
1232 | const char *name; | |
1233 | ||
1234 | /* Find the starting address of the function containing the PC. */ | |
1235 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1236 | return 0; | |
1237 | ||
1238 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
1239 | if (strncmp (name, mips_str_mips16_call_stub, | |
1240 | strlen (mips_str_mips16_call_stub)) == 0) | |
1241 | return 1; | |
1242 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
1243 | if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
1244 | return 1; | |
1245 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
1246 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0) | |
1247 | return 1; | |
1248 | ||
1249 | return 0; /* Not a stub. */ | |
1250 | } | |
1251 | ||
b2fa5097 | 1252 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1253 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1254 | |
1255 | static CORE_ADDR | |
61a1198a | 1256 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1257 | { |
8376de04 | 1258 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
70242eb1 | 1259 | LONGEST pc; |
8376de04 | 1260 | |
61a1198a | 1261 | regcache_cooked_read_signed (regcache, regnum, &pc); |
4cc0665f MR |
1262 | if (is_compact_addr (pc)) |
1263 | pc = unmake_compact_addr (pc); | |
61a1198a | 1264 | return pc; |
b6cb9035 AC |
1265 | } |
1266 | ||
58dfe9ff AC |
1267 | static CORE_ADDR |
1268 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1269 | { | |
14132e89 | 1270 | CORE_ADDR pc; |
930bd0e0 | 1271 | |
8376de04 | 1272 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
4cc0665f MR |
1273 | if (is_compact_addr (pc)) |
1274 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1275 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1276 | intermediate frames. In this case we can get the caller's address | |
1277 | from $ra, or if $ra contains an address within a thunk as well, then | |
1278 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1279 | and thus the caller's address is in $s2. */ | |
1280 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1281 | { | |
1282 | pc = frame_unwind_register_signed | |
1283 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
4cc0665f MR |
1284 | if (is_compact_addr (pc)) |
1285 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1286 | if (mips_in_frame_stub (pc)) |
1287 | { | |
1288 | pc = frame_unwind_register_signed | |
1289 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
4cc0665f MR |
1290 | if (is_compact_addr (pc)) |
1291 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1292 | } |
1293 | } | |
930bd0e0 | 1294 | return pc; |
edfae063 AC |
1295 | } |
1296 | ||
30244cd8 UW |
1297 | static CORE_ADDR |
1298 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1299 | { | |
72a155b4 UW |
1300 | return frame_unwind_register_signed |
1301 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1302 | } |
1303 | ||
b8a22b94 | 1304 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1305 | dummy frame. The frame ID's base needs to match the TOS value |
1306 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1307 | breakpoint. */ | |
1308 | ||
1309 | static struct frame_id | |
b8a22b94 | 1310 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1311 | { |
f57d151a | 1312 | return frame_id_build |
b8a22b94 DJ |
1313 | (get_frame_register_signed (this_frame, |
1314 | gdbarch_num_regs (gdbarch) | |
1315 | + MIPS_SP_REGNUM), | |
1316 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1317 | } |
1318 | ||
5a439849 MR |
1319 | /* Implement the "write_pc" gdbarch method. */ |
1320 | ||
1321 | void | |
61a1198a | 1322 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1323 | { |
8376de04 MR |
1324 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
1325 | ||
4cc0665f | 1326 | if (mips_pc_is_mips (pc)) |
930bd0e0 | 1327 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
4cc0665f MR |
1328 | else |
1329 | regcache_cooked_write_unsigned (regcache, regnum, make_compact_addr (pc)); | |
6c997a34 | 1330 | } |
c906108c | 1331 | |
4cc0665f MR |
1332 | /* Fetch and return instruction from the specified location. Handle |
1333 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1334 | |
d37cca3d | 1335 | static ULONGEST |
4cc0665f MR |
1336 | mips_fetch_instruction (struct gdbarch *gdbarch, |
1337 | enum mips_isa isa, CORE_ADDR addr, int *statusp) | |
c906108c | 1338 | { |
e17a4113 | 1339 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1340 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1341 | int instlen; |
1342 | int status; | |
1343 | ||
4cc0665f | 1344 | switch (isa) |
c906108c | 1345 | { |
4cc0665f MR |
1346 | case ISA_MICROMIPS: |
1347 | case ISA_MIPS16: | |
95ac2dcf | 1348 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1349 | addr = unmake_compact_addr (addr); |
1350 | break; | |
1351 | case ISA_MIPS: | |
1352 | instlen = MIPS_INSN32_SIZE; | |
1353 | break; | |
1354 | default: | |
1355 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1356 | break; | |
c906108c | 1357 | } |
8defab1a | 1358 | status = target_read_memory (addr, buf, instlen); |
4cc0665f MR |
1359 | if (statusp != NULL) |
1360 | *statusp = status; | |
c906108c | 1361 | if (status) |
4cc0665f MR |
1362 | { |
1363 | if (statusp == NULL) | |
1364 | memory_error (status, addr); | |
1365 | return 0; | |
1366 | } | |
e17a4113 | 1367 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1368 | } |
1369 | ||
025bb325 | 1370 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1371 | #define mips32_op(x) (x >> 26) |
1372 | #define itype_op(x) (x >> 26) | |
1373 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1374 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1375 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1376 | |
e135b889 DJ |
1377 | #define jtype_op(x) (x >> 26) |
1378 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1379 | |
e135b889 DJ |
1380 | #define rtype_op(x) (x >> 26) |
1381 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1382 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1383 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1384 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1385 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1386 | |
4cc0665f MR |
1387 | /* MicroMIPS instruction fields. */ |
1388 | #define micromips_op(x) ((x) >> 10) | |
1389 | ||
1390 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1391 | bit and the size respectively of the field extracted. */ | |
1392 | #define b0s4_imm(x) ((x) & 0xf) | |
1393 | #define b0s5_imm(x) ((x) & 0x1f) | |
1394 | #define b0s5_reg(x) ((x) & 0x1f) | |
1395 | #define b0s7_imm(x) ((x) & 0x7f) | |
1396 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1397 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1398 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1399 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1400 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1401 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1402 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1403 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1404 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1405 | ||
1406 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1407 | respectively of the field extracted. */ | |
1408 | #define b0s6_op(x) ((x) & 0x3f) | |
1409 | #define b0s11_op(x) ((x) & 0x7ff) | |
1410 | #define b0s12_imm(x) ((x) & 0xfff) | |
1411 | #define b0s16_imm(x) ((x) & 0xffff) | |
1412 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1413 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1414 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1415 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1416 | ||
1417 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1418 | instruction set. */ | |
1419 | ||
1420 | static int | |
1421 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1422 | { | |
1423 | switch (isa) | |
1424 | { | |
1425 | case ISA_MICROMIPS: | |
1426 | if (micromips_op (insn) == 0x1f) | |
1427 | return 3 * MIPS_INSN16_SIZE; | |
1428 | else if (((micromips_op (insn) & 0x4) == 0x4) | |
1429 | || ((micromips_op (insn) & 0x7) == 0x0)) | |
1430 | return 2 * MIPS_INSN16_SIZE; | |
1431 | else | |
1432 | return MIPS_INSN16_SIZE; | |
1433 | case ISA_MIPS16: | |
1434 | if ((insn & 0xf800) == 0xf000) | |
1435 | return 2 * MIPS_INSN16_SIZE; | |
1436 | else | |
1437 | return MIPS_INSN16_SIZE; | |
1438 | case ISA_MIPS: | |
1439 | return MIPS_INSN32_SIZE; | |
1440 | } | |
1441 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1442 | } | |
1443 | ||
06987e64 MK |
1444 | static LONGEST |
1445 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1446 | { |
06987e64 | 1447 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1448 | } |
1449 | ||
a385295e MR |
1450 | /* Determine the address of the next instruction executed after the INST |
1451 | floating condition branch instruction at PC. COUNT specifies the | |
1452 | number of the floating condition bits tested by the branch. */ | |
1453 | ||
1454 | static CORE_ADDR | |
1455 | mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1456 | ULONGEST inst, CORE_ADDR pc, int count) | |
1457 | { | |
1458 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1459 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1460 | int tf = itype_rt (inst) & 1; | |
1461 | int mask = (1 << count) - 1; | |
1462 | ULONGEST fcs; | |
1463 | int cond; | |
1464 | ||
1465 | if (fcsr == -1) | |
1466 | /* No way to handle; it'll most likely trap anyway. */ | |
1467 | return pc; | |
1468 | ||
1469 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1470 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1471 | ||
1472 | if (((cond >> cnum) & mask) != mask * !tf) | |
1473 | pc += mips32_relative_offset (inst); | |
1474 | else | |
1475 | pc += 4; | |
1476 | ||
1477 | return pc; | |
1478 | } | |
1479 | ||
f94363d7 AP |
1480 | /* Return nonzero if the gdbarch is an Octeon series. */ |
1481 | ||
1482 | static int | |
1483 | is_octeon (struct gdbarch *gdbarch) | |
1484 | { | |
1485 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
1486 | ||
1487 | return (info->mach == bfd_mach_mips_octeon | |
1488 | || info->mach == bfd_mach_mips_octeonp | |
1489 | || info->mach == bfd_mach_mips_octeon2); | |
1490 | } | |
1491 | ||
1492 | /* Return true if the OP represents the Octeon's BBIT instruction. */ | |
1493 | ||
1494 | static int | |
1495 | is_octeon_bbit_op (int op, struct gdbarch *gdbarch) | |
1496 | { | |
1497 | if (!is_octeon (gdbarch)) | |
1498 | return 0; | |
1499 | /* BBIT0 is encoded as LWC2: 110 010. */ | |
1500 | /* BBIT032 is encoded as LDC2: 110 110. */ | |
1501 | /* BBIT1 is encoded as SWC2: 111 010. */ | |
1502 | /* BBIT132 is encoded as SDC2: 111 110. */ | |
1503 | if (op == 50 || op == 54 || op == 58 || op == 62) | |
1504 | return 1; | |
1505 | return 0; | |
1506 | } | |
1507 | ||
1508 | ||
f49e4e6d MS |
1509 | /* Determine where to set a single step breakpoint while considering |
1510 | branch prediction. */ | |
78a59c2f | 1511 | |
5a89d8aa | 1512 | static CORE_ADDR |
0b1b3e42 | 1513 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1514 | { |
e17a4113 | 1515 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1516 | unsigned long inst; |
1517 | int op; | |
4cc0665f | 1518 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
4f5bcb50 | 1519 | op = itype_op (inst); |
025bb325 MS |
1520 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1521 | instruction. */ | |
c5aa993b | 1522 | { |
4f5bcb50 | 1523 | if (op >> 2 == 5) |
6d82d43b | 1524 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1525 | { |
4f5bcb50 | 1526 | switch (op & 0x03) |
c906108c | 1527 | { |
e135b889 DJ |
1528 | case 0: /* BEQL */ |
1529 | goto equal_branch; | |
1530 | case 1: /* BNEL */ | |
1531 | goto neq_branch; | |
1532 | case 2: /* BLEZL */ | |
1533 | goto less_branch; | |
313628cc | 1534 | case 3: /* BGTZL */ |
e135b889 | 1535 | goto greater_branch; |
c5aa993b JM |
1536 | default: |
1537 | pc += 4; | |
c906108c SS |
1538 | } |
1539 | } | |
4f5bcb50 | 1540 | else if (op == 17 && itype_rs (inst) == 8) |
6d82d43b | 1541 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e | 1542 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
4f5bcb50 | 1543 | else if (op == 17 && itype_rs (inst) == 9 |
a385295e MR |
1544 | && (itype_rt (inst) & 2) == 0) |
1545 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
1546 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); | |
4f5bcb50 | 1547 | else if (op == 17 && itype_rs (inst) == 10 |
a385295e MR |
1548 | && (itype_rt (inst) & 2) == 0) |
1549 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
1550 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); | |
4f5bcb50 | 1551 | else if (op == 29) |
9e8da49c MR |
1552 | /* JALX: 011101 */ |
1553 | /* The new PC will be alternate mode. */ | |
1554 | { | |
1555 | unsigned long reg; | |
1556 | ||
1557 | reg = jtype_target (inst) << 2; | |
1558 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1559 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1560 | } | |
f94363d7 AP |
1561 | else if (is_octeon_bbit_op (op, gdbarch)) |
1562 | { | |
1563 | int bit, branch_if; | |
1564 | ||
1565 | branch_if = op == 58 || op == 62; | |
1566 | bit = itype_rt (inst); | |
1567 | ||
1568 | /* Take into account the *32 instructions. */ | |
1569 | if (op == 54 || op == 62) | |
1570 | bit += 32; | |
1571 | ||
1572 | if (((get_frame_register_signed (frame, | |
1573 | itype_rs (inst)) >> bit) & 1) | |
1574 | == branch_if) | |
1575 | pc += mips32_relative_offset (inst) + 4; | |
1576 | else | |
1577 | pc += 8; /* After the delay slot. */ | |
1578 | } | |
1579 | ||
c5aa993b | 1580 | else |
025bb325 | 1581 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1582 | } |
1583 | else | |
025bb325 | 1584 | { /* This gets way messy. */ |
c5aa993b | 1585 | |
025bb325 | 1586 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
4f5bcb50 | 1587 | switch (op & 0x07) /* Extract bits 28,27,26. */ |
c906108c | 1588 | { |
c5aa993b JM |
1589 | case 0: /* SPECIAL */ |
1590 | op = rtype_funct (inst); | |
1591 | switch (op) | |
1592 | { | |
1593 | case 8: /* JR */ | |
1594 | case 9: /* JALR */ | |
025bb325 | 1595 | /* Set PC to that address. */ |
0b1b3e42 | 1596 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1597 | break; |
e38d4e1a DJ |
1598 | case 12: /* SYSCALL */ |
1599 | { | |
1600 | struct gdbarch_tdep *tdep; | |
1601 | ||
1602 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1603 | if (tdep->syscall_next_pc != NULL) | |
1604 | pc = tdep->syscall_next_pc (frame); | |
1605 | else | |
1606 | pc += 4; | |
1607 | } | |
1608 | break; | |
c5aa993b JM |
1609 | default: |
1610 | pc += 4; | |
1611 | } | |
1612 | ||
6d82d43b | 1613 | break; /* end SPECIAL */ |
025bb325 | 1614 | case 1: /* REGIMM */ |
c906108c | 1615 | { |
e135b889 DJ |
1616 | op = itype_rt (inst); /* branch condition */ |
1617 | switch (op) | |
c906108c | 1618 | { |
c5aa993b | 1619 | case 0: /* BLTZ */ |
e135b889 DJ |
1620 | case 2: /* BLTZL */ |
1621 | case 16: /* BLTZAL */ | |
c5aa993b | 1622 | case 18: /* BLTZALL */ |
c906108c | 1623 | less_branch: |
0b1b3e42 | 1624 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1625 | pc += mips32_relative_offset (inst) + 4; |
1626 | else | |
1627 | pc += 8; /* after the delay slot */ | |
1628 | break; | |
e135b889 | 1629 | case 1: /* BGEZ */ |
c5aa993b JM |
1630 | case 3: /* BGEZL */ |
1631 | case 17: /* BGEZAL */ | |
1632 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1633 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1634 | pc += mips32_relative_offset (inst) + 4; |
1635 | else | |
1636 | pc += 8; /* after the delay slot */ | |
1637 | break; | |
a385295e MR |
1638 | case 0x1c: /* BPOSGE32 */ |
1639 | case 0x1e: /* BPOSGE64 */ | |
1640 | pc += 4; | |
1641 | if (itype_rs (inst) == 0) | |
1642 | { | |
1643 | unsigned int pos = (op & 2) ? 64 : 32; | |
1644 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1645 | ||
1646 | if (dspctl == -1) | |
1647 | /* No way to handle; it'll most likely trap anyway. */ | |
1648 | break; | |
1649 | ||
1650 | if ((get_frame_register_unsigned (frame, | |
1651 | dspctl) & 0x7f) >= pos) | |
1652 | pc += mips32_relative_offset (inst); | |
1653 | else | |
1654 | pc += 4; | |
1655 | } | |
1656 | break; | |
e135b889 | 1657 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1658 | default: |
1659 | pc += 4; | |
c906108c SS |
1660 | } |
1661 | } | |
6d82d43b | 1662 | break; /* end REGIMM */ |
c5aa993b JM |
1663 | case 2: /* J */ |
1664 | case 3: /* JAL */ | |
1665 | { | |
1666 | unsigned long reg; | |
1667 | reg = jtype_target (inst) << 2; | |
025bb325 | 1668 | /* Upper four bits get never changed... */ |
5b652102 | 1669 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1670 | } |
c5aa993b | 1671 | break; |
e135b889 | 1672 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1673 | equal_branch: |
0b1b3e42 UW |
1674 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1675 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1676 | pc += mips32_relative_offset (inst) + 4; |
1677 | else | |
1678 | pc += 8; | |
1679 | break; | |
e135b889 | 1680 | case 5: /* BNE, BNEL */ |
c5aa993b | 1681 | neq_branch: |
0b1b3e42 UW |
1682 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1683 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1684 | pc += mips32_relative_offset (inst) + 4; |
1685 | else | |
1686 | pc += 8; | |
1687 | break; | |
e135b889 | 1688 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1689 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1690 | pc += mips32_relative_offset (inst) + 4; |
1691 | else | |
1692 | pc += 8; | |
1693 | break; | |
1694 | case 7: | |
e135b889 DJ |
1695 | default: |
1696 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1697 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1698 | pc += mips32_relative_offset (inst) + 4; |
1699 | else | |
1700 | pc += 8; | |
1701 | break; | |
c5aa993b JM |
1702 | } /* switch */ |
1703 | } /* else */ | |
1704 | return pc; | |
1705 | } /* mips32_next_pc */ | |
c906108c | 1706 | |
4cc0665f MR |
1707 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1708 | INSN. */ | |
1709 | ||
1710 | static LONGEST | |
1711 | micromips_relative_offset7 (ULONGEST insn) | |
1712 | { | |
1713 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1714 | } | |
1715 | ||
1716 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1717 | INSN. */ | |
1718 | ||
1719 | static LONGEST | |
1720 | micromips_relative_offset10 (ULONGEST insn) | |
1721 | { | |
1722 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1723 | } | |
1724 | ||
1725 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1726 | INSN. */ | |
1727 | ||
1728 | static LONGEST | |
1729 | micromips_relative_offset16 (ULONGEST insn) | |
1730 | { | |
1731 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1732 | } | |
1733 | ||
1734 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1735 | ||
1736 | static int | |
1737 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1738 | { | |
1739 | ULONGEST insn; | |
1740 | ||
1741 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1742 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1743 | } | |
1744 | ||
1745 | /* Calculate the address of the next microMIPS instruction to execute | |
1746 | after the INSN coprocessor 1 conditional branch instruction at the | |
1747 | address PC. COUNT denotes the number of coprocessor condition bits | |
1748 | examined by the branch. */ | |
1749 | ||
1750 | static CORE_ADDR | |
1751 | micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1752 | ULONGEST insn, CORE_ADDR pc, int count) | |
1753 | { | |
1754 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1755 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1756 | int tf = b5s5_op (insn >> 16) & 1; | |
1757 | int mask = (1 << count) - 1; | |
1758 | ULONGEST fcs; | |
1759 | int cond; | |
1760 | ||
1761 | if (fcsr == -1) | |
1762 | /* No way to handle; it'll most likely trap anyway. */ | |
1763 | return pc; | |
1764 | ||
1765 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1766 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1767 | ||
1768 | if (((cond >> cnum) & mask) != mask * !tf) | |
1769 | pc += micromips_relative_offset16 (insn); | |
1770 | else | |
1771 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1772 | ||
1773 | return pc; | |
1774 | } | |
1775 | ||
1776 | /* Calculate the address of the next microMIPS instruction to execute | |
1777 | after the instruction at the address PC. */ | |
1778 | ||
1779 | static CORE_ADDR | |
1780 | micromips_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
1781 | { | |
1782 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1783 | ULONGEST insn; | |
1784 | ||
1785 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1786 | pc += MIPS_INSN16_SIZE; | |
1787 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1788 | { | |
1789 | /* 48-bit instructions. */ | |
1790 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
1791 | /* No branch or jump instructions in this category. */ | |
1792 | pc += 2 * MIPS_INSN16_SIZE; | |
1793 | break; | |
1794 | ||
1795 | /* 32-bit instructions. */ | |
1796 | case 2 * MIPS_INSN16_SIZE: | |
1797 | insn <<= 16; | |
1798 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1799 | pc += MIPS_INSN16_SIZE; | |
1800 | switch (micromips_op (insn >> 16)) | |
1801 | { | |
1802 | case 0x00: /* POOL32A: bits 000000 */ | |
1803 | if (b0s6_op (insn) == 0x3c | |
1804 | /* POOL32Axf: bits 000000 ... 111100 */ | |
1805 | && (b6s10_ext (insn) & 0x2bf) == 0x3c) | |
1806 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
1807 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
1808 | pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16)); | |
1809 | break; | |
1810 | ||
1811 | case 0x10: /* POOL32I: bits 010000 */ | |
1812 | switch (b5s5_op (insn >> 16)) | |
1813 | { | |
1814 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1815 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1816 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
1817 | if (get_frame_register_signed (frame, | |
1818 | b0s5_reg (insn >> 16)) < 0) | |
1819 | pc += micromips_relative_offset16 (insn); | |
1820 | else | |
1821 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1822 | break; | |
1823 | ||
1824 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1825 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1826 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
1827 | if (get_frame_register_signed (frame, | |
1828 | b0s5_reg (insn >> 16)) >= 0) | |
1829 | pc += micromips_relative_offset16 (insn); | |
1830 | else | |
1831 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1832 | break; | |
1833 | ||
1834 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
1835 | if (get_frame_register_signed (frame, | |
1836 | b0s5_reg (insn >> 16)) <= 0) | |
1837 | pc += micromips_relative_offset16 (insn); | |
1838 | else | |
1839 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1840 | break; | |
1841 | ||
1842 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
1843 | if (get_frame_register_signed (frame, | |
1844 | b0s5_reg (insn >> 16)) != 0) | |
1845 | pc += micromips_relative_offset16 (insn); | |
1846 | break; | |
1847 | ||
1848 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
1849 | if (get_frame_register_signed (frame, | |
1850 | b0s5_reg (insn >> 16)) > 0) | |
1851 | pc += micromips_relative_offset16 (insn); | |
1852 | else | |
1853 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1854 | break; | |
1855 | ||
1856 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
1857 | if (get_frame_register_signed (frame, | |
1858 | b0s5_reg (insn >> 16)) == 0) | |
1859 | pc += micromips_relative_offset16 (insn); | |
1860 | break; | |
1861 | ||
1862 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
1863 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
1864 | if (((insn >> 16) & 0x3) == 0x0) | |
1865 | /* BC2F, BC2T: don't know how to handle these. */ | |
1866 | break; | |
1867 | break; | |
1868 | ||
1869 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
1870 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
1871 | { | |
1872 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
1873 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1874 | ||
1875 | if (dspctl == -1) | |
1876 | /* No way to handle; it'll most likely trap anyway. */ | |
1877 | break; | |
1878 | ||
1879 | if ((get_frame_register_unsigned (frame, | |
1880 | dspctl) & 0x7f) >= pos) | |
1881 | pc += micromips_relative_offset16 (insn); | |
1882 | else | |
1883 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1884 | } | |
1885 | break; | |
1886 | ||
1887 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
1888 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
1889 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
1890 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
1891 | if (((insn >> 16) & 0x2) == 0x0) | |
1892 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, | |
1893 | ((insn >> 16) & 0x1) + 1); | |
1894 | break; | |
1895 | ||
1896 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
1897 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
1898 | if (((insn >> 16) & 0x3) == 0x1) | |
1899 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4); | |
1900 | break; | |
1901 | } | |
1902 | break; | |
1903 | ||
1904 | case 0x1d: /* JALS: bits 011101 */ | |
1905 | case 0x35: /* J: bits 110101 */ | |
1906 | case 0x3d: /* JAL: bits 111101 */ | |
1907 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
1908 | break; | |
1909 | ||
1910 | case 0x25: /* BEQ: bits 100101 */ | |
1911 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1912 | == get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1913 | pc += micromips_relative_offset16 (insn); | |
1914 | else | |
1915 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1916 | break; | |
1917 | ||
1918 | case 0x2d: /* BNE: bits 101101 */ | |
1919 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1920 | != get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1921 | pc += micromips_relative_offset16 (insn); | |
1922 | else | |
1923 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1924 | break; | |
1925 | ||
1926 | case 0x3c: /* JALX: bits 111100 */ | |
1927 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
1928 | break; | |
1929 | } | |
1930 | break; | |
1931 | ||
1932 | /* 16-bit instructions. */ | |
1933 | case MIPS_INSN16_SIZE: | |
1934 | switch (micromips_op (insn)) | |
1935 | { | |
1936 | case 0x11: /* POOL16C: bits 010001 */ | |
1937 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
1938 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
1939 | pc = get_frame_register_signed (frame, b0s5_reg (insn)); | |
1940 | else if (b5s5_op (insn) == 0x18) | |
1941 | /* JRADDIUSP: bits 010001 11000 */ | |
1942 | pc = get_frame_register_signed (frame, MIPS_RA_REGNUM); | |
1943 | break; | |
1944 | ||
1945 | case 0x23: /* BEQZ16: bits 100011 */ | |
1946 | { | |
1947 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1948 | ||
1949 | if (get_frame_register_signed (frame, rs) == 0) | |
1950 | pc += micromips_relative_offset7 (insn); | |
1951 | else | |
1952 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1953 | } | |
1954 | break; | |
1955 | ||
1956 | case 0x2b: /* BNEZ16: bits 101011 */ | |
1957 | { | |
1958 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1959 | ||
1960 | if (get_frame_register_signed (frame, rs) != 0) | |
1961 | pc += micromips_relative_offset7 (insn); | |
1962 | else | |
1963 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1964 | } | |
1965 | break; | |
1966 | ||
1967 | case 0x33: /* B16: bits 110011 */ | |
1968 | pc += micromips_relative_offset10 (insn); | |
1969 | break; | |
1970 | } | |
1971 | break; | |
1972 | } | |
1973 | ||
1974 | return pc; | |
1975 | } | |
1976 | ||
c906108c | 1977 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
1978 | mips 16 variant, but fortunately, there fewer instructions. We have |
1979 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1980 | 32 bit instructions. We dont want to set a single step instruction | |
1981 | on the extend instruction either. */ | |
c906108c SS |
1982 | |
1983 | /* Lots of mips16 instruction formats */ | |
1984 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1985 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1986 | enum mips16_inst_fmts |
1987 | { | |
c5aa993b JM |
1988 | itype, /* 0 immediate 5,10 */ |
1989 | ritype, /* 1 5,3,8 */ | |
1990 | rrtype, /* 2 5,3,3,5 */ | |
1991 | rritype, /* 3 5,3,3,5 */ | |
1992 | rrrtype, /* 4 5,3,3,3,2 */ | |
1993 | rriatype, /* 5 5,3,3,1,4 */ | |
1994 | shifttype, /* 6 5,3,3,3,2 */ | |
1995 | i8type, /* 7 5,3,8 */ | |
1996 | i8movtype, /* 8 5,3,3,5 */ | |
1997 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1998 | i64type, /* 10 5,3,8 */ | |
1999 | ri64type, /* 11 5,3,3,5 */ | |
2000 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
2001 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
2002 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
2003 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
2004 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
2005 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
2006 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
2007 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
2008 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
2009 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
2010 | }; | |
12f02c2a | 2011 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 2012 | then, only the fields which are involved in instruction extension. */ |
c906108c | 2013 | struct upk_mips16 |
6d82d43b AC |
2014 | { |
2015 | CORE_ADDR offset; | |
025bb325 | 2016 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
2017 | unsigned int regy; |
2018 | }; | |
c906108c SS |
2019 | |
2020 | ||
12f02c2a | 2021 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 2022 | for the bits which make up the immediate extension. */ |
c906108c | 2023 | |
12f02c2a AC |
2024 | static CORE_ADDR |
2025 | extended_offset (unsigned int extension) | |
c906108c | 2026 | { |
12f02c2a | 2027 | CORE_ADDR value; |
130854df | 2028 | |
4c2051c6 | 2029 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 2030 | value = value << 6; |
4c2051c6 | 2031 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 2032 | value = value << 5; |
130854df MR |
2033 | value |= extension & 0x1f; /* Extract 4:0. */ |
2034 | ||
c5aa993b | 2035 | return value; |
c906108c SS |
2036 | } |
2037 | ||
2038 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
2039 | instruction. It won't malfunction, but why make excess remote memory |
2040 | references? If the immediate operands get sign extended or something, | |
2041 | do it after the extension is performed. */ | |
c906108c | 2042 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 2043 | when the offset is to be used in relative addressing. */ |
c906108c | 2044 | |
12f02c2a | 2045 | static unsigned int |
e17a4113 | 2046 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2047 | { |
e17a4113 | 2048 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 2049 | gdb_byte buf[8]; |
a2fb2cee MR |
2050 | |
2051 | pc = unmake_compact_addr (pc); /* Clear the low order bit. */ | |
c5aa993b | 2052 | target_read_memory (pc, buf, 2); |
e17a4113 | 2053 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
2054 | } |
2055 | ||
2056 | static void | |
e17a4113 | 2057 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
2058 | unsigned int extension, |
2059 | unsigned int inst, | |
6d82d43b | 2060 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2061 | { |
12f02c2a AC |
2062 | CORE_ADDR offset; |
2063 | int regx; | |
2064 | int regy; | |
2065 | switch (insn_format) | |
c906108c | 2066 | { |
c5aa993b | 2067 | case itype: |
c906108c | 2068 | { |
12f02c2a AC |
2069 | CORE_ADDR value; |
2070 | if (extension) | |
c5aa993b | 2071 | { |
4c2051c6 MR |
2072 | value = extended_offset ((extension << 16) | inst); |
2073 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2074 | } |
2075 | else | |
c5aa993b | 2076 | { |
12f02c2a | 2077 | value = inst & 0x7ff; |
4c2051c6 | 2078 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2079 | } |
12f02c2a AC |
2080 | offset = value; |
2081 | regx = -1; | |
2082 | regy = -1; | |
c906108c | 2083 | } |
c5aa993b JM |
2084 | break; |
2085 | case ritype: | |
2086 | case i8type: | |
025bb325 | 2087 | { /* A register identifier and an offset. */ |
c906108c | 2088 | /* Most of the fields are the same as I type but the |
025bb325 | 2089 | immediate value is of a different length. */ |
12f02c2a AC |
2090 | CORE_ADDR value; |
2091 | if (extension) | |
c906108c | 2092 | { |
4c2051c6 MR |
2093 | value = extended_offset ((extension << 16) | inst); |
2094 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2095 | } |
c5aa993b JM |
2096 | else |
2097 | { | |
4c2051c6 MR |
2098 | value = inst & 0xff; /* 8 bits */ |
2099 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2100 | } |
12f02c2a | 2101 | offset = value; |
4c2051c6 | 2102 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2103 | regy = -1; |
c5aa993b | 2104 | break; |
c906108c | 2105 | } |
c5aa993b | 2106 | case jalxtype: |
c906108c | 2107 | { |
c5aa993b | 2108 | unsigned long value; |
12f02c2a AC |
2109 | unsigned int nexthalf; |
2110 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2111 | value = value << 16; |
4cc0665f MR |
2112 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2113 | /* Low bit still set. */ | |
c5aa993b | 2114 | value |= nexthalf; |
12f02c2a AC |
2115 | offset = value; |
2116 | regx = -1; | |
2117 | regy = -1; | |
c5aa993b | 2118 | break; |
c906108c SS |
2119 | } |
2120 | default: | |
e2e0b3e5 | 2121 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 2122 | } |
12f02c2a AC |
2123 | upk->offset = offset; |
2124 | upk->regx = regx; | |
2125 | upk->regy = regy; | |
c906108c SS |
2126 | } |
2127 | ||
2128 | ||
484933d1 MR |
2129 | /* Calculate the destination of a branch whose 16-bit opcode word is at PC, |
2130 | and having a signed 16-bit OFFSET. */ | |
2131 | ||
c5aa993b JM |
2132 | static CORE_ADDR |
2133 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2134 | { |
484933d1 | 2135 | return pc + (offset << 1) + 2; |
c906108c SS |
2136 | } |
2137 | ||
12f02c2a | 2138 | static CORE_ADDR |
0b1b3e42 | 2139 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 2140 | unsigned int extension, unsigned int insn) |
c906108c | 2141 | { |
e17a4113 | 2142 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
2143 | int op = (insn >> 11); |
2144 | switch (op) | |
c906108c | 2145 | { |
6d82d43b | 2146 | case 2: /* Branch */ |
12f02c2a | 2147 | { |
12f02c2a | 2148 | struct upk_mips16 upk; |
e17a4113 | 2149 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
484933d1 | 2150 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2151 | break; |
2152 | } | |
025bb325 MS |
2153 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2154 | instructions. */ | |
12f02c2a AC |
2155 | { |
2156 | struct upk_mips16 upk; | |
e17a4113 | 2157 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
484933d1 | 2158 | pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); |
12f02c2a | 2159 | if ((insn >> 10) & 0x01) /* Exchange mode */ |
025bb325 | 2160 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2161 | else |
2162 | pc |= 0x01; | |
2163 | break; | |
2164 | } | |
6d82d43b | 2165 | case 4: /* beqz */ |
12f02c2a AC |
2166 | { |
2167 | struct upk_mips16 upk; | |
2168 | int reg; | |
e17a4113 | 2169 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2170 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2171 | if (reg == 0) |
484933d1 | 2172 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2173 | else |
2174 | pc += 2; | |
2175 | break; | |
2176 | } | |
6d82d43b | 2177 | case 5: /* bnez */ |
12f02c2a AC |
2178 | { |
2179 | struct upk_mips16 upk; | |
2180 | int reg; | |
e17a4113 | 2181 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2182 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2183 | if (reg != 0) |
484933d1 | 2184 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2185 | else |
2186 | pc += 2; | |
2187 | break; | |
2188 | } | |
6d82d43b | 2189 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2190 | { |
2191 | struct upk_mips16 upk; | |
2192 | int reg; | |
e17a4113 | 2193 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2194 | /* upk.regx contains the opcode */ |
0b1b3e42 | 2195 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
2196 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2197 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
484933d1 | 2198 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2199 | else |
2200 | pc += 2; | |
2201 | break; | |
2202 | } | |
6d82d43b | 2203 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2204 | { |
2205 | struct upk_mips16 upk; | |
2206 | /* upk.fmt = rrtype; */ | |
2207 | op = insn & 0x1f; | |
2208 | if (op == 0) | |
c5aa993b | 2209 | { |
12f02c2a AC |
2210 | int reg; |
2211 | upk.regx = (insn >> 8) & 0x07; | |
2212 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2213 | if ((upk.regy & 1) == 0) |
4cc0665f | 2214 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2215 | else |
2216 | reg = 31; /* Function return instruction. */ | |
0b1b3e42 | 2217 | pc = get_frame_register_signed (frame, reg); |
c906108c | 2218 | } |
12f02c2a | 2219 | else |
c5aa993b | 2220 | pc += 2; |
12f02c2a AC |
2221 | break; |
2222 | } | |
2223 | case 30: | |
2224 | /* This is an instruction extension. Fetch the real instruction | |
2225 | (which follows the extension) and decode things based on | |
025bb325 | 2226 | that. */ |
12f02c2a AC |
2227 | { |
2228 | pc += 2; | |
e17a4113 UW |
2229 | pc = extended_mips16_next_pc (frame, pc, insn, |
2230 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
2231 | break; |
2232 | } | |
2233 | default: | |
2234 | { | |
2235 | pc += 2; | |
2236 | break; | |
2237 | } | |
c906108c | 2238 | } |
c5aa993b | 2239 | return pc; |
12f02c2a | 2240 | } |
c906108c | 2241 | |
5a89d8aa | 2242 | static CORE_ADDR |
0b1b3e42 | 2243 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 2244 | { |
e17a4113 UW |
2245 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2246 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 2247 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
2248 | } |
2249 | ||
2250 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2251 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2252 | It works by decoding the current instruction and predicting where a |
1aee363c | 2253 | branch will go. This isn't hard because all the data is available. |
4cc0665f | 2254 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2255 | static CORE_ADDR |
0b1b3e42 | 2256 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2257 | { |
4cc0665f MR |
2258 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2259 | ||
2260 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
0b1b3e42 | 2261 | return mips16_next_pc (frame, pc); |
4cc0665f MR |
2262 | else if (mips_pc_is_micromips (gdbarch, pc)) |
2263 | return micromips_next_pc (frame, pc); | |
c5aa993b | 2264 | else |
0b1b3e42 | 2265 | return mips32_next_pc (frame, pc); |
12f02c2a | 2266 | } |
c906108c | 2267 | |
ab50adb6 MR |
2268 | /* Return non-zero if the MIPS16 instruction INSN is a compact branch |
2269 | or jump. */ | |
2270 | ||
2271 | static int | |
2272 | mips16_instruction_is_compact_branch (unsigned short insn) | |
2273 | { | |
2274 | switch (insn & 0xf800) | |
2275 | { | |
2276 | case 0xe800: | |
2277 | return (insn & 0x009f) == 0x80; /* JALRC/JRC */ | |
2278 | case 0x6000: | |
2279 | return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ | |
2280 | case 0x2800: /* BNEZ */ | |
2281 | case 0x2000: /* BEQZ */ | |
2282 | case 0x1000: /* B */ | |
2283 | return 1; | |
2284 | default: | |
2285 | return 0; | |
2286 | } | |
2287 | } | |
2288 | ||
2289 | /* Return non-zero if the microMIPS instruction INSN is a compact branch | |
2290 | or jump. */ | |
2291 | ||
2292 | static int | |
2293 | micromips_instruction_is_compact_branch (unsigned short insn) | |
2294 | { | |
2295 | switch (micromips_op (insn)) | |
2296 | { | |
2297 | case 0x11: /* POOL16C: bits 010001 */ | |
2298 | return (b5s5_op (insn) == 0x18 | |
2299 | /* JRADDIUSP: bits 010001 11000 */ | |
2300 | || b5s5_op (insn) == 0xd); | |
2301 | /* JRC: bits 010011 01101 */ | |
2302 | case 0x10: /* POOL32I: bits 010000 */ | |
2303 | return (b5s5_op (insn) & 0x1d) == 0x5; | |
2304 | /* BEQZC/BNEZC: bits 010000 001x1 */ | |
2305 | default: | |
2306 | return 0; | |
2307 | } | |
2308 | } | |
2309 | ||
edfae063 AC |
2310 | struct mips_frame_cache |
2311 | { | |
2312 | CORE_ADDR base; | |
2313 | struct trad_frame_saved_reg *saved_regs; | |
2314 | }; | |
2315 | ||
29639122 JB |
2316 | /* Set a register's saved stack address in temp_saved_regs. If an |
2317 | address has already been set for this register, do nothing; this | |
2318 | way we will only recognize the first save of a given register in a | |
2319 | function prologue. | |
eec63939 | 2320 | |
f57d151a UW |
2321 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2322 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2323 | Strictly speaking, only the second range is used as it is only second | |
2324 | range (the ABI instead of ISA registers) that comes into play when finding | |
2325 | saved registers in a frame. */ | |
eec63939 AC |
2326 | |
2327 | static void | |
74ed0bb4 MD |
2328 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2329 | int regnum, CORE_ADDR offset) | |
eec63939 | 2330 | { |
29639122 JB |
2331 | if (this_cache != NULL |
2332 | && this_cache->saved_regs[regnum].addr == -1) | |
2333 | { | |
74ed0bb4 MD |
2334 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
2335 | = offset; | |
2336 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
2337 | = offset; | |
29639122 | 2338 | } |
eec63939 AC |
2339 | } |
2340 | ||
eec63939 | 2341 | |
29639122 JB |
2342 | /* Fetch the immediate value from a MIPS16 instruction. |
2343 | If the previous instruction was an EXTEND, use it to extend | |
2344 | the upper bits of the immediate value. This is a helper function | |
2345 | for mips16_scan_prologue. */ | |
eec63939 | 2346 | |
29639122 JB |
2347 | static int |
2348 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2349 | unsigned short inst, /* current instruction */ | |
2350 | int nbits, /* number of bits in imm field */ | |
2351 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2352 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2353 | { |
29639122 | 2354 | int offset; |
eec63939 | 2355 | |
29639122 JB |
2356 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2357 | { | |
2358 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2359 | if (offset & 0x8000) /* check for negative extend */ | |
2360 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2361 | return offset | (inst & 0x1f); | |
2362 | } | |
eec63939 | 2363 | else |
29639122 JB |
2364 | { |
2365 | int max_imm = 1 << nbits; | |
2366 | int mask = max_imm - 1; | |
2367 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2368 | |
29639122 JB |
2369 | offset = inst & mask; |
2370 | if (is_signed && (offset & sign_bit)) | |
2371 | offset = 0 - (max_imm - offset); | |
2372 | return offset * scale; | |
2373 | } | |
2374 | } | |
eec63939 | 2375 | |
65596487 | 2376 | |
29639122 JB |
2377 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2378 | the associated FRAME_CACHE if not null. | |
2379 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2380 | |
29639122 | 2381 | static CORE_ADDR |
e17a4113 UW |
2382 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2383 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2384 | struct frame_info *this_frame, |
29639122 JB |
2385 | struct mips_frame_cache *this_cache) |
2386 | { | |
ab50adb6 MR |
2387 | int prev_non_prologue_insn = 0; |
2388 | int this_non_prologue_insn; | |
2389 | int non_prologue_insns = 0; | |
2390 | CORE_ADDR prev_pc; | |
29639122 | 2391 | CORE_ADDR cur_pc; |
025bb325 | 2392 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2393 | CORE_ADDR sp; |
2394 | long frame_offset = 0; /* Size of stack frame. */ | |
2395 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2396 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2397 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2398 | unsigned inst = 0; /* current instruction */ |
2399 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2400 | unsigned save_inst = 0; /* the save instruction */ |
ab50adb6 MR |
2401 | int prev_delay_slot = 0; |
2402 | int in_delay_slot; | |
29639122 | 2403 | int reg, offset; |
a343eb3c | 2404 | |
29639122 | 2405 | int extend_bytes = 0; |
ab50adb6 MR |
2406 | int prev_extend_bytes = 0; |
2407 | CORE_ADDR end_prologue_addr; | |
a343eb3c | 2408 | |
29639122 | 2409 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2410 | THIS_FRAME. */ |
2411 | if (this_frame != NULL) | |
2412 | sp = get_frame_register_signed (this_frame, | |
2413 | gdbarch_num_regs (gdbarch) | |
2414 | + MIPS_SP_REGNUM); | |
29639122 JB |
2415 | else |
2416 | sp = 0; | |
eec63939 | 2417 | |
29639122 JB |
2418 | if (limit_pc > start_pc + 200) |
2419 | limit_pc = start_pc + 200; | |
ab50adb6 | 2420 | prev_pc = start_pc; |
eec63939 | 2421 | |
ab50adb6 MR |
2422 | /* Permit at most one non-prologue non-control-transfer instruction |
2423 | in the middle which may have been reordered by the compiler for | |
2424 | optimisation. */ | |
95ac2dcf | 2425 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 | 2426 | { |
ab50adb6 MR |
2427 | this_non_prologue_insn = 0; |
2428 | in_delay_slot = 0; | |
2429 | ||
29639122 JB |
2430 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
2431 | the immediate offset extension from it in mips16_get_imm. */ | |
2432 | prev_inst = inst; | |
eec63939 | 2433 | |
025bb325 | 2434 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2435 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2436 | cur_pc, NULL); | |
eec63939 | 2437 | |
29639122 JB |
2438 | /* Normally we ignore extend instructions. However, if it is |
2439 | not followed by a valid prologue instruction, then this | |
2440 | instruction is not part of the prologue either. We must | |
2441 | remember in this case to adjust the end_prologue_addr back | |
2442 | over the extend. */ | |
2443 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2444 | { | |
95ac2dcf | 2445 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
2446 | continue; |
2447 | } | |
eec63939 | 2448 | |
29639122 JB |
2449 | prev_extend_bytes = extend_bytes; |
2450 | extend_bytes = 0; | |
eec63939 | 2451 | |
29639122 JB |
2452 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2453 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2454 | { | |
2455 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2456 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2457 | frame_offset -= offset; |
2458 | else | |
2459 | /* Exit loop if a positive stack adjustment is found, which | |
2460 | usually means that the stack cleanup code in the function | |
2461 | epilogue is reached. */ | |
2462 | break; | |
2463 | } | |
2464 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2465 | { | |
2466 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2467 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2468 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2469 | } |
2470 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2471 | { | |
2472 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2473 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2474 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2475 | } |
2476 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2477 | { | |
2478 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2479 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2480 | } |
2481 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2482 | { | |
2483 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2484 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2485 | } |
2486 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2487 | { | |
2488 | frame_addr = sp; | |
2489 | frame_reg = 17; | |
2490 | } | |
2491 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2492 | { | |
2493 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2494 | frame_addr = sp + offset; | |
2495 | frame_reg = 17; | |
2496 | frame_adjust = offset; | |
2497 | } | |
2498 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2499 | { | |
2500 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2501 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2502 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2503 | } |
2504 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2505 | { | |
2506 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2507 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2508 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2509 | } |
2510 | else if ((inst & 0xf81f) == 0xe809 | |
2511 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 2512 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2513 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2514 | { | |
025bb325 | 2515 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2516 | if (prev_extend_bytes) /* extend */ |
2517 | save_inst |= prev_inst << 16; | |
2518 | } | |
29639122 JB |
2519 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
2520 | { | |
2521 | /* This instruction is part of the prologue, but we don't | |
2522 | need to do anything special to handle it. */ | |
2523 | } | |
ab50adb6 MR |
2524 | else if (mips16_instruction_has_delay_slot (inst, 0)) |
2525 | /* JAL/JALR/JALX/JR */ | |
2526 | { | |
2527 | /* The instruction in the delay slot can be a part | |
2528 | of the prologue, so move forward once more. */ | |
2529 | in_delay_slot = 1; | |
2530 | if (mips16_instruction_has_delay_slot (inst, 1)) | |
2531 | /* JAL/JALX */ | |
2532 | { | |
2533 | prev_extend_bytes = MIPS_INSN16_SIZE; | |
2534 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ | |
2535 | } | |
2536 | } | |
29639122 JB |
2537 | else |
2538 | { | |
ab50adb6 | 2539 | this_non_prologue_insn = 1; |
29639122 | 2540 | } |
ab50adb6 MR |
2541 | |
2542 | non_prologue_insns += this_non_prologue_insn; | |
2543 | ||
2544 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
2545 | then we must have reached the end of the prologue by now. */ | |
2546 | if (prev_delay_slot || non_prologue_insns > 1 | |
2547 | || mips16_instruction_is_compact_branch (inst)) | |
2548 | break; | |
2549 | ||
2550 | prev_non_prologue_insn = this_non_prologue_insn; | |
2551 | prev_delay_slot = in_delay_slot; | |
2552 | prev_pc = cur_pc - prev_extend_bytes; | |
29639122 | 2553 | } |
eec63939 | 2554 | |
29639122 JB |
2555 | /* The entry instruction is typically the first instruction in a function, |
2556 | and it stores registers at offsets relative to the value of the old SP | |
2557 | (before the prologue). But the value of the sp parameter to this | |
2558 | function is the new SP (after the prologue has been executed). So we | |
2559 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2560 | and can calculate what the old SP must have been. */ |
29639122 JB |
2561 | if (entry_inst != 0) |
2562 | { | |
2563 | int areg_count = (entry_inst >> 8) & 7; | |
2564 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2565 | |
29639122 JB |
2566 | /* The entry instruction always subtracts 32 from the SP. */ |
2567 | frame_offset += 32; | |
2568 | ||
2569 | /* Now we can calculate what the SP must have been at the | |
2570 | start of the function prologue. */ | |
2571 | sp += frame_offset; | |
2572 | ||
2573 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2574 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2575 | { | |
74ed0bb4 | 2576 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2577 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2578 | } |
2579 | ||
2580 | /* Check if the ra register was pushed on the stack. */ | |
2581 | offset = -4; | |
2582 | if (entry_inst & 0x20) | |
2583 | { | |
74ed0bb4 | 2584 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2585 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2586 | } |
2587 | ||
2588 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2589 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2590 | { | |
74ed0bb4 | 2591 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2592 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2593 | } |
2594 | } | |
2595 | ||
2207132d MR |
2596 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2597 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2598 | size of the frame is specified as an immediate field of instruction | |
2599 | and an extended variation exists which lets additional registers and | |
2600 | frame space to be specified. The instruction always treats registers | |
2601 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2602 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2603 | { | |
2604 | static int args_table[16] = { | |
2605 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2606 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2607 | }; | |
2608 | static int astatic_table[16] = { | |
2609 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2610 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2611 | }; | |
2612 | int aregs = (save_inst >> 16) & 0xf; | |
2613 | int xsregs = (save_inst >> 24) & 0x7; | |
2614 | int args = args_table[aregs]; | |
2615 | int astatic = astatic_table[aregs]; | |
2616 | long frame_size; | |
2617 | ||
2618 | if (args < 0) | |
2619 | { | |
2620 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2621 | args = 0; | |
2622 | } | |
2623 | if (astatic < 0) | |
2624 | { | |
2625 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2626 | astatic = 0; | |
2627 | } | |
2628 | ||
2629 | /* For standard SAVE the frame size of 0 means 128. */ | |
2630 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2631 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2632 | frame_size = 16; | |
2633 | frame_size *= 8; | |
2634 | frame_offset += frame_size; | |
2635 | ||
2636 | /* Now we can calculate what the SP must have been at the | |
2637 | start of the function prologue. */ | |
2638 | sp += frame_offset; | |
2639 | ||
2640 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2641 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2642 | { | |
74ed0bb4 | 2643 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2644 | offset += mips_abi_regsize (gdbarch); |
2645 | } | |
2646 | ||
2647 | offset = -4; | |
2648 | ||
2649 | /* Check if the RA register was pushed on the stack. */ | |
2650 | if (save_inst & 0x40) | |
2651 | { | |
74ed0bb4 | 2652 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2653 | offset -= mips_abi_regsize (gdbarch); |
2654 | } | |
2655 | ||
2656 | /* Check if the S8 register was pushed on the stack. */ | |
2657 | if (xsregs > 6) | |
2658 | { | |
74ed0bb4 | 2659 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2660 | offset -= mips_abi_regsize (gdbarch); |
2661 | xsregs--; | |
2662 | } | |
2663 | /* Check if S2-S7 were pushed on the stack. */ | |
2664 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2665 | { | |
74ed0bb4 | 2666 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2667 | offset -= mips_abi_regsize (gdbarch); |
2668 | } | |
2669 | ||
2670 | /* Check if the S1 register was pushed on the stack. */ | |
2671 | if (save_inst & 0x10) | |
2672 | { | |
74ed0bb4 | 2673 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2674 | offset -= mips_abi_regsize (gdbarch); |
2675 | } | |
2676 | /* Check if the S0 register was pushed on the stack. */ | |
2677 | if (save_inst & 0x20) | |
2678 | { | |
74ed0bb4 | 2679 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2680 | offset -= mips_abi_regsize (gdbarch); |
2681 | } | |
2682 | ||
4cc0665f MR |
2683 | /* Check if A0-A3 were pushed on the stack. */ |
2684 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2685 | { | |
2686 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2687 | offset -= mips_abi_regsize (gdbarch); | |
2688 | } | |
2689 | } | |
2690 | ||
2691 | if (this_cache != NULL) | |
2692 | { | |
2693 | this_cache->base = | |
2694 | (get_frame_register_signed (this_frame, | |
2695 | gdbarch_num_regs (gdbarch) + frame_reg) | |
2696 | + frame_offset - frame_adjust); | |
2697 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
2698 | be able to get rid of the assignment below, evetually. But it's | |
2699 | still needed for now. */ | |
2700 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
2701 | + mips_regnum (gdbarch)->pc] | |
2702 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
2703 | } | |
2704 | ||
ab50adb6 MR |
2705 | /* Set end_prologue_addr to the address of the instruction immediately |
2706 | after the last one we scanned. Unless the last one looked like a | |
2707 | non-prologue instruction (and we looked ahead), in which case use | |
2708 | its address instead. */ | |
2709 | end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot | |
2710 | ? prev_pc : cur_pc - prev_extend_bytes); | |
4cc0665f MR |
2711 | |
2712 | return end_prologue_addr; | |
2713 | } | |
2714 | ||
2715 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2716 | Procedures that use the 32-bit instruction set are handled by the | |
2717 | mips_insn32 unwinder. */ | |
2718 | ||
2719 | static struct mips_frame_cache * | |
2720 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2721 | { | |
2722 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2723 | struct mips_frame_cache *cache; | |
2724 | ||
2725 | if ((*this_cache) != NULL) | |
2726 | return (*this_cache); | |
2727 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
2728 | (*this_cache) = cache; | |
2729 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2730 | ||
2731 | /* Analyze the function prologue. */ | |
2732 | { | |
2733 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2734 | CORE_ADDR start_addr; | |
2735 | ||
2736 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2737 | if (start_addr == 0) | |
2738 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2739 | /* We can't analyze the prologue if we couldn't find the begining | |
2740 | of the function. */ | |
2741 | if (start_addr == 0) | |
2742 | return cache; | |
2743 | ||
2744 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); | |
2745 | } | |
2746 | ||
2747 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
2748 | trad_frame_set_value (cache->saved_regs, | |
2749 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, | |
2750 | cache->base); | |
2751 | ||
2752 | return (*this_cache); | |
2753 | } | |
2754 | ||
2755 | static void | |
2756 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
2757 | struct frame_id *this_id) | |
2758 | { | |
2759 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2760 | this_cache); | |
2761 | /* This marks the outermost frame. */ | |
2762 | if (info->base == 0) | |
2763 | return; | |
2764 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2765 | } | |
2766 | ||
2767 | static struct value * | |
2768 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2769 | void **this_cache, int regnum) | |
2770 | { | |
2771 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2772 | this_cache); | |
2773 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2774 | } | |
2775 | ||
2776 | static int | |
2777 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2778 | struct frame_info *this_frame, void **this_cache) | |
2779 | { | |
2780 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2781 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2782 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2783 | return 1; | |
2784 | return 0; | |
2785 | } | |
2786 | ||
2787 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2788 | { | |
2789 | NORMAL_FRAME, | |
2790 | default_frame_unwind_stop_reason, | |
2791 | mips_insn16_frame_this_id, | |
2792 | mips_insn16_frame_prev_register, | |
2793 | NULL, | |
2794 | mips_insn16_frame_sniffer | |
2795 | }; | |
2796 | ||
2797 | static CORE_ADDR | |
2798 | mips_insn16_frame_base_address (struct frame_info *this_frame, | |
2799 | void **this_cache) | |
2800 | { | |
2801 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2802 | this_cache); | |
2803 | return info->base; | |
2804 | } | |
2805 | ||
2806 | static const struct frame_base mips_insn16_frame_base = | |
2807 | { | |
2808 | &mips_insn16_frame_unwind, | |
2809 | mips_insn16_frame_base_address, | |
2810 | mips_insn16_frame_base_address, | |
2811 | mips_insn16_frame_base_address | |
2812 | }; | |
2813 | ||
2814 | static const struct frame_base * | |
2815 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | |
2816 | { | |
2817 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2818 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2819 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2820 | return &mips_insn16_frame_base; | |
2821 | else | |
2822 | return NULL; | |
2823 | } | |
2824 | ||
2825 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2826 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2827 | interpreted directly, and then multiplied by 4. */ | |
2828 | ||
2829 | static int | |
2830 | micromips_decode_imm9 (int imm) | |
2831 | { | |
2832 | imm = (imm ^ 0x100) - 0x100; | |
2833 | if (imm > -3 && imm < 2) | |
2834 | imm ^= 0x100; | |
2835 | return imm << 2; | |
2836 | } | |
2837 | ||
2838 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2839 | the address of the first instruction past the prologue. */ | |
2840 | ||
2841 | static CORE_ADDR | |
2842 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2843 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
2844 | struct frame_info *this_frame, | |
2845 | struct mips_frame_cache *this_cache) | |
2846 | { | |
ab50adb6 | 2847 | CORE_ADDR end_prologue_addr; |
4cc0665f MR |
2848 | int prev_non_prologue_insn = 0; |
2849 | int frame_reg = MIPS_SP_REGNUM; | |
2850 | int this_non_prologue_insn; | |
2851 | int non_prologue_insns = 0; | |
2852 | long frame_offset = 0; /* Size of stack frame. */ | |
2853 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2854 | CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */ | |
ab50adb6 MR |
2855 | int prev_delay_slot = 0; |
2856 | int in_delay_slot; | |
4cc0665f MR |
2857 | CORE_ADDR prev_pc; |
2858 | CORE_ADDR cur_pc; | |
2859 | ULONGEST insn; /* current instruction */ | |
2860 | CORE_ADDR sp; | |
2861 | long offset; | |
2862 | long sp_adj; | |
2863 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
2864 | int reglist; | |
2865 | int breg; | |
2866 | int dreg; | |
2867 | int sreg; | |
2868 | int treg; | |
2869 | int loc; | |
2870 | int op; | |
2871 | int s; | |
2872 | int i; | |
2873 | ||
2874 | /* Can be called when there's no process, and hence when there's no | |
2875 | THIS_FRAME. */ | |
2876 | if (this_frame != NULL) | |
2877 | sp = get_frame_register_signed (this_frame, | |
2878 | gdbarch_num_regs (gdbarch) | |
2879 | + MIPS_SP_REGNUM); | |
2880 | else | |
2881 | sp = 0; | |
2882 | ||
2883 | if (limit_pc > start_pc + 200) | |
2884 | limit_pc = start_pc + 200; | |
2885 | prev_pc = start_pc; | |
2886 | ||
2887 | /* Permit at most one non-prologue non-control-transfer instruction | |
2888 | in the middle which may have been reordered by the compiler for | |
2889 | optimisation. */ | |
2890 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
2891 | { | |
2892 | this_non_prologue_insn = 0; | |
ab50adb6 | 2893 | in_delay_slot = 0; |
4cc0665f MR |
2894 | sp_adj = 0; |
2895 | loc = 0; | |
2896 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
2897 | loc += MIPS_INSN16_SIZE; | |
2898 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
2899 | { | |
2900 | /* 48-bit instructions. */ | |
2901 | case 3 * MIPS_INSN16_SIZE: | |
2902 | /* No prologue instructions in this category. */ | |
2903 | this_non_prologue_insn = 1; | |
2904 | loc += 2 * MIPS_INSN16_SIZE; | |
2905 | break; | |
2906 | ||
2907 | /* 32-bit instructions. */ | |
2908 | case 2 * MIPS_INSN16_SIZE: | |
2909 | insn <<= 16; | |
2910 | insn |= mips_fetch_instruction (gdbarch, | |
2911 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
2912 | loc += MIPS_INSN16_SIZE; | |
2913 | switch (micromips_op (insn >> 16)) | |
2914 | { | |
2915 | /* Record $sp/$fp adjustment. */ | |
2916 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
2917 | case 0x0: /* POOL32A: bits 000000 */ | |
2918 | case 0x16: /* POOL32S: bits 010110 */ | |
2919 | op = b0s11_op (insn); | |
2920 | sreg = b0s5_reg (insn >> 16); | |
2921 | treg = b5s5_reg (insn >> 16); | |
2922 | dreg = b11s5_reg (insn); | |
2923 | if (op == 0x1d0 | |
2924 | /* SUBU: bits 000000 00111010000 */ | |
2925 | /* DSUBU: bits 010110 00111010000 */ | |
2926 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
2927 | && treg == 3) | |
2928 | /* (D)SUBU $sp, $v1 */ | |
2929 | sp_adj = v1_off; | |
2930 | else if (op != 0x150 | |
2931 | /* ADDU: bits 000000 00101010000 */ | |
2932 | /* DADDU: bits 010110 00101010000 */ | |
2933 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
2934 | this_non_prologue_insn = 1; | |
2935 | break; | |
2936 | ||
2937 | case 0x8: /* POOL32B: bits 001000 */ | |
2938 | op = b12s4_op (insn); | |
2939 | breg = b0s5_reg (insn >> 16); | |
2940 | reglist = sreg = b5s5_reg (insn >> 16); | |
2941 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
2942 | if ((op == 0x9 || op == 0xc) | |
2943 | /* SWP: bits 001000 1001 */ | |
2944 | /* SDP: bits 001000 1100 */ | |
2945 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
2946 | /* S[DW]P reg,offset($sp) */ | |
2947 | { | |
2948 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
2949 | set_reg_offset (gdbarch, this_cache, | |
2950 | sreg, sp + offset); | |
2951 | set_reg_offset (gdbarch, this_cache, | |
2952 | sreg + 1, sp + offset + s); | |
2953 | } | |
2954 | else if ((op == 0xd || op == 0xf) | |
2955 | /* SWM: bits 001000 1101 */ | |
2956 | /* SDM: bits 001000 1111 */ | |
2957 | && breg == MIPS_SP_REGNUM | |
2958 | /* SWM reglist,offset($sp) */ | |
2959 | && ((reglist >= 1 && reglist <= 9) | |
2960 | || (reglist >= 16 && reglist <= 25))) | |
2961 | { | |
2962 | int sreglist = min(reglist & 0xf, 8); | |
2963 | ||
2964 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
2965 | for (i = 0; i < sreglist; i++) | |
2966 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
2967 | if ((reglist & 0xf) > 8) | |
2968 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
2969 | if ((reglist & 0x10) == 0x10) | |
2970 | set_reg_offset (gdbarch, this_cache, | |
2971 | MIPS_RA_REGNUM, sp + s * i++); | |
2972 | } | |
2973 | else | |
2974 | this_non_prologue_insn = 1; | |
2975 | break; | |
2976 | ||
2977 | /* Record $sp/$fp adjustment. */ | |
2978 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
2979 | case 0xc: /* ADDIU: bits 001100 */ | |
2980 | case 0x17: /* DADDIU: bits 010111 */ | |
2981 | sreg = b0s5_reg (insn >> 16); | |
2982 | dreg = b5s5_reg (insn >> 16); | |
2983 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
2984 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
2985 | /* (D)ADDIU $sp, imm */ | |
2986 | sp_adj = offset; | |
2987 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
2988 | /* (D)ADDIU $fp, $sp, imm */ | |
2989 | { | |
2990 | frame_addr = sp + offset; | |
2991 | frame_adjust = offset; | |
2992 | frame_reg = 30; | |
2993 | } | |
2994 | else if (sreg != 28 || dreg != 28) | |
2995 | /* (D)ADDIU $gp, imm */ | |
2996 | this_non_prologue_insn = 1; | |
2997 | break; | |
2998 | ||
2999 | /* LUI $v1 is used for larger $sp adjustments. */ | |
3356937a | 3000 | /* Discard LUI $gp used for PIC code. */ |
4cc0665f MR |
3001 | case 0x10: /* POOL32I: bits 010000 */ |
3002 | if (b5s5_op (insn >> 16) == 0xd | |
3003 | /* LUI: bits 010000 001101 */ | |
3004 | && b0s5_reg (insn >> 16) == 3) | |
3005 | /* LUI $v1, imm */ | |
3006 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
3007 | else if (b5s5_op (insn >> 16) != 0xd | |
3008 | /* LUI: bits 010000 001101 */ | |
3009 | || b0s5_reg (insn >> 16) != 28) | |
3010 | /* LUI $gp, imm */ | |
3011 | this_non_prologue_insn = 1; | |
3012 | break; | |
3013 | ||
3014 | /* ORI $v1 is used for larger $sp adjustments. */ | |
3015 | case 0x14: /* ORI: bits 010100 */ | |
3016 | sreg = b0s5_reg (insn >> 16); | |
3017 | dreg = b5s5_reg (insn >> 16); | |
3018 | if (sreg == 3 && dreg == 3) | |
3019 | /* ORI $v1, imm */ | |
3020 | v1_off |= b0s16_imm (insn); | |
3021 | else | |
3022 | this_non_prologue_insn = 1; | |
3023 | break; | |
3024 | ||
3025 | case 0x26: /* SWC1: bits 100110 */ | |
3026 | case 0x2e: /* SDC1: bits 101110 */ | |
3027 | breg = b0s5_reg (insn >> 16); | |
3028 | if (breg != MIPS_SP_REGNUM) | |
3029 | /* S[DW]C1 reg,offset($sp) */ | |
3030 | this_non_prologue_insn = 1; | |
3031 | break; | |
3032 | ||
3033 | case 0x36: /* SD: bits 110110 */ | |
3034 | case 0x3e: /* SW: bits 111110 */ | |
3035 | breg = b0s5_reg (insn >> 16); | |
3036 | sreg = b5s5_reg (insn >> 16); | |
3037 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3038 | if (breg == MIPS_SP_REGNUM) | |
3039 | /* S[DW] reg,offset($sp) */ | |
3040 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3041 | else | |
3042 | this_non_prologue_insn = 1; | |
3043 | break; | |
3044 | ||
3045 | default: | |
ab50adb6 MR |
3046 | /* The instruction in the delay slot can be a part |
3047 | of the prologue, so move forward once more. */ | |
3048 | if (micromips_instruction_has_delay_slot (insn, 0)) | |
3049 | in_delay_slot = 1; | |
3050 | else | |
3051 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3052 | break; |
3053 | } | |
ab50adb6 | 3054 | insn >>= 16; |
4cc0665f MR |
3055 | break; |
3056 | ||
3057 | /* 16-bit instructions. */ | |
3058 | case MIPS_INSN16_SIZE: | |
3059 | switch (micromips_op (insn)) | |
3060 | { | |
3061 | case 0x3: /* MOVE: bits 000011 */ | |
3062 | sreg = b0s5_reg (insn); | |
3063 | dreg = b5s5_reg (insn); | |
3064 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3065 | /* MOVE $fp, $sp */ | |
3066 | { | |
3067 | frame_addr = sp; | |
3068 | frame_reg = 30; | |
3069 | } | |
3070 | else if ((sreg & 0x1c) != 0x4) | |
3071 | /* MOVE reg, $a0-$a3 */ | |
3072 | this_non_prologue_insn = 1; | |
3073 | break; | |
3074 | ||
3075 | case 0x11: /* POOL16C: bits 010001 */ | |
3076 | if (b6s4_op (insn) == 0x5) | |
3077 | /* SWM: bits 010001 0101 */ | |
3078 | { | |
3079 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
3080 | reglist = b4s2_regl (insn); | |
3081 | for (i = 0; i <= reglist; i++) | |
3082 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
3083 | set_reg_offset (gdbarch, this_cache, | |
3084 | MIPS_RA_REGNUM, sp + 4 * i++); | |
3085 | } | |
3086 | else | |
3087 | this_non_prologue_insn = 1; | |
3088 | break; | |
3089 | ||
3090 | case 0x13: /* POOL16D: bits 010011 */ | |
3091 | if ((insn & 0x1) == 0x1) | |
3092 | /* ADDIUSP: bits 010011 1 */ | |
3093 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
3094 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
3095 | /* ADDIUS5: bits 010011 0 */ | |
3096 | /* ADDIUS5 $sp, imm */ | |
3097 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
3098 | else | |
3099 | this_non_prologue_insn = 1; | |
3100 | break; | |
3101 | ||
3102 | case 0x32: /* SWSP: bits 110010 */ | |
3103 | offset = b0s5_imm (insn) << 2; | |
3104 | sreg = b5s5_reg (insn); | |
3105 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3106 | break; | |
3107 | ||
3108 | default: | |
ab50adb6 MR |
3109 | /* The instruction in the delay slot can be a part |
3110 | of the prologue, so move forward once more. */ | |
3111 | if (micromips_instruction_has_delay_slot (insn << 16, 0)) | |
3112 | in_delay_slot = 1; | |
3113 | else | |
3114 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3115 | break; |
3116 | } | |
3117 | break; | |
3118 | } | |
3119 | if (sp_adj < 0) | |
3120 | frame_offset -= sp_adj; | |
3121 | ||
3122 | non_prologue_insns += this_non_prologue_insn; | |
ab50adb6 MR |
3123 | |
3124 | /* A jump or branch, enough non-prologue insns seen or positive | |
3125 | stack adjustment? If so, then we must have reached the end | |
3126 | of the prologue by now. */ | |
3127 | if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 | |
3128 | || micromips_instruction_is_compact_branch (insn)) | |
3129 | break; | |
3130 | ||
4cc0665f | 3131 | prev_non_prologue_insn = this_non_prologue_insn; |
ab50adb6 | 3132 | prev_delay_slot = in_delay_slot; |
4cc0665f | 3133 | prev_pc = cur_pc; |
2207132d MR |
3134 | } |
3135 | ||
29639122 JB |
3136 | if (this_cache != NULL) |
3137 | { | |
3138 | this_cache->base = | |
4cc0665f | 3139 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3140 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 3141 | + frame_offset - frame_adjust); |
29639122 | 3142 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
3143 | be able to get rid of the assignment below, evetually. But it's |
3144 | still needed for now. */ | |
72a155b4 UW |
3145 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3146 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 3147 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
3148 | } |
3149 | ||
ab50adb6 MR |
3150 | /* Set end_prologue_addr to the address of the instruction immediately |
3151 | after the last one we scanned. Unless the last one looked like a | |
3152 | non-prologue instruction (and we looked ahead), in which case use | |
3153 | its address instead. */ | |
3154 | end_prologue_addr | |
3155 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3156 | |
3157 | return end_prologue_addr; | |
eec63939 AC |
3158 | } |
3159 | ||
4cc0665f | 3160 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3161 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3162 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3163 | |
3164 | static struct mips_frame_cache * | |
4cc0665f | 3165 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 3166 | { |
e17a4113 | 3167 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3168 | struct mips_frame_cache *cache; |
eec63939 AC |
3169 | |
3170 | if ((*this_cache) != NULL) | |
3171 | return (*this_cache); | |
4cc0665f | 3172 | |
29639122 JB |
3173 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3174 | (*this_cache) = cache; | |
b8a22b94 | 3175 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3176 | |
29639122 JB |
3177 | /* Analyze the function prologue. */ |
3178 | { | |
b8a22b94 | 3179 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3180 | CORE_ADDR start_addr; |
eec63939 | 3181 | |
29639122 JB |
3182 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3183 | if (start_addr == 0) | |
4cc0665f | 3184 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3185 | /* We can't analyze the prologue if we couldn't find the begining |
3186 | of the function. */ | |
3187 | if (start_addr == 0) | |
3188 | return cache; | |
eec63939 | 3189 | |
4cc0665f | 3190 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 | 3191 | } |
4cc0665f | 3192 | |
3e8c568d | 3193 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 3194 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3195 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 3196 | cache->base); |
eec63939 | 3197 | |
29639122 | 3198 | return (*this_cache); |
eec63939 AC |
3199 | } |
3200 | ||
3201 | static void | |
4cc0665f MR |
3202 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
3203 | struct frame_id *this_id) | |
eec63939 | 3204 | { |
4cc0665f MR |
3205 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3206 | this_cache); | |
21327321 DJ |
3207 | /* This marks the outermost frame. */ |
3208 | if (info->base == 0) | |
3209 | return; | |
b8a22b94 | 3210 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3211 | } |
3212 | ||
b8a22b94 | 3213 | static struct value * |
4cc0665f MR |
3214 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
3215 | void **this_cache, int regnum) | |
eec63939 | 3216 | { |
4cc0665f MR |
3217 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3218 | this_cache); | |
b8a22b94 DJ |
3219 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3220 | } | |
3221 | ||
3222 | static int | |
4cc0665f MR |
3223 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
3224 | struct frame_info *this_frame, void **this_cache) | |
b8a22b94 | 3225 | { |
4cc0665f | 3226 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3227 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3228 | |
3229 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3230 | return 1; |
3231 | return 0; | |
eec63939 AC |
3232 | } |
3233 | ||
4cc0665f | 3234 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 AC |
3235 | { |
3236 | NORMAL_FRAME, | |
8fbca658 | 3237 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3238 | mips_micro_frame_this_id, |
3239 | mips_micro_frame_prev_register, | |
b8a22b94 | 3240 | NULL, |
4cc0665f | 3241 | mips_micro_frame_sniffer |
eec63939 AC |
3242 | }; |
3243 | ||
eec63939 | 3244 | static CORE_ADDR |
4cc0665f MR |
3245 | mips_micro_frame_base_address (struct frame_info *this_frame, |
3246 | void **this_cache) | |
eec63939 | 3247 | { |
4cc0665f MR |
3248 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3249 | this_cache); | |
29639122 | 3250 | return info->base; |
eec63939 AC |
3251 | } |
3252 | ||
4cc0665f | 3253 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3254 | { |
4cc0665f MR |
3255 | &mips_micro_frame_unwind, |
3256 | mips_micro_frame_base_address, | |
3257 | mips_micro_frame_base_address, | |
3258 | mips_micro_frame_base_address | |
eec63939 AC |
3259 | }; |
3260 | ||
3261 | static const struct frame_base * | |
4cc0665f | 3262 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 3263 | { |
4cc0665f | 3264 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3265 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3266 | |
3267 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3268 | return &mips_micro_frame_base; | |
eec63939 AC |
3269 | else |
3270 | return NULL; | |
edfae063 AC |
3271 | } |
3272 | ||
29639122 JB |
3273 | /* Mark all the registers as unset in the saved_regs array |
3274 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3275 | ||
74ed0bb4 MD |
3276 | static void |
3277 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3278 | { |
29639122 JB |
3279 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3280 | return; | |
3281 | ||
3282 | { | |
74ed0bb4 | 3283 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3284 | int i; |
64159455 | 3285 | |
29639122 JB |
3286 | for (i = 0; i < num_regs; i++) |
3287 | { | |
3288 | this_cache->saved_regs[i].addr = -1; | |
3289 | } | |
3290 | } | |
c906108c SS |
3291 | } |
3292 | ||
025bb325 | 3293 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3294 | the associated FRAME_CACHE if not null. |
3295 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3296 | |
875e1767 | 3297 | static CORE_ADDR |
e17a4113 UW |
3298 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3299 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 3300 | struct frame_info *this_frame, |
29639122 | 3301 | struct mips_frame_cache *this_cache) |
c906108c | 3302 | { |
ab50adb6 MR |
3303 | int prev_non_prologue_insn; |
3304 | int this_non_prologue_insn; | |
3305 | int non_prologue_insns; | |
025bb325 MS |
3306 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3307 | frame-pointer. */ | |
ab50adb6 MR |
3308 | int prev_delay_slot; |
3309 | CORE_ADDR prev_pc; | |
3310 | CORE_ADDR cur_pc; | |
29639122 JB |
3311 | CORE_ADDR sp; |
3312 | long frame_offset; | |
3313 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3314 | |
ab50adb6 | 3315 | CORE_ADDR end_prologue_addr; |
29639122 JB |
3316 | int seen_sp_adjust = 0; |
3317 | int load_immediate_bytes = 0; | |
ab50adb6 | 3318 | int in_delay_slot; |
7d1e6fb8 | 3319 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3320 | |
29639122 | 3321 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3322 | THIS_FRAME. */ |
3323 | if (this_frame != NULL) | |
3324 | sp = get_frame_register_signed (this_frame, | |
3325 | gdbarch_num_regs (gdbarch) | |
3326 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3327 | else |
29639122 | 3328 | sp = 0; |
9022177c | 3329 | |
29639122 JB |
3330 | if (limit_pc > start_pc + 200) |
3331 | limit_pc = start_pc + 200; | |
9022177c | 3332 | |
29639122 | 3333 | restart: |
ab50adb6 MR |
3334 | prev_non_prologue_insn = 0; |
3335 | non_prologue_insns = 0; | |
3336 | prev_delay_slot = 0; | |
3337 | prev_pc = start_pc; | |
9022177c | 3338 | |
ab50adb6 MR |
3339 | /* Permit at most one non-prologue non-control-transfer instruction |
3340 | in the middle which may have been reordered by the compiler for | |
3341 | optimisation. */ | |
29639122 | 3342 | frame_offset = 0; |
95ac2dcf | 3343 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3344 | { |
29639122 JB |
3345 | unsigned long inst, high_word, low_word; |
3346 | int reg; | |
9022177c | 3347 | |
ab50adb6 MR |
3348 | this_non_prologue_insn = 0; |
3349 | in_delay_slot = 0; | |
3350 | ||
025bb325 | 3351 | /* Fetch the instruction. */ |
4cc0665f MR |
3352 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3353 | cur_pc, NULL); | |
9022177c | 3354 | |
29639122 JB |
3355 | /* Save some code by pre-extracting some useful fields. */ |
3356 | high_word = (inst >> 16) & 0xffff; | |
3357 | low_word = inst & 0xffff; | |
3358 | reg = high_word & 0x1f; | |
fe29b929 | 3359 | |
025bb325 | 3360 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3361 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3362 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3363 | { | |
025bb325 | 3364 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
3365 | frame_offset += 0x10000 - low_word; |
3366 | else | |
3367 | /* Exit loop if a positive stack adjustment is found, which | |
3368 | usually means that the stack cleanup code in the function | |
3369 | epilogue is reached. */ | |
3370 | break; | |
3371 | seen_sp_adjust = 1; | |
3372 | } | |
7d1e6fb8 KB |
3373 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
3374 | && !regsize_is_64_bits) | |
29639122 | 3375 | { |
74ed0bb4 | 3376 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 3377 | } |
7d1e6fb8 KB |
3378 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
3379 | && regsize_is_64_bits) | |
29639122 JB |
3380 | { |
3381 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 3382 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
3383 | } |
3384 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3385 | { | |
3386 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
3387 | if ((long) low_word != frame_offset) | |
3388 | frame_addr = sp + low_word; | |
b8a22b94 | 3389 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3390 | { |
3391 | unsigned alloca_adjust; | |
a4b8ebc8 | 3392 | |
29639122 | 3393 | frame_reg = 30; |
b8a22b94 DJ |
3394 | frame_addr = get_frame_register_signed |
3395 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
ca9c94ef | 3396 | frame_offset = 0; |
d2ca4222 | 3397 | |
29639122 JB |
3398 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
3399 | if (alloca_adjust > 0) | |
3400 | { | |
025bb325 | 3401 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3402 | an alloca or somethings similar. Fix sp to |
3403 | "pre-alloca" value, and try again. */ | |
3404 | sp += alloca_adjust; | |
3405 | /* Need to reset the status of all registers. Otherwise, | |
3406 | we will hit a guard that prevents the new address | |
3407 | for each register to be recomputed during the second | |
3408 | pass. */ | |
74ed0bb4 | 3409 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3410 | goto restart; |
3411 | } | |
3412 | } | |
3413 | } | |
3414 | /* move $30,$sp. With different versions of gas this will be either | |
3415 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
3416 | Accept any one of these. */ | |
3417 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3418 | { | |
3419 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3420 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3421 | { |
3422 | unsigned alloca_adjust; | |
c906108c | 3423 | |
29639122 | 3424 | frame_reg = 30; |
b8a22b94 DJ |
3425 | frame_addr = get_frame_register_signed |
3426 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3427 | |
29639122 JB |
3428 | alloca_adjust = (unsigned) (frame_addr - sp); |
3429 | if (alloca_adjust > 0) | |
3430 | { | |
025bb325 | 3431 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3432 | an alloca or somethings similar. Fix sp to |
3433 | "pre-alloca" value, and try again. */ | |
3434 | sp = frame_addr; | |
3435 | /* Need to reset the status of all registers. Otherwise, | |
3436 | we will hit a guard that prevents the new address | |
3437 | for each register to be recomputed during the second | |
3438 | pass. */ | |
74ed0bb4 | 3439 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3440 | goto restart; |
3441 | } | |
3442 | } | |
3443 | } | |
7d1e6fb8 KB |
3444 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
3445 | && !regsize_is_64_bits) | |
29639122 | 3446 | { |
74ed0bb4 | 3447 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
3448 | } |
3449 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
3450 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
3451 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3452 | || high_word == 0x3c1c /* lui $gp,n */ | |
3453 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
3454 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3455 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
3456 | ) | |
19080931 MR |
3457 | { |
3458 | /* These instructions are part of the prologue, but we don't | |
3459 | need to do anything special to handle them. */ | |
3460 | } | |
29639122 JB |
3461 | /* The instructions below load $at or $t0 with an immediate |
3462 | value in preparation for a stack adjustment via | |
025bb325 | 3463 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
3464 | initialize a local variable, so we accept them only before |
3465 | a stack adjustment instruction was seen. */ | |
3466 | else if (!seen_sp_adjust | |
ab50adb6 | 3467 | && !prev_delay_slot |
19080931 MR |
3468 | && (high_word == 0x3c01 /* lui $at,n */ |
3469 | || high_word == 0x3c08 /* lui $t0,n */ | |
3470 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3471 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3472 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3473 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3474 | )) | |
3475 | { | |
ab50adb6 | 3476 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
19080931 | 3477 | } |
ab50adb6 MR |
3478 | /* Check for branches and jumps. The instruction in the delay |
3479 | slot can be a part of the prologue, so move forward once more. */ | |
3480 | else if (mips32_instruction_has_delay_slot (gdbarch, inst)) | |
3481 | { | |
3482 | in_delay_slot = 1; | |
3483 | } | |
3484 | /* This instruction is not an instruction typically found | |
3485 | in a prologue, so we must have reached the end of the | |
3486 | prologue. */ | |
29639122 | 3487 | else |
19080931 | 3488 | { |
ab50adb6 | 3489 | this_non_prologue_insn = 1; |
19080931 | 3490 | } |
db5f024e | 3491 | |
ab50adb6 MR |
3492 | non_prologue_insns += this_non_prologue_insn; |
3493 | ||
3494 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
3495 | then we must have reached the end of the prologue by now. */ | |
3496 | if (prev_delay_slot || non_prologue_insns > 1) | |
db5f024e | 3497 | break; |
ab50adb6 MR |
3498 | |
3499 | prev_non_prologue_insn = this_non_prologue_insn; | |
3500 | prev_delay_slot = in_delay_slot; | |
3501 | prev_pc = cur_pc; | |
a4b8ebc8 | 3502 | } |
c906108c | 3503 | |
29639122 JB |
3504 | if (this_cache != NULL) |
3505 | { | |
3506 | this_cache->base = | |
b8a22b94 DJ |
3507 | (get_frame_register_signed (this_frame, |
3508 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
3509 | + frame_offset); |
3510 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
3511 | this assignment below, eventually. But it's still needed | |
3512 | for now. */ | |
72a155b4 UW |
3513 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3514 | + mips_regnum (gdbarch)->pc] | |
3515 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 3516 | + MIPS_RA_REGNUM]; |
29639122 | 3517 | } |
c906108c | 3518 | |
ab50adb6 MR |
3519 | /* Set end_prologue_addr to the address of the instruction immediately |
3520 | after the last one we scanned. Unless the last one looked like a | |
3521 | non-prologue instruction (and we looked ahead), in which case use | |
3522 | its address instead. */ | |
3523 | end_prologue_addr | |
3524 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3525 | |
3526 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3527 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3528 | if the load immediate was not followed by a stack adjustment. */ |
3529 | if (load_immediate_bytes && !seen_sp_adjust) | |
3530 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3531 | |
29639122 | 3532 | return end_prologue_addr; |
c906108c SS |
3533 | } |
3534 | ||
29639122 JB |
3535 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3536 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3537 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3538 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3539 | |
29639122 | 3540 | static struct mips_frame_cache * |
b8a22b94 | 3541 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 3542 | { |
e17a4113 | 3543 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3544 | struct mips_frame_cache *cache; |
c906108c | 3545 | |
29639122 JB |
3546 | if ((*this_cache) != NULL) |
3547 | return (*this_cache); | |
c5aa993b | 3548 | |
29639122 JB |
3549 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3550 | (*this_cache) = cache; | |
b8a22b94 | 3551 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3552 | |
29639122 JB |
3553 | /* Analyze the function prologue. */ |
3554 | { | |
b8a22b94 | 3555 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3556 | CORE_ADDR start_addr; |
c906108c | 3557 | |
29639122 JB |
3558 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3559 | if (start_addr == 0) | |
e17a4113 | 3560 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3561 | /* We can't analyze the prologue if we couldn't find the begining |
3562 | of the function. */ | |
3563 | if (start_addr == 0) | |
3564 | return cache; | |
c5aa993b | 3565 | |
e17a4113 | 3566 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
3567 | } |
3568 | ||
3e8c568d | 3569 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 3570 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3571 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 3572 | cache->base); |
c5aa993b | 3573 | |
29639122 | 3574 | return (*this_cache); |
c906108c SS |
3575 | } |
3576 | ||
29639122 | 3577 | static void |
b8a22b94 | 3578 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 3579 | struct frame_id *this_id) |
c906108c | 3580 | { |
b8a22b94 | 3581 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3582 | this_cache); |
21327321 DJ |
3583 | /* This marks the outermost frame. */ |
3584 | if (info->base == 0) | |
3585 | return; | |
b8a22b94 | 3586 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3587 | } |
c906108c | 3588 | |
b8a22b94 DJ |
3589 | static struct value * |
3590 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
3591 | void **this_cache, int regnum) | |
29639122 | 3592 | { |
b8a22b94 | 3593 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3594 | this_cache); |
b8a22b94 DJ |
3595 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3596 | } | |
3597 | ||
3598 | static int | |
3599 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
3600 | struct frame_info *this_frame, void **this_cache) | |
3601 | { | |
3602 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3603 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3604 | return 1; |
3605 | return 0; | |
c906108c SS |
3606 | } |
3607 | ||
29639122 JB |
3608 | static const struct frame_unwind mips_insn32_frame_unwind = |
3609 | { | |
3610 | NORMAL_FRAME, | |
8fbca658 | 3611 | default_frame_unwind_stop_reason, |
29639122 | 3612 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3613 | mips_insn32_frame_prev_register, |
3614 | NULL, | |
3615 | mips_insn32_frame_sniffer | |
29639122 | 3616 | }; |
c906108c | 3617 | |
1c645fec | 3618 | static CORE_ADDR |
b8a22b94 | 3619 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 3620 | void **this_cache) |
c906108c | 3621 | { |
b8a22b94 | 3622 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3623 | this_cache); |
3624 | return info->base; | |
3625 | } | |
c906108c | 3626 | |
29639122 JB |
3627 | static const struct frame_base mips_insn32_frame_base = |
3628 | { | |
3629 | &mips_insn32_frame_unwind, | |
3630 | mips_insn32_frame_base_address, | |
3631 | mips_insn32_frame_base_address, | |
3632 | mips_insn32_frame_base_address | |
3633 | }; | |
1c645fec | 3634 | |
29639122 | 3635 | static const struct frame_base * |
b8a22b94 | 3636 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3637 | { |
b8a22b94 | 3638 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3639 | if (mips_pc_is_mips (pc)) |
29639122 | 3640 | return &mips_insn32_frame_base; |
a65bbe44 | 3641 | else |
29639122 JB |
3642 | return NULL; |
3643 | } | |
a65bbe44 | 3644 | |
29639122 | 3645 | static struct trad_frame_cache * |
b8a22b94 | 3646 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
3647 | { |
3648 | CORE_ADDR pc; | |
3649 | CORE_ADDR start_addr; | |
3650 | CORE_ADDR stack_addr; | |
3651 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3652 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3653 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3654 | |
29639122 JB |
3655 | if ((*this_cache) != NULL) |
3656 | return (*this_cache); | |
b8a22b94 | 3657 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3658 | (*this_cache) = this_trad_cache; |
1c645fec | 3659 | |
29639122 | 3660 | /* The return address is in the link register. */ |
3e8c568d | 3661 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3662 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3663 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3664 | |
29639122 JB |
3665 | /* Frame ID, since it's a frameless / stackless function, no stack |
3666 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3667 | pc = get_frame_pc (this_frame); |
29639122 | 3668 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3669 | stack_addr = get_frame_register_signed (this_frame, |
3670 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3671 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3672 | |
29639122 JB |
3673 | /* Assume that the frame's base is the same as the |
3674 | stack-pointer. */ | |
3675 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3676 | |
29639122 JB |
3677 | return this_trad_cache; |
3678 | } | |
c906108c | 3679 | |
29639122 | 3680 | static void |
b8a22b94 | 3681 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
3682 | struct frame_id *this_id) |
3683 | { | |
3684 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3685 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3686 | trad_frame_get_id (this_trad_cache, this_id); |
3687 | } | |
c906108c | 3688 | |
b8a22b94 DJ |
3689 | static struct value * |
3690 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
3691 | void **this_cache, int regnum) | |
29639122 JB |
3692 | { |
3693 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3694 | = mips_stub_frame_cache (this_frame, this_cache); |
3695 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3696 | } |
c906108c | 3697 | |
b8a22b94 DJ |
3698 | static int |
3699 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
3700 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 3701 | { |
aa6c981f | 3702 | gdb_byte dummy[4]; |
979b38e0 | 3703 | struct obj_section *s; |
b8a22b94 | 3704 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
7cbd4a93 | 3705 | struct bound_minimal_symbol msym; |
979b38e0 | 3706 | |
aa6c981f | 3707 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3708 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3709 | return 1; | |
aa6c981f | 3710 | |
3e5d3a5a | 3711 | if (in_plt_section (pc) || in_mips_stubs_section (pc)) |
b8a22b94 | 3712 | return 1; |
979b38e0 | 3713 | |
db5f024e DJ |
3714 | /* Calling a PIC function from a non-PIC function passes through a |
3715 | stub. The stub for foo is named ".pic.foo". */ | |
3716 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 3717 | if (msym.minsym != NULL |
efd66ac6 TT |
3718 | && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL |
3719 | && strncmp (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.", 5) == 0) | |
db5f024e DJ |
3720 | return 1; |
3721 | ||
b8a22b94 | 3722 | return 0; |
29639122 | 3723 | } |
c906108c | 3724 | |
b8a22b94 DJ |
3725 | static const struct frame_unwind mips_stub_frame_unwind = |
3726 | { | |
3727 | NORMAL_FRAME, | |
8fbca658 | 3728 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3729 | mips_stub_frame_this_id, |
3730 | mips_stub_frame_prev_register, | |
3731 | NULL, | |
3732 | mips_stub_frame_sniffer | |
3733 | }; | |
3734 | ||
29639122 | 3735 | static CORE_ADDR |
b8a22b94 | 3736 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
3737 | void **this_cache) |
3738 | { | |
3739 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3740 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3741 | return trad_frame_get_this_base (this_trad_cache); |
3742 | } | |
0fce0821 | 3743 | |
29639122 JB |
3744 | static const struct frame_base mips_stub_frame_base = |
3745 | { | |
3746 | &mips_stub_frame_unwind, | |
3747 | mips_stub_frame_base_address, | |
3748 | mips_stub_frame_base_address, | |
3749 | mips_stub_frame_base_address | |
3750 | }; | |
3751 | ||
3752 | static const struct frame_base * | |
b8a22b94 | 3753 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3754 | { |
b8a22b94 | 3755 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3756 | return &mips_stub_frame_base; |
3757 | else | |
3758 | return NULL; | |
3759 | } | |
3760 | ||
29639122 | 3761 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3762 | |
29639122 | 3763 | static CORE_ADDR |
24568a2c | 3764 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3765 | { |
24568a2c | 3766 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 | 3767 | |
4cc0665f MR |
3768 | if (is_compact_addr (addr)) |
3769 | addr = unmake_compact_addr (addr); | |
930bd0e0 | 3770 | |
29639122 JB |
3771 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3772 | /* This hack is a work-around for existing boards using PMON, the | |
3773 | simulator, and any other 64-bit targets that doesn't have true | |
3774 | 64-bit addressing. On these targets, the upper 32 bits of | |
3775 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3776 | likely to have been sign extended to all 1s by instruction | |
3777 | sequences that load 32-bit addresses. For example, a typical | |
3778 | piece of code that loads an address is this: | |
65596487 | 3779 | |
29639122 JB |
3780 | lui $r2, <upper 16 bits> |
3781 | ori $r2, <lower 16 bits> | |
65596487 | 3782 | |
29639122 JB |
3783 | But the lui sign-extends the value such that the upper 32 bits |
3784 | may be all 1s. The workaround is simply to mask off these | |
3785 | bits. In the future, gcc may be changed to support true 64-bit | |
3786 | addressing, and this masking will have to be disabled. */ | |
3787 | return addr &= 0xffffffffUL; | |
3788 | else | |
3789 | return addr; | |
65596487 JB |
3790 | } |
3791 | ||
3d5f6d12 DJ |
3792 | |
3793 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3794 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3795 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3796 | the sequence. */ | |
3797 | ||
4cc0665f MR |
3798 | /* Instructions used during single-stepping of atomic sequences, standard |
3799 | ISA version. */ | |
3800 | #define LL_OPCODE 0x30 | |
3801 | #define LLD_OPCODE 0x34 | |
3802 | #define SC_OPCODE 0x38 | |
3803 | #define SCD_OPCODE 0x3c | |
3804 | ||
3d5f6d12 | 3805 | static int |
4cc0665f MR |
3806 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
3807 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
3808 | { |
3809 | CORE_ADDR breaks[2] = {-1, -1}; | |
3810 | CORE_ADDR loc = pc; | |
3811 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3812 | ULONGEST insn; |
3d5f6d12 DJ |
3813 | int insn_count; |
3814 | int index; | |
3815 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3816 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3817 | ||
4cc0665f | 3818 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3819 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3820 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
3821 | return 0; | |
3822 | ||
3823 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3824 | instructions. */ | |
3825 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3826 | { | |
3827 | int is_branch = 0; | |
3828 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3829 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3830 | |
3831 | /* Assume that there is at most one branch in the atomic | |
3832 | sequence. If a branch is found, put a breakpoint in its | |
3833 | destination address. */ | |
3834 | switch (itype_op (insn)) | |
3835 | { | |
3836 | case 0: /* SPECIAL */ | |
3837 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 3838 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3839 | break; |
3840 | case 1: /* REGIMM */ | |
a385295e MR |
3841 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3842 | || ((itype_rt (insn) & 0x1e) == 0 | |
3843 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3844 | break; |
3845 | case 2: /* J */ | |
3846 | case 3: /* JAL */ | |
025bb325 | 3847 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3848 | case 4: /* BEQ */ |
3849 | case 5: /* BNE */ | |
3850 | case 6: /* BLEZ */ | |
3851 | case 7: /* BGTZ */ | |
3852 | case 20: /* BEQL */ | |
3853 | case 21: /* BNEL */ | |
3854 | case 22: /* BLEZL */ | |
3855 | case 23: /* BGTTL */ | |
3856 | is_branch = 1; | |
3857 | break; | |
3858 | case 17: /* COP1 */ | |
a385295e MR |
3859 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3860 | && (itype_rt (insn) & 0x2) == 0); | |
3861 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3862 | break; | |
3863 | /* Fall through. */ | |
3d5f6d12 DJ |
3864 | case 18: /* COP2 */ |
3865 | case 19: /* COP3 */ | |
3866 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3867 | break; | |
3868 | } | |
3869 | if (is_branch) | |
3870 | { | |
3871 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
3872 | if (last_breakpoint >= 1) | |
3873 | return 0; /* More than one branch found, fallback to the | |
3874 | standard single-step code. */ | |
3875 | breaks[1] = branch_bp; | |
3876 | last_breakpoint++; | |
3877 | } | |
3878 | ||
3879 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
3880 | break; | |
3881 | } | |
3882 | ||
3883 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
3884 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
3885 | return 0; | |
3886 | ||
3887 | loc += MIPS_INSN32_SIZE; | |
3888 | ||
3889 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3890 | breaks[0] = loc; | |
3891 | ||
3892 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 3893 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
3894 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
3895 | last_breakpoint = 0; | |
3896 | ||
3897 | /* Effectively inserts the breakpoints. */ | |
3898 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 3899 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
3900 | |
3901 | return 1; | |
3902 | } | |
3903 | ||
4cc0665f MR |
3904 | static int |
3905 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
3906 | struct address_space *aspace, | |
3907 | CORE_ADDR pc) | |
3908 | { | |
3909 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3910 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3911 | CORE_ADDR breaks[2] = {-1, -1}; | |
4b844a38 AT |
3912 | CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's |
3913 | destination. */ | |
4cc0665f MR |
3914 | CORE_ADDR loc = pc; |
3915 | int sc_found = 0; | |
3916 | ULONGEST insn; | |
3917 | int insn_count; | |
3918 | int index; | |
3919 | ||
3920 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
3921 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3922 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
3923 | return 0; | |
3924 | loc += MIPS_INSN16_SIZE; | |
3925 | insn <<= 16; | |
3926 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3927 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
3928 | return 0; | |
3929 | loc += MIPS_INSN16_SIZE; | |
3930 | ||
3931 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
3932 | that no atomic sequence is longer than "atomic_sequence_length" | |
3933 | instructions. */ | |
3934 | for (insn_count = 0; | |
3935 | !sc_found && insn_count < atomic_sequence_length; | |
3936 | ++insn_count) | |
3937 | { | |
3938 | int is_branch = 0; | |
3939 | ||
3940 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3941 | loc += MIPS_INSN16_SIZE; | |
3942 | ||
3943 | /* Assume that there is at most one conditional branch in the | |
3944 | atomic sequence. If a branch is found, put a breakpoint in | |
3945 | its destination address. */ | |
3946 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
3947 | { | |
3948 | /* 48-bit instructions. */ | |
3949 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
3950 | loc += 2 * MIPS_INSN16_SIZE; | |
3951 | break; | |
3952 | ||
3953 | /* 32-bit instructions. */ | |
3954 | case 2 * MIPS_INSN16_SIZE: | |
3955 | switch (micromips_op (insn)) | |
3956 | { | |
3957 | case 0x10: /* POOL32I: bits 010000 */ | |
3958 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
3959 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
3960 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
3961 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
3962 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
3963 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
3964 | || (insn & 0x3) != 0x0) | |
3965 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
3966 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
3967 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
3968 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
3969 | || (insn & 0x3) != 0x0) | |
3970 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
3971 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
3972 | || (insn & 0x3) != 0x1)) | |
3973 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
3974 | break; | |
3975 | /* Fall through. */ | |
3976 | ||
3977 | case 0x25: /* BEQ: bits 100101 */ | |
3978 | case 0x2d: /* BNE: bits 101101 */ | |
3979 | insn <<= 16; | |
3980 | insn |= mips_fetch_instruction (gdbarch, | |
3981 | ISA_MICROMIPS, loc, NULL); | |
3982 | branch_bp = (loc + MIPS_INSN16_SIZE | |
3983 | + micromips_relative_offset16 (insn)); | |
3984 | is_branch = 1; | |
3985 | break; | |
3986 | ||
3987 | case 0x00: /* POOL32A: bits 000000 */ | |
3988 | insn <<= 16; | |
3989 | insn |= mips_fetch_instruction (gdbarch, | |
3990 | ISA_MICROMIPS, loc, NULL); | |
3991 | if (b0s6_op (insn) != 0x3c | |
3992 | /* POOL32Axf: bits 000000 ... 111100 */ | |
3993 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
3994 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
3995 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
3996 | break; | |
3997 | /* Fall through. */ | |
3998 | ||
3999 | case 0x1d: /* JALS: bits 011101 */ | |
4000 | case 0x35: /* J: bits 110101 */ | |
4001 | case 0x3d: /* JAL: bits 111101 */ | |
4002 | case 0x3c: /* JALX: bits 111100 */ | |
4003 | return 0; /* Fall back to the standard single-step code. */ | |
4004 | ||
4005 | case 0x18: /* POOL32C: bits 011000 */ | |
4006 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
4007 | /* SC, SCD: bits 011000 1x11 */ | |
4008 | sc_found = 1; | |
4009 | break; | |
4010 | } | |
4011 | loc += MIPS_INSN16_SIZE; | |
4012 | break; | |
4013 | ||
4014 | /* 16-bit instructions. */ | |
4015 | case MIPS_INSN16_SIZE: | |
4016 | switch (micromips_op (insn)) | |
4017 | { | |
4018 | case 0x23: /* BEQZ16: bits 100011 */ | |
4019 | case 0x2b: /* BNEZ16: bits 101011 */ | |
4020 | branch_bp = loc + micromips_relative_offset7 (insn); | |
4021 | is_branch = 1; | |
4022 | break; | |
4023 | ||
4024 | case 0x11: /* POOL16C: bits 010001 */ | |
4025 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
4026 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
4027 | && b5s5_op (insn) != 0x18) | |
4028 | /* JRADDIUSP: bits 010001 11000 */ | |
4029 | break; | |
4030 | return 0; /* Fall back to the standard single-step code. */ | |
4031 | ||
4032 | case 0x33: /* B16: bits 110011 */ | |
4033 | return 0; /* Fall back to the standard single-step code. */ | |
4034 | } | |
4035 | break; | |
4036 | } | |
4037 | if (is_branch) | |
4038 | { | |
4039 | if (last_breakpoint >= 1) | |
4040 | return 0; /* More than one branch found, fallback to the | |
4041 | standard single-step code. */ | |
4042 | breaks[1] = branch_bp; | |
4043 | last_breakpoint++; | |
4044 | } | |
4045 | } | |
4046 | if (!sc_found) | |
4047 | return 0; | |
4048 | ||
4049 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
4050 | breaks[0] = loc; | |
4051 | ||
4052 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
4053 | placed (branch instruction's destination) in the atomic sequence */ | |
4054 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
4055 | last_breakpoint = 0; | |
4056 | ||
4057 | /* Effectively inserts the breakpoints. */ | |
4058 | for (index = 0; index <= last_breakpoint; index++) | |
3373342d | 4059 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
4cc0665f MR |
4060 | |
4061 | return 1; | |
4062 | } | |
4063 | ||
4064 | static int | |
4065 | deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
4066 | struct address_space *aspace, CORE_ADDR pc) | |
4067 | { | |
4068 | if (mips_pc_is_mips (pc)) | |
4069 | return mips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
4070 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
4071 | return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
4072 | else | |
4073 | return 0; | |
4074 | } | |
4075 | ||
29639122 JB |
4076 | /* mips_software_single_step() is called just before we want to resume |
4077 | the inferior, if we want to single-step it but there is no hardware | |
4078 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 4079 | the target of the coming instruction and breakpoint it. */ |
29639122 | 4080 | |
e6590a1b | 4081 | int |
0b1b3e42 | 4082 | mips_software_single_step (struct frame_info *frame) |
c906108c | 4083 | { |
a6d9a66e | 4084 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 4085 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 4086 | CORE_ADDR pc, next_pc; |
65596487 | 4087 | |
0b1b3e42 | 4088 | pc = get_frame_pc (frame); |
6c95b8df | 4089 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
4090 | return 1; |
4091 | ||
0b1b3e42 | 4092 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 4093 | |
6c95b8df | 4094 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 4095 | return 1; |
29639122 | 4096 | } |
a65bbe44 | 4097 | |
29639122 | 4098 | /* Test whether the PC points to the return instruction at the |
025bb325 | 4099 | end of a function. */ |
65596487 | 4100 | |
29639122 | 4101 | static int |
e17a4113 | 4102 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 4103 | { |
6321c22a MR |
4104 | ULONGEST insn; |
4105 | ULONGEST hint; | |
4106 | ||
4107 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
4108 | called for MIPS16 functions. And likewise microMIPS ones. */ |
4109 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 4110 | |
4cc0665f | 4111 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
4112 | hint = 0x7c0; |
4113 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 4114 | } |
c906108c | 4115 | |
c906108c | 4116 | |
29639122 JB |
4117 | /* This fencepost looks highly suspicious to me. Removing it also |
4118 | seems suspicious as it could affect remote debugging across serial | |
4119 | lines. */ | |
c906108c | 4120 | |
29639122 | 4121 | static CORE_ADDR |
74ed0bb4 | 4122 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
4123 | { |
4124 | CORE_ADDR start_pc; | |
4125 | CORE_ADDR fence; | |
4126 | int instlen; | |
4127 | int seen_adjsp = 0; | |
d6b48e9c | 4128 | struct inferior *inf; |
65596487 | 4129 | |
74ed0bb4 | 4130 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
4131 | start_pc = pc; |
4132 | fence = start_pc - heuristic_fence_post; | |
4133 | if (start_pc == 0) | |
4134 | return 0; | |
65596487 | 4135 | |
44096aee | 4136 | if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) |
29639122 | 4137 | fence = VM_MIN_ADDRESS; |
65596487 | 4138 | |
4cc0665f | 4139 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 4140 | |
d6b48e9c PA |
4141 | inf = current_inferior (); |
4142 | ||
025bb325 | 4143 | /* Search back for previous return. */ |
29639122 JB |
4144 | for (start_pc -= instlen;; start_pc -= instlen) |
4145 | if (start_pc < fence) | |
4146 | { | |
4147 | /* It's not clear to me why we reach this point when | |
4148 | stop_soon, but with this test, at least we | |
4149 | don't print out warnings for every child forked (eg, on | |
4150 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 4151 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
4152 | { |
4153 | static int blurb_printed = 0; | |
98b4dd94 | 4154 | |
5af949e3 UW |
4155 | warning (_("GDB can't find the start of the function at %s."), |
4156 | paddress (gdbarch, pc)); | |
29639122 JB |
4157 | |
4158 | if (!blurb_printed) | |
4159 | { | |
4160 | /* This actually happens frequently in embedded | |
4161 | development, when you first connect to a board | |
4162 | and your stack pointer and pc are nowhere in | |
4163 | particular. This message needs to give people | |
4164 | in that situation enough information to | |
4165 | determine that it's no big deal. */ | |
4166 | printf_filtered ("\n\ | |
5af949e3 | 4167 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4168 | and thus can't determine the size of that function's stack frame.\n\ |
4169 | This means that GDB may be unable to access that stack frame, or\n\ | |
4170 | the frames below it.\n\ | |
4171 | This problem is most likely caused by an invalid program counter or\n\ | |
4172 | stack pointer.\n\ | |
4173 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4174 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4175 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
4176 | heuristic-fence-post' command.\n", |
4177 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
4178 | blurb_printed = 1; |
4179 | } | |
4180 | } | |
4181 | ||
4182 | return 0; | |
4183 | } | |
4cc0665f | 4184 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4185 | { |
4186 | unsigned short inst; | |
4187 | ||
4188 | /* On MIPS16, any one of the following is likely to be the | |
4189 | start of a function: | |
193774b3 MR |
4190 | extend save |
4191 | save | |
29639122 JB |
4192 | entry |
4193 | addiu sp,-n | |
4194 | daddiu sp,-n | |
025bb325 | 4195 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4196 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4197 | if ((inst & 0xff80) == 0x6480) /* save */ |
4198 | { | |
4199 | if (start_pc - instlen >= fence) | |
4200 | { | |
4cc0665f MR |
4201 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4202 | start_pc - instlen, NULL); | |
193774b3 MR |
4203 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4204 | start_pc -= instlen; | |
4205 | } | |
4206 | break; | |
4207 | } | |
4208 | else if (((inst & 0xf81f) == 0xe809 | |
4209 | && (inst & 0x700) != 0x700) /* entry */ | |
4210 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4211 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4212 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4213 | break; |
4214 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4215 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4216 | seen_adjsp = 1; | |
4217 | else | |
4218 | seen_adjsp = 0; | |
4219 | } | |
4cc0665f MR |
4220 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4221 | { | |
4222 | ULONGEST insn; | |
4223 | int stop = 0; | |
4224 | long offset; | |
4225 | int dreg; | |
4226 | int sreg; | |
4227 | ||
4228 | /* On microMIPS, any one of the following is likely to be the | |
4229 | start of a function: | |
4230 | ADDIUSP -imm | |
4231 | (D)ADDIU $sp, -imm | |
4232 | LUI $gp, imm */ | |
4233 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4234 | switch (micromips_op (insn)) | |
4235 | { | |
4236 | case 0xc: /* ADDIU: bits 001100 */ | |
4237 | case 0x17: /* DADDIU: bits 010111 */ | |
4238 | sreg = b0s5_reg (insn); | |
4239 | dreg = b5s5_reg (insn); | |
4240 | insn <<= 16; | |
4241 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4242 | pc + MIPS_INSN16_SIZE, NULL); | |
4243 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4244 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4245 | /* (D)ADDIU $sp, imm */ | |
4246 | && offset < 0) | |
4247 | stop = 1; | |
4248 | break; | |
4249 | ||
4250 | case 0x10: /* POOL32I: bits 010000 */ | |
4251 | if (b5s5_op (insn) == 0xd | |
4252 | /* LUI: bits 010000 001101 */ | |
4253 | && b0s5_reg (insn >> 16) == 28) | |
4254 | /* LUI $gp, imm */ | |
4255 | stop = 1; | |
4256 | break; | |
4257 | ||
4258 | case 0x13: /* POOL16D: bits 010011 */ | |
4259 | if ((insn & 0x1) == 0x1) | |
4260 | /* ADDIUSP: bits 010011 1 */ | |
4261 | { | |
4262 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4263 | if (offset < 0) | |
4264 | /* ADDIUSP -imm */ | |
4265 | stop = 1; | |
4266 | } | |
4267 | else | |
4268 | /* ADDIUS5: bits 010011 0 */ | |
4269 | { | |
4270 | dreg = b5s5_reg (insn); | |
4271 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4272 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4273 | /* ADDIUS5 $sp, -imm */ | |
4274 | stop = 1; | |
4275 | } | |
4276 | break; | |
4277 | } | |
4278 | if (stop) | |
4279 | break; | |
4280 | } | |
e17a4113 | 4281 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4282 | { |
4c7d22cb | 4283 | /* Skip return and its delay slot. */ |
95ac2dcf | 4284 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4285 | break; |
4286 | } | |
4287 | ||
4288 | return start_pc; | |
c906108c SS |
4289 | } |
4290 | ||
6c0d6680 DJ |
4291 | struct mips_objfile_private |
4292 | { | |
4293 | bfd_size_type size; | |
4294 | char *contents; | |
4295 | }; | |
4296 | ||
f09ded24 AC |
4297 | /* According to the current ABI, should the type be passed in a |
4298 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4299 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4300 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4301 | arguments into integer registers. */ |
f09ded24 AC |
4302 | |
4303 | static int | |
74ed0bb4 MD |
4304 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4305 | struct type *arg_type) | |
f09ded24 AC |
4306 | { |
4307 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 4308 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
4309 | && (typecode == TYPE_CODE_STRUCT |
4310 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 4311 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
4312 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
4313 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 4314 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4315 | } |
4316 | ||
49e790b0 | 4317 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4318 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4319 | |
4320 | static int | |
4321 | mips_type_needs_double_align (struct type *type) | |
4322 | { | |
4323 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 4324 | |
49e790b0 DJ |
4325 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
4326 | return 1; | |
4327 | else if (typecode == TYPE_CODE_STRUCT) | |
4328 | { | |
4329 | if (TYPE_NFIELDS (type) < 1) | |
4330 | return 0; | |
4331 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
4332 | } | |
4333 | else if (typecode == TYPE_CODE_UNION) | |
4334 | { | |
361d1df0 | 4335 | int i, n; |
49e790b0 DJ |
4336 | |
4337 | n = TYPE_NFIELDS (type); | |
4338 | for (i = 0; i < n; i++) | |
4339 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
4340 | return 1; | |
4341 | return 0; | |
4342 | } | |
4343 | return 0; | |
4344 | } | |
4345 | ||
dc604539 AC |
4346 | /* Adjust the address downward (direction of stack growth) so that it |
4347 | is correctly aligned for a new stack frame. */ | |
4348 | static CORE_ADDR | |
4349 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4350 | { | |
5b03f266 | 4351 | return align_down (addr, 16); |
dc604539 AC |
4352 | } |
4353 | ||
8ae38c14 | 4354 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4355 | |
4356 | static CORE_ADDR | |
4357 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4358 | CORE_ADDR funaddr, struct value **args, | |
4359 | int nargs, struct type *value_type, | |
4360 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4361 | struct regcache *regcache) | |
4362 | { | |
2c76a0c7 | 4363 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
2e81047f MR |
4364 | CORE_ADDR nop_addr; |
4365 | CORE_ADDR bp_slot; | |
2c76a0c7 JB |
4366 | |
4367 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
2e81047f MR |
4368 | bp_slot = sp - sizeof (nop_insn); |
4369 | ||
4370 | /* Return to microMIPS mode if calling microMIPS code to avoid | |
4371 | triggering an address error exception on processors that only | |
4372 | support microMIPS execution. */ | |
4373 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) | |
4374 | ? make_compact_addr (bp_slot) : bp_slot); | |
2c76a0c7 JB |
4375 | |
4376 | /* The breakpoint layer automatically adjusts the address of | |
4377 | breakpoints inserted in a branch delay slot. With enough | |
4378 | bad luck, the 4 bytes located just before our breakpoint | |
4379 | instruction could look like a branch instruction, and thus | |
4380 | trigger the adjustement, and break the function call entirely. | |
4381 | So, we reserve those 4 bytes and write a nop instruction | |
4382 | to prevent that from happening. */ | |
2e81047f | 4383 | nop_addr = bp_slot - sizeof (nop_insn); |
2c76a0c7 JB |
4384 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
4385 | sp = mips_frame_align (gdbarch, nop_addr); | |
4386 | ||
4387 | /* Inferior resumes at the function entry point. */ | |
4388 | *real_pc = funaddr; | |
4389 | ||
4390 | return sp; | |
4391 | } | |
4392 | ||
f7ab6ec6 | 4393 | static CORE_ADDR |
7d9b040b | 4394 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4395 | struct regcache *regcache, CORE_ADDR bp_addr, |
4396 | int nargs, struct value **args, CORE_ADDR sp, | |
4397 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
4398 | { |
4399 | int argreg; | |
4400 | int float_argreg; | |
4401 | int argnum; | |
4402 | int len = 0; | |
4403 | int stack_offset = 0; | |
e17a4113 | 4404 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4405 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 4406 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 4407 | |
25ab4790 AC |
4408 | /* For shared libraries, "t9" needs to point at the function |
4409 | address. */ | |
4c7d22cb | 4410 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4411 | |
4412 | /* Set the return address register to point to the entry point of | |
4413 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4414 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4415 | |
c906108c | 4416 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4417 | are properly aligned. The stack has to be at least 64-bit |
4418 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4419 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4420 | aligned, so we round to this widest known alignment. */ | |
4421 | ||
5b03f266 AC |
4422 | sp = align_down (sp, 16); |
4423 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4424 | |
46e0f506 | 4425 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4426 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4427 | passed in registers, but that's OK. */ |
c906108c | 4428 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 4429 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 4430 | sp -= align_up (len, 16); |
c906108c | 4431 | |
9ace0497 | 4432 | if (mips_debug) |
6d82d43b | 4433 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4434 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
4435 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 4436 | |
c906108c | 4437 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4438 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4439 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4440 | |
46e0f506 | 4441 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 4442 | if (struct_return) |
9ace0497 AC |
4443 | { |
4444 | if (mips_debug) | |
4445 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4446 | "mips_eabi_push_dummy_call: " |
4447 | "struct_return reg=%d %s\n", | |
5af949e3 | 4448 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4449 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4450 | } |
c906108c SS |
4451 | |
4452 | /* Now load as many as possible of the first arguments into | |
4453 | registers, and push the rest onto the stack. Loop thru args | |
4454 | from first to last. */ | |
4455 | for (argnum = 0; argnum < nargs; argnum++) | |
4456 | { | |
47a35522 MK |
4457 | const gdb_byte *val; |
4458 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 4459 | struct value *arg = args[argnum]; |
4991999e | 4460 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
4461 | int len = TYPE_LENGTH (arg_type); |
4462 | enum type_code typecode = TYPE_CODE (arg_type); | |
4463 | ||
9ace0497 AC |
4464 | if (mips_debug) |
4465 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4466 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 4467 | argnum + 1, len, (int) typecode); |
9ace0497 | 4468 | |
930bd0e0 KB |
4469 | /* Function pointer arguments to mips16 code need to be made into |
4470 | mips16 pointers. */ | |
4471 | if (typecode == TYPE_CODE_PTR | |
4472 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4473 | { | |
4474 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4475 | len, byte_order); | |
4cc0665f MR |
4476 | if (mips_pc_is_mips (addr)) |
4477 | val = value_contents (arg); | |
4478 | else | |
930bd0e0 KB |
4479 | { |
4480 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 4481 | make_compact_addr (addr)); |
930bd0e0 KB |
4482 | val = valbuf; |
4483 | } | |
930bd0e0 | 4484 | } |
c906108c | 4485 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 4486 | reference. */ |
930bd0e0 | 4487 | else if (len > regsize |
9ace0497 | 4488 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4489 | { |
e17a4113 UW |
4490 | store_unsigned_integer (valbuf, regsize, byte_order, |
4491 | value_address (arg)); | |
c906108c | 4492 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 4493 | len = regsize; |
c906108c | 4494 | val = valbuf; |
9ace0497 AC |
4495 | if (mips_debug) |
4496 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
4497 | } |
4498 | else | |
47a35522 | 4499 | val = value_contents (arg); |
c906108c SS |
4500 | |
4501 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
4502 | even-numbered floating point register. Round the FP register |
4503 | up before the check to see if there are any FP registers | |
46e0f506 MS |
4504 | left. Non MIPS_EABI targets also pass the FP in the integer |
4505 | registers so also round up normal registers. */ | |
74ed0bb4 | 4506 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4507 | { |
4508 | if ((float_argreg & 1)) | |
4509 | float_argreg++; | |
4510 | } | |
c906108c SS |
4511 | |
4512 | /* Floating point arguments passed in registers have to be | |
4513 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
4514 | are passed in register pairs; the even register gets |
4515 | the low word, and the odd register gets the high word. | |
4516 | On non-EABI processors, the first two floating point arguments are | |
4517 | also copied to general registers, because MIPS16 functions | |
4518 | don't use float registers for arguments. This duplication of | |
4519 | arguments in general registers can't hurt non-MIPS16 functions | |
4520 | because those registers are normally skipped. */ | |
1012bd0e EZ |
4521 | /* MIPS_EABI squeezes a struct that contains a single floating |
4522 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 4523 | stack. */ |
74ed0bb4 MD |
4524 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4525 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 4526 | { |
6da397e0 KB |
4527 | /* EABI32 will pass doubles in consecutive registers, even on |
4528 | 64-bit cores. At one time, we used to check the size of | |
4529 | `float_argreg' to determine whether or not to pass doubles | |
4530 | in consecutive registers, but this is not sufficient for | |
4531 | making the ABI determination. */ | |
4532 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4533 | { |
72a155b4 | 4534 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4535 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4536 | long regval; |
c906108c SS |
4537 | |
4538 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4539 | regval = extract_signed_integer (val + low_offset, |
4540 | 4, byte_order); | |
9ace0497 | 4541 | if (mips_debug) |
acdb74a0 | 4542 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4543 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4544 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4545 | |
4546 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4547 | regval = extract_signed_integer (val + 4 - low_offset, |
4548 | 4, byte_order); | |
9ace0497 | 4549 | if (mips_debug) |
acdb74a0 | 4550 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4551 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4552 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4553 | } |
4554 | else | |
4555 | { | |
4556 | /* This is a floating point value that fits entirely | |
4557 | in a single register. */ | |
53a5351d | 4558 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 4559 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4560 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4561 | if (mips_debug) |
acdb74a0 | 4562 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4563 | float_argreg, phex (regval, len)); |
a8852dc5 | 4564 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4565 | } |
4566 | } | |
4567 | else | |
4568 | { | |
4569 | /* Copy the argument to general registers or the stack in | |
4570 | register-sized pieces. Large arguments are split between | |
4571 | registers and stack. */ | |
1a69e1e4 DJ |
4572 | /* Note: structs whose size is not a multiple of regsize |
4573 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
4574 | them in registers where gcc sometimes puts them on the |
4575 | stack. For maximum compatibility, we will put them in | |
4576 | both places. */ | |
1a69e1e4 | 4577 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 4578 | |
f09ded24 | 4579 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4580 | register are only written to memory. */ |
c906108c SS |
4581 | while (len > 0) |
4582 | { | |
ebafbe83 | 4583 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4584 | int stack_used_p = 0; |
1a69e1e4 | 4585 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 4586 | |
acdb74a0 AC |
4587 | if (mips_debug) |
4588 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4589 | partial_len); | |
4590 | ||
566f0f7a | 4591 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4592 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 4593 | || odd_sized_struct |
74ed0bb4 | 4594 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4595 | { |
c906108c | 4596 | /* Should shorter than int integer values be |
025bb325 | 4597 | promoted to int before being stored? */ |
c906108c | 4598 | int longword_offset = 0; |
9ace0497 | 4599 | CORE_ADDR addr; |
566f0f7a | 4600 | stack_used_p = 1; |
72a155b4 | 4601 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4602 | { |
1a69e1e4 | 4603 | if (regsize == 8 |
480d3dd2 AC |
4604 | && (typecode == TYPE_CODE_INT |
4605 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4606 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 4607 | longword_offset = regsize - len; |
480d3dd2 AC |
4608 | else if ((typecode == TYPE_CODE_STRUCT |
4609 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
4610 | && TYPE_LENGTH (arg_type) < regsize) |
4611 | longword_offset = regsize - len; | |
7a292a7a | 4612 | } |
c5aa993b | 4613 | |
9ace0497 AC |
4614 | if (mips_debug) |
4615 | { | |
5af949e3 UW |
4616 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4617 | paddress (gdbarch, stack_offset)); | |
4618 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4619 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4620 | } |
361d1df0 | 4621 | |
9ace0497 AC |
4622 | addr = sp + stack_offset + longword_offset; |
4623 | ||
4624 | if (mips_debug) | |
4625 | { | |
4626 | int i; | |
5af949e3 UW |
4627 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4628 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4629 | for (i = 0; i < partial_len; i++) |
4630 | { | |
6d82d43b | 4631 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 4632 | val[i] & 0xff); |
9ace0497 AC |
4633 | } |
4634 | } | |
4635 | write_memory (addr, val, partial_len); | |
c906108c SS |
4636 | } |
4637 | ||
f09ded24 AC |
4638 | /* Note!!! This is NOT an else clause. Odd sized |
4639 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 4640 | arguments will not. */ |
566f0f7a | 4641 | /* Write this portion of the argument to a general |
6d82d43b | 4642 | purpose register. */ |
74ed0bb4 MD |
4643 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
4644 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 4645 | { |
6d82d43b | 4646 | LONGEST regval = |
a8852dc5 | 4647 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4648 | |
9ace0497 | 4649 | if (mips_debug) |
acdb74a0 | 4650 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 4651 | argreg, |
1a69e1e4 | 4652 | phex (regval, regsize)); |
a8852dc5 | 4653 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4654 | argreg++; |
c906108c | 4655 | } |
c5aa993b | 4656 | |
c906108c SS |
4657 | len -= partial_len; |
4658 | val += partial_len; | |
4659 | ||
b021a221 MS |
4660 | /* Compute the offset into the stack at which we will |
4661 | copy the next parameter. | |
566f0f7a | 4662 | |
566f0f7a | 4663 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 4664 | only needs to be adjusted when it has been used. */ |
c906108c | 4665 | |
46e0f506 | 4666 | if (stack_used_p) |
1a69e1e4 | 4667 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
4668 | } |
4669 | } | |
9ace0497 AC |
4670 | if (mips_debug) |
4671 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
4672 | } |
4673 | ||
f10683bb | 4674 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4675 | |
0f71a2f6 JM |
4676 | /* Return adjusted stack pointer. */ |
4677 | return sp; | |
4678 | } | |
4679 | ||
a1f5b845 | 4680 | /* Determine the return value convention being used. */ |
6d82d43b | 4681 | |
9c8fdbfa | 4682 | static enum return_value_convention |
6a3a010b | 4683 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4684 | struct type *type, struct regcache *regcache, |
47a35522 | 4685 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4686 | { |
609ba780 JM |
4687 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4688 | int fp_return_type = 0; | |
4689 | int offset, regnum, xfer; | |
4690 | ||
9c8fdbfa AC |
4691 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
4692 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
4693 | |
4694 | /* Floating point type? */ | |
4695 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4696 | { | |
4697 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
4698 | fp_return_type = 1; | |
4699 | /* Structs with a single field of float type | |
4700 | are returned in a floating point register. */ | |
4701 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4702 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4703 | && TYPE_NFIELDS (type) == 1) | |
4704 | { | |
4705 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
4706 | ||
4707 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
4708 | fp_return_type = 1; | |
4709 | } | |
4710 | } | |
4711 | ||
4712 | if (fp_return_type) | |
4713 | { | |
4714 | /* A floating-point value belongs in the least significant part | |
4715 | of FP0/FP1. */ | |
4716 | if (mips_debug) | |
4717 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4718 | regnum = mips_regnum (gdbarch)->fp0; | |
4719 | } | |
4720 | else | |
4721 | { | |
4722 | /* An integer value goes in V0/V1. */ | |
4723 | if (mips_debug) | |
4724 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
4725 | regnum = MIPS_V0_REGNUM; | |
4726 | } | |
4727 | for (offset = 0; | |
4728 | offset < TYPE_LENGTH (type); | |
4729 | offset += mips_abi_regsize (gdbarch), regnum++) | |
4730 | { | |
4731 | xfer = mips_abi_regsize (gdbarch); | |
4732 | if (offset + xfer > TYPE_LENGTH (type)) | |
4733 | xfer = TYPE_LENGTH (type) - offset; | |
4734 | mips_xfer_register (gdbarch, regcache, | |
4735 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4736 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4737 | offset); | |
4738 | } | |
4739 | ||
9c8fdbfa | 4740 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4741 | } |
4742 | ||
6d82d43b AC |
4743 | |
4744 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4745 | |
8d26208a DJ |
4746 | /* Search for a naturally aligned double at OFFSET inside a struct |
4747 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4748 | registers. */ | |
4749 | ||
4750 | static int | |
74ed0bb4 MD |
4751 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4752 | int offset) | |
8d26208a DJ |
4753 | { |
4754 | int i; | |
4755 | ||
4756 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
4757 | return 0; | |
4758 | ||
74ed0bb4 | 4759 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4760 | return 0; |
4761 | ||
4762 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
4763 | return 0; | |
4764 | ||
4765 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
4766 | { | |
4767 | int pos; | |
4768 | struct type *field_type; | |
4769 | ||
4770 | /* We're only looking at normal fields. */ | |
5bc60cfb | 4771 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
4772 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
4773 | continue; | |
4774 | ||
4775 | /* If we have gone past the offset, there is no double to pass. */ | |
4776 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
4777 | if (pos > offset) | |
4778 | return 0; | |
4779 | ||
4780 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
4781 | ||
4782 | /* If this field is entirely before the requested offset, go | |
4783 | on to the next one. */ | |
4784 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
4785 | continue; | |
4786 | ||
4787 | /* If this is our special aligned double, we can stop. */ | |
4788 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
4789 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
4790 | return 1; | |
4791 | ||
4792 | /* This field starts at or before the requested offset, and | |
4793 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4794 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4795 | } |
4796 | ||
4797 | return 0; | |
4798 | } | |
4799 | ||
f7ab6ec6 | 4800 | static CORE_ADDR |
7d9b040b | 4801 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4802 | struct regcache *regcache, CORE_ADDR bp_addr, |
4803 | int nargs, struct value **args, CORE_ADDR sp, | |
4804 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4805 | { |
4806 | int argreg; | |
4807 | int float_argreg; | |
4808 | int argnum; | |
4809 | int len = 0; | |
4810 | int stack_offset = 0; | |
e17a4113 | 4811 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4812 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4813 | |
25ab4790 AC |
4814 | /* For shared libraries, "t9" needs to point at the function |
4815 | address. */ | |
4c7d22cb | 4816 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4817 | |
4818 | /* Set the return address register to point to the entry point of | |
4819 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4820 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4821 | |
cb3d25d1 MS |
4822 | /* First ensure that the stack and structure return address (if any) |
4823 | are properly aligned. The stack has to be at least 64-bit | |
4824 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4825 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4826 | aligned, so we round to this widest known alignment. */ | |
4827 | ||
5b03f266 AC |
4828 | sp = align_down (sp, 16); |
4829 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4830 | |
4831 | /* Now make space on the stack for the args. */ | |
4832 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 4833 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 4834 | sp -= align_up (len, 16); |
cb3d25d1 MS |
4835 | |
4836 | if (mips_debug) | |
6d82d43b | 4837 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4838 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
4839 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
4840 | |
4841 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4842 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4843 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4844 | |
46e0f506 | 4845 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
4846 | if (struct_return) |
4847 | { | |
4848 | if (mips_debug) | |
4849 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4850 | "mips_n32n64_push_dummy_call: " |
4851 | "struct_return reg=%d %s\n", | |
5af949e3 | 4852 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4853 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4854 | } |
4855 | ||
4856 | /* Now load as many as possible of the first arguments into | |
4857 | registers, and push the rest onto the stack. Loop thru args | |
4858 | from first to last. */ | |
4859 | for (argnum = 0; argnum < nargs; argnum++) | |
4860 | { | |
47a35522 | 4861 | const gdb_byte *val; |
cb3d25d1 | 4862 | struct value *arg = args[argnum]; |
4991999e | 4863 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
4864 | int len = TYPE_LENGTH (arg_type); |
4865 | enum type_code typecode = TYPE_CODE (arg_type); | |
4866 | ||
4867 | if (mips_debug) | |
4868 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4869 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
4870 | argnum + 1, len, (int) typecode); |
4871 | ||
47a35522 | 4872 | val = value_contents (arg); |
cb3d25d1 | 4873 | |
5b68030f JM |
4874 | /* A 128-bit long double value requires an even-odd pair of |
4875 | floating-point registers. */ | |
4876 | if (len == 16 | |
4877 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4878 | && (float_argreg & 1)) | |
4879 | { | |
4880 | float_argreg++; | |
4881 | argreg++; | |
4882 | } | |
4883 | ||
74ed0bb4 MD |
4884 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4885 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
4886 | { |
4887 | /* This is a floating point value that fits entirely | |
5b68030f JM |
4888 | in a single register or a pair of registers. */ |
4889 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 4890 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
4891 | if (mips_debug) |
4892 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 4893 | float_argreg, phex (regval, reglen)); |
8d26208a | 4894 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
4895 | |
4896 | if (mips_debug) | |
4897 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 4898 | argreg, phex (regval, reglen)); |
9c9acae0 | 4899 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
4900 | float_argreg++; |
4901 | argreg++; | |
5b68030f JM |
4902 | if (len == 16) |
4903 | { | |
e17a4113 UW |
4904 | regval = extract_unsigned_integer (val + reglen, |
4905 | reglen, byte_order); | |
5b68030f JM |
4906 | if (mips_debug) |
4907 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4908 | float_argreg, phex (regval, reglen)); | |
4909 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
4910 | ||
4911 | if (mips_debug) | |
4912 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4913 | argreg, phex (regval, reglen)); | |
4914 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
4915 | float_argreg++; | |
4916 | argreg++; | |
4917 | } | |
cb3d25d1 MS |
4918 | } |
4919 | else | |
4920 | { | |
4921 | /* Copy the argument to general registers or the stack in | |
4922 | register-sized pieces. Large arguments are split between | |
4923 | registers and stack. */ | |
ab2e1992 MR |
4924 | /* For N32/N64, structs, unions, or other composite types are |
4925 | treated as a sequence of doublewords, and are passed in integer | |
4926 | or floating point registers as though they were simple scalar | |
4927 | parameters to the extent that they fit, with any excess on the | |
4928 | stack packed according to the normal memory layout of the | |
4929 | object. | |
4930 | The caller does not reserve space for the register arguments; | |
4931 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 4932 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4933 | register are only written to memory. */ |
cb3d25d1 MS |
4934 | while (len > 0) |
4935 | { | |
ad018eee | 4936 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 4937 | int stack_used_p = 0; |
1a69e1e4 | 4938 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
4939 | |
4940 | if (mips_debug) | |
4941 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4942 | partial_len); | |
4943 | ||
74ed0bb4 MD |
4944 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
4945 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 4946 | |
cb3d25d1 | 4947 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4948 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
4949 | { |
4950 | /* Should shorter than int integer values be | |
025bb325 | 4951 | promoted to int before being stored? */ |
cb3d25d1 MS |
4952 | int longword_offset = 0; |
4953 | CORE_ADDR addr; | |
4954 | stack_used_p = 1; | |
72a155b4 | 4955 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 4956 | { |
1a69e1e4 | 4957 | if ((typecode == TYPE_CODE_INT |
5b68030f | 4958 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
4959 | && len <= 4) |
4960 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
4961 | } |
4962 | ||
4963 | if (mips_debug) | |
4964 | { | |
5af949e3 UW |
4965 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4966 | paddress (gdbarch, stack_offset)); | |
4967 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4968 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
4969 | } |
4970 | ||
4971 | addr = sp + stack_offset + longword_offset; | |
4972 | ||
4973 | if (mips_debug) | |
4974 | { | |
4975 | int i; | |
5af949e3 UW |
4976 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4977 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
4978 | for (i = 0; i < partial_len; i++) |
4979 | { | |
6d82d43b | 4980 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
4981 | val[i] & 0xff); |
4982 | } | |
4983 | } | |
4984 | write_memory (addr, val, partial_len); | |
4985 | } | |
4986 | ||
4987 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 4988 | structs may go thru BOTH paths. */ |
cb3d25d1 | 4989 | /* Write this portion of the argument to a general |
6d82d43b | 4990 | purpose register. */ |
74ed0bb4 | 4991 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 4992 | { |
5863b5d5 MR |
4993 | LONGEST regval; |
4994 | ||
4995 | /* Sign extend pointers, 32-bit integers and signed | |
4996 | 16-bit and 8-bit integers; everything else is taken | |
4997 | as is. */ | |
4998 | ||
4999 | if ((partial_len == 4 | |
5000 | && (typecode == TYPE_CODE_PTR | |
5001 | || typecode == TYPE_CODE_INT)) | |
5002 | || (partial_len < 4 | |
5003 | && typecode == TYPE_CODE_INT | |
5004 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
5005 | regval = extract_signed_integer (val, partial_len, |
5006 | byte_order); | |
5863b5d5 | 5007 | else |
e17a4113 UW |
5008 | regval = extract_unsigned_integer (val, partial_len, |
5009 | byte_order); | |
cb3d25d1 MS |
5010 | |
5011 | /* A non-floating-point argument being passed in a | |
5012 | general register. If a struct or union, and if | |
5013 | the remaining length is smaller than the register | |
5014 | size, we have to adjust the register value on | |
5015 | big endian targets. | |
5016 | ||
5017 | It does not seem to be necessary to do the | |
1a69e1e4 | 5018 | same for integral types. */ |
cb3d25d1 | 5019 | |
72a155b4 | 5020 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5021 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5022 | && (typecode == TYPE_CODE_STRUCT |
5023 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5024 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5025 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
5026 | |
5027 | if (mips_debug) | |
5028 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5029 | argreg, | |
1a69e1e4 | 5030 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 5031 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 5032 | |
74ed0bb4 | 5033 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
5034 | TYPE_LENGTH (arg_type) - len)) |
5035 | { | |
5036 | if (mips_debug) | |
5037 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
5038 | float_argreg, | |
5039 | phex (regval, MIPS64_REGSIZE)); | |
5040 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
5041 | regval); | |
5042 | } | |
5043 | ||
5044 | float_argreg++; | |
cb3d25d1 MS |
5045 | argreg++; |
5046 | } | |
5047 | ||
5048 | len -= partial_len; | |
5049 | val += partial_len; | |
5050 | ||
b021a221 MS |
5051 | /* Compute the offset into the stack at which we will |
5052 | copy the next parameter. | |
cb3d25d1 MS |
5053 | |
5054 | In N32 (N64?), the stack_offset only needs to be | |
5055 | adjusted when it has been used. */ | |
5056 | ||
5057 | if (stack_used_p) | |
1a69e1e4 | 5058 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
5059 | } |
5060 | } | |
5061 | if (mips_debug) | |
5062 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5063 | } | |
5064 | ||
f10683bb | 5065 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5066 | |
cb3d25d1 MS |
5067 | /* Return adjusted stack pointer. */ |
5068 | return sp; | |
5069 | } | |
5070 | ||
6d82d43b | 5071 | static enum return_value_convention |
6a3a010b | 5072 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 5073 | struct type *type, struct regcache *regcache, |
47a35522 | 5074 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 5075 | { |
72a155b4 | 5076 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
5077 | |
5078 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
5079 | ||
5080 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
5081 | if needed), as appropriate for the type. Composite results (struct, | |
5082 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
5083 | following rules: | |
5084 | ||
5085 | * A struct with only one or two floating point fields is returned in $f0 | |
5086 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
5087 | case. | |
5088 | ||
f08877ba | 5089 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
5090 | $2 (first 64 bits) and $3 (remainder, if necessary). |
5091 | ||
5092 | * Larger composite results are handled by converting the function to a | |
5093 | procedure with an implicit first parameter, which is a pointer to an area | |
5094 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
5095 | that all composite results be handled by conversion to implicit first | |
5096 | parameters. The MIPS/SGI Fortran implementation has always made a | |
5097 | specific exception to return COMPLEX results in the floating point | |
5098 | registers.] */ | |
5099 | ||
f08877ba | 5100 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 5101 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
5102 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
5103 | && TYPE_LENGTH (type) == 16 | |
5104 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5105 | { | |
5106 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
5107 | two registers are used in the same as memory order, so the | |
5108 | eight bytes with the lower memory address are in $f0. */ | |
5109 | if (mips_debug) | |
5110 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 5111 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5112 | (gdbarch_num_regs (gdbarch) |
5113 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 5114 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5115 | readbuf, writebuf, 0); |
ba32f989 | 5116 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5117 | (gdbarch_num_regs (gdbarch) |
5118 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 5119 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5120 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
5121 | writebuf ? writebuf + 8 : writebuf, 0); |
5122 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5123 | } | |
6d82d43b AC |
5124 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
5125 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5126 | { | |
59aa1faa | 5127 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
5128 | if (mips_debug) |
5129 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 5130 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5131 | (gdbarch_num_regs (gdbarch) |
5132 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 5133 | TYPE_LENGTH (type), |
72a155b4 | 5134 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5135 | readbuf, writebuf, 0); |
6d82d43b AC |
5136 | return RETURN_VALUE_REGISTER_CONVENTION; |
5137 | } | |
5138 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5139 | && TYPE_NFIELDS (type) <= 2 | |
5140 | && TYPE_NFIELDS (type) >= 1 | |
5141 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 5142 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
5143 | == TYPE_CODE_FLT)) |
5144 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 5145 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 5146 | == TYPE_CODE_FLT) |
b18bb924 | 5147 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 5148 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
5149 | { |
5150 | /* A struct that contains one or two floats. Each value is part | |
5151 | in the least significant part of their floating point | |
5b68030f | 5152 | register (or GPR, for soft float). */ |
6d82d43b AC |
5153 | int regnum; |
5154 | int field; | |
5b68030f JM |
5155 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
5156 | ? mips_regnum (gdbarch)->fp0 | |
5157 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
5158 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5159 | { | |
5160 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5161 | / TARGET_CHAR_BIT); | |
5162 | if (mips_debug) | |
5163 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5164 | offset); | |
5b68030f JM |
5165 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
5166 | { | |
5167 | /* A 16-byte long double field goes in two consecutive | |
5168 | registers. */ | |
5169 | mips_xfer_register (gdbarch, regcache, | |
5170 | gdbarch_num_regs (gdbarch) + regnum, | |
5171 | 8, | |
5172 | gdbarch_byte_order (gdbarch), | |
5173 | readbuf, writebuf, offset); | |
5174 | mips_xfer_register (gdbarch, regcache, | |
5175 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5176 | 8, | |
5177 | gdbarch_byte_order (gdbarch), | |
5178 | readbuf, writebuf, offset + 8); | |
5179 | } | |
5180 | else | |
5181 | mips_xfer_register (gdbarch, regcache, | |
5182 | gdbarch_num_regs (gdbarch) + regnum, | |
5183 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
5184 | gdbarch_byte_order (gdbarch), | |
5185 | readbuf, writebuf, offset); | |
6d82d43b AC |
5186 | } |
5187 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5188 | } | |
5189 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
5190 | || TYPE_CODE (type) == TYPE_CODE_UNION |
5191 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 5192 | { |
f08877ba | 5193 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
5194 | regardless of the byte order. I.e. DO NOT USE |
5195 | mips_xfer_lower. */ | |
5196 | int offset; | |
5197 | int regnum; | |
4c7d22cb | 5198 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5199 | offset < TYPE_LENGTH (type); |
72a155b4 | 5200 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5201 | { |
72a155b4 | 5202 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5203 | if (offset + xfer > TYPE_LENGTH (type)) |
5204 | xfer = TYPE_LENGTH (type) - offset; | |
5205 | if (mips_debug) | |
5206 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5207 | offset, xfer, regnum); | |
ba32f989 DJ |
5208 | mips_xfer_register (gdbarch, regcache, |
5209 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5210 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5211 | offset); | |
6d82d43b AC |
5212 | } |
5213 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5214 | } | |
5215 | else | |
5216 | { | |
5217 | /* A scalar extract each part but least-significant-byte | |
5218 | justified. */ | |
5219 | int offset; | |
5220 | int regnum; | |
4c7d22cb | 5221 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5222 | offset < TYPE_LENGTH (type); |
72a155b4 | 5223 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5224 | { |
72a155b4 | 5225 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5226 | if (offset + xfer > TYPE_LENGTH (type)) |
5227 | xfer = TYPE_LENGTH (type) - offset; | |
5228 | if (mips_debug) | |
5229 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5230 | offset, xfer, regnum); | |
ba32f989 DJ |
5231 | mips_xfer_register (gdbarch, regcache, |
5232 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5233 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5234 | readbuf, writebuf, offset); |
6d82d43b AC |
5235 | } |
5236 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5237 | } | |
5238 | } | |
5239 | ||
6a3a010b MR |
5240 | /* Which registers to use for passing floating-point values between |
5241 | function calls, one of floating-point, general and both kinds of | |
5242 | registers. O32 and O64 use different register kinds for standard | |
5243 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5244 | not know what kind of code is being used (e.g. no debug information) | |
5245 | easier we sometimes use both kinds. */ | |
5246 | ||
5247 | enum mips_fval_reg | |
5248 | { | |
5249 | mips_fval_fpr, | |
5250 | mips_fval_gpr, | |
5251 | mips_fval_both | |
5252 | }; | |
5253 | ||
6d82d43b AC |
5254 | /* O32 ABI stuff. */ |
5255 | ||
5256 | static CORE_ADDR | |
7d9b040b | 5257 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5258 | struct regcache *regcache, CORE_ADDR bp_addr, |
5259 | int nargs, struct value **args, CORE_ADDR sp, | |
5260 | int struct_return, CORE_ADDR struct_addr) | |
5261 | { | |
5262 | int argreg; | |
5263 | int float_argreg; | |
5264 | int argnum; | |
5265 | int len = 0; | |
5266 | int stack_offset = 0; | |
e17a4113 | 5267 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5268 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5269 | |
5270 | /* For shared libraries, "t9" needs to point at the function | |
5271 | address. */ | |
4c7d22cb | 5272 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5273 | |
5274 | /* Set the return address register to point to the entry point of | |
5275 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5276 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5277 | |
5278 | /* First ensure that the stack and structure return address (if any) | |
5279 | are properly aligned. The stack has to be at least 64-bit | |
5280 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5281 | aligned. For n32 and n64, stack frames need to be 128-bit |
5282 | aligned, so we round to this widest known alignment. */ | |
5283 | ||
5b03f266 AC |
5284 | sp = align_down (sp, 16); |
5285 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5286 | |
5287 | /* Now make space on the stack for the args. */ | |
5288 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5289 | { |
5290 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 MR |
5291 | |
5292 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5293 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 5294 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 5295 | /* Allocate space on the stack. */ |
354ecfd5 | 5296 | len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE); |
968b5391 | 5297 | } |
5b03f266 | 5298 | sp -= align_up (len, 16); |
ebafbe83 MS |
5299 | |
5300 | if (mips_debug) | |
6d82d43b | 5301 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5302 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
5303 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
5304 | |
5305 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5306 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5307 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5308 | |
bcb0cc15 | 5309 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
5310 | if (struct_return) |
5311 | { | |
5312 | if (mips_debug) | |
5313 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5314 | "mips_o32_push_dummy_call: " |
5315 | "struct_return reg=%d %s\n", | |
5af949e3 | 5316 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5317 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5318 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5319 | } |
5320 | ||
5321 | /* Now load as many as possible of the first arguments into | |
5322 | registers, and push the rest onto the stack. Loop thru args | |
5323 | from first to last. */ | |
5324 | for (argnum = 0; argnum < nargs; argnum++) | |
5325 | { | |
47a35522 | 5326 | const gdb_byte *val; |
ebafbe83 | 5327 | struct value *arg = args[argnum]; |
4991999e | 5328 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
5329 | int len = TYPE_LENGTH (arg_type); |
5330 | enum type_code typecode = TYPE_CODE (arg_type); | |
5331 | ||
5332 | if (mips_debug) | |
5333 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5334 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
5335 | argnum + 1, len, (int) typecode); |
5336 | ||
47a35522 | 5337 | val = value_contents (arg); |
46cac009 AC |
5338 | |
5339 | /* 32-bit ABIs always start floating point arguments in an | |
5340 | even-numbered floating point register. Round the FP register | |
5341 | up before the check to see if there are any FP registers | |
6a3a010b MR |
5342 | left. O32 targets also pass the FP in the integer registers |
5343 | so also round up normal registers. */ | |
74ed0bb4 | 5344 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5345 | { |
5346 | if ((float_argreg & 1)) | |
5347 | float_argreg++; | |
5348 | } | |
5349 | ||
5350 | /* Floating point arguments passed in registers have to be | |
6a3a010b MR |
5351 | treated specially. On 32-bit architectures, doubles are |
5352 | passed in register pairs; the even FP register gets the | |
5353 | low word, and the odd FP register gets the high word. | |
5354 | On O32, the first two floating point arguments are also | |
5355 | copied to general registers, following their memory order, | |
5356 | because MIPS16 functions don't use float registers for | |
5357 | arguments. This duplication of arguments in general | |
5358 | registers can't hurt non-MIPS16 functions, because those | |
5359 | registers are normally skipped. */ | |
46cac009 | 5360 | |
74ed0bb4 MD |
5361 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5362 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 5363 | { |
8b07f6d8 | 5364 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5365 | { |
6a3a010b MR |
5366 | int freg_offset = gdbarch_byte_order (gdbarch) |
5367 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5368 | unsigned long regval; |
5369 | ||
6a3a010b MR |
5370 | /* First word. */ |
5371 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
5372 | if (mips_debug) |
5373 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5374 | float_argreg + freg_offset, |
5375 | phex (regval, 4)); | |
025bb325 | 5376 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5377 | float_argreg++ + freg_offset, |
5378 | regval); | |
46cac009 AC |
5379 | if (mips_debug) |
5380 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5381 | argreg, phex (regval, 4)); | |
9c9acae0 | 5382 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5383 | |
6a3a010b MR |
5384 | /* Second word. */ |
5385 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
5386 | if (mips_debug) |
5387 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5388 | float_argreg - freg_offset, |
5389 | phex (regval, 4)); | |
025bb325 | 5390 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5391 | float_argreg++ - freg_offset, |
5392 | regval); | |
46cac009 AC |
5393 | if (mips_debug) |
5394 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5395 | argreg, phex (regval, 4)); | |
9c9acae0 | 5396 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5397 | } |
5398 | else | |
5399 | { | |
5400 | /* This is a floating point value that fits entirely | |
5401 | in a single register. */ | |
5402 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 5403 | above to ensure that it is even register aligned. */ |
e17a4113 | 5404 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
5405 | if (mips_debug) |
5406 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5407 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5408 | regcache_cooked_write_unsigned (regcache, |
5409 | float_argreg++, regval); | |
5b68030f JM |
5410 | /* Although two FP registers are reserved for each |
5411 | argument, only one corresponding integer register is | |
5412 | reserved. */ | |
46cac009 AC |
5413 | if (mips_debug) |
5414 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5415 | argreg, phex (regval, len)); | |
5b68030f | 5416 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5417 | } |
5418 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5419 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5420 | } |
5421 | else | |
5422 | { | |
5423 | /* Copy the argument to general registers or the stack in | |
5424 | register-sized pieces. Large arguments are split between | |
5425 | registers and stack. */ | |
1a69e1e4 DJ |
5426 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5427 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5428 | them in registers where gcc sometimes puts them on the |
5429 | stack. For maximum compatibility, we will put them in | |
5430 | both places. */ | |
1a69e1e4 DJ |
5431 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5432 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5433 | /* Structures should be aligned to eight bytes (even arg registers) |
5434 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5435 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5436 | { |
5437 | if ((argreg & 1)) | |
968b5391 MR |
5438 | { |
5439 | argreg++; | |
1a69e1e4 | 5440 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5441 | } |
46cac009 | 5442 | } |
46cac009 AC |
5443 | while (len > 0) |
5444 | { | |
5445 | /* Remember if the argument was written to the stack. */ | |
5446 | int stack_used_p = 0; | |
1a69e1e4 | 5447 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5448 | |
5449 | if (mips_debug) | |
5450 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5451 | partial_len); | |
5452 | ||
5453 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5454 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5455 | || odd_sized_struct) |
46cac009 AC |
5456 | { |
5457 | /* Should shorter than int integer values be | |
025bb325 | 5458 | promoted to int before being stored? */ |
46cac009 AC |
5459 | int longword_offset = 0; |
5460 | CORE_ADDR addr; | |
5461 | stack_used_p = 1; | |
46cac009 AC |
5462 | |
5463 | if (mips_debug) | |
5464 | { | |
5af949e3 UW |
5465 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5466 | paddress (gdbarch, stack_offset)); | |
5467 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5468 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5469 | } |
5470 | ||
5471 | addr = sp + stack_offset + longword_offset; | |
5472 | ||
5473 | if (mips_debug) | |
5474 | { | |
5475 | int i; | |
5af949e3 UW |
5476 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5477 | paddress (gdbarch, addr)); | |
46cac009 AC |
5478 | for (i = 0; i < partial_len; i++) |
5479 | { | |
6d82d43b | 5480 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
5481 | val[i] & 0xff); |
5482 | } | |
5483 | } | |
5484 | write_memory (addr, val, partial_len); | |
5485 | } | |
5486 | ||
5487 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5488 | structs may go thru BOTH paths. */ |
46cac009 | 5489 | /* Write this portion of the argument to a general |
6d82d43b | 5490 | purpose register. */ |
74ed0bb4 | 5491 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 5492 | { |
e17a4113 UW |
5493 | LONGEST regval = extract_signed_integer (val, partial_len, |
5494 | byte_order); | |
4246e332 | 5495 | /* Value may need to be sign extended, because |
1b13c4f6 | 5496 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5497 | |
5498 | /* A non-floating-point argument being passed in a | |
5499 | general register. If a struct or union, and if | |
5500 | the remaining length is smaller than the register | |
5501 | size, we have to adjust the register value on | |
5502 | big endian targets. | |
5503 | ||
5504 | It does not seem to be necessary to do the | |
5505 | same for integral types. | |
5506 | ||
5507 | Also don't do this adjustment on O64 binaries. | |
5508 | ||
5509 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5510 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5511 | mips_abi_regsize(), generates a left shift |
5512 | as part of storing the argument in a register | |
5513 | (the left shift isn't generated when | |
1b13c4f6 | 5514 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5515 | it is quite possible that this is GCC |
5516 | contradicting the LE/O32 ABI, GDB has not been | |
5517 | adjusted to accommodate this. Either someone | |
5518 | needs to demonstrate that the LE/O32 ABI | |
5519 | specifies such a left shift OR this new ABI gets | |
5520 | identified as such and GDB gets tweaked | |
5521 | accordingly. */ | |
5522 | ||
72a155b4 | 5523 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5524 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5525 | && (typecode == TYPE_CODE_STRUCT |
5526 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5527 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5528 | * TARGET_CHAR_BIT); |
46cac009 AC |
5529 | |
5530 | if (mips_debug) | |
5531 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5532 | argreg, | |
1a69e1e4 | 5533 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 5534 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5535 | argreg++; |
5536 | ||
5537 | /* Prevent subsequent floating point arguments from | |
5538 | being passed in floating point registers. */ | |
74ed0bb4 | 5539 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
5540 | } |
5541 | ||
5542 | len -= partial_len; | |
5543 | val += partial_len; | |
5544 | ||
b021a221 MS |
5545 | /* Compute the offset into the stack at which we will |
5546 | copy the next parameter. | |
46cac009 | 5547 | |
6d82d43b AC |
5548 | In older ABIs, the caller reserved space for |
5549 | registers that contained arguments. This was loosely | |
5550 | refered to as their "home". Consequently, space is | |
5551 | always allocated. */ | |
46cac009 | 5552 | |
1a69e1e4 | 5553 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5554 | } |
5555 | } | |
5556 | if (mips_debug) | |
5557 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5558 | } | |
5559 | ||
f10683bb | 5560 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5561 | |
46cac009 AC |
5562 | /* Return adjusted stack pointer. */ |
5563 | return sp; | |
5564 | } | |
5565 | ||
6d82d43b | 5566 | static enum return_value_convention |
6a3a010b | 5567 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5568 | struct type *type, struct regcache *regcache, |
47a35522 | 5569 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5570 | { |
6a3a010b | 5571 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5572 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5573 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5574 | enum mips_fval_reg fval_reg; |
6d82d43b | 5575 | |
6a3a010b | 5576 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
6d82d43b AC |
5577 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5578 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5579 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5580 | return RETURN_VALUE_STRUCT_CONVENTION; | |
5581 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5582 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5583 | { | |
6a3a010b MR |
5584 | /* A single-precision floating-point value. If reading in or copying, |
5585 | then we get it from/put it to FP0 for standard MIPS code or GPR2 | |
5586 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5587 | and GPR2. We do not support reading in with no function known, if | |
5588 | this safety check ever triggers, then we'll have to try harder. */ | |
5589 | gdb_assert (function || !readbuf); | |
6d82d43b | 5590 | if (mips_debug) |
6a3a010b MR |
5591 | switch (fval_reg) |
5592 | { | |
5593 | case mips_fval_fpr: | |
5594 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5595 | break; | |
5596 | case mips_fval_gpr: | |
5597 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5598 | break; | |
5599 | case mips_fval_both: | |
5600 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5601 | break; | |
5602 | } | |
5603 | if (fval_reg != mips_fval_gpr) | |
5604 | mips_xfer_register (gdbarch, regcache, | |
5605 | (gdbarch_num_regs (gdbarch) | |
5606 | + mips_regnum (gdbarch)->fp0), | |
5607 | TYPE_LENGTH (type), | |
5608 | gdbarch_byte_order (gdbarch), | |
5609 | readbuf, writebuf, 0); | |
5610 | if (fval_reg != mips_fval_fpr) | |
5611 | mips_xfer_register (gdbarch, regcache, | |
5612 | gdbarch_num_regs (gdbarch) + 2, | |
5613 | TYPE_LENGTH (type), | |
5614 | gdbarch_byte_order (gdbarch), | |
5615 | readbuf, writebuf, 0); | |
6d82d43b AC |
5616 | return RETURN_VALUE_REGISTER_CONVENTION; |
5617 | } | |
5618 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5619 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5620 | { | |
6a3a010b MR |
5621 | /* A double-precision floating-point value. If reading in or copying, |
5622 | then we get it from/put it to FP1 and FP0 for standard MIPS code or | |
5623 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5624 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5625 | no function known, if this safety check ever triggers, then we'll | |
5626 | have to try harder. */ | |
5627 | gdb_assert (function || !readbuf); | |
6d82d43b | 5628 | if (mips_debug) |
6a3a010b MR |
5629 | switch (fval_reg) |
5630 | { | |
5631 | case mips_fval_fpr: | |
5632 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
5633 | break; | |
5634 | case mips_fval_gpr: | |
5635 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
5636 | break; | |
5637 | case mips_fval_both: | |
5638 | fprintf_unfiltered (gdb_stderr, | |
5639 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
5640 | break; | |
5641 | } | |
5642 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5643 | { |
6a3a010b MR |
5644 | /* The most significant part goes in FP1, and the least significant |
5645 | in FP0. */ | |
5646 | switch (gdbarch_byte_order (gdbarch)) | |
5647 | { | |
5648 | case BFD_ENDIAN_LITTLE: | |
5649 | mips_xfer_register (gdbarch, regcache, | |
5650 | (gdbarch_num_regs (gdbarch) | |
5651 | + mips_regnum (gdbarch)->fp0 + 0), | |
5652 | 4, gdbarch_byte_order (gdbarch), | |
5653 | readbuf, writebuf, 0); | |
5654 | mips_xfer_register (gdbarch, regcache, | |
5655 | (gdbarch_num_regs (gdbarch) | |
5656 | + mips_regnum (gdbarch)->fp0 + 1), | |
5657 | 4, gdbarch_byte_order (gdbarch), | |
5658 | readbuf, writebuf, 4); | |
5659 | break; | |
5660 | case BFD_ENDIAN_BIG: | |
5661 | mips_xfer_register (gdbarch, regcache, | |
5662 | (gdbarch_num_regs (gdbarch) | |
5663 | + mips_regnum (gdbarch)->fp0 + 1), | |
5664 | 4, gdbarch_byte_order (gdbarch), | |
5665 | readbuf, writebuf, 0); | |
5666 | mips_xfer_register (gdbarch, regcache, | |
5667 | (gdbarch_num_regs (gdbarch) | |
5668 | + mips_regnum (gdbarch)->fp0 + 0), | |
5669 | 4, gdbarch_byte_order (gdbarch), | |
5670 | readbuf, writebuf, 4); | |
5671 | break; | |
5672 | default: | |
5673 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
5674 | } | |
5675 | } | |
5676 | if (fval_reg != mips_fval_fpr) | |
5677 | { | |
5678 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5679 | following these registers' memory order. */ | |
ba32f989 | 5680 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5681 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5682 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5683 | readbuf, writebuf, 0); |
ba32f989 | 5684 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5685 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5686 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5687 | readbuf, writebuf, 4); |
6d82d43b AC |
5688 | } |
5689 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5690 | } | |
5691 | #if 0 | |
5692 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5693 | && TYPE_NFIELDS (type) <= 2 | |
5694 | && TYPE_NFIELDS (type) >= 1 | |
5695 | && ((TYPE_NFIELDS (type) == 1 | |
5696 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5697 | == TYPE_CODE_FLT)) | |
5698 | || (TYPE_NFIELDS (type) == 2 | |
5699 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5700 | == TYPE_CODE_FLT) | |
5701 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
5702 | == TYPE_CODE_FLT))) | |
5703 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5704 | { | |
5705 | /* A struct that contains one or two floats. Each value is part | |
5706 | in the least significant part of their floating point | |
5707 | register.. */ | |
870cd05e | 5708 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
5709 | int regnum; |
5710 | int field; | |
72a155b4 | 5711 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
5712 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5713 | { | |
5714 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5715 | / TARGET_CHAR_BIT); | |
5716 | if (mips_debug) | |
5717 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5718 | offset); | |
ba32f989 DJ |
5719 | mips_xfer_register (gdbarch, regcache, |
5720 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 5721 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 5722 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5723 | readbuf, writebuf, offset); |
6d82d43b AC |
5724 | } |
5725 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5726 | } | |
5727 | #endif | |
5728 | #if 0 | |
5729 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5730 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
5731 | { | |
5732 | /* A structure or union. Extract the left justified value, | |
5733 | regardless of the byte order. I.e. DO NOT USE | |
5734 | mips_xfer_lower. */ | |
5735 | int offset; | |
5736 | int regnum; | |
4c7d22cb | 5737 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5738 | offset < TYPE_LENGTH (type); |
72a155b4 | 5739 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5740 | { |
72a155b4 | 5741 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5742 | if (offset + xfer > TYPE_LENGTH (type)) |
5743 | xfer = TYPE_LENGTH (type) - offset; | |
5744 | if (mips_debug) | |
5745 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5746 | offset, xfer, regnum); | |
ba32f989 DJ |
5747 | mips_xfer_register (gdbarch, regcache, |
5748 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5749 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5750 | } | |
5751 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5752 | } | |
5753 | #endif | |
5754 | else | |
5755 | { | |
5756 | /* A scalar extract each part but least-significant-byte | |
5757 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 5758 | the ISA. */ |
6d82d43b AC |
5759 | int offset; |
5760 | int regnum; | |
4c7d22cb | 5761 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5762 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 5763 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5764 | { |
1a69e1e4 | 5765 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
5766 | if (offset + xfer > TYPE_LENGTH (type)) |
5767 | xfer = TYPE_LENGTH (type) - offset; | |
5768 | if (mips_debug) | |
5769 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5770 | offset, xfer, regnum); | |
ba32f989 DJ |
5771 | mips_xfer_register (gdbarch, regcache, |
5772 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5773 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5774 | readbuf, writebuf, offset); |
6d82d43b AC |
5775 | } |
5776 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5777 | } | |
5778 | } | |
5779 | ||
5780 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5781 | ABI. */ | |
46cac009 AC |
5782 | |
5783 | static CORE_ADDR | |
7d9b040b | 5784 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5785 | struct regcache *regcache, CORE_ADDR bp_addr, |
5786 | int nargs, | |
5787 | struct value **args, CORE_ADDR sp, | |
5788 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
5789 | { |
5790 | int argreg; | |
5791 | int float_argreg; | |
5792 | int argnum; | |
5793 | int len = 0; | |
5794 | int stack_offset = 0; | |
e17a4113 | 5795 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5796 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5797 | |
25ab4790 AC |
5798 | /* For shared libraries, "t9" needs to point at the function |
5799 | address. */ | |
4c7d22cb | 5800 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5801 | |
5802 | /* Set the return address register to point to the entry point of | |
5803 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5804 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5805 | |
46cac009 AC |
5806 | /* First ensure that the stack and structure return address (if any) |
5807 | are properly aligned. The stack has to be at least 64-bit | |
5808 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5809 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5810 | aligned, so we round to this widest known alignment. */ | |
5811 | ||
5b03f266 AC |
5812 | sp = align_down (sp, 16); |
5813 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5814 | |
5815 | /* Now make space on the stack for the args. */ | |
5816 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5817 | { |
5818 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 | 5819 | |
968b5391 | 5820 | /* Allocate space on the stack. */ |
354ecfd5 | 5821 | len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE); |
968b5391 | 5822 | } |
5b03f266 | 5823 | sp -= align_up (len, 16); |
46cac009 AC |
5824 | |
5825 | if (mips_debug) | |
6d82d43b | 5826 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5827 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
5828 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
5829 | |
5830 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5831 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5832 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5833 | |
5834 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
5835 | if (struct_return) | |
5836 | { | |
5837 | if (mips_debug) | |
5838 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5839 | "mips_o64_push_dummy_call: " |
5840 | "struct_return reg=%d %s\n", | |
5af949e3 | 5841 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5842 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5843 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5844 | } |
5845 | ||
5846 | /* Now load as many as possible of the first arguments into | |
5847 | registers, and push the rest onto the stack. Loop thru args | |
5848 | from first to last. */ | |
5849 | for (argnum = 0; argnum < nargs; argnum++) | |
5850 | { | |
47a35522 | 5851 | const gdb_byte *val; |
930bd0e0 | 5852 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 5853 | struct value *arg = args[argnum]; |
4991999e | 5854 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
5855 | int len = TYPE_LENGTH (arg_type); |
5856 | enum type_code typecode = TYPE_CODE (arg_type); | |
5857 | ||
5858 | if (mips_debug) | |
5859 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5860 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
5861 | argnum + 1, len, (int) typecode); |
5862 | ||
47a35522 | 5863 | val = value_contents (arg); |
ebafbe83 | 5864 | |
930bd0e0 KB |
5865 | /* Function pointer arguments to mips16 code need to be made into |
5866 | mips16 pointers. */ | |
5867 | if (typecode == TYPE_CODE_PTR | |
5868 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
5869 | { | |
5870 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
5871 | len, byte_order); | |
4cc0665f | 5872 | if (!mips_pc_is_mips (addr)) |
930bd0e0 KB |
5873 | { |
5874 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 5875 | make_compact_addr (addr)); |
930bd0e0 KB |
5876 | val = valbuf; |
5877 | } | |
5878 | } | |
5879 | ||
ebafbe83 | 5880 | /* Floating point arguments passed in registers have to be |
6a3a010b MR |
5881 | treated specially. On 32-bit architectures, doubles are |
5882 | passed in register pairs; the even FP register gets the | |
5883 | low word, and the odd FP register gets the high word. | |
5884 | On O64, the first two floating point arguments are also | |
5885 | copied to general registers, because MIPS16 functions | |
5886 | don't use float registers for arguments. This duplication | |
5887 | of arguments in general registers can't hurt non-MIPS16 | |
5888 | functions because those registers are normally skipped. */ | |
ebafbe83 | 5889 | |
74ed0bb4 MD |
5890 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5891 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 5892 | { |
e17a4113 | 5893 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
5894 | if (mips_debug) |
5895 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5896 | float_argreg, phex (regval, len)); | |
9c9acae0 | 5897 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
5898 | if (mips_debug) |
5899 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5900 | argreg, phex (regval, len)); | |
9c9acae0 | 5901 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 5902 | argreg++; |
ebafbe83 | 5903 | /* Reserve space for the FP register. */ |
1a69e1e4 | 5904 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
5905 | } |
5906 | else | |
5907 | { | |
5908 | /* Copy the argument to general registers or the stack in | |
5909 | register-sized pieces. Large arguments are split between | |
5910 | registers and stack. */ | |
1a69e1e4 | 5911 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
5912 | are treated specially: Irix cc passes them in registers |
5913 | where gcc sometimes puts them on the stack. For maximum | |
5914 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
5915 | int odd_sized_struct = (len > MIPS64_REGSIZE |
5916 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
5917 | while (len > 0) |
5918 | { | |
5919 | /* Remember if the argument was written to the stack. */ | |
5920 | int stack_used_p = 0; | |
1a69e1e4 | 5921 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
5922 | |
5923 | if (mips_debug) | |
5924 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5925 | partial_len); | |
5926 | ||
5927 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5928 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5929 | || odd_sized_struct) |
ebafbe83 MS |
5930 | { |
5931 | /* Should shorter than int integer values be | |
025bb325 | 5932 | promoted to int before being stored? */ |
ebafbe83 MS |
5933 | int longword_offset = 0; |
5934 | CORE_ADDR addr; | |
5935 | stack_used_p = 1; | |
72a155b4 | 5936 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 5937 | { |
1a69e1e4 DJ |
5938 | if ((typecode == TYPE_CODE_INT |
5939 | || typecode == TYPE_CODE_PTR | |
5940 | || typecode == TYPE_CODE_FLT) | |
5941 | && len <= 4) | |
5942 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
5943 | } |
5944 | ||
5945 | if (mips_debug) | |
5946 | { | |
5af949e3 UW |
5947 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5948 | paddress (gdbarch, stack_offset)); | |
5949 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5950 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
5951 | } |
5952 | ||
5953 | addr = sp + stack_offset + longword_offset; | |
5954 | ||
5955 | if (mips_debug) | |
5956 | { | |
5957 | int i; | |
5af949e3 UW |
5958 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5959 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
5960 | for (i = 0; i < partial_len; i++) |
5961 | { | |
6d82d43b | 5962 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
5963 | val[i] & 0xff); |
5964 | } | |
5965 | } | |
5966 | write_memory (addr, val, partial_len); | |
5967 | } | |
5968 | ||
5969 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5970 | structs may go thru BOTH paths. */ |
ebafbe83 | 5971 | /* Write this portion of the argument to a general |
6d82d43b | 5972 | purpose register. */ |
74ed0bb4 | 5973 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 5974 | { |
e17a4113 UW |
5975 | LONGEST regval = extract_signed_integer (val, partial_len, |
5976 | byte_order); | |
4246e332 | 5977 | /* Value may need to be sign extended, because |
1b13c4f6 | 5978 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
5979 | |
5980 | /* A non-floating-point argument being passed in a | |
5981 | general register. If a struct or union, and if | |
5982 | the remaining length is smaller than the register | |
5983 | size, we have to adjust the register value on | |
5984 | big endian targets. | |
5985 | ||
5986 | It does not seem to be necessary to do the | |
025bb325 | 5987 | same for integral types. */ |
480d3dd2 | 5988 | |
72a155b4 | 5989 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5990 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5991 | && (typecode == TYPE_CODE_STRUCT |
5992 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5993 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5994 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
5995 | |
5996 | if (mips_debug) | |
5997 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5998 | argreg, | |
1a69e1e4 | 5999 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 6000 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
6001 | argreg++; |
6002 | ||
6003 | /* Prevent subsequent floating point arguments from | |
6004 | being passed in floating point registers. */ | |
74ed0bb4 | 6005 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
6006 | } |
6007 | ||
6008 | len -= partial_len; | |
6009 | val += partial_len; | |
6010 | ||
b021a221 MS |
6011 | /* Compute the offset into the stack at which we will |
6012 | copy the next parameter. | |
ebafbe83 | 6013 | |
6d82d43b AC |
6014 | In older ABIs, the caller reserved space for |
6015 | registers that contained arguments. This was loosely | |
6016 | refered to as their "home". Consequently, space is | |
6017 | always allocated. */ | |
ebafbe83 | 6018 | |
1a69e1e4 | 6019 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
6020 | } |
6021 | } | |
6022 | if (mips_debug) | |
6023 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
6024 | } | |
6025 | ||
f10683bb | 6026 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 6027 | |
ebafbe83 MS |
6028 | /* Return adjusted stack pointer. */ |
6029 | return sp; | |
6030 | } | |
6031 | ||
9c8fdbfa | 6032 | static enum return_value_convention |
6a3a010b | 6033 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 6034 | struct type *type, struct regcache *regcache, |
47a35522 | 6035 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 6036 | { |
6a3a010b | 6037 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 6038 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 6039 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 6040 | enum mips_fval_reg fval_reg; |
7a076fd2 | 6041 | |
6a3a010b | 6042 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
7a076fd2 FF |
6043 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
6044 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
6045 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6046 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 6047 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 | 6048 | { |
6a3a010b MR |
6049 | /* A floating-point value. If reading in or copying, then we get it |
6050 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. | |
6051 | If writing out only, then we put it to both FP0 and GPR2. We do | |
6052 | not support reading in with no function known, if this safety | |
6053 | check ever triggers, then we'll have to try harder. */ | |
6054 | gdb_assert (function || !readbuf); | |
7a076fd2 | 6055 | if (mips_debug) |
6a3a010b MR |
6056 | switch (fval_reg) |
6057 | { | |
6058 | case mips_fval_fpr: | |
6059 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
6060 | break; | |
6061 | case mips_fval_gpr: | |
6062 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
6063 | break; | |
6064 | case mips_fval_both: | |
6065 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
6066 | break; | |
6067 | } | |
6068 | if (fval_reg != mips_fval_gpr) | |
6069 | mips_xfer_register (gdbarch, regcache, | |
6070 | (gdbarch_num_regs (gdbarch) | |
6071 | + mips_regnum (gdbarch)->fp0), | |
6072 | TYPE_LENGTH (type), | |
6073 | gdbarch_byte_order (gdbarch), | |
6074 | readbuf, writebuf, 0); | |
6075 | if (fval_reg != mips_fval_fpr) | |
6076 | mips_xfer_register (gdbarch, regcache, | |
6077 | gdbarch_num_regs (gdbarch) + 2, | |
6078 | TYPE_LENGTH (type), | |
6079 | gdbarch_byte_order (gdbarch), | |
6080 | readbuf, writebuf, 0); | |
7a076fd2 FF |
6081 | return RETURN_VALUE_REGISTER_CONVENTION; |
6082 | } | |
6083 | else | |
6084 | { | |
6085 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 6086 | justified. */ |
7a076fd2 FF |
6087 | int offset; |
6088 | int regnum; | |
6089 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
6090 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 6091 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 6092 | { |
1a69e1e4 | 6093 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
6094 | if (offset + xfer > TYPE_LENGTH (type)) |
6095 | xfer = TYPE_LENGTH (type) - offset; | |
6096 | if (mips_debug) | |
6097 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
6098 | offset, xfer, regnum); | |
ba32f989 DJ |
6099 | mips_xfer_register (gdbarch, regcache, |
6100 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 6101 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 6102 | readbuf, writebuf, offset); |
7a076fd2 FF |
6103 | } |
6104 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6105 | } | |
6d82d43b AC |
6106 | } |
6107 | ||
dd824b04 DJ |
6108 | /* Floating point register management. |
6109 | ||
6110 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
6111 | 64bit operations, these early MIPS cpus treat fp register pairs | |
6112 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
6113 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
6114 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
6115 | double precision floats into two 32-bit chunks and store them in | |
6116 | consecutive fp regs. To display 64-bit floats stored in this | |
6117 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
6118 | Throw in user-configurable endianness and you have a real mess. | |
6119 | ||
6120 | The way this works is: | |
6121 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
6122 | double-precision value will be split across two logical registers. | |
6123 | The lower-numbered logical register will hold the low-order bits, | |
6124 | regardless of the processor's endianness. | |
6125 | - If we are on a 64-bit processor, and we are looking for a | |
6126 | single-precision value, it will be in the low ordered bits | |
6127 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
6128 | save slot in memory. | |
6129 | - If we are in 64-bit mode, everything is straightforward. | |
6130 | ||
6131 | Note that this code only deals with "live" registers at the top of the | |
6132 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 6133 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
6134 | interface that can deal with dynamic saved register sizes -- fp |
6135 | regs could be 32 bits wide in one frame and 64 on the frame above | |
6136 | and below). */ | |
6137 | ||
6138 | /* Copy a 32-bit single-precision value from the current frame | |
6139 | into rare_buffer. */ | |
6140 | ||
6141 | static void | |
e11c53d2 | 6142 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 6143 | gdb_byte *rare_buffer) |
dd824b04 | 6144 | { |
72a155b4 UW |
6145 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6146 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 6147 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 6148 | |
ca9d61b9 | 6149 | if (!deprecated_frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 6150 | error (_("can't read register %d (%s)"), |
72a155b4 | 6151 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6152 | if (raw_size == 8) |
6153 | { | |
6154 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 6155 | 32 bits. */ |
dd824b04 DJ |
6156 | int offset; |
6157 | ||
72a155b4 | 6158 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
6159 | offset = 4; |
6160 | else | |
6161 | offset = 0; | |
6162 | ||
6163 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6164 | } | |
6165 | else | |
6166 | { | |
6167 | memcpy (rare_buffer, raw_buffer, 4); | |
6168 | } | |
6169 | } | |
6170 | ||
6171 | /* Copy a 64-bit double-precision value from the current frame into | |
6172 | rare_buffer. This may include getting half of it from the next | |
6173 | register. */ | |
6174 | ||
6175 | static void | |
e11c53d2 | 6176 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 6177 | gdb_byte *rare_buffer) |
dd824b04 | 6178 | { |
72a155b4 UW |
6179 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6180 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6181 | |
9c9acae0 | 6182 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6183 | { |
6184 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 6185 | all 64 bits. */ |
ca9d61b9 | 6186 | if (!deprecated_frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6187 | error (_("can't read register %d (%s)"), |
72a155b4 | 6188 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6189 | } |
6190 | else | |
6191 | { | |
72a155b4 | 6192 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6193 | |
72a155b4 | 6194 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 6195 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
6196 | _("mips_read_fp_register_double: bad access to " |
6197 | "odd-numbered FP register")); | |
dd824b04 DJ |
6198 | |
6199 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 6200 | each register. */ |
72a155b4 | 6201 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6202 | { |
e11c53d2 AC |
6203 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6204 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6205 | } |
361d1df0 | 6206 | else |
dd824b04 | 6207 | { |
e11c53d2 AC |
6208 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6209 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6210 | } |
6211 | } | |
6212 | } | |
6213 | ||
c906108c | 6214 | static void |
e11c53d2 AC |
6215 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
6216 | int regnum) | |
025bb325 | 6217 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6218 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6219 | gdb_byte *raw_buffer; |
025bb325 | 6220 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 6221 | int inv1, inv2; |
c5aa993b | 6222 | |
025bb325 MS |
6223 | raw_buffer = alloca (2 * register_size (gdbarch, |
6224 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 6225 | |
72a155b4 | 6226 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 6227 | fprintf_filtered (file, "%*s", |
72a155b4 | 6228 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 6229 | ""); |
f0ef6b29 | 6230 | |
72a155b4 | 6231 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6232 | { |
79a45b7d TT |
6233 | struct value_print_options opts; |
6234 | ||
f0ef6b29 KB |
6235 | /* 4-byte registers: Print hex and floating. Also print even |
6236 | numbered registers as doubles. */ | |
e11c53d2 | 6237 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
6238 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6239 | raw_buffer, &inv1); | |
c5aa993b | 6240 | |
79a45b7d | 6241 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6242 | print_scalar_formatted (raw_buffer, |
6243 | builtin_type (gdbarch)->builtin_uint32, | |
6244 | &opts, 'w', file); | |
dd824b04 | 6245 | |
e11c53d2 | 6246 | fprintf_filtered (file, " flt: "); |
1adad886 | 6247 | if (inv1) |
e11c53d2 | 6248 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 6249 | else |
e11c53d2 | 6250 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6251 | |
72a155b4 | 6252 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6253 | { |
e11c53d2 | 6254 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6255 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6256 | raw_buffer, &inv2); | |
1adad886 | 6257 | |
e11c53d2 | 6258 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6259 | if (inv2) |
e11c53d2 | 6260 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 6261 | else |
e11c53d2 | 6262 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 6263 | } |
c906108c SS |
6264 | } |
6265 | else | |
dd824b04 | 6266 | { |
79a45b7d TT |
6267 | struct value_print_options opts; |
6268 | ||
f0ef6b29 | 6269 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6270 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
6271 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6272 | raw_buffer, &inv1); | |
c906108c | 6273 | |
e11c53d2 | 6274 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6275 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6276 | raw_buffer, &inv2); | |
f0ef6b29 | 6277 | |
79a45b7d | 6278 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6279 | print_scalar_formatted (raw_buffer, |
6280 | builtin_type (gdbarch)->builtin_uint64, | |
6281 | &opts, 'g', file); | |
f0ef6b29 | 6282 | |
e11c53d2 | 6283 | fprintf_filtered (file, " flt: "); |
1adad886 | 6284 | if (inv1) |
e11c53d2 | 6285 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 6286 | else |
e11c53d2 | 6287 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6288 | |
e11c53d2 | 6289 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6290 | if (inv2) |
e11c53d2 | 6291 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 6292 | else |
e11c53d2 | 6293 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
6294 | } |
6295 | } | |
6296 | ||
6297 | static void | |
e11c53d2 | 6298 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 6299 | int regnum) |
f0ef6b29 | 6300 | { |
a4b8ebc8 | 6301 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6302 | struct value_print_options opts; |
de15c4ab | 6303 | struct value *val; |
1adad886 | 6304 | |
004159a2 | 6305 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6306 | { |
e11c53d2 | 6307 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6308 | return; |
6309 | } | |
6310 | ||
de15c4ab | 6311 | val = get_frame_register_value (frame, regnum); |
f0ef6b29 | 6312 | |
72a155b4 | 6313 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6314 | |
6315 | /* The problem with printing numeric register names (r26, etc.) is that | |
6316 | the user can't use them on input. Probably the best solution is to | |
6317 | fix it so that either the numeric or the funky (a2, etc.) names | |
6318 | are accepted on input. */ | |
6319 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 6320 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 6321 | else |
e11c53d2 | 6322 | fprintf_filtered (file, ": "); |
f0ef6b29 | 6323 | |
79a45b7d | 6324 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
6325 | val_print_scalar_formatted (value_type (val), |
6326 | value_contents_for_printing (val), | |
6327 | value_embedded_offset (val), | |
6328 | val, | |
6329 | &opts, 0, file); | |
c906108c SS |
6330 | } |
6331 | ||
f0ef6b29 KB |
6332 | /* Replacement for generic do_registers_info. |
6333 | Print regs in pretty columns. */ | |
6334 | ||
6335 | static int | |
e11c53d2 AC |
6336 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
6337 | int regnum) | |
f0ef6b29 | 6338 | { |
e11c53d2 AC |
6339 | fprintf_filtered (file, " "); |
6340 | mips_print_fp_register (file, frame, regnum); | |
6341 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
6342 | return regnum + 1; |
6343 | } | |
6344 | ||
6345 | ||
025bb325 | 6346 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6347 | |
6348 | static int | |
e11c53d2 | 6349 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 6350 | int start_regnum) |
c906108c | 6351 | { |
a4b8ebc8 | 6352 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6353 | /* Do values for GP (int) regs. */ |
47a35522 | 6354 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
6355 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6356 | per row. */ | |
c906108c | 6357 | int col, byte; |
a4b8ebc8 | 6358 | int regnum; |
c906108c | 6359 | |
025bb325 | 6360 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6361 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6362 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6363 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6364 | regnum++) |
c906108c | 6365 | { |
72a155b4 | 6366 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6367 | continue; /* unused register */ |
004159a2 | 6368 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6369 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6370 | /* Large registers are handled separately. */ |
72a155b4 | 6371 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6372 | { |
6373 | if (col > 0) | |
6374 | break; /* End the row before this register. */ | |
6375 | ||
6376 | /* Print this register on a row by itself. */ | |
6377 | mips_print_register (file, frame, regnum); | |
6378 | fprintf_filtered (file, "\n"); | |
6379 | return regnum + 1; | |
6380 | } | |
d05f6826 DJ |
6381 | if (col == 0) |
6382 | fprintf_filtered (file, " "); | |
6d82d43b | 6383 | fprintf_filtered (file, |
72a155b4 UW |
6384 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
6385 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6386 | col++; |
6387 | } | |
d05f6826 DJ |
6388 | |
6389 | if (col == 0) | |
6390 | return regnum; | |
6391 | ||
025bb325 | 6392 | /* Print the R0 to R31 names. */ |
72a155b4 | 6393 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 6394 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 6395 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
6396 | else |
6397 | fprintf_filtered (file, "\n "); | |
c906108c | 6398 | |
025bb325 | 6399 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6400 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6401 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6402 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6403 | regnum++) |
c906108c | 6404 | { |
72a155b4 | 6405 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6406 | continue; /* unused register */ |
004159a2 | 6407 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6408 | break; /* End row: reached FP register. */ |
72a155b4 | 6409 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6410 | break; /* End row: large register. */ |
6411 | ||
c906108c | 6412 | /* OK: get the data in raw format. */ |
ca9d61b9 | 6413 | if (!deprecated_frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 6414 | error (_("can't read register %d (%s)"), |
72a155b4 | 6415 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 6416 | /* pad small registers */ |
4246e332 | 6417 | for (byte = 0; |
72a155b4 UW |
6418 | byte < (mips_abi_regsize (gdbarch) |
6419 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 6420 | printf_filtered (" "); |
025bb325 | 6421 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6422 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6423 | for (byte = |
72a155b4 UW |
6424 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6425 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 6426 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 6427 | else |
72a155b4 | 6428 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6429 | byte >= 0; byte--) |
47a35522 | 6430 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 6431 | fprintf_filtered (file, " "); |
c906108c SS |
6432 | col++; |
6433 | } | |
025bb325 | 6434 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 6435 | fprintf_filtered (file, "\n"); |
c906108c SS |
6436 | |
6437 | return regnum; | |
6438 | } | |
6439 | ||
025bb325 | 6440 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6441 | |
bf1f5b4c | 6442 | static void |
e11c53d2 AC |
6443 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
6444 | struct frame_info *frame, int regnum, int all) | |
c906108c | 6445 | { |
025bb325 | 6446 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6447 | { |
72a155b4 UW |
6448 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6449 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6450 | error (_("Not a valid register for the current processor type")); |
c906108c | 6451 | |
0cc93a06 | 6452 | mips_print_register (file, frame, regnum); |
e11c53d2 | 6453 | fprintf_filtered (file, "\n"); |
c906108c | 6454 | } |
c5aa993b | 6455 | else |
025bb325 | 6456 | /* Do all (or most) registers. */ |
c906108c | 6457 | { |
72a155b4 UW |
6458 | regnum = gdbarch_num_regs (gdbarch); |
6459 | while (regnum < gdbarch_num_regs (gdbarch) | |
6460 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 6461 | { |
004159a2 | 6462 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6463 | { |
025bb325 | 6464 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6465 | regnum = print_fp_register_row (file, frame, regnum); |
6466 | else | |
025bb325 | 6467 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6468 | } |
c906108c | 6469 | else |
e11c53d2 | 6470 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6471 | } |
6472 | } | |
6473 | } | |
6474 | ||
63807e1d | 6475 | static int |
3352ef37 AC |
6476 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
6477 | struct frame_info *frame) | |
c906108c | 6478 | { |
e17a4113 | 6479 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 6480 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6481 | struct address_space *aspace; |
6482 | enum mips_isa isa; | |
6483 | ULONGEST insn; | |
6484 | int status; | |
6485 | int size; | |
6486 | ||
6487 | if ((mips_pc_is_mips (pc) | |
ab50adb6 | 6488 | && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) |
4cc0665f | 6489 | || (mips_pc_is_micromips (gdbarch, pc) |
ab50adb6 | 6490 | && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) |
4cc0665f | 6491 | || (mips_pc_is_mips16 (gdbarch, pc) |
ab50adb6 | 6492 | && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) |
06648491 MK |
6493 | return 0; |
6494 | ||
4cc0665f MR |
6495 | isa = mips_pc_isa (gdbarch, pc); |
6496 | /* _has_delay_slot above will have validated the read. */ | |
6497 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6498 | size = mips_insn_size (isa, insn); | |
6499 | aspace = get_frame_address_space (frame); | |
6500 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; | |
c906108c SS |
6501 | } |
6502 | ||
6d82d43b AC |
6503 | /* To skip prologues, I use this predicate. Returns either PC itself |
6504 | if the code at PC does not look like a function prologue; otherwise | |
6505 | returns an address that (if we're lucky) follows the prologue. If | |
6506 | LENIENT, then we must skip everything which is involved in setting | |
6507 | up the frame (it's OK to skip more, just so long as we don't skip | |
6508 | anything which might clobber the registers which are being saved. | |
6509 | We must skip more in the case where part of the prologue is in the | |
6510 | delay slot of a non-prologue instruction). */ | |
6511 | ||
6512 | static CORE_ADDR | |
6093d2eb | 6513 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6514 | { |
8b622e6a AC |
6515 | CORE_ADDR limit_pc; |
6516 | CORE_ADDR func_addr; | |
6517 | ||
6d82d43b AC |
6518 | /* See if we can determine the end of the prologue via the symbol table. |
6519 | If so, then return either PC, or the PC after the prologue, whichever | |
6520 | is greater. */ | |
8b622e6a AC |
6521 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6522 | { | |
d80b854b UW |
6523 | CORE_ADDR post_prologue_pc |
6524 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
6525 | if (post_prologue_pc != 0) |
6526 | return max (pc, post_prologue_pc); | |
6527 | } | |
6d82d43b AC |
6528 | |
6529 | /* Can't determine prologue from the symbol table, need to examine | |
6530 | instructions. */ | |
6531 | ||
98b4dd94 JB |
6532 | /* Find an upper limit on the function prologue using the debug |
6533 | information. If the debug information could not be used to provide | |
6534 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6535 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6536 | if (limit_pc == 0) |
6537 | limit_pc = pc + 100; /* Magic. */ | |
6538 | ||
4cc0665f | 6539 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6540 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6541 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6542 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6543 | else |
e17a4113 | 6544 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6545 | } |
6546 | ||
97ab0fdd MR |
6547 | /* Check whether the PC is in a function epilogue (32-bit version). |
6548 | This is a helper function for mips_in_function_epilogue_p. */ | |
6549 | static int | |
e17a4113 | 6550 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6551 | { |
6552 | CORE_ADDR func_addr = 0, func_end = 0; | |
6553 | ||
6554 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6555 | { | |
6556 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6557 | CORE_ADDR addr = func_end - 12; | |
6558 | ||
6559 | if (addr < func_addr + 4) | |
6560 | addr = func_addr + 4; | |
6561 | if (pc < addr) | |
6562 | return 0; | |
6563 | ||
6564 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6565 | { | |
6566 | unsigned long high_word; | |
6567 | unsigned long inst; | |
6568 | ||
4cc0665f | 6569 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6570 | high_word = (inst >> 16) & 0xffff; |
6571 | ||
6572 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6573 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6574 | && inst != 0x03e00008 /* jr $ra */ | |
6575 | && inst != 0x00000000) /* nop */ | |
6576 | return 0; | |
6577 | } | |
6578 | ||
6579 | return 1; | |
6580 | } | |
6581 | ||
6582 | return 0; | |
6583 | } | |
6584 | ||
4cc0665f MR |
6585 | /* Check whether the PC is in a function epilogue (microMIPS version). |
6586 | This is a helper function for mips_in_function_epilogue_p. */ | |
6587 | ||
6588 | static int | |
6589 | micromips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6590 | { | |
6591 | CORE_ADDR func_addr = 0; | |
6592 | CORE_ADDR func_end = 0; | |
6593 | CORE_ADDR addr; | |
6594 | ULONGEST insn; | |
6595 | long offset; | |
6596 | int dreg; | |
6597 | int sreg; | |
6598 | int loc; | |
6599 | ||
6600 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6601 | return 0; | |
6602 | ||
6603 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6604 | addr = func_end - 12; | |
6605 | ||
6606 | if (addr < func_addr + 2) | |
6607 | addr = func_addr + 2; | |
6608 | if (pc < addr) | |
6609 | return 0; | |
6610 | ||
6611 | for (; pc < func_end; pc += loc) | |
6612 | { | |
6613 | loc = 0; | |
6614 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6615 | loc += MIPS_INSN16_SIZE; | |
6616 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6617 | { | |
6618 | /* 48-bit instructions. */ | |
6619 | case 3 * MIPS_INSN16_SIZE: | |
6620 | /* No epilogue instructions in this category. */ | |
6621 | return 0; | |
6622 | ||
6623 | /* 32-bit instructions. */ | |
6624 | case 2 * MIPS_INSN16_SIZE: | |
6625 | insn <<= 16; | |
6626 | insn |= mips_fetch_instruction (gdbarch, | |
6627 | ISA_MICROMIPS, pc + loc, NULL); | |
6628 | loc += MIPS_INSN16_SIZE; | |
6629 | switch (micromips_op (insn >> 16)) | |
6630 | { | |
6631 | case 0xc: /* ADDIU: bits 001100 */ | |
6632 | case 0x17: /* DADDIU: bits 010111 */ | |
6633 | sreg = b0s5_reg (insn >> 16); | |
6634 | dreg = b5s5_reg (insn >> 16); | |
6635 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6636 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6637 | /* (D)ADDIU $sp, imm */ | |
6638 | && offset >= 0) | |
6639 | break; | |
6640 | return 0; | |
6641 | ||
6642 | default: | |
6643 | return 0; | |
6644 | } | |
6645 | break; | |
6646 | ||
6647 | /* 16-bit instructions. */ | |
6648 | case MIPS_INSN16_SIZE: | |
6649 | switch (micromips_op (insn)) | |
6650 | { | |
6651 | case 0x3: /* MOVE: bits 000011 */ | |
6652 | sreg = b0s5_reg (insn); | |
6653 | dreg = b5s5_reg (insn); | |
6654 | if (sreg == 0 && dreg == 0) | |
6655 | /* MOVE $zero, $zero aka NOP */ | |
6656 | break; | |
6657 | return 0; | |
6658 | ||
6659 | case 0x11: /* POOL16C: bits 010001 */ | |
6660 | if (b5s5_op (insn) == 0x18 | |
6661 | /* JRADDIUSP: bits 010011 11000 */ | |
6662 | || (b5s5_op (insn) == 0xd | |
6663 | /* JRC: bits 010011 01101 */ | |
6664 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6665 | /* JRC $ra */ | |
6666 | break; | |
6667 | return 0; | |
6668 | ||
6669 | case 0x13: /* POOL16D: bits 010011 */ | |
6670 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6671 | if ((insn & 0x1) == 0x1 | |
6672 | /* ADDIUSP: bits 010011 1 */ | |
6673 | && offset > 0) | |
6674 | break; | |
6675 | return 0; | |
6676 | ||
6677 | default: | |
6678 | return 0; | |
6679 | } | |
6680 | } | |
6681 | } | |
6682 | ||
6683 | return 1; | |
6684 | } | |
6685 | ||
97ab0fdd MR |
6686 | /* Check whether the PC is in a function epilogue (16-bit version). |
6687 | This is a helper function for mips_in_function_epilogue_p. */ | |
6688 | static int | |
e17a4113 | 6689 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6690 | { |
6691 | CORE_ADDR func_addr = 0, func_end = 0; | |
6692 | ||
6693 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6694 | { | |
6695 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6696 | CORE_ADDR addr = func_end - 12; | |
6697 | ||
6698 | if (addr < func_addr + 4) | |
6699 | addr = func_addr + 4; | |
6700 | if (pc < addr) | |
6701 | return 0; | |
6702 | ||
6703 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6704 | { | |
6705 | unsigned short inst; | |
6706 | ||
4cc0665f | 6707 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6708 | |
6709 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6710 | continue; | |
6711 | ||
6712 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6713 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6714 | && inst != 0xe820 /* jr $ra */ | |
6715 | && inst != 0xe8a0 /* jrc $ra */ | |
6716 | && inst != 0x6500) /* nop */ | |
6717 | return 0; | |
6718 | } | |
6719 | ||
6720 | return 1; | |
6721 | } | |
6722 | ||
6723 | return 0; | |
6724 | } | |
6725 | ||
6726 | /* The epilogue is defined here as the area at the end of a function, | |
6727 | after an instruction which destroys the function's stack frame. */ | |
6728 | static int | |
6729 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6730 | { | |
4cc0665f | 6731 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6732 | return mips16_in_function_epilogue_p (gdbarch, pc); |
4cc0665f MR |
6733 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6734 | return micromips_in_function_epilogue_p (gdbarch, pc); | |
97ab0fdd | 6735 | else |
e17a4113 | 6736 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
6737 | } |
6738 | ||
025bb325 | 6739 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
6740 | used for all MIPS-specific commands. */ |
6741 | ||
a5ea2558 | 6742 | static void |
acdb74a0 | 6743 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
6744 | { |
6745 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
6746 | } | |
6747 | ||
a5ea2558 | 6748 | static void |
acdb74a0 | 6749 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 6750 | { |
6d82d43b AC |
6751 | printf_unfiltered |
6752 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
6753 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
6754 | } | |
6755 | ||
c906108c SS |
6756 | /* Commands to show/set the MIPS FPU type. */ |
6757 | ||
c906108c | 6758 | static void |
acdb74a0 | 6759 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 6760 | { |
c906108c | 6761 | char *fpu; |
6ca0852e | 6762 | |
f5656ead | 6763 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
6ca0852e UW |
6764 | { |
6765 | printf_unfiltered | |
6766 | ("The MIPS floating-point coprocessor is unknown " | |
6767 | "because the current architecture is not MIPS.\n"); | |
6768 | return; | |
6769 | } | |
6770 | ||
f5656ead | 6771 | switch (MIPS_FPU_TYPE (target_gdbarch ())) |
c906108c SS |
6772 | { |
6773 | case MIPS_FPU_SINGLE: | |
6774 | fpu = "single-precision"; | |
6775 | break; | |
6776 | case MIPS_FPU_DOUBLE: | |
6777 | fpu = "double-precision"; | |
6778 | break; | |
6779 | case MIPS_FPU_NONE: | |
6780 | fpu = "absent (none)"; | |
6781 | break; | |
93d56215 | 6782 | default: |
e2e0b3e5 | 6783 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
6784 | } |
6785 | if (mips_fpu_type_auto) | |
025bb325 MS |
6786 | printf_unfiltered ("The MIPS floating-point coprocessor " |
6787 | "is set automatically (currently %s)\n", | |
6788 | fpu); | |
c906108c | 6789 | else |
6d82d43b AC |
6790 | printf_unfiltered |
6791 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
6792 | } |
6793 | ||
6794 | ||
c906108c | 6795 | static void |
acdb74a0 | 6796 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 6797 | { |
025bb325 MS |
6798 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
6799 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
6800 | show_mipsfpu_command (args, from_tty); |
6801 | } | |
6802 | ||
c906108c | 6803 | static void |
acdb74a0 | 6804 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 6805 | { |
8d5838b5 AC |
6806 | struct gdbarch_info info; |
6807 | gdbarch_info_init (&info); | |
c906108c SS |
6808 | mips_fpu_type = MIPS_FPU_SINGLE; |
6809 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6810 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6811 | instead of relying on globals. Doing that would let generic code | |
6812 | handle the search for this specific architecture. */ | |
6813 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6814 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6815 | } |
6816 | ||
c906108c | 6817 | static void |
acdb74a0 | 6818 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 6819 | { |
8d5838b5 AC |
6820 | struct gdbarch_info info; |
6821 | gdbarch_info_init (&info); | |
c906108c SS |
6822 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6823 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6824 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6825 | instead of relying on globals. Doing that would let generic code | |
6826 | handle the search for this specific architecture. */ | |
6827 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6828 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6829 | } |
6830 | ||
c906108c | 6831 | static void |
acdb74a0 | 6832 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 6833 | { |
8d5838b5 AC |
6834 | struct gdbarch_info info; |
6835 | gdbarch_info_init (&info); | |
c906108c SS |
6836 | mips_fpu_type = MIPS_FPU_NONE; |
6837 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6838 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6839 | instead of relying on globals. Doing that would let generic code | |
6840 | handle the search for this specific architecture. */ | |
6841 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6842 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6843 | } |
6844 | ||
c906108c | 6845 | static void |
acdb74a0 | 6846 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
6847 | { |
6848 | mips_fpu_type_auto = 1; | |
6849 | } | |
6850 | ||
c906108c | 6851 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
6852 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
6853 | the relevant processor still exists (it dates back to '94) and | |
6854 | secondly this is not the way to do this. The processor type should | |
6855 | be set by forcing an architecture change. */ | |
c906108c | 6856 | |
691c0433 AC |
6857 | void |
6858 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 6859 | { |
bb486190 UW |
6860 | struct regcache *regcache = get_current_regcache (); |
6861 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
6862 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 6863 | ULONGEST prid; |
c906108c | 6864 | |
bb486190 | 6865 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 6866 | if ((prid & ~0xf) == 0x700) |
691c0433 | 6867 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
6868 | } |
6869 | ||
6870 | /* Just like reinit_frame_cache, but with the right arguments to be | |
6871 | callable as an sfunc. */ | |
6872 | ||
6873 | static void | |
acdb74a0 AC |
6874 | reinit_frame_cache_sfunc (char *args, int from_tty, |
6875 | struct cmd_list_element *c) | |
c906108c SS |
6876 | { |
6877 | reinit_frame_cache (); | |
6878 | } | |
6879 | ||
a89aa300 AC |
6880 | static int |
6881 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 6882 | { |
4cc0665f MR |
6883 | struct gdbarch *gdbarch = info->application_data; |
6884 | ||
d31431ed AC |
6885 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
6886 | disassembler needs to be able to locally determine the ISA, and | |
6887 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
6888 | work. */ | |
4cc0665f | 6889 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 6890 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
6891 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
6892 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
6893 | |
6894 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
6895 | memaddr &= (info->mach == bfd_mach_mips16 |
6896 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 6897 | |
e5ab0dce | 6898 | /* Set the disassembler options. */ |
9dae60cc | 6899 | if (!info->disassembler_options) |
e5ab0dce AC |
6900 | /* This string is not recognized explicitly by the disassembler, |
6901 | but it tells the disassembler to not try to guess the ABI from | |
6902 | the bfd elf headers, such that, if the user overrides the ABI | |
6903 | of a program linked as NewABI, the disassembly will follow the | |
6904 | register naming conventions specified by the user. */ | |
6905 | info->disassembler_options = "gpr-names=32"; | |
6906 | ||
c906108c | 6907 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 6908 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
6909 | return print_insn_big_mips (memaddr, info); |
6910 | else | |
6911 | return print_insn_little_mips (memaddr, info); | |
6912 | } | |
6913 | ||
9dae60cc UW |
6914 | static int |
6915 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
6916 | { | |
6917 | /* Set up the disassembler info, so that we get the right | |
6918 | register names from libopcodes. */ | |
6919 | info->disassembler_options = "gpr-names=n32"; | |
6920 | info->flavour = bfd_target_elf_flavour; | |
6921 | ||
6922 | return gdb_print_insn_mips (memaddr, info); | |
6923 | } | |
6924 | ||
6925 | static int | |
6926 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
6927 | { | |
6928 | /* Set up the disassembler info, so that we get the right | |
6929 | register names from libopcodes. */ | |
6930 | info->disassembler_options = "gpr-names=64"; | |
6931 | info->flavour = bfd_target_elf_flavour; | |
6932 | ||
6933 | return gdb_print_insn_mips (memaddr, info); | |
6934 | } | |
6935 | ||
025bb325 MS |
6936 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
6937 | program counter value to determine whether a 16- or 32-bit breakpoint | |
6938 | should be used. It returns a pointer to a string of bytes that encode a | |
6939 | breakpoint instruction, stores the length of the string to *lenptr, and | |
6940 | adjusts pc (if necessary) to point to the actual memory location where | |
6941 | the breakpoint should be inserted. */ | |
c906108c | 6942 | |
47a35522 | 6943 | static const gdb_byte * |
025bb325 MS |
6944 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
6945 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 6946 | { |
4cc0665f MR |
6947 | CORE_ADDR pc = *pcptr; |
6948 | ||
67d57894 | 6949 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 6950 | { |
4cc0665f | 6951 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 6952 | { |
47a35522 | 6953 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
4cc0665f | 6954 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 6955 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
6956 | return mips16_big_breakpoint; |
6957 | } | |
4cc0665f MR |
6958 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6959 | { | |
6960 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
6961 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
6962 | ULONGEST insn; | |
6963 | int status; | |
6964 | int size; | |
6965 | ||
6966 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6967 | size = status ? 2 | |
6968 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6969 | *pcptr = unmake_compact_addr (pc); | |
6970 | *lenptr = size; | |
6971 | return (size == 2) ? micromips16_big_breakpoint | |
6972 | : micromips32_big_breakpoint; | |
6973 | } | |
c906108c SS |
6974 | else |
6975 | { | |
aaab4dba AC |
6976 | /* The IDT board uses an unusual breakpoint value, and |
6977 | sometimes gets confused when it sees the usual MIPS | |
6978 | breakpoint instruction. */ | |
47a35522 MK |
6979 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
6980 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
6981 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 6982 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 6983 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 6984 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 6985 | |
c5aa993b | 6986 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
6987 | |
6988 | if (strcmp (target_shortname, "mips") == 0) | |
6989 | return idt_big_breakpoint; | |
6990 | else if (strcmp (target_shortname, "ddb") == 0 | |
6991 | || strcmp (target_shortname, "pmon") == 0 | |
6992 | || strcmp (target_shortname, "lsi") == 0) | |
6993 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
6994 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
6995 | return irix_big_breakpoint; | |
c906108c SS |
6996 | else |
6997 | return big_breakpoint; | |
6998 | } | |
6999 | } | |
7000 | else | |
7001 | { | |
4cc0665f | 7002 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 7003 | { |
47a35522 | 7004 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
4cc0665f | 7005 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 7006 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
7007 | return mips16_little_breakpoint; |
7008 | } | |
4cc0665f MR |
7009 | else if (mips_pc_is_micromips (gdbarch, pc)) |
7010 | { | |
7011 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
7012 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
7013 | ULONGEST insn; | |
7014 | int status; | |
7015 | int size; | |
7016 | ||
7017 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
7018 | size = status ? 2 | |
7019 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
7020 | *pcptr = unmake_compact_addr (pc); | |
7021 | *lenptr = size; | |
7022 | return (size == 2) ? micromips16_little_breakpoint | |
7023 | : micromips32_little_breakpoint; | |
7024 | } | |
c906108c SS |
7025 | else |
7026 | { | |
47a35522 MK |
7027 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
7028 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
7029 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 7030 | |
c5aa993b | 7031 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
7032 | |
7033 | if (strcmp (target_shortname, "mips") == 0) | |
7034 | return idt_little_breakpoint; | |
7035 | else if (strcmp (target_shortname, "ddb") == 0 | |
7036 | || strcmp (target_shortname, "pmon") == 0 | |
7037 | || strcmp (target_shortname, "lsi") == 0) | |
7038 | return pmon_little_breakpoint; | |
7039 | else | |
7040 | return little_breakpoint; | |
7041 | } | |
7042 | } | |
7043 | } | |
7044 | ||
4cc0665f MR |
7045 | /* Determine the remote breakpoint kind suitable for the PC. The following |
7046 | kinds are used: | |
7047 | ||
7048 | * 2 -- 16-bit MIPS16 mode breakpoint, | |
7049 | ||
7050 | * 3 -- 16-bit microMIPS mode breakpoint, | |
7051 | ||
7052 | * 4 -- 32-bit standard MIPS mode breakpoint, | |
7053 | ||
7054 | * 5 -- 32-bit microMIPS mode breakpoint. */ | |
7055 | ||
7056 | static void | |
7057 | mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
7058 | int *kindptr) | |
7059 | { | |
7060 | CORE_ADDR pc = *pcptr; | |
7061 | ||
7062 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
7063 | { | |
7064 | *pcptr = unmake_compact_addr (pc); | |
7065 | *kindptr = 2; | |
7066 | } | |
7067 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
7068 | { | |
7069 | ULONGEST insn; | |
7070 | int status; | |
7071 | int size; | |
7072 | ||
7073 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
7074 | size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
7075 | *pcptr = unmake_compact_addr (pc); | |
7076 | *kindptr = size | 1; | |
7077 | } | |
7078 | else | |
7079 | *kindptr = 4; | |
7080 | } | |
7081 | ||
ab50adb6 MR |
7082 | /* Return non-zero if the standard MIPS instruction INST has a branch |
7083 | delay slot (i.e. it is a jump or branch instruction). This function | |
7084 | is based on mips32_next_pc. */ | |
c8cef75f MR |
7085 | |
7086 | static int | |
ab50adb6 | 7087 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) |
c8cef75f | 7088 | { |
c8cef75f | 7089 | int op; |
a385295e MR |
7090 | int rs; |
7091 | int rt; | |
c8cef75f | 7092 | |
c8cef75f MR |
7093 | op = itype_op (inst); |
7094 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
7095 | { |
7096 | rs = itype_rs (inst); | |
7097 | rt = itype_rt (inst); | |
f94363d7 AP |
7098 | return (is_octeon_bbit_op (op, gdbarch) |
7099 | || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
a385295e MR |
7100 | || op == 29 /* JALX: bits 011101 */ |
7101 | || (op == 17 | |
7102 | && (rs == 8 | |
c8cef75f | 7103 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
7104 | || (rs == 9 && (rt & 0x2) == 0) |
7105 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
7106 | || (rs == 10 && (rt & 0x2) == 0)))); | |
7107 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
7108 | } | |
c8cef75f MR |
7109 | else |
7110 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
7111 | { | |
7112 | case 0: /* SPECIAL */ | |
7113 | op = rtype_funct (inst); | |
7114 | return (op == 8 /* JR */ | |
7115 | || op == 9); /* JALR */ | |
7116 | break; /* end SPECIAL */ | |
7117 | case 1: /* REGIMM */ | |
a385295e MR |
7118 | rs = itype_rs (inst); |
7119 | rt = itype_rt (inst); /* branch condition */ | |
7120 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
7121 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
7122 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
7123 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
7124 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
7125 | break; /* end REGIMM */ |
7126 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
7127 | return 1; | |
7128 | break; | |
7129 | } | |
7130 | } | |
7131 | ||
ab50adb6 MR |
7132 | /* Return non-zero if a standard MIPS instruction at ADDR has a branch |
7133 | delay slot (i.e. it is a jump or branch instruction). */ | |
c8cef75f | 7134 | |
4cc0665f | 7135 | static int |
ab50adb6 | 7136 | mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) |
4cc0665f MR |
7137 | { |
7138 | ULONGEST insn; | |
7139 | int status; | |
7140 | ||
ab50adb6 | 7141 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
4cc0665f MR |
7142 | if (status) |
7143 | return 0; | |
7144 | ||
ab50adb6 MR |
7145 | return mips32_instruction_has_delay_slot (gdbarch, insn); |
7146 | } | |
4cc0665f | 7147 | |
ab50adb6 MR |
7148 | /* Return non-zero if the microMIPS instruction INSN, comprising the |
7149 | 16-bit major opcode word in the high 16 bits and any second word | |
7150 | in the low 16 bits, has a branch delay slot (i.e. it is a non-compact | |
7151 | jump or branch instruction). The instruction must be 32-bit if | |
7152 | MUSTBE32 is set or can be any instruction otherwise. */ | |
7153 | ||
7154 | static int | |
7155 | micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) | |
7156 | { | |
7157 | ULONGEST major = insn >> 16; | |
4cc0665f | 7158 | |
ab50adb6 MR |
7159 | switch (micromips_op (major)) |
7160 | { | |
7161 | /* 16-bit instructions. */ | |
7162 | case 0x33: /* B16: bits 110011 */ | |
7163 | case 0x2b: /* BNEZ16: bits 101011 */ | |
7164 | case 0x23: /* BEQZ16: bits 100011 */ | |
7165 | return !mustbe32; | |
7166 | case 0x11: /* POOL16C: bits 010001 */ | |
7167 | return (!mustbe32 | |
7168 | && ((b5s5_op (major) == 0xc | |
7169 | /* JR16: bits 010001 01100 */ | |
7170 | || (b5s5_op (major) & 0x1e) == 0xe))); | |
7171 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7172 | /* 32-bit instructions. */ | |
7173 | case 0x3d: /* JAL: bits 111101 */ | |
7174 | case 0x3c: /* JALX: bits 111100 */ | |
7175 | case 0x35: /* J: bits 110101 */ | |
7176 | case 0x2d: /* BNE: bits 101101 */ | |
7177 | case 0x25: /* BEQ: bits 100101 */ | |
7178 | case 0x1d: /* JALS: bits 011101 */ | |
7179 | return 1; | |
7180 | case 0x10: /* POOL32I: bits 010000 */ | |
7181 | return ((b5s5_op (major) & 0x1c) == 0x0 | |
4cc0665f | 7182 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
ab50adb6 | 7183 | || (b5s5_op (major) & 0x1d) == 0x4 |
4cc0665f | 7184 | /* BLEZ, BGTZ: bits 010000 001x0 */ |
ab50adb6 | 7185 | || (b5s5_op (major) & 0x1d) == 0x11 |
4cc0665f | 7186 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
ab50adb6 MR |
7187 | || ((b5s5_op (major) & 0x1e) == 0x14 |
7188 | && (major & 0x3) == 0x0) | |
4cc0665f | 7189 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
ab50adb6 | 7190 | || (b5s5_op (major) & 0x1e) == 0x1a |
4cc0665f | 7191 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
ab50adb6 MR |
7192 | || ((b5s5_op (major) & 0x1e) == 0x1c |
7193 | && (major & 0x3) == 0x0) | |
4cc0665f | 7194 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
ab50adb6 MR |
7195 | || ((b5s5_op (major) & 0x1c) == 0x1c |
7196 | && (major & 0x3) == 0x1)); | |
4cc0665f | 7197 | /* BC1ANY*: bits 010000 111xx xxx01 */ |
ab50adb6 MR |
7198 | case 0x0: /* POOL32A: bits 000000 */ |
7199 | return (b0s6_op (insn) == 0x3c | |
7200 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7201 | && (b6s10_ext (insn) & 0x2bf) == 0x3c); | |
7202 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7203 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7204 | default: | |
7205 | return 0; | |
7206 | } | |
4cc0665f MR |
7207 | } |
7208 | ||
ab50adb6 | 7209 | /* Return non-zero if a microMIPS instruction at ADDR has a branch delay |
ae790652 MR |
7210 | slot (i.e. it is a non-compact jump instruction). The instruction |
7211 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7212 | ||
c8cef75f | 7213 | static int |
ab50adb6 MR |
7214 | micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
7215 | CORE_ADDR addr, int mustbe32) | |
c8cef75f | 7216 | { |
ab50adb6 | 7217 | ULONGEST insn; |
c8cef75f MR |
7218 | int status; |
7219 | ||
ab50adb6 | 7220 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
c8cef75f MR |
7221 | if (status) |
7222 | return 0; | |
ab50adb6 MR |
7223 | insn <<= 16; |
7224 | if (mips_insn_size (ISA_MICROMIPS, insn) == 2 * MIPS_INSN16_SIZE) | |
7225 | { | |
7226 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7227 | if (status) | |
7228 | return 0; | |
7229 | } | |
7230 | ||
7231 | return micromips_instruction_has_delay_slot (insn, mustbe32); | |
7232 | } | |
c8cef75f | 7233 | |
ab50adb6 MR |
7234 | /* Return non-zero if the MIPS16 instruction INST, which must be |
7235 | a 32-bit instruction if MUSTBE32 is set or can be any instruction | |
7236 | otherwise, has a branch delay slot (i.e. it is a non-compact jump | |
7237 | instruction). This function is based on mips16_next_pc. */ | |
7238 | ||
7239 | static int | |
7240 | mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) | |
7241 | { | |
ae790652 MR |
7242 | if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ |
7243 | return !mustbe32; | |
c8cef75f MR |
7244 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ |
7245 | } | |
7246 | ||
ab50adb6 MR |
7247 | /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay |
7248 | slot (i.e. it is a non-compact jump instruction). The instruction | |
7249 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7250 | ||
7251 | static int | |
7252 | mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
7253 | CORE_ADDR addr, int mustbe32) | |
7254 | { | |
7255 | unsigned short insn; | |
7256 | int status; | |
7257 | ||
7258 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); | |
7259 | if (status) | |
7260 | return 0; | |
7261 | ||
7262 | return mips16_instruction_has_delay_slot (insn, mustbe32); | |
7263 | } | |
7264 | ||
c8cef75f MR |
7265 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. |
7266 | This assumes KSSEG exists. */ | |
7267 | ||
7268 | static CORE_ADDR | |
7269 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7270 | { | |
7271 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7272 | int segsize; | |
7273 | ||
7274 | if (sizeof (CORE_ADDR) == 8) | |
7275 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7276 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7277 | though in that case this is dead code). */ | |
7278 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7279 | { | |
7280 | case 3: | |
7281 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7282 | segsize = 29; /* 32-bit compatibility segment */ | |
7283 | else | |
7284 | segsize = 62; /* xkseg */ | |
7285 | break; | |
7286 | case 2: /* xkphys */ | |
7287 | segsize = 59; | |
7288 | break; | |
7289 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7290 | segsize = 62; | |
7291 | break; | |
7292 | } | |
7293 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7294 | segsize = 29; | |
7295 | else | |
7296 | segsize = 31; /* user segment */ | |
7297 | mask <<= segsize; | |
7298 | return bpaddr & mask; | |
7299 | } | |
7300 | ||
7301 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7302 | it backwards if necessary. Return the address of the new location. */ | |
7303 | ||
7304 | static CORE_ADDR | |
7305 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7306 | { | |
22e048c9 | 7307 | CORE_ADDR prev_addr; |
c8cef75f MR |
7308 | CORE_ADDR boundary; |
7309 | CORE_ADDR func_addr; | |
7310 | ||
7311 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7312 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7313 | the instruction in the branch delay slot, the PC will point to | |
7314 | the branch instruction. Since the PC doesn't match any known | |
7315 | breakpoints, GDB reports a trap exception. | |
7316 | ||
7317 | There are two possible fixes for this problem. | |
7318 | ||
7319 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7320 | Cause register (which indicates the last exception occurred in a | |
7321 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7322 | the instruction in the branch delay slot. | |
7323 | ||
7324 | 2) When the user sets the breakpoint, don't allow him to set the | |
7325 | breakpoint on the instruction in the branch delay slot. Instead | |
7326 | move the breakpoint to the branch instruction (which will have | |
7327 | the same result). | |
7328 | ||
7329 | The problem with the first solution is that if the user then | |
7330 | single-steps the processor, the branch instruction will get | |
7331 | skipped (since GDB thinks the PC is on the instruction in the | |
7332 | branch delay slot). | |
7333 | ||
7334 | So, we'll use the second solution. To do this we need to know if | |
7335 | the instruction we're trying to set the breakpoint on is in the | |
7336 | branch delay slot. */ | |
7337 | ||
7338 | boundary = mips_segment_boundary (bpaddr); | |
7339 | ||
7340 | /* Make sure we don't scan back before the beginning of the current | |
7341 | function, since we may fetch constant data or insns that look like | |
7342 | a jump. Of course we might do that anyway if the compiler has | |
7343 | moved constants inline. :-( */ | |
7344 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7345 | && func_addr > boundary && func_addr <= bpaddr) | |
7346 | boundary = func_addr; | |
7347 | ||
4cc0665f | 7348 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7349 | { |
7350 | if (bpaddr == boundary) | |
7351 | return bpaddr; | |
7352 | ||
7353 | /* If the previous instruction has a branch delay slot, we have | |
7354 | to move the breakpoint to the branch instruction. */ | |
7355 | prev_addr = bpaddr - 4; | |
ab50adb6 | 7356 | if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) |
c8cef75f MR |
7357 | bpaddr = prev_addr; |
7358 | } | |
7359 | else | |
7360 | { | |
ab50adb6 | 7361 | int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7362 | CORE_ADDR addr, jmpaddr; |
7363 | int i; | |
7364 | ||
4cc0665f | 7365 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7366 | |
7367 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
7368 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
7369 | so try for that first, then try the 2 byte JALR/JR. | |
4cc0665f MR |
7370 | The microMIPS ASE has a whole range of jumps and branches |
7371 | with delay slots, some of which take 4 bytes and some take | |
7372 | 2 bytes, so the idea is the same. | |
c8cef75f MR |
7373 | FIXME: We have to assume that bpaddr is not the second half |
7374 | of an extended instruction. */ | |
ab50adb6 MR |
7375 | insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7376 | ? micromips_insn_at_pc_has_delay_slot | |
7377 | : mips16_insn_at_pc_has_delay_slot); | |
c8cef75f MR |
7378 | |
7379 | jmpaddr = 0; | |
7380 | addr = bpaddr; | |
7381 | for (i = 1; i < 4; i++) | |
7382 | { | |
4cc0665f | 7383 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7384 | break; |
4cc0665f | 7385 | addr -= MIPS_INSN16_SIZE; |
ab50adb6 | 7386 | if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) |
c8cef75f MR |
7387 | /* Looks like a JR/JALR at [target-1], but it could be |
7388 | the second word of a previous JAL/JALX, so record it | |
7389 | and check back one more. */ | |
7390 | jmpaddr = addr; | |
ab50adb6 | 7391 | else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7392 | { |
7393 | if (i == 2) | |
7394 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7395 | be the second word of a previous JAL/JALX, record it, | |
7396 | and check back one more. */ | |
7397 | jmpaddr = addr; | |
7398 | else | |
7399 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7400 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7401 | ||
7402 | >-3: JAL | |
7403 | -2: JAL-ext (can't be JAL/JALX) | |
7404 | -1: bdslot (can't be JR/JALR) | |
7405 | 0: target insn | |
7406 | ||
7407 | Of course it could be another JAL-ext which looks | |
7408 | like a JAL, but in that case we'd have broken out | |
7409 | of this loop at [target-2]: | |
7410 | ||
7411 | -4: JAL | |
7412 | >-3: JAL-ext | |
7413 | -2: bdslot (can't be jmp) | |
7414 | -1: JR/JALR | |
7415 | 0: target insn */ | |
7416 | jmpaddr = 0; | |
7417 | } | |
7418 | else | |
7419 | { | |
7420 | /* Not a jump instruction: if we're at [target-1] this | |
7421 | could be the second word of a JAL/JALX, so continue; | |
7422 | otherwise we're done. */ | |
7423 | if (i > 1) | |
7424 | break; | |
7425 | } | |
7426 | } | |
7427 | ||
7428 | if (jmpaddr) | |
7429 | bpaddr = jmpaddr; | |
7430 | } | |
7431 | ||
7432 | return bpaddr; | |
7433 | } | |
7434 | ||
14132e89 MR |
7435 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7436 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7437 | ||
7438 | static int | |
7439 | mips_is_stub_suffix (const char *suffix, int zero) | |
7440 | { | |
7441 | switch (suffix[0]) | |
7442 | { | |
7443 | case '0': | |
7444 | return zero && suffix[1] == '\0'; | |
7445 | case '1': | |
7446 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7447 | case '2': | |
7448 | case '5': | |
7449 | case '6': | |
7450 | case '9': | |
7451 | return suffix[1] == '\0'; | |
7452 | default: | |
7453 | return 0; | |
7454 | } | |
7455 | } | |
7456 | ||
7457 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7458 | call stubs, one of sf, df, sc, or dc. */ | |
7459 | ||
7460 | static int | |
7461 | mips_is_stub_mode (const char *mode) | |
7462 | { | |
7463 | return ((mode[0] == 's' || mode[0] == 'd') | |
7464 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7465 | } | |
7466 | ||
7467 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7468 | bar might have a name like __fn_stub_bar, and might look like this: | |
7469 | ||
7470 | mfc1 $4, $f13 | |
7471 | mfc1 $5, $f12 | |
7472 | mfc1 $6, $f15 | |
7473 | mfc1 $7, $f14 | |
7474 | ||
7475 | followed by (or interspersed with): | |
7476 | ||
7477 | j bar | |
7478 | ||
7479 | or: | |
7480 | ||
7481 | lui $25, %hi(bar) | |
7482 | addiu $25, $25, %lo(bar) | |
7483 | jr $25 | |
7484 | ||
7485 | ($1 may be used in old code; for robustness we accept any register) | |
7486 | or, in PIC code: | |
7487 | ||
7488 | lui $28, %hi(_gp_disp) | |
7489 | addiu $28, $28, %lo(_gp_disp) | |
7490 | addu $28, $28, $25 | |
7491 | lw $25, %got(bar) | |
7492 | addiu $25, $25, %lo(bar) | |
7493 | jr $25 | |
7494 | ||
7495 | In the case of a __call_stub_bar stub, the sequence to set up | |
7496 | arguments might look like this: | |
7497 | ||
7498 | mtc1 $4, $f13 | |
7499 | mtc1 $5, $f12 | |
7500 | mtc1 $6, $f15 | |
7501 | mtc1 $7, $f14 | |
7502 | ||
7503 | followed by (or interspersed with) one of the jump sequences above. | |
7504 | ||
7505 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7506 | of J or JR, respectively, followed by: | |
7507 | ||
7508 | mfc1 $2, $f0 | |
7509 | mfc1 $3, $f1 | |
7510 | jr $18 | |
7511 | ||
7512 | We are at the beginning of the stub here, and scan down and extract | |
7513 | the target address from the jump immediate instruction or, if a jump | |
7514 | register instruction is used, from the register referred. Return | |
7515 | the value of PC calculated or 0 if inconclusive. | |
7516 | ||
7517 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7518 | ||
7519 | static CORE_ADDR | |
7520 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
7521 | { | |
7522 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7523 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7524 | int addrreg = MIPS_ZERO_REGNUM; | |
7525 | CORE_ADDR start_pc = pc; | |
7526 | CORE_ADDR target_pc = 0; | |
7527 | CORE_ADDR addr = 0; | |
7528 | CORE_ADDR gp = 0; | |
7529 | int status = 0; | |
7530 | int i; | |
7531 | ||
7532 | for (i = 0; | |
7533 | status == 0 && target_pc == 0 && i < 20; | |
7534 | i++, pc += MIPS_INSN32_SIZE) | |
7535 | { | |
4cc0665f | 7536 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7537 | CORE_ADDR imm; |
7538 | int rt; | |
7539 | int rs; | |
7540 | int rd; | |
7541 | ||
7542 | switch (itype_op (inst)) | |
7543 | { | |
7544 | case 0: /* SPECIAL */ | |
7545 | switch (rtype_funct (inst)) | |
7546 | { | |
7547 | case 8: /* JR */ | |
7548 | case 9: /* JALR */ | |
7549 | rs = rtype_rs (inst); | |
7550 | if (rs == MIPS_GP_REGNUM) | |
7551 | target_pc = gp; /* Hmm... */ | |
7552 | else if (rs == addrreg) | |
7553 | target_pc = addr; | |
7554 | break; | |
7555 | ||
7556 | case 0x21: /* ADDU */ | |
7557 | rt = rtype_rt (inst); | |
7558 | rs = rtype_rs (inst); | |
7559 | rd = rtype_rd (inst); | |
7560 | if (rd == MIPS_GP_REGNUM | |
7561 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7562 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7563 | gp += start_pc; | |
7564 | break; | |
7565 | } | |
7566 | break; | |
7567 | ||
7568 | case 2: /* J */ | |
7569 | case 3: /* JAL */ | |
7570 | target_pc = jtype_target (inst) << 2; | |
7571 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7572 | break; | |
7573 | ||
7574 | case 9: /* ADDIU */ | |
7575 | rt = itype_rt (inst); | |
7576 | rs = itype_rs (inst); | |
7577 | if (rt == rs) | |
7578 | { | |
7579 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7580 | if (rt == MIPS_GP_REGNUM) | |
7581 | gp += imm; | |
7582 | else if (rt == addrreg) | |
7583 | addr += imm; | |
7584 | } | |
7585 | break; | |
7586 | ||
7587 | case 0xf: /* LUI */ | |
7588 | rt = itype_rt (inst); | |
7589 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7590 | if (rt == MIPS_GP_REGNUM) | |
7591 | gp = imm; | |
7592 | else if (rt != MIPS_ZERO_REGNUM) | |
7593 | { | |
7594 | addrreg = rt; | |
7595 | addr = imm; | |
7596 | } | |
7597 | break; | |
7598 | ||
7599 | case 0x23: /* LW */ | |
7600 | rt = itype_rt (inst); | |
7601 | rs = itype_rs (inst); | |
7602 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7603 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7604 | { | |
7605 | gdb_byte buf[4]; | |
7606 | ||
7607 | memset (buf, 0, sizeof (buf)); | |
7608 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7609 | addrreg = rt; | |
7610 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7611 | } | |
7612 | break; | |
7613 | } | |
7614 | } | |
7615 | ||
7616 | return target_pc; | |
7617 | } | |
7618 | ||
7619 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7620 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7621 | cases which must be handled: |
7622 | ||
14132e89 MR |
7623 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7624 | and the target PC is in $31 ($ra). | |
c906108c | 7625 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7626 | and the target PC is in $2. |
7627 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7628 | i.e. before the JALR instruction, this is effectively a call stub | |
7629 | and the target PC is in $2. Otherwise this is effectively | |
7630 | a return stub and the target PC is in $18. | |
7631 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7632 | JAL or JALR instruction, this is effectively a call stub and the | |
7633 | target PC is buried in the instruction stream. Otherwise this | |
7634 | is effectively a return stub and the target PC is in $18. | |
7635 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7636 | stub and the target PC is buried in the instruction stream. | |
7637 | ||
7638 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7639 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7640 | gory details. */ |
c906108c | 7641 | |
757a7cc6 | 7642 | static CORE_ADDR |
db5f024e | 7643 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 7644 | { |
e17a4113 | 7645 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7646 | CORE_ADDR start_addr; |
14132e89 MR |
7647 | const char *name; |
7648 | size_t prefixlen; | |
c906108c SS |
7649 | |
7650 | /* Find the starting address and name of the function containing the PC. */ | |
7651 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7652 | return 0; | |
7653 | ||
14132e89 MR |
7654 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7655 | and the target PC is in $31 ($ra). */ | |
7656 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7657 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7658 | && mips_is_stub_mode (name + prefixlen) | |
7659 | && name[prefixlen + 2] == '\0') | |
7660 | return get_frame_register_signed | |
7661 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7662 | ||
7663 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7664 | call/return stubs. */ | |
7665 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7666 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7667 | { |
7668 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
7669 | and the target PC is in $2. */ | |
14132e89 MR |
7670 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7671 | return get_frame_register_signed | |
7672 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7673 | |
14132e89 MR |
7674 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
7675 | i.e. before the JALR instruction, this is effectively a call stub | |
b021a221 | 7676 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 7677 | a return stub and the target PC is in $18. */ |
14132e89 MR |
7678 | else if (mips_is_stub_mode (name + prefixlen) |
7679 | && name[prefixlen + 2] == '_' | |
7680 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7681 | { |
7682 | if (pc == start_addr) | |
14132e89 MR |
7683 | /* This is the 'call' part of a call stub. The return |
7684 | address is in $2. */ | |
7685 | return get_frame_register_signed | |
7686 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7687 | else |
7688 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7689 | address is in $18. */ |
7690 | return get_frame_register_signed | |
7691 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7692 | } |
14132e89 MR |
7693 | else |
7694 | return 0; /* Not a stub. */ | |
7695 | } | |
7696 | ||
7697 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7698 | compiler-generated call or call/return stubs. */ | |
7699 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0 | |
7700 | || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
7701 | { | |
7702 | if (pc == start_addr) | |
7703 | /* This is the 'call' part of a call stub. Call this helper | |
7704 | to scan through this code for interesting instructions | |
7705 | and determine the final PC. */ | |
7706 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7707 | else | |
7708 | /* This is the 'return' part of a call stub. The return address | |
7709 | is in $18. */ | |
7710 | return get_frame_register_signed | |
7711 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7712 | } |
14132e89 MR |
7713 | |
7714 | return 0; /* Not a stub. */ | |
7715 | } | |
7716 | ||
7717 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7718 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7719 | ||
7720 | static int | |
7721 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7722 | { | |
7723 | CORE_ADDR start_addr; | |
7724 | size_t prefixlen; | |
7725 | ||
7726 | /* Find the starting address of the function containing the PC. */ | |
7727 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7728 | return 0; | |
7729 | ||
7730 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7731 | the start, i.e. after the JALR instruction, this is effectively | |
7732 | a return stub. */ | |
7733 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7734 | if (pc != start_addr | |
7735 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7736 | && mips_is_stub_mode (name + prefixlen) | |
7737 | && name[prefixlen + 2] == '_' | |
7738 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7739 | return 1; | |
7740 | ||
7741 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7742 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7743 | prefixlen = strlen (mips_str_call_fp_stub); | |
7744 | if (pc != start_addr | |
7745 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7746 | return 1; | |
7747 | ||
7748 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7749 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7750 | or the call stub path will trigger in handle_inferior_event causing | |
7751 | it to go astray. */ | |
7752 | prefixlen = strlen (mips_str_pic); | |
7753 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7754 | name += prefixlen; | |
7755 | ||
7756 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7757 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7758 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7759 | && mips_is_stub_mode (name + prefixlen) | |
7760 | && name[prefixlen + 2] == '\0') | |
7761 | return 1; | |
7762 | ||
7763 | return 0; /* Not a stub. */ | |
c906108c SS |
7764 | } |
7765 | ||
db5f024e DJ |
7766 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7767 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7768 | so that $t9 has the correct value at function entry. */ | |
7769 | ||
7770 | static CORE_ADDR | |
7771 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7772 | { | |
e17a4113 UW |
7773 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7774 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7cbd4a93 | 7775 | struct bound_minimal_symbol msym; |
db5f024e DJ |
7776 | int i; |
7777 | gdb_byte stub_code[16]; | |
7778 | int32_t stub_words[4]; | |
7779 | ||
7780 | /* The stub for foo is named ".pic.foo", and is either two | |
7781 | instructions inserted before foo or a three instruction sequence | |
7782 | which jumps to foo. */ | |
7783 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 7784 | if (msym.minsym == NULL |
77e371c0 | 7785 | || BMSYMBOL_VALUE_ADDRESS (msym) != pc |
efd66ac6 TT |
7786 | || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL |
7787 | || strncmp (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.", 5) != 0) | |
db5f024e DJ |
7788 | return 0; |
7789 | ||
7790 | /* A two-instruction header. */ | |
7cbd4a93 | 7791 | if (MSYMBOL_SIZE (msym.minsym) == 8) |
db5f024e DJ |
7792 | return pc + 8; |
7793 | ||
7794 | /* A three-instruction (plus delay slot) trampoline. */ | |
7cbd4a93 | 7795 | if (MSYMBOL_SIZE (msym.minsym) == 16) |
db5f024e DJ |
7796 | { |
7797 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7798 | return 0; | |
7799 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7800 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7801 | 4, byte_order); | |
db5f024e DJ |
7802 | |
7803 | /* A stub contains these instructions: | |
7804 | lui t9, %hi(target) | |
7805 | j target | |
7806 | addiu t9, t9, %lo(target) | |
7807 | nop | |
7808 | ||
7809 | This works even for N64, since stubs are only generated with | |
7810 | -msym32. */ | |
7811 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7812 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7813 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7814 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7815 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7816 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7817 | } |
7818 | ||
7819 | /* Not a recognized stub. */ | |
7820 | return 0; | |
7821 | } | |
7822 | ||
7823 | static CORE_ADDR | |
7824 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7825 | { | |
14132e89 | 7826 | CORE_ADDR requested_pc = pc; |
db5f024e | 7827 | CORE_ADDR target_pc; |
14132e89 MR |
7828 | CORE_ADDR new_pc; |
7829 | ||
7830 | do | |
7831 | { | |
7832 | target_pc = pc; | |
db5f024e | 7833 | |
14132e89 MR |
7834 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7835 | if (new_pc) | |
7836 | { | |
7837 | pc = new_pc; | |
4cc0665f MR |
7838 | if (is_compact_addr (pc)) |
7839 | pc = unmake_compact_addr (pc); | |
14132e89 | 7840 | } |
db5f024e | 7841 | |
14132e89 MR |
7842 | new_pc = find_solib_trampoline_target (frame, pc); |
7843 | if (new_pc) | |
7844 | { | |
7845 | pc = new_pc; | |
4cc0665f MR |
7846 | if (is_compact_addr (pc)) |
7847 | pc = unmake_compact_addr (pc); | |
14132e89 | 7848 | } |
db5f024e | 7849 | |
14132e89 MR |
7850 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7851 | if (new_pc) | |
7852 | { | |
7853 | pc = new_pc; | |
4cc0665f MR |
7854 | if (is_compact_addr (pc)) |
7855 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
7856 | } |
7857 | } | |
7858 | while (pc != target_pc); | |
db5f024e | 7859 | |
14132e89 | 7860 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7861 | } |
7862 | ||
a4b8ebc8 | 7863 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7864 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7865 | |
7866 | static int | |
d3f73121 | 7867 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7868 | { |
a4b8ebc8 | 7869 | int regnum; |
2f38ef89 | 7870 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7871 | regnum = num; |
2f38ef89 | 7872 | else if (num >= 38 && num < 70) |
d3f73121 | 7873 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7874 | else if (num == 70) |
d3f73121 | 7875 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7876 | else if (num == 71) |
d3f73121 | 7877 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7878 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7879 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7880 | else |
a4b8ebc8 AC |
7881 | /* This will hopefully (eventually) provoke a warning. Should |
7882 | we be calling complaint() here? */ | |
d3f73121 MD |
7883 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7884 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
7885 | } |
7886 | ||
2f38ef89 | 7887 | |
a4b8ebc8 | 7888 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7889 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7890 | |
7891 | static int | |
d3f73121 | 7892 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7893 | { |
a4b8ebc8 | 7894 | int regnum; |
2f38ef89 | 7895 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7896 | regnum = num; |
2f38ef89 | 7897 | else if (num >= 32 && num < 64) |
d3f73121 | 7898 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7899 | else if (num == 64) |
d3f73121 | 7900 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7901 | else if (num == 65) |
d3f73121 | 7902 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7903 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7904 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7905 | else |
a4b8ebc8 AC |
7906 | /* This will hopefully (eventually) provoke a warning. Should we |
7907 | be calling complaint() here? */ | |
d3f73121 MD |
7908 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7909 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
7910 | } |
7911 | ||
7912 | static int | |
e7faf938 | 7913 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7914 | { |
7915 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7916 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7917 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7918 | decide if it is valid. Should instead define a standard sim/gdb | |
7919 | register numbering scheme. */ | |
e7faf938 MD |
7920 | if (gdbarch_register_name (gdbarch, |
7921 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
7922 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
7923 | gdbarch_num_regs (gdbarch) |
7924 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
7925 | return regnum; |
7926 | else | |
6d82d43b | 7927 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7928 | } |
7929 | ||
2f38ef89 | 7930 | |
4844f454 CV |
7931 | /* Convert an integer into an address. Extracting the value signed |
7932 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7933 | |
7934 | static CORE_ADDR | |
79dd2d24 | 7935 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7936 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7937 | { |
e17a4113 UW |
7938 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7939 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
7940 | } |
7941 | ||
82e91389 DJ |
7942 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7943 | than most other architectures; we just need to be explicit about it, | |
7944 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7945 | an assertion failure. */ | |
7946 | ||
7947 | static void | |
a54fba4c MD |
7948 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7949 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7950 | { |
7951 | *reg = MIPS_SP_REGNUM; | |
7952 | *offset = 0; | |
7953 | } | |
7954 | ||
caaa3122 DJ |
7955 | static void |
7956 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7957 | { | |
7958 | enum mips_abi *abip = (enum mips_abi *) obj; | |
7959 | const char *name = bfd_get_section_name (abfd, sect); | |
7960 | ||
7961 | if (*abip != MIPS_ABI_UNKNOWN) | |
7962 | return; | |
7963 | ||
7964 | if (strncmp (name, ".mdebug.", 8) != 0) | |
7965 | return; | |
7966 | ||
7967 | if (strcmp (name, ".mdebug.abi32") == 0) | |
7968 | *abip = MIPS_ABI_O32; | |
7969 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
7970 | *abip = MIPS_ABI_N32; | |
62a49b2c | 7971 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 7972 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
7973 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
7974 | *abip = MIPS_ABI_O64; | |
7975 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
7976 | *abip = MIPS_ABI_EABI32; | |
7977 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
7978 | *abip = MIPS_ABI_EABI64; | |
7979 | else | |
8a3fe4f8 | 7980 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
7981 | } |
7982 | ||
22e47e37 FF |
7983 | static void |
7984 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
7985 | { | |
7986 | int *lbp = (int *) obj; | |
7987 | const char *name = bfd_get_section_name (abfd, sect); | |
7988 | ||
7989 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
7990 | *lbp = 32; | |
7991 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
7992 | *lbp = 64; | |
7993 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
7994 | warning (_("unrecognized .gcc_compiled_longXX")); | |
7995 | } | |
7996 | ||
2e4ebe70 DJ |
7997 | static enum mips_abi |
7998 | global_mips_abi (void) | |
7999 | { | |
8000 | int i; | |
8001 | ||
8002 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
8003 | if (mips_abi_strings[i] == mips_abi_string) | |
8004 | return (enum mips_abi) i; | |
8005 | ||
e2e0b3e5 | 8006 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
8007 | } |
8008 | ||
4cc0665f MR |
8009 | /* Return the default compressed instruction set, either of MIPS16 |
8010 | or microMIPS, selected when none could have been determined from | |
8011 | the ELF header of the binary being executed (or no binary has been | |
8012 | selected. */ | |
8013 | ||
8014 | static enum mips_isa | |
8015 | global_mips_compression (void) | |
8016 | { | |
8017 | int i; | |
8018 | ||
8019 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
8020 | if (mips_compression_strings[i] == mips_compression_string) | |
8021 | return (enum mips_isa) i; | |
8022 | ||
8023 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); | |
8024 | } | |
8025 | ||
29709017 DJ |
8026 | static void |
8027 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8028 | { | |
29709017 DJ |
8029 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
8030 | assume that's what we've got. */ | |
4eb0ad19 DJ |
8031 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
8032 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8033 | |
8034 | /* If the size matches the full set of registers GDB traditionally | |
8035 | knows about, including floating point, for either 32-bit or | |
8036 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
8037 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
8038 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8039 | |
8040 | /* Otherwise we don't have a useful guess. */ | |
8041 | } | |
8042 | ||
f8b73d13 DJ |
8043 | static struct value * |
8044 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
8045 | { | |
8046 | const int *reg_p = baton; | |
8047 | return value_of_register (*reg_p, frame); | |
8048 | } | |
8049 | ||
c2d11a7d | 8050 | static struct gdbarch * |
6d82d43b | 8051 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 8052 | { |
c2d11a7d JM |
8053 | struct gdbarch *gdbarch; |
8054 | struct gdbarch_tdep *tdep; | |
8055 | int elf_flags; | |
2e4ebe70 | 8056 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 8057 | int i, num_regs; |
8d5838b5 | 8058 | enum mips_fpu_type fpu_type; |
f8b73d13 | 8059 | struct tdesc_arch_data *tdesc_data = NULL; |
d929bc19 | 8060 | int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; |
1faeff08 MR |
8061 | const char **reg_names; |
8062 | struct mips_regnum mips_regnum, *regnum; | |
4cc0665f | 8063 | enum mips_isa mips_isa; |
1faeff08 MR |
8064 | int dspacc; |
8065 | int dspctl; | |
8066 | ||
8067 | /* Fill in the OS dependent register numbers and names. */ | |
8068 | if (info.osabi == GDB_OSABI_IRIX) | |
8069 | { | |
8070 | mips_regnum.fp0 = 32; | |
8071 | mips_regnum.pc = 64; | |
8072 | mips_regnum.cause = 65; | |
8073 | mips_regnum.badvaddr = 66; | |
8074 | mips_regnum.hi = 67; | |
8075 | mips_regnum.lo = 68; | |
8076 | mips_regnum.fp_control_status = 69; | |
8077 | mips_regnum.fp_implementation_revision = 70; | |
8078 | mips_regnum.dspacc = dspacc = -1; | |
8079 | mips_regnum.dspctl = dspctl = -1; | |
8080 | num_regs = 71; | |
8081 | reg_names = mips_irix_reg_names; | |
8082 | } | |
8083 | else if (info.osabi == GDB_OSABI_LINUX) | |
8084 | { | |
8085 | mips_regnum.fp0 = 38; | |
8086 | mips_regnum.pc = 37; | |
8087 | mips_regnum.cause = 36; | |
8088 | mips_regnum.badvaddr = 35; | |
8089 | mips_regnum.hi = 34; | |
8090 | mips_regnum.lo = 33; | |
8091 | mips_regnum.fp_control_status = 70; | |
8092 | mips_regnum.fp_implementation_revision = 71; | |
8093 | mips_regnum.dspacc = -1; | |
8094 | mips_regnum.dspctl = -1; | |
8095 | dspacc = 72; | |
8096 | dspctl = 78; | |
8097 | num_regs = 79; | |
8098 | reg_names = mips_linux_reg_names; | |
8099 | } | |
8100 | else | |
8101 | { | |
8102 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
8103 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
8104 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
8105 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
8106 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
8107 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
8108 | mips_regnum.fp_control_status = 70; | |
8109 | mips_regnum.fp_implementation_revision = 71; | |
8110 | mips_regnum.dspacc = dspacc = -1; | |
8111 | mips_regnum.dspctl = dspctl = -1; | |
8112 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
8113 | if (info.bfd_arch_info != NULL | |
8114 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
8115 | reg_names = mips_tx39_reg_names; | |
8116 | else | |
8117 | reg_names = mips_generic_reg_names; | |
8118 | } | |
f8b73d13 DJ |
8119 | |
8120 | /* Check any target description for validity. */ | |
8121 | if (tdesc_has_registers (info.target_desc)) | |
8122 | { | |
8123 | static const char *const mips_gprs[] = { | |
8124 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
8125 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
8126 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
8127 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
8128 | }; | |
8129 | static const char *const mips_fprs[] = { | |
8130 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
8131 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
8132 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
8133 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
8134 | }; | |
8135 | ||
8136 | const struct tdesc_feature *feature; | |
8137 | int valid_p; | |
8138 | ||
8139 | feature = tdesc_find_feature (info.target_desc, | |
8140 | "org.gnu.gdb.mips.cpu"); | |
8141 | if (feature == NULL) | |
8142 | return NULL; | |
8143 | ||
8144 | tdesc_data = tdesc_data_alloc (); | |
8145 | ||
8146 | valid_p = 1; | |
8147 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
8148 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
8149 | mips_gprs[i]); | |
8150 | ||
8151 | ||
8152 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8153 | mips_regnum.lo, "lo"); |
f8b73d13 | 8154 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 8155 | mips_regnum.hi, "hi"); |
f8b73d13 | 8156 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 8157 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
8158 | |
8159 | if (!valid_p) | |
8160 | { | |
8161 | tdesc_data_cleanup (tdesc_data); | |
8162 | return NULL; | |
8163 | } | |
8164 | ||
8165 | feature = tdesc_find_feature (info.target_desc, | |
8166 | "org.gnu.gdb.mips.cp0"); | |
8167 | if (feature == NULL) | |
8168 | { | |
8169 | tdesc_data_cleanup (tdesc_data); | |
8170 | return NULL; | |
8171 | } | |
8172 | ||
8173 | valid_p = 1; | |
8174 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8175 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
8176 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
8177 | MIPS_PS_REGNUM, "status"); | |
8178 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8179 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
8180 | |
8181 | if (!valid_p) | |
8182 | { | |
8183 | tdesc_data_cleanup (tdesc_data); | |
8184 | return NULL; | |
8185 | } | |
8186 | ||
8187 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
8188 | backend is not prepared for that, though. */ | |
8189 | feature = tdesc_find_feature (info.target_desc, | |
8190 | "org.gnu.gdb.mips.fpu"); | |
8191 | if (feature == NULL) | |
8192 | { | |
8193 | tdesc_data_cleanup (tdesc_data); | |
8194 | return NULL; | |
8195 | } | |
8196 | ||
8197 | valid_p = 1; | |
8198 | for (i = 0; i < 32; i++) | |
8199 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8200 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
8201 | |
8202 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
8203 | mips_regnum.fp_control_status, |
8204 | "fcsr"); | |
8205 | valid_p | |
8206 | &= tdesc_numbered_register (feature, tdesc_data, | |
8207 | mips_regnum.fp_implementation_revision, | |
8208 | "fir"); | |
f8b73d13 DJ |
8209 | |
8210 | if (!valid_p) | |
8211 | { | |
8212 | tdesc_data_cleanup (tdesc_data); | |
8213 | return NULL; | |
8214 | } | |
8215 | ||
1faeff08 MR |
8216 | if (dspacc >= 0) |
8217 | { | |
8218 | feature = tdesc_find_feature (info.target_desc, | |
8219 | "org.gnu.gdb.mips.dsp"); | |
8220 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8221 | if (feature != NULL) | |
8222 | { | |
8223 | i = 0; | |
8224 | valid_p = 1; | |
8225 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8226 | dspacc + i++, "hi1"); | |
8227 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8228 | dspacc + i++, "lo1"); | |
8229 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8230 | dspacc + i++, "hi2"); | |
8231 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8232 | dspacc + i++, "lo2"); | |
8233 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8234 | dspacc + i++, "hi3"); | |
8235 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8236 | dspacc + i++, "lo3"); | |
8237 | ||
8238 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8239 | dspctl, "dspctl"); | |
8240 | ||
8241 | if (!valid_p) | |
8242 | { | |
8243 | tdesc_data_cleanup (tdesc_data); | |
8244 | return NULL; | |
8245 | } | |
8246 | ||
8247 | mips_regnum.dspacc = dspacc; | |
8248 | mips_regnum.dspctl = dspctl; | |
8249 | } | |
8250 | } | |
8251 | ||
f8b73d13 DJ |
8252 | /* It would be nice to detect an attempt to use a 64-bit ABI |
8253 | when only 32-bit registers are provided. */ | |
1faeff08 | 8254 | reg_names = NULL; |
f8b73d13 | 8255 | } |
c2d11a7d | 8256 | |
ec03c1ac AC |
8257 | /* First of all, extract the elf_flags, if available. */ |
8258 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8259 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
8260 | else if (arches != NULL) |
8261 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
8262 | else |
8263 | elf_flags = 0; | |
8264 | if (gdbarch_debug) | |
8265 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8266 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 8267 | |
102182a9 | 8268 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8269 | switch ((elf_flags & EF_MIPS_ABI)) |
8270 | { | |
8271 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8272 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8273 | break; |
8274 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8275 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8276 | break; |
8277 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8278 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8279 | break; |
8280 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8281 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8282 | break; |
8283 | default: | |
acdb74a0 | 8284 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8285 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8286 | else |
ec03c1ac | 8287 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8288 | break; |
8289 | } | |
acdb74a0 | 8290 | |
caaa3122 | 8291 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8292 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8293 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8294 | |
dc305454 | 8295 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8296 | MIPS architecture (if there is one). */ |
8297 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
8298 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 8299 | |
32a6503c | 8300 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8301 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8302 | && info.bfd_arch_info != NULL |
8303 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8304 | { | |
8305 | switch (info.bfd_arch_info->mach) | |
8306 | { | |
8307 | case bfd_mach_mips3900: | |
ec03c1ac | 8308 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8309 | break; |
8310 | case bfd_mach_mips4100: | |
8311 | case bfd_mach_mips5000: | |
ec03c1ac | 8312 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8313 | break; |
1d06468c EZ |
8314 | case bfd_mach_mips8000: |
8315 | case bfd_mach_mips10000: | |
32a6503c KB |
8316 | /* On Irix, ELF64 executables use the N64 ABI. The |
8317 | pseudo-sections which describe the ABI aren't present | |
8318 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
8319 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
8320 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 8321 | found_abi = MIPS_ABI_N64; |
28d169de | 8322 | else |
ec03c1ac | 8323 | found_abi = MIPS_ABI_N32; |
1d06468c | 8324 | break; |
bf64bfd6 AC |
8325 | } |
8326 | } | |
2e4ebe70 | 8327 | |
26c53e50 DJ |
8328 | /* Default 64-bit objects to N64 instead of O32. */ |
8329 | if (found_abi == MIPS_ABI_UNKNOWN | |
8330 | && info.abfd != NULL | |
8331 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8332 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8333 | found_abi = MIPS_ABI_N64; | |
8334 | ||
ec03c1ac AC |
8335 | if (gdbarch_debug) |
8336 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
8337 | found_abi); | |
8338 | ||
8339 | /* What has the user specified from the command line? */ | |
8340 | wanted_abi = global_mips_abi (); | |
8341 | if (gdbarch_debug) | |
8342 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
8343 | wanted_abi); | |
2e4ebe70 DJ |
8344 | |
8345 | /* Now that we have found what the ABI for this binary would be, | |
8346 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8347 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8348 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8349 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8350 | mips_abi = found_abi; | |
8351 | else | |
8352 | mips_abi = MIPS_ABI_O32; | |
8353 | if (gdbarch_debug) | |
8354 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
8355 | mips_abi); | |
2e4ebe70 | 8356 | |
4cc0665f MR |
8357 | /* Determine the default compressed ISA. */ |
8358 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8359 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8360 | mips_isa = ISA_MICROMIPS; | |
8361 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8362 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8363 | mips_isa = ISA_MIPS16; | |
8364 | else | |
8365 | mips_isa = global_mips_compression (); | |
8366 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8367 | ||
ec03c1ac | 8368 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8369 | if (gdbarch_debug) |
ec03c1ac | 8370 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
8371 | "mips_gdbarch_init: " |
8372 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 8373 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 8374 | |
8d5838b5 | 8375 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8376 | #ifdef HAVE_ELF |
8377 | if (info.abfd | |
8378 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8379 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8380 | Tag_GNU_MIPS_ABI_FP); | |
8381 | #endif /* HAVE_ELF */ | |
8382 | ||
8d5838b5 AC |
8383 | if (!mips_fpu_type_auto) |
8384 | fpu_type = mips_fpu_type; | |
d929bc19 | 8385 | else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) |
609ca2b9 DJ |
8386 | { |
8387 | switch (elf_fpu_type) | |
8388 | { | |
d929bc19 | 8389 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
609ca2b9 DJ |
8390 | fpu_type = MIPS_FPU_DOUBLE; |
8391 | break; | |
d929bc19 | 8392 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
609ca2b9 DJ |
8393 | fpu_type = MIPS_FPU_SINGLE; |
8394 | break; | |
d929bc19 | 8395 | case Val_GNU_MIPS_ABI_FP_SOFT: |
609ca2b9 DJ |
8396 | default: |
8397 | /* Soft float or unknown. */ | |
8398 | fpu_type = MIPS_FPU_NONE; | |
8399 | break; | |
8400 | } | |
8401 | } | |
8d5838b5 AC |
8402 | else if (info.bfd_arch_info != NULL |
8403 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8404 | switch (info.bfd_arch_info->mach) | |
8405 | { | |
8406 | case bfd_mach_mips3900: | |
8407 | case bfd_mach_mips4100: | |
8408 | case bfd_mach_mips4111: | |
a9d61c86 | 8409 | case bfd_mach_mips4120: |
8d5838b5 AC |
8410 | fpu_type = MIPS_FPU_NONE; |
8411 | break; | |
8412 | case bfd_mach_mips4650: | |
8413 | fpu_type = MIPS_FPU_SINGLE; | |
8414 | break; | |
8415 | default: | |
8416 | fpu_type = MIPS_FPU_DOUBLE; | |
8417 | break; | |
8418 | } | |
8419 | else if (arches != NULL) | |
8420 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
8421 | else | |
8422 | fpu_type = MIPS_FPU_DOUBLE; | |
8423 | if (gdbarch_debug) | |
8424 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8425 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 8426 | |
29709017 DJ |
8427 | /* Check for blatant incompatibilities. */ |
8428 | ||
8429 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8430 | ABI. */ | |
8431 | if (info.target_desc | |
8432 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8433 | && mips_abi != MIPS_ABI_EABI32 | |
8434 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
8435 | { |
8436 | if (tdesc_data != NULL) | |
8437 | tdesc_data_cleanup (tdesc_data); | |
8438 | return NULL; | |
8439 | } | |
29709017 | 8440 | |
025bb325 | 8441 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8442 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8443 | arches != NULL; | |
8444 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8445 | { | |
d54398a7 MR |
8446 | /* MIPS needs to be pedantic about which ABI and the compressed |
8447 | ISA variation the object is using. */ | |
9103eae0 | 8448 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 8449 | continue; |
9103eae0 | 8450 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 8451 | continue; |
d54398a7 MR |
8452 | if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa) |
8453 | continue; | |
719ec221 AC |
8454 | /* Need to be pedantic about which register virtual size is |
8455 | used. */ | |
8456 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
8457 | != mips64_transfers_32bit_regs_p) | |
8458 | continue; | |
8d5838b5 AC |
8459 | /* Be pedantic about which FPU is selected. */ |
8460 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
8461 | continue; | |
f8b73d13 DJ |
8462 | |
8463 | if (tdesc_data != NULL) | |
8464 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 8465 | return arches->gdbarch; |
c2d11a7d JM |
8466 | } |
8467 | ||
102182a9 | 8468 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
8469 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
8470 | gdbarch = gdbarch_alloc (&info, tdep); | |
8471 | tdep->elf_flags = elf_flags; | |
719ec221 | 8472 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8473 | tdep->found_abi = found_abi; |
8474 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8475 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8476 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8477 | tdep->register_size_valid_p = 0; |
8478 | tdep->register_size = 0; | |
8479 | ||
8480 | if (info.target_desc) | |
8481 | { | |
8482 | /* Some useful properties can be inferred from the target. */ | |
8483 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8484 | { | |
8485 | tdep->register_size_valid_p = 1; | |
8486 | tdep->register_size = 4; | |
8487 | } | |
8488 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8489 | { | |
8490 | tdep->register_size_valid_p = 1; | |
8491 | tdep->register_size = 8; | |
8492 | } | |
8493 | } | |
c2d11a7d | 8494 | |
102182a9 | 8495 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8496 | set_gdbarch_short_bit (gdbarch, 16); |
8497 | set_gdbarch_int_bit (gdbarch, 32); | |
8498 | set_gdbarch_float_bit (gdbarch, 32); | |
8499 | set_gdbarch_double_bit (gdbarch, 64); | |
8500 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8501 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8502 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8503 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8504 | |
175ff332 HZ |
8505 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8506 | mips_ax_pseudo_register_collect); | |
8507 | set_gdbarch_ax_pseudo_register_push_stack | |
8508 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8509 | ||
6d82d43b | 8510 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
8511 | mips_elf_make_msymbol_special); |
8512 | ||
1faeff08 MR |
8513 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8514 | *regnum = mips_regnum; | |
1faeff08 MR |
8515 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8516 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8517 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8518 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8519 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8520 | tdep->mips_processor_reg_names = reg_names; | |
8521 | tdep->regnum = regnum; | |
fe29b929 | 8522 | |
0dadbba0 | 8523 | switch (mips_abi) |
c2d11a7d | 8524 | { |
0dadbba0 | 8525 | case MIPS_ABI_O32: |
25ab4790 | 8526 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8527 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8528 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8529 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8530 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8531 | set_gdbarch_long_bit (gdbarch, 32); |
8532 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8533 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8534 | break; | |
0dadbba0 | 8535 | case MIPS_ABI_O64: |
25ab4790 | 8536 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8537 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8538 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8539 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8540 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8541 | set_gdbarch_long_bit (gdbarch, 32); |
8542 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8543 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8544 | break; | |
0dadbba0 | 8545 | case MIPS_ABI_EABI32: |
25ab4790 | 8546 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8547 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8548 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8549 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8550 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8551 | set_gdbarch_long_bit (gdbarch, 32); |
8552 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8553 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8554 | break; | |
0dadbba0 | 8555 | case MIPS_ABI_EABI64: |
25ab4790 | 8556 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8557 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8558 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8559 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8560 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8561 | set_gdbarch_long_bit (gdbarch, 64); |
8562 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8563 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8564 | break; | |
0dadbba0 | 8565 | case MIPS_ABI_N32: |
25ab4790 | 8566 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8567 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8568 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8569 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8570 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8571 | set_gdbarch_long_bit (gdbarch, 32); |
8572 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8573 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8574 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8575 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8576 | break; |
8577 | case MIPS_ABI_N64: | |
25ab4790 | 8578 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8579 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8580 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8581 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8582 | tdep->default_mask_address_p = 0; |
8583 | set_gdbarch_long_bit (gdbarch, 64); | |
8584 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8585 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8586 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8587 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8588 | break; |
c2d11a7d | 8589 | default: |
e2e0b3e5 | 8590 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
8591 | } |
8592 | ||
22e47e37 FF |
8593 | /* GCC creates a pseudo-section whose name specifies the size of |
8594 | longs, since -mlong32 or -mlong64 may be used independent of | |
8595 | other options. How those options affect pointer sizes is ABI and | |
8596 | architecture dependent, so use them to override the default sizes | |
8597 | set by the ABI. This table shows the relationship between ABI, | |
8598 | -mlongXX, and size of pointers: | |
8599 | ||
8600 | ABI -mlongXX ptr bits | |
8601 | --- -------- -------- | |
8602 | o32 32 32 | |
8603 | o32 64 32 | |
8604 | n32 32 32 | |
8605 | n32 64 64 | |
8606 | o64 32 32 | |
8607 | o64 64 64 | |
8608 | n64 32 32 | |
8609 | n64 64 64 | |
8610 | eabi32 32 32 | |
8611 | eabi32 64 32 | |
8612 | eabi64 32 32 | |
8613 | eabi64 64 64 | |
8614 | ||
8615 | Note that for o32 and eabi32, pointers are always 32 bits | |
8616 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8617 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8618 | |
8619 | if (info.abfd != NULL) | |
8620 | { | |
8621 | int long_bit = 0; | |
8622 | ||
8623 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8624 | if (long_bit) | |
8625 | { | |
8626 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8627 | switch (mips_abi) | |
8628 | { | |
8629 | case MIPS_ABI_O32: | |
8630 | case MIPS_ABI_EABI32: | |
8631 | break; | |
8632 | case MIPS_ABI_N32: | |
8633 | case MIPS_ABI_O64: | |
8634 | case MIPS_ABI_N64: | |
8635 | case MIPS_ABI_EABI64: | |
8636 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8637 | break; | |
8638 | default: | |
8639 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
8640 | } | |
8641 | } | |
8642 | } | |
8643 | ||
a5ea2558 AC |
8644 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8645 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8646 | comment: | |
8647 | ||
8648 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8649 | flag in object files because to do so would make it impossible to | |
102182a9 | 8650 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8651 | unnecessarily restrictive. |
361d1df0 | 8652 | |
a5ea2558 AC |
8653 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8654 | but to set this flag before gcc is built with such multilibs will | |
8655 | break too many systems.'' | |
8656 | ||
8657 | But even more unhelpfully, the default linker output target for | |
8658 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8659 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8660 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8661 | this flag to detect 32-bit mode would do the wrong thing given |
8662 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8663 | as 32-bit programs by default. */ |
a5ea2558 | 8664 | |
6c997a34 | 8665 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8666 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8667 | |
102182a9 MS |
8668 | /* Add/remove bits from an address. The MIPS needs be careful to |
8669 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8670 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8671 | ||
58dfe9ff AC |
8672 | /* Unwind the frame. */ |
8673 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8674 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8675 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8676 | |
102182a9 | 8677 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8678 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8679 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8680 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8681 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8682 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8683 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8684 | |
025bb325 | 8685 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8686 | |
2c76a0c7 JB |
8687 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8688 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8689 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8690 | |
87783b8b AC |
8691 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8692 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8693 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8694 | ||
f7b9e9fc AC |
8695 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
8696 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
4cc0665f MR |
8697 | set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
8698 | mips_remote_breakpoint_from_pc); | |
c8cef75f MR |
8699 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8700 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8701 | |
8702 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8703 | |
97ab0fdd MR |
8704 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
8705 | ||
fc0c74b1 AC |
8706 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8707 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8708 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8709 | |
a4b8ebc8 | 8710 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8711 | |
e11c53d2 | 8712 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8713 | |
9dae60cc UW |
8714 | if (mips_abi == MIPS_ABI_N32) |
8715 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
8716 | else if (mips_abi == MIPS_ABI_N64) | |
8717 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
8718 | else | |
8719 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 8720 | |
d92524f1 PM |
8721 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8722 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8723 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8724 | being used as guards for target_stopped_by_watchpoint, why not have |
8725 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8726 | is sitting on? */ |
8727 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8728 | ||
e7d6a6d2 | 8729 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8730 | |
14132e89 MR |
8731 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8732 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8733 | if we have an OS ABI that actually supports shared libraries, since | |
8734 | shared library support is more important. If we have an OS someday | |
8735 | that supports both shared libraries and MIPS16, we'll have to find | |
8736 | a better place for these. | |
8737 | macro/2012-04-25: But that applies to return trampolines only and | |
8738 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8739 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8740 | ||
025bb325 MS |
8741 | set_gdbarch_single_step_through_delay (gdbarch, |
8742 | mips_single_step_through_delay); | |
3352ef37 | 8743 | |
0d5de010 DJ |
8744 | /* Virtual tables. */ |
8745 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8746 | ||
29709017 DJ |
8747 | mips_register_g_packet_guesses (gdbarch); |
8748 | ||
6de918a6 | 8749 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 8750 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 8751 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8752 | |
9aac7884 MR |
8753 | /* The hook may have adjusted num_regs, fetch the final value and |
8754 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8755 | num_regs = gdbarch_num_regs (gdbarch); |
8756 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8757 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8758 | ||
5792a79b | 8759 | /* Unwind the frame. */ |
b8a22b94 DJ |
8760 | dwarf2_append_unwinders (gdbarch); |
8761 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8762 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8763 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8764 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8765 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8766 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8767 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8768 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8769 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8770 | |
f8b73d13 DJ |
8771 | if (tdesc_data) |
8772 | { | |
8773 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 8774 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
8775 | |
8776 | /* Override the normal target description methods to handle our | |
8777 | dual real and pseudo registers. */ | |
8778 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8779 | set_gdbarch_register_reggroup_p (gdbarch, |
8780 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8781 | |
8782 | num_regs = gdbarch_num_regs (gdbarch); | |
8783 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8784 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8785 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8786 | } | |
8787 | ||
8788 | /* Add ABI-specific aliases for the registers. */ | |
8789 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8790 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8791 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8792 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8793 | else | |
8794 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8795 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8796 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8797 | ||
8798 | /* Add some other standard aliases. */ | |
8799 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8800 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8801 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8802 | ||
865093a3 AR |
8803 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8804 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8805 | value_of_mips_user_reg, | |
8806 | &mips_numeric_register_aliases[i].regnum); | |
8807 | ||
4b9b3959 AC |
8808 | return gdbarch; |
8809 | } | |
8810 | ||
2e4ebe70 | 8811 | static void |
6d82d43b | 8812 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
8813 | { |
8814 | struct gdbarch_info info; | |
8815 | ||
8816 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8817 | mips_gdbarch_init will take care of the rest. */ | |
8818 | gdbarch_info_init (&info); | |
8819 | gdbarch_update_p (info); | |
8820 | } | |
8821 | ||
ad188201 KB |
8822 | /* Print out which MIPS ABI is in use. */ |
8823 | ||
8824 | static void | |
1f8ca57c JB |
8825 | show_mips_abi (struct ui_file *file, |
8826 | int from_tty, | |
8827 | struct cmd_list_element *ignored_cmd, | |
8828 | const char *ignored_value) | |
ad188201 | 8829 | { |
f5656ead | 8830 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
1f8ca57c JB |
8831 | fprintf_filtered |
8832 | (file, | |
8833 | "The MIPS ABI is unknown because the current architecture " | |
8834 | "is not MIPS.\n"); | |
ad188201 KB |
8835 | else |
8836 | { | |
8837 | enum mips_abi global_abi = global_mips_abi (); | |
f5656ead | 8838 | enum mips_abi actual_abi = mips_abi (target_gdbarch ()); |
ad188201 KB |
8839 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8840 | ||
8841 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
8842 | fprintf_filtered |
8843 | (file, | |
8844 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8845 | actual_abi_str); |
ad188201 | 8846 | else if (global_abi == actual_abi) |
1f8ca57c JB |
8847 | fprintf_filtered |
8848 | (file, | |
8849 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8850 | actual_abi_str); |
ad188201 KB |
8851 | else |
8852 | { | |
8853 | /* Probably shouldn't happen... */ | |
025bb325 MS |
8854 | fprintf_filtered (file, |
8855 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8856 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 8857 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
8858 | } |
8859 | } | |
8860 | } | |
8861 | ||
4cc0665f MR |
8862 | /* Print out which MIPS compressed ISA encoding is used. */ |
8863 | ||
8864 | static void | |
8865 | show_mips_compression (struct ui_file *file, int from_tty, | |
8866 | struct cmd_list_element *c, const char *value) | |
8867 | { | |
8868 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), | |
8869 | value); | |
8870 | } | |
8871 | ||
4b9b3959 | 8872 | static void |
72a155b4 | 8873 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8874 | { |
72a155b4 | 8875 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 8876 | if (tdep != NULL) |
c2d11a7d | 8877 | { |
acdb74a0 AC |
8878 | int ef_mips_arch; |
8879 | int ef_mips_32bitmode; | |
f49e4e6d | 8880 | /* Determine the ISA. */ |
acdb74a0 AC |
8881 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8882 | { | |
8883 | case E_MIPS_ARCH_1: | |
8884 | ef_mips_arch = 1; | |
8885 | break; | |
8886 | case E_MIPS_ARCH_2: | |
8887 | ef_mips_arch = 2; | |
8888 | break; | |
8889 | case E_MIPS_ARCH_3: | |
8890 | ef_mips_arch = 3; | |
8891 | break; | |
8892 | case E_MIPS_ARCH_4: | |
93d56215 | 8893 | ef_mips_arch = 4; |
acdb74a0 AC |
8894 | break; |
8895 | default: | |
93d56215 | 8896 | ef_mips_arch = 0; |
acdb74a0 AC |
8897 | break; |
8898 | } | |
f49e4e6d | 8899 | /* Determine the size of a pointer. */ |
acdb74a0 | 8900 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
8901 | fprintf_unfiltered (file, |
8902 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 8903 | tdep->elf_flags); |
4b9b3959 | 8904 | fprintf_unfiltered (file, |
acdb74a0 AC |
8905 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
8906 | ef_mips_32bitmode); | |
8907 | fprintf_unfiltered (file, | |
8908 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8909 | ef_mips_arch); | |
8910 | fprintf_unfiltered (file, | |
8911 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 8912 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 8913 | fprintf_unfiltered (file, |
025bb325 MS |
8914 | "mips_dump_tdep: " |
8915 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 8916 | mips_mask_address_p (tdep), |
4014092b | 8917 | tdep->default_mask_address_p); |
c2d11a7d | 8918 | } |
4b9b3959 AC |
8919 | fprintf_unfiltered (file, |
8920 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8921 | MIPS_DEFAULT_FPU_TYPE, | |
8922 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
8923 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
8924 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
8925 | : "???")); | |
74ed0bb4 MD |
8926 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
8927 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
8928 | fprintf_unfiltered (file, |
8929 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
8930 | MIPS_FPU_TYPE (gdbarch), |
8931 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
8932 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
8933 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 8934 | : "???")); |
c2d11a7d JM |
8935 | } |
8936 | ||
025bb325 | 8937 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 8938 | |
c906108c | 8939 | void |
acdb74a0 | 8940 | _initialize_mips_tdep (void) |
c906108c SS |
8941 | { |
8942 | static struct cmd_list_element *mipsfpulist = NULL; | |
8943 | struct cmd_list_element *c; | |
8944 | ||
6d82d43b | 8945 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8946 | if (MIPS_ABI_LAST + 1 |
8947 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 8948 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 8949 | |
4b9b3959 | 8950 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8951 | |
8d5f9dcb DJ |
8952 | mips_pdr_data = register_objfile_data (); |
8953 | ||
4eb0ad19 DJ |
8954 | /* Create feature sets with the appropriate properties. The values |
8955 | are not important. */ | |
8956 | mips_tdesc_gp32 = allocate_target_description (); | |
8957 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
8958 | ||
8959 | mips_tdesc_gp64 = allocate_target_description (); | |
8960 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
8961 | ||
025bb325 | 8962 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 8963 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 8964 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8965 | &setmipscmdlist, "set mips ", 0, &setlist); |
8966 | ||
8967 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 8968 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8969 | &showmipscmdlist, "show mips ", 0, &showlist); |
8970 | ||
025bb325 | 8971 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
8972 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
8973 | &mips_abi_string, _("\ | |
8974 | Set the MIPS ABI used by this program."), _("\ | |
8975 | Show the MIPS ABI used by this program."), _("\ | |
8976 | This option can be set to one of:\n\ | |
8977 | auto - the default ABI associated with the current binary\n\ | |
8978 | o32\n\ | |
8979 | o64\n\ | |
8980 | n32\n\ | |
8981 | n64\n\ | |
8982 | eabi32\n\ | |
8983 | eabi64"), | |
8984 | mips_abi_update, | |
8985 | show_mips_abi, | |
8986 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 8987 | |
4cc0665f MR |
8988 | /* Allow the user to set the ISA to assume for compressed code if ELF |
8989 | file flags don't tell or there is no program file selected. This | |
8990 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
8991 | and carried over to subsequent sessions. */ | |
8992 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
8993 | &mips_compression_string, _("\ | |
8994 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
8995 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
8996 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
8997 | information available. The encoding can be set to either of:\n\ | |
8998 | mips16\n\ | |
8999 | micromips\n\ | |
9000 | and is updated automatically from ELF file flags if available."), | |
9001 | mips_abi_update, | |
9002 | show_mips_compression, | |
9003 | &setmipscmdlist, &showmipscmdlist); | |
9004 | ||
c906108c SS |
9005 | /* Let the user turn off floating point and set the fence post for |
9006 | heuristic_proc_start. */ | |
9007 | ||
9008 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 9009 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
9010 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
9011 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 9012 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
9013 | &mipsfpulist); |
9014 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 9015 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
9016 | &mipsfpulist); |
9017 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
9018 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
9019 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
9020 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 9021 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
9022 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
9023 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
9024 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
9025 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 9026 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
9027 | &mipsfpulist); |
9028 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 9029 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
9030 | &showlist); |
9031 | ||
c906108c SS |
9032 | /* We really would like to have both "0" and "unlimited" work, but |
9033 | command.c doesn't deal with that. So make it a var_zinteger | |
9034 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 9035 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
9036 | &heuristic_fence_post, _("\ |
9037 | Set the distance searched for the start of a function."), _("\ | |
9038 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
9039 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
9040 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 9041 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 9042 | reinit_frame_cache_sfunc, |
025bb325 MS |
9043 | NULL, /* FIXME: i18n: The distance searched for |
9044 | the start of a function is %s. */ | |
6bcadd06 | 9045 | &setlist, &showlist); |
c906108c SS |
9046 | |
9047 | /* Allow the user to control whether the upper bits of 64-bit | |
9048 | addresses should be zeroed. */ | |
7915a72c AC |
9049 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
9050 | &mask_address_var, _("\ | |
9051 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
9052 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 9053 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 9054 | allow GDB to determine the correct value."), |
08546159 AC |
9055 | NULL, show_mask_address, |
9056 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
9057 | |
9058 | /* Allow the user to control the size of 32 bit registers within the | |
9059 | raw remote packet. */ | |
b3f42336 | 9060 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
9061 | &mips64_transfers_32bit_regs_p, _("\ |
9062 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9063 | _("\ | |
9064 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9065 | _("\ | |
719ec221 AC |
9066 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
9067 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 9068 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 9069 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
9070 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
9071 | MIPS target that transfers 32-bit | |
9072 | quantities is %s. */ | |
7915a72c | 9073 | &setlist, &showlist); |
9ace0497 | 9074 | |
025bb325 | 9075 | /* Debug this files internals. */ |
ccce17b0 YQ |
9076 | add_setshow_zuinteger_cmd ("mips", class_maintenance, |
9077 | &mips_debug, _("\ | |
7915a72c AC |
9078 | Set mips debugging."), _("\ |
9079 | Show mips debugging."), _("\ | |
9080 | When non-zero, mips specific debugging is enabled."), | |
ccce17b0 YQ |
9081 | NULL, |
9082 | NULL, /* FIXME: i18n: Mips debugging is | |
9083 | currently %s. */ | |
9084 | &setdebuglist, &showdebuglist); | |
c906108c | 9085 | } |