Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
1e698235 | 4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
5e2e9765 | 28 | #include "gdb_assert.h" |
c906108c SS |
29 | #include "frame.h" |
30 | #include "inferior.h" | |
31 | #include "symtab.h" | |
32 | #include "value.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "language.h" | |
35 | #include "gdbcore.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "gdbtypes.h" | |
39 | #include "target.h" | |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
70f80edf | 42 | #include "osabi.h" |
d1973055 | 43 | #include "mips-tdep.h" |
fe898f56 | 44 | #include "block.h" |
a4b8ebc8 | 45 | #include "reggroups.h" |
c906108c | 46 | #include "opcode/mips.h" |
c2d11a7d JM |
47 | #include "elf/mips.h" |
48 | #include "elf-bfd.h" | |
2475bac3 | 49 | #include "symcat.h" |
a4b8ebc8 | 50 | #include "sim-regno.h" |
a89aa300 | 51 | #include "dis-asm.h" |
c906108c | 52 | |
e0f7ec59 | 53 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 54 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 55 | |
dd824b04 DJ |
56 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
57 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
58 | #define ST0_FR (1 << 26) | |
59 | ||
b0069a17 AC |
60 | /* The sizes of floating point registers. */ |
61 | ||
62 | enum | |
63 | { | |
64 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
65 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
66 | }; | |
67 | ||
0dadbba0 | 68 | |
2e4ebe70 DJ |
69 | static const char *mips_abi_string; |
70 | ||
71 | static const char *mips_abi_strings[] = { | |
72 | "auto", | |
73 | "n32", | |
74 | "o32", | |
28d169de | 75 | "n64", |
2e4ebe70 DJ |
76 | "o64", |
77 | "eabi32", | |
78 | "eabi64", | |
79 | NULL | |
80 | }; | |
81 | ||
cce74817 | 82 | struct frame_extra_info |
c5aa993b JM |
83 | { |
84 | mips_extra_func_info_t proc_desc; | |
85 | int num_args; | |
86 | }; | |
cce74817 | 87 | |
d929b26f AC |
88 | /* Various MIPS ISA options (related to stack analysis) can be |
89 | overridden dynamically. Establish an enum/array for managing | |
90 | them. */ | |
91 | ||
53904c9e AC |
92 | static const char size_auto[] = "auto"; |
93 | static const char size_32[] = "32"; | |
94 | static const char size_64[] = "64"; | |
d929b26f | 95 | |
53904c9e | 96 | static const char *size_enums[] = { |
d929b26f AC |
97 | size_auto, |
98 | size_32, | |
99 | size_64, | |
a5ea2558 AC |
100 | 0 |
101 | }; | |
102 | ||
7a292a7a SS |
103 | /* Some MIPS boards don't support floating point while others only |
104 | support single-precision floating-point operations. See also | |
105 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
106 | |
107 | enum mips_fpu_type | |
c5aa993b JM |
108 | { |
109 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
110 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
111 | MIPS_FPU_NONE /* No floating point. */ | |
112 | }; | |
c906108c SS |
113 | |
114 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
115 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
116 | #endif | |
117 | static int mips_fpu_type_auto = 1; | |
118 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 119 | |
9ace0497 | 120 | static int mips_debug = 0; |
7a292a7a | 121 | |
c2d11a7d JM |
122 | /* MIPS specific per-architecture information */ |
123 | struct gdbarch_tdep | |
124 | { | |
125 | /* from the elf header */ | |
126 | int elf_flags; | |
70f80edf | 127 | |
c2d11a7d | 128 | /* mips options */ |
0dadbba0 | 129 | enum mips_abi mips_abi; |
2e4ebe70 | 130 | enum mips_abi found_abi; |
c2d11a7d JM |
131 | enum mips_fpu_type mips_fpu_type; |
132 | int mips_last_arg_regnum; | |
133 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 134 | int mips_default_saved_regsize; |
c2d11a7d | 135 | int mips_fp_register_double; |
d929b26f | 136 | int mips_default_stack_argsize; |
5213ab06 | 137 | int gdb_target_is_mips64; |
4014092b | 138 | int default_mask_address_p; |
c2d11a7d JM |
139 | }; |
140 | ||
0dadbba0 | 141 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 142 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 143 | |
c2d11a7d | 144 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 145 | |
c2d11a7d | 146 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 147 | |
c2d11a7d | 148 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 149 | |
d929b26f AC |
150 | /* Return the currently configured (or set) saved register size. */ |
151 | ||
a5ea2558 | 152 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 153 | |
53904c9e | 154 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
155 | |
156 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
157 | ||
95404a3e AC |
158 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
159 | functions to test, set, or clear bit 0 of addresses. */ | |
160 | ||
161 | static CORE_ADDR | |
162 | is_mips16_addr (CORE_ADDR addr) | |
163 | { | |
164 | return ((addr) & 1); | |
165 | } | |
166 | ||
167 | static CORE_ADDR | |
168 | make_mips16_addr (CORE_ADDR addr) | |
169 | { | |
170 | return ((addr) | 1); | |
171 | } | |
172 | ||
173 | static CORE_ADDR | |
174 | unmake_mips16_addr (CORE_ADDR addr) | |
175 | { | |
176 | return ((addr) & ~1); | |
177 | } | |
178 | ||
22540ece AC |
179 | /* Return the contents of register REGNUM as a signed integer. */ |
180 | ||
181 | static LONGEST | |
182 | read_signed_register (int regnum) | |
183 | { | |
12c266ea | 184 | void *buf = alloca (DEPRECATED_REGISTER_RAW_SIZE (regnum)); |
22540ece | 185 | deprecated_read_register_gen (regnum, buf); |
12c266ea | 186 | return (extract_signed_integer (buf, DEPRECATED_REGISTER_RAW_SIZE (regnum))); |
22540ece AC |
187 | } |
188 | ||
189 | static LONGEST | |
190 | read_signed_register_pid (int regnum, ptid_t ptid) | |
191 | { | |
192 | ptid_t save_ptid; | |
193 | LONGEST retval; | |
194 | ||
195 | if (ptid_equal (ptid, inferior_ptid)) | |
196 | return read_signed_register (regnum); | |
197 | ||
198 | save_ptid = inferior_ptid; | |
199 | ||
200 | inferior_ptid = ptid; | |
201 | ||
202 | retval = read_signed_register (regnum); | |
203 | ||
204 | inferior_ptid = save_ptid; | |
205 | ||
206 | return retval; | |
207 | } | |
208 | ||
d1973055 KB |
209 | /* Return the MIPS ABI associated with GDBARCH. */ |
210 | enum mips_abi | |
211 | mips_abi (struct gdbarch *gdbarch) | |
212 | { | |
213 | return gdbarch_tdep (gdbarch)->mips_abi; | |
214 | } | |
215 | ||
d929b26f | 216 | static unsigned int |
acdb74a0 | 217 | mips_saved_regsize (void) |
d929b26f AC |
218 | { |
219 | if (mips_saved_regsize_string == size_auto) | |
220 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
221 | else if (mips_saved_regsize_string == size_64) | |
222 | return 8; | |
223 | else /* if (mips_saved_regsize_string == size_32) */ | |
224 | return 4; | |
225 | } | |
226 | ||
71b8ef93 | 227 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa MS |
228 | marks it as 16-bit function. The MSB of the minimal symbol's |
229 | "info" field is used for this purpose. This field is already | |
230 | being used to store the symbol size, so the assumption is | |
231 | that the symbol size cannot exceed 2^31. | |
232 | ||
233 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
234 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
235 | minimal symbol to mark it as a 16-bit function | |
236 | ||
237 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
238 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
239 | the "info" field with the "special" bit masked out */ | |
240 | ||
5a89d8aa MS |
241 | static void |
242 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
243 | { | |
244 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
245 | { | |
246 | MSYMBOL_INFO (msym) = (char *) | |
247 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
248 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
249 | } | |
250 | } | |
251 | ||
71b8ef93 MS |
252 | static int |
253 | msymbol_is_special (struct minimal_symbol *msym) | |
254 | { | |
255 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
256 | } | |
257 | ||
258 | static long | |
259 | msymbol_size (struct minimal_symbol *msym) | |
260 | { | |
261 | return ((long) MSYMBOL_INFO (msym) & 0x7fffffff); | |
262 | } | |
263 | ||
88658117 AC |
264 | /* XFER a value from the big/little/left end of the register. |
265 | Depending on the size of the value it might occupy the entire | |
266 | register or just part of it. Make an allowance for this, aligning | |
267 | things accordingly. */ | |
268 | ||
269 | static void | |
270 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
271 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
272 | int buf_offset) | |
273 | { | |
d9d9c31f | 274 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 | 275 | int reg_offset = 0; |
a4b8ebc8 | 276 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
277 | /* Need to transfer the left or right part of the register, based on |
278 | the targets byte order. */ | |
88658117 AC |
279 | switch (endian) |
280 | { | |
281 | case BFD_ENDIAN_BIG: | |
12c266ea | 282 | reg_offset = DEPRECATED_REGISTER_RAW_SIZE (reg_num) - length; |
88658117 AC |
283 | break; |
284 | case BFD_ENDIAN_LITTLE: | |
285 | reg_offset = 0; | |
286 | break; | |
287 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
288 | reg_offset = 0; | |
289 | break; | |
290 | default: | |
291 | internal_error (__FILE__, __LINE__, "bad switch"); | |
292 | } | |
293 | if (mips_debug) | |
cb1d2653 AC |
294 | fprintf_unfiltered (gdb_stderr, |
295 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
296 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
297 | if (mips_debug && out != NULL) |
298 | { | |
299 | int i; | |
cb1d2653 | 300 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 301 | for (i = 0; i < length; i++) |
cb1d2653 | 302 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
303 | } |
304 | if (in != NULL) | |
a4b8ebc8 | 305 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); |
88658117 | 306 | if (out != NULL) |
a4b8ebc8 | 307 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
308 | if (mips_debug && in != NULL) |
309 | { | |
310 | int i; | |
cb1d2653 | 311 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 312 | for (i = 0; i < length; i++) |
cb1d2653 | 313 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
314 | } |
315 | if (mips_debug) | |
316 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
317 | } | |
318 | ||
dd824b04 DJ |
319 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
320 | compatiblity mode. A return value of 1 means that we have | |
321 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
322 | ||
323 | static int | |
324 | mips2_fp_compat (void) | |
325 | { | |
326 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
327 | meaningful. */ | |
12c266ea | 328 | if (DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM) == 4) |
dd824b04 DJ |
329 | return 0; |
330 | ||
331 | #if 0 | |
332 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
333 | in all the places we deal with FP registers. PR gdb/413. */ | |
334 | /* Otherwise check the FR bit in the status register - it controls | |
335 | the FP compatiblity mode. If it is clear we are in compatibility | |
336 | mode. */ | |
337 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
338 | return 1; | |
339 | #endif | |
361d1df0 | 340 | |
dd824b04 DJ |
341 | return 0; |
342 | } | |
343 | ||
c2d11a7d JM |
344 | /* Indicate that the ABI makes use of double-precision registers |
345 | provided by the FPU (rather than combining pairs of registers to | |
346 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
347 | determine if the ABI is using double-precision registers. See also | |
348 | MIPS_FPU_TYPE. */ | |
c2d11a7d | 349 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 350 | |
d929b26f AC |
351 | /* The amount of space reserved on the stack for registers. This is |
352 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
353 | data allocated after the registers have run out. */ | |
354 | ||
0dadbba0 | 355 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
356 | |
357 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
358 | ||
53904c9e | 359 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
360 | |
361 | static unsigned int | |
362 | mips_stack_argsize (void) | |
363 | { | |
364 | if (mips_stack_argsize_string == size_auto) | |
365 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
366 | else if (mips_stack_argsize_string == size_64) | |
367 | return 8; | |
368 | else /* if (mips_stack_argsize_string == size_32) */ | |
369 | return 4; | |
370 | } | |
371 | ||
5213ab06 | 372 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) |
c2d11a7d | 373 | |
92e1c15c | 374 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 375 | |
7a292a7a | 376 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 377 | |
570b8f7c AC |
378 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
379 | struct frame_info *, int); | |
c906108c | 380 | |
a14ed312 | 381 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 382 | |
a14ed312 | 383 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 384 | |
5a89d8aa | 385 | static int mips_set_processor_type (char *); |
c906108c | 386 | |
a14ed312 | 387 | static void mips_show_processor_type_command (char *, int); |
c906108c | 388 | |
a14ed312 | 389 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 390 | |
570b8f7c AC |
391 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
392 | struct frame_info *next_frame, | |
393 | int cur_frame); | |
c906108c | 394 | |
a14ed312 KB |
395 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
396 | mips_extra_func_info_t proc_desc); | |
c906108c | 397 | |
67b2c998 DJ |
398 | static struct type *mips_float_register_type (void); |
399 | static struct type *mips_double_register_type (void); | |
400 | ||
c906108c SS |
401 | /* This value is the model of MIPS in use. It is derived from the value |
402 | of the PrID register. */ | |
403 | ||
404 | char *mips_processor_type; | |
405 | ||
406 | char *tmp_mips_processor_type; | |
407 | ||
acdb74a0 AC |
408 | /* The list of available "set mips " and "show mips " commands */ |
409 | ||
410 | static struct cmd_list_element *setmipscmdlist = NULL; | |
411 | static struct cmd_list_element *showmipscmdlist = NULL; | |
412 | ||
c906108c SS |
413 | /* A set of original names, to be used when restoring back to generic |
414 | registers from a specific set. */ | |
5e2e9765 | 415 | static char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
c906108c | 416 | |
5e2e9765 KB |
417 | /* Integer registers 0 thru 31 are handled explicitly by |
418 | mips_register_name(). Processor specific registers 32 and above | |
419 | are listed in the sets of register names assigned to | |
420 | mips_processor_reg_names. */ | |
421 | static char **mips_processor_reg_names = mips_generic_reg_names; | |
cce74817 | 422 | |
5e2e9765 | 423 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 424 | static const char * |
5e2e9765 | 425 | mips_register_name (int regno) |
cce74817 | 426 | { |
5e2e9765 KB |
427 | /* GPR names for all ABIs other than n32/n64. */ |
428 | static char *mips_gpr_names[] = { | |
429 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
430 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
431 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
432 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
433 | }; | |
434 | ||
435 | /* GPR names for n32 and n64 ABIs. */ | |
436 | static char *mips_n32_n64_gpr_names[] = { | |
437 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
438 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
439 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
440 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
441 | }; | |
442 | ||
443 | enum mips_abi abi = mips_abi (current_gdbarch); | |
444 | ||
a4b8ebc8 AC |
445 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
446 | don't make the raw register names visible. */ | |
447 | int rawnum = regno % NUM_REGS; | |
448 | if (regno < NUM_REGS) | |
449 | return ""; | |
450 | ||
5e2e9765 KB |
451 | /* The MIPS integer registers are always mapped from 0 to 31. The |
452 | names of the registers (which reflects the conventions regarding | |
453 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 454 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
455 | { |
456 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 457 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 458 | else |
a4b8ebc8 | 459 | return mips_gpr_names[rawnum]; |
5e2e9765 | 460 | } |
a4b8ebc8 AC |
461 | else if (32 <= rawnum && rawnum < NUM_REGS) |
462 | return mips_processor_reg_names[rawnum - 32]; | |
5e2e9765 KB |
463 | else |
464 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 465 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 466 | } |
5e2e9765 | 467 | |
9846de1b | 468 | /* *INDENT-OFF* */ |
c906108c SS |
469 | /* Names of IDT R3041 registers. */ |
470 | ||
471 | char *mips_r3041_reg_names[] = { | |
c906108c SS |
472 | "sr", "lo", "hi", "bad", "cause","pc", |
473 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
474 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
475 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
476 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 477 | "fsr", "fir", "",/*"fp"*/ "", |
c906108c SS |
478 | "", "", "bus", "ccfg", "", "", "", "", |
479 | "", "", "port", "cmp", "", "", "epc", "prid", | |
480 | }; | |
481 | ||
482 | /* Names of IDT R3051 registers. */ | |
483 | ||
484 | char *mips_r3051_reg_names[] = { | |
c906108c SS |
485 | "sr", "lo", "hi", "bad", "cause","pc", |
486 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
487 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
488 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
489 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 490 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
491 | "inx", "rand", "elo", "", "ctxt", "", "", "", |
492 | "", "", "ehi", "", "", "", "epc", "prid", | |
493 | }; | |
494 | ||
495 | /* Names of IDT R3081 registers. */ | |
496 | ||
497 | char *mips_r3081_reg_names[] = { | |
c906108c SS |
498 | "sr", "lo", "hi", "bad", "cause","pc", |
499 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
500 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
501 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
502 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 503 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
504 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", |
505 | "", "", "ehi", "", "", "", "epc", "prid", | |
506 | }; | |
507 | ||
508 | /* Names of LSI 33k registers. */ | |
509 | ||
510 | char *mips_lsi33k_reg_names[] = { | |
c906108c SS |
511 | "epc", "hi", "lo", "sr", "cause","badvaddr", |
512 | "dcic", "bpc", "bda", "", "", "", "", "", | |
513 | "", "", "", "", "", "", "", "", | |
514 | "", "", "", "", "", "", "", "", | |
515 | "", "", "", "", "", "", "", "", | |
516 | "", "", "", "", | |
517 | "", "", "", "", "", "", "", "", | |
518 | "", "", "", "", "", "", "", "", | |
519 | }; | |
520 | ||
521 | struct { | |
522 | char *name; | |
523 | char **regnames; | |
524 | } mips_processor_type_table[] = { | |
525 | { "generic", mips_generic_reg_names }, | |
526 | { "r3041", mips_r3041_reg_names }, | |
527 | { "r3051", mips_r3051_reg_names }, | |
528 | { "r3071", mips_r3081_reg_names }, | |
529 | { "r3081", mips_r3081_reg_names }, | |
530 | { "lsi33k", mips_lsi33k_reg_names }, | |
531 | { NULL, NULL } | |
532 | }; | |
9846de1b | 533 | /* *INDENT-ON* */ |
c906108c | 534 | |
a4b8ebc8 | 535 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 536 | |
a4b8ebc8 AC |
537 | static int |
538 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
539 | struct reggroup *reggroup) | |
540 | { | |
541 | int vector_p; | |
542 | int float_p; | |
543 | int raw_p; | |
544 | int rawnum = regnum % NUM_REGS; | |
545 | int pseudo = regnum / NUM_REGS; | |
546 | if (reggroup == all_reggroup) | |
547 | return pseudo; | |
548 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
549 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
550 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
551 | (gdbarch), as not all architectures are multi-arch. */ | |
552 | raw_p = rawnum < NUM_REGS; | |
553 | if (REGISTER_NAME (regnum) == NULL | |
554 | || REGISTER_NAME (regnum)[0] == '\0') | |
555 | return 0; | |
556 | if (reggroup == float_reggroup) | |
557 | return float_p && pseudo; | |
558 | if (reggroup == vector_reggroup) | |
559 | return vector_p && pseudo; | |
560 | if (reggroup == general_reggroup) | |
561 | return (!vector_p && !float_p) && pseudo; | |
562 | /* Save the pseudo registers. Need to make certain that any code | |
563 | extracting register values from a saved register cache also uses | |
564 | pseudo registers. */ | |
565 | if (reggroup == save_reggroup) | |
566 | return raw_p && pseudo; | |
567 | /* Restore the same pseudo register. */ | |
568 | if (reggroup == restore_reggroup) | |
569 | return raw_p && pseudo; | |
570 | return 0; | |
571 | } | |
572 | ||
573 | /* Map the symbol table registers which live in the range [1 * | |
574 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
575 | registers. */ | |
c5aa993b | 576 | |
a4b8ebc8 AC |
577 | static void |
578 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
579 | int cookednum, void *buf) | |
580 | { | |
581 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); | |
582 | return regcache_raw_read (regcache, cookednum % NUM_REGS, buf); | |
583 | } | |
584 | ||
585 | static void | |
586 | mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
587 | int cookednum, const void *buf) | |
588 | { | |
589 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); | |
590 | return regcache_raw_write (regcache, cookednum % NUM_REGS, buf); | |
591 | } | |
c5aa993b | 592 | |
c906108c | 593 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
594 | static int mips16_to_32_reg[8] = |
595 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
596 | |
597 | /* Heuristic_proc_start may hunt through the text section for a long | |
598 | time across a 2400 baud serial line. Allows the user to limit this | |
599 | search. */ | |
600 | ||
601 | static unsigned int heuristic_fence_post = 0; | |
602 | ||
c5aa993b JM |
603 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
604 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
605 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
606 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
607 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
608 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
609 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
610 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
611 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
612 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
613 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
614 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
615 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
616 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
617 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
618 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
619 | ||
620 | struct linked_proc_info | |
c5aa993b JM |
621 | { |
622 | struct mips_extra_func_info info; | |
623 | struct linked_proc_info *next; | |
624 | } | |
625 | *linked_proc_desc_table = NULL; | |
c906108c | 626 | |
46cd78fb AC |
627 | /* Number of bytes of storage in the actual machine representation for |
628 | register N. NOTE: This indirectly defines the register size | |
a4b8ebc8 | 629 | transfered by the GDB protocol. */ |
43e526b9 JM |
630 | |
631 | static int mips64_transfers_32bit_regs_p = 0; | |
632 | ||
f7ab6ec6 | 633 | static int |
a4b8ebc8 | 634 | mips_register_raw_size (int regnum) |
43e526b9 | 635 | { |
a4b8ebc8 AC |
636 | gdb_assert (regnum >= 0); |
637 | if (regnum < NUM_REGS) | |
638 | { | |
639 | /* For compatibility with old code, implemnt the broken register raw | |
640 | size map for the raw registers. | |
641 | ||
642 | NOTE: cagney/2003-06-15: This is so bogus. The register's | |
643 | raw size is changing according to the ABI | |
644 | (FP_REGISTER_DOUBLE). Also, GDB's protocol is defined by a | |
12c266ea | 645 | combination of DEPRECATED_REGISTER_RAW_SIZE and DEPRECATED_REGISTER_BYTE. */ |
a4b8ebc8 | 646 | if (mips64_transfers_32bit_regs_p) |
f30992d4 | 647 | return DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum); |
a4b8ebc8 AC |
648 | else if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32 |
649 | && FP_REGISTER_DOUBLE) | |
650 | /* For MIPS_ABI_N32 (for example) we need 8 byte floating point | |
651 | registers. */ | |
652 | return 8; | |
653 | else | |
654 | return MIPS_REGSIZE; | |
655 | } | |
656 | else if (regnum < 2 * NUM_REGS) | |
657 | { | |
658 | /* For the moment map [NUM_REGS .. 2*NUM_REGS) onto the same raw | |
659 | registers, but always return the virtual size. */ | |
660 | int rawnum = regnum % NUM_REGS; | |
5bbcb741 | 661 | return TYPE_LENGTH (gdbarch_register_type (current_gdbarch, rawnum)); |
a4b8ebc8 | 662 | } |
43e526b9 | 663 | else |
a4b8ebc8 AC |
664 | internal_error (__FILE__, __LINE__, "Register %d out of range", regnum); |
665 | } | |
666 | ||
667 | /* Register offset in a buffer for each register. | |
668 | ||
669 | FIXME: cagney/2003-06-15: This is so bogus. Instead REGISTER_TYPE | |
ce2826aa | 670 | should strictly return the layout of the buffer. Unfortunately |
a4b8ebc8 AC |
671 | remote.c and the MIPS have come to rely on a custom layout that |
672 | doesn't 1:1 map onto the register type. */ | |
673 | ||
674 | static int | |
675 | mips_register_byte (int regnum) | |
676 | { | |
677 | gdb_assert (regnum >= 0); | |
678 | if (regnum < NUM_REGS) | |
679 | /* Pick up the relevant per-tm file register byte method. */ | |
680 | return MIPS_REGISTER_BYTE (regnum); | |
681 | else if (regnum < 2 * NUM_REGS) | |
682 | { | |
683 | int reg; | |
684 | int byte; | |
685 | /* Start with the end of the raw register buffer - assum that | |
686 | MIPS_REGISTER_BYTE (NUM_REGS) returns that end. */ | |
687 | byte = MIPS_REGISTER_BYTE (NUM_REGS); | |
688 | /* Add space for all the proceeding registers based on their | |
689 | real size. */ | |
690 | for (reg = NUM_REGS; reg < regnum; reg++) | |
5bbcb741 JB |
691 | byte += TYPE_LENGTH (gdbarch_register_type (current_gdbarch, |
692 | (reg % NUM_REGS))); | |
a4b8ebc8 AC |
693 | return byte; |
694 | } | |
695 | else | |
696 | internal_error (__FILE__, __LINE__, "Register %d out of range", regnum); | |
43e526b9 JM |
697 | } |
698 | ||
46cd78fb AC |
699 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
700 | defines the remote-gdb packet. */ | |
701 | ||
d05285fa | 702 | static int |
acdb74a0 | 703 | mips_register_convertible (int reg_nr) |
43e526b9 JM |
704 | { |
705 | if (mips64_transfers_32bit_regs_p) | |
706 | return 0; | |
707 | else | |
12c266ea | 708 | return (DEPRECATED_REGISTER_RAW_SIZE (reg_nr) > DEPRECATED_REGISTER_VIRTUAL_SIZE (reg_nr)); |
43e526b9 JM |
709 | } |
710 | ||
d05285fa | 711 | static void |
acdb74a0 AC |
712 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
713 | char *raw_buf, char *virt_buf) | |
43e526b9 | 714 | { |
d7449b42 | 715 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 | 716 | memcpy (virt_buf, |
12c266ea | 717 | raw_buf + (DEPRECATED_REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
43e526b9 JM |
718 | TYPE_LENGTH (virtual_type)); |
719 | else | |
720 | memcpy (virt_buf, | |
721 | raw_buf, | |
722 | TYPE_LENGTH (virtual_type)); | |
723 | } | |
724 | ||
d05285fa | 725 | static void |
acdb74a0 | 726 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
781a750d | 727 | const char *virt_buf, char *raw_buf) |
43e526b9 | 728 | { |
12c266ea | 729 | memset (raw_buf, 0, DEPRECATED_REGISTER_RAW_SIZE (n)); |
d7449b42 | 730 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
12c266ea | 731 | memcpy (raw_buf + (DEPRECATED_REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
43e526b9 JM |
732 | virt_buf, |
733 | TYPE_LENGTH (virtual_type)); | |
734 | else | |
735 | memcpy (raw_buf, | |
736 | virt_buf, | |
737 | TYPE_LENGTH (virtual_type)); | |
738 | } | |
739 | ||
ff2e87ac AC |
740 | static int |
741 | mips_convert_register_p (int regnum, struct type *type) | |
742 | { | |
743 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
12c266ea | 744 | && DEPRECATED_REGISTER_RAW_SIZE (regnum) == 4 |
ff2e87ac AC |
745 | && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32 |
746 | && TYPE_CODE(type) == TYPE_CODE_FLT | |
747 | && TYPE_LENGTH(type) == 8); | |
748 | } | |
749 | ||
42c466d7 | 750 | static void |
ff2e87ac AC |
751 | mips_register_to_value (struct frame_info *frame, int regnum, |
752 | struct type *type, void *to) | |
102182a9 | 753 | { |
7f5f525d AC |
754 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
755 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
756 | } |
757 | ||
42c466d7 | 758 | static void |
ff2e87ac AC |
759 | mips_value_to_register (struct frame_info *frame, int regnum, |
760 | struct type *type, const void *from) | |
102182a9 | 761 | { |
ff2e87ac AC |
762 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
763 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
764 | } |
765 | ||
a4b8ebc8 AC |
766 | /* Return the GDB type object for the "standard" data type of data in |
767 | register REG. */ | |
78fde5f8 KB |
768 | |
769 | static struct type * | |
a4b8ebc8 AC |
770 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
771 | { | |
772 | /* For moment, map [NUM_REGS .. 2*NUM_REGS) onto the same raw | |
773 | registers. Even return the same type. */ | |
774 | int rawnum = regnum % NUM_REGS; | |
775 | gdb_assert (rawnum >= 0 && rawnum < NUM_REGS); | |
776 | #ifdef MIPS_REGISTER_TYPE | |
777 | return MIPS_REGISTER_TYPE (rawnum); | |
778 | #else | |
779 | if (FP0_REGNUM <= rawnum && rawnum < FP0_REGNUM + 32) | |
a6425924 KB |
780 | { |
781 | /* Floating point registers... */ | |
782 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
783 | return builtin_type_ieee_double_big; | |
784 | else | |
785 | return builtin_type_ieee_double_little; | |
786 | } | |
a4b8ebc8 | 787 | else if (rawnum == PS_REGNUM /* CR */) |
78fde5f8 | 788 | return builtin_type_uint32; |
a4b8ebc8 | 789 | else if (FCRCS_REGNUM <= rawnum && rawnum <= LAST_EMBED_REGNUM) |
78fde5f8 KB |
790 | return builtin_type_uint32; |
791 | else | |
792 | { | |
a6425924 KB |
793 | /* Everything else... |
794 | Return type appropriate for width of register. */ | |
795 | if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64)) | |
796 | return builtin_type_uint64; | |
78fde5f8 | 797 | else |
a6425924 | 798 | return builtin_type_uint32; |
78fde5f8 | 799 | } |
a4b8ebc8 | 800 | #endif |
78fde5f8 KB |
801 | } |
802 | ||
bcb0cc15 MS |
803 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
804 | ||
805 | static CORE_ADDR | |
806 | mips_read_sp (void) | |
807 | { | |
e227b13c | 808 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
809 | } |
810 | ||
c906108c | 811 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 812 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
813 | |
814 | static int | |
815 | mips_mask_address_p (void) | |
816 | { | |
817 | switch (mask_address_var) | |
818 | { | |
7f19b9a2 | 819 | case AUTO_BOOLEAN_TRUE: |
4014092b | 820 | return 1; |
7f19b9a2 | 821 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
822 | return 0; |
823 | break; | |
7f19b9a2 | 824 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 825 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 826 | default: |
8e65ff28 AC |
827 | internal_error (__FILE__, __LINE__, |
828 | "mips_mask_address_p: bad switch"); | |
4014092b | 829 | return -1; |
361d1df0 | 830 | } |
4014092b AC |
831 | } |
832 | ||
833 | static void | |
e9e68a56 | 834 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
835 | { |
836 | switch (mask_address_var) | |
837 | { | |
7f19b9a2 | 838 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
839 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
840 | break; | |
7f19b9a2 | 841 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
842 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
843 | break; | |
7f19b9a2 | 844 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
845 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
846 | mips_mask_address_p () ? "enabled" : "disabled"); | |
847 | break; | |
848 | default: | |
8e65ff28 AC |
849 | internal_error (__FILE__, __LINE__, |
850 | "show_mask_address: bad switch"); | |
4014092b | 851 | break; |
361d1df0 | 852 | } |
4014092b | 853 | } |
c906108c SS |
854 | |
855 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 856 | |
f7ab6ec6 | 857 | static int |
cb811fe7 | 858 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 859 | { |
cb811fe7 MS |
860 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
861 | } | |
862 | ||
f7ab6ec6 | 863 | static int |
cb811fe7 MS |
864 | mips_n32n64_use_struct_convention (int gcc_p, struct type *type) |
865 | { | |
b78bcb18 | 866 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
cb811fe7 MS |
867 | } |
868 | ||
8b389c40 MS |
869 | /* Should call_function pass struct by reference? |
870 | For each architecture, structs are passed either by | |
871 | value or by reference, depending on their size. */ | |
872 | ||
873 | static int | |
874 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
875 | { | |
876 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
877 | int len = TYPE_LENGTH (check_typedef (type)); | |
878 | ||
879 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
880 | return (len > MIPS_SAVED_REGSIZE); | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
885 | static int | |
886 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
887 | { | |
888 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
889 | } | |
890 | ||
f7ab6ec6 | 891 | static int |
8b389c40 MS |
892 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) |
893 | { | |
894 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
895 | } | |
896 | ||
c906108c SS |
897 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
898 | ||
899 | static int | |
900 | pc_is_mips16 (bfd_vma memaddr) | |
901 | { | |
902 | struct minimal_symbol *sym; | |
903 | ||
904 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 905 | if (is_mips16_addr (memaddr)) |
c906108c SS |
906 | return 1; |
907 | ||
908 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
909 | the high bit of the info field. Use this to decide if the function is | |
910 | MIPS16 or normal MIPS. */ | |
911 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
912 | if (sym) | |
71b8ef93 | 913 | return msymbol_is_special (sym); |
c906108c SS |
914 | else |
915 | return 0; | |
916 | } | |
917 | ||
6c997a34 AC |
918 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
919 | all registers should be sign extended for simplicity? */ | |
920 | ||
921 | static CORE_ADDR | |
39f77062 | 922 | mips_read_pc (ptid_t ptid) |
6c997a34 | 923 | { |
39f77062 | 924 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 925 | } |
c906108c SS |
926 | |
927 | /* This returns the PC of the first inst after the prologue. If we can't | |
928 | find the prologue, then return 0. */ | |
929 | ||
930 | static CORE_ADDR | |
acdb74a0 AC |
931 | after_prologue (CORE_ADDR pc, |
932 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
933 | { |
934 | struct symtab_and_line sal; | |
935 | CORE_ADDR func_addr, func_end; | |
936 | ||
479412cd DJ |
937 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
938 | to read the stack pointer from the current machine state, because | |
939 | the current machine state has nothing to do with the information | |
940 | we need from the proc_desc; and the process may or may not exist | |
941 | right now. */ | |
c906108c | 942 | if (!proc_desc) |
479412cd | 943 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
944 | |
945 | if (proc_desc) | |
946 | { | |
947 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 948 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
949 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
950 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
951 | return 0; | |
952 | } | |
953 | ||
954 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
955 | return 0; /* Unknown */ | |
956 | ||
957 | sal = find_pc_line (func_addr, 0); | |
958 | ||
959 | if (sal.end < func_end) | |
960 | return sal.end; | |
961 | ||
962 | /* The line after the prologue is after the end of the function. In this | |
963 | case, tell the caller to find the prologue the hard way. */ | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
969 | set the appropriate bit in the general register mask or float register mask | |
970 | to indicate which register is saved. This is a helper function | |
971 | for mips_find_saved_regs. */ | |
972 | ||
973 | static void | |
acdb74a0 AC |
974 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
975 | unsigned long *float_mask) | |
c906108c SS |
976 | { |
977 | int reg; | |
978 | ||
979 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
980 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
981 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
982 | { | |
983 | /* It might be possible to use the instruction to | |
c5aa993b JM |
984 | find the offset, rather than the code below which |
985 | is based on things being in a certain order in the | |
986 | frame, but figuring out what the instruction's offset | |
987 | is relative to might be a little tricky. */ | |
c906108c SS |
988 | reg = (inst & 0x001f0000) >> 16; |
989 | *gen_mask |= (1 << reg); | |
990 | } | |
991 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
992 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
993 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
994 | |
995 | { | |
996 | reg = ((inst & 0x001f0000) >> 16); | |
997 | *float_mask |= (1 << reg); | |
998 | } | |
999 | } | |
1000 | ||
1001 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
1002 | set the appropriate bit in the general register or float register mask | |
1003 | to indicate which register is saved. This is a helper function | |
1004 | for mips_find_saved_regs. */ | |
1005 | ||
1006 | static void | |
acdb74a0 | 1007 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 1008 | { |
c5aa993b | 1009 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
1010 | { |
1011 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1012 | *gen_mask |= (1 << reg); | |
1013 | } | |
c5aa993b | 1014 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
1015 | { |
1016 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1017 | *gen_mask |= (1 << reg); | |
1018 | } | |
c5aa993b | 1019 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
1020 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
1021 | *gen_mask |= (1 << RA_REGNUM); | |
1022 | } | |
1023 | ||
1024 | ||
1025 | /* Fetch and return instruction from the specified location. If the PC | |
1026 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
1027 | ||
1028 | static t_inst | |
acdb74a0 | 1029 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
1030 | { |
1031 | char buf[MIPS_INSTLEN]; | |
1032 | int instlen; | |
1033 | int status; | |
1034 | ||
1035 | if (pc_is_mips16 (addr)) | |
1036 | { | |
1037 | instlen = MIPS16_INSTLEN; | |
95404a3e | 1038 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1039 | } |
1040 | else | |
c5aa993b | 1041 | instlen = MIPS_INSTLEN; |
c906108c SS |
1042 | status = read_memory_nobpt (addr, buf, instlen); |
1043 | if (status) | |
1044 | memory_error (status, addr); | |
1045 | return extract_unsigned_integer (buf, instlen); | |
1046 | } | |
1047 | ||
1048 | ||
1049 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
1050 | #define mips32_op(x) (x >> 26) |
1051 | #define itype_op(x) (x >> 26) | |
1052 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1053 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1054 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1055 | |
e135b889 DJ |
1056 | #define jtype_op(x) (x >> 26) |
1057 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1058 | |
e135b889 DJ |
1059 | #define rtype_op(x) (x >> 26) |
1060 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1061 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1062 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1063 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1064 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
1065 | |
1066 | static CORE_ADDR | |
c5aa993b JM |
1067 | mips32_relative_offset (unsigned long inst) |
1068 | { | |
1069 | long x; | |
1070 | x = itype_immediate (inst); | |
1071 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 1072 | { |
c5aa993b | 1073 | x |= 0xffff0000; /* sign extension */ |
c906108c | 1074 | } |
c5aa993b JM |
1075 | x = x << 2; |
1076 | return x; | |
c906108c SS |
1077 | } |
1078 | ||
1079 | /* Determine whate to set a single step breakpoint while considering | |
1080 | branch prediction */ | |
5a89d8aa | 1081 | static CORE_ADDR |
c5aa993b JM |
1082 | mips32_next_pc (CORE_ADDR pc) |
1083 | { | |
1084 | unsigned long inst; | |
1085 | int op; | |
1086 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1087 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1088 | { |
e135b889 DJ |
1089 | if (itype_op (inst) >> 2 == 5) |
1090 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 1091 | { |
e135b889 | 1092 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1093 | switch (op) |
1094 | { | |
e135b889 DJ |
1095 | case 0: /* BEQL */ |
1096 | goto equal_branch; | |
1097 | case 1: /* BNEL */ | |
1098 | goto neq_branch; | |
1099 | case 2: /* BLEZL */ | |
1100 | goto less_branch; | |
1101 | case 3: /* BGTZ */ | |
1102 | goto greater_branch; | |
c5aa993b JM |
1103 | default: |
1104 | pc += 4; | |
c906108c SS |
1105 | } |
1106 | } | |
e135b889 DJ |
1107 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
1108 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
1109 | { | |
1110 | int tf = itype_rt (inst) & 0x01; | |
1111 | int cnum = itype_rt (inst) >> 2; | |
1112 | int fcrcs = read_signed_register (FCRCS_REGNUM); | |
1113 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); | |
1114 | ||
1115 | if (((cond >> cnum) & 0x01) == tf) | |
1116 | pc += mips32_relative_offset (inst) + 4; | |
1117 | else | |
1118 | pc += 8; | |
1119 | } | |
c5aa993b JM |
1120 | else |
1121 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1122 | } |
1123 | else | |
c5aa993b JM |
1124 | { /* This gets way messy */ |
1125 | ||
c906108c | 1126 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1127 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1128 | { |
c5aa993b JM |
1129 | case 0: /* SPECIAL */ |
1130 | op = rtype_funct (inst); | |
1131 | switch (op) | |
1132 | { | |
1133 | case 8: /* JR */ | |
1134 | case 9: /* JALR */ | |
6c997a34 AC |
1135 | /* Set PC to that address */ |
1136 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1137 | break; |
1138 | default: | |
1139 | pc += 4; | |
1140 | } | |
1141 | ||
e135b889 | 1142 | break; /* end SPECIAL */ |
c5aa993b | 1143 | case 1: /* REGIMM */ |
c906108c | 1144 | { |
e135b889 DJ |
1145 | op = itype_rt (inst); /* branch condition */ |
1146 | switch (op) | |
c906108c | 1147 | { |
c5aa993b | 1148 | case 0: /* BLTZ */ |
e135b889 DJ |
1149 | case 2: /* BLTZL */ |
1150 | case 16: /* BLTZAL */ | |
c5aa993b | 1151 | case 18: /* BLTZALL */ |
c906108c | 1152 | less_branch: |
6c997a34 | 1153 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1154 | pc += mips32_relative_offset (inst) + 4; |
1155 | else | |
1156 | pc += 8; /* after the delay slot */ | |
1157 | break; | |
e135b889 | 1158 | case 1: /* BGEZ */ |
c5aa993b JM |
1159 | case 3: /* BGEZL */ |
1160 | case 17: /* BGEZAL */ | |
1161 | case 19: /* BGEZALL */ | |
c906108c | 1162 | greater_equal_branch: |
6c997a34 | 1163 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1164 | pc += mips32_relative_offset (inst) + 4; |
1165 | else | |
1166 | pc += 8; /* after the delay slot */ | |
1167 | break; | |
e135b889 | 1168 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1169 | default: |
1170 | pc += 4; | |
c906108c SS |
1171 | } |
1172 | } | |
e135b889 | 1173 | break; /* end REGIMM */ |
c5aa993b JM |
1174 | case 2: /* J */ |
1175 | case 3: /* JAL */ | |
1176 | { | |
1177 | unsigned long reg; | |
1178 | reg = jtype_target (inst) << 2; | |
e135b889 | 1179 | /* Upper four bits get never changed... */ |
c5aa993b | 1180 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1181 | } |
c5aa993b JM |
1182 | break; |
1183 | /* FIXME case JALX : */ | |
1184 | { | |
1185 | unsigned long reg; | |
1186 | reg = jtype_target (inst) << 2; | |
1187 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1188 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1189 | } | |
c5aa993b | 1190 | break; /* The new PC will be alternate mode */ |
e135b889 | 1191 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1192 | equal_branch: |
6c997a34 AC |
1193 | if (read_signed_register (itype_rs (inst)) == |
1194 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1195 | pc += mips32_relative_offset (inst) + 4; |
1196 | else | |
1197 | pc += 8; | |
1198 | break; | |
e135b889 | 1199 | case 5: /* BNE, BNEL */ |
c5aa993b | 1200 | neq_branch: |
6c997a34 | 1201 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1202 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1203 | pc += mips32_relative_offset (inst) + 4; |
1204 | else | |
1205 | pc += 8; | |
1206 | break; | |
e135b889 | 1207 | case 6: /* BLEZ, BLEZL */ |
c906108c | 1208 | less_zero_branch: |
6c997a34 | 1209 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1210 | pc += mips32_relative_offset (inst) + 4; |
1211 | else | |
1212 | pc += 8; | |
1213 | break; | |
1214 | case 7: | |
e135b889 DJ |
1215 | default: |
1216 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1217 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1218 | pc += mips32_relative_offset (inst) + 4; |
1219 | else | |
1220 | pc += 8; | |
1221 | break; | |
c5aa993b JM |
1222 | } /* switch */ |
1223 | } /* else */ | |
1224 | return pc; | |
1225 | } /* mips32_next_pc */ | |
c906108c SS |
1226 | |
1227 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1228 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1229 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1230 | We dont want to set a single step instruction on the extend instruction | |
1231 | either. | |
c5aa993b | 1232 | */ |
c906108c SS |
1233 | |
1234 | /* Lots of mips16 instruction formats */ | |
1235 | /* Predicting jumps requires itype,ritype,i8type | |
1236 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1237 | */ |
c906108c SS |
1238 | enum mips16_inst_fmts |
1239 | { | |
c5aa993b JM |
1240 | itype, /* 0 immediate 5,10 */ |
1241 | ritype, /* 1 5,3,8 */ | |
1242 | rrtype, /* 2 5,3,3,5 */ | |
1243 | rritype, /* 3 5,3,3,5 */ | |
1244 | rrrtype, /* 4 5,3,3,3,2 */ | |
1245 | rriatype, /* 5 5,3,3,1,4 */ | |
1246 | shifttype, /* 6 5,3,3,3,2 */ | |
1247 | i8type, /* 7 5,3,8 */ | |
1248 | i8movtype, /* 8 5,3,3,5 */ | |
1249 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1250 | i64type, /* 10 5,3,8 */ | |
1251 | ri64type, /* 11 5,3,3,5 */ | |
1252 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1253 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1254 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1255 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1256 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1257 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1258 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1259 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1260 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1261 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1262 | }; | |
12f02c2a AC |
1263 | /* I am heaping all the fields of the formats into one structure and |
1264 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1265 | struct upk_mips16 |
c5aa993b | 1266 | { |
12f02c2a | 1267 | CORE_ADDR offset; |
c5aa993b JM |
1268 | unsigned int regx; /* Function in i8 type */ |
1269 | unsigned int regy; | |
1270 | }; | |
c906108c SS |
1271 | |
1272 | ||
12f02c2a AC |
1273 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1274 | for the bits which make up the immediatate extension. */ | |
c906108c | 1275 | |
12f02c2a AC |
1276 | static CORE_ADDR |
1277 | extended_offset (unsigned int extension) | |
c906108c | 1278 | { |
12f02c2a | 1279 | CORE_ADDR value; |
c5aa993b JM |
1280 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1281 | value = value << 6; | |
1282 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1283 | value = value << 5; | |
1284 | value |= extension & 0x01f; /* extract 4:0 */ | |
1285 | return value; | |
c906108c SS |
1286 | } |
1287 | ||
1288 | /* Only call this function if you know that this is an extendable | |
1289 | instruction, It wont malfunction, but why make excess remote memory references? | |
1290 | If the immediate operands get sign extended or somthing, do it after | |
1291 | the extension is performed. | |
c5aa993b | 1292 | */ |
c906108c SS |
1293 | /* FIXME: Every one of these cases needs to worry about sign extension |
1294 | when the offset is to be used in relative addressing */ | |
1295 | ||
1296 | ||
12f02c2a | 1297 | static unsigned int |
c5aa993b | 1298 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1299 | { |
c5aa993b JM |
1300 | char buf[8]; |
1301 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1302 | target_read_memory (pc, buf, 2); | |
1303 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1304 | } |
1305 | ||
1306 | static void | |
c5aa993b | 1307 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1308 | unsigned int extension, |
1309 | unsigned int inst, | |
1310 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1311 | struct upk_mips16 *upk) |
c906108c | 1312 | { |
12f02c2a AC |
1313 | CORE_ADDR offset; |
1314 | int regx; | |
1315 | int regy; | |
1316 | switch (insn_format) | |
c906108c | 1317 | { |
c5aa993b | 1318 | case itype: |
c906108c | 1319 | { |
12f02c2a AC |
1320 | CORE_ADDR value; |
1321 | if (extension) | |
c5aa993b JM |
1322 | { |
1323 | value = extended_offset (extension); | |
1324 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1325 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1326 | } |
1327 | else | |
c5aa993b | 1328 | { |
12f02c2a | 1329 | value = inst & 0x7ff; |
c5aa993b | 1330 | /* FIXME : Consider sign extension */ |
c906108c | 1331 | } |
12f02c2a AC |
1332 | offset = value; |
1333 | regx = -1; | |
1334 | regy = -1; | |
c906108c | 1335 | } |
c5aa993b JM |
1336 | break; |
1337 | case ritype: | |
1338 | case i8type: | |
1339 | { /* A register identifier and an offset */ | |
c906108c SS |
1340 | /* Most of the fields are the same as I type but the |
1341 | immediate value is of a different length */ | |
12f02c2a AC |
1342 | CORE_ADDR value; |
1343 | if (extension) | |
c906108c | 1344 | { |
c5aa993b JM |
1345 | value = extended_offset (extension); |
1346 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1347 | value |= inst & 0xff; /* eleven bits from instruction */ |
1348 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1349 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1350 | { | |
1351 | value &= ~0x3fff; /* remove the sign bit */ | |
1352 | value = -value; | |
c906108c SS |
1353 | } |
1354 | } | |
c5aa993b JM |
1355 | else |
1356 | { | |
12f02c2a AC |
1357 | value = inst & 0xff; /* 8 bits */ |
1358 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1359 | /* FIXME: Do sign extension , this format needs it */ |
1360 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1361 | { | |
1362 | value &= 0xef; /* remove the sign bit */ | |
1363 | value = -value; | |
1364 | } | |
c5aa993b | 1365 | } |
12f02c2a AC |
1366 | offset = value; |
1367 | regy = -1; | |
c5aa993b | 1368 | break; |
c906108c | 1369 | } |
c5aa993b | 1370 | case jalxtype: |
c906108c | 1371 | { |
c5aa993b | 1372 | unsigned long value; |
12f02c2a AC |
1373 | unsigned int nexthalf; |
1374 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1375 | value = value << 16; |
1376 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1377 | value |= nexthalf; | |
12f02c2a AC |
1378 | offset = value; |
1379 | regx = -1; | |
1380 | regy = -1; | |
c5aa993b | 1381 | break; |
c906108c SS |
1382 | } |
1383 | default: | |
8e65ff28 AC |
1384 | internal_error (__FILE__, __LINE__, |
1385 | "bad switch"); | |
c906108c | 1386 | } |
12f02c2a AC |
1387 | upk->offset = offset; |
1388 | upk->regx = regx; | |
1389 | upk->regy = regy; | |
c906108c SS |
1390 | } |
1391 | ||
1392 | ||
c5aa993b JM |
1393 | static CORE_ADDR |
1394 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1395 | { |
c5aa993b | 1396 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1397 | } |
1398 | ||
12f02c2a AC |
1399 | static CORE_ADDR |
1400 | extended_mips16_next_pc (CORE_ADDR pc, | |
1401 | unsigned int extension, | |
1402 | unsigned int insn) | |
c906108c | 1403 | { |
12f02c2a AC |
1404 | int op = (insn >> 11); |
1405 | switch (op) | |
c906108c | 1406 | { |
12f02c2a AC |
1407 | case 2: /* Branch */ |
1408 | { | |
1409 | CORE_ADDR offset; | |
1410 | struct upk_mips16 upk; | |
1411 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1412 | offset = upk.offset; | |
1413 | if (offset & 0x800) | |
1414 | { | |
1415 | offset &= 0xeff; | |
1416 | offset = -offset; | |
1417 | } | |
1418 | pc += (offset << 1) + 2; | |
1419 | break; | |
1420 | } | |
1421 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1422 | { | |
1423 | struct upk_mips16 upk; | |
1424 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1425 | pc = add_offset_16 (pc, upk.offset); | |
1426 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1427 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1428 | else | |
1429 | pc |= 0x01; | |
1430 | break; | |
1431 | } | |
1432 | case 4: /* beqz */ | |
1433 | { | |
1434 | struct upk_mips16 upk; | |
1435 | int reg; | |
1436 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1437 | reg = read_signed_register (upk.regx); | |
1438 | if (reg == 0) | |
1439 | pc += (upk.offset << 1) + 2; | |
1440 | else | |
1441 | pc += 2; | |
1442 | break; | |
1443 | } | |
1444 | case 5: /* bnez */ | |
1445 | { | |
1446 | struct upk_mips16 upk; | |
1447 | int reg; | |
1448 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1449 | reg = read_signed_register (upk.regx); | |
1450 | if (reg != 0) | |
1451 | pc += (upk.offset << 1) + 2; | |
1452 | else | |
1453 | pc += 2; | |
1454 | break; | |
1455 | } | |
1456 | case 12: /* I8 Formats btez btnez */ | |
1457 | { | |
1458 | struct upk_mips16 upk; | |
1459 | int reg; | |
1460 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1461 | /* upk.regx contains the opcode */ | |
1462 | reg = read_signed_register (24); /* Test register is 24 */ | |
1463 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1464 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1465 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1466 | pc += (upk.offset << 1) + 2; | |
1467 | else | |
1468 | pc += 2; | |
1469 | break; | |
1470 | } | |
1471 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1472 | { | |
1473 | struct upk_mips16 upk; | |
1474 | /* upk.fmt = rrtype; */ | |
1475 | op = insn & 0x1f; | |
1476 | if (op == 0) | |
c5aa993b | 1477 | { |
12f02c2a AC |
1478 | int reg; |
1479 | upk.regx = (insn >> 8) & 0x07; | |
1480 | upk.regy = (insn >> 5) & 0x07; | |
1481 | switch (upk.regy) | |
c5aa993b | 1482 | { |
12f02c2a AC |
1483 | case 0: |
1484 | reg = upk.regx; | |
1485 | break; | |
1486 | case 1: | |
1487 | reg = 31; | |
1488 | break; /* Function return instruction */ | |
1489 | case 2: | |
1490 | reg = upk.regx; | |
1491 | break; | |
1492 | default: | |
1493 | reg = 31; | |
1494 | break; /* BOGUS Guess */ | |
c906108c | 1495 | } |
12f02c2a | 1496 | pc = read_signed_register (reg); |
c906108c | 1497 | } |
12f02c2a | 1498 | else |
c5aa993b | 1499 | pc += 2; |
12f02c2a AC |
1500 | break; |
1501 | } | |
1502 | case 30: | |
1503 | /* This is an instruction extension. Fetch the real instruction | |
1504 | (which follows the extension) and decode things based on | |
1505 | that. */ | |
1506 | { | |
1507 | pc += 2; | |
1508 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1509 | break; | |
1510 | } | |
1511 | default: | |
1512 | { | |
1513 | pc += 2; | |
1514 | break; | |
1515 | } | |
c906108c | 1516 | } |
c5aa993b | 1517 | return pc; |
12f02c2a | 1518 | } |
c906108c | 1519 | |
5a89d8aa | 1520 | static CORE_ADDR |
12f02c2a AC |
1521 | mips16_next_pc (CORE_ADDR pc) |
1522 | { | |
1523 | unsigned int insn = fetch_mips_16 (pc); | |
1524 | return extended_mips16_next_pc (pc, 0, insn); | |
1525 | } | |
1526 | ||
1527 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1528 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1529 | It works by decoding the current instruction and predicting where a |
1530 | branch will go. This isnt hard because all the data is available. | |
1531 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1532 | CORE_ADDR |
1533 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1534 | { |
c5aa993b JM |
1535 | if (pc & 0x01) |
1536 | return mips16_next_pc (pc); | |
1537 | else | |
1538 | return mips32_next_pc (pc); | |
12f02c2a | 1539 | } |
c906108c | 1540 | |
e0f7ec59 AC |
1541 | /* Set up the 'saved_regs' array. This is a data structure containing |
1542 | the addresses on the stack where each register has been saved, for | |
1543 | each stack frame. Registers that have not been saved will have | |
1544 | zero here. The stack pointer register is special: rather than the | |
1545 | address where the stack register has been saved, | |
1546 | saved_regs[SP_REGNUM] will have the actual value of the previous | |
1547 | frame's stack register. */ | |
c906108c | 1548 | |
d28e01f4 | 1549 | static void |
acdb74a0 | 1550 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1551 | { |
1552 | int ireg; | |
c906108c SS |
1553 | /* r0 bit means kernel trap */ |
1554 | int kernel_trap; | |
1555 | /* What registers have been saved? Bitmasks. */ | |
1556 | unsigned long gen_mask, float_mask; | |
1557 | mips_extra_func_info_t proc_desc; | |
1558 | t_inst inst; | |
e0f7ec59 | 1559 | CORE_ADDR *saved_regs; |
c906108c | 1560 | |
1b1d3794 | 1561 | if (deprecated_get_frame_saved_regs (fci) != NULL) |
e0f7ec59 AC |
1562 | return; |
1563 | saved_regs = frame_saved_regs_zalloc (fci); | |
c906108c SS |
1564 | |
1565 | /* If it is the frame for sigtramp, the saved registers are located | |
e0f7ec59 AC |
1566 | in a sigcontext structure somewhere on the stack. If the stack |
1567 | layout for sigtramp changes we might have to change these | |
1568 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
c906108c | 1569 | #ifndef SIGFRAME_BASE |
e0f7ec59 AC |
1570 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
1571 | above the sigtramp frame. */ | |
c906108c SS |
1572 | #define SIGFRAME_BASE MIPS_REGSIZE |
1573 | /* FIXME! Are these correct?? */ | |
1574 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1575 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1576 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1577 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1578 | #endif | |
1579 | #ifndef SIGFRAME_REG_SIZE | |
e0f7ec59 | 1580 | /* FIXME! Is this correct?? */ |
c906108c SS |
1581 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE |
1582 | #endif | |
5a203e44 | 1583 | if ((get_frame_type (fci) == SIGTRAMP_FRAME)) |
c906108c SS |
1584 | { |
1585 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1586 | { | |
e0f7ec59 AC |
1587 | CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF |
1588 | + ireg * SIGFRAME_REG_SIZE); | |
1589 | set_reg_offset (saved_regs, ireg, reg_position); | |
c906108c SS |
1590 | } |
1591 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1592 | { | |
e0f7ec59 AC |
1593 | CORE_ADDR reg_position = (get_frame_base (fci) |
1594 | + SIGFRAME_FPREGSAVE_OFF | |
1595 | + ireg * SIGFRAME_REG_SIZE); | |
1596 | set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position); | |
c906108c | 1597 | } |
e0f7ec59 AC |
1598 | |
1599 | set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF); | |
1600 | /* SP_REGNUM, contains the value and not the address. */ | |
1601 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
c906108c SS |
1602 | return; |
1603 | } | |
1604 | ||
da50a4b7 | 1605 | proc_desc = get_frame_extra_info (fci)->proc_desc; |
c906108c | 1606 | if (proc_desc == NULL) |
e0f7ec59 AC |
1607 | /* I'm not sure how/whether this can happen. Normally when we |
1608 | can't find a proc_desc, we "synthesize" one using | |
1609 | heuristic_proc_desc and set the saved_regs right away. */ | |
c906108c SS |
1610 | return; |
1611 | ||
c5aa993b JM |
1612 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1613 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1614 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1615 | |
e0f7ec59 AC |
1616 | if (/* In any frame other than the innermost or a frame interrupted |
1617 | by a signal, we assume that all registers have been saved. | |
1618 | This assumes that all register saves in a function happen | |
1619 | before the first function call. */ | |
11c02a10 AC |
1620 | (get_next_frame (fci) == NULL |
1621 | || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) | |
c906108c | 1622 | |
e0f7ec59 | 1623 | /* In a dummy frame we know exactly where things are saved. */ |
c5aa993b | 1624 | && !PROC_DESC_IS_DUMMY (proc_desc) |
c906108c | 1625 | |
e0f7ec59 AC |
1626 | /* Don't bother unless we are inside a function prologue. |
1627 | Outside the prologue, we know where everything is. */ | |
c906108c | 1628 | |
50abf9e5 | 1629 | && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc)) |
c906108c | 1630 | |
e0f7ec59 AC |
1631 | /* Not sure exactly what kernel_trap means, but if it means the |
1632 | kernel saves the registers without a prologue doing it, we | |
1633 | better not examine the prologue to see whether registers | |
1634 | have been saved yet. */ | |
c5aa993b | 1635 | && !kernel_trap) |
c906108c | 1636 | { |
e0f7ec59 AC |
1637 | /* We need to figure out whether the registers that the |
1638 | proc_desc claims are saved have been saved yet. */ | |
c906108c SS |
1639 | |
1640 | CORE_ADDR addr; | |
1641 | ||
1642 | /* Bitmasks; set if we have found a save for the register. */ | |
1643 | unsigned long gen_save_found = 0; | |
1644 | unsigned long float_save_found = 0; | |
1645 | int instlen; | |
1646 | ||
1647 | /* If the address is odd, assume this is MIPS16 code. */ | |
1648 | addr = PROC_LOW_ADDR (proc_desc); | |
1649 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1650 | ||
e0f7ec59 AC |
1651 | /* Scan through this function's instructions preceding the |
1652 | current PC, and look for those that save registers. */ | |
50abf9e5 | 1653 | while (addr < get_frame_pc (fci)) |
c906108c SS |
1654 | { |
1655 | inst = mips_fetch_instruction (addr); | |
1656 | if (pc_is_mips16 (addr)) | |
1657 | mips16_decode_reg_save (inst, &gen_save_found); | |
1658 | else | |
1659 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1660 | addr += instlen; | |
1661 | } | |
1662 | gen_mask = gen_save_found; | |
1663 | float_mask = float_save_found; | |
1664 | } | |
1665 | ||
e0f7ec59 AC |
1666 | /* Fill in the offsets for the registers which gen_mask says were |
1667 | saved. */ | |
1668 | { | |
1669 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1670 | + PROC_REG_OFFSET (proc_desc)); | |
1671 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1672 | if (gen_mask & 0x80000000) | |
1673 | { | |
1674 | set_reg_offset (saved_regs, ireg, reg_position); | |
1675 | reg_position -= MIPS_SAVED_REGSIZE; | |
1676 | } | |
1677 | } | |
c906108c | 1678 | |
e0f7ec59 AC |
1679 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse |
1680 | order of that normally used by gcc. Therefore, we have to fetch | |
1681 | the first instruction of the function, and if it's an entry | |
1682 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
c906108c SS |
1683 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
1684 | { | |
1685 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
e0f7ec59 AC |
1686 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) |
1687 | /* entry */ | |
c906108c SS |
1688 | { |
1689 | int reg; | |
1690 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1691 | |
c906108c | 1692 | /* Check if the ra register was pushed on the stack. */ |
e0f7ec59 AC |
1693 | CORE_ADDR reg_position = (get_frame_base (fci) |
1694 | + PROC_REG_OFFSET (proc_desc)); | |
c906108c | 1695 | if (inst & 0x20) |
7a292a7a | 1696 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c | 1697 | |
e0f7ec59 AC |
1698 | /* Check if the s0 and s1 registers were pushed on the |
1699 | stack. */ | |
c5aa993b | 1700 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c | 1701 | { |
e0f7ec59 | 1702 | set_reg_offset (saved_regs, reg, reg_position); |
7a292a7a | 1703 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1704 | } |
1705 | } | |
1706 | } | |
1707 | ||
e0f7ec59 AC |
1708 | /* Fill in the offsets for the registers which float_mask says were |
1709 | saved. */ | |
1710 | { | |
1711 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1712 | + PROC_FREG_OFFSET (proc_desc)); | |
6acdf5c7 | 1713 | |
e0f7ec59 AC |
1714 | /* Fill in the offsets for the float registers which float_mask |
1715 | says were saved. */ | |
1716 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1717 | if (float_mask & 0x80000000) | |
1718 | { | |
c57bb9fa AC |
1719 | if (MIPS_SAVED_REGSIZE == 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1720 | { | |
1721 | /* On a big endian 32 bit ABI, floating point registers | |
1722 | are paired to form doubles such that the most | |
1723 | significant part is in $f[N+1] and the least | |
1724 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1725 | registers are also spilled as a pair and stored as a | |
1726 | double. | |
1727 | ||
1728 | When little-endian the least significant part is | |
1729 | stored first leading to the memory order $f[N] and | |
1730 | then $f[N+1]. | |
1731 | ||
ce2826aa | 1732 | Unfortunately, when big-endian the most significant |
c57bb9fa AC |
1733 | part of the double is stored first, and the least |
1734 | significant is stored second. This leads to the | |
1735 | registers being ordered in memory as firt $f[N+1] and | |
1736 | then $f[N]. | |
1737 | ||
1738 | For the big-endian case make certain that the | |
1739 | addresses point at the correct (swapped) locations | |
1740 | $f[N] and $f[N+1] pair (keep in mind that | |
1741 | reg_position is decremented each time through the | |
1742 | loop). */ | |
1743 | if ((ireg & 1)) | |
1744 | set_reg_offset (saved_regs, FP0_REGNUM + ireg, | |
1745 | reg_position - MIPS_SAVED_REGSIZE); | |
1746 | else | |
1747 | set_reg_offset (saved_regs, FP0_REGNUM + ireg, | |
1748 | reg_position + MIPS_SAVED_REGSIZE); | |
1749 | } | |
1750 | else | |
1751 | set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position); | |
e0f7ec59 AC |
1752 | reg_position -= MIPS_SAVED_REGSIZE; |
1753 | } | |
c906108c | 1754 | |
e0f7ec59 AC |
1755 | set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]); |
1756 | } | |
d28e01f4 | 1757 | |
e0f7ec59 AC |
1758 | /* SP_REGNUM, contains the value and not the address. */ |
1759 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
d28e01f4 KB |
1760 | } |
1761 | ||
c906108c | 1762 | static CORE_ADDR |
acdb74a0 | 1763 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1764 | { |
a4b8ebc8 AC |
1765 | /* Always a pseudo. */ |
1766 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 1767 | if (fi == NULL) |
c906108c | 1768 | { |
a4b8ebc8 AC |
1769 | LONGEST val; |
1770 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
1771 | return val; | |
f796e4be | 1772 | } |
a4b8ebc8 AC |
1773 | else if ((regno % NUM_REGS) == SP_REGNUM) |
1774 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
1775 | In fact, it is so special that it can even only be fetched | |
1776 | using a raw register number! Once this code as been converted | |
1777 | to frame-unwind the problem goes away. */ | |
1778 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 1779 | else |
a4b8ebc8 | 1780 | return frame_unwind_register_signed (fi, regno); |
64159455 | 1781 | |
c906108c SS |
1782 | } |
1783 | ||
1784 | /* mips_addr_bits_remove - remove useless address bits */ | |
1785 | ||
875e1767 | 1786 | static CORE_ADDR |
acdb74a0 | 1787 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1788 | { |
5213ab06 AC |
1789 | if (GDB_TARGET_IS_MIPS64) |
1790 | { | |
4014092b | 1791 | if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
5213ab06 AC |
1792 | { |
1793 | /* This hack is a work-around for existing boards using | |
1794 | PMON, the simulator, and any other 64-bit targets that | |
1795 | doesn't have true 64-bit addressing. On these targets, | |
1796 | the upper 32 bits of addresses are ignored by the | |
1797 | hardware. Thus, the PC or SP are likely to have been | |
1798 | sign extended to all 1s by instruction sequences that | |
1799 | load 32-bit addresses. For example, a typical piece of | |
4014092b AC |
1800 | code that loads an address is this: |
1801 | lui $r2, <upper 16 bits> | |
1802 | ori $r2, <lower 16 bits> | |
1803 | But the lui sign-extends the value such that the upper 32 | |
1804 | bits may be all 1s. The workaround is simply to mask off | |
1805 | these bits. In the future, gcc may be changed to support | |
1806 | true 64-bit addressing, and this masking will have to be | |
1807 | disabled. */ | |
5213ab06 AC |
1808 | addr &= (CORE_ADDR) 0xffffffff; |
1809 | } | |
1810 | } | |
4014092b | 1811 | else if (mips_mask_address_p ()) |
5213ab06 | 1812 | { |
4014092b AC |
1813 | /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be |
1814 | masking off bits, instead, the actual target should be asking | |
1815 | for the address to be converted to a valid pointer. */ | |
5213ab06 AC |
1816 | /* Even when GDB is configured for some 32-bit targets |
1817 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1818 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1819 | useless bits from addresses. */ | |
c5aa993b | 1820 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1821 | } |
c906108c SS |
1822 | return addr; |
1823 | } | |
1824 | ||
9022177c DJ |
1825 | /* mips_software_single_step() is called just before we want to resume |
1826 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1827 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1828 | the target of the coming instruction and breakpoint it. |
1829 | ||
1830 | single_step is also called just after the inferior stops. If we had | |
1831 | set up a simulated single-step, we undo our damage. */ | |
1832 | ||
1833 | void | |
1834 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1835 | { | |
1836 | static CORE_ADDR next_pc; | |
1837 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1838 | static binsn_quantum break_mem; | |
1839 | CORE_ADDR pc; | |
1840 | ||
1841 | if (insert_breakpoints_p) | |
1842 | { | |
1843 | pc = read_register (PC_REGNUM); | |
1844 | next_pc = mips_next_pc (pc); | |
1845 | ||
1846 | target_insert_breakpoint (next_pc, break_mem); | |
1847 | } | |
1848 | else | |
1849 | target_remove_breakpoint (next_pc, break_mem); | |
1850 | } | |
1851 | ||
97f46953 | 1852 | static CORE_ADDR |
acdb74a0 | 1853 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1854 | { |
1855 | CORE_ADDR pc, tmp; | |
1856 | ||
11c02a10 | 1857 | pc = ((fromleaf) |
6913c89a | 1858 | ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) |
11c02a10 | 1859 | : get_next_frame (prev) |
8bedc050 | 1860 | ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) |
11c02a10 | 1861 | : read_pc ()); |
5a89d8aa | 1862 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
97f46953 | 1863 | return tmp ? tmp : pc; |
c906108c SS |
1864 | } |
1865 | ||
1866 | ||
f7ab6ec6 | 1867 | static CORE_ADDR |
acdb74a0 | 1868 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1869 | { |
1870 | CORE_ADDR saved_pc; | |
c906108c | 1871 | |
50abf9e5 | 1872 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
1873 | { |
1874 | LONGEST tmp; | |
a4b8ebc8 AC |
1875 | /* Always unwind the cooked PC register value. */ |
1876 | frame_unwind_signed_register (frame, NUM_REGS + PC_REGNUM, &tmp); | |
cedea778 AC |
1877 | saved_pc = tmp; |
1878 | } | |
c906108c | 1879 | else |
a4b8ebc8 AC |
1880 | { |
1881 | mips_extra_func_info_t proc_desc | |
1882 | = get_frame_extra_info (frame)->proc_desc; | |
1883 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) | |
1884 | saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); | |
1885 | else | |
1886 | { | |
1887 | /* We have to get the saved pc from the sigcontext if it is | |
1888 | a signal handler frame. */ | |
1889 | int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME ? PC_REGNUM | |
1890 | : proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); | |
1891 | saved_pc = read_next_frame_reg (frame, NUM_REGS + pcreg); | |
1892 | } | |
1893 | } | |
c906108c SS |
1894 | return ADDR_BITS_REMOVE (saved_pc); |
1895 | } | |
1896 | ||
1897 | static struct mips_extra_func_info temp_proc_desc; | |
fe29b929 KB |
1898 | |
1899 | /* This hack will go away once the get_prev_frame() code has been | |
1900 | modified to set the frame's type first. That is BEFORE init extra | |
1901 | frame info et.al. is called. This is because it will become | |
1902 | possible to skip the init extra info call for sigtramp and dummy | |
1903 | frames. */ | |
1904 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1905 | |
e0f7ec59 AC |
1906 | /* Set a register's saved stack address in temp_saved_regs. If an |
1907 | address has already been set for this register, do nothing; this | |
1908 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
1909 | function prologue. |
1910 | ||
1911 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
1912 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1913 | is used as it is only second range (the ABI instead of ISA | |
1914 | registers) that comes into play when finding saved registers in a | |
1915 | frame. */ | |
c906108c SS |
1916 | |
1917 | static void | |
e0f7ec59 | 1918 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1919 | { |
e0f7ec59 | 1920 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
1921 | { |
1922 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
1923 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
1924 | } | |
c906108c SS |
1925 | } |
1926 | ||
1927 | ||
1928 | /* Test whether the PC points to the return instruction at the | |
1929 | end of a function. */ | |
1930 | ||
c5aa993b | 1931 | static int |
acdb74a0 | 1932 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1933 | { |
1934 | if (pc_is_mips16 (pc)) | |
1935 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1936 | generates a "jr $ra"; other times it generates code to load | |
1937 | the return address from the stack to an accessible register (such | |
1938 | as $a3), then a "jr" using that register. This second case | |
1939 | is almost impossible to distinguish from an indirect jump | |
1940 | used for switch statements, so we don't even try. */ | |
1941 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1942 | else | |
1943 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1944 | } | |
1945 | ||
1946 | ||
1947 | /* This fencepost looks highly suspicious to me. Removing it also | |
1948 | seems suspicious as it could affect remote debugging across serial | |
1949 | lines. */ | |
1950 | ||
1951 | static CORE_ADDR | |
acdb74a0 | 1952 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1953 | { |
c5aa993b JM |
1954 | CORE_ADDR start_pc; |
1955 | CORE_ADDR fence; | |
1956 | int instlen; | |
1957 | int seen_adjsp = 0; | |
c906108c | 1958 | |
c5aa993b JM |
1959 | pc = ADDR_BITS_REMOVE (pc); |
1960 | start_pc = pc; | |
1961 | fence = start_pc - heuristic_fence_post; | |
1962 | if (start_pc == 0) | |
1963 | return 0; | |
c906108c | 1964 | |
c5aa993b JM |
1965 | if (heuristic_fence_post == UINT_MAX |
1966 | || fence < VM_MIN_ADDRESS) | |
1967 | fence = VM_MIN_ADDRESS; | |
c906108c | 1968 | |
c5aa993b | 1969 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1970 | |
c5aa993b JM |
1971 | /* search back for previous return */ |
1972 | for (start_pc -= instlen;; start_pc -= instlen) | |
1973 | if (start_pc < fence) | |
1974 | { | |
1975 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1976 | stop_soon, but with this test, at least we |
c5aa993b JM |
1977 | don't print out warnings for every child forked (eg, on |
1978 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1979 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1980 | { |
c5aa993b JM |
1981 | static int blurb_printed = 0; |
1982 | ||
1983 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1984 | paddr_nz (pc)); | |
1985 | ||
1986 | if (!blurb_printed) | |
c906108c | 1987 | { |
c5aa993b JM |
1988 | /* This actually happens frequently in embedded |
1989 | development, when you first connect to a board | |
1990 | and your stack pointer and pc are nowhere in | |
1991 | particular. This message needs to give people | |
1992 | in that situation enough information to | |
1993 | determine that it's no big deal. */ | |
1994 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1995 | GDB is unable to find the start of the function at 0x%s\n\ |
1996 | and thus can't determine the size of that function's stack frame.\n\ | |
1997 | This means that GDB may be unable to access that stack frame, or\n\ | |
1998 | the frames below it.\n\ | |
1999 | This problem is most likely caused by an invalid program counter or\n\ | |
2000 | stack pointer.\n\ | |
2001 | However, if you think GDB should simply search farther back\n\ | |
2002 | from 0x%s for code which looks like the beginning of a\n\ | |
2003 | function, you can increase the range of the search using the `set\n\ | |
2004 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
2005 | paddr_nz (pc), paddr_nz (pc)); |
2006 | blurb_printed = 1; | |
c906108c | 2007 | } |
c906108c SS |
2008 | } |
2009 | ||
c5aa993b JM |
2010 | return 0; |
2011 | } | |
2012 | else if (pc_is_mips16 (start_pc)) | |
2013 | { | |
2014 | unsigned short inst; | |
2015 | ||
2016 | /* On MIPS16, any one of the following is likely to be the | |
2017 | start of a function: | |
2018 | entry | |
2019 | addiu sp,-n | |
2020 | daddiu sp,-n | |
2021 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2022 | inst = mips_fetch_instruction (start_pc); | |
2023 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2024 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2025 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2026 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2027 | break; | |
2028 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2029 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2030 | seen_adjsp = 1; | |
2031 | else | |
2032 | seen_adjsp = 0; | |
2033 | } | |
2034 | else if (mips_about_to_return (start_pc)) | |
2035 | { | |
2036 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
2037 | break; | |
2038 | } | |
2039 | ||
c5aa993b | 2040 | return start_pc; |
c906108c SS |
2041 | } |
2042 | ||
2043 | /* Fetch the immediate value from a MIPS16 instruction. | |
2044 | If the previous instruction was an EXTEND, use it to extend | |
2045 | the upper bits of the immediate value. This is a helper function | |
2046 | for mips16_heuristic_proc_desc. */ | |
2047 | ||
2048 | static int | |
acdb74a0 AC |
2049 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
2050 | unsigned short inst, /* current instruction */ | |
2051 | int nbits, /* number of bits in imm field */ | |
2052 | int scale, /* scale factor to be applied to imm */ | |
2053 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
2054 | { |
2055 | int offset; | |
2056 | ||
2057 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
2058 | { | |
2059 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 2060 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
2061 | offset = 0 - (0x10000 - (offset & 0xffff)); |
2062 | return offset | (inst & 0x1f); | |
2063 | } | |
2064 | else | |
2065 | { | |
2066 | int max_imm = 1 << nbits; | |
2067 | int mask = max_imm - 1; | |
2068 | int sign_bit = max_imm >> 1; | |
2069 | ||
2070 | offset = inst & mask; | |
2071 | if (is_signed && (offset & sign_bit)) | |
2072 | offset = 0 - (max_imm - offset); | |
2073 | return offset * scale; | |
2074 | } | |
2075 | } | |
2076 | ||
2077 | ||
2078 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
2079 | stream from start_pc to limit_pc. */ | |
2080 | ||
2081 | static void | |
acdb74a0 AC |
2082 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2083 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2084 | { |
2085 | CORE_ADDR cur_pc; | |
2086 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
2087 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
2088 | unsigned inst = 0; /* current instruction */ | |
2089 | unsigned entry_inst = 0; /* the entry instruction */ | |
2090 | int reg, offset; | |
2091 | ||
c5aa993b JM |
2092 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
2093 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
2094 | |
2095 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2096 | { | |
2097 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2098 | the immediate offset extension from it in mips16_get_imm. */ | |
2099 | prev_inst = inst; | |
2100 | ||
2101 | /* Fetch and decode the instruction. */ | |
2102 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2103 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
2104 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
2105 | { | |
2106 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2107 | if (offset < 0) /* negative stack adjustment? */ |
2108 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2109 | else |
2110 | /* Exit loop if a positive stack adjustment is found, which | |
2111 | usually means that the stack cleanup code in the function | |
2112 | epilogue is reached. */ | |
2113 | break; | |
2114 | } | |
2115 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2116 | { | |
2117 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2118 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2119 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2120 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2121 | } |
2122 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2123 | { | |
2124 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2125 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2126 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2127 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2128 | } |
2129 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2130 | { | |
2131 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2132 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2133 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2134 | } |
2135 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2136 | { | |
2137 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2138 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2139 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2140 | } |
c5aa993b | 2141 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2142 | { |
2143 | frame_addr = sp; | |
2144 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2145 | } | |
2146 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2147 | { | |
2148 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2149 | frame_addr = sp + offset; | |
2150 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2151 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2152 | } | |
2153 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2154 | { | |
2155 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2156 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2157 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2158 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2159 | } |
2160 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2161 | { | |
2162 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2163 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2164 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2165 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2166 | } |
c5aa993b JM |
2167 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2168 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2169 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2170 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2171 | } |
2172 | ||
c5aa993b JM |
2173 | /* The entry instruction is typically the first instruction in a function, |
2174 | and it stores registers at offsets relative to the value of the old SP | |
2175 | (before the prologue). But the value of the sp parameter to this | |
2176 | function is the new SP (after the prologue has been executed). So we | |
2177 | can't calculate those offsets until we've seen the entire prologue, | |
2178 | and can calculate what the old SP must have been. */ | |
2179 | if (entry_inst != 0) | |
2180 | { | |
2181 | int areg_count = (entry_inst >> 8) & 7; | |
2182 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2183 | |
c5aa993b JM |
2184 | /* The entry instruction always subtracts 32 from the SP. */ |
2185 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2186 | |
c5aa993b JM |
2187 | /* Now we can calculate what the SP must have been at the |
2188 | start of the function prologue. */ | |
2189 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2190 | |
c5aa993b JM |
2191 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2192 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2193 | { | |
2194 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2195 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2196 | offset += MIPS_SAVED_REGSIZE; |
2197 | } | |
c906108c | 2198 | |
c5aa993b JM |
2199 | /* Check if the ra register was pushed on the stack. */ |
2200 | offset = -4; | |
2201 | if (entry_inst & 0x20) | |
2202 | { | |
2203 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2204 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c5aa993b JM |
2205 | offset -= MIPS_SAVED_REGSIZE; |
2206 | } | |
c906108c | 2207 | |
c5aa993b JM |
2208 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2209 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2210 | { | |
2211 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2212 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2213 | offset -= MIPS_SAVED_REGSIZE; |
2214 | } | |
2215 | } | |
c906108c SS |
2216 | } |
2217 | ||
2218 | static void | |
fba45db2 KB |
2219 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2220 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2221 | { |
2222 | CORE_ADDR cur_pc; | |
c5aa993b | 2223 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2224 | restart: |
fe29b929 | 2225 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2226 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2227 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2228 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2229 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2230 | { | |
2231 | unsigned long inst, high_word, low_word; | |
2232 | int reg; | |
2233 | ||
2234 | /* Fetch the instruction. */ | |
2235 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2236 | ||
2237 | /* Save some code by pre-extracting some useful fields. */ | |
2238 | high_word = (inst >> 16) & 0xffff; | |
2239 | low_word = inst & 0xffff; | |
2240 | reg = high_word & 0x1f; | |
2241 | ||
c5aa993b | 2242 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2243 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2244 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2245 | { | |
2246 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2247 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2248 | else |
2249 | /* Exit loop if a positive stack adjustment is found, which | |
2250 | usually means that the stack cleanup code in the function | |
2251 | epilogue is reached. */ | |
2252 | break; | |
2253 | } | |
2254 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2255 | { | |
c5aa993b | 2256 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2257 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2258 | } |
2259 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2260 | { | |
2261 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2262 | but the register size used is only 32 bits. Make the address | |
2263 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2264 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2265 | set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - MIPS_REGSIZE); |
c906108c | 2266 | } |
c5aa993b | 2267 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2268 | { |
2269 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2270 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2271 | frame_addr = sp + low_word; | |
c906108c SS |
2272 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2273 | { | |
2274 | unsigned alloca_adjust; | |
2275 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2276 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2277 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2278 | if (alloca_adjust > 0) |
2279 | { | |
2280 | /* FP > SP + frame_size. This may be because | |
2281 | * of an alloca or somethings similar. | |
2282 | * Fix sp to "pre-alloca" value, and try again. | |
2283 | */ | |
2284 | sp += alloca_adjust; | |
2285 | goto restart; | |
2286 | } | |
2287 | } | |
2288 | } | |
c5aa993b JM |
2289 | /* move $30,$sp. With different versions of gas this will be either |
2290 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2291 | Accept any one of these. */ | |
c906108c SS |
2292 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2293 | { | |
2294 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2295 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2296 | { | |
2297 | unsigned alloca_adjust; | |
2298 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2299 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2300 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2301 | if (alloca_adjust > 0) |
2302 | { | |
2303 | /* FP > SP + frame_size. This may be because | |
2304 | * of an alloca or somethings similar. | |
2305 | * Fix sp to "pre-alloca" value, and try again. | |
2306 | */ | |
2307 | sp += alloca_adjust; | |
2308 | goto restart; | |
2309 | } | |
2310 | } | |
2311 | } | |
c5aa993b | 2312 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2313 | { |
c5aa993b | 2314 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2315 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2316 | } |
2317 | } | |
2318 | } | |
2319 | ||
2320 | static mips_extra_func_info_t | |
acdb74a0 | 2321 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2322 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2323 | { |
479412cd DJ |
2324 | CORE_ADDR sp; |
2325 | ||
2326 | if (cur_frame) | |
a4b8ebc8 | 2327 | sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); |
479412cd DJ |
2328 | else |
2329 | sp = 0; | |
c906108c | 2330 | |
c5aa993b JM |
2331 | if (start_pc == 0) |
2332 | return NULL; | |
2333 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2334 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2335 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2336 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2337 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2338 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2339 | ||
2340 | if (start_pc + 200 < limit_pc) | |
2341 | limit_pc = start_pc + 200; | |
2342 | if (pc_is_mips16 (start_pc)) | |
2343 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2344 | else | |
2345 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2346 | return &temp_proc_desc; | |
2347 | } | |
2348 | ||
6c0d6680 DJ |
2349 | struct mips_objfile_private |
2350 | { | |
2351 | bfd_size_type size; | |
2352 | char *contents; | |
2353 | }; | |
2354 | ||
2355 | /* Global used to communicate between non_heuristic_proc_desc and | |
2356 | compare_pdr_entries within qsort (). */ | |
2357 | static bfd *the_bfd; | |
2358 | ||
2359 | static int | |
2360 | compare_pdr_entries (const void *a, const void *b) | |
2361 | { | |
2362 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2363 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2364 | ||
2365 | if (lhs < rhs) | |
2366 | return -1; | |
2367 | else if (lhs == rhs) | |
2368 | return 0; | |
2369 | else | |
2370 | return 1; | |
2371 | } | |
2372 | ||
c906108c | 2373 | static mips_extra_func_info_t |
acdb74a0 | 2374 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2375 | { |
2376 | CORE_ADDR startaddr; | |
2377 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2378 | struct block *b = block_for_pc (pc); |
c906108c | 2379 | struct symbol *sym; |
6c0d6680 DJ |
2380 | struct obj_section *sec; |
2381 | struct mips_objfile_private *priv; | |
2382 | ||
ae45cd16 | 2383 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2384 | return NULL; |
c906108c SS |
2385 | |
2386 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2387 | if (addrptr) | |
2388 | *addrptr = startaddr; | |
6c0d6680 DJ |
2389 | |
2390 | priv = NULL; | |
2391 | ||
2392 | sec = find_pc_section (pc); | |
2393 | if (sec != NULL) | |
c906108c | 2394 | { |
6c0d6680 DJ |
2395 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2396 | ||
2397 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2398 | the information normally found in ECOFF PDRs. */ | |
2399 | ||
2400 | the_bfd = sec->objfile->obfd; | |
2401 | if (priv == NULL | |
2402 | && (the_bfd->format == bfd_object | |
2403 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2404 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2405 | { | |
2406 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2407 | This means that we should not bother with this method on 64-bit | |
2408 | targets (until that is fixed). */ | |
2409 | ||
2410 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2411 | sizeof (struct mips_objfile_private)); | |
2412 | priv->size = 0; | |
2413 | sec->objfile->obj_private = priv; | |
2414 | } | |
2415 | else if (priv == NULL) | |
2416 | { | |
2417 | asection *bfdsec; | |
2418 | ||
2419 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2420 | sizeof (struct mips_objfile_private)); | |
2421 | ||
2422 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2423 | if (bfdsec != NULL) | |
2424 | { | |
2425 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2426 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2427 | priv->size); | |
2428 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2429 | priv->contents, 0, priv->size); | |
2430 | ||
2431 | /* In general, the .pdr section is sorted. However, in the | |
2432 | presence of multiple code sections (and other corner cases) | |
2433 | it can become unsorted. Sort it so that we can use a faster | |
2434 | binary search. */ | |
2435 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2436 | } | |
2437 | else | |
2438 | priv->size = 0; | |
2439 | ||
2440 | sec->objfile->obj_private = priv; | |
2441 | } | |
2442 | the_bfd = NULL; | |
2443 | ||
2444 | if (priv->size != 0) | |
2445 | { | |
2446 | int low, mid, high; | |
2447 | char *ptr; | |
2448 | ||
2449 | low = 0; | |
2450 | high = priv->size / 32; | |
2451 | ||
2452 | do | |
2453 | { | |
2454 | CORE_ADDR pdr_pc; | |
2455 | ||
2456 | mid = (low + high) / 2; | |
2457 | ||
2458 | ptr = priv->contents + mid * 32; | |
2459 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2460 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2461 | SECT_OFF_TEXT (sec->objfile)); | |
2462 | if (pdr_pc == startaddr) | |
2463 | break; | |
2464 | if (pdr_pc > startaddr) | |
2465 | high = mid; | |
2466 | else | |
2467 | low = mid + 1; | |
2468 | } | |
2469 | while (low != high); | |
2470 | ||
2471 | if (low != high) | |
2472 | { | |
2473 | struct symbol *sym = find_pc_function (pc); | |
2474 | ||
2475 | /* Fill in what we need of the proc_desc. */ | |
2476 | proc_desc = (mips_extra_func_info_t) | |
2477 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2478 | sizeof (struct mips_extra_func_info)); | |
2479 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2480 | ||
2481 | /* Only used for dummy frames. */ | |
2482 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2483 | ||
2484 | PROC_FRAME_OFFSET (proc_desc) | |
2485 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2486 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2487 | ptr + 24); | |
2488 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2489 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2490 | ptr + 4); | |
2491 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2492 | ptr + 12); | |
2493 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2494 | ptr + 8); | |
2495 | PROC_FREG_OFFSET (proc_desc) | |
2496 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2497 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2498 | ptr + 28); | |
2499 | proc_desc->pdr.isym = (long) sym; | |
2500 | ||
2501 | return proc_desc; | |
2502 | } | |
2503 | } | |
c906108c SS |
2504 | } |
2505 | ||
6c0d6680 DJ |
2506 | if (b == NULL) |
2507 | return NULL; | |
2508 | ||
2509 | if (startaddr > BLOCK_START (b)) | |
2510 | { | |
2511 | /* This is the "pathological" case referred to in a comment in | |
2512 | print_frame_info. It might be better to move this check into | |
2513 | symbol reading. */ | |
2514 | return NULL; | |
2515 | } | |
2516 | ||
176620f1 | 2517 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2518 | |
c906108c SS |
2519 | /* If we never found a PDR for this function in symbol reading, then |
2520 | examine prologues to find the information. */ | |
2521 | if (sym) | |
2522 | { | |
2523 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2524 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2525 | return NULL; | |
2526 | else | |
2527 | return proc_desc; | |
2528 | } | |
2529 | else | |
2530 | return NULL; | |
2531 | } | |
2532 | ||
2533 | ||
2534 | static mips_extra_func_info_t | |
479412cd | 2535 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2536 | { |
2537 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2538 | CORE_ADDR startaddr = 0; |
c906108c SS |
2539 | |
2540 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2541 | ||
2542 | if (proc_desc) | |
2543 | { | |
2544 | /* IF this is the topmost frame AND | |
2545 | * (this proc does not have debugging information OR | |
2546 | * the PC is in the procedure prologue) | |
2547 | * THEN create a "heuristic" proc_desc (by analyzing | |
2548 | * the actual code) to replace the "official" proc_desc. | |
2549 | */ | |
2550 | if (next_frame == NULL) | |
2551 | { | |
2552 | struct symtab_and_line val; | |
2553 | struct symbol *proc_symbol = | |
c86b5b38 | 2554 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2555 | |
2556 | if (proc_symbol) | |
2557 | { | |
2558 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2559 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2560 | 0); |
2561 | val.pc = val.end ? val.end : pc; | |
2562 | } | |
2563 | if (!proc_symbol || pc < val.pc) | |
2564 | { | |
2565 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2566 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2567 | pc, next_frame, cur_frame); | |
c906108c SS |
2568 | if (found_heuristic) |
2569 | proc_desc = found_heuristic; | |
2570 | } | |
2571 | } | |
2572 | } | |
2573 | else | |
2574 | { | |
2575 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2576 | by procedure call dummys. However, the procedures being called ought |
2577 | to have their own proc_descs, and even if they don't, | |
2578 | heuristic_proc_desc knows how to create them! */ | |
c906108c | 2579 | |
aa1ee363 | 2580 | struct linked_proc_info *link; |
c906108c SS |
2581 | |
2582 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2583 | if (PROC_LOW_ADDR (&link->info) <= pc |
2584 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2585 | return &link->info; |
2586 | ||
2587 | if (startaddr == 0) | |
2588 | startaddr = heuristic_proc_start (pc); | |
2589 | ||
2590 | proc_desc = | |
479412cd | 2591 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2592 | } |
2593 | return proc_desc; | |
2594 | } | |
2595 | ||
2596 | static CORE_ADDR | |
acdb74a0 AC |
2597 | get_frame_pointer (struct frame_info *frame, |
2598 | mips_extra_func_info_t proc_desc) | |
c906108c | 2599 | { |
a4b8ebc8 | 2600 | return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) |
e227b13c AC |
2601 | + PROC_FRAME_OFFSET (proc_desc) |
2602 | - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2603 | } |
2604 | ||
5a89d8aa | 2605 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2606 | |
f7ab6ec6 | 2607 | static CORE_ADDR |
acdb74a0 | 2608 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2609 | { |
2610 | mips_extra_func_info_t proc_desc; | |
2611 | CORE_ADDR tmp; | |
8bedc050 | 2612 | CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); |
c906108c | 2613 | |
627b3ba2 | 2614 | if (saved_pc == 0 || deprecated_inside_entry_file (saved_pc)) |
c906108c SS |
2615 | return 0; |
2616 | ||
2617 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2618 | PC of the caller of that stub. */ | |
5a89d8aa | 2619 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2620 | saved_pc = tmp; |
2621 | ||
ae45cd16 | 2622 | if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0)) |
cedea778 AC |
2623 | { |
2624 | /* A dummy frame, uses SP not FP. Get the old SP value. If all | |
2625 | is well, frame->frame the bottom of the current frame will | |
2626 | contain that value. */ | |
1e2330ba | 2627 | return get_frame_base (frame); |
cedea778 AC |
2628 | } |
2629 | ||
c906108c | 2630 | /* Look up the procedure descriptor for this PC. */ |
479412cd | 2631 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2632 | if (!proc_desc) |
2633 | return 0; | |
2634 | ||
2635 | cached_proc_desc = proc_desc; | |
2636 | ||
2637 | /* If no frame pointer and frame size is zero, we must be at end | |
2638 | of stack (or otherwise hosed). If we don't check frame size, | |
2639 | we loop forever if we see a zero size frame. */ | |
2640 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2641 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2642 | /* The previous frame from a sigtramp frame might be frameless |
2643 | and have frame size zero. */ | |
5a203e44 | 2644 | && !(get_frame_type (frame) == SIGTRAMP_FRAME) |
cedea778 AC |
2645 | /* For a generic dummy frame, let get_frame_pointer() unwind a |
2646 | register value saved as part of the dummy frame call. */ | |
50abf9e5 | 2647 | && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))) |
c906108c SS |
2648 | return 0; |
2649 | else | |
2650 | return get_frame_pointer (frame, proc_desc); | |
2651 | } | |
2652 | ||
f7ab6ec6 | 2653 | static void |
acdb74a0 | 2654 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2655 | { |
2656 | int regnum; | |
f2c16bd6 KB |
2657 | mips_extra_func_info_t proc_desc; |
2658 | ||
2659 | if (get_frame_type (fci) == DUMMY_FRAME) | |
2660 | return; | |
c906108c | 2661 | |
f796e4be KB |
2662 | /* Use proc_desc calculated in frame_chain. When there is no |
2663 | next frame, i.e, get_next_frame (fci) == NULL, we call | |
2664 | find_proc_desc () to calculate it, passing an explicit | |
2665 | NULL as the frame parameter. */ | |
f2c16bd6 | 2666 | proc_desc = |
11c02a10 AC |
2667 | get_next_frame (fci) |
2668 | ? cached_proc_desc | |
f796e4be KB |
2669 | : find_proc_desc (get_frame_pc (fci), |
2670 | NULL /* i.e, get_next_frame (fci) */, | |
2671 | 1); | |
c906108c | 2672 | |
a00a19e9 | 2673 | frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); |
cce74817 | 2674 | |
7b5849cc | 2675 | deprecated_set_frame_saved_regs_hack (fci, NULL); |
da50a4b7 | 2676 | get_frame_extra_info (fci)->proc_desc = |
c906108c SS |
2677 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2678 | if (proc_desc) | |
2679 | { | |
2680 | /* Fixup frame-pointer - only needed for top frame */ | |
2681 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2682 | Get the value of the frame relative sp, procedure might have been |
2683 | interrupted by a signal at it's very start. */ | |
50abf9e5 | 2684 | if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) |
c906108c | 2685 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
a4b8ebc8 | 2686 | deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), NUM_REGS + SP_REGNUM)); |
50abf9e5 | 2687 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) |
cedea778 AC |
2688 | /* Do not ``fix'' fci->frame. It will have the value of the |
2689 | generic dummy frame's top-of-stack (since the draft | |
2690 | fci->frame is obtained by returning the unwound stack | |
2691 | pointer) and that is what we want. That way the fci->frame | |
2692 | value will match the top-of-stack value that was saved as | |
2693 | part of the dummy frames data. */ | |
2694 | /* Do nothing. */; | |
c906108c | 2695 | else |
11c02a10 | 2696 | deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc)); |
c906108c SS |
2697 | |
2698 | if (proc_desc == &temp_proc_desc) | |
2699 | { | |
2700 | char *name; | |
2701 | ||
2702 | /* Do not set the saved registers for a sigtramp frame, | |
5a203e44 AC |
2703 | mips_find_saved_registers will do that for us. We can't |
2704 | use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not | |
2705 | yet set. */ | |
2706 | /* FIXME: cagney/2002-11-18: This problem will go away once | |
2707 | frame.c:get_prev_frame() is modified to set the frame's | |
2708 | type before calling functions like this. */ | |
50abf9e5 | 2709 | find_pc_partial_function (get_frame_pc (fci), &name, |
c5aa993b | 2710 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
50abf9e5 | 2711 | if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name)) |
c906108c | 2712 | { |
c5aa993b | 2713 | frame_saved_regs_zalloc (fci); |
e0f7ec59 AC |
2714 | /* Set value of previous frame's stack pointer. |
2715 | Remember that saved_regs[SP_REGNUM] is special in | |
2716 | that it contains the value of the stack pointer | |
2717 | register. The other saved_regs values are addresses | |
2718 | (in the inferior) at which a given register's value | |
2719 | may be found. */ | |
2720 | set_reg_offset (temp_saved_regs, SP_REGNUM, | |
2721 | get_frame_base (fci)); | |
2722 | set_reg_offset (temp_saved_regs, PC_REGNUM, | |
2723 | temp_saved_regs[RA_REGNUM]); | |
1b1d3794 | 2724 | memcpy (deprecated_get_frame_saved_regs (fci), temp_saved_regs, |
e0f7ec59 | 2725 | SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2726 | } |
2727 | } | |
2728 | ||
2729 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 | 2730 | /* assume we can't tell how many args for now */ |
da50a4b7 | 2731 | get_frame_extra_info (fci)->num_args = -1; |
c906108c SS |
2732 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2733 | { | |
c5aa993b | 2734 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2735 | { |
da50a4b7 | 2736 | get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2737 | break; |
2738 | } | |
c5aa993b | 2739 | } |
c906108c SS |
2740 | } |
2741 | } | |
2742 | ||
2743 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2744 | we basically have to look at symbol information for the function | |
2745 | that we stopped in, which tells us *which* register (if any) is | |
2746 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2747 | the frame itself is at. |
c906108c SS |
2748 | |
2749 | This presents a problem when trying to examine a stack in memory | |
2750 | (that isn't executing at the moment), using the "frame" command. We | |
2751 | don't have a PC, nor do we have any registers except SP. | |
2752 | ||
2753 | This routine takes two arguments, SP and PC, and tries to make the | |
2754 | cached frames look as if these two arguments defined a frame on the | |
2755 | cache. This allows the rest of info frame to extract the important | |
2756 | arguments without difficulty. */ | |
2757 | ||
2758 | struct frame_info * | |
acdb74a0 | 2759 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2760 | { |
2761 | if (argc != 2) | |
2762 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2763 | ||
2764 | return create_new_frame (argv[0], argv[1]); | |
2765 | } | |
2766 | ||
f09ded24 AC |
2767 | /* According to the current ABI, should the type be passed in a |
2768 | floating-point register (assuming that there is space)? When there | |
2769 | is no FPU, FP are not even considered as possibile candidates for | |
2770 | FP registers and, consequently this returns false - forces FP | |
2771 | arguments into integer registers. */ | |
2772 | ||
2773 | static int | |
2774 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2775 | { | |
2776 | return ((typecode == TYPE_CODE_FLT | |
2777 | || (MIPS_EABI | |
2778 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2779 | && TYPE_NFIELDS (arg_type) == 1 | |
2780 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2781 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2782 | } |
2783 | ||
49e790b0 DJ |
2784 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2785 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2786 | ||
2787 | static int | |
2788 | mips_type_needs_double_align (struct type *type) | |
2789 | { | |
2790 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2791 | |
49e790b0 DJ |
2792 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2793 | return 1; | |
2794 | else if (typecode == TYPE_CODE_STRUCT) | |
2795 | { | |
2796 | if (TYPE_NFIELDS (type) < 1) | |
2797 | return 0; | |
2798 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2799 | } | |
2800 | else if (typecode == TYPE_CODE_UNION) | |
2801 | { | |
361d1df0 | 2802 | int i, n; |
49e790b0 DJ |
2803 | |
2804 | n = TYPE_NFIELDS (type); | |
2805 | for (i = 0; i < n; i++) | |
2806 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2807 | return 1; | |
2808 | return 0; | |
2809 | } | |
2810 | return 0; | |
2811 | } | |
2812 | ||
dc604539 AC |
2813 | /* Adjust the address downward (direction of stack growth) so that it |
2814 | is correctly aligned for a new stack frame. */ | |
2815 | static CORE_ADDR | |
2816 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2817 | { | |
5b03f266 | 2818 | return align_down (addr, 16); |
dc604539 AC |
2819 | } |
2820 | ||
f7ab6ec6 | 2821 | static CORE_ADDR |
25ab4790 AC |
2822 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2823 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2824 | struct value **args, CORE_ADDR sp, int struct_return, | |
2825 | CORE_ADDR struct_addr) | |
c906108c SS |
2826 | { |
2827 | int argreg; | |
2828 | int float_argreg; | |
2829 | int argnum; | |
2830 | int len = 0; | |
2831 | int stack_offset = 0; | |
2832 | ||
25ab4790 AC |
2833 | /* For shared libraries, "t9" needs to point at the function |
2834 | address. */ | |
2835 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2836 | ||
2837 | /* Set the return address register to point to the entry point of | |
2838 | the program, where a breakpoint lies in wait. */ | |
2839 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2840 | ||
c906108c | 2841 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2842 | are properly aligned. The stack has to be at least 64-bit |
2843 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2844 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2845 | aligned, so we round to this widest known alignment. */ | |
2846 | ||
5b03f266 AC |
2847 | sp = align_down (sp, 16); |
2848 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2849 | |
46e0f506 | 2850 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2851 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2852 | passed in registers, but that's OK. */ |
c906108c | 2853 | for (argnum = 0; argnum < nargs; argnum++) |
5b03f266 | 2854 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46e0f506 | 2855 | MIPS_STACK_ARGSIZE); |
5b03f266 | 2856 | sp -= align_up (len, 16); |
c906108c | 2857 | |
9ace0497 | 2858 | if (mips_debug) |
46e0f506 | 2859 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2860 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2861 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2862 | |
c906108c SS |
2863 | /* Initialize the integer and float register pointers. */ |
2864 | argreg = A0_REGNUM; | |
2865 | float_argreg = FPA0_REGNUM; | |
2866 | ||
46e0f506 | 2867 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2868 | if (struct_return) |
9ace0497 AC |
2869 | { |
2870 | if (mips_debug) | |
2871 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2872 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2873 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2874 | write_register (argreg++, struct_addr); |
2875 | } | |
c906108c SS |
2876 | |
2877 | /* Now load as many as possible of the first arguments into | |
2878 | registers, and push the rest onto the stack. Loop thru args | |
2879 | from first to last. */ | |
2880 | for (argnum = 0; argnum < nargs; argnum++) | |
2881 | { | |
2882 | char *val; | |
d9d9c31f | 2883 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2884 | struct value *arg = args[argnum]; |
c906108c SS |
2885 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2886 | int len = TYPE_LENGTH (arg_type); | |
2887 | enum type_code typecode = TYPE_CODE (arg_type); | |
2888 | ||
9ace0497 AC |
2889 | if (mips_debug) |
2890 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2891 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2892 | argnum + 1, len, (int) typecode); |
9ace0497 | 2893 | |
c906108c | 2894 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2895 | reference. */ |
2896 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2897 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2898 | { |
fbd9dcd3 | 2899 | store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2900 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2901 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2902 | val = valbuf; |
9ace0497 AC |
2903 | if (mips_debug) |
2904 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2905 | } |
2906 | else | |
c5aa993b | 2907 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2908 | |
2909 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2910 | even-numbered floating point register. Round the FP register |
2911 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2912 | left. Non MIPS_EABI targets also pass the FP in the integer |
2913 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2914 | if (!FP_REGISTER_DOUBLE |
2915 | && fp_register_arg_p (typecode, arg_type)) | |
2916 | { | |
2917 | if ((float_argreg & 1)) | |
2918 | float_argreg++; | |
2919 | } | |
c906108c SS |
2920 | |
2921 | /* Floating point arguments passed in registers have to be | |
2922 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2923 | are passed in register pairs; the even register gets |
2924 | the low word, and the odd register gets the high word. | |
2925 | On non-EABI processors, the first two floating point arguments are | |
2926 | also copied to general registers, because MIPS16 functions | |
2927 | don't use float registers for arguments. This duplication of | |
2928 | arguments in general registers can't hurt non-MIPS16 functions | |
2929 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2930 | /* MIPS_EABI squeezes a struct that contains a single floating |
2931 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2932 | stack. */ |
f09ded24 AC |
2933 | if (fp_register_arg_p (typecode, arg_type) |
2934 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2935 | { |
2936 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2937 | { | |
d7449b42 | 2938 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2939 | unsigned long regval; |
2940 | ||
2941 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2942 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2943 | if (mips_debug) |
acdb74a0 | 2944 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2945 | float_argreg, phex (regval, 4)); |
c906108c | 2946 | write_register (float_argreg++, regval); |
c906108c SS |
2947 | |
2948 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2949 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2950 | if (mips_debug) |
acdb74a0 | 2951 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2952 | float_argreg, phex (regval, 4)); |
c906108c | 2953 | write_register (float_argreg++, regval); |
c906108c SS |
2954 | } |
2955 | else | |
2956 | { | |
2957 | /* This is a floating point value that fits entirely | |
2958 | in a single register. */ | |
53a5351d | 2959 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2960 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2961 | LONGEST regval = extract_unsigned_integer (val, len); |
2962 | if (mips_debug) | |
acdb74a0 | 2963 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2964 | float_argreg, phex (regval, len)); |
c906108c | 2965 | write_register (float_argreg++, regval); |
c906108c SS |
2966 | } |
2967 | } | |
2968 | else | |
2969 | { | |
2970 | /* Copy the argument to general registers or the stack in | |
2971 | register-sized pieces. Large arguments are split between | |
2972 | registers and stack. */ | |
2973 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2974 | are treated specially: Irix cc passes them in registers | |
2975 | where gcc sometimes puts them on the stack. For maximum | |
2976 | compatibility, we will put them in both places. */ | |
c5aa993b | 2977 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2978 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2979 | |
f09ded24 | 2980 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2981 | register are only written to memory. */ |
c906108c SS |
2982 | while (len > 0) |
2983 | { | |
ebafbe83 | 2984 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2985 | int stack_used_p = 0; |
46e0f506 MS |
2986 | int partial_len = |
2987 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2988 | |
acdb74a0 AC |
2989 | if (mips_debug) |
2990 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2991 | partial_len); | |
2992 | ||
566f0f7a | 2993 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2994 | if (argreg > MIPS_LAST_ARG_REGNUM |
2995 | || odd_sized_struct | |
2996 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2997 | { |
c906108c SS |
2998 | /* Should shorter than int integer values be |
2999 | promoted to int before being stored? */ | |
c906108c | 3000 | int longword_offset = 0; |
9ace0497 | 3001 | CORE_ADDR addr; |
566f0f7a | 3002 | stack_used_p = 1; |
d7449b42 | 3003 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 3004 | { |
d929b26f | 3005 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
3006 | (typecode == TYPE_CODE_INT || |
3007 | typecode == TYPE_CODE_PTR || | |
3008 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 3009 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
3010 | else if ((typecode == TYPE_CODE_STRUCT || |
3011 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
3012 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
3013 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 3014 | } |
c5aa993b | 3015 | |
9ace0497 AC |
3016 | if (mips_debug) |
3017 | { | |
cb3d25d1 MS |
3018 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
3019 | paddr_nz (stack_offset)); | |
3020 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3021 | paddr_nz (longword_offset)); | |
9ace0497 | 3022 | } |
361d1df0 | 3023 | |
9ace0497 AC |
3024 | addr = sp + stack_offset + longword_offset; |
3025 | ||
3026 | if (mips_debug) | |
3027 | { | |
3028 | int i; | |
cb3d25d1 MS |
3029 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
3030 | paddr_nz (addr)); | |
9ace0497 AC |
3031 | for (i = 0; i < partial_len; i++) |
3032 | { | |
cb3d25d1 MS |
3033 | fprintf_unfiltered (gdb_stdlog, "%02x", |
3034 | val[i] & 0xff); | |
9ace0497 AC |
3035 | } |
3036 | } | |
3037 | write_memory (addr, val, partial_len); | |
c906108c SS |
3038 | } |
3039 | ||
f09ded24 AC |
3040 | /* Note!!! This is NOT an else clause. Odd sized |
3041 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3042 | arguments will not. */ |
566f0f7a | 3043 | /* Write this portion of the argument to a general |
46e0f506 | 3044 | purpose register. */ |
f09ded24 AC |
3045 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3046 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3047 | { |
9ace0497 | 3048 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 3049 | |
9ace0497 | 3050 | if (mips_debug) |
acdb74a0 | 3051 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
3052 | argreg, |
3053 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
3054 | write_register (argreg, regval); |
3055 | argreg++; | |
c906108c | 3056 | } |
c5aa993b | 3057 | |
c906108c SS |
3058 | len -= partial_len; |
3059 | val += partial_len; | |
3060 | ||
566f0f7a AC |
3061 | /* Compute the the offset into the stack at which we |
3062 | will copy the next parameter. | |
3063 | ||
566f0f7a | 3064 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3065 | only needs to be adjusted when it has been used. */ |
c906108c | 3066 | |
46e0f506 | 3067 | if (stack_used_p) |
5b03f266 | 3068 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
3069 | } |
3070 | } | |
9ace0497 AC |
3071 | if (mips_debug) |
3072 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3073 | } |
3074 | ||
310e9b6a AC |
3075 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3076 | ||
0f71a2f6 JM |
3077 | /* Return adjusted stack pointer. */ |
3078 | return sp; | |
3079 | } | |
3080 | ||
25ab4790 | 3081 | /* N32/N64 version of push_dummy_call. */ |
ebafbe83 | 3082 | |
f7ab6ec6 | 3083 | static CORE_ADDR |
25ab4790 AC |
3084 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3085 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3086 | struct value **args, CORE_ADDR sp, int struct_return, | |
3087 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3088 | { |
3089 | int argreg; | |
3090 | int float_argreg; | |
3091 | int argnum; | |
3092 | int len = 0; | |
3093 | int stack_offset = 0; | |
3094 | ||
25ab4790 AC |
3095 | /* For shared libraries, "t9" needs to point at the function |
3096 | address. */ | |
3097 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3098 | ||
3099 | /* Set the return address register to point to the entry point of | |
3100 | the program, where a breakpoint lies in wait. */ | |
3101 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3102 | ||
cb3d25d1 MS |
3103 | /* First ensure that the stack and structure return address (if any) |
3104 | are properly aligned. The stack has to be at least 64-bit | |
3105 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3106 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3107 | aligned, so we round to this widest known alignment. */ | |
3108 | ||
5b03f266 AC |
3109 | sp = align_down (sp, 16); |
3110 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3111 | |
3112 | /* Now make space on the stack for the args. */ | |
3113 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3114 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
cb3d25d1 | 3115 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3116 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3117 | |
3118 | if (mips_debug) | |
3119 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3120 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3121 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3122 | |
3123 | /* Initialize the integer and float register pointers. */ | |
3124 | argreg = A0_REGNUM; | |
3125 | float_argreg = FPA0_REGNUM; | |
3126 | ||
46e0f506 | 3127 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3128 | if (struct_return) |
3129 | { | |
3130 | if (mips_debug) | |
3131 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3132 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3133 | argreg, paddr_nz (struct_addr)); |
3134 | write_register (argreg++, struct_addr); | |
3135 | } | |
3136 | ||
3137 | /* Now load as many as possible of the first arguments into | |
3138 | registers, and push the rest onto the stack. Loop thru args | |
3139 | from first to last. */ | |
3140 | for (argnum = 0; argnum < nargs; argnum++) | |
3141 | { | |
3142 | char *val; | |
d9d9c31f | 3143 | char valbuf[MAX_REGISTER_SIZE]; |
cb3d25d1 MS |
3144 | struct value *arg = args[argnum]; |
3145 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3146 | int len = TYPE_LENGTH (arg_type); | |
3147 | enum type_code typecode = TYPE_CODE (arg_type); | |
3148 | ||
3149 | if (mips_debug) | |
3150 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3151 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3152 | argnum + 1, len, (int) typecode); |
3153 | ||
3154 | val = (char *) VALUE_CONTENTS (arg); | |
3155 | ||
3156 | if (fp_register_arg_p (typecode, arg_type) | |
3157 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3158 | { | |
3159 | /* This is a floating point value that fits entirely | |
3160 | in a single register. */ | |
3161 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3162 | above to ensure that it is even register aligned. */ | |
3163 | LONGEST regval = extract_unsigned_integer (val, len); | |
3164 | if (mips_debug) | |
3165 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3166 | float_argreg, phex (regval, len)); | |
3167 | write_register (float_argreg++, regval); | |
3168 | ||
3169 | if (mips_debug) | |
3170 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3171 | argreg, phex (regval, len)); | |
3172 | write_register (argreg, regval); | |
3173 | argreg += 1; | |
3174 | } | |
3175 | else | |
3176 | { | |
3177 | /* Copy the argument to general registers or the stack in | |
3178 | register-sized pieces. Large arguments are split between | |
3179 | registers and stack. */ | |
3180 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3181 | are treated specially: Irix cc passes them in registers | |
3182 | where gcc sometimes puts them on the stack. For maximum | |
3183 | compatibility, we will put them in both places. */ | |
3184 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3185 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3186 | /* Note: Floating-point values that didn't fit into an FP | |
3187 | register are only written to memory. */ | |
3188 | while (len > 0) | |
3189 | { | |
3190 | /* Rememer if the argument was written to the stack. */ | |
3191 | int stack_used_p = 0; | |
3192 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
3193 | len : MIPS_SAVED_REGSIZE; | |
3194 | ||
3195 | if (mips_debug) | |
3196 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3197 | partial_len); | |
3198 | ||
3199 | /* Write this portion of the argument to the stack. */ | |
3200 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3201 | || odd_sized_struct | |
3202 | || fp_register_arg_p (typecode, arg_type)) | |
3203 | { | |
3204 | /* Should shorter than int integer values be | |
3205 | promoted to int before being stored? */ | |
3206 | int longword_offset = 0; | |
3207 | CORE_ADDR addr; | |
3208 | stack_used_p = 1; | |
3209 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3210 | { | |
3211 | if (MIPS_STACK_ARGSIZE == 8 && | |
3212 | (typecode == TYPE_CODE_INT || | |
3213 | typecode == TYPE_CODE_PTR || | |
3214 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3215 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
cb3d25d1 MS |
3216 | } |
3217 | ||
3218 | if (mips_debug) | |
3219 | { | |
3220 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3221 | paddr_nz (stack_offset)); | |
3222 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3223 | paddr_nz (longword_offset)); | |
3224 | } | |
3225 | ||
3226 | addr = sp + stack_offset + longword_offset; | |
3227 | ||
3228 | if (mips_debug) | |
3229 | { | |
3230 | int i; | |
3231 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3232 | paddr_nz (addr)); | |
3233 | for (i = 0; i < partial_len; i++) | |
3234 | { | |
3235 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3236 | val[i] & 0xff); | |
3237 | } | |
3238 | } | |
3239 | write_memory (addr, val, partial_len); | |
3240 | } | |
3241 | ||
3242 | /* Note!!! This is NOT an else clause. Odd sized | |
3243 | structs may go thru BOTH paths. Floating point | |
3244 | arguments will not. */ | |
3245 | /* Write this portion of the argument to a general | |
3246 | purpose register. */ | |
3247 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3248 | && !fp_register_arg_p (typecode, arg_type)) | |
3249 | { | |
3250 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
3251 | ||
3252 | /* A non-floating-point argument being passed in a | |
3253 | general register. If a struct or union, and if | |
3254 | the remaining length is smaller than the register | |
3255 | size, we have to adjust the register value on | |
3256 | big endian targets. | |
3257 | ||
3258 | It does not seem to be necessary to do the | |
3259 | same for integral types. | |
3260 | ||
3261 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3262 | outputting LE O32 with sizeof (struct) < | |
3263 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3264 | part of storing the argument in a register a | |
3265 | register (the left shift isn't generated when | |
3266 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3267 | is quite possible that this is GCC contradicting | |
3268 | the LE/O32 ABI, GDB has not been adjusted to | |
3269 | accommodate this. Either someone needs to | |
3270 | demonstrate that the LE/O32 ABI specifies such a | |
3271 | left shift OR this new ABI gets identified as | |
3272 | such and GDB gets tweaked accordingly. */ | |
3273 | ||
3274 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3275 | && partial_len < MIPS_SAVED_REGSIZE | |
3276 | && (typecode == TYPE_CODE_STRUCT || | |
3277 | typecode == TYPE_CODE_UNION)) | |
3278 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3279 | TARGET_CHAR_BIT); | |
3280 | ||
3281 | if (mips_debug) | |
3282 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3283 | argreg, | |
3284 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3285 | write_register (argreg, regval); | |
3286 | argreg++; | |
3287 | } | |
3288 | ||
3289 | len -= partial_len; | |
3290 | val += partial_len; | |
3291 | ||
3292 | /* Compute the the offset into the stack at which we | |
3293 | will copy the next parameter. | |
3294 | ||
3295 | In N32 (N64?), the stack_offset only needs to be | |
3296 | adjusted when it has been used. */ | |
3297 | ||
3298 | if (stack_used_p) | |
5b03f266 | 3299 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
cb3d25d1 MS |
3300 | } |
3301 | } | |
3302 | if (mips_debug) | |
3303 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3304 | } | |
3305 | ||
310e9b6a AC |
3306 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3307 | ||
cb3d25d1 MS |
3308 | /* Return adjusted stack pointer. */ |
3309 | return sp; | |
3310 | } | |
3311 | ||
25ab4790 | 3312 | /* O32 version of push_dummy_call. */ |
ebafbe83 | 3313 | |
46cac009 | 3314 | static CORE_ADDR |
25ab4790 AC |
3315 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3316 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3317 | struct value **args, CORE_ADDR sp, int struct_return, | |
3318 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3319 | { |
3320 | int argreg; | |
3321 | int float_argreg; | |
3322 | int argnum; | |
3323 | int len = 0; | |
3324 | int stack_offset = 0; | |
ebafbe83 | 3325 | |
25ab4790 AC |
3326 | /* For shared libraries, "t9" needs to point at the function |
3327 | address. */ | |
3328 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3329 | ||
3330 | /* Set the return address register to point to the entry point of | |
3331 | the program, where a breakpoint lies in wait. */ | |
3332 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3333 | ||
ebafbe83 MS |
3334 | /* First ensure that the stack and structure return address (if any) |
3335 | are properly aligned. The stack has to be at least 64-bit | |
3336 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3337 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3338 | aligned, so we round to this widest known alignment. */ | |
3339 | ||
5b03f266 AC |
3340 | sp = align_down (sp, 16); |
3341 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3342 | |
3343 | /* Now make space on the stack for the args. */ | |
3344 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3345 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
ebafbe83 | 3346 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3347 | sp -= align_up (len, 16); |
ebafbe83 MS |
3348 | |
3349 | if (mips_debug) | |
3350 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3351 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3352 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3353 | |
3354 | /* Initialize the integer and float register pointers. */ | |
3355 | argreg = A0_REGNUM; | |
3356 | float_argreg = FPA0_REGNUM; | |
3357 | ||
bcb0cc15 | 3358 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3359 | if (struct_return) |
3360 | { | |
3361 | if (mips_debug) | |
3362 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3363 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3364 | argreg, paddr_nz (struct_addr)); |
3365 | write_register (argreg++, struct_addr); | |
3366 | stack_offset += MIPS_STACK_ARGSIZE; | |
3367 | } | |
3368 | ||
3369 | /* Now load as many as possible of the first arguments into | |
3370 | registers, and push the rest onto the stack. Loop thru args | |
3371 | from first to last. */ | |
3372 | for (argnum = 0; argnum < nargs; argnum++) | |
3373 | { | |
3374 | char *val; | |
d9d9c31f | 3375 | char valbuf[MAX_REGISTER_SIZE]; |
ebafbe83 MS |
3376 | struct value *arg = args[argnum]; |
3377 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3378 | int len = TYPE_LENGTH (arg_type); | |
3379 | enum type_code typecode = TYPE_CODE (arg_type); | |
3380 | ||
3381 | if (mips_debug) | |
3382 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3383 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3384 | argnum + 1, len, (int) typecode); |
3385 | ||
3386 | val = (char *) VALUE_CONTENTS (arg); | |
3387 | ||
3388 | /* 32-bit ABIs always start floating point arguments in an | |
3389 | even-numbered floating point register. Round the FP register | |
3390 | up before the check to see if there are any FP registers | |
3391 | left. O32/O64 targets also pass the FP in the integer | |
3392 | registers so also round up normal registers. */ | |
3393 | if (!FP_REGISTER_DOUBLE | |
3394 | && fp_register_arg_p (typecode, arg_type)) | |
3395 | { | |
3396 | if ((float_argreg & 1)) | |
3397 | float_argreg++; | |
3398 | } | |
3399 | ||
3400 | /* Floating point arguments passed in registers have to be | |
3401 | treated specially. On 32-bit architectures, doubles | |
3402 | are passed in register pairs; the even register gets | |
3403 | the low word, and the odd register gets the high word. | |
3404 | On O32/O64, the first two floating point arguments are | |
3405 | also copied to general registers, because MIPS16 functions | |
3406 | don't use float registers for arguments. This duplication of | |
3407 | arguments in general registers can't hurt non-MIPS16 functions | |
3408 | because those registers are normally skipped. */ | |
3409 | ||
3410 | if (fp_register_arg_p (typecode, arg_type) | |
3411 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3412 | { | |
3413 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3414 | { | |
3415 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3416 | unsigned long regval; | |
3417 | ||
3418 | /* Write the low word of the double to the even register(s). */ | |
3419 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3420 | if (mips_debug) | |
3421 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3422 | float_argreg, phex (regval, 4)); | |
3423 | write_register (float_argreg++, regval); | |
3424 | if (mips_debug) | |
3425 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3426 | argreg, phex (regval, 4)); | |
3427 | write_register (argreg++, regval); | |
3428 | ||
3429 | /* Write the high word of the double to the odd register(s). */ | |
3430 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3431 | if (mips_debug) | |
3432 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3433 | float_argreg, phex (regval, 4)); | |
3434 | write_register (float_argreg++, regval); | |
3435 | ||
3436 | if (mips_debug) | |
3437 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3438 | argreg, phex (regval, 4)); | |
3439 | write_register (argreg++, regval); | |
3440 | } | |
3441 | else | |
3442 | { | |
3443 | /* This is a floating point value that fits entirely | |
3444 | in a single register. */ | |
3445 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3446 | above to ensure that it is even register aligned. */ | |
3447 | LONGEST regval = extract_unsigned_integer (val, len); | |
3448 | if (mips_debug) | |
3449 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3450 | float_argreg, phex (regval, len)); | |
3451 | write_register (float_argreg++, regval); | |
3452 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3453 | registers for each argument. The below is (my | |
3454 | guess) to ensure that the corresponding integer | |
3455 | register has reserved the same space. */ | |
3456 | if (mips_debug) | |
3457 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3458 | argreg, phex (regval, len)); | |
3459 | write_register (argreg, regval); | |
3460 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3461 | } | |
3462 | /* Reserve space for the FP register. */ | |
5b03f266 | 3463 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3464 | } |
3465 | else | |
3466 | { | |
3467 | /* Copy the argument to general registers or the stack in | |
3468 | register-sized pieces. Large arguments are split between | |
3469 | registers and stack. */ | |
3470 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3471 | are treated specially: Irix cc passes them in registers | |
3472 | where gcc sometimes puts them on the stack. For maximum | |
3473 | compatibility, we will put them in both places. */ | |
3474 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3475 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3476 | /* Structures should be aligned to eight bytes (even arg registers) | |
3477 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3478 | if (MIPS_SAVED_REGSIZE < 8 | |
3479 | && mips_type_needs_double_align (arg_type)) | |
3480 | { | |
3481 | if ((argreg & 1)) | |
3482 | argreg++; | |
3483 | } | |
3484 | /* Note: Floating-point values that didn't fit into an FP | |
3485 | register are only written to memory. */ | |
3486 | while (len > 0) | |
3487 | { | |
3488 | /* Remember if the argument was written to the stack. */ | |
3489 | int stack_used_p = 0; | |
3490 | int partial_len = | |
3491 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3492 | ||
3493 | if (mips_debug) | |
3494 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3495 | partial_len); | |
3496 | ||
3497 | /* Write this portion of the argument to the stack. */ | |
3498 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3499 | || odd_sized_struct | |
3500 | || fp_register_arg_p (typecode, arg_type)) | |
3501 | { | |
3502 | /* Should shorter than int integer values be | |
3503 | promoted to int before being stored? */ | |
3504 | int longword_offset = 0; | |
3505 | CORE_ADDR addr; | |
3506 | stack_used_p = 1; | |
3507 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3508 | { | |
3509 | if (MIPS_STACK_ARGSIZE == 8 && | |
3510 | (typecode == TYPE_CODE_INT || | |
3511 | typecode == TYPE_CODE_PTR || | |
3512 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3513 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3514 | } | |
3515 | ||
3516 | if (mips_debug) | |
3517 | { | |
3518 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3519 | paddr_nz (stack_offset)); | |
3520 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3521 | paddr_nz (longword_offset)); | |
3522 | } | |
3523 | ||
3524 | addr = sp + stack_offset + longword_offset; | |
3525 | ||
3526 | if (mips_debug) | |
3527 | { | |
3528 | int i; | |
3529 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3530 | paddr_nz (addr)); | |
3531 | for (i = 0; i < partial_len; i++) | |
3532 | { | |
3533 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3534 | val[i] & 0xff); | |
3535 | } | |
3536 | } | |
3537 | write_memory (addr, val, partial_len); | |
3538 | } | |
3539 | ||
3540 | /* Note!!! This is NOT an else clause. Odd sized | |
3541 | structs may go thru BOTH paths. Floating point | |
3542 | arguments will not. */ | |
3543 | /* Write this portion of the argument to a general | |
3544 | purpose register. */ | |
3545 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3546 | && !fp_register_arg_p (typecode, arg_type)) | |
3547 | { | |
3548 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3549 | /* Value may need to be sign extended, because | |
3550 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3551 | ||
3552 | /* A non-floating-point argument being passed in a | |
3553 | general register. If a struct or union, and if | |
3554 | the remaining length is smaller than the register | |
3555 | size, we have to adjust the register value on | |
3556 | big endian targets. | |
3557 | ||
3558 | It does not seem to be necessary to do the | |
3559 | same for integral types. | |
3560 | ||
3561 | Also don't do this adjustment on O64 binaries. | |
3562 | ||
3563 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3564 | outputting LE O32 with sizeof (struct) < | |
3565 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3566 | part of storing the argument in a register a | |
3567 | register (the left shift isn't generated when | |
3568 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3569 | is quite possible that this is GCC contradicting | |
3570 | the LE/O32 ABI, GDB has not been adjusted to | |
3571 | accommodate this. Either someone needs to | |
3572 | demonstrate that the LE/O32 ABI specifies such a | |
3573 | left shift OR this new ABI gets identified as | |
3574 | such and GDB gets tweaked accordingly. */ | |
3575 | ||
3576 | if (MIPS_SAVED_REGSIZE < 8 | |
3577 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3578 | && partial_len < MIPS_SAVED_REGSIZE | |
3579 | && (typecode == TYPE_CODE_STRUCT || | |
3580 | typecode == TYPE_CODE_UNION)) | |
3581 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3582 | TARGET_CHAR_BIT); | |
3583 | ||
3584 | if (mips_debug) | |
3585 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3586 | argreg, | |
3587 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3588 | write_register (argreg, regval); | |
3589 | argreg++; | |
3590 | ||
3591 | /* Prevent subsequent floating point arguments from | |
3592 | being passed in floating point registers. */ | |
3593 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3594 | } | |
3595 | ||
3596 | len -= partial_len; | |
3597 | val += partial_len; | |
3598 | ||
3599 | /* Compute the the offset into the stack at which we | |
3600 | will copy the next parameter. | |
3601 | ||
3602 | In older ABIs, the caller reserved space for | |
3603 | registers that contained arguments. This was loosely | |
3604 | refered to as their "home". Consequently, space is | |
3605 | always allocated. */ | |
3606 | ||
5b03f266 | 3607 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3608 | } |
3609 | } | |
3610 | if (mips_debug) | |
3611 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3612 | } | |
3613 | ||
310e9b6a AC |
3614 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3615 | ||
46cac009 AC |
3616 | /* Return adjusted stack pointer. */ |
3617 | return sp; | |
3618 | } | |
3619 | ||
25ab4790 | 3620 | /* O64 version of push_dummy_call. */ |
46cac009 AC |
3621 | |
3622 | static CORE_ADDR | |
25ab4790 AC |
3623 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3624 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3625 | struct value **args, CORE_ADDR sp, int struct_return, | |
3626 | CORE_ADDR struct_addr) | |
46cac009 AC |
3627 | { |
3628 | int argreg; | |
3629 | int float_argreg; | |
3630 | int argnum; | |
3631 | int len = 0; | |
3632 | int stack_offset = 0; | |
3633 | ||
25ab4790 AC |
3634 | /* For shared libraries, "t9" needs to point at the function |
3635 | address. */ | |
3636 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3637 | ||
3638 | /* Set the return address register to point to the entry point of | |
3639 | the program, where a breakpoint lies in wait. */ | |
3640 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3641 | ||
46cac009 AC |
3642 | /* First ensure that the stack and structure return address (if any) |
3643 | are properly aligned. The stack has to be at least 64-bit | |
3644 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3645 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3646 | aligned, so we round to this widest known alignment. */ | |
3647 | ||
5b03f266 AC |
3648 | sp = align_down (sp, 16); |
3649 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3650 | |
3651 | /* Now make space on the stack for the args. */ | |
3652 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3653 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46cac009 | 3654 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3655 | sp -= align_up (len, 16); |
46cac009 AC |
3656 | |
3657 | if (mips_debug) | |
3658 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3659 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3660 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3661 | |
3662 | /* Initialize the integer and float register pointers. */ | |
3663 | argreg = A0_REGNUM; | |
3664 | float_argreg = FPA0_REGNUM; | |
3665 | ||
3666 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3667 | if (struct_return) | |
3668 | { | |
3669 | if (mips_debug) | |
3670 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3671 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3672 | argreg, paddr_nz (struct_addr)); |
3673 | write_register (argreg++, struct_addr); | |
3674 | stack_offset += MIPS_STACK_ARGSIZE; | |
3675 | } | |
3676 | ||
3677 | /* Now load as many as possible of the first arguments into | |
3678 | registers, and push the rest onto the stack. Loop thru args | |
3679 | from first to last. */ | |
3680 | for (argnum = 0; argnum < nargs; argnum++) | |
3681 | { | |
3682 | char *val; | |
d9d9c31f | 3683 | char valbuf[MAX_REGISTER_SIZE]; |
46cac009 AC |
3684 | struct value *arg = args[argnum]; |
3685 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3686 | int len = TYPE_LENGTH (arg_type); | |
3687 | enum type_code typecode = TYPE_CODE (arg_type); | |
3688 | ||
3689 | if (mips_debug) | |
3690 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3691 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3692 | argnum + 1, len, (int) typecode); |
3693 | ||
3694 | val = (char *) VALUE_CONTENTS (arg); | |
3695 | ||
3696 | /* 32-bit ABIs always start floating point arguments in an | |
3697 | even-numbered floating point register. Round the FP register | |
3698 | up before the check to see if there are any FP registers | |
3699 | left. O32/O64 targets also pass the FP in the integer | |
3700 | registers so also round up normal registers. */ | |
3701 | if (!FP_REGISTER_DOUBLE | |
3702 | && fp_register_arg_p (typecode, arg_type)) | |
3703 | { | |
3704 | if ((float_argreg & 1)) | |
3705 | float_argreg++; | |
3706 | } | |
3707 | ||
3708 | /* Floating point arguments passed in registers have to be | |
3709 | treated specially. On 32-bit architectures, doubles | |
3710 | are passed in register pairs; the even register gets | |
3711 | the low word, and the odd register gets the high word. | |
3712 | On O32/O64, the first two floating point arguments are | |
3713 | also copied to general registers, because MIPS16 functions | |
3714 | don't use float registers for arguments. This duplication of | |
3715 | arguments in general registers can't hurt non-MIPS16 functions | |
3716 | because those registers are normally skipped. */ | |
3717 | ||
3718 | if (fp_register_arg_p (typecode, arg_type) | |
3719 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3720 | { | |
3721 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3722 | { | |
3723 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3724 | unsigned long regval; | |
3725 | ||
3726 | /* Write the low word of the double to the even register(s). */ | |
3727 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3728 | if (mips_debug) | |
3729 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3730 | float_argreg, phex (regval, 4)); | |
3731 | write_register (float_argreg++, regval); | |
3732 | if (mips_debug) | |
3733 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3734 | argreg, phex (regval, 4)); | |
3735 | write_register (argreg++, regval); | |
3736 | ||
3737 | /* Write the high word of the double to the odd register(s). */ | |
3738 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3739 | if (mips_debug) | |
3740 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3741 | float_argreg, phex (regval, 4)); | |
3742 | write_register (float_argreg++, regval); | |
3743 | ||
3744 | if (mips_debug) | |
3745 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3746 | argreg, phex (regval, 4)); | |
3747 | write_register (argreg++, regval); | |
3748 | } | |
3749 | else | |
3750 | { | |
3751 | /* This is a floating point value that fits entirely | |
3752 | in a single register. */ | |
3753 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3754 | above to ensure that it is even register aligned. */ | |
3755 | LONGEST regval = extract_unsigned_integer (val, len); | |
3756 | if (mips_debug) | |
3757 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3758 | float_argreg, phex (regval, len)); | |
3759 | write_register (float_argreg++, regval); | |
3760 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3761 | registers for each argument. The below is (my | |
3762 | guess) to ensure that the corresponding integer | |
3763 | register has reserved the same space. */ | |
3764 | if (mips_debug) | |
3765 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3766 | argreg, phex (regval, len)); | |
3767 | write_register (argreg, regval); | |
3768 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3769 | } | |
3770 | /* Reserve space for the FP register. */ | |
5b03f266 | 3771 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3772 | } |
3773 | else | |
3774 | { | |
3775 | /* Copy the argument to general registers or the stack in | |
3776 | register-sized pieces. Large arguments are split between | |
3777 | registers and stack. */ | |
3778 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3779 | are treated specially: Irix cc passes them in registers | |
3780 | where gcc sometimes puts them on the stack. For maximum | |
3781 | compatibility, we will put them in both places. */ | |
3782 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3783 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3784 | /* Structures should be aligned to eight bytes (even arg registers) | |
3785 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3786 | if (MIPS_SAVED_REGSIZE < 8 | |
3787 | && mips_type_needs_double_align (arg_type)) | |
3788 | { | |
3789 | if ((argreg & 1)) | |
3790 | argreg++; | |
3791 | } | |
3792 | /* Note: Floating-point values that didn't fit into an FP | |
3793 | register are only written to memory. */ | |
3794 | while (len > 0) | |
3795 | { | |
3796 | /* Remember if the argument was written to the stack. */ | |
3797 | int stack_used_p = 0; | |
3798 | int partial_len = | |
3799 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3800 | ||
3801 | if (mips_debug) | |
3802 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3803 | partial_len); | |
3804 | ||
3805 | /* Write this portion of the argument to the stack. */ | |
3806 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3807 | || odd_sized_struct | |
3808 | || fp_register_arg_p (typecode, arg_type)) | |
3809 | { | |
3810 | /* Should shorter than int integer values be | |
3811 | promoted to int before being stored? */ | |
3812 | int longword_offset = 0; | |
3813 | CORE_ADDR addr; | |
3814 | stack_used_p = 1; | |
3815 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3816 | { | |
3817 | if (MIPS_STACK_ARGSIZE == 8 && | |
3818 | (typecode == TYPE_CODE_INT || | |
3819 | typecode == TYPE_CODE_PTR || | |
3820 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3821 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3822 | } | |
3823 | ||
3824 | if (mips_debug) | |
3825 | { | |
3826 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3827 | paddr_nz (stack_offset)); | |
3828 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3829 | paddr_nz (longword_offset)); | |
3830 | } | |
3831 | ||
3832 | addr = sp + stack_offset + longword_offset; | |
3833 | ||
3834 | if (mips_debug) | |
3835 | { | |
3836 | int i; | |
3837 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3838 | paddr_nz (addr)); | |
3839 | for (i = 0; i < partial_len; i++) | |
3840 | { | |
3841 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3842 | val[i] & 0xff); | |
3843 | } | |
3844 | } | |
3845 | write_memory (addr, val, partial_len); | |
3846 | } | |
3847 | ||
3848 | /* Note!!! This is NOT an else clause. Odd sized | |
3849 | structs may go thru BOTH paths. Floating point | |
3850 | arguments will not. */ | |
3851 | /* Write this portion of the argument to a general | |
3852 | purpose register. */ | |
3853 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3854 | && !fp_register_arg_p (typecode, arg_type)) | |
3855 | { | |
3856 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3857 | /* Value may need to be sign extended, because | |
3858 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3859 | ||
3860 | /* A non-floating-point argument being passed in a | |
3861 | general register. If a struct or union, and if | |
3862 | the remaining length is smaller than the register | |
3863 | size, we have to adjust the register value on | |
3864 | big endian targets. | |
3865 | ||
3866 | It does not seem to be necessary to do the | |
3867 | same for integral types. | |
3868 | ||
3869 | Also don't do this adjustment on O64 binaries. | |
3870 | ||
3871 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3872 | outputting LE O32 with sizeof (struct) < | |
3873 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3874 | part of storing the argument in a register a | |
3875 | register (the left shift isn't generated when | |
3876 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3877 | is quite possible that this is GCC contradicting | |
3878 | the LE/O32 ABI, GDB has not been adjusted to | |
3879 | accommodate this. Either someone needs to | |
3880 | demonstrate that the LE/O32 ABI specifies such a | |
3881 | left shift OR this new ABI gets identified as | |
3882 | such and GDB gets tweaked accordingly. */ | |
3883 | ||
3884 | if (MIPS_SAVED_REGSIZE < 8 | |
3885 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3886 | && partial_len < MIPS_SAVED_REGSIZE | |
3887 | && (typecode == TYPE_CODE_STRUCT || | |
3888 | typecode == TYPE_CODE_UNION)) | |
3889 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3890 | TARGET_CHAR_BIT); | |
3891 | ||
3892 | if (mips_debug) | |
3893 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3894 | argreg, | |
3895 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3896 | write_register (argreg, regval); | |
3897 | argreg++; | |
3898 | ||
3899 | /* Prevent subsequent floating point arguments from | |
3900 | being passed in floating point registers. */ | |
3901 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3902 | } | |
3903 | ||
3904 | len -= partial_len; | |
3905 | val += partial_len; | |
3906 | ||
3907 | /* Compute the the offset into the stack at which we | |
3908 | will copy the next parameter. | |
3909 | ||
3910 | In older ABIs, the caller reserved space for | |
3911 | registers that contained arguments. This was loosely | |
3912 | refered to as their "home". Consequently, space is | |
3913 | always allocated. */ | |
3914 | ||
5b03f266 | 3915 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3916 | } |
3917 | } | |
3918 | if (mips_debug) | |
3919 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3920 | } | |
3921 | ||
310e9b6a AC |
3922 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3923 | ||
ebafbe83 MS |
3924 | /* Return adjusted stack pointer. */ |
3925 | return sp; | |
3926 | } | |
3927 | ||
f7ab6ec6 | 3928 | static void |
acdb74a0 | 3929 | mips_pop_frame (void) |
c906108c | 3930 | { |
52f0bd74 | 3931 | int regnum; |
c906108c | 3932 | struct frame_info *frame = get_current_frame (); |
c193f6ac | 3933 | CORE_ADDR new_sp = get_frame_base (frame); |
e227b13c | 3934 | mips_extra_func_info_t proc_desc; |
c906108c | 3935 | |
50abf9e5 | 3936 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
3937 | { |
3938 | generic_pop_dummy_frame (); | |
3939 | flush_cached_frames (); | |
3940 | return; | |
3941 | } | |
3942 | ||
e227b13c | 3943 | proc_desc = get_frame_extra_info (frame)->proc_desc; |
8bedc050 | 3944 | write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
e0f7ec59 | 3945 | mips_find_saved_regs (frame); |
c906108c | 3946 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
21f87145 | 3947 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1b1d3794 | 3948 | && deprecated_get_frame_saved_regs (frame)[regnum]) |
21f87145 MS |
3949 | { |
3950 | /* Floating point registers must not be sign extended, | |
3951 | in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */ | |
3952 | ||
3953 | if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32) | |
3954 | write_register (regnum, | |
1b1d3794 | 3955 | read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3956 | MIPS_SAVED_REGSIZE)); |
3957 | else | |
3958 | write_register (regnum, | |
1b1d3794 | 3959 | read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3960 | MIPS_SAVED_REGSIZE)); |
3961 | } | |
757a7cc6 | 3962 | |
c906108c SS |
3963 | write_register (SP_REGNUM, new_sp); |
3964 | flush_cached_frames (); | |
3965 | ||
c5aa993b | 3966 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3967 | { |
3968 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3969 | ||
3970 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3971 | pi_ptr != NULL; | |
3972 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3973 | { | |
3974 | if (&pi_ptr->info == proc_desc) | |
3975 | break; | |
3976 | } | |
3977 | ||
3978 | if (pi_ptr == NULL) | |
3979 | error ("Can't locate dummy extra frame info\n"); | |
3980 | ||
3981 | if (prev_ptr != NULL) | |
3982 | prev_ptr->next = pi_ptr->next; | |
3983 | else | |
3984 | linked_proc_desc_table = pi_ptr->next; | |
3985 | ||
b8c9b27d | 3986 | xfree (pi_ptr); |
c906108c SS |
3987 | |
3988 | write_register (HI_REGNUM, | |
c5aa993b | 3989 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3990 | MIPS_SAVED_REGSIZE)); |
c906108c | 3991 | write_register (LO_REGNUM, |
c5aa993b | 3992 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3993 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3994 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
3995 | write_register (FCRCS_REGNUM, | |
c5aa993b | 3996 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3997 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3998 | } |
3999 | } | |
4000 | ||
dd824b04 DJ |
4001 | /* Floating point register management. |
4002 | ||
4003 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4004 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4005 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4006 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4007 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4008 | double precision floats into two 32-bit chunks and store them in | |
4009 | consecutive fp regs. To display 64-bit floats stored in this | |
4010 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4011 | Throw in user-configurable endianness and you have a real mess. | |
4012 | ||
4013 | The way this works is: | |
4014 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4015 | double-precision value will be split across two logical registers. | |
4016 | The lower-numbered logical register will hold the low-order bits, | |
4017 | regardless of the processor's endianness. | |
4018 | - If we are on a 64-bit processor, and we are looking for a | |
4019 | single-precision value, it will be in the low ordered bits | |
4020 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4021 | save slot in memory. | |
4022 | - If we are in 64-bit mode, everything is straightforward. | |
4023 | ||
4024 | Note that this code only deals with "live" registers at the top of the | |
4025 | stack. We will attempt to deal with saved registers later, when | |
4026 | the raw/cooked register interface is in place. (We need a general | |
4027 | interface that can deal with dynamic saved register sizes -- fp | |
4028 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4029 | and below). */ | |
4030 | ||
67b2c998 DJ |
4031 | static struct type * |
4032 | mips_float_register_type (void) | |
4033 | { | |
361d1df0 | 4034 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4035 | return builtin_type_ieee_single_big; |
4036 | else | |
4037 | return builtin_type_ieee_single_little; | |
4038 | } | |
4039 | ||
4040 | static struct type * | |
4041 | mips_double_register_type (void) | |
4042 | { | |
361d1df0 | 4043 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4044 | return builtin_type_ieee_double_big; |
4045 | else | |
4046 | return builtin_type_ieee_double_little; | |
4047 | } | |
4048 | ||
dd824b04 DJ |
4049 | /* Copy a 32-bit single-precision value from the current frame |
4050 | into rare_buffer. */ | |
4051 | ||
4052 | static void | |
e11c53d2 AC |
4053 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4054 | char *rare_buffer) | |
dd824b04 | 4055 | { |
12c266ea | 4056 | int raw_size = DEPRECATED_REGISTER_RAW_SIZE (regno); |
dd824b04 DJ |
4057 | char *raw_buffer = alloca (raw_size); |
4058 | ||
e11c53d2 | 4059 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4060 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4061 | if (raw_size == 8) | |
4062 | { | |
4063 | /* We have a 64-bit value for this register. Find the low-order | |
4064 | 32 bits. */ | |
4065 | int offset; | |
4066 | ||
4067 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4068 | offset = 4; | |
4069 | else | |
4070 | offset = 0; | |
4071 | ||
4072 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4073 | } | |
4074 | else | |
4075 | { | |
4076 | memcpy (rare_buffer, raw_buffer, 4); | |
4077 | } | |
4078 | } | |
4079 | ||
4080 | /* Copy a 64-bit double-precision value from the current frame into | |
4081 | rare_buffer. This may include getting half of it from the next | |
4082 | register. */ | |
4083 | ||
4084 | static void | |
e11c53d2 AC |
4085 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4086 | char *rare_buffer) | |
dd824b04 | 4087 | { |
12c266ea | 4088 | int raw_size = DEPRECATED_REGISTER_RAW_SIZE (regno); |
dd824b04 DJ |
4089 | |
4090 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4091 | { | |
4092 | /* We have a 64-bit value for this register, and we should use | |
4093 | all 64 bits. */ | |
e11c53d2 | 4094 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4095 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4096 | } | |
4097 | else | |
4098 | { | |
4099 | if ((regno - FP0_REGNUM) & 1) | |
4100 | internal_error (__FILE__, __LINE__, | |
4101 | "mips_read_fp_register_double: bad access to " | |
4102 | "odd-numbered FP register"); | |
4103 | ||
4104 | /* mips_read_fp_register_single will find the correct 32 bits from | |
4105 | each register. */ | |
4106 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4107 | { | |
e11c53d2 AC |
4108 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4109 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4110 | } |
361d1df0 | 4111 | else |
dd824b04 | 4112 | { |
e11c53d2 AC |
4113 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4114 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4115 | } |
4116 | } | |
4117 | } | |
4118 | ||
c906108c | 4119 | static void |
e11c53d2 AC |
4120 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4121 | int regnum) | |
c5aa993b | 4122 | { /* do values for FP (float) regs */ |
dd824b04 | 4123 | char *raw_buffer; |
c906108c | 4124 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
f0ef6b29 | 4125 | int inv1, inv2, namelen; |
c5aa993b | 4126 | |
12c266ea | 4127 | raw_buffer = (char *) alloca (2 * DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM)); |
c906108c | 4128 | |
e11c53d2 AC |
4129 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4130 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4131 | ""); | |
f0ef6b29 | 4132 | |
12c266ea | 4133 | if (DEPRECATED_REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4134 | { |
f0ef6b29 KB |
4135 | /* 4-byte registers: Print hex and floating. Also print even |
4136 | numbered registers as doubles. */ | |
e11c53d2 | 4137 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4138 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4139 | |
e11c53d2 | 4140 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file); |
dd824b04 | 4141 | |
e11c53d2 | 4142 | fprintf_filtered (file, " flt: "); |
1adad886 | 4143 | if (inv1) |
e11c53d2 | 4144 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4145 | else |
e11c53d2 | 4146 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4147 | |
f0ef6b29 KB |
4148 | if (regnum % 2 == 0) |
4149 | { | |
e11c53d2 | 4150 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4151 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
4152 | &inv2); | |
1adad886 | 4153 | |
e11c53d2 | 4154 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4155 | if (inv2) |
e11c53d2 | 4156 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4157 | else |
e11c53d2 | 4158 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4159 | } |
c906108c SS |
4160 | } |
4161 | else | |
dd824b04 | 4162 | { |
f0ef6b29 | 4163 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4164 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4165 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4166 | |
e11c53d2 | 4167 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4168 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4169 | ||
361d1df0 | 4170 | |
e11c53d2 | 4171 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file); |
f0ef6b29 | 4172 | |
e11c53d2 | 4173 | fprintf_filtered (file, " flt: "); |
1adad886 | 4174 | if (inv1) |
e11c53d2 | 4175 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4176 | else |
e11c53d2 | 4177 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4178 | |
e11c53d2 | 4179 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4180 | if (inv2) |
e11c53d2 | 4181 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4182 | else |
e11c53d2 | 4183 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4184 | } |
4185 | } | |
4186 | ||
4187 | static void | |
e11c53d2 AC |
4188 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4189 | int regnum, int all) | |
f0ef6b29 | 4190 | { |
a4b8ebc8 | 4191 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4192 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4193 | int offset; |
1adad886 | 4194 | |
a4b8ebc8 | 4195 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4196 | { |
e11c53d2 | 4197 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4198 | return; |
4199 | } | |
4200 | ||
4201 | /* Get the data in raw format. */ | |
e11c53d2 | 4202 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4203 | { |
e11c53d2 | 4204 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4205 | return; |
c906108c | 4206 | } |
f0ef6b29 | 4207 | |
e11c53d2 | 4208 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4209 | |
4210 | /* The problem with printing numeric register names (r26, etc.) is that | |
4211 | the user can't use them on input. Probably the best solution is to | |
4212 | fix it so that either the numeric or the funky (a2, etc.) names | |
4213 | are accepted on input. */ | |
4214 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4215 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4216 | else |
e11c53d2 | 4217 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4218 | |
4219 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
12c266ea | 4220 | offset = DEPRECATED_REGISTER_RAW_SIZE (regnum) - DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum); |
f0ef6b29 KB |
4221 | else |
4222 | offset = 0; | |
4223 | ||
a4b8ebc8 | 4224 | print_scalar_formatted (raw_buffer + offset, gdbarch_register_type (gdbarch, regnum), |
e11c53d2 | 4225 | 'x', 0, file); |
c906108c SS |
4226 | } |
4227 | ||
f0ef6b29 KB |
4228 | /* Replacement for generic do_registers_info. |
4229 | Print regs in pretty columns. */ | |
4230 | ||
4231 | static int | |
e11c53d2 AC |
4232 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4233 | int regnum) | |
f0ef6b29 | 4234 | { |
e11c53d2 AC |
4235 | fprintf_filtered (file, " "); |
4236 | mips_print_fp_register (file, frame, regnum); | |
4237 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4238 | return regnum + 1; |
4239 | } | |
4240 | ||
4241 | ||
c906108c SS |
4242 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4243 | ||
4244 | static int | |
e11c53d2 | 4245 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4246 | int start_regnum) |
c906108c | 4247 | { |
a4b8ebc8 | 4248 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4249 | /* do values for GP (int) regs */ |
d9d9c31f | 4250 | char raw_buffer[MAX_REGISTER_SIZE]; |
c906108c SS |
4251 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ |
4252 | int col, byte; | |
a4b8ebc8 | 4253 | int regnum; |
c906108c SS |
4254 | |
4255 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4256 | fprintf_filtered (file, " "); |
a4b8ebc8 AC |
4257 | for (col = 0, regnum = start_regnum; |
4258 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4259 | regnum++) | |
c906108c SS |
4260 | { |
4261 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4262 | continue; /* unused register */ |
a4b8ebc8 | 4263 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4264 | break; /* end the row: reached FP register */ |
e11c53d2 AC |
4265 | fprintf_filtered (file, MIPS_REGSIZE == 8 ? "%17s" : "%9s", |
4266 | REGISTER_NAME (regnum)); | |
c906108c SS |
4267 | col++; |
4268 | } | |
a4b8ebc8 | 4269 | /* print the R0 to R31 names */ |
20e6603c AC |
4270 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4271 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4272 | else | |
4273 | fprintf_filtered (file, "\n "); | |
c906108c | 4274 | |
c906108c | 4275 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 AC |
4276 | for (col = 0, regnum = start_regnum; |
4277 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4278 | regnum++) | |
c906108c SS |
4279 | { |
4280 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4281 | continue; /* unused register */ |
a4b8ebc8 | 4282 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4283 | break; /* end row: reached FP register */ |
c906108c | 4284 | /* OK: get the data in raw format. */ |
e11c53d2 | 4285 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4286 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4287 | /* pad small registers */ | |
f30992d4 | 4288 | for (byte = 0; byte < (MIPS_REGSIZE - DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
4289 | printf_filtered (" "); |
4290 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4291 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
12c266ea AC |
4292 | for (byte = DEPRECATED_REGISTER_RAW_SIZE (regnum) - DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum); |
4293 | byte < DEPRECATED_REGISTER_RAW_SIZE (regnum); | |
43e526b9 | 4294 | byte++) |
e11c53d2 | 4295 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4296 | else |
f30992d4 | 4297 | for (byte = DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum) - 1; |
43e526b9 JM |
4298 | byte >= 0; |
4299 | byte--) | |
e11c53d2 AC |
4300 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4301 | fprintf_filtered (file, " "); | |
c906108c SS |
4302 | col++; |
4303 | } | |
c5aa993b | 4304 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4305 | fprintf_filtered (file, "\n"); |
c906108c SS |
4306 | |
4307 | return regnum; | |
4308 | } | |
4309 | ||
4310 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4311 | ||
bf1f5b4c | 4312 | static void |
e11c53d2 AC |
4313 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4314 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4315 | { |
c5aa993b | 4316 | if (regnum != -1) /* do one specified register */ |
c906108c | 4317 | { |
a4b8ebc8 | 4318 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4319 | if (*(REGISTER_NAME (regnum)) == '\0') |
4320 | error ("Not a valid register for the current processor type"); | |
4321 | ||
e11c53d2 AC |
4322 | mips_print_register (file, frame, regnum, 0); |
4323 | fprintf_filtered (file, "\n"); | |
c906108c | 4324 | } |
c5aa993b JM |
4325 | else |
4326 | /* do all (or most) registers */ | |
c906108c | 4327 | { |
a4b8ebc8 AC |
4328 | regnum = NUM_REGS; |
4329 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4330 | { |
a4b8ebc8 | 4331 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
e11c53d2 AC |
4332 | { |
4333 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4334 | regnum = print_fp_register_row (file, frame, regnum); | |
4335 | else | |
4336 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4337 | } | |
c906108c | 4338 | else |
e11c53d2 | 4339 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4340 | } |
4341 | } | |
4342 | } | |
4343 | ||
c906108c SS |
4344 | /* Is this a branch with a delay slot? */ |
4345 | ||
a14ed312 | 4346 | static int is_delayed (unsigned long); |
c906108c SS |
4347 | |
4348 | static int | |
acdb74a0 | 4349 | is_delayed (unsigned long insn) |
c906108c SS |
4350 | { |
4351 | int i; | |
4352 | for (i = 0; i < NUMOPCODES; ++i) | |
4353 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4354 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4355 | break; | |
4356 | return (i < NUMOPCODES | |
4357 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4358 | | INSN_COND_BRANCH_DELAY | |
4359 | | INSN_COND_BRANCH_LIKELY))); | |
4360 | } | |
4361 | ||
4362 | int | |
acdb74a0 | 4363 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4364 | { |
4365 | char buf[MIPS_INSTLEN]; | |
4366 | ||
4367 | /* There is no branch delay slot on MIPS16. */ | |
4368 | if (pc_is_mips16 (pc)) | |
4369 | return 0; | |
4370 | ||
4371 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4372 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4373 | return 0; | |
c5aa993b | 4374 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4375 | } |
4376 | ||
4377 | ||
4378 | /* Skip the PC past function prologue instructions (32-bit version). | |
4379 | This is a helper function for mips_skip_prologue. */ | |
4380 | ||
4381 | static CORE_ADDR | |
f7b9e9fc | 4382 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4383 | { |
c5aa993b JM |
4384 | t_inst inst; |
4385 | CORE_ADDR end_pc; | |
4386 | int seen_sp_adjust = 0; | |
4387 | int load_immediate_bytes = 0; | |
4388 | ||
4389 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4390 | instruction and the instructions that save registers on the stack | |
4391 | or in the gcc frame. */ | |
4392 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
4393 | { | |
4394 | unsigned long high_word; | |
c906108c | 4395 | |
c5aa993b JM |
4396 | inst = mips_fetch_instruction (pc); |
4397 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4398 | |
c5aa993b JM |
4399 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4400 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4401 | seen_sp_adjust = 1; | |
4402 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4403 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4404 | seen_sp_adjust = 1; | |
4405 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4406 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4407 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4408 | continue; | |
4409 | ||
4410 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4411 | continue; | |
4412 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4413 | /* sx reg,n($s8) */ | |
4414 | continue; /* reg != $zero */ | |
4415 | ||
4416 | /* move $s8,$sp. With different versions of gas this will be either | |
4417 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4418 | Accept any one of these. */ | |
4419 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4420 | continue; | |
4421 | ||
4422 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4423 | continue; | |
4424 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4425 | continue; | |
4426 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4427 | continue; | |
4428 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4429 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4430 | continue; | |
4431 | /* The following instructions load $at or $t0 with an immediate | |
4432 | value in preparation for a stack adjustment via | |
4433 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4434 | a local variable, so we accept them only before a stack adjustment | |
4435 | instruction was seen. */ | |
4436 | else if (!seen_sp_adjust) | |
4437 | { | |
4438 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4439 | high_word == 0x3c08) /* lui $t0,n */ | |
4440 | { | |
4441 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4442 | continue; | |
4443 | } | |
4444 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4445 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4446 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4447 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4448 | { | |
4449 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4450 | continue; | |
4451 | } | |
4452 | else | |
4453 | break; | |
4454 | } | |
4455 | else | |
4456 | break; | |
c906108c SS |
4457 | } |
4458 | ||
c5aa993b JM |
4459 | /* In a frameless function, we might have incorrectly |
4460 | skipped some load immediate instructions. Undo the skipping | |
4461 | if the load immediate was not followed by a stack adjustment. */ | |
4462 | if (load_immediate_bytes && !seen_sp_adjust) | |
4463 | pc -= load_immediate_bytes; | |
4464 | return pc; | |
c906108c SS |
4465 | } |
4466 | ||
4467 | /* Skip the PC past function prologue instructions (16-bit version). | |
4468 | This is a helper function for mips_skip_prologue. */ | |
4469 | ||
4470 | static CORE_ADDR | |
f7b9e9fc | 4471 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4472 | { |
c5aa993b JM |
4473 | CORE_ADDR end_pc; |
4474 | int extend_bytes = 0; | |
4475 | int prev_extend_bytes; | |
c906108c | 4476 | |
c5aa993b JM |
4477 | /* Table of instructions likely to be found in a function prologue. */ |
4478 | static struct | |
c906108c SS |
4479 | { |
4480 | unsigned short inst; | |
4481 | unsigned short mask; | |
c5aa993b JM |
4482 | } |
4483 | table[] = | |
4484 | { | |
c906108c | 4485 | { |
c5aa993b JM |
4486 | 0x6300, 0xff00 |
4487 | } | |
4488 | , /* addiu $sp,offset */ | |
4489 | { | |
4490 | 0xfb00, 0xff00 | |
4491 | } | |
4492 | , /* daddiu $sp,offset */ | |
4493 | { | |
4494 | 0xd000, 0xf800 | |
4495 | } | |
4496 | , /* sw reg,n($sp) */ | |
4497 | { | |
4498 | 0xf900, 0xff00 | |
4499 | } | |
4500 | , /* sd reg,n($sp) */ | |
4501 | { | |
4502 | 0x6200, 0xff00 | |
4503 | } | |
4504 | , /* sw $ra,n($sp) */ | |
4505 | { | |
4506 | 0xfa00, 0xff00 | |
4507 | } | |
4508 | , /* sd $ra,n($sp) */ | |
4509 | { | |
4510 | 0x673d, 0xffff | |
4511 | } | |
4512 | , /* move $s1,sp */ | |
4513 | { | |
4514 | 0xd980, 0xff80 | |
4515 | } | |
4516 | , /* sw $a0-$a3,n($s1) */ | |
4517 | { | |
4518 | 0x6704, 0xff1c | |
4519 | } | |
4520 | , /* move reg,$a0-$a3 */ | |
4521 | { | |
4522 | 0xe809, 0xf81f | |
4523 | } | |
4524 | , /* entry pseudo-op */ | |
4525 | { | |
4526 | 0x0100, 0xff00 | |
4527 | } | |
4528 | , /* addiu $s1,$sp,n */ | |
4529 | { | |
4530 | 0, 0 | |
4531 | } /* end of table marker */ | |
4532 | }; | |
4533 | ||
4534 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4535 | instruction and the instructions that save registers on the stack | |
4536 | or in the gcc frame. */ | |
4537 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
4538 | { | |
4539 | unsigned short inst; | |
4540 | int i; | |
c906108c | 4541 | |
c5aa993b | 4542 | inst = mips_fetch_instruction (pc); |
c906108c | 4543 | |
c5aa993b JM |
4544 | /* Normally we ignore an extend instruction. However, if it is |
4545 | not followed by a valid prologue instruction, we must adjust | |
4546 | the pc back over the extend so that it won't be considered | |
4547 | part of the prologue. */ | |
4548 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4549 | { | |
4550 | extend_bytes = MIPS16_INSTLEN; | |
4551 | continue; | |
4552 | } | |
4553 | prev_extend_bytes = extend_bytes; | |
4554 | extend_bytes = 0; | |
c906108c | 4555 | |
c5aa993b JM |
4556 | /* Check for other valid prologue instructions besides extend. */ |
4557 | for (i = 0; table[i].mask != 0; i++) | |
4558 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4559 | break; | |
4560 | if (table[i].mask != 0) /* it was in table? */ | |
4561 | continue; /* ignore it */ | |
4562 | else | |
4563 | /* non-prologue */ | |
4564 | { | |
4565 | /* Return the current pc, adjusted backwards by 2 if | |
4566 | the previous instruction was an extend. */ | |
4567 | return pc - prev_extend_bytes; | |
4568 | } | |
c906108c SS |
4569 | } |
4570 | return pc; | |
4571 | } | |
4572 | ||
4573 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4574 | if the code at PC does not look like a function prologue; otherwise | |
4575 | returns an address that (if we're lucky) follows the prologue. If | |
4576 | LENIENT, then we must skip everything which is involved in setting | |
4577 | up the frame (it's OK to skip more, just so long as we don't skip | |
4578 | anything which might clobber the registers which are being saved. | |
4579 | We must skip more in the case where part of the prologue is in the | |
4580 | delay slot of a non-prologue instruction). */ | |
4581 | ||
f7ab6ec6 | 4582 | static CORE_ADDR |
f7b9e9fc | 4583 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4584 | { |
4585 | /* See if we can determine the end of the prologue via the symbol table. | |
4586 | If so, then return either PC, or the PC after the prologue, whichever | |
4587 | is greater. */ | |
4588 | ||
4589 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4590 | ||
4591 | if (post_prologue_pc != 0) | |
4592 | return max (pc, post_prologue_pc); | |
4593 | ||
4594 | /* Can't determine prologue from the symbol table, need to examine | |
4595 | instructions. */ | |
4596 | ||
4597 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4598 | return mips16_skip_prologue (pc); |
c906108c | 4599 | else |
f7b9e9fc | 4600 | return mips32_skip_prologue (pc); |
c906108c | 4601 | } |
c906108c | 4602 | |
7a292a7a SS |
4603 | /* Determine how a return value is stored within the MIPS register |
4604 | file, given the return type `valtype'. */ | |
4605 | ||
4606 | struct return_value_word | |
4607 | { | |
4608 | int len; | |
4609 | int reg; | |
4610 | int reg_offset; | |
4611 | int buf_offset; | |
4612 | }; | |
4613 | ||
7a292a7a | 4614 | static void |
acdb74a0 AC |
4615 | return_value_location (struct type *valtype, |
4616 | struct return_value_word *hi, | |
4617 | struct return_value_word *lo) | |
7a292a7a SS |
4618 | { |
4619 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4620 | |
7a292a7a SS |
4621 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4622 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4623 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4624 | { | |
4625 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4626 | { | |
4627 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4628 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4629 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4630 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4631 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
12c266ea | 4632 | && DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM) == 8) |
7a292a7a SS |
4633 | ? 4 : 0); |
4634 | hi->reg_offset = lo->reg_offset; | |
4635 | lo->reg = FP0_REGNUM + 0; | |
4636 | hi->reg = FP0_REGNUM + 1; | |
4637 | lo->len = 4; | |
4638 | hi->len = 4; | |
4639 | } | |
4640 | else | |
4641 | { | |
4642 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4643 | register. */ |
d7449b42 | 4644 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
12c266ea | 4645 | && DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM) == 8 |
7a292a7a SS |
4646 | && len == 4) |
4647 | ? 4 : 0); | |
4648 | lo->reg = FP0_REGNUM; | |
4649 | lo->len = len; | |
4650 | lo->buf_offset = 0; | |
4651 | hi->len = 0; | |
4652 | hi->reg_offset = 0; | |
4653 | hi->buf_offset = 0; | |
4654 | hi->reg = 0; | |
4655 | } | |
4656 | } | |
4657 | else | |
4658 | { | |
4659 | /* Locate a result possibly spread across two registers. */ | |
4660 | int regnum = 2; | |
4661 | lo->reg = regnum + 0; | |
4662 | hi->reg = regnum + 1; | |
d7449b42 | 4663 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4664 | && len < MIPS_SAVED_REGSIZE) |
4665 | { | |
bf1f5b4c MS |
4666 | /* "un-left-justify" the value in the low register */ |
4667 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
bcb0cc15 | 4668 | lo->len = len; |
bf1f5b4c | 4669 | hi->reg_offset = 0; |
7a292a7a SS |
4670 | hi->len = 0; |
4671 | } | |
d7449b42 | 4672 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4673 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4674 | && len < MIPS_SAVED_REGSIZE * 2 | |
4675 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4676 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4677 | { | |
4678 | /* "un-left-justify" the value spread across two registers. */ | |
4679 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4680 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4681 | hi->reg_offset = 0; | |
4682 | hi->len = len - lo->len; | |
4683 | } | |
4684 | else | |
4685 | { | |
4686 | /* Only perform a partial copy of the second register. */ | |
4687 | lo->reg_offset = 0; | |
4688 | hi->reg_offset = 0; | |
4689 | if (len > MIPS_SAVED_REGSIZE) | |
4690 | { | |
4691 | lo->len = MIPS_SAVED_REGSIZE; | |
4692 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4693 | } | |
4694 | else | |
4695 | { | |
4696 | lo->len = len; | |
4697 | hi->len = 0; | |
4698 | } | |
4699 | } | |
d7449b42 | 4700 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
12c266ea | 4701 | && DEPRECATED_REGISTER_RAW_SIZE (regnum) == 8 |
7a292a7a SS |
4702 | && MIPS_SAVED_REGSIZE == 4) |
4703 | { | |
4704 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4705 | of the register is being used */ |
7a292a7a SS |
4706 | lo->reg_offset += 4; |
4707 | hi->reg_offset += 4; | |
4708 | } | |
4709 | lo->buf_offset = 0; | |
4710 | hi->buf_offset = lo->len; | |
4711 | } | |
4712 | } | |
4713 | ||
4714 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4715 | copy its value into `valbuf'. */ | |
4716 | ||
46cac009 AC |
4717 | static void |
4718 | mips_eabi_extract_return_value (struct type *valtype, | |
b8b527c5 | 4719 | char regbuf[], |
46cac009 AC |
4720 | char *valbuf) |
4721 | { | |
4722 | struct return_value_word lo; | |
4723 | struct return_value_word hi; | |
4724 | return_value_location (valtype, &hi, &lo); | |
4725 | ||
4726 | memcpy (valbuf + lo.buf_offset, | |
62700349 | 4727 | regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset, |
46cac009 AC |
4728 | lo.len); |
4729 | ||
4730 | if (hi.len > 0) | |
4731 | memcpy (valbuf + hi.buf_offset, | |
62700349 | 4732 | regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset, |
46cac009 AC |
4733 | hi.len); |
4734 | } | |
4735 | ||
46cac009 AC |
4736 | static void |
4737 | mips_o64_extract_return_value (struct type *valtype, | |
b8b527c5 | 4738 | char regbuf[], |
46cac009 AC |
4739 | char *valbuf) |
4740 | { | |
4741 | struct return_value_word lo; | |
4742 | struct return_value_word hi; | |
4743 | return_value_location (valtype, &hi, &lo); | |
4744 | ||
4745 | memcpy (valbuf + lo.buf_offset, | |
62700349 | 4746 | regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset, |
46cac009 AC |
4747 | lo.len); |
4748 | ||
4749 | if (hi.len > 0) | |
4750 | memcpy (valbuf + hi.buf_offset, | |
62700349 | 4751 | regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset, |
46cac009 AC |
4752 | hi.len); |
4753 | } | |
4754 | ||
7a292a7a SS |
4755 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4756 | value into the appropriate register. */ | |
4757 | ||
46cac009 AC |
4758 | static void |
4759 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4760 | { | |
d9d9c31f | 4761 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4762 | struct return_value_word lo; |
4763 | struct return_value_word hi; | |
4764 | return_value_location (valtype, &hi, &lo); | |
4765 | ||
4766 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4767 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4768 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
12c266ea | 4769 | DEPRECATED_REGISTER_RAW_SIZE (lo.reg)); |
46cac009 AC |
4770 | |
4771 | if (hi.len > 0) | |
4772 | { | |
4773 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4774 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4775 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
12c266ea | 4776 | DEPRECATED_REGISTER_RAW_SIZE (hi.reg)); |
46cac009 AC |
4777 | } |
4778 | } | |
4779 | ||
4780 | static void | |
cb1d2653 | 4781 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 | 4782 | { |
d9d9c31f | 4783 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4784 | struct return_value_word lo; |
4785 | struct return_value_word hi; | |
4786 | return_value_location (valtype, &hi, &lo); | |
4787 | ||
4788 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4789 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4790 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
12c266ea | 4791 | DEPRECATED_REGISTER_RAW_SIZE (lo.reg)); |
46cac009 AC |
4792 | |
4793 | if (hi.len > 0) | |
4794 | { | |
4795 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4796 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4797 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
12c266ea | 4798 | DEPRECATED_REGISTER_RAW_SIZE (hi.reg)); |
46cac009 AC |
4799 | } |
4800 | } | |
4801 | ||
cb1d2653 AC |
4802 | /* O32 ABI stuff. */ |
4803 | ||
46cac009 | 4804 | static void |
cb1d2653 AC |
4805 | mips_o32_xfer_return_value (struct type *type, |
4806 | struct regcache *regcache, | |
4807 | bfd_byte *in, const bfd_byte *out) | |
46cac009 | 4808 | { |
cb1d2653 AC |
4809 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4810 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4811 | && TYPE_LENGTH (type) == 4 | |
4812 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4813 | { |
cb1d2653 AC |
4814 | /* A single-precision floating-point value. It fits in the |
4815 | least significant part of FP0. */ | |
4816 | if (mips_debug) | |
4817 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
a4b8ebc8 | 4818 | mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM, TYPE_LENGTH (type), |
cb1d2653 AC |
4819 | TARGET_BYTE_ORDER, in, out, 0); |
4820 | } | |
4821 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4822 | && TYPE_LENGTH (type) == 8 | |
4823 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4824 | { | |
a4b8ebc8 AC |
4825 | /* A double-precision floating-point value. The most |
4826 | significant part goes in FP1, and the least significant in | |
4827 | FP0. */ | |
cb1d2653 | 4828 | if (mips_debug) |
a4b8ebc8 | 4829 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); |
cb1d2653 AC |
4830 | switch (TARGET_BYTE_ORDER) |
4831 | { | |
4832 | case BFD_ENDIAN_LITTLE: | |
a4b8ebc8 | 4833 | mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 0, 4, |
cb1d2653 | 4834 | TARGET_BYTE_ORDER, in, out, 0); |
a4b8ebc8 | 4835 | mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 1, 4, |
cb1d2653 AC |
4836 | TARGET_BYTE_ORDER, in, out, 4); |
4837 | break; | |
4838 | case BFD_ENDIAN_BIG: | |
a4b8ebc8 | 4839 | mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 1, 4, |
cb1d2653 | 4840 | TARGET_BYTE_ORDER, in, out, 0); |
a4b8ebc8 | 4841 | mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 0, 4, |
cb1d2653 AC |
4842 | TARGET_BYTE_ORDER, in, out, 4); |
4843 | break; | |
4844 | default: | |
4845 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4846 | } | |
4847 | } | |
4848 | #if 0 | |
4849 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4850 | && TYPE_NFIELDS (type) <= 2 | |
4851 | && TYPE_NFIELDS (type) >= 1 | |
4852 | && ((TYPE_NFIELDS (type) == 1 | |
4853 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4854 | == TYPE_CODE_FLT)) | |
4855 | || (TYPE_NFIELDS (type) == 2 | |
4856 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4857 | == TYPE_CODE_FLT) | |
4858 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4859 | == TYPE_CODE_FLT))) | |
4860 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4861 | { | |
4862 | /* A struct that contains one or two floats. Each value is part | |
4863 | in the least significant part of their floating point | |
4864 | register.. */ | |
d9d9c31f | 4865 | bfd_byte reg[MAX_REGISTER_SIZE]; |
cb1d2653 AC |
4866 | int regnum; |
4867 | int field; | |
4868 | for (field = 0, regnum = FP0_REGNUM; | |
4869 | field < TYPE_NFIELDS (type); | |
4870 | field++, regnum += 2) | |
4871 | { | |
4872 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4873 | / TARGET_CHAR_BIT); | |
4874 | if (mips_debug) | |
4875 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4876 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4877 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
cb1d2653 AC |
4878 | TARGET_BYTE_ORDER, in, out, offset); |
4879 | } | |
4880 | } | |
4881 | #endif | |
4882 | #if 0 | |
4883 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4884 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4885 | { | |
4886 | /* A structure or union. Extract the left justified value, | |
4887 | regardless of the byte order. I.e. DO NOT USE | |
4888 | mips_xfer_lower. */ | |
4889 | int offset; | |
4890 | int regnum; | |
4891 | for (offset = 0, regnum = V0_REGNUM; | |
4892 | offset < TYPE_LENGTH (type); | |
12c266ea | 4893 | offset += DEPRECATED_REGISTER_RAW_SIZE (regnum), regnum++) |
cb1d2653 | 4894 | { |
12c266ea | 4895 | int xfer = DEPRECATED_REGISTER_RAW_SIZE (regnum); |
cb1d2653 AC |
4896 | if (offset + xfer > TYPE_LENGTH (type)) |
4897 | xfer = TYPE_LENGTH (type) - offset; | |
4898 | if (mips_debug) | |
4899 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4900 | offset, xfer, regnum); | |
a4b8ebc8 AC |
4901 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
4902 | BFD_ENDIAN_UNKNOWN, in, out, offset); | |
cb1d2653 AC |
4903 | } |
4904 | } | |
4905 | #endif | |
4906 | else | |
4907 | { | |
4908 | /* A scalar extract each part but least-significant-byte | |
4909 | justified. o32 thinks registers are 4 byte, regardless of | |
4910 | the ISA. mips_stack_argsize controls this. */ | |
4911 | int offset; | |
4912 | int regnum; | |
4913 | for (offset = 0, regnum = V0_REGNUM; | |
4914 | offset < TYPE_LENGTH (type); | |
4915 | offset += mips_stack_argsize (), regnum++) | |
4916 | { | |
4917 | int xfer = mips_stack_argsize (); | |
4918 | int pos = 0; | |
4919 | if (offset + xfer > TYPE_LENGTH (type)) | |
4920 | xfer = TYPE_LENGTH (type) - offset; | |
4921 | if (mips_debug) | |
4922 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4923 | offset, xfer, regnum); | |
a4b8ebc8 AC |
4924 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
4925 | TARGET_BYTE_ORDER, in, out, offset); | |
cb1d2653 | 4926 | } |
46cac009 AC |
4927 | } |
4928 | } | |
4929 | ||
cb1d2653 AC |
4930 | static void |
4931 | mips_o32_extract_return_value (struct type *type, | |
4932 | struct regcache *regcache, | |
ebba8386 | 4933 | void *valbuf) |
cb1d2653 AC |
4934 | { |
4935 | mips_o32_xfer_return_value (type, regcache, valbuf, NULL); | |
4936 | } | |
4937 | ||
4938 | static void | |
4939 | mips_o32_store_return_value (struct type *type, char *valbuf) | |
4940 | { | |
4941 | mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf); | |
4942 | } | |
4943 | ||
4944 | /* N32/N44 ABI stuff. */ | |
4945 | ||
46cac009 | 4946 | static void |
88658117 AC |
4947 | mips_n32n64_xfer_return_value (struct type *type, |
4948 | struct regcache *regcache, | |
4949 | bfd_byte *in, const bfd_byte *out) | |
c906108c | 4950 | { |
88658117 AC |
4951 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4952 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4953 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4954 | { |
88658117 AC |
4955 | /* A floating-point value belongs in the least significant part |
4956 | of FP0. */ | |
4957 | if (mips_debug) | |
4958 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
a4b8ebc8 | 4959 | mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM, TYPE_LENGTH (type), |
88658117 AC |
4960 | TARGET_BYTE_ORDER, in, out, 0); |
4961 | } | |
4962 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4963 | && TYPE_NFIELDS (type) <= 2 | |
4964 | && TYPE_NFIELDS (type) >= 1 | |
4965 | && ((TYPE_NFIELDS (type) == 1 | |
4966 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4967 | == TYPE_CODE_FLT)) | |
4968 | || (TYPE_NFIELDS (type) == 2 | |
4969 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4970 | == TYPE_CODE_FLT) | |
4971 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4972 | == TYPE_CODE_FLT))) | |
4973 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4974 | { | |
4975 | /* A struct that contains one or two floats. Each value is part | |
4976 | in the least significant part of their floating point | |
4977 | register.. */ | |
d9d9c31f | 4978 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 AC |
4979 | int regnum; |
4980 | int field; | |
4981 | for (field = 0, regnum = FP0_REGNUM; | |
4982 | field < TYPE_NFIELDS (type); | |
4983 | field++, regnum += 2) | |
4984 | { | |
4985 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4986 | / TARGET_CHAR_BIT); | |
4987 | if (mips_debug) | |
4988 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4989 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4990 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
88658117 AC |
4991 | TARGET_BYTE_ORDER, in, out, offset); |
4992 | } | |
7a292a7a | 4993 | } |
88658117 AC |
4994 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4995 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4996 | { | |
4997 | /* A structure or union. Extract the left justified value, | |
4998 | regardless of the byte order. I.e. DO NOT USE | |
4999 | mips_xfer_lower. */ | |
5000 | int offset; | |
5001 | int regnum; | |
5002 | for (offset = 0, regnum = V0_REGNUM; | |
5003 | offset < TYPE_LENGTH (type); | |
12c266ea | 5004 | offset += DEPRECATED_REGISTER_RAW_SIZE (regnum), regnum++) |
88658117 | 5005 | { |
12c266ea | 5006 | int xfer = DEPRECATED_REGISTER_RAW_SIZE (regnum); |
88658117 AC |
5007 | if (offset + xfer > TYPE_LENGTH (type)) |
5008 | xfer = TYPE_LENGTH (type) - offset; | |
5009 | if (mips_debug) | |
5010 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5011 | offset, xfer, regnum); | |
a4b8ebc8 AC |
5012 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
5013 | BFD_ENDIAN_UNKNOWN, in, out, offset); | |
88658117 AC |
5014 | } |
5015 | } | |
5016 | else | |
5017 | { | |
5018 | /* A scalar extract each part but least-significant-byte | |
5019 | justified. */ | |
5020 | int offset; | |
5021 | int regnum; | |
5022 | for (offset = 0, regnum = V0_REGNUM; | |
5023 | offset < TYPE_LENGTH (type); | |
12c266ea | 5024 | offset += DEPRECATED_REGISTER_RAW_SIZE (regnum), regnum++) |
88658117 | 5025 | { |
12c266ea | 5026 | int xfer = DEPRECATED_REGISTER_RAW_SIZE (regnum); |
88658117 AC |
5027 | int pos = 0; |
5028 | if (offset + xfer > TYPE_LENGTH (type)) | |
5029 | xfer = TYPE_LENGTH (type) - offset; | |
5030 | if (mips_debug) | |
5031 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5032 | offset, xfer, regnum); | |
a4b8ebc8 AC |
5033 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
5034 | TARGET_BYTE_ORDER, in, out, offset); | |
88658117 AC |
5035 | } |
5036 | } | |
5037 | } | |
5038 | ||
5039 | static void | |
5040 | mips_n32n64_extract_return_value (struct type *type, | |
5041 | struct regcache *regcache, | |
ebba8386 | 5042 | void *valbuf) |
88658117 AC |
5043 | { |
5044 | mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL); | |
5045 | } | |
5046 | ||
5047 | static void | |
5048 | mips_n32n64_store_return_value (struct type *type, char *valbuf) | |
5049 | { | |
5050 | mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf); | |
c906108c SS |
5051 | } |
5052 | ||
2f1488ce | 5053 | static CORE_ADDR |
6672060b | 5054 | mips_extract_struct_value_address (struct regcache *regcache) |
2f1488ce MS |
5055 | { |
5056 | /* FIXME: This will only work at random. The caller passes the | |
5057 | struct_return address in V0, but it is not preserved. It may | |
5058 | still be there, or this may be a random value. */ | |
77d8f2b4 MS |
5059 | LONGEST val; |
5060 | ||
5061 | regcache_cooked_read_signed (regcache, V0_REGNUM, &val); | |
6672060b | 5062 | return val; |
2f1488ce MS |
5063 | } |
5064 | ||
c906108c SS |
5065 | /* Exported procedure: Is PC in the signal trampoline code */ |
5066 | ||
102182a9 MS |
5067 | static int |
5068 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
5069 | { |
5070 | if (sigtramp_address == 0) | |
5071 | fixup_sigtramp (); | |
5072 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
5073 | } | |
5074 | ||
a5ea2558 AC |
5075 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5076 | used for all MIPS-specific commands. */ | |
5077 | ||
a5ea2558 | 5078 | static void |
acdb74a0 | 5079 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5080 | { |
5081 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5082 | } | |
5083 | ||
a5ea2558 | 5084 | static void |
acdb74a0 | 5085 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5086 | { |
5087 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
5088 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
5089 | } | |
5090 | ||
c906108c SS |
5091 | /* Commands to show/set the MIPS FPU type. */ |
5092 | ||
c906108c | 5093 | static void |
acdb74a0 | 5094 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5095 | { |
c906108c SS |
5096 | char *fpu; |
5097 | switch (MIPS_FPU_TYPE) | |
5098 | { | |
5099 | case MIPS_FPU_SINGLE: | |
5100 | fpu = "single-precision"; | |
5101 | break; | |
5102 | case MIPS_FPU_DOUBLE: | |
5103 | fpu = "double-precision"; | |
5104 | break; | |
5105 | case MIPS_FPU_NONE: | |
5106 | fpu = "absent (none)"; | |
5107 | break; | |
93d56215 AC |
5108 | default: |
5109 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5110 | } |
5111 | if (mips_fpu_type_auto) | |
5112 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5113 | fpu); | |
5114 | else | |
5115 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
5116 | fpu); | |
5117 | } | |
5118 | ||
5119 | ||
c906108c | 5120 | static void |
acdb74a0 | 5121 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
5122 | { |
5123 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
5124 | show_mipsfpu_command (args, from_tty); | |
5125 | } | |
5126 | ||
c906108c | 5127 | static void |
acdb74a0 | 5128 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
5129 | { |
5130 | mips_fpu_type = MIPS_FPU_SINGLE; | |
5131 | mips_fpu_type_auto = 0; | |
9e364162 | 5132 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
5133 | } |
5134 | ||
c906108c | 5135 | static void |
acdb74a0 | 5136 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
5137 | { |
5138 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
5139 | mips_fpu_type_auto = 0; | |
9e364162 | 5140 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
5141 | } |
5142 | ||
c906108c | 5143 | static void |
acdb74a0 | 5144 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
5145 | { |
5146 | mips_fpu_type = MIPS_FPU_NONE; | |
5147 | mips_fpu_type_auto = 0; | |
9e364162 | 5148 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
5149 | } |
5150 | ||
c906108c | 5151 | static void |
acdb74a0 | 5152 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5153 | { |
5154 | mips_fpu_type_auto = 1; | |
5155 | } | |
5156 | ||
5157 | /* Command to set the processor type. */ | |
5158 | ||
5159 | void | |
acdb74a0 | 5160 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
5161 | { |
5162 | int i; | |
5163 | ||
5164 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
5165 | { | |
5166 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
5167 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5168 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
5169 | ||
5170 | /* Restore the value. */ | |
4fcf66da | 5171 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5172 | |
5173 | return; | |
5174 | } | |
c5aa993b | 5175 | |
c906108c SS |
5176 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
5177 | { | |
5178 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
5179 | /* Restore its value. */ | |
4fcf66da | 5180 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5181 | } |
5182 | } | |
5183 | ||
5184 | static void | |
acdb74a0 | 5185 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
5186 | { |
5187 | } | |
5188 | ||
5189 | /* Modify the actual processor type. */ | |
5190 | ||
5a89d8aa | 5191 | static int |
acdb74a0 | 5192 | mips_set_processor_type (char *str) |
c906108c | 5193 | { |
1012bd0e | 5194 | int i; |
c906108c SS |
5195 | |
5196 | if (str == NULL) | |
5197 | return 0; | |
5198 | ||
5199 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5200 | { | |
5201 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
5202 | { | |
5203 | mips_processor_type = str; | |
cce74817 | 5204 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 5205 | return 1; |
c906108c SS |
5206 | /* FIXME tweak fpu flag too */ |
5207 | } | |
5208 | } | |
5209 | ||
5210 | return 0; | |
5211 | } | |
5212 | ||
5213 | /* Attempt to identify the particular processor model by reading the | |
5214 | processor id. */ | |
5215 | ||
5216 | char * | |
acdb74a0 | 5217 | mips_read_processor_type (void) |
c906108c SS |
5218 | { |
5219 | CORE_ADDR prid; | |
5220 | ||
5221 | prid = read_register (PRID_REGNUM); | |
5222 | ||
5223 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 5224 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
5225 | |
5226 | return NULL; | |
5227 | } | |
5228 | ||
5229 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5230 | callable as an sfunc. */ | |
5231 | ||
5232 | static void | |
acdb74a0 AC |
5233 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5234 | struct cmd_list_element *c) | |
c906108c SS |
5235 | { |
5236 | reinit_frame_cache (); | |
5237 | } | |
5238 | ||
a89aa300 AC |
5239 | static int |
5240 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5241 | { |
e5ab0dce | 5242 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5243 | mips_extra_func_info_t proc_desc; |
5244 | ||
5245 | /* Search for the function containing this address. Set the low bit | |
5246 | of the address when searching, in case we were given an even address | |
5247 | that is the start of a 16-bit function. If we didn't do this, | |
5248 | the search would fail because the symbol table says the function | |
5249 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5250 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5251 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5252 | |
5253 | /* Make an attempt to determine if this is a 16-bit function. If | |
5254 | the procedure descriptor exists and the address therein is odd, | |
5255 | it's definitely a 16-bit function. Otherwise, we have to just | |
5256 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5257 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5258 | disassembler needs to be able to locally determine the ISA, and | |
5259 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5260 | work. */ | |
c906108c | 5261 | if (proc_desc) |
d31431ed AC |
5262 | { |
5263 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
5264 | info->mach = bfd_mach_mips16; | |
5265 | } | |
c906108c | 5266 | else |
d31431ed AC |
5267 | { |
5268 | if (pc_is_mips16 (memaddr)) | |
5269 | info->mach = bfd_mach_mips16; | |
5270 | } | |
c906108c SS |
5271 | |
5272 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5273 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5274 | |
e5ab0dce AC |
5275 | /* Set the disassembler options. */ |
5276 | if (tdep->mips_abi == MIPS_ABI_N32 | |
5277 | || tdep->mips_abi == MIPS_ABI_N64) | |
5278 | { | |
5279 | /* Set up the disassembler info, so that we get the right | |
5280 | register names from libopcodes. */ | |
5281 | if (tdep->mips_abi == MIPS_ABI_N32) | |
5282 | info->disassembler_options = "gpr-names=n32"; | |
5283 | else | |
5284 | info->disassembler_options = "gpr-names=64"; | |
5285 | info->flavour = bfd_target_elf_flavour; | |
5286 | } | |
5287 | else | |
5288 | /* This string is not recognized explicitly by the disassembler, | |
5289 | but it tells the disassembler to not try to guess the ABI from | |
5290 | the bfd elf headers, such that, if the user overrides the ABI | |
5291 | of a program linked as NewABI, the disassembly will follow the | |
5292 | register naming conventions specified by the user. */ | |
5293 | info->disassembler_options = "gpr-names=32"; | |
5294 | ||
c906108c | 5295 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5296 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5297 | return print_insn_big_mips (memaddr, info); |
5298 | else | |
5299 | return print_insn_little_mips (memaddr, info); | |
5300 | } | |
5301 | ||
c906108c SS |
5302 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5303 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5304 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5305 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5306 | (if necessary) to point to the actual memory location where the | |
5307 | breakpoint should be inserted. */ | |
5308 | ||
f7ab6ec6 | 5309 | static const unsigned char * |
acdb74a0 | 5310 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5311 | { |
d7449b42 | 5312 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5313 | { |
5314 | if (pc_is_mips16 (*pcptr)) | |
5315 | { | |
aaab4dba | 5316 | static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5}; |
95404a3e | 5317 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5318 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5319 | return mips16_big_breakpoint; |
5320 | } | |
5321 | else | |
5322 | { | |
aaab4dba AC |
5323 | /* The IDT board uses an unusual breakpoint value, and |
5324 | sometimes gets confused when it sees the usual MIPS | |
5325 | breakpoint instruction. */ | |
5326 | static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd}; | |
5327 | static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd}; | |
5328 | static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd}; | |
c906108c | 5329 | |
c5aa993b | 5330 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5331 | |
5332 | if (strcmp (target_shortname, "mips") == 0) | |
5333 | return idt_big_breakpoint; | |
5334 | else if (strcmp (target_shortname, "ddb") == 0 | |
5335 | || strcmp (target_shortname, "pmon") == 0 | |
5336 | || strcmp (target_shortname, "lsi") == 0) | |
5337 | return pmon_big_breakpoint; | |
5338 | else | |
5339 | return big_breakpoint; | |
5340 | } | |
5341 | } | |
5342 | else | |
5343 | { | |
5344 | if (pc_is_mips16 (*pcptr)) | |
5345 | { | |
aaab4dba | 5346 | static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8}; |
95404a3e | 5347 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5348 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5349 | return mips16_little_breakpoint; |
5350 | } | |
5351 | else | |
5352 | { | |
aaab4dba AC |
5353 | static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0}; |
5354 | static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0}; | |
5355 | static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0}; | |
c906108c | 5356 | |
c5aa993b | 5357 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5358 | |
5359 | if (strcmp (target_shortname, "mips") == 0) | |
5360 | return idt_little_breakpoint; | |
5361 | else if (strcmp (target_shortname, "ddb") == 0 | |
5362 | || strcmp (target_shortname, "pmon") == 0 | |
5363 | || strcmp (target_shortname, "lsi") == 0) | |
5364 | return pmon_little_breakpoint; | |
5365 | else | |
5366 | return little_breakpoint; | |
5367 | } | |
5368 | } | |
5369 | } | |
5370 | ||
5371 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5372 | PC, which is either the callee or the caller. There are several | |
5373 | cases which must be handled: | |
5374 | ||
5375 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5376 | target PC is in $31 ($ra). |
c906108c | 5377 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5378 | and the target PC is in $2. |
c906108c | 5379 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5380 | before the jal instruction, this is effectively a call stub |
5381 | and the the target PC is in $2. Otherwise this is effectively | |
5382 | a return stub and the target PC is in $18. | |
c906108c SS |
5383 | |
5384 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5385 | gory details. | |
5386 | ||
5387 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5388 | */ |
c906108c | 5389 | |
757a7cc6 | 5390 | static CORE_ADDR |
acdb74a0 | 5391 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5392 | { |
5393 | char *name; | |
5394 | CORE_ADDR start_addr; | |
5395 | ||
5396 | /* Find the starting address and name of the function containing the PC. */ | |
5397 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5398 | return 0; | |
5399 | ||
5400 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5401 | target PC is in $31 ($ra). */ | |
5402 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5403 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5404 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5405 | |
5406 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5407 | { | |
5408 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5409 | and the target PC is in $2. */ | |
5410 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5411 | return read_signed_register (2); |
c906108c SS |
5412 | |
5413 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5414 | before the jal instruction, this is effectively a call stub |
5415 | and the the target PC is in $2. Otherwise this is effectively | |
5416 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5417 | else if (name[19] == 's' || name[19] == 'd') |
5418 | { | |
5419 | if (pc == start_addr) | |
5420 | { | |
5421 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5422 | stub. Such a stub for a function bar might have a name |
5423 | like __fn_stub_bar, and might look like this: | |
5424 | mfc1 $4,$f13 | |
5425 | mfc1 $5,$f12 | |
5426 | mfc1 $6,$f15 | |
5427 | mfc1 $7,$f14 | |
5428 | la $1,bar (becomes a lui/addiu pair) | |
5429 | jr $1 | |
5430 | So scan down to the lui/addi and extract the target | |
5431 | address from those two instructions. */ | |
c906108c | 5432 | |
6c997a34 | 5433 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5434 | t_inst inst; |
5435 | int i; | |
5436 | ||
5437 | /* See if the name of the target function is __fn_stub_*. */ | |
5438 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5439 | return target_pc; | |
5440 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5441 | && strcmp (name, "etext") != 0 | |
5442 | && strcmp (name, "_etext") != 0) | |
5443 | return target_pc; | |
5444 | ||
5445 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5446 | The limit on the search is arbitrarily set to 20 |
5447 | instructions. FIXME. */ | |
c906108c SS |
5448 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5449 | { | |
c5aa993b JM |
5450 | inst = mips_fetch_instruction (target_pc); |
5451 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5452 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5453 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5454 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5455 | } |
5456 | ||
5457 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5458 | return target_pc; | |
5459 | } | |
5460 | else | |
5461 | /* This is the 'return' part of a call stub. The return | |
5462 | address is in $r18. */ | |
6c997a34 | 5463 | return read_signed_register (18); |
c906108c SS |
5464 | } |
5465 | } | |
c5aa993b | 5466 | return 0; /* not a stub */ |
c906108c SS |
5467 | } |
5468 | ||
5469 | ||
5470 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5471 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5472 | ||
757a7cc6 | 5473 | static int |
acdb74a0 | 5474 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5475 | { |
5476 | CORE_ADDR start_addr; | |
5477 | ||
5478 | /* Find the starting address of the function containing the PC. If the | |
5479 | caller didn't give us a name, look it up at the same time. */ | |
5480 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5481 | return 0; | |
5482 | ||
5483 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5484 | { | |
5485 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5486 | if (name[19] >= '0' && name[19] <= '9') | |
5487 | return 1; | |
5488 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5489 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5490 | else if (name[19] == 's' || name[19] == 'd') |
5491 | return pc == start_addr; | |
5492 | } | |
5493 | ||
c5aa993b | 5494 | return 0; /* not a stub */ |
c906108c SS |
5495 | } |
5496 | ||
5497 | ||
5498 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5499 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5500 | ||
e41b17f0 | 5501 | static int |
acdb74a0 | 5502 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5503 | { |
5504 | CORE_ADDR start_addr; | |
5505 | ||
5506 | /* Find the starting address of the function containing the PC. */ | |
5507 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5508 | return 0; | |
5509 | ||
5510 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5511 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5512 | || strcmp (name, "__mips16_ret_df") == 0) | |
5513 | return 1; | |
5514 | ||
5515 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5516 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5517 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5518 | && (name[19] == 's' || name[19] == 'd') | |
5519 | && pc != start_addr) | |
5520 | return 1; | |
5521 | ||
c5aa993b | 5522 | return 0; /* not a stub */ |
c906108c SS |
5523 | } |
5524 | ||
5525 | ||
5526 | /* Return non-zero if the PC is in a library helper function that should | |
5527 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5528 | ||
5529 | int | |
acdb74a0 | 5530 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5531 | { |
5532 | char *name; | |
5533 | ||
5534 | /* Find the starting address and name of the function containing the PC. */ | |
5535 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5536 | return 0; | |
5537 | ||
5538 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5539 | that we want to ignore. */ | |
5540 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5541 | || strcmp (name, "__mips16_ret_df") == 0); | |
5542 | } | |
5543 | ||
5544 | ||
47a8d4ba AC |
5545 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5546 | the register stored on the stack (32) is different to its real raw | |
5547 | size (64). The below ensures that registers are fetched from the | |
5548 | stack using their ABI size and then stored into the RAW_BUFFER | |
5549 | using their raw size. | |
5550 | ||
5551 | The alternative to adding this function would be to add an ABI | |
5552 | macro - REGISTER_STACK_SIZE(). */ | |
5553 | ||
5554 | static void | |
acdb74a0 | 5555 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5556 | int *optimizedp, |
acdb74a0 AC |
5557 | CORE_ADDR *addrp, |
5558 | struct frame_info *frame, | |
5559 | int regnum, | |
795e1e11 | 5560 | enum lval_type *lvalp) |
47a8d4ba | 5561 | { |
795e1e11 AC |
5562 | CORE_ADDR addrx; |
5563 | enum lval_type lvalx; | |
5564 | int optimizedx; | |
6e51443a | 5565 | int realnumx; |
47a8d4ba | 5566 | |
a4b8ebc8 AC |
5567 | /* Always a pseudo. */ |
5568 | gdb_assert (regnum >= NUM_REGS); | |
47a8d4ba | 5569 | |
795e1e11 AC |
5570 | /* Make certain that all needed parameters are present. */ |
5571 | if (addrp == NULL) | |
5572 | addrp = &addrx; | |
5573 | if (lvalp == NULL) | |
5574 | lvalp = &lvalx; | |
5575 | if (optimizedp == NULL) | |
5576 | optimizedp = &optimizedx; | |
a4b8ebc8 AC |
5577 | |
5578 | if ((regnum % NUM_REGS) == SP_REGNUM) | |
5579 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
5580 | In fact, it is so special that it can even only be fetched | |
5581 | using a raw register number! Once this code as been converted | |
5582 | to frame-unwind the problem goes away. */ | |
5583 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5584 | regnum % NUM_REGS, optimizedp, lvalp, addrp, | |
5585 | &realnumx, raw_buffer); | |
5586 | else | |
5587 | /* Get it from the next frame. */ | |
5588 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5589 | regnum, optimizedp, lvalp, addrp, | |
5590 | &realnumx, raw_buffer); | |
47a8d4ba | 5591 | } |
2acceee2 | 5592 | |
f7b9e9fc AC |
5593 | /* Immediately after a function call, return the saved pc. |
5594 | Can't always go through the frames for this because on some machines | |
5595 | the new frame is not set up until the new function executes | |
5596 | some instructions. */ | |
5597 | ||
5598 | static CORE_ADDR | |
5599 | mips_saved_pc_after_call (struct frame_info *frame) | |
5600 | { | |
6c997a34 | 5601 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5602 | } |
5603 | ||
5604 | ||
a4b8ebc8 AC |
5605 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5606 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5607 | |
5608 | static int | |
5609 | mips_stab_reg_to_regnum (int num) | |
5610 | { | |
a4b8ebc8 | 5611 | int regnum; |
2f38ef89 | 5612 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5613 | regnum = num; |
2f38ef89 | 5614 | else if (num >= 38 && num < 70) |
a4b8ebc8 | 5615 | regnum = num + FP0_REGNUM - 38; |
040b99fd | 5616 | else if (num == 70) |
a4b8ebc8 | 5617 | regnum = HI_REGNUM; |
040b99fd | 5618 | else if (num == 71) |
a4b8ebc8 | 5619 | regnum = LO_REGNUM; |
2f38ef89 | 5620 | else |
a4b8ebc8 AC |
5621 | /* This will hopefully (eventually) provoke a warning. Should |
5622 | we be calling complaint() here? */ | |
5623 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5624 | return NUM_REGS + regnum; | |
88c72b7d AC |
5625 | } |
5626 | ||
2f38ef89 | 5627 | |
a4b8ebc8 AC |
5628 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5629 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5630 | |
5631 | static int | |
2f38ef89 | 5632 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5633 | { |
a4b8ebc8 | 5634 | int regnum; |
2f38ef89 | 5635 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5636 | regnum = num; |
2f38ef89 | 5637 | else if (num >= 32 && num < 64) |
a4b8ebc8 | 5638 | regnum = num + FP0_REGNUM - 32; |
040b99fd | 5639 | else if (num == 64) |
a4b8ebc8 | 5640 | regnum = HI_REGNUM; |
040b99fd | 5641 | else if (num == 65) |
a4b8ebc8 | 5642 | regnum = LO_REGNUM; |
2f38ef89 | 5643 | else |
a4b8ebc8 AC |
5644 | /* This will hopefully (eventually) provoke a warning. Should we |
5645 | be calling complaint() here? */ | |
5646 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5647 | return NUM_REGS + regnum; | |
5648 | } | |
5649 | ||
5650 | static int | |
5651 | mips_register_sim_regno (int regnum) | |
5652 | { | |
5653 | /* Only makes sense to supply raw registers. */ | |
5654 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5655 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5656 | decide if it is valid. Should instead define a standard sim/gdb | |
5657 | register numbering scheme. */ | |
5658 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5659 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5660 | return regnum; | |
5661 | else | |
5662 | return LEGACY_SIM_REGNO_IGNORE; | |
88c72b7d AC |
5663 | } |
5664 | ||
2f38ef89 | 5665 | |
fc0c74b1 AC |
5666 | /* Convert an integer into an address. By first converting the value |
5667 | into a pointer and then extracting it signed, the address is | |
5668 | guarenteed to be correctly sign extended. */ | |
5669 | ||
5670 | static CORE_ADDR | |
5671 | mips_integer_to_address (struct type *type, void *buf) | |
5672 | { | |
5673 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5674 | LONGEST val = unpack_long (type, buf); | |
5675 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5676 | return extract_signed_integer (tmp, | |
5677 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5678 | } | |
5679 | ||
caaa3122 DJ |
5680 | static void |
5681 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5682 | { | |
5683 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5684 | const char *name = bfd_get_section_name (abfd, sect); | |
5685 | ||
5686 | if (*abip != MIPS_ABI_UNKNOWN) | |
5687 | return; | |
5688 | ||
5689 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5690 | return; | |
5691 | ||
5692 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5693 | *abip = MIPS_ABI_O32; | |
5694 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5695 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5696 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5697 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5698 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5699 | *abip = MIPS_ABI_O64; | |
5700 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5701 | *abip = MIPS_ABI_EABI32; | |
5702 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5703 | *abip = MIPS_ABI_EABI64; | |
5704 | else | |
5705 | warning ("unsupported ABI %s.", name + 8); | |
5706 | } | |
5707 | ||
2e4ebe70 DJ |
5708 | static enum mips_abi |
5709 | global_mips_abi (void) | |
5710 | { | |
5711 | int i; | |
5712 | ||
5713 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5714 | if (mips_abi_strings[i] == mips_abi_string) | |
5715 | return (enum mips_abi) i; | |
5716 | ||
5717 | internal_error (__FILE__, __LINE__, | |
5718 | "unknown ABI string"); | |
5719 | } | |
5720 | ||
c2d11a7d | 5721 | static struct gdbarch * |
acdb74a0 AC |
5722 | mips_gdbarch_init (struct gdbarch_info info, |
5723 | struct gdbarch_list *arches) | |
c2d11a7d | 5724 | { |
c2d11a7d JM |
5725 | struct gdbarch *gdbarch; |
5726 | struct gdbarch_tdep *tdep; | |
5727 | int elf_flags; | |
2e4ebe70 | 5728 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5729 | int num_regs; |
c2d11a7d | 5730 | |
70f80edf JT |
5731 | elf_flags = 0; |
5732 | ||
5733 | if (info.abfd) | |
5734 | { | |
5735 | /* First of all, extract the elf_flags, if available. */ | |
5736 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5737 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
70f80edf | 5738 | } |
c2d11a7d | 5739 | |
102182a9 | 5740 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5741 | switch ((elf_flags & EF_MIPS_ABI)) |
5742 | { | |
5743 | case E_MIPS_ABI_O32: | |
5744 | mips_abi = MIPS_ABI_O32; | |
5745 | break; | |
5746 | case E_MIPS_ABI_O64: | |
5747 | mips_abi = MIPS_ABI_O64; | |
5748 | break; | |
5749 | case E_MIPS_ABI_EABI32: | |
5750 | mips_abi = MIPS_ABI_EABI32; | |
5751 | break; | |
5752 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 5753 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5754 | break; |
5755 | default: | |
acdb74a0 AC |
5756 | if ((elf_flags & EF_MIPS_ABI2)) |
5757 | mips_abi = MIPS_ABI_N32; | |
5758 | else | |
5759 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
5760 | break; |
5761 | } | |
acdb74a0 | 5762 | |
caaa3122 DJ |
5763 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
5764 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
5765 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
5766 | ||
2e4ebe70 DJ |
5767 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
5768 | Use the ABI from the last architecture if there is one. */ | |
5769 | if (info.abfd == NULL && arches != NULL) | |
5770 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
5771 | ||
32a6503c | 5772 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
5773 | if (mips_abi == MIPS_ABI_UNKNOWN |
5774 | && info.bfd_arch_info != NULL | |
5775 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5776 | { | |
5777 | switch (info.bfd_arch_info->mach) | |
5778 | { | |
5779 | case bfd_mach_mips3900: | |
5780 | mips_abi = MIPS_ABI_EABI32; | |
5781 | break; | |
5782 | case bfd_mach_mips4100: | |
5783 | case bfd_mach_mips5000: | |
5784 | mips_abi = MIPS_ABI_EABI64; | |
5785 | break; | |
1d06468c EZ |
5786 | case bfd_mach_mips8000: |
5787 | case bfd_mach_mips10000: | |
32a6503c KB |
5788 | /* On Irix, ELF64 executables use the N64 ABI. The |
5789 | pseudo-sections which describe the ABI aren't present | |
5790 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5791 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5792 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5793 | mips_abi = MIPS_ABI_N64; | |
5794 | else | |
5795 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 5796 | break; |
bf64bfd6 AC |
5797 | } |
5798 | } | |
2e4ebe70 | 5799 | |
2e4ebe70 DJ |
5800 | if (mips_abi == MIPS_ABI_UNKNOWN) |
5801 | mips_abi = MIPS_ABI_O32; | |
5802 | ||
5803 | /* Now that we have found what the ABI for this binary would be, | |
5804 | check whether the user is overriding it. */ | |
5805 | found_abi = mips_abi; | |
5806 | wanted_abi = global_mips_abi (); | |
5807 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
5808 | mips_abi = wanted_abi; | |
5809 | ||
4b9b3959 AC |
5810 | if (gdbarch_debug) |
5811 | { | |
5812 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 5813 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 5814 | elf_flags); |
4b9b3959 AC |
5815 | fprintf_unfiltered (gdb_stdlog, |
5816 | "mips_gdbarch_init: mips_abi = %d\n", | |
5817 | mips_abi); | |
2e4ebe70 DJ |
5818 | fprintf_unfiltered (gdb_stdlog, |
5819 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
5820 | found_abi); | |
4b9b3959 | 5821 | } |
0dadbba0 | 5822 | |
c2d11a7d JM |
5823 | /* try to find a pre-existing architecture */ |
5824 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5825 | arches != NULL; | |
5826 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5827 | { | |
5828 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5829 | using. */ |
9103eae0 | 5830 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5831 | continue; |
9103eae0 | 5832 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5833 | continue; |
4be87837 | 5834 | return arches->gdbarch; |
c2d11a7d JM |
5835 | } |
5836 | ||
102182a9 | 5837 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5838 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5839 | gdbarch = gdbarch_alloc (&info, tdep); | |
5840 | tdep->elf_flags = elf_flags; | |
5841 | ||
102182a9 | 5842 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5843 | set_gdbarch_short_bit (gdbarch, 16); |
5844 | set_gdbarch_int_bit (gdbarch, 32); | |
5845 | set_gdbarch_float_bit (gdbarch, 32); | |
5846 | set_gdbarch_double_bit (gdbarch, 64); | |
5847 | set_gdbarch_long_double_bit (gdbarch, 64); | |
9c04cab7 | 5848 | set_gdbarch_deprecated_register_raw_size (gdbarch, mips_register_raw_size); |
a4b8ebc8 AC |
5849 | set_gdbarch_deprecated_register_byte (gdbarch, mips_register_byte); |
5850 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); | |
5851 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5852 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
2e4ebe70 | 5853 | tdep->found_abi = found_abi; |
0dadbba0 | 5854 | tdep->mips_abi = mips_abi; |
1d06468c | 5855 | |
f7ab6ec6 MS |
5856 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5857 | mips_elf_make_msymbol_special); | |
5858 | ||
a4b8ebc8 | 5859 | |
4be87837 | 5860 | if (info.osabi == GDB_OSABI_IRIX) |
a4b8ebc8 | 5861 | num_regs = 71; |
fe29b929 | 5862 | else |
a4b8ebc8 AC |
5863 | num_regs = 90; |
5864 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5865 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
fe29b929 | 5866 | |
0dadbba0 | 5867 | switch (mips_abi) |
c2d11a7d | 5868 | { |
0dadbba0 | 5869 | case MIPS_ABI_O32: |
25ab4790 | 5870 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
ebba8386 | 5871 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value); |
cb1d2653 | 5872 | set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value); |
a5ea2558 | 5873 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5874 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5875 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5876 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5877 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5878 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5879 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5880 | set_gdbarch_long_bit (gdbarch, 32); |
5881 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5882 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5883 | set_gdbarch_deprecated_reg_struct_has_addr |
5884 | (gdbarch, mips_o32_reg_struct_has_addr); | |
cb811fe7 | 5885 | set_gdbarch_use_struct_convention (gdbarch, |
1fd35568 | 5886 | always_use_struct_convention); |
c2d11a7d | 5887 | break; |
0dadbba0 | 5888 | case MIPS_ABI_O64: |
25ab4790 | 5889 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
ebba8386 | 5890 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5891 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5892 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5893 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5894 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5895 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5896 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5897 | tdep->gdb_target_is_mips64 = 1; |
361d1df0 | 5898 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5899 | set_gdbarch_long_bit (gdbarch, 32); |
5900 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5901 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5902 | set_gdbarch_deprecated_reg_struct_has_addr |
5903 | (gdbarch, mips_o32_reg_struct_has_addr); | |
b060cbea | 5904 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 5905 | break; |
0dadbba0 | 5906 | case MIPS_ABI_EABI32: |
25ab4790 | 5907 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5908 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5909 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5910 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5911 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5912 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5913 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5914 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5915 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5916 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5917 | set_gdbarch_long_bit (gdbarch, 32); |
5918 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5919 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5920 | set_gdbarch_deprecated_reg_struct_has_addr |
5921 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5922 | set_gdbarch_use_struct_convention (gdbarch, |
5923 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5924 | break; |
0dadbba0 | 5925 | case MIPS_ABI_EABI64: |
25ab4790 | 5926 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5927 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5928 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5929 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5930 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5931 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5932 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5933 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5934 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5935 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5936 | set_gdbarch_long_bit (gdbarch, 64); |
5937 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5938 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5939 | set_gdbarch_deprecated_reg_struct_has_addr |
5940 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5941 | set_gdbarch_use_struct_convention (gdbarch, |
5942 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5943 | break; |
0dadbba0 | 5944 | case MIPS_ABI_N32: |
25ab4790 | 5945 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
ebba8386 | 5946 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5947 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
63db5580 | 5948 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5949 | tdep->mips_default_stack_argsize = 8; |
5950 | tdep->mips_fp_register_double = 1; | |
acdb74a0 AC |
5951 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5952 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
6acdf5c7 | 5953 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5954 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5955 | set_gdbarch_long_bit (gdbarch, 32); |
5956 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5957 | set_gdbarch_long_long_bit (gdbarch, 64); | |
cb811fe7 MS |
5958 | set_gdbarch_use_struct_convention (gdbarch, |
5959 | mips_n32n64_use_struct_convention); | |
2110b94f MK |
5960 | set_gdbarch_deprecated_reg_struct_has_addr |
5961 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5962 | break; |
5963 | case MIPS_ABI_N64: | |
25ab4790 | 5964 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
ebba8386 | 5965 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5966 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
28d169de KB |
5967 | tdep->mips_default_saved_regsize = 8; |
5968 | tdep->mips_default_stack_argsize = 8; | |
5969 | tdep->mips_fp_register_double = 1; | |
5970 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
5971 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
28d169de KB |
5972 | tdep->gdb_target_is_mips64 = 1; |
5973 | tdep->default_mask_address_p = 0; | |
5974 | set_gdbarch_long_bit (gdbarch, 64); | |
5975 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5976 | set_gdbarch_long_long_bit (gdbarch, 64); | |
cb811fe7 MS |
5977 | set_gdbarch_use_struct_convention (gdbarch, |
5978 | mips_n32n64_use_struct_convention); | |
2110b94f MK |
5979 | set_gdbarch_deprecated_reg_struct_has_addr |
5980 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5981 | break; |
c2d11a7d | 5982 | default: |
2e4ebe70 DJ |
5983 | internal_error (__FILE__, __LINE__, |
5984 | "unknown ABI in switch"); | |
c2d11a7d JM |
5985 | } |
5986 | ||
a5ea2558 AC |
5987 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5988 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5989 | comment: | |
5990 | ||
5991 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5992 | flag in object files because to do so would make it impossible to | |
102182a9 | 5993 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5994 | unnecessarily restrictive. |
361d1df0 | 5995 | |
a5ea2558 AC |
5996 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5997 | but to set this flag before gcc is built with such multilibs will | |
5998 | break too many systems.'' | |
5999 | ||
6000 | But even more unhelpfully, the default linker output target for | |
6001 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6002 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6003 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6004 | this flag to detect 32-bit mode would do the wrong thing given |
6005 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6006 | as 32-bit programs by default. */ |
a5ea2558 | 6007 | |
c2d11a7d JM |
6008 | /* enable/disable the MIPS FPU */ |
6009 | if (!mips_fpu_type_auto) | |
6010 | tdep->mips_fpu_type = mips_fpu_type; | |
6011 | else if (info.bfd_arch_info != NULL | |
6012 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6013 | switch (info.bfd_arch_info->mach) | |
6014 | { | |
b0069a17 | 6015 | case bfd_mach_mips3900: |
c2d11a7d | 6016 | case bfd_mach_mips4100: |
ed9a39eb | 6017 | case bfd_mach_mips4111: |
c2d11a7d JM |
6018 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
6019 | break; | |
bf64bfd6 AC |
6020 | case bfd_mach_mips4650: |
6021 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
6022 | break; | |
c2d11a7d JM |
6023 | default: |
6024 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
6025 | break; | |
6026 | } | |
6027 | else | |
6028 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
6029 | ||
6030 | /* MIPS version of register names. NOTE: At present the MIPS | |
6031 | register name management is part way between the old - | |
77949794 | 6032 | #undef/#define MIPS_REGISTER_NAMES and the new REGISTER_NAME(nr). |
102182a9 | 6033 | Further work on it is required. */ |
c2d11a7d | 6034 | set_gdbarch_register_name (gdbarch, mips_register_name); |
6c997a34 | 6035 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d | 6036 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
0ba6dca9 | 6037 | set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ |
bcb0cc15 | 6038 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 6039 | |
102182a9 MS |
6040 | /* Add/remove bits from an address. The MIPS needs be careful to |
6041 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6042 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6043 | ||
10312cc4 | 6044 | /* There's a mess in stack frame creation. See comments in |
2ca6c561 AC |
6045 | blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */ |
6046 | set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
10312cc4 | 6047 | |
102182a9 | 6048 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6049 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
2f38ef89 KB |
6050 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
6051 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6052 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6053 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6054 | |
c2d11a7d | 6055 | /* Initialize a frame */ |
e0f7ec59 | 6056 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs); |
e9582e71 | 6057 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); |
c2d11a7d JM |
6058 | |
6059 | /* MIPS version of CALL_DUMMY */ | |
6060 | ||
9710e734 AC |
6061 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6062 | replaced by a command, and all targets will default to on stack | |
6063 | (regardless of the stack's execute status). */ | |
6064 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
749b82f6 | 6065 | set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); |
dc604539 | 6066 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
a59fe496 | 6067 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
781a750d AC |
6068 | set_gdbarch_deprecated_register_convertible (gdbarch, mips_register_convertible); |
6069 | set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, mips_register_convert_to_virtual); | |
6070 | set_gdbarch_deprecated_register_convert_to_raw (gdbarch, mips_register_convert_to_raw); | |
d05285fa | 6071 | |
618ce49f | 6072 | set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); |
b5d1566e MS |
6073 | set_gdbarch_frameless_function_invocation (gdbarch, |
6074 | generic_frameless_function_invocation_not); | |
8bedc050 | 6075 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); |
b5d1566e MS |
6076 | set_gdbarch_frame_args_skip (gdbarch, 0); |
6077 | ||
129c1cd6 | 6078 | set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 6079 | |
f7b9e9fc AC |
6080 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6081 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
6082 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
6083 | |
6084 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
6913c89a | 6085 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); |
f7b9e9fc | 6086 | |
fc0c74b1 AC |
6087 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6088 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6089 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6090 | |
102182a9 MS |
6091 | set_gdbarch_function_start_offset (gdbarch, 0); |
6092 | ||
a4b8ebc8 | 6093 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6094 | |
e11c53d2 | 6095 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 6096 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 6097 | |
e5ab0dce AC |
6098 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6099 | ||
3a3bc038 AC |
6100 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6101 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6102 | need to all be folded into the target vector. Since they are | |
6103 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6104 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6105 | is sitting on? */ | |
6106 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6107 | ||
70f80edf | 6108 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 6109 | gdbarch_init_osabi (info, gdbarch); |
70f80edf | 6110 | |
2f1488ce MS |
6111 | set_gdbarch_extract_struct_value_address (gdbarch, |
6112 | mips_extract_struct_value_address); | |
757a7cc6 MS |
6113 | |
6114 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); | |
6115 | ||
6116 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 6117 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 6118 | |
4b9b3959 AC |
6119 | return gdbarch; |
6120 | } | |
6121 | ||
2e4ebe70 DJ |
6122 | static void |
6123 | mips_abi_update (char *ignore_args, int from_tty, | |
6124 | struct cmd_list_element *c) | |
6125 | { | |
6126 | struct gdbarch_info info; | |
6127 | ||
6128 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6129 | mips_gdbarch_init will take care of the rest. */ | |
6130 | gdbarch_info_init (&info); | |
6131 | gdbarch_update_p (info); | |
6132 | } | |
6133 | ||
ad188201 KB |
6134 | /* Print out which MIPS ABI is in use. */ |
6135 | ||
6136 | static void | |
6137 | show_mips_abi (char *ignore_args, int from_tty) | |
6138 | { | |
6139 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6140 | printf_filtered ( | |
6141 | "The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
6142 | else | |
6143 | { | |
6144 | enum mips_abi global_abi = global_mips_abi (); | |
6145 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6146 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6147 | ||
6148 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6149 | printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6150 | actual_abi_str); | |
6151 | else if (global_abi == actual_abi) | |
6152 | printf_filtered ( | |
6153 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6154 | actual_abi_str); | |
6155 | else | |
6156 | { | |
6157 | /* Probably shouldn't happen... */ | |
6158 | printf_filtered ( | |
6159 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6160 | actual_abi_str, | |
6161 | mips_abi_strings[global_abi]); | |
6162 | } | |
6163 | } | |
6164 | } | |
6165 | ||
4b9b3959 AC |
6166 | static void |
6167 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6168 | { | |
6169 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6170 | if (tdep != NULL) | |
c2d11a7d | 6171 | { |
acdb74a0 AC |
6172 | int ef_mips_arch; |
6173 | int ef_mips_32bitmode; | |
6174 | /* determine the ISA */ | |
6175 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6176 | { | |
6177 | case E_MIPS_ARCH_1: | |
6178 | ef_mips_arch = 1; | |
6179 | break; | |
6180 | case E_MIPS_ARCH_2: | |
6181 | ef_mips_arch = 2; | |
6182 | break; | |
6183 | case E_MIPS_ARCH_3: | |
6184 | ef_mips_arch = 3; | |
6185 | break; | |
6186 | case E_MIPS_ARCH_4: | |
93d56215 | 6187 | ef_mips_arch = 4; |
acdb74a0 AC |
6188 | break; |
6189 | default: | |
93d56215 | 6190 | ef_mips_arch = 0; |
acdb74a0 AC |
6191 | break; |
6192 | } | |
6193 | /* determine the size of a pointer */ | |
6194 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6195 | fprintf_unfiltered (file, |
6196 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6197 | tdep->elf_flags); |
4b9b3959 | 6198 | fprintf_unfiltered (file, |
acdb74a0 AC |
6199 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6200 | ef_mips_32bitmode); | |
6201 | fprintf_unfiltered (file, | |
6202 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6203 | ef_mips_arch); | |
6204 | fprintf_unfiltered (file, | |
6205 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6206 | tdep->mips_abi, | |
2e4ebe70 | 6207 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6208 | fprintf_unfiltered (file, |
6209 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
6210 | mips_mask_address_p (), | |
6211 | tdep->default_mask_address_p); | |
c2d11a7d | 6212 | } |
4b9b3959 AC |
6213 | fprintf_unfiltered (file, |
6214 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6215 | FP_REGISTER_DOUBLE); | |
6216 | fprintf_unfiltered (file, | |
6217 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6218 | MIPS_DEFAULT_FPU_TYPE, | |
6219 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6220 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6221 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6222 | : "???")); | |
6223 | fprintf_unfiltered (file, | |
6224 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6225 | MIPS_EABI); | |
6226 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6227 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n", |
6228 | MIPS_LAST_FP_ARG_REGNUM, | |
6229 | MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1); | |
4b9b3959 AC |
6230 | fprintf_unfiltered (file, |
6231 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6232 | MIPS_FPU_TYPE, | |
6233 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6234 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6235 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6236 | : "???")); | |
6237 | fprintf_unfiltered (file, | |
6238 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
6239 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
6240 | fprintf_unfiltered (file, |
6241 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6242 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
6243 | fprintf_unfiltered (file, |
6244 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
6245 | MIPS_DEFAULT_STACK_ARGSIZE); | |
6246 | fprintf_unfiltered (file, | |
6247 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
6248 | MIPS_STACK_ARGSIZE); | |
6249 | fprintf_unfiltered (file, | |
6250 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
6251 | MIPS_REGSIZE); | |
2475bac3 AC |
6252 | fprintf_unfiltered (file, |
6253 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6254 | A0_REGNUM); | |
6255 | fprintf_unfiltered (file, | |
6256 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6257 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6258 | fprintf_unfiltered (file, | |
6259 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6260 | XSTRING (ATTACH_DETACH)); | |
6261 | fprintf_unfiltered (file, | |
6262 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
6263 | BADVADDR_REGNUM); | |
2475bac3 AC |
6264 | fprintf_unfiltered (file, |
6265 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
6266 | CAUSE_REGNUM); | |
2475bac3 AC |
6267 | fprintf_unfiltered (file, |
6268 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6269 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6270 | fprintf_unfiltered (file, | |
6271 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6272 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6273 | fprintf_unfiltered (file, |
6274 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
6275 | FCRCS_REGNUM); | |
6276 | fprintf_unfiltered (file, | |
6277 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
6278 | FCRIR_REGNUM); | |
6279 | fprintf_unfiltered (file, | |
6280 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6281 | FIRST_EMBED_REGNUM); | |
6282 | fprintf_unfiltered (file, | |
6283 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
6284 | FPA0_REGNUM); | |
6285 | fprintf_unfiltered (file, | |
6286 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
6287 | GDB_TARGET_IS_MIPS64); | |
2475bac3 AC |
6288 | fprintf_unfiltered (file, |
6289 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
6290 | HI_REGNUM); | |
2475bac3 AC |
6291 | fprintf_unfiltered (file, |
6292 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6293 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6294 | fprintf_unfiltered (file, |
6295 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6296 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6297 | fprintf_unfiltered (file, | |
6298 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6299 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6300 | fprintf_unfiltered (file, |
6301 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6302 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6303 | fprintf_unfiltered (file, |
6304 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
6305 | LO_REGNUM); | |
6306 | #ifdef MACHINE_CPROC_FP_OFFSET | |
6307 | fprintf_unfiltered (file, | |
6308 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6309 | MACHINE_CPROC_FP_OFFSET); | |
6310 | #endif | |
6311 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6312 | fprintf_unfiltered (file, | |
6313 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6314 | MACHINE_CPROC_PC_OFFSET); | |
6315 | #endif | |
6316 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6317 | fprintf_unfiltered (file, | |
6318 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6319 | MACHINE_CPROC_SP_OFFSET); | |
6320 | #endif | |
2475bac3 AC |
6321 | fprintf_unfiltered (file, |
6322 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6323 | MIPS16_INSTLEN); | |
2475bac3 AC |
6324 | fprintf_unfiltered (file, |
6325 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6326 | fprintf_unfiltered (file, | |
6327 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6328 | fprintf_unfiltered (file, | |
6329 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6330 | MIPS_INSTLEN); | |
6331 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6332 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6333 | MIPS_LAST_ARG_REGNUM, | |
6334 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6335 | fprintf_unfiltered (file, |
6336 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6337 | MIPS_NUMREGS); | |
6338 | fprintf_unfiltered (file, | |
6339 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
6340 | fprintf_unfiltered (file, | |
6341 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
6342 | MIPS_SAVED_REGSIZE); | |
2475bac3 AC |
6343 | fprintf_unfiltered (file, |
6344 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
6345 | fprintf_unfiltered (file, | |
6346 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
2475bac3 AC |
6347 | fprintf_unfiltered (file, |
6348 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6349 | PRID_REGNUM); | |
2475bac3 AC |
6350 | fprintf_unfiltered (file, |
6351 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6352 | fprintf_unfiltered (file, | |
6353 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6354 | fprintf_unfiltered (file, | |
6355 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6356 | fprintf_unfiltered (file, | |
6357 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6358 | fprintf_unfiltered (file, | |
6359 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6360 | fprintf_unfiltered (file, | |
6361 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6362 | fprintf_unfiltered (file, | |
6363 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6364 | fprintf_unfiltered (file, | |
6365 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6366 | fprintf_unfiltered (file, | |
6367 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6368 | fprintf_unfiltered (file, | |
6369 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6370 | fprintf_unfiltered (file, | |
6371 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6372 | fprintf_unfiltered (file, | |
6373 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6374 | fprintf_unfiltered (file, | |
6375 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6376 | PS_REGNUM); | |
2475bac3 AC |
6377 | fprintf_unfiltered (file, |
6378 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6379 | RA_REGNUM); | |
2475bac3 AC |
6380 | #ifdef SAVED_BYTES |
6381 | fprintf_unfiltered (file, | |
6382 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6383 | SAVED_BYTES); | |
6384 | #endif | |
6385 | #ifdef SAVED_FP | |
6386 | fprintf_unfiltered (file, | |
6387 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6388 | SAVED_FP); | |
6389 | #endif | |
6390 | #ifdef SAVED_PC | |
6391 | fprintf_unfiltered (file, | |
6392 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6393 | SAVED_PC); | |
6394 | #endif | |
6395 | fprintf_unfiltered (file, | |
6396 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6397 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6398 | fprintf_unfiltered (file, | |
6399 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6400 | fprintf_unfiltered (file, | |
6401 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6402 | SIGFRAME_BASE); | |
6403 | fprintf_unfiltered (file, | |
6404 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6405 | SIGFRAME_FPREGSAVE_OFF); | |
6406 | fprintf_unfiltered (file, | |
6407 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6408 | SIGFRAME_PC_OFF); | |
6409 | fprintf_unfiltered (file, | |
6410 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6411 | SIGFRAME_REGSAVE_OFF); | |
6412 | fprintf_unfiltered (file, | |
6413 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
6414 | SIGFRAME_REG_SIZE); | |
6415 | fprintf_unfiltered (file, | |
6416 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6417 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6418 | fprintf_unfiltered (file, | |
6419 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6420 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6421 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6422 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6423 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6424 | fprintf_unfiltered (file, |
6425 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6426 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6427 | #ifdef STACK_END_ADDR | |
6428 | fprintf_unfiltered (file, | |
6429 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6430 | STACK_END_ADDR); | |
6431 | #endif | |
6432 | fprintf_unfiltered (file, | |
6433 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6434 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6435 | fprintf_unfiltered (file, | |
6436 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6437 | STEP_SKIPS_DELAY_P); | |
6438 | fprintf_unfiltered (file, | |
6439 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6440 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6441 | fprintf_unfiltered (file, | |
6442 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6443 | T9_REGNUM); | |
6444 | fprintf_unfiltered (file, | |
6445 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6446 | fprintf_unfiltered (file, | |
6447 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6448 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6449 | fprintf_unfiltered (file, | |
6450 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6451 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6452 | #ifdef TRACE_CLEAR |
6453 | fprintf_unfiltered (file, | |
6454 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6455 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6456 | #endif | |
6457 | #ifdef TRACE_FLAVOR | |
6458 | fprintf_unfiltered (file, | |
6459 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6460 | TRACE_FLAVOR); | |
6461 | #endif | |
6462 | #ifdef TRACE_FLAVOR_SIZE | |
6463 | fprintf_unfiltered (file, | |
6464 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6465 | TRACE_FLAVOR_SIZE); | |
6466 | #endif | |
6467 | #ifdef TRACE_SET | |
6468 | fprintf_unfiltered (file, | |
6469 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6470 | XSTRING (TRACE_SET (X,STATE))); | |
6471 | #endif | |
2475bac3 AC |
6472 | #ifdef UNUSED_REGNUM |
6473 | fprintf_unfiltered (file, | |
6474 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6475 | UNUSED_REGNUM); | |
6476 | #endif | |
6477 | fprintf_unfiltered (file, | |
6478 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6479 | V0_REGNUM); | |
6480 | fprintf_unfiltered (file, | |
6481 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6482 | (long) VM_MIN_ADDRESS); | |
2475bac3 AC |
6483 | fprintf_unfiltered (file, |
6484 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6485 | ZERO_REGNUM); | |
6486 | fprintf_unfiltered (file, | |
6487 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6488 | _PROC_MAGIC_); | |
c2d11a7d JM |
6489 | } |
6490 | ||
a78f21af AC |
6491 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
6492 | ||
c906108c | 6493 | void |
acdb74a0 | 6494 | _initialize_mips_tdep (void) |
c906108c SS |
6495 | { |
6496 | static struct cmd_list_element *mipsfpulist = NULL; | |
6497 | struct cmd_list_element *c; | |
6498 | ||
2e4ebe70 DJ |
6499 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6500 | if (MIPS_ABI_LAST + 1 | |
6501 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6502 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6503 | ||
4b9b3959 | 6504 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6505 | |
a5ea2558 AC |
6506 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6507 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6508 | "Various MIPS specific commands.", | |
6509 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6510 | ||
6511 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6512 | "Various MIPS specific commands.", | |
6513 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6514 | ||
6515 | /* Allow the user to override the saved register size. */ | |
6516 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6517 | class_obscure, |
6518 | size_enums, | |
6519 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6520 | Set size of general purpose registers saved on the stack.\n\ |
6521 | This option can be set to one of:\n\ | |
6522 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6523 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6524 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6525 | saved GP register size from information contained in the executable.\n\ | |
6526 | (default: auto)", | |
1ed2a135 | 6527 | &setmipscmdlist), |
a5ea2558 AC |
6528 | &showmipscmdlist); |
6529 | ||
d929b26f AC |
6530 | /* Allow the user to override the argument stack size. */ |
6531 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6532 | class_obscure, | |
6533 | size_enums, | |
1ed2a135 | 6534 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6535 | Set the amount of stack space reserved for each argument.\n\ |
6536 | This option can be set to one of:\n\ | |
6537 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6538 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6539 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6540 | target and executable (default)", | |
6541 | &setmipscmdlist), | |
6542 | &showmipscmdlist); | |
6543 | ||
2e4ebe70 DJ |
6544 | /* Allow the user to override the ABI. */ |
6545 | c = add_set_enum_cmd | |
6546 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6547 | "Set the ABI used by this program.\n" | |
6548 | "This option can be set to one of:\n" | |
6549 | " auto - the default ABI associated with the current binary\n" | |
6550 | " o32\n" | |
6551 | " o64\n" | |
6552 | " n32\n" | |
f3a7b3a5 | 6553 | " n64\n" |
2e4ebe70 DJ |
6554 | " eabi32\n" |
6555 | " eabi64", | |
6556 | &setmipscmdlist); | |
2e4ebe70 | 6557 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 KB |
6558 | add_cmd ("abi", class_obscure, show_mips_abi, |
6559 | "Show ABI in use by MIPS target", &showmipscmdlist); | |
2e4ebe70 | 6560 | |
c906108c SS |
6561 | /* Let the user turn off floating point and set the fence post for |
6562 | heuristic_proc_start. */ | |
6563 | ||
6564 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6565 | "Set use of MIPS floating-point coprocessor.", | |
6566 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6567 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6568 | "Select single-precision MIPS floating-point coprocessor.", | |
6569 | &mipsfpulist); | |
6570 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6571 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6572 | &mipsfpulist); |
6573 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6574 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6575 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6576 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6577 | "Select no MIPS floating-point coprocessor.", | |
6578 | &mipsfpulist); | |
6579 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6580 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6581 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6582 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6583 | "Select MIPS floating-point coprocessor automatically.", | |
6584 | &mipsfpulist); | |
6585 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6586 | "Show current use of MIPS floating-point coprocessor target.", | |
6587 | &showlist); | |
6588 | ||
c906108c SS |
6589 | /* We really would like to have both "0" and "unlimited" work, but |
6590 | command.c doesn't deal with that. So make it a var_zinteger | |
6591 | because the user can always use "999999" or some such for unlimited. */ | |
6592 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6593 | (char *) &heuristic_fence_post, | |
6594 | "\ | |
6595 | Set the distance searched for the start of a function.\n\ | |
6596 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6597 | program for the start of a function. This command sets the distance of the\n\ | |
6598 | search. The only need to set it is when debugging a stripped executable.", | |
6599 | &setlist); | |
6600 | /* We need to throw away the frame cache when we set this, since it | |
6601 | might change our ability to get backtraces. */ | |
9f60d481 | 6602 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6603 | add_show_from_set (c, &showlist); |
6604 | ||
6605 | /* Allow the user to control whether the upper bits of 64-bit | |
6606 | addresses should be zeroed. */ | |
e9e68a56 AC |
6607 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6608 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6609 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6610 | allow GDB to determine the correct value.\n", "\ | |
6611 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6612 | NULL, show_mask_address, | |
6613 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6614 | |
6615 | /* Allow the user to control the size of 32 bit registers within the | |
6616 | raw remote packet. */ | |
6617 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
6618 | class_obscure, | |
6619 | var_boolean, | |
6620 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
6621 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
6622 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6623 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6624 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
6625 | &setlist), | |
6626 | &showlist); | |
9ace0497 AC |
6627 | |
6628 | /* Debug this files internals. */ | |
6629 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6630 | &mips_debug, "Set mips debugging.\n\ | |
6631 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6632 | &showdebuglist); | |
c906108c | 6633 | } |