Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
0fb0cc75 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
79a45b7d | 60 | #include "valprint.h" |
c906108c | 61 | |
8d5f9dcb DJ |
62 | static const struct objfile_data *mips_pdr_data; |
63 | ||
5bbcb741 | 64 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 65 | |
24e05951 | 66 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
67 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
68 | #define ST0_FR (1 << 26) | |
69 | ||
b0069a17 AC |
70 | /* The sizes of floating point registers. */ |
71 | ||
72 | enum | |
73 | { | |
74 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
75 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
76 | }; | |
77 | ||
1a69e1e4 DJ |
78 | enum |
79 | { | |
80 | MIPS32_REGSIZE = 4, | |
81 | MIPS64_REGSIZE = 8 | |
82 | }; | |
0dadbba0 | 83 | |
2e4ebe70 DJ |
84 | static const char *mips_abi_string; |
85 | ||
86 | static const char *mips_abi_strings[] = { | |
87 | "auto", | |
88 | "n32", | |
89 | "o32", | |
28d169de | 90 | "n64", |
2e4ebe70 DJ |
91 | "o64", |
92 | "eabi32", | |
93 | "eabi64", | |
94 | NULL | |
95 | }; | |
96 | ||
f8b73d13 DJ |
97 | /* The standard register names, and all the valid aliases for them. */ |
98 | struct register_alias | |
99 | { | |
100 | const char *name; | |
101 | int regnum; | |
102 | }; | |
103 | ||
104 | /* Aliases for o32 and most other ABIs. */ | |
105 | const struct register_alias mips_o32_aliases[] = { | |
106 | { "ta0", 12 }, | |
107 | { "ta1", 13 }, | |
108 | { "ta2", 14 }, | |
109 | { "ta3", 15 } | |
110 | }; | |
111 | ||
112 | /* Aliases for n32 and n64. */ | |
113 | const struct register_alias mips_n32_n64_aliases[] = { | |
114 | { "ta0", 8 }, | |
115 | { "ta1", 9 }, | |
116 | { "ta2", 10 }, | |
117 | { "ta3", 11 } | |
118 | }; | |
119 | ||
120 | /* Aliases for ABI-independent registers. */ | |
121 | const struct register_alias mips_register_aliases[] = { | |
122 | /* The architecture manuals specify these ABI-independent names for | |
123 | the GPRs. */ | |
124 | #define R(n) { "r" #n, n } | |
125 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
126 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
127 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
128 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
129 | #undef R | |
130 | ||
131 | /* k0 and k1 are sometimes called these instead (for "kernel | |
132 | temp"). */ | |
133 | { "kt0", 26 }, | |
134 | { "kt1", 27 }, | |
135 | ||
136 | /* This is the traditional GDB name for the CP0 status register. */ | |
137 | { "sr", MIPS_PS_REGNUM }, | |
138 | ||
139 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
140 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
141 | ||
142 | /* This is the traditional GDB name for the FCSR. */ | |
143 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
144 | }; | |
145 | ||
865093a3 AR |
146 | const struct register_alias mips_numeric_register_aliases[] = { |
147 | #define R(n) { #n, n } | |
148 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
149 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
150 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
151 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
152 | #undef R | |
153 | }; | |
154 | ||
c906108c SS |
155 | #ifndef MIPS_DEFAULT_FPU_TYPE |
156 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
157 | #endif | |
158 | static int mips_fpu_type_auto = 1; | |
159 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 160 | |
9ace0497 | 161 | static int mips_debug = 0; |
7a292a7a | 162 | |
29709017 DJ |
163 | /* Properties (for struct target_desc) describing the g/G packet |
164 | layout. */ | |
165 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
166 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
167 | ||
4eb0ad19 DJ |
168 | struct target_desc *mips_tdesc_gp32; |
169 | struct target_desc *mips_tdesc_gp64; | |
170 | ||
56cea623 AC |
171 | const struct mips_regnum * |
172 | mips_regnum (struct gdbarch *gdbarch) | |
173 | { | |
174 | return gdbarch_tdep (gdbarch)->regnum; | |
175 | } | |
176 | ||
177 | static int | |
178 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
179 | { | |
180 | return mips_regnum (gdbarch)->fp0 + 12; | |
181 | } | |
182 | ||
74ed0bb4 MD |
183 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
184 | == MIPS_ABI_EABI32 \ | |
185 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 186 | |
74ed0bb4 | 187 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 188 | |
74ed0bb4 | 189 | #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 190 | |
74ed0bb4 | 191 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 192 | |
95404a3e AC |
193 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
194 | functions to test, set, or clear bit 0 of addresses. */ | |
195 | ||
196 | static CORE_ADDR | |
197 | is_mips16_addr (CORE_ADDR addr) | |
198 | { | |
199 | return ((addr) & 1); | |
200 | } | |
201 | ||
95404a3e AC |
202 | static CORE_ADDR |
203 | unmake_mips16_addr (CORE_ADDR addr) | |
204 | { | |
5b652102 | 205 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
206 | } |
207 | ||
d1973055 KB |
208 | /* Return the MIPS ABI associated with GDBARCH. */ |
209 | enum mips_abi | |
210 | mips_abi (struct gdbarch *gdbarch) | |
211 | { | |
212 | return gdbarch_tdep (gdbarch)->mips_abi; | |
213 | } | |
214 | ||
4246e332 | 215 | int |
1b13c4f6 | 216 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 217 | { |
29709017 DJ |
218 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
219 | ||
220 | /* If we know how big the registers are, use that size. */ | |
221 | if (tdep->register_size_valid_p) | |
222 | return tdep->register_size; | |
223 | ||
224 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
225 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
226 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
227 | } | |
228 | ||
480d3dd2 AC |
229 | /* Return the currently configured (or set) saved register size. */ |
230 | ||
e6bc2e8a | 231 | unsigned int |
13326b4e | 232 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 233 | { |
1a69e1e4 DJ |
234 | switch (mips_abi (gdbarch)) |
235 | { | |
236 | case MIPS_ABI_EABI32: | |
237 | case MIPS_ABI_O32: | |
238 | return 4; | |
239 | case MIPS_ABI_N32: | |
240 | case MIPS_ABI_N64: | |
241 | case MIPS_ABI_O64: | |
242 | case MIPS_ABI_EABI64: | |
243 | return 8; | |
244 | case MIPS_ABI_UNKNOWN: | |
245 | case MIPS_ABI_LAST: | |
246 | default: | |
247 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
248 | } | |
d929b26f AC |
249 | } |
250 | ||
71b8ef93 | 251 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 252 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 253 | "info" field is used for this purpose. |
5a89d8aa | 254 | |
95f1da47 | 255 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
256 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
257 | minimal symbol to mark it as a 16-bit function | |
258 | ||
f594e5e9 | 259 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 260 | |
5a89d8aa | 261 | static void |
6d82d43b AC |
262 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
263 | { | |
264 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
265 | { | |
b887350f | 266 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b AC |
267 | SYMBOL_VALUE_ADDRESS (msym) |= 1; |
268 | } | |
5a89d8aa MS |
269 | } |
270 | ||
71b8ef93 MS |
271 | static int |
272 | msymbol_is_special (struct minimal_symbol *msym) | |
273 | { | |
b887350f | 274 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
275 | } |
276 | ||
88658117 AC |
277 | /* XFER a value from the big/little/left end of the register. |
278 | Depending on the size of the value it might occupy the entire | |
279 | register or just part of it. Make an allowance for this, aligning | |
280 | things accordingly. */ | |
281 | ||
282 | static void | |
ba32f989 DJ |
283 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
284 | int reg_num, int length, | |
870cd05e MK |
285 | enum bfd_endian endian, gdb_byte *in, |
286 | const gdb_byte *out, int buf_offset) | |
88658117 | 287 | { |
88658117 | 288 | int reg_offset = 0; |
72a155b4 UW |
289 | |
290 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
291 | /* Need to transfer the left or right part of the register, based on |
292 | the targets byte order. */ | |
88658117 AC |
293 | switch (endian) |
294 | { | |
295 | case BFD_ENDIAN_BIG: | |
72a155b4 | 296 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
297 | break; |
298 | case BFD_ENDIAN_LITTLE: | |
299 | reg_offset = 0; | |
300 | break; | |
6d82d43b | 301 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
302 | reg_offset = 0; |
303 | break; | |
304 | default: | |
e2e0b3e5 | 305 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
306 | } |
307 | if (mips_debug) | |
cb1d2653 AC |
308 | fprintf_unfiltered (gdb_stderr, |
309 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
310 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
311 | if (mips_debug && out != NULL) |
312 | { | |
313 | int i; | |
cb1d2653 | 314 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 315 | for (i = 0; i < length; i++) |
cb1d2653 | 316 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
317 | } |
318 | if (in != NULL) | |
6d82d43b AC |
319 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
320 | in + buf_offset); | |
88658117 | 321 | if (out != NULL) |
6d82d43b AC |
322 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
323 | out + buf_offset); | |
88658117 AC |
324 | if (mips_debug && in != NULL) |
325 | { | |
326 | int i; | |
cb1d2653 | 327 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 328 | for (i = 0; i < length; i++) |
cb1d2653 | 329 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
330 | } |
331 | if (mips_debug) | |
332 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
333 | } | |
334 | ||
dd824b04 DJ |
335 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
336 | compatiblity mode. A return value of 1 means that we have | |
337 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
338 | ||
339 | static int | |
9c9acae0 | 340 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 341 | { |
72a155b4 | 342 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
343 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
344 | meaningful. */ | |
72a155b4 | 345 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
346 | return 0; |
347 | ||
348 | #if 0 | |
349 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
350 | in all the places we deal with FP registers. PR gdb/413. */ | |
351 | /* Otherwise check the FR bit in the status register - it controls | |
352 | the FP compatiblity mode. If it is clear we are in compatibility | |
353 | mode. */ | |
9c9acae0 | 354 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
355 | return 1; |
356 | #endif | |
361d1df0 | 357 | |
dd824b04 DJ |
358 | return 0; |
359 | } | |
360 | ||
7a292a7a | 361 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 362 | |
74ed0bb4 | 363 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 364 | |
a14ed312 | 365 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 366 | |
acdb74a0 AC |
367 | /* The list of available "set mips " and "show mips " commands */ |
368 | ||
369 | static struct cmd_list_element *setmipscmdlist = NULL; | |
370 | static struct cmd_list_element *showmipscmdlist = NULL; | |
371 | ||
5e2e9765 KB |
372 | /* Integer registers 0 thru 31 are handled explicitly by |
373 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 374 | are listed in the following tables. */ |
691c0433 | 375 | |
6d82d43b AC |
376 | enum |
377 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
378 | |
379 | /* Generic MIPS. */ | |
380 | ||
381 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
382 | "sr", "lo", "hi", "bad", "cause", "pc", |
383 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
384 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
385 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
386 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
387 | "fsr", "fir", "" /*"fp" */ , "", | |
388 | "", "", "", "", "", "", "", "", | |
389 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
390 | }; |
391 | ||
392 | /* Names of IDT R3041 registers. */ | |
393 | ||
394 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
395 | "sr", "lo", "hi", "bad", "cause", "pc", |
396 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
397 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
398 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
399 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
400 | "fsr", "fir", "", /*"fp" */ "", | |
401 | "", "", "bus", "ccfg", "", "", "", "", | |
402 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
403 | }; |
404 | ||
405 | /* Names of tx39 registers. */ | |
406 | ||
407 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
408 | "sr", "lo", "hi", "bad", "cause", "pc", |
409 | "", "", "", "", "", "", "", "", | |
410 | "", "", "", "", "", "", "", "", | |
411 | "", "", "", "", "", "", "", "", | |
412 | "", "", "", "", "", "", "", "", | |
413 | "", "", "", "", | |
414 | "", "", "", "", "", "", "", "", | |
415 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
416 | }; |
417 | ||
418 | /* Names of IRIX registers. */ | |
419 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
420 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
421 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
422 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
423 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
424 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
425 | }; |
426 | ||
cce74817 | 427 | |
5e2e9765 | 428 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 429 | static const char * |
d93859e2 | 430 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 431 | { |
d93859e2 | 432 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
433 | /* GPR names for all ABIs other than n32/n64. */ |
434 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
435 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
436 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
437 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
438 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
439 | }; |
440 | ||
441 | /* GPR names for n32 and n64 ABIs. */ | |
442 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
443 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
444 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
445 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
446 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
447 | }; |
448 | ||
d93859e2 | 449 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 450 | |
f57d151a UW |
451 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
452 | but then don't make the raw register names visible. */ | |
d93859e2 UW |
453 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
454 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
455 | return ""; |
456 | ||
5e2e9765 KB |
457 | /* The MIPS integer registers are always mapped from 0 to 31. The |
458 | names of the registers (which reflects the conventions regarding | |
459 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 460 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
461 | { |
462 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 463 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 464 | else |
a4b8ebc8 | 465 | return mips_gpr_names[rawnum]; |
5e2e9765 | 466 | } |
d93859e2 UW |
467 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
468 | return tdesc_register_name (gdbarch, rawnum); | |
469 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
470 | { |
471 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
472 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
473 | } | |
5e2e9765 KB |
474 | else |
475 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 476 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 477 | } |
5e2e9765 | 478 | |
a4b8ebc8 | 479 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 480 | |
a4b8ebc8 AC |
481 | static int |
482 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
483 | struct reggroup *reggroup) | |
484 | { | |
485 | int vector_p; | |
486 | int float_p; | |
487 | int raw_p; | |
72a155b4 UW |
488 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
489 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
490 | if (reggroup == all_reggroup) |
491 | return pseudo; | |
492 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
493 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
494 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
495 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
496 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
497 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
498 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
499 | return 0; |
500 | if (reggroup == float_reggroup) | |
501 | return float_p && pseudo; | |
502 | if (reggroup == vector_reggroup) | |
503 | return vector_p && pseudo; | |
504 | if (reggroup == general_reggroup) | |
505 | return (!vector_p && !float_p) && pseudo; | |
506 | /* Save the pseudo registers. Need to make certain that any code | |
507 | extracting register values from a saved register cache also uses | |
508 | pseudo registers. */ | |
509 | if (reggroup == save_reggroup) | |
510 | return raw_p && pseudo; | |
511 | /* Restore the same pseudo register. */ | |
512 | if (reggroup == restore_reggroup) | |
513 | return raw_p && pseudo; | |
6d82d43b | 514 | return 0; |
a4b8ebc8 AC |
515 | } |
516 | ||
f8b73d13 DJ |
517 | /* Return the groups that a MIPS register can be categorised into. |
518 | This version is only used if we have a target description which | |
519 | describes real registers (and their groups). */ | |
520 | ||
521 | static int | |
522 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
523 | struct reggroup *reggroup) | |
524 | { | |
525 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
526 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
527 | int ret; | |
528 | ||
529 | /* Only save, restore, and display the pseudo registers. Need to | |
530 | make certain that any code extracting register values from a | |
531 | saved register cache also uses pseudo registers. | |
532 | ||
533 | Note: saving and restoring the pseudo registers is slightly | |
534 | strange; if we have 64 bits, we should save and restore all | |
535 | 64 bits. But this is hard and has little benefit. */ | |
536 | if (!pseudo) | |
537 | return 0; | |
538 | ||
539 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
540 | if (ret != -1) | |
541 | return ret; | |
542 | ||
543 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
544 | } | |
545 | ||
a4b8ebc8 | 546 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 547 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 548 | registers. Take care of alignment and size problems. */ |
c5aa993b | 549 | |
a4b8ebc8 AC |
550 | static void |
551 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 552 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 553 | { |
72a155b4 UW |
554 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
555 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
556 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 557 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 558 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
559 | else if (register_size (gdbarch, rawnum) > |
560 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
561 | { |
562 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 563 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
564 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
565 | else | |
566 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
567 | } | |
568 | else | |
e2e0b3e5 | 569 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
570 | } |
571 | ||
572 | static void | |
6d82d43b AC |
573 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
574 | struct regcache *regcache, int cookednum, | |
47a35522 | 575 | const gdb_byte *buf) |
a4b8ebc8 | 576 | { |
72a155b4 UW |
577 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
578 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
579 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 580 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 581 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
582 | else if (register_size (gdbarch, rawnum) > |
583 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
584 | { |
585 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 586 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
587 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
588 | else | |
589 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
590 | } | |
591 | else | |
e2e0b3e5 | 592 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 593 | } |
c5aa993b | 594 | |
c906108c | 595 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 596 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
597 | |
598 | /* Heuristic_proc_start may hunt through the text section for a long | |
599 | time across a 2400 baud serial line. Allows the user to limit this | |
600 | search. */ | |
601 | ||
602 | static unsigned int heuristic_fence_post = 0; | |
603 | ||
46cd78fb | 604 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
605 | register N. NOTE: This defines the pseudo register type so need to |
606 | rebuild the architecture vector. */ | |
43e526b9 JM |
607 | |
608 | static int mips64_transfers_32bit_regs_p = 0; | |
609 | ||
719ec221 AC |
610 | static void |
611 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
612 | struct cmd_list_element *c) | |
43e526b9 | 613 | { |
719ec221 AC |
614 | struct gdbarch_info info; |
615 | gdbarch_info_init (&info); | |
616 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
617 | instead of relying on globals. Doing that would let generic code | |
618 | handle the search for this specific architecture. */ | |
619 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 620 | { |
719ec221 | 621 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 622 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 623 | } |
a4b8ebc8 AC |
624 | } |
625 | ||
47ebcfbe | 626 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 627 | |
ff2e87ac | 628 | static int |
0abe36f5 | 629 | mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
ff2e87ac | 630 | { |
0abe36f5 MD |
631 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
632 | && register_size (gdbarch, regnum) == 4 | |
633 | && (regnum % gdbarch_num_regs (gdbarch)) | |
634 | >= mips_regnum (gdbarch)->fp0 | |
635 | && (regnum % gdbarch_num_regs (gdbarch)) | |
636 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 637 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
638 | } |
639 | ||
42c466d7 | 640 | static void |
ff2e87ac | 641 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 642 | struct type *type, gdb_byte *to) |
102182a9 | 643 | { |
47a35522 MK |
644 | get_frame_register (frame, regnum + 0, to + 4); |
645 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
646 | } |
647 | ||
42c466d7 | 648 | static void |
ff2e87ac | 649 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 650 | struct type *type, const gdb_byte *from) |
102182a9 | 651 | { |
47a35522 MK |
652 | put_frame_register (frame, regnum + 0, from + 4); |
653 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
654 | } |
655 | ||
a4b8ebc8 AC |
656 | /* Return the GDB type object for the "standard" data type of data in |
657 | register REG. */ | |
78fde5f8 KB |
658 | |
659 | static struct type * | |
a4b8ebc8 AC |
660 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
661 | { | |
72a155b4 UW |
662 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
663 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
664 | && (regnum % gdbarch_num_regs (gdbarch)) | |
665 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 666 | { |
5ef80fb0 | 667 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 668 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 669 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 670 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 671 | else |
27067745 | 672 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 673 | } |
72a155b4 | 674 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
675 | { |
676 | /* The raw or ISA registers. These are all sized according to | |
677 | the ISA regsize. */ | |
678 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 679 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 680 | else |
df4df182 | 681 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 682 | } |
78fde5f8 | 683 | else |
d5ac5a39 AC |
684 | { |
685 | /* The cooked or ABI registers. These are sized according to | |
686 | the ABI (with a few complications). */ | |
72a155b4 UW |
687 | if (regnum >= (gdbarch_num_regs (gdbarch) |
688 | + mips_regnum (gdbarch)->fp_control_status) | |
689 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
690 | /* The pseudo/cooked view of the embedded registers is always |
691 | 32-bit. The raw view is handled below. */ | |
df4df182 | 692 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
693 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
694 | /* The target, while possibly using a 64-bit register buffer, | |
695 | is only transfering 32-bits of each integer register. | |
696 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 697 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
698 | else if (mips_abi_regsize (gdbarch) == 4) |
699 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
700 | 32- or 64-bit). */ | |
df4df182 | 701 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
702 | else |
703 | /* 64-bit ABI. */ | |
df4df182 | 704 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 705 | } |
78fde5f8 KB |
706 | } |
707 | ||
f8b73d13 DJ |
708 | /* Return the GDB type for the pseudo register REGNUM, which is the |
709 | ABI-level view. This function is only called if there is a target | |
710 | description which includes registers, so we know precisely the | |
711 | types of hardware registers. */ | |
712 | ||
713 | static struct type * | |
714 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
715 | { | |
716 | const int num_regs = gdbarch_num_regs (gdbarch); | |
717 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
718 | int rawnum = regnum % num_regs; | |
719 | struct type *rawtype; | |
720 | ||
721 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
722 | ||
723 | /* Absent registers are still absent. */ | |
724 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
725 | if (TYPE_LENGTH (rawtype) == 0) | |
726 | return rawtype; | |
727 | ||
728 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
729 | /* Present the floating point registers however the hardware did; | |
730 | do not try to convert between FPU layouts. */ | |
731 | return rawtype; | |
732 | ||
733 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
734 | { | |
735 | /* The pseudo/cooked view of embedded registers is always | |
736 | 32-bit, even if the target transfers 64-bit values for them. | |
737 | New targets relying on XML descriptions should only transfer | |
738 | the necessary 32 bits, but older versions of GDB expected 64, | |
739 | so allow the target to provide 64 bits without interfering | |
740 | with the displayed type. */ | |
df4df182 | 741 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
742 | } |
743 | ||
744 | /* Use pointer types for registers if we can. For n32 we can not, | |
745 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
746 | if (mips_abi_regsize (gdbarch) |
747 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
748 | { |
749 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 750 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 751 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 752 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
753 | } |
754 | ||
755 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
756 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
df4df182 | 757 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
758 | |
759 | /* For all other registers, pass through the hardware type. */ | |
760 | return rawtype; | |
761 | } | |
bcb0cc15 | 762 | |
c906108c | 763 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 764 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
765 | |
766 | static int | |
480d3dd2 | 767 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
768 | { |
769 | switch (mask_address_var) | |
770 | { | |
7f19b9a2 | 771 | case AUTO_BOOLEAN_TRUE: |
4014092b | 772 | return 1; |
7f19b9a2 | 773 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
774 | return 0; |
775 | break; | |
7f19b9a2 | 776 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 777 | return tdep->default_mask_address_p; |
4014092b | 778 | default: |
e2e0b3e5 | 779 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 780 | return -1; |
361d1df0 | 781 | } |
4014092b AC |
782 | } |
783 | ||
784 | static void | |
08546159 AC |
785 | show_mask_address (struct ui_file *file, int from_tty, |
786 | struct cmd_list_element *c, const char *value) | |
4014092b | 787 | { |
1cf3db46 | 788 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
789 | |
790 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
791 | switch (mask_address_var) |
792 | { | |
7f19b9a2 | 793 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
794 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
795 | break; | |
7f19b9a2 | 796 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
797 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
798 | break; | |
7f19b9a2 | 799 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
800 | printf_filtered |
801 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
802 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
803 | break; |
804 | default: | |
e2e0b3e5 | 805 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 806 | break; |
361d1df0 | 807 | } |
4014092b | 808 | } |
c906108c | 809 | |
c906108c SS |
810 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
811 | ||
0fe7e7c8 AC |
812 | int |
813 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
814 | { |
815 | struct minimal_symbol *sym; | |
816 | ||
817 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 818 | if (is_mips16_addr (memaddr)) |
c906108c SS |
819 | return 1; |
820 | ||
821 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
822 | the high bit of the info field. Use this to decide if the function is | |
823 | MIPS16 or normal MIPS. */ | |
824 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
825 | if (sym) | |
71b8ef93 | 826 | return msymbol_is_special (sym); |
c906108c SS |
827 | else |
828 | return 0; | |
829 | } | |
830 | ||
b2fa5097 | 831 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
832 | all registers should be sign extended for simplicity? */ |
833 | ||
834 | static CORE_ADDR | |
61a1198a | 835 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 836 | { |
61a1198a UW |
837 | ULONGEST pc; |
838 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
839 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
840 | return pc; | |
b6cb9035 AC |
841 | } |
842 | ||
58dfe9ff AC |
843 | static CORE_ADDR |
844 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
845 | { | |
72a155b4 UW |
846 | return frame_unwind_register_signed |
847 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
848 | } |
849 | ||
30244cd8 UW |
850 | static CORE_ADDR |
851 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
852 | { | |
72a155b4 UW |
853 | return frame_unwind_register_signed |
854 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
855 | } |
856 | ||
b8a22b94 | 857 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
858 | dummy frame. The frame ID's base needs to match the TOS value |
859 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
860 | breakpoint. */ | |
861 | ||
862 | static struct frame_id | |
b8a22b94 | 863 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 864 | { |
f57d151a | 865 | return frame_id_build |
b8a22b94 DJ |
866 | (get_frame_register_signed (this_frame, |
867 | gdbarch_num_regs (gdbarch) | |
868 | + MIPS_SP_REGNUM), | |
869 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
870 | } |
871 | ||
b6cb9035 | 872 | static void |
61a1198a | 873 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 874 | { |
61a1198a UW |
875 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
876 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 877 | } |
c906108c | 878 | |
c906108c SS |
879 | /* Fetch and return instruction from the specified location. If the PC |
880 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
881 | ||
d37cca3d | 882 | static ULONGEST |
e17a4113 | 883 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 884 | { |
e17a4113 | 885 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 886 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
887 | int instlen; |
888 | int status; | |
889 | ||
0fe7e7c8 | 890 | if (mips_pc_is_mips16 (addr)) |
c906108c | 891 | { |
95ac2dcf | 892 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 893 | addr = unmake_mips16_addr (addr); |
c906108c SS |
894 | } |
895 | else | |
95ac2dcf | 896 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 897 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
898 | if (status) |
899 | memory_error (status, addr); | |
e17a4113 | 900 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
901 | } |
902 | ||
c906108c | 903 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
904 | #define mips32_op(x) (x >> 26) |
905 | #define itype_op(x) (x >> 26) | |
906 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 907 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 908 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 909 | |
e135b889 DJ |
910 | #define jtype_op(x) (x >> 26) |
911 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 912 | |
e135b889 DJ |
913 | #define rtype_op(x) (x >> 26) |
914 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
915 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
916 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
917 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
918 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 919 | |
06987e64 MK |
920 | static LONGEST |
921 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 922 | { |
06987e64 | 923 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
924 | } |
925 | ||
f49e4e6d MS |
926 | /* Determine where to set a single step breakpoint while considering |
927 | branch prediction. */ | |
5a89d8aa | 928 | static CORE_ADDR |
0b1b3e42 | 929 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 930 | { |
e17a4113 | 931 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
932 | unsigned long inst; |
933 | int op; | |
e17a4113 | 934 | inst = mips_fetch_instruction (gdbarch, pc); |
e135b889 | 935 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 936 | { |
e135b889 | 937 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 938 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 939 | { |
e135b889 | 940 | op = (itype_op (inst) & 0x03); |
c906108c SS |
941 | switch (op) |
942 | { | |
e135b889 DJ |
943 | case 0: /* BEQL */ |
944 | goto equal_branch; | |
945 | case 1: /* BNEL */ | |
946 | goto neq_branch; | |
947 | case 2: /* BLEZL */ | |
948 | goto less_branch; | |
313628cc | 949 | case 3: /* BGTZL */ |
e135b889 | 950 | goto greater_branch; |
c5aa993b JM |
951 | default: |
952 | pc += 4; | |
c906108c SS |
953 | } |
954 | } | |
e135b889 | 955 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 956 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
957 | { |
958 | int tf = itype_rt (inst) & 0x01; | |
959 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 960 | int fcrcs = |
72a155b4 UW |
961 | get_frame_register_signed (frame, |
962 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 963 | fp_control_status); |
e135b889 DJ |
964 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
965 | ||
966 | if (((cond >> cnum) & 0x01) == tf) | |
967 | pc += mips32_relative_offset (inst) + 4; | |
968 | else | |
969 | pc += 8; | |
970 | } | |
c5aa993b JM |
971 | else |
972 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
973 | } |
974 | else | |
c5aa993b JM |
975 | { /* This gets way messy */ |
976 | ||
c906108c | 977 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 978 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 979 | { |
c5aa993b JM |
980 | case 0: /* SPECIAL */ |
981 | op = rtype_funct (inst); | |
982 | switch (op) | |
983 | { | |
984 | case 8: /* JR */ | |
985 | case 9: /* JALR */ | |
6c997a34 | 986 | /* Set PC to that address */ |
0b1b3e42 | 987 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 988 | break; |
e38d4e1a DJ |
989 | case 12: /* SYSCALL */ |
990 | { | |
991 | struct gdbarch_tdep *tdep; | |
992 | ||
993 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
994 | if (tdep->syscall_next_pc != NULL) | |
995 | pc = tdep->syscall_next_pc (frame); | |
996 | else | |
997 | pc += 4; | |
998 | } | |
999 | break; | |
c5aa993b JM |
1000 | default: |
1001 | pc += 4; | |
1002 | } | |
1003 | ||
6d82d43b | 1004 | break; /* end SPECIAL */ |
c5aa993b | 1005 | case 1: /* REGIMM */ |
c906108c | 1006 | { |
e135b889 DJ |
1007 | op = itype_rt (inst); /* branch condition */ |
1008 | switch (op) | |
c906108c | 1009 | { |
c5aa993b | 1010 | case 0: /* BLTZ */ |
e135b889 DJ |
1011 | case 2: /* BLTZL */ |
1012 | case 16: /* BLTZAL */ | |
c5aa993b | 1013 | case 18: /* BLTZALL */ |
c906108c | 1014 | less_branch: |
0b1b3e42 | 1015 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1016 | pc += mips32_relative_offset (inst) + 4; |
1017 | else | |
1018 | pc += 8; /* after the delay slot */ | |
1019 | break; | |
e135b889 | 1020 | case 1: /* BGEZ */ |
c5aa993b JM |
1021 | case 3: /* BGEZL */ |
1022 | case 17: /* BGEZAL */ | |
1023 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1024 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1025 | pc += mips32_relative_offset (inst) + 4; |
1026 | else | |
1027 | pc += 8; /* after the delay slot */ | |
1028 | break; | |
e135b889 | 1029 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1030 | default: |
1031 | pc += 4; | |
c906108c SS |
1032 | } |
1033 | } | |
6d82d43b | 1034 | break; /* end REGIMM */ |
c5aa993b JM |
1035 | case 2: /* J */ |
1036 | case 3: /* JAL */ | |
1037 | { | |
1038 | unsigned long reg; | |
1039 | reg = jtype_target (inst) << 2; | |
e135b889 | 1040 | /* Upper four bits get never changed... */ |
5b652102 | 1041 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1042 | } |
c5aa993b JM |
1043 | break; |
1044 | /* FIXME case JALX : */ | |
1045 | { | |
1046 | unsigned long reg; | |
1047 | reg = jtype_target (inst) << 2; | |
5b652102 | 1048 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1049 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1050 | } | |
c5aa993b | 1051 | break; /* The new PC will be alternate mode */ |
e135b889 | 1052 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1053 | equal_branch: |
0b1b3e42 UW |
1054 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1055 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1056 | pc += mips32_relative_offset (inst) + 4; |
1057 | else | |
1058 | pc += 8; | |
1059 | break; | |
e135b889 | 1060 | case 5: /* BNE, BNEL */ |
c5aa993b | 1061 | neq_branch: |
0b1b3e42 UW |
1062 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1063 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1064 | pc += mips32_relative_offset (inst) + 4; |
1065 | else | |
1066 | pc += 8; | |
1067 | break; | |
e135b889 | 1068 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1069 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1070 | pc += mips32_relative_offset (inst) + 4; |
1071 | else | |
1072 | pc += 8; | |
1073 | break; | |
1074 | case 7: | |
e135b889 DJ |
1075 | default: |
1076 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1077 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1078 | pc += mips32_relative_offset (inst) + 4; |
1079 | else | |
1080 | pc += 8; | |
1081 | break; | |
c5aa993b JM |
1082 | } /* switch */ |
1083 | } /* else */ | |
1084 | return pc; | |
1085 | } /* mips32_next_pc */ | |
c906108c SS |
1086 | |
1087 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1088 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1089 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1090 | We dont want to set a single step instruction on the extend instruction | |
1091 | either. | |
c5aa993b | 1092 | */ |
c906108c SS |
1093 | |
1094 | /* Lots of mips16 instruction formats */ | |
1095 | /* Predicting jumps requires itype,ritype,i8type | |
1096 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1097 | */ |
c906108c SS |
1098 | enum mips16_inst_fmts |
1099 | { | |
c5aa993b JM |
1100 | itype, /* 0 immediate 5,10 */ |
1101 | ritype, /* 1 5,3,8 */ | |
1102 | rrtype, /* 2 5,3,3,5 */ | |
1103 | rritype, /* 3 5,3,3,5 */ | |
1104 | rrrtype, /* 4 5,3,3,3,2 */ | |
1105 | rriatype, /* 5 5,3,3,1,4 */ | |
1106 | shifttype, /* 6 5,3,3,3,2 */ | |
1107 | i8type, /* 7 5,3,8 */ | |
1108 | i8movtype, /* 8 5,3,3,5 */ | |
1109 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1110 | i64type, /* 10 5,3,8 */ | |
1111 | ri64type, /* 11 5,3,3,5 */ | |
1112 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1113 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1114 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1115 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1116 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1117 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1118 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1119 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1120 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1121 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1122 | }; | |
12f02c2a AC |
1123 | /* I am heaping all the fields of the formats into one structure and |
1124 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1125 | struct upk_mips16 |
6d82d43b AC |
1126 | { |
1127 | CORE_ADDR offset; | |
1128 | unsigned int regx; /* Function in i8 type */ | |
1129 | unsigned int regy; | |
1130 | }; | |
c906108c SS |
1131 | |
1132 | ||
12f02c2a | 1133 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1134 | for the bits which make up the immediate extension. */ |
c906108c | 1135 | |
12f02c2a AC |
1136 | static CORE_ADDR |
1137 | extended_offset (unsigned int extension) | |
c906108c | 1138 | { |
12f02c2a | 1139 | CORE_ADDR value; |
c5aa993b JM |
1140 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1141 | value = value << 6; | |
1142 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1143 | value = value << 5; | |
1144 | value |= extension & 0x01f; /* extract 4:0 */ | |
1145 | return value; | |
c906108c SS |
1146 | } |
1147 | ||
1148 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1149 | instruction. It won't malfunction, but why make excess remote memory |
1150 | references? If the immediate operands get sign extended or something, | |
1151 | do it after the extension is performed. */ | |
c906108c | 1152 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1153 | when the offset is to be used in relative addressing. */ |
c906108c | 1154 | |
12f02c2a | 1155 | static unsigned int |
e17a4113 | 1156 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1157 | { |
e17a4113 | 1158 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1159 | gdb_byte buf[8]; |
c5aa993b JM |
1160 | pc &= 0xfffffffe; /* clear the low order bit */ |
1161 | target_read_memory (pc, buf, 2); | |
e17a4113 | 1162 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1163 | } |
1164 | ||
1165 | static void | |
e17a4113 | 1166 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1167 | unsigned int extension, |
1168 | unsigned int inst, | |
6d82d43b | 1169 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1170 | { |
12f02c2a AC |
1171 | CORE_ADDR offset; |
1172 | int regx; | |
1173 | int regy; | |
1174 | switch (insn_format) | |
c906108c | 1175 | { |
c5aa993b | 1176 | case itype: |
c906108c | 1177 | { |
12f02c2a AC |
1178 | CORE_ADDR value; |
1179 | if (extension) | |
c5aa993b JM |
1180 | { |
1181 | value = extended_offset (extension); | |
1182 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1183 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1184 | } |
1185 | else | |
c5aa993b | 1186 | { |
12f02c2a | 1187 | value = inst & 0x7ff; |
c5aa993b | 1188 | /* FIXME : Consider sign extension */ |
c906108c | 1189 | } |
12f02c2a AC |
1190 | offset = value; |
1191 | regx = -1; | |
1192 | regy = -1; | |
c906108c | 1193 | } |
c5aa993b JM |
1194 | break; |
1195 | case ritype: | |
1196 | case i8type: | |
1197 | { /* A register identifier and an offset */ | |
c906108c SS |
1198 | /* Most of the fields are the same as I type but the |
1199 | immediate value is of a different length */ | |
12f02c2a AC |
1200 | CORE_ADDR value; |
1201 | if (extension) | |
c906108c | 1202 | { |
c5aa993b JM |
1203 | value = extended_offset (extension); |
1204 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1205 | value |= inst & 0xff; /* eleven bits from instruction */ |
1206 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1207 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1208 | { | |
1209 | value &= ~0x3fff; /* remove the sign bit */ | |
1210 | value = -value; | |
c906108c SS |
1211 | } |
1212 | } | |
c5aa993b JM |
1213 | else |
1214 | { | |
12f02c2a AC |
1215 | value = inst & 0xff; /* 8 bits */ |
1216 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1217 | /* FIXME: Do sign extension , this format needs it */ |
1218 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1219 | { | |
1220 | value &= 0xef; /* remove the sign bit */ | |
1221 | value = -value; | |
1222 | } | |
c5aa993b | 1223 | } |
12f02c2a AC |
1224 | offset = value; |
1225 | regy = -1; | |
c5aa993b | 1226 | break; |
c906108c | 1227 | } |
c5aa993b | 1228 | case jalxtype: |
c906108c | 1229 | { |
c5aa993b | 1230 | unsigned long value; |
12f02c2a AC |
1231 | unsigned int nexthalf; |
1232 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1233 | value = value << 16; |
e17a4113 | 1234 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit still set */ |
c5aa993b | 1235 | value |= nexthalf; |
12f02c2a AC |
1236 | offset = value; |
1237 | regx = -1; | |
1238 | regy = -1; | |
c5aa993b | 1239 | break; |
c906108c SS |
1240 | } |
1241 | default: | |
e2e0b3e5 | 1242 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1243 | } |
12f02c2a AC |
1244 | upk->offset = offset; |
1245 | upk->regx = regx; | |
1246 | upk->regy = regy; | |
c906108c SS |
1247 | } |
1248 | ||
1249 | ||
c5aa993b JM |
1250 | static CORE_ADDR |
1251 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1252 | { |
5b652102 | 1253 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1254 | } |
1255 | ||
12f02c2a | 1256 | static CORE_ADDR |
0b1b3e42 | 1257 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1258 | unsigned int extension, unsigned int insn) |
c906108c | 1259 | { |
e17a4113 | 1260 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1261 | int op = (insn >> 11); |
1262 | switch (op) | |
c906108c | 1263 | { |
6d82d43b | 1264 | case 2: /* Branch */ |
12f02c2a AC |
1265 | { |
1266 | CORE_ADDR offset; | |
1267 | struct upk_mips16 upk; | |
e17a4113 | 1268 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
12f02c2a AC |
1269 | offset = upk.offset; |
1270 | if (offset & 0x800) | |
1271 | { | |
1272 | offset &= 0xeff; | |
1273 | offset = -offset; | |
1274 | } | |
1275 | pc += (offset << 1) + 2; | |
1276 | break; | |
1277 | } | |
6d82d43b | 1278 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1279 | { |
1280 | struct upk_mips16 upk; | |
e17a4113 | 1281 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1282 | pc = add_offset_16 (pc, upk.offset); |
1283 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1284 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1285 | else | |
1286 | pc |= 0x01; | |
1287 | break; | |
1288 | } | |
6d82d43b | 1289 | case 4: /* beqz */ |
12f02c2a AC |
1290 | { |
1291 | struct upk_mips16 upk; | |
1292 | int reg; | |
e17a4113 | 1293 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1294 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1295 | if (reg == 0) |
1296 | pc += (upk.offset << 1) + 2; | |
1297 | else | |
1298 | pc += 2; | |
1299 | break; | |
1300 | } | |
6d82d43b | 1301 | case 5: /* bnez */ |
12f02c2a AC |
1302 | { |
1303 | struct upk_mips16 upk; | |
1304 | int reg; | |
e17a4113 | 1305 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1306 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1307 | if (reg != 0) |
1308 | pc += (upk.offset << 1) + 2; | |
1309 | else | |
1310 | pc += 2; | |
1311 | break; | |
1312 | } | |
6d82d43b | 1313 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1314 | { |
1315 | struct upk_mips16 upk; | |
1316 | int reg; | |
e17a4113 | 1317 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1318 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1319 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1320 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1321 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1322 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1323 | pc += (upk.offset << 1) + 2; | |
1324 | else | |
1325 | pc += 2; | |
1326 | break; | |
1327 | } | |
6d82d43b | 1328 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1329 | { |
1330 | struct upk_mips16 upk; | |
1331 | /* upk.fmt = rrtype; */ | |
1332 | op = insn & 0x1f; | |
1333 | if (op == 0) | |
c5aa993b | 1334 | { |
12f02c2a AC |
1335 | int reg; |
1336 | upk.regx = (insn >> 8) & 0x07; | |
1337 | upk.regy = (insn >> 5) & 0x07; | |
1338 | switch (upk.regy) | |
c5aa993b | 1339 | { |
12f02c2a AC |
1340 | case 0: |
1341 | reg = upk.regx; | |
1342 | break; | |
1343 | case 1: | |
1344 | reg = 31; | |
6d82d43b | 1345 | break; /* Function return instruction */ |
12f02c2a AC |
1346 | case 2: |
1347 | reg = upk.regx; | |
1348 | break; | |
1349 | default: | |
1350 | reg = 31; | |
6d82d43b | 1351 | break; /* BOGUS Guess */ |
c906108c | 1352 | } |
0b1b3e42 | 1353 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1354 | } |
12f02c2a | 1355 | else |
c5aa993b | 1356 | pc += 2; |
12f02c2a AC |
1357 | break; |
1358 | } | |
1359 | case 30: | |
1360 | /* This is an instruction extension. Fetch the real instruction | |
1361 | (which follows the extension) and decode things based on | |
1362 | that. */ | |
1363 | { | |
1364 | pc += 2; | |
e17a4113 UW |
1365 | pc = extended_mips16_next_pc (frame, pc, insn, |
1366 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1367 | break; |
1368 | } | |
1369 | default: | |
1370 | { | |
1371 | pc += 2; | |
1372 | break; | |
1373 | } | |
c906108c | 1374 | } |
c5aa993b | 1375 | return pc; |
12f02c2a | 1376 | } |
c906108c | 1377 | |
5a89d8aa | 1378 | static CORE_ADDR |
0b1b3e42 | 1379 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1380 | { |
e17a4113 UW |
1381 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1382 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1383 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1384 | } |
1385 | ||
1386 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1387 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1388 | It works by decoding the current instruction and predicting where a |
1389 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1390 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1391 | static CORE_ADDR |
0b1b3e42 | 1392 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1393 | { |
ce1f96de | 1394 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1395 | return mips16_next_pc (frame, pc); |
c5aa993b | 1396 | else |
0b1b3e42 | 1397 | return mips32_next_pc (frame, pc); |
12f02c2a | 1398 | } |
c906108c | 1399 | |
edfae063 AC |
1400 | struct mips_frame_cache |
1401 | { | |
1402 | CORE_ADDR base; | |
1403 | struct trad_frame_saved_reg *saved_regs; | |
1404 | }; | |
1405 | ||
29639122 JB |
1406 | /* Set a register's saved stack address in temp_saved_regs. If an |
1407 | address has already been set for this register, do nothing; this | |
1408 | way we will only recognize the first save of a given register in a | |
1409 | function prologue. | |
eec63939 | 1410 | |
f57d151a UW |
1411 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1412 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1413 | Strictly speaking, only the second range is used as it is only second | |
1414 | range (the ABI instead of ISA registers) that comes into play when finding | |
1415 | saved registers in a frame. */ | |
eec63939 AC |
1416 | |
1417 | static void | |
74ed0bb4 MD |
1418 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1419 | int regnum, CORE_ADDR offset) | |
eec63939 | 1420 | { |
29639122 JB |
1421 | if (this_cache != NULL |
1422 | && this_cache->saved_regs[regnum].addr == -1) | |
1423 | { | |
74ed0bb4 MD |
1424 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1425 | = offset; | |
1426 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1427 | = offset; | |
29639122 | 1428 | } |
eec63939 AC |
1429 | } |
1430 | ||
eec63939 | 1431 | |
29639122 JB |
1432 | /* Fetch the immediate value from a MIPS16 instruction. |
1433 | If the previous instruction was an EXTEND, use it to extend | |
1434 | the upper bits of the immediate value. This is a helper function | |
1435 | for mips16_scan_prologue. */ | |
eec63939 | 1436 | |
29639122 JB |
1437 | static int |
1438 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1439 | unsigned short inst, /* current instruction */ | |
1440 | int nbits, /* number of bits in imm field */ | |
1441 | int scale, /* scale factor to be applied to imm */ | |
1442 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1443 | { |
29639122 | 1444 | int offset; |
eec63939 | 1445 | |
29639122 JB |
1446 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1447 | { | |
1448 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1449 | if (offset & 0x8000) /* check for negative extend */ | |
1450 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1451 | return offset | (inst & 0x1f); | |
1452 | } | |
eec63939 | 1453 | else |
29639122 JB |
1454 | { |
1455 | int max_imm = 1 << nbits; | |
1456 | int mask = max_imm - 1; | |
1457 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1458 | |
29639122 JB |
1459 | offset = inst & mask; |
1460 | if (is_signed && (offset & sign_bit)) | |
1461 | offset = 0 - (max_imm - offset); | |
1462 | return offset * scale; | |
1463 | } | |
1464 | } | |
eec63939 | 1465 | |
65596487 | 1466 | |
29639122 JB |
1467 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1468 | the associated FRAME_CACHE if not null. | |
1469 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1470 | |
29639122 | 1471 | static CORE_ADDR |
e17a4113 UW |
1472 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1473 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1474 | struct frame_info *this_frame, |
29639122 JB |
1475 | struct mips_frame_cache *this_cache) |
1476 | { | |
1477 | CORE_ADDR cur_pc; | |
1478 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1479 | CORE_ADDR sp; | |
1480 | long frame_offset = 0; /* Size of stack frame. */ | |
1481 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1482 | int frame_reg = MIPS_SP_REGNUM; | |
1483 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1484 | unsigned inst = 0; /* current instruction */ | |
1485 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1486 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1487 | int reg, offset; |
a343eb3c | 1488 | |
29639122 JB |
1489 | int extend_bytes = 0; |
1490 | int prev_extend_bytes; | |
1491 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1492 | |
29639122 | 1493 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1494 | THIS_FRAME. */ |
1495 | if (this_frame != NULL) | |
1496 | sp = get_frame_register_signed (this_frame, | |
1497 | gdbarch_num_regs (gdbarch) | |
1498 | + MIPS_SP_REGNUM); | |
29639122 JB |
1499 | else |
1500 | sp = 0; | |
eec63939 | 1501 | |
29639122 JB |
1502 | if (limit_pc > start_pc + 200) |
1503 | limit_pc = start_pc + 200; | |
eec63939 | 1504 | |
95ac2dcf | 1505 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1506 | { |
1507 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1508 | the immediate offset extension from it in mips16_get_imm. */ | |
1509 | prev_inst = inst; | |
eec63939 | 1510 | |
29639122 | 1511 | /* Fetch and decode the instruction. */ |
e17a4113 | 1512 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1513 | |
29639122 JB |
1514 | /* Normally we ignore extend instructions. However, if it is |
1515 | not followed by a valid prologue instruction, then this | |
1516 | instruction is not part of the prologue either. We must | |
1517 | remember in this case to adjust the end_prologue_addr back | |
1518 | over the extend. */ | |
1519 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1520 | { | |
95ac2dcf | 1521 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1522 | continue; |
1523 | } | |
eec63939 | 1524 | |
29639122 JB |
1525 | prev_extend_bytes = extend_bytes; |
1526 | extend_bytes = 0; | |
eec63939 | 1527 | |
29639122 JB |
1528 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1529 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1530 | { | |
1531 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1532 | if (offset < 0) /* negative stack adjustment? */ | |
1533 | frame_offset -= offset; | |
1534 | else | |
1535 | /* Exit loop if a positive stack adjustment is found, which | |
1536 | usually means that the stack cleanup code in the function | |
1537 | epilogue is reached. */ | |
1538 | break; | |
1539 | } | |
1540 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1541 | { | |
1542 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1543 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1544 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1545 | } |
1546 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1547 | { | |
1548 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1549 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1550 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1551 | } |
1552 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1553 | { | |
1554 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1555 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1556 | } |
1557 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1558 | { | |
1559 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1560 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1561 | } |
1562 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1563 | { | |
1564 | frame_addr = sp; | |
1565 | frame_reg = 17; | |
1566 | } | |
1567 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1568 | { | |
1569 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1570 | frame_addr = sp + offset; | |
1571 | frame_reg = 17; | |
1572 | frame_adjust = offset; | |
1573 | } | |
1574 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1575 | { | |
1576 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1577 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1578 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1579 | } |
1580 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1581 | { | |
1582 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1583 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1584 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1585 | } |
1586 | else if ((inst & 0xf81f) == 0xe809 | |
1587 | && (inst & 0x700) != 0x700) /* entry */ | |
1588 | entry_inst = inst; /* save for later processing */ | |
2207132d MR |
1589 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1590 | { | |
1591 | save_inst = inst; /* save for later processing */ | |
1592 | if (prev_extend_bytes) /* extend */ | |
1593 | save_inst |= prev_inst << 16; | |
1594 | } | |
29639122 | 1595 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1596 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1597 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1598 | { | |
1599 | /* This instruction is part of the prologue, but we don't | |
1600 | need to do anything special to handle it. */ | |
1601 | } | |
1602 | else | |
1603 | { | |
1604 | /* This instruction is not an instruction typically found | |
1605 | in a prologue, so we must have reached the end of the | |
1606 | prologue. */ | |
1607 | if (end_prologue_addr == 0) | |
1608 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1609 | } | |
1610 | } | |
eec63939 | 1611 | |
29639122 JB |
1612 | /* The entry instruction is typically the first instruction in a function, |
1613 | and it stores registers at offsets relative to the value of the old SP | |
1614 | (before the prologue). But the value of the sp parameter to this | |
1615 | function is the new SP (after the prologue has been executed). So we | |
1616 | can't calculate those offsets until we've seen the entire prologue, | |
1617 | and can calculate what the old SP must have been. */ | |
1618 | if (entry_inst != 0) | |
1619 | { | |
1620 | int areg_count = (entry_inst >> 8) & 7; | |
1621 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1622 | |
29639122 JB |
1623 | /* The entry instruction always subtracts 32 from the SP. */ |
1624 | frame_offset += 32; | |
1625 | ||
1626 | /* Now we can calculate what the SP must have been at the | |
1627 | start of the function prologue. */ | |
1628 | sp += frame_offset; | |
1629 | ||
1630 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1631 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1632 | { | |
74ed0bb4 | 1633 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1634 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1635 | } |
1636 | ||
1637 | /* Check if the ra register was pushed on the stack. */ | |
1638 | offset = -4; | |
1639 | if (entry_inst & 0x20) | |
1640 | { | |
74ed0bb4 | 1641 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1642 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1643 | } |
1644 | ||
1645 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1646 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1647 | { | |
74ed0bb4 | 1648 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1649 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1650 | } |
1651 | } | |
1652 | ||
2207132d MR |
1653 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1654 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1655 | size of the frame is specified as an immediate field of instruction | |
1656 | and an extended variation exists which lets additional registers and | |
1657 | frame space to be specified. The instruction always treats registers | |
1658 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1659 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1660 | { | |
1661 | static int args_table[16] = { | |
1662 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1663 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1664 | }; | |
1665 | static int astatic_table[16] = { | |
1666 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1667 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1668 | }; | |
1669 | int aregs = (save_inst >> 16) & 0xf; | |
1670 | int xsregs = (save_inst >> 24) & 0x7; | |
1671 | int args = args_table[aregs]; | |
1672 | int astatic = astatic_table[aregs]; | |
1673 | long frame_size; | |
1674 | ||
1675 | if (args < 0) | |
1676 | { | |
1677 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1678 | args = 0; | |
1679 | } | |
1680 | if (astatic < 0) | |
1681 | { | |
1682 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1683 | astatic = 0; | |
1684 | } | |
1685 | ||
1686 | /* For standard SAVE the frame size of 0 means 128. */ | |
1687 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1688 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1689 | frame_size = 16; | |
1690 | frame_size *= 8; | |
1691 | frame_offset += frame_size; | |
1692 | ||
1693 | /* Now we can calculate what the SP must have been at the | |
1694 | start of the function prologue. */ | |
1695 | sp += frame_offset; | |
1696 | ||
1697 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1698 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1699 | { | |
74ed0bb4 | 1700 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1701 | offset += mips_abi_regsize (gdbarch); |
1702 | } | |
1703 | ||
1704 | offset = -4; | |
1705 | ||
1706 | /* Check if the RA register was pushed on the stack. */ | |
1707 | if (save_inst & 0x40) | |
1708 | { | |
74ed0bb4 | 1709 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1710 | offset -= mips_abi_regsize (gdbarch); |
1711 | } | |
1712 | ||
1713 | /* Check if the S8 register was pushed on the stack. */ | |
1714 | if (xsregs > 6) | |
1715 | { | |
74ed0bb4 | 1716 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1717 | offset -= mips_abi_regsize (gdbarch); |
1718 | xsregs--; | |
1719 | } | |
1720 | /* Check if S2-S7 were pushed on the stack. */ | |
1721 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1722 | { | |
74ed0bb4 | 1723 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1724 | offset -= mips_abi_regsize (gdbarch); |
1725 | } | |
1726 | ||
1727 | /* Check if the S1 register was pushed on the stack. */ | |
1728 | if (save_inst & 0x10) | |
1729 | { | |
74ed0bb4 | 1730 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1731 | offset -= mips_abi_regsize (gdbarch); |
1732 | } | |
1733 | /* Check if the S0 register was pushed on the stack. */ | |
1734 | if (save_inst & 0x20) | |
1735 | { | |
74ed0bb4 | 1736 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1737 | offset -= mips_abi_regsize (gdbarch); |
1738 | } | |
1739 | ||
1740 | /* Check if A0-A3 were pushed on the stack. */ | |
1741 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1742 | { | |
74ed0bb4 | 1743 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1744 | offset -= mips_abi_regsize (gdbarch); |
1745 | } | |
1746 | } | |
1747 | ||
29639122 JB |
1748 | if (this_cache != NULL) |
1749 | { | |
1750 | this_cache->base = | |
b8a22b94 DJ |
1751 | (get_frame_register_signed (this_frame, |
1752 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1753 | + frame_offset - frame_adjust); |
1754 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1755 | be able to get rid of the assignment below, evetually. But it's | |
1756 | still needed for now. */ | |
72a155b4 UW |
1757 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1758 | + mips_regnum (gdbarch)->pc] | |
1759 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1760 | } |
1761 | ||
1762 | /* If we didn't reach the end of the prologue when scanning the function | |
1763 | instructions, then set end_prologue_addr to the address of the | |
1764 | instruction immediately after the last one we scanned. */ | |
1765 | if (end_prologue_addr == 0) | |
1766 | end_prologue_addr = cur_pc; | |
1767 | ||
1768 | return end_prologue_addr; | |
eec63939 AC |
1769 | } |
1770 | ||
29639122 JB |
1771 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1772 | Procedures that use the 32-bit instruction set are handled by the | |
1773 | mips_insn32 unwinder. */ | |
1774 | ||
1775 | static struct mips_frame_cache * | |
b8a22b94 | 1776 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1777 | { |
e17a4113 | 1778 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 1779 | struct mips_frame_cache *cache; |
eec63939 AC |
1780 | |
1781 | if ((*this_cache) != NULL) | |
1782 | return (*this_cache); | |
29639122 JB |
1783 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1784 | (*this_cache) = cache; | |
b8a22b94 | 1785 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1786 | |
29639122 JB |
1787 | /* Analyze the function prologue. */ |
1788 | { | |
b8a22b94 | 1789 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1790 | CORE_ADDR start_addr; |
eec63939 | 1791 | |
29639122 JB |
1792 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1793 | if (start_addr == 0) | |
e17a4113 | 1794 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
1795 | /* We can't analyze the prologue if we couldn't find the begining |
1796 | of the function. */ | |
1797 | if (start_addr == 0) | |
1798 | return cache; | |
eec63939 | 1799 | |
e17a4113 | 1800 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1801 | } |
1802 | ||
3e8c568d | 1803 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1804 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 1805 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 1806 | cache->base); |
eec63939 | 1807 | |
29639122 | 1808 | return (*this_cache); |
eec63939 AC |
1809 | } |
1810 | ||
1811 | static void | |
b8a22b94 | 1812 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 1813 | struct frame_id *this_id) |
eec63939 | 1814 | { |
b8a22b94 | 1815 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1816 | this_cache); |
b8a22b94 | 1817 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
1818 | } |
1819 | ||
b8a22b94 DJ |
1820 | static struct value * |
1821 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
1822 | void **this_cache, int regnum) | |
eec63939 | 1823 | { |
b8a22b94 | 1824 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1825 | this_cache); |
b8a22b94 DJ |
1826 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1827 | } | |
1828 | ||
1829 | static int | |
1830 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
1831 | struct frame_info *this_frame, void **this_cache) | |
1832 | { | |
1833 | CORE_ADDR pc = get_frame_pc (this_frame); | |
1834 | if (mips_pc_is_mips16 (pc)) | |
1835 | return 1; | |
1836 | return 0; | |
eec63939 AC |
1837 | } |
1838 | ||
29639122 | 1839 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1840 | { |
1841 | NORMAL_FRAME, | |
29639122 | 1842 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
1843 | mips_insn16_frame_prev_register, |
1844 | NULL, | |
1845 | mips_insn16_frame_sniffer | |
eec63939 AC |
1846 | }; |
1847 | ||
eec63939 | 1848 | static CORE_ADDR |
b8a22b94 | 1849 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 1850 | void **this_cache) |
eec63939 | 1851 | { |
b8a22b94 | 1852 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
1853 | this_cache); |
1854 | return info->base; | |
eec63939 AC |
1855 | } |
1856 | ||
29639122 | 1857 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1858 | { |
29639122 JB |
1859 | &mips_insn16_frame_unwind, |
1860 | mips_insn16_frame_base_address, | |
1861 | mips_insn16_frame_base_address, | |
1862 | mips_insn16_frame_base_address | |
eec63939 AC |
1863 | }; |
1864 | ||
1865 | static const struct frame_base * | |
b8a22b94 | 1866 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 1867 | { |
b8a22b94 DJ |
1868 | CORE_ADDR pc = get_frame_pc (this_frame); |
1869 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 1870 | return &mips_insn16_frame_base; |
eec63939 AC |
1871 | else |
1872 | return NULL; | |
edfae063 AC |
1873 | } |
1874 | ||
29639122 JB |
1875 | /* Mark all the registers as unset in the saved_regs array |
1876 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1877 | ||
74ed0bb4 MD |
1878 | static void |
1879 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 1880 | { |
29639122 JB |
1881 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1882 | return; | |
1883 | ||
1884 | { | |
74ed0bb4 | 1885 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 1886 | int i; |
64159455 | 1887 | |
29639122 JB |
1888 | for (i = 0; i < num_regs; i++) |
1889 | { | |
1890 | this_cache->saved_regs[i].addr = -1; | |
1891 | } | |
1892 | } | |
c906108c SS |
1893 | } |
1894 | ||
29639122 JB |
1895 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1896 | the associated FRAME_CACHE if not null. | |
1897 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1898 | |
875e1767 | 1899 | static CORE_ADDR |
e17a4113 UW |
1900 | mips32_scan_prologue (struct gdbarch *gdbarch, |
1901 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1902 | struct frame_info *this_frame, |
29639122 | 1903 | struct mips_frame_cache *this_cache) |
c906108c | 1904 | { |
29639122 JB |
1905 | CORE_ADDR cur_pc; |
1906 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1907 | CORE_ADDR sp; | |
1908 | long frame_offset; | |
1909 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1910 | |
29639122 JB |
1911 | CORE_ADDR end_prologue_addr = 0; |
1912 | int seen_sp_adjust = 0; | |
1913 | int load_immediate_bytes = 0; | |
db5f024e | 1914 | int in_delay_slot = 0; |
7d1e6fb8 | 1915 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 1916 | |
29639122 | 1917 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1918 | THIS_FRAME. */ |
1919 | if (this_frame != NULL) | |
1920 | sp = get_frame_register_signed (this_frame, | |
1921 | gdbarch_num_regs (gdbarch) | |
1922 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1923 | else |
29639122 | 1924 | sp = 0; |
9022177c | 1925 | |
29639122 JB |
1926 | if (limit_pc > start_pc + 200) |
1927 | limit_pc = start_pc + 200; | |
9022177c | 1928 | |
29639122 | 1929 | restart: |
9022177c | 1930 | |
29639122 | 1931 | frame_offset = 0; |
95ac2dcf | 1932 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1933 | { |
29639122 JB |
1934 | unsigned long inst, high_word, low_word; |
1935 | int reg; | |
9022177c | 1936 | |
29639122 | 1937 | /* Fetch the instruction. */ |
e17a4113 | 1938 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 1939 | |
29639122 JB |
1940 | /* Save some code by pre-extracting some useful fields. */ |
1941 | high_word = (inst >> 16) & 0xffff; | |
1942 | low_word = inst & 0xffff; | |
1943 | reg = high_word & 0x1f; | |
fe29b929 | 1944 | |
29639122 JB |
1945 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1946 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1947 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1948 | { | |
1949 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1950 | frame_offset += 0x10000 - low_word; | |
1951 | else | |
1952 | /* Exit loop if a positive stack adjustment is found, which | |
1953 | usually means that the stack cleanup code in the function | |
1954 | epilogue is reached. */ | |
1955 | break; | |
1956 | seen_sp_adjust = 1; | |
1957 | } | |
7d1e6fb8 KB |
1958 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
1959 | && !regsize_is_64_bits) | |
29639122 | 1960 | { |
74ed0bb4 | 1961 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 1962 | } |
7d1e6fb8 KB |
1963 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
1964 | && regsize_is_64_bits) | |
29639122 JB |
1965 | { |
1966 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 1967 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
1968 | } |
1969 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1970 | { | |
1971 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1972 | if ((long) low_word != frame_offset) | |
1973 | frame_addr = sp + low_word; | |
b8a22b94 | 1974 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1975 | { |
1976 | unsigned alloca_adjust; | |
a4b8ebc8 | 1977 | |
29639122 | 1978 | frame_reg = 30; |
b8a22b94 DJ |
1979 | frame_addr = get_frame_register_signed |
1980 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 1981 | |
29639122 JB |
1982 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1983 | if (alloca_adjust > 0) | |
1984 | { | |
1985 | /* FP > SP + frame_size. This may be because of | |
1986 | an alloca or somethings similar. Fix sp to | |
1987 | "pre-alloca" value, and try again. */ | |
1988 | sp += alloca_adjust; | |
1989 | /* Need to reset the status of all registers. Otherwise, | |
1990 | we will hit a guard that prevents the new address | |
1991 | for each register to be recomputed during the second | |
1992 | pass. */ | |
74ed0bb4 | 1993 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
1994 | goto restart; |
1995 | } | |
1996 | } | |
1997 | } | |
1998 | /* move $30,$sp. With different versions of gas this will be either | |
1999 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2000 | Accept any one of these. */ | |
2001 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2002 | { | |
2003 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2004 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2005 | { |
2006 | unsigned alloca_adjust; | |
c906108c | 2007 | |
29639122 | 2008 | frame_reg = 30; |
b8a22b94 DJ |
2009 | frame_addr = get_frame_register_signed |
2010 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2011 | |
29639122 JB |
2012 | alloca_adjust = (unsigned) (frame_addr - sp); |
2013 | if (alloca_adjust > 0) | |
2014 | { | |
2015 | /* FP > SP + frame_size. This may be because of | |
2016 | an alloca or somethings similar. Fix sp to | |
2017 | "pre-alloca" value, and try again. */ | |
2018 | sp = frame_addr; | |
2019 | /* Need to reset the status of all registers. Otherwise, | |
2020 | we will hit a guard that prevents the new address | |
2021 | for each register to be recomputed during the second | |
2022 | pass. */ | |
74ed0bb4 | 2023 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2024 | goto restart; |
2025 | } | |
2026 | } | |
2027 | } | |
7d1e6fb8 KB |
2028 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2029 | && !regsize_is_64_bits) | |
29639122 | 2030 | { |
74ed0bb4 | 2031 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2032 | } |
2033 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2034 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2035 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2036 | || high_word == 0x3c1c /* lui $gp,n */ | |
2037 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2038 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2039 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2040 | ) | |
2041 | { | |
2042 | /* These instructions are part of the prologue, but we don't | |
2043 | need to do anything special to handle them. */ | |
2044 | } | |
2045 | /* The instructions below load $at or $t0 with an immediate | |
2046 | value in preparation for a stack adjustment via | |
2047 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2048 | initialize a local variable, so we accept them only before | |
2049 | a stack adjustment instruction was seen. */ | |
2050 | else if (!seen_sp_adjust | |
2051 | && (high_word == 0x3c01 /* lui $at,n */ | |
2052 | || high_word == 0x3c08 /* lui $t0,n */ | |
2053 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2054 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2055 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2056 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2057 | )) | |
2058 | { | |
95ac2dcf | 2059 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2060 | } |
2061 | else | |
2062 | { | |
2063 | /* This instruction is not an instruction typically found | |
2064 | in a prologue, so we must have reached the end of the | |
2065 | prologue. */ | |
2066 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2067 | loop now? Why would we need to continue scanning the function | |
2068 | instructions? */ | |
2069 | if (end_prologue_addr == 0) | |
2070 | end_prologue_addr = cur_pc; | |
db5f024e DJ |
2071 | |
2072 | /* Check for branches and jumps. For now, only jump to | |
2073 | register are caught (i.e. returns). */ | |
2074 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2075 | in_delay_slot = 1; | |
29639122 | 2076 | } |
db5f024e DJ |
2077 | |
2078 | /* If the previous instruction was a jump, we must have reached | |
2079 | the end of the prologue by now. Stop scanning so that we do | |
2080 | not go past the function return. */ | |
2081 | if (in_delay_slot) | |
2082 | break; | |
a4b8ebc8 | 2083 | } |
c906108c | 2084 | |
29639122 JB |
2085 | if (this_cache != NULL) |
2086 | { | |
2087 | this_cache->base = | |
b8a22b94 DJ |
2088 | (get_frame_register_signed (this_frame, |
2089 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2090 | + frame_offset); |
2091 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2092 | this assignment below, eventually. But it's still needed | |
2093 | for now. */ | |
72a155b4 UW |
2094 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2095 | + mips_regnum (gdbarch)->pc] | |
2096 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2097 | + MIPS_RA_REGNUM]; |
29639122 | 2098 | } |
c906108c | 2099 | |
29639122 JB |
2100 | /* If we didn't reach the end of the prologue when scanning the function |
2101 | instructions, then set end_prologue_addr to the address of the | |
2102 | instruction immediately after the last one we scanned. */ | |
2103 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2104 | we may as well be careful and do our best if we have a null | |
2105 | end_prologue_addr. */ | |
2106 | if (end_prologue_addr == 0) | |
2107 | end_prologue_addr = cur_pc; | |
2108 | ||
2109 | /* In a frameless function, we might have incorrectly | |
2110 | skipped some load immediate instructions. Undo the skipping | |
2111 | if the load immediate was not followed by a stack adjustment. */ | |
2112 | if (load_immediate_bytes && !seen_sp_adjust) | |
2113 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2114 | |
29639122 | 2115 | return end_prologue_addr; |
c906108c SS |
2116 | } |
2117 | ||
29639122 JB |
2118 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2119 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2120 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2121 | unwinder. */ | |
c906108c | 2122 | |
29639122 | 2123 | static struct mips_frame_cache * |
b8a22b94 | 2124 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2125 | { |
e17a4113 | 2126 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2127 | struct mips_frame_cache *cache; |
c906108c | 2128 | |
29639122 JB |
2129 | if ((*this_cache) != NULL) |
2130 | return (*this_cache); | |
c5aa993b | 2131 | |
29639122 JB |
2132 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2133 | (*this_cache) = cache; | |
b8a22b94 | 2134 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2135 | |
29639122 JB |
2136 | /* Analyze the function prologue. */ |
2137 | { | |
b8a22b94 | 2138 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2139 | CORE_ADDR start_addr; |
c906108c | 2140 | |
29639122 JB |
2141 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2142 | if (start_addr == 0) | |
e17a4113 | 2143 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2144 | /* We can't analyze the prologue if we couldn't find the begining |
2145 | of the function. */ | |
2146 | if (start_addr == 0) | |
2147 | return cache; | |
c5aa993b | 2148 | |
e17a4113 | 2149 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2150 | } |
2151 | ||
3e8c568d | 2152 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2153 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2154 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2155 | cache->base); |
c5aa993b | 2156 | |
29639122 | 2157 | return (*this_cache); |
c906108c SS |
2158 | } |
2159 | ||
29639122 | 2160 | static void |
b8a22b94 | 2161 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2162 | struct frame_id *this_id) |
c906108c | 2163 | { |
b8a22b94 | 2164 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2165 | this_cache); |
b8a22b94 | 2166 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2167 | } |
c906108c | 2168 | |
b8a22b94 DJ |
2169 | static struct value * |
2170 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2171 | void **this_cache, int regnum) | |
29639122 | 2172 | { |
b8a22b94 | 2173 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2174 | this_cache); |
b8a22b94 DJ |
2175 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2176 | } | |
2177 | ||
2178 | static int | |
2179 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2180 | struct frame_info *this_frame, void **this_cache) | |
2181 | { | |
2182 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2183 | if (! mips_pc_is_mips16 (pc)) | |
2184 | return 1; | |
2185 | return 0; | |
c906108c SS |
2186 | } |
2187 | ||
29639122 JB |
2188 | static const struct frame_unwind mips_insn32_frame_unwind = |
2189 | { | |
2190 | NORMAL_FRAME, | |
2191 | mips_insn32_frame_this_id, | |
b8a22b94 DJ |
2192 | mips_insn32_frame_prev_register, |
2193 | NULL, | |
2194 | mips_insn32_frame_sniffer | |
29639122 | 2195 | }; |
c906108c | 2196 | |
1c645fec | 2197 | static CORE_ADDR |
b8a22b94 | 2198 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2199 | void **this_cache) |
c906108c | 2200 | { |
b8a22b94 | 2201 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2202 | this_cache); |
2203 | return info->base; | |
2204 | } | |
c906108c | 2205 | |
29639122 JB |
2206 | static const struct frame_base mips_insn32_frame_base = |
2207 | { | |
2208 | &mips_insn32_frame_unwind, | |
2209 | mips_insn32_frame_base_address, | |
2210 | mips_insn32_frame_base_address, | |
2211 | mips_insn32_frame_base_address | |
2212 | }; | |
1c645fec | 2213 | |
29639122 | 2214 | static const struct frame_base * |
b8a22b94 | 2215 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2216 | { |
b8a22b94 DJ |
2217 | CORE_ADDR pc = get_frame_pc (this_frame); |
2218 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2219 | return &mips_insn32_frame_base; |
a65bbe44 | 2220 | else |
29639122 JB |
2221 | return NULL; |
2222 | } | |
a65bbe44 | 2223 | |
29639122 | 2224 | static struct trad_frame_cache * |
b8a22b94 | 2225 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2226 | { |
2227 | CORE_ADDR pc; | |
2228 | CORE_ADDR start_addr; | |
2229 | CORE_ADDR stack_addr; | |
2230 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2231 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2232 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2233 | |
29639122 JB |
2234 | if ((*this_cache) != NULL) |
2235 | return (*this_cache); | |
b8a22b94 | 2236 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2237 | (*this_cache) = this_trad_cache; |
1c645fec | 2238 | |
29639122 | 2239 | /* The return address is in the link register. */ |
3e8c568d | 2240 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2241 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2242 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2243 | |
29639122 JB |
2244 | /* Frame ID, since it's a frameless / stackless function, no stack |
2245 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2246 | pc = get_frame_pc (this_frame); |
29639122 | 2247 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2248 | stack_addr = get_frame_register_signed (this_frame, |
2249 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2250 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2251 | |
29639122 JB |
2252 | /* Assume that the frame's base is the same as the |
2253 | stack-pointer. */ | |
2254 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2255 | |
29639122 JB |
2256 | return this_trad_cache; |
2257 | } | |
c906108c | 2258 | |
29639122 | 2259 | static void |
b8a22b94 | 2260 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2261 | struct frame_id *this_id) |
2262 | { | |
2263 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2264 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2265 | trad_frame_get_id (this_trad_cache, this_id); |
2266 | } | |
c906108c | 2267 | |
b8a22b94 DJ |
2268 | static struct value * |
2269 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2270 | void **this_cache, int regnum) | |
29639122 JB |
2271 | { |
2272 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2273 | = mips_stub_frame_cache (this_frame, this_cache); |
2274 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2275 | } |
c906108c | 2276 | |
b8a22b94 DJ |
2277 | static int |
2278 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2279 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2280 | { |
aa6c981f | 2281 | gdb_byte dummy[4]; |
979b38e0 | 2282 | struct obj_section *s; |
b8a22b94 | 2283 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2284 | struct minimal_symbol *msym; |
979b38e0 | 2285 | |
aa6c981f | 2286 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2287 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2288 | return 1; | |
aa6c981f | 2289 | |
29639122 | 2290 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2291 | return 1; |
979b38e0 DJ |
2292 | |
2293 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2294 | s = find_pc_section (pc); | |
2295 | ||
2296 | if (s != NULL | |
2297 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2298 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2299 | return 1; |
979b38e0 | 2300 | |
db5f024e DJ |
2301 | /* Calling a PIC function from a non-PIC function passes through a |
2302 | stub. The stub for foo is named ".pic.foo". */ | |
2303 | msym = lookup_minimal_symbol_by_pc (pc); | |
2304 | if (msym != NULL | |
2305 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2306 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2307 | return 1; | |
2308 | ||
b8a22b94 | 2309 | return 0; |
29639122 | 2310 | } |
c906108c | 2311 | |
b8a22b94 DJ |
2312 | static const struct frame_unwind mips_stub_frame_unwind = |
2313 | { | |
2314 | NORMAL_FRAME, | |
2315 | mips_stub_frame_this_id, | |
2316 | mips_stub_frame_prev_register, | |
2317 | NULL, | |
2318 | mips_stub_frame_sniffer | |
2319 | }; | |
2320 | ||
29639122 | 2321 | static CORE_ADDR |
b8a22b94 | 2322 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2323 | void **this_cache) |
2324 | { | |
2325 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2326 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2327 | return trad_frame_get_this_base (this_trad_cache); |
2328 | } | |
0fce0821 | 2329 | |
29639122 JB |
2330 | static const struct frame_base mips_stub_frame_base = |
2331 | { | |
2332 | &mips_stub_frame_unwind, | |
2333 | mips_stub_frame_base_address, | |
2334 | mips_stub_frame_base_address, | |
2335 | mips_stub_frame_base_address | |
2336 | }; | |
2337 | ||
2338 | static const struct frame_base * | |
b8a22b94 | 2339 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2340 | { |
b8a22b94 | 2341 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2342 | return &mips_stub_frame_base; |
2343 | else | |
2344 | return NULL; | |
2345 | } | |
2346 | ||
29639122 | 2347 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2348 | |
29639122 | 2349 | static CORE_ADDR |
24568a2c | 2350 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2351 | { |
24568a2c | 2352 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
29639122 JB |
2353 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2354 | /* This hack is a work-around for existing boards using PMON, the | |
2355 | simulator, and any other 64-bit targets that doesn't have true | |
2356 | 64-bit addressing. On these targets, the upper 32 bits of | |
2357 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2358 | likely to have been sign extended to all 1s by instruction | |
2359 | sequences that load 32-bit addresses. For example, a typical | |
2360 | piece of code that loads an address is this: | |
65596487 | 2361 | |
29639122 JB |
2362 | lui $r2, <upper 16 bits> |
2363 | ori $r2, <lower 16 bits> | |
65596487 | 2364 | |
29639122 JB |
2365 | But the lui sign-extends the value such that the upper 32 bits |
2366 | may be all 1s. The workaround is simply to mask off these | |
2367 | bits. In the future, gcc may be changed to support true 64-bit | |
2368 | addressing, and this masking will have to be disabled. */ | |
2369 | return addr &= 0xffffffffUL; | |
2370 | else | |
2371 | return addr; | |
65596487 JB |
2372 | } |
2373 | ||
3d5f6d12 DJ |
2374 | /* Instructions used during single-stepping of atomic sequences. */ |
2375 | #define LL_OPCODE 0x30 | |
2376 | #define LLD_OPCODE 0x34 | |
2377 | #define SC_OPCODE 0x38 | |
2378 | #define SCD_OPCODE 0x3c | |
2379 | ||
2380 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2381 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2382 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2383 | the sequence. */ | |
2384 | ||
2385 | static int | |
a6d9a66e | 2386 | deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
3d5f6d12 DJ |
2387 | { |
2388 | CORE_ADDR breaks[2] = {-1, -1}; | |
2389 | CORE_ADDR loc = pc; | |
2390 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2391 | unsigned long insn; | |
2392 | int insn_count; | |
2393 | int index; | |
2394 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2395 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2396 | ||
2397 | if (pc & 0x01) | |
2398 | return 0; | |
2399 | ||
e17a4113 | 2400 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2401 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2402 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2403 | return 0; | |
2404 | ||
2405 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2406 | instructions. */ | |
2407 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2408 | { | |
2409 | int is_branch = 0; | |
2410 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2411 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2412 | |
2413 | /* Assume that there is at most one branch in the atomic | |
2414 | sequence. If a branch is found, put a breakpoint in its | |
2415 | destination address. */ | |
2416 | switch (itype_op (insn)) | |
2417 | { | |
2418 | case 0: /* SPECIAL */ | |
2419 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
2420 | return 0; /* fallback to the standard single-step code. */ | |
2421 | break; | |
2422 | case 1: /* REGIMM */ | |
2423 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2424 | break; | |
2425 | case 2: /* J */ | |
2426 | case 3: /* JAL */ | |
2427 | return 0; /* fallback to the standard single-step code. */ | |
2428 | case 4: /* BEQ */ | |
2429 | case 5: /* BNE */ | |
2430 | case 6: /* BLEZ */ | |
2431 | case 7: /* BGTZ */ | |
2432 | case 20: /* BEQL */ | |
2433 | case 21: /* BNEL */ | |
2434 | case 22: /* BLEZL */ | |
2435 | case 23: /* BGTTL */ | |
2436 | is_branch = 1; | |
2437 | break; | |
2438 | case 17: /* COP1 */ | |
2439 | case 18: /* COP2 */ | |
2440 | case 19: /* COP3 */ | |
2441 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2442 | break; | |
2443 | } | |
2444 | if (is_branch) | |
2445 | { | |
2446 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2447 | if (last_breakpoint >= 1) | |
2448 | return 0; /* More than one branch found, fallback to the | |
2449 | standard single-step code. */ | |
2450 | breaks[1] = branch_bp; | |
2451 | last_breakpoint++; | |
2452 | } | |
2453 | ||
2454 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2455 | break; | |
2456 | } | |
2457 | ||
2458 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2459 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2460 | return 0; | |
2461 | ||
2462 | loc += MIPS_INSN32_SIZE; | |
2463 | ||
2464 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2465 | breaks[0] = loc; | |
2466 | ||
2467 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
2468 | placed (branch instruction's destination) in the atomic sequence */ | |
2469 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
2470 | last_breakpoint = 0; | |
2471 | ||
2472 | /* Effectively inserts the breakpoints. */ | |
2473 | for (index = 0; index <= last_breakpoint; index++) | |
a6d9a66e | 2474 | insert_single_step_breakpoint (gdbarch, breaks[index]); |
3d5f6d12 DJ |
2475 | |
2476 | return 1; | |
2477 | } | |
2478 | ||
29639122 JB |
2479 | /* mips_software_single_step() is called just before we want to resume |
2480 | the inferior, if we want to single-step it but there is no hardware | |
2481 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2482 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2483 | |
e6590a1b | 2484 | int |
0b1b3e42 | 2485 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2486 | { |
a6d9a66e | 2487 | struct gdbarch *gdbarch = get_frame_arch (frame); |
8181d85f | 2488 | CORE_ADDR pc, next_pc; |
65596487 | 2489 | |
0b1b3e42 | 2490 | pc = get_frame_pc (frame); |
a6d9a66e | 2491 | if (deal_with_atomic_sequence (gdbarch, pc)) |
3d5f6d12 DJ |
2492 | return 1; |
2493 | ||
0b1b3e42 | 2494 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2495 | |
a6d9a66e | 2496 | insert_single_step_breakpoint (gdbarch, next_pc); |
e6590a1b | 2497 | return 1; |
29639122 | 2498 | } |
a65bbe44 | 2499 | |
29639122 JB |
2500 | /* Test whether the PC points to the return instruction at the |
2501 | end of a function. */ | |
65596487 | 2502 | |
29639122 | 2503 | static int |
e17a4113 | 2504 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2505 | { |
0fe7e7c8 | 2506 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2507 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2508 | generates a "jr $ra"; other times it generates code to load | |
2509 | the return address from the stack to an accessible register (such | |
2510 | as $a3), then a "jr" using that register. This second case | |
2511 | is almost impossible to distinguish from an indirect jump | |
2512 | used for switch statements, so we don't even try. */ | |
e17a4113 | 2513 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
29639122 | 2514 | else |
e17a4113 | 2515 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
29639122 | 2516 | } |
c906108c | 2517 | |
c906108c | 2518 | |
29639122 JB |
2519 | /* This fencepost looks highly suspicious to me. Removing it also |
2520 | seems suspicious as it could affect remote debugging across serial | |
2521 | lines. */ | |
c906108c | 2522 | |
29639122 | 2523 | static CORE_ADDR |
74ed0bb4 | 2524 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2525 | { |
2526 | CORE_ADDR start_pc; | |
2527 | CORE_ADDR fence; | |
2528 | int instlen; | |
2529 | int seen_adjsp = 0; | |
d6b48e9c | 2530 | struct inferior *inf; |
65596487 | 2531 | |
74ed0bb4 | 2532 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2533 | start_pc = pc; |
2534 | fence = start_pc - heuristic_fence_post; | |
2535 | if (start_pc == 0) | |
2536 | return 0; | |
65596487 | 2537 | |
29639122 JB |
2538 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2539 | fence = VM_MIN_ADDRESS; | |
65596487 | 2540 | |
95ac2dcf | 2541 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2542 | |
d6b48e9c PA |
2543 | inf = current_inferior (); |
2544 | ||
29639122 JB |
2545 | /* search back for previous return */ |
2546 | for (start_pc -= instlen;; start_pc -= instlen) | |
2547 | if (start_pc < fence) | |
2548 | { | |
2549 | /* It's not clear to me why we reach this point when | |
2550 | stop_soon, but with this test, at least we | |
2551 | don't print out warnings for every child forked (eg, on | |
2552 | decstation). 22apr93 rich@cygnus.com. */ | |
d6b48e9c | 2553 | if (inf->stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2554 | { |
2555 | static int blurb_printed = 0; | |
98b4dd94 | 2556 | |
5af949e3 UW |
2557 | warning (_("GDB can't find the start of the function at %s."), |
2558 | paddress (gdbarch, pc)); | |
29639122 JB |
2559 | |
2560 | if (!blurb_printed) | |
2561 | { | |
2562 | /* This actually happens frequently in embedded | |
2563 | development, when you first connect to a board | |
2564 | and your stack pointer and pc are nowhere in | |
2565 | particular. This message needs to give people | |
2566 | in that situation enough information to | |
2567 | determine that it's no big deal. */ | |
2568 | printf_filtered ("\n\ | |
5af949e3 | 2569 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2570 | and thus can't determine the size of that function's stack frame.\n\ |
2571 | This means that GDB may be unable to access that stack frame, or\n\ | |
2572 | the frames below it.\n\ | |
2573 | This problem is most likely caused by an invalid program counter or\n\ | |
2574 | stack pointer.\n\ | |
2575 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2576 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2577 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2578 | heuristic-fence-post' command.\n", |
2579 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2580 | blurb_printed = 1; |
2581 | } | |
2582 | } | |
2583 | ||
2584 | return 0; | |
2585 | } | |
0fe7e7c8 | 2586 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2587 | { |
2588 | unsigned short inst; | |
2589 | ||
2590 | /* On MIPS16, any one of the following is likely to be the | |
2591 | start of a function: | |
193774b3 MR |
2592 | extend save |
2593 | save | |
29639122 JB |
2594 | entry |
2595 | addiu sp,-n | |
2596 | daddiu sp,-n | |
2597 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
e17a4113 | 2598 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2599 | if ((inst & 0xff80) == 0x6480) /* save */ |
2600 | { | |
2601 | if (start_pc - instlen >= fence) | |
2602 | { | |
e17a4113 | 2603 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2604 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2605 | start_pc -= instlen; | |
2606 | } | |
2607 | break; | |
2608 | } | |
2609 | else if (((inst & 0xf81f) == 0xe809 | |
2610 | && (inst & 0x700) != 0x700) /* entry */ | |
2611 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2612 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2613 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2614 | break; |
2615 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2616 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2617 | seen_adjsp = 1; | |
2618 | else | |
2619 | seen_adjsp = 0; | |
2620 | } | |
e17a4113 | 2621 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2622 | { |
4c7d22cb | 2623 | /* Skip return and its delay slot. */ |
95ac2dcf | 2624 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2625 | break; |
2626 | } | |
2627 | ||
2628 | return start_pc; | |
c906108c SS |
2629 | } |
2630 | ||
6c0d6680 DJ |
2631 | struct mips_objfile_private |
2632 | { | |
2633 | bfd_size_type size; | |
2634 | char *contents; | |
2635 | }; | |
2636 | ||
f09ded24 AC |
2637 | /* According to the current ABI, should the type be passed in a |
2638 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2639 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2640 | FP registers and, consequently this returns false - forces FP |
2641 | arguments into integer registers. */ | |
2642 | ||
2643 | static int | |
74ed0bb4 MD |
2644 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2645 | struct type *arg_type) | |
f09ded24 AC |
2646 | { |
2647 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2648 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2649 | && (typecode == TYPE_CODE_STRUCT |
2650 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2651 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2652 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2653 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2654 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2655 | } |
2656 | ||
49e790b0 DJ |
2657 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2658 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2659 | ||
2660 | static int | |
2661 | mips_type_needs_double_align (struct type *type) | |
2662 | { | |
2663 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2664 | |
49e790b0 DJ |
2665 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2666 | return 1; | |
2667 | else if (typecode == TYPE_CODE_STRUCT) | |
2668 | { | |
2669 | if (TYPE_NFIELDS (type) < 1) | |
2670 | return 0; | |
2671 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2672 | } | |
2673 | else if (typecode == TYPE_CODE_UNION) | |
2674 | { | |
361d1df0 | 2675 | int i, n; |
49e790b0 DJ |
2676 | |
2677 | n = TYPE_NFIELDS (type); | |
2678 | for (i = 0; i < n; i++) | |
2679 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2680 | return 1; | |
2681 | return 0; | |
2682 | } | |
2683 | return 0; | |
2684 | } | |
2685 | ||
dc604539 AC |
2686 | /* Adjust the address downward (direction of stack growth) so that it |
2687 | is correctly aligned for a new stack frame. */ | |
2688 | static CORE_ADDR | |
2689 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2690 | { | |
5b03f266 | 2691 | return align_down (addr, 16); |
dc604539 AC |
2692 | } |
2693 | ||
f7ab6ec6 | 2694 | static CORE_ADDR |
7d9b040b | 2695 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2696 | struct regcache *regcache, CORE_ADDR bp_addr, |
2697 | int nargs, struct value **args, CORE_ADDR sp, | |
2698 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2699 | { |
2700 | int argreg; | |
2701 | int float_argreg; | |
2702 | int argnum; | |
2703 | int len = 0; | |
2704 | int stack_offset = 0; | |
480d3dd2 | 2705 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 2706 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 2707 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2708 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2709 | |
25ab4790 AC |
2710 | /* For shared libraries, "t9" needs to point at the function |
2711 | address. */ | |
4c7d22cb | 2712 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2713 | |
2714 | /* Set the return address register to point to the entry point of | |
2715 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2716 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2717 | |
c906108c | 2718 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2719 | are properly aligned. The stack has to be at least 64-bit |
2720 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2721 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2722 | aligned, so we round to this widest known alignment. */ | |
2723 | ||
5b03f266 AC |
2724 | sp = align_down (sp, 16); |
2725 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2726 | |
46e0f506 | 2727 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2728 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2729 | passed in registers, but that's OK. */ |
c906108c | 2730 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2731 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2732 | sp -= align_up (len, 16); |
c906108c | 2733 | |
9ace0497 | 2734 | if (mips_debug) |
6d82d43b | 2735 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2736 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2737 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2738 | |
c906108c | 2739 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2740 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2741 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2742 | |
46e0f506 | 2743 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2744 | if (struct_return) |
9ace0497 AC |
2745 | { |
2746 | if (mips_debug) | |
2747 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
2748 | "mips_eabi_push_dummy_call: struct_return reg=%d %s\n", |
2749 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 2750 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2751 | } |
c906108c SS |
2752 | |
2753 | /* Now load as many as possible of the first arguments into | |
2754 | registers, and push the rest onto the stack. Loop thru args | |
2755 | from first to last. */ | |
2756 | for (argnum = 0; argnum < nargs; argnum++) | |
2757 | { | |
47a35522 MK |
2758 | const gdb_byte *val; |
2759 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2760 | struct value *arg = args[argnum]; |
4991999e | 2761 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2762 | int len = TYPE_LENGTH (arg_type); |
2763 | enum type_code typecode = TYPE_CODE (arg_type); | |
2764 | ||
9ace0497 AC |
2765 | if (mips_debug) |
2766 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2767 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2768 | argnum + 1, len, (int) typecode); |
9ace0497 | 2769 | |
c906108c | 2770 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2771 | reference. */ |
1a69e1e4 | 2772 | if (len > regsize |
9ace0497 | 2773 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2774 | { |
e17a4113 UW |
2775 | store_unsigned_integer (valbuf, regsize, byte_order, |
2776 | value_address (arg)); | |
c906108c | 2777 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2778 | len = regsize; |
c906108c | 2779 | val = valbuf; |
9ace0497 AC |
2780 | if (mips_debug) |
2781 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2782 | } |
2783 | else | |
47a35522 | 2784 | val = value_contents (arg); |
c906108c SS |
2785 | |
2786 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2787 | even-numbered floating point register. Round the FP register |
2788 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2789 | left. Non MIPS_EABI targets also pass the FP in the integer |
2790 | registers so also round up normal registers. */ | |
74ed0bb4 | 2791 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
2792 | { |
2793 | if ((float_argreg & 1)) | |
2794 | float_argreg++; | |
2795 | } | |
c906108c SS |
2796 | |
2797 | /* Floating point arguments passed in registers have to be | |
2798 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2799 | are passed in register pairs; the even register gets |
2800 | the low word, and the odd register gets the high word. | |
2801 | On non-EABI processors, the first two floating point arguments are | |
2802 | also copied to general registers, because MIPS16 functions | |
2803 | don't use float registers for arguments. This duplication of | |
2804 | arguments in general registers can't hurt non-MIPS16 functions | |
2805 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2806 | /* MIPS_EABI squeezes a struct that contains a single floating |
2807 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2808 | stack. */ |
74ed0bb4 MD |
2809 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
2810 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 2811 | { |
6da397e0 KB |
2812 | /* EABI32 will pass doubles in consecutive registers, even on |
2813 | 64-bit cores. At one time, we used to check the size of | |
2814 | `float_argreg' to determine whether or not to pass doubles | |
2815 | in consecutive registers, but this is not sufficient for | |
2816 | making the ABI determination. */ | |
2817 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2818 | { |
72a155b4 | 2819 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 2820 | == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2821 | unsigned long regval; |
2822 | ||
2823 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
2824 | regval = extract_unsigned_integer (val + low_offset, |
2825 | 4, byte_order); | |
9ace0497 | 2826 | if (mips_debug) |
acdb74a0 | 2827 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2828 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2829 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2830 | |
2831 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
2832 | regval = extract_unsigned_integer (val + 4 - low_offset, |
2833 | 4, byte_order); | |
9ace0497 | 2834 | if (mips_debug) |
acdb74a0 | 2835 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2836 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2837 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2838 | } |
2839 | else | |
2840 | { | |
2841 | /* This is a floating point value that fits entirely | |
2842 | in a single register. */ | |
53a5351d | 2843 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2844 | above to ensure that it is even register aligned. */ |
e17a4113 | 2845 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
9ace0497 | 2846 | if (mips_debug) |
acdb74a0 | 2847 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2848 | float_argreg, phex (regval, len)); |
9c9acae0 | 2849 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2850 | } |
2851 | } | |
2852 | else | |
2853 | { | |
2854 | /* Copy the argument to general registers or the stack in | |
2855 | register-sized pieces. Large arguments are split between | |
2856 | registers and stack. */ | |
1a69e1e4 DJ |
2857 | /* Note: structs whose size is not a multiple of regsize |
2858 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2859 | them in registers where gcc sometimes puts them on the |
2860 | stack. For maximum compatibility, we will put them in | |
2861 | both places. */ | |
1a69e1e4 | 2862 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2863 | |
f09ded24 | 2864 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2865 | register are only written to memory. */ |
c906108c SS |
2866 | while (len > 0) |
2867 | { | |
ebafbe83 | 2868 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2869 | int stack_used_p = 0; |
1a69e1e4 | 2870 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2871 | |
acdb74a0 AC |
2872 | if (mips_debug) |
2873 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2874 | partial_len); | |
2875 | ||
566f0f7a | 2876 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 2877 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 2878 | || odd_sized_struct |
74ed0bb4 | 2879 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 2880 | { |
c906108c SS |
2881 | /* Should shorter than int integer values be |
2882 | promoted to int before being stored? */ | |
c906108c | 2883 | int longword_offset = 0; |
9ace0497 | 2884 | CORE_ADDR addr; |
566f0f7a | 2885 | stack_used_p = 1; |
72a155b4 | 2886 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2887 | { |
1a69e1e4 | 2888 | if (regsize == 8 |
480d3dd2 AC |
2889 | && (typecode == TYPE_CODE_INT |
2890 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2891 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2892 | longword_offset = regsize - len; |
480d3dd2 AC |
2893 | else if ((typecode == TYPE_CODE_STRUCT |
2894 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2895 | && TYPE_LENGTH (arg_type) < regsize) |
2896 | longword_offset = regsize - len; | |
7a292a7a | 2897 | } |
c5aa993b | 2898 | |
9ace0497 AC |
2899 | if (mips_debug) |
2900 | { | |
5af949e3 UW |
2901 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
2902 | paddress (gdbarch, stack_offset)); | |
2903 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
2904 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 2905 | } |
361d1df0 | 2906 | |
9ace0497 AC |
2907 | addr = sp + stack_offset + longword_offset; |
2908 | ||
2909 | if (mips_debug) | |
2910 | { | |
2911 | int i; | |
5af949e3 UW |
2912 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
2913 | paddress (gdbarch, addr)); | |
9ace0497 AC |
2914 | for (i = 0; i < partial_len; i++) |
2915 | { | |
6d82d43b | 2916 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2917 | val[i] & 0xff); |
9ace0497 AC |
2918 | } |
2919 | } | |
2920 | write_memory (addr, val, partial_len); | |
c906108c SS |
2921 | } |
2922 | ||
f09ded24 AC |
2923 | /* Note!!! This is NOT an else clause. Odd sized |
2924 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2925 | arguments will not. */ |
566f0f7a | 2926 | /* Write this portion of the argument to a general |
6d82d43b | 2927 | purpose register. */ |
74ed0bb4 MD |
2928 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
2929 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 2930 | { |
6d82d43b | 2931 | LONGEST regval = |
e17a4113 | 2932 | extract_unsigned_integer (val, partial_len, byte_order); |
c906108c | 2933 | |
9ace0497 | 2934 | if (mips_debug) |
acdb74a0 | 2935 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2936 | argreg, |
1a69e1e4 | 2937 | phex (regval, regsize)); |
9c9acae0 | 2938 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
c906108c | 2939 | argreg++; |
c906108c | 2940 | } |
c5aa993b | 2941 | |
c906108c SS |
2942 | len -= partial_len; |
2943 | val += partial_len; | |
2944 | ||
566f0f7a | 2945 | /* Compute the the offset into the stack at which we |
6d82d43b | 2946 | will copy the next parameter. |
566f0f7a | 2947 | |
566f0f7a | 2948 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2949 | only needs to be adjusted when it has been used. */ |
c906108c | 2950 | |
46e0f506 | 2951 | if (stack_used_p) |
1a69e1e4 | 2952 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2953 | } |
2954 | } | |
9ace0497 AC |
2955 | if (mips_debug) |
2956 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2957 | } |
2958 | ||
f10683bb | 2959 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2960 | |
0f71a2f6 JM |
2961 | /* Return adjusted stack pointer. */ |
2962 | return sp; | |
2963 | } | |
2964 | ||
a1f5b845 | 2965 | /* Determine the return value convention being used. */ |
6d82d43b | 2966 | |
9c8fdbfa | 2967 | static enum return_value_convention |
c055b101 | 2968 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 2969 | struct type *type, struct regcache *regcache, |
47a35522 | 2970 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2971 | { |
609ba780 JM |
2972 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2973 | int fp_return_type = 0; | |
2974 | int offset, regnum, xfer; | |
2975 | ||
9c8fdbfa AC |
2976 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2977 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
2978 | |
2979 | /* Floating point type? */ | |
2980 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2981 | { | |
2982 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2983 | fp_return_type = 1; | |
2984 | /* Structs with a single field of float type | |
2985 | are returned in a floating point register. */ | |
2986 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2987 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2988 | && TYPE_NFIELDS (type) == 1) | |
2989 | { | |
2990 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
2991 | ||
2992 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
2993 | fp_return_type = 1; | |
2994 | } | |
2995 | } | |
2996 | ||
2997 | if (fp_return_type) | |
2998 | { | |
2999 | /* A floating-point value belongs in the least significant part | |
3000 | of FP0/FP1. */ | |
3001 | if (mips_debug) | |
3002 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3003 | regnum = mips_regnum (gdbarch)->fp0; | |
3004 | } | |
3005 | else | |
3006 | { | |
3007 | /* An integer value goes in V0/V1. */ | |
3008 | if (mips_debug) | |
3009 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3010 | regnum = MIPS_V0_REGNUM; | |
3011 | } | |
3012 | for (offset = 0; | |
3013 | offset < TYPE_LENGTH (type); | |
3014 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3015 | { | |
3016 | xfer = mips_abi_regsize (gdbarch); | |
3017 | if (offset + xfer > TYPE_LENGTH (type)) | |
3018 | xfer = TYPE_LENGTH (type) - offset; | |
3019 | mips_xfer_register (gdbarch, regcache, | |
3020 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3021 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3022 | offset); | |
3023 | } | |
3024 | ||
9c8fdbfa | 3025 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3026 | } |
3027 | ||
6d82d43b AC |
3028 | |
3029 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3030 | |
8d26208a DJ |
3031 | /* Search for a naturally aligned double at OFFSET inside a struct |
3032 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3033 | registers. */ | |
3034 | ||
3035 | static int | |
74ed0bb4 MD |
3036 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3037 | int offset) | |
8d26208a DJ |
3038 | { |
3039 | int i; | |
3040 | ||
3041 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3042 | return 0; | |
3043 | ||
74ed0bb4 | 3044 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3045 | return 0; |
3046 | ||
3047 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3048 | return 0; | |
3049 | ||
3050 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3051 | { | |
3052 | int pos; | |
3053 | struct type *field_type; | |
3054 | ||
3055 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3056 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3057 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3058 | continue; | |
3059 | ||
3060 | /* If we have gone past the offset, there is no double to pass. */ | |
3061 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3062 | if (pos > offset) | |
3063 | return 0; | |
3064 | ||
3065 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3066 | ||
3067 | /* If this field is entirely before the requested offset, go | |
3068 | on to the next one. */ | |
3069 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3070 | continue; | |
3071 | ||
3072 | /* If this is our special aligned double, we can stop. */ | |
3073 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3074 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3075 | return 1; | |
3076 | ||
3077 | /* This field starts at or before the requested offset, and | |
3078 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3079 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3080 | } |
3081 | ||
3082 | return 0; | |
3083 | } | |
3084 | ||
f7ab6ec6 | 3085 | static CORE_ADDR |
7d9b040b | 3086 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3087 | struct regcache *regcache, CORE_ADDR bp_addr, |
3088 | int nargs, struct value **args, CORE_ADDR sp, | |
3089 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3090 | { |
3091 | int argreg; | |
3092 | int float_argreg; | |
3093 | int argnum; | |
3094 | int len = 0; | |
3095 | int stack_offset = 0; | |
480d3dd2 | 3096 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3097 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3098 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3099 | |
25ab4790 AC |
3100 | /* For shared libraries, "t9" needs to point at the function |
3101 | address. */ | |
4c7d22cb | 3102 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3103 | |
3104 | /* Set the return address register to point to the entry point of | |
3105 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3106 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3107 | |
cb3d25d1 MS |
3108 | /* First ensure that the stack and structure return address (if any) |
3109 | are properly aligned. The stack has to be at least 64-bit | |
3110 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3111 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3112 | aligned, so we round to this widest known alignment. */ | |
3113 | ||
5b03f266 AC |
3114 | sp = align_down (sp, 16); |
3115 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3116 | |
3117 | /* Now make space on the stack for the args. */ | |
3118 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3119 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3120 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3121 | |
3122 | if (mips_debug) | |
6d82d43b | 3123 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3124 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3125 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3126 | |
3127 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3128 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3129 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3130 | |
46e0f506 | 3131 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3132 | if (struct_return) |
3133 | { | |
3134 | if (mips_debug) | |
3135 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3136 | "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n", |
3137 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3138 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3139 | } |
3140 | ||
3141 | /* Now load as many as possible of the first arguments into | |
3142 | registers, and push the rest onto the stack. Loop thru args | |
3143 | from first to last. */ | |
3144 | for (argnum = 0; argnum < nargs; argnum++) | |
3145 | { | |
47a35522 | 3146 | const gdb_byte *val; |
cb3d25d1 | 3147 | struct value *arg = args[argnum]; |
4991999e | 3148 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3149 | int len = TYPE_LENGTH (arg_type); |
3150 | enum type_code typecode = TYPE_CODE (arg_type); | |
3151 | ||
3152 | if (mips_debug) | |
3153 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3154 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3155 | argnum + 1, len, (int) typecode); |
3156 | ||
47a35522 | 3157 | val = value_contents (arg); |
cb3d25d1 | 3158 | |
5b68030f JM |
3159 | /* A 128-bit long double value requires an even-odd pair of |
3160 | floating-point registers. */ | |
3161 | if (len == 16 | |
3162 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3163 | && (float_argreg & 1)) | |
3164 | { | |
3165 | float_argreg++; | |
3166 | argreg++; | |
3167 | } | |
3168 | ||
74ed0bb4 MD |
3169 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3170 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3171 | { |
3172 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3173 | in a single register or a pair of registers. */ |
3174 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3175 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3176 | if (mips_debug) |
3177 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3178 | float_argreg, phex (regval, reglen)); |
8d26208a | 3179 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3180 | |
3181 | if (mips_debug) | |
3182 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3183 | argreg, phex (regval, reglen)); |
9c9acae0 | 3184 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3185 | float_argreg++; |
3186 | argreg++; | |
5b68030f JM |
3187 | if (len == 16) |
3188 | { | |
e17a4113 UW |
3189 | regval = extract_unsigned_integer (val + reglen, |
3190 | reglen, byte_order); | |
5b68030f JM |
3191 | if (mips_debug) |
3192 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3193 | float_argreg, phex (regval, reglen)); | |
3194 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3195 | ||
3196 | if (mips_debug) | |
3197 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3198 | argreg, phex (regval, reglen)); | |
3199 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3200 | float_argreg++; | |
3201 | argreg++; | |
3202 | } | |
cb3d25d1 MS |
3203 | } |
3204 | else | |
3205 | { | |
3206 | /* Copy the argument to general registers or the stack in | |
3207 | register-sized pieces. Large arguments are split between | |
3208 | registers and stack. */ | |
ab2e1992 MR |
3209 | /* For N32/N64, structs, unions, or other composite types are |
3210 | treated as a sequence of doublewords, and are passed in integer | |
3211 | or floating point registers as though they were simple scalar | |
3212 | parameters to the extent that they fit, with any excess on the | |
3213 | stack packed according to the normal memory layout of the | |
3214 | object. | |
3215 | The caller does not reserve space for the register arguments; | |
3216 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3217 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3218 | register are only written to memory. */ |
cb3d25d1 MS |
3219 | while (len > 0) |
3220 | { | |
ad018eee | 3221 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3222 | int stack_used_p = 0; |
1a69e1e4 | 3223 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3224 | |
3225 | if (mips_debug) | |
3226 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3227 | partial_len); | |
3228 | ||
74ed0bb4 MD |
3229 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3230 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3231 | |
cb3d25d1 | 3232 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3233 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3234 | { |
3235 | /* Should shorter than int integer values be | |
3236 | promoted to int before being stored? */ | |
3237 | int longword_offset = 0; | |
3238 | CORE_ADDR addr; | |
3239 | stack_used_p = 1; | |
72a155b4 | 3240 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3241 | { |
1a69e1e4 | 3242 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3243 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3244 | && len <= 4) |
3245 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3246 | } |
3247 | ||
3248 | if (mips_debug) | |
3249 | { | |
5af949e3 UW |
3250 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3251 | paddress (gdbarch, stack_offset)); | |
3252 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3253 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3254 | } |
3255 | ||
3256 | addr = sp + stack_offset + longword_offset; | |
3257 | ||
3258 | if (mips_debug) | |
3259 | { | |
3260 | int i; | |
5af949e3 UW |
3261 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3262 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3263 | for (i = 0; i < partial_len; i++) |
3264 | { | |
6d82d43b | 3265 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3266 | val[i] & 0xff); |
3267 | } | |
3268 | } | |
3269 | write_memory (addr, val, partial_len); | |
3270 | } | |
3271 | ||
3272 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3273 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3274 | /* Write this portion of the argument to a general |
6d82d43b | 3275 | purpose register. */ |
74ed0bb4 | 3276 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3277 | { |
5863b5d5 MR |
3278 | LONGEST regval; |
3279 | ||
3280 | /* Sign extend pointers, 32-bit integers and signed | |
3281 | 16-bit and 8-bit integers; everything else is taken | |
3282 | as is. */ | |
3283 | ||
3284 | if ((partial_len == 4 | |
3285 | && (typecode == TYPE_CODE_PTR | |
3286 | || typecode == TYPE_CODE_INT)) | |
3287 | || (partial_len < 4 | |
3288 | && typecode == TYPE_CODE_INT | |
3289 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3290 | regval = extract_signed_integer (val, partial_len, |
3291 | byte_order); | |
5863b5d5 | 3292 | else |
e17a4113 UW |
3293 | regval = extract_unsigned_integer (val, partial_len, |
3294 | byte_order); | |
cb3d25d1 MS |
3295 | |
3296 | /* A non-floating-point argument being passed in a | |
3297 | general register. If a struct or union, and if | |
3298 | the remaining length is smaller than the register | |
3299 | size, we have to adjust the register value on | |
3300 | big endian targets. | |
3301 | ||
3302 | It does not seem to be necessary to do the | |
1a69e1e4 | 3303 | same for integral types. */ |
cb3d25d1 | 3304 | |
72a155b4 | 3305 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3306 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3307 | && (typecode == TYPE_CODE_STRUCT |
3308 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3309 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3310 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3311 | |
3312 | if (mips_debug) | |
3313 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3314 | argreg, | |
1a69e1e4 | 3315 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3316 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3317 | |
74ed0bb4 | 3318 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3319 | TYPE_LENGTH (arg_type) - len)) |
3320 | { | |
3321 | if (mips_debug) | |
3322 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3323 | float_argreg, | |
3324 | phex (regval, MIPS64_REGSIZE)); | |
3325 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3326 | regval); | |
3327 | } | |
3328 | ||
3329 | float_argreg++; | |
cb3d25d1 MS |
3330 | argreg++; |
3331 | } | |
3332 | ||
3333 | len -= partial_len; | |
3334 | val += partial_len; | |
3335 | ||
3336 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3337 | will copy the next parameter. |
cb3d25d1 MS |
3338 | |
3339 | In N32 (N64?), the stack_offset only needs to be | |
3340 | adjusted when it has been used. */ | |
3341 | ||
3342 | if (stack_used_p) | |
1a69e1e4 | 3343 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3344 | } |
3345 | } | |
3346 | if (mips_debug) | |
3347 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3348 | } | |
3349 | ||
f10683bb | 3350 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3351 | |
cb3d25d1 MS |
3352 | /* Return adjusted stack pointer. */ |
3353 | return sp; | |
3354 | } | |
3355 | ||
6d82d43b | 3356 | static enum return_value_convention |
c055b101 | 3357 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3358 | struct type *type, struct regcache *regcache, |
47a35522 | 3359 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3360 | { |
72a155b4 | 3361 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3362 | |
3363 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3364 | ||
3365 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3366 | if needed), as appropriate for the type. Composite results (struct, | |
3367 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3368 | following rules: | |
3369 | ||
3370 | * A struct with only one or two floating point fields is returned in $f0 | |
3371 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3372 | case. | |
3373 | ||
3374 | * Any other struct or union results of at most 128 bits are returned in | |
3375 | $2 (first 64 bits) and $3 (remainder, if necessary). | |
3376 | ||
3377 | * Larger composite results are handled by converting the function to a | |
3378 | procedure with an implicit first parameter, which is a pointer to an area | |
3379 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3380 | that all composite results be handled by conversion to implicit first | |
3381 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3382 | specific exception to return COMPLEX results in the floating point | |
3383 | registers.] */ | |
3384 | ||
3385 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3386 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3387 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3388 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3389 | && TYPE_LENGTH (type) == 16 | |
3390 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3391 | { | |
3392 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3393 | two registers are used in the same as memory order, so the | |
3394 | eight bytes with the lower memory address are in $f0. */ | |
3395 | if (mips_debug) | |
3396 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3397 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3398 | gdbarch_num_regs (gdbarch) |
3399 | + mips_regnum (gdbarch)->fp0, | |
3400 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3401 | readbuf, writebuf, 0); |
ba32f989 | 3402 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3403 | gdbarch_num_regs (gdbarch) |
3404 | + mips_regnum (gdbarch)->fp0 + 2, | |
3405 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3406 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3407 | writebuf ? writebuf + 8 : writebuf, 0); |
3408 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3409 | } | |
6d82d43b AC |
3410 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3411 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3412 | { | |
59aa1faa | 3413 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3414 | if (mips_debug) |
3415 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3416 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3417 | gdbarch_num_regs (gdbarch) |
3418 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3419 | TYPE_LENGTH (type), |
72a155b4 | 3420 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3421 | readbuf, writebuf, 0); |
6d82d43b AC |
3422 | return RETURN_VALUE_REGISTER_CONVENTION; |
3423 | } | |
3424 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3425 | && TYPE_NFIELDS (type) <= 2 | |
3426 | && TYPE_NFIELDS (type) >= 1 | |
3427 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3428 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3429 | == TYPE_CODE_FLT)) |
3430 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3431 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3432 | == TYPE_CODE_FLT) |
b18bb924 | 3433 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3434 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3435 | { |
3436 | /* A struct that contains one or two floats. Each value is part | |
3437 | in the least significant part of their floating point | |
5b68030f | 3438 | register (or GPR, for soft float). */ |
6d82d43b AC |
3439 | int regnum; |
3440 | int field; | |
5b68030f JM |
3441 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3442 | ? mips_regnum (gdbarch)->fp0 | |
3443 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3444 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3445 | { | |
3446 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3447 | / TARGET_CHAR_BIT); | |
3448 | if (mips_debug) | |
3449 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3450 | offset); | |
5b68030f JM |
3451 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3452 | { | |
3453 | /* A 16-byte long double field goes in two consecutive | |
3454 | registers. */ | |
3455 | mips_xfer_register (gdbarch, regcache, | |
3456 | gdbarch_num_regs (gdbarch) + regnum, | |
3457 | 8, | |
3458 | gdbarch_byte_order (gdbarch), | |
3459 | readbuf, writebuf, offset); | |
3460 | mips_xfer_register (gdbarch, regcache, | |
3461 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3462 | 8, | |
3463 | gdbarch_byte_order (gdbarch), | |
3464 | readbuf, writebuf, offset + 8); | |
3465 | } | |
3466 | else | |
3467 | mips_xfer_register (gdbarch, regcache, | |
3468 | gdbarch_num_regs (gdbarch) + regnum, | |
3469 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3470 | gdbarch_byte_order (gdbarch), | |
3471 | readbuf, writebuf, offset); | |
6d82d43b AC |
3472 | } |
3473 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3474 | } | |
3475 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3476 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3477 | { | |
3478 | /* A structure or union. Extract the left justified value, | |
3479 | regardless of the byte order. I.e. DO NOT USE | |
3480 | mips_xfer_lower. */ | |
3481 | int offset; | |
3482 | int regnum; | |
4c7d22cb | 3483 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3484 | offset < TYPE_LENGTH (type); |
72a155b4 | 3485 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3486 | { |
72a155b4 | 3487 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3488 | if (offset + xfer > TYPE_LENGTH (type)) |
3489 | xfer = TYPE_LENGTH (type) - offset; | |
3490 | if (mips_debug) | |
3491 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3492 | offset, xfer, regnum); | |
ba32f989 DJ |
3493 | mips_xfer_register (gdbarch, regcache, |
3494 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3495 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3496 | offset); | |
6d82d43b AC |
3497 | } |
3498 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3499 | } | |
3500 | else | |
3501 | { | |
3502 | /* A scalar extract each part but least-significant-byte | |
3503 | justified. */ | |
3504 | int offset; | |
3505 | int regnum; | |
4c7d22cb | 3506 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3507 | offset < TYPE_LENGTH (type); |
72a155b4 | 3508 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3509 | { |
72a155b4 | 3510 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3511 | if (offset + xfer > TYPE_LENGTH (type)) |
3512 | xfer = TYPE_LENGTH (type) - offset; | |
3513 | if (mips_debug) | |
3514 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3515 | offset, xfer, regnum); | |
ba32f989 DJ |
3516 | mips_xfer_register (gdbarch, regcache, |
3517 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3518 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3519 | readbuf, writebuf, offset); |
6d82d43b AC |
3520 | } |
3521 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3522 | } | |
3523 | } | |
3524 | ||
3525 | /* O32 ABI stuff. */ | |
3526 | ||
3527 | static CORE_ADDR | |
7d9b040b | 3528 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3529 | struct regcache *regcache, CORE_ADDR bp_addr, |
3530 | int nargs, struct value **args, CORE_ADDR sp, | |
3531 | int struct_return, CORE_ADDR struct_addr) | |
3532 | { | |
3533 | int argreg; | |
3534 | int float_argreg; | |
3535 | int argnum; | |
3536 | int len = 0; | |
3537 | int stack_offset = 0; | |
3538 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3539 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3540 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3541 | |
3542 | /* For shared libraries, "t9" needs to point at the function | |
3543 | address. */ | |
4c7d22cb | 3544 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3545 | |
3546 | /* Set the return address register to point to the entry point of | |
3547 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3548 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3549 | |
3550 | /* First ensure that the stack and structure return address (if any) | |
3551 | are properly aligned. The stack has to be at least 64-bit | |
3552 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3553 | aligned. For n32 and n64, stack frames need to be 128-bit |
3554 | aligned, so we round to this widest known alignment. */ | |
3555 | ||
5b03f266 AC |
3556 | sp = align_down (sp, 16); |
3557 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3558 | |
3559 | /* Now make space on the stack for the args. */ | |
3560 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3561 | { |
3562 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3563 | int arglen = TYPE_LENGTH (arg_type); | |
3564 | ||
3565 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3566 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3567 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3568 | /* Allocate space on the stack. */ |
1a69e1e4 | 3569 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3570 | } |
5b03f266 | 3571 | sp -= align_up (len, 16); |
ebafbe83 MS |
3572 | |
3573 | if (mips_debug) | |
6d82d43b | 3574 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3575 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3576 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3577 | |
3578 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3579 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3580 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3581 | |
bcb0cc15 | 3582 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3583 | if (struct_return) |
3584 | { | |
3585 | if (mips_debug) | |
3586 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3587 | "mips_o32_push_dummy_call: struct_return reg=%d %s\n", |
3588 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3589 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3590 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3591 | } |
3592 | ||
3593 | /* Now load as many as possible of the first arguments into | |
3594 | registers, and push the rest onto the stack. Loop thru args | |
3595 | from first to last. */ | |
3596 | for (argnum = 0; argnum < nargs; argnum++) | |
3597 | { | |
47a35522 | 3598 | const gdb_byte *val; |
ebafbe83 | 3599 | struct value *arg = args[argnum]; |
4991999e | 3600 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3601 | int len = TYPE_LENGTH (arg_type); |
3602 | enum type_code typecode = TYPE_CODE (arg_type); | |
3603 | ||
3604 | if (mips_debug) | |
3605 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3606 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3607 | argnum + 1, len, (int) typecode); |
3608 | ||
47a35522 | 3609 | val = value_contents (arg); |
46cac009 AC |
3610 | |
3611 | /* 32-bit ABIs always start floating point arguments in an | |
3612 | even-numbered floating point register. Round the FP register | |
3613 | up before the check to see if there are any FP registers | |
3614 | left. O32/O64 targets also pass the FP in the integer | |
3615 | registers so also round up normal registers. */ | |
74ed0bb4 | 3616 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3617 | { |
3618 | if ((float_argreg & 1)) | |
3619 | float_argreg++; | |
3620 | } | |
3621 | ||
3622 | /* Floating point arguments passed in registers have to be | |
3623 | treated specially. On 32-bit architectures, doubles | |
3624 | are passed in register pairs; the even register gets | |
3625 | the low word, and the odd register gets the high word. | |
3626 | On O32/O64, the first two floating point arguments are | |
3627 | also copied to general registers, because MIPS16 functions | |
3628 | don't use float registers for arguments. This duplication of | |
3629 | arguments in general registers can't hurt non-MIPS16 functions | |
3630 | because those registers are normally skipped. */ | |
3631 | ||
74ed0bb4 MD |
3632 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3633 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3634 | { |
8b07f6d8 | 3635 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3636 | { |
72a155b4 | 3637 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3638 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3639 | unsigned long regval; |
3640 | ||
3641 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
3642 | regval = extract_unsigned_integer (val + low_offset, |
3643 | 4, byte_order); | |
46cac009 AC |
3644 | if (mips_debug) |
3645 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3646 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3647 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3648 | if (mips_debug) |
3649 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3650 | argreg, phex (regval, 4)); | |
9c9acae0 | 3651 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3652 | |
3653 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
3654 | regval = extract_unsigned_integer (val + 4 - low_offset, |
3655 | 4, byte_order); | |
46cac009 AC |
3656 | if (mips_debug) |
3657 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3658 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3659 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3660 | |
3661 | if (mips_debug) | |
3662 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3663 | argreg, phex (regval, 4)); | |
9c9acae0 | 3664 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3665 | } |
3666 | else | |
3667 | { | |
3668 | /* This is a floating point value that fits entirely | |
3669 | in a single register. */ | |
3670 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3671 | above to ensure that it is even register aligned. */ |
e17a4113 | 3672 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
3673 | if (mips_debug) |
3674 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3675 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3676 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
5b68030f JM |
3677 | /* Although two FP registers are reserved for each |
3678 | argument, only one corresponding integer register is | |
3679 | reserved. */ | |
46cac009 AC |
3680 | if (mips_debug) |
3681 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3682 | argreg, phex (regval, len)); | |
5b68030f | 3683 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3684 | } |
3685 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3686 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3687 | } |
3688 | else | |
3689 | { | |
3690 | /* Copy the argument to general registers or the stack in | |
3691 | register-sized pieces. Large arguments are split between | |
3692 | registers and stack. */ | |
1a69e1e4 DJ |
3693 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3694 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3695 | them in registers where gcc sometimes puts them on the |
3696 | stack. For maximum compatibility, we will put them in | |
3697 | both places. */ | |
1a69e1e4 DJ |
3698 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3699 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3700 | /* Structures should be aligned to eight bytes (even arg registers) |
3701 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3702 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3703 | { |
3704 | if ((argreg & 1)) | |
968b5391 MR |
3705 | { |
3706 | argreg++; | |
1a69e1e4 | 3707 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3708 | } |
46cac009 | 3709 | } |
46cac009 AC |
3710 | while (len > 0) |
3711 | { | |
3712 | /* Remember if the argument was written to the stack. */ | |
3713 | int stack_used_p = 0; | |
1a69e1e4 | 3714 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3715 | |
3716 | if (mips_debug) | |
3717 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3718 | partial_len); | |
3719 | ||
3720 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3721 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3722 | || odd_sized_struct) |
46cac009 AC |
3723 | { |
3724 | /* Should shorter than int integer values be | |
3725 | promoted to int before being stored? */ | |
3726 | int longword_offset = 0; | |
3727 | CORE_ADDR addr; | |
3728 | stack_used_p = 1; | |
46cac009 AC |
3729 | |
3730 | if (mips_debug) | |
3731 | { | |
5af949e3 UW |
3732 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3733 | paddress (gdbarch, stack_offset)); | |
3734 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3735 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
3736 | } |
3737 | ||
3738 | addr = sp + stack_offset + longword_offset; | |
3739 | ||
3740 | if (mips_debug) | |
3741 | { | |
3742 | int i; | |
5af949e3 UW |
3743 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3744 | paddress (gdbarch, addr)); | |
46cac009 AC |
3745 | for (i = 0; i < partial_len; i++) |
3746 | { | |
6d82d43b | 3747 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3748 | val[i] & 0xff); |
3749 | } | |
3750 | } | |
3751 | write_memory (addr, val, partial_len); | |
3752 | } | |
3753 | ||
3754 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3755 | structs may go thru BOTH paths. */ |
46cac009 | 3756 | /* Write this portion of the argument to a general |
6d82d43b | 3757 | purpose register. */ |
74ed0bb4 | 3758 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 3759 | { |
e17a4113 UW |
3760 | LONGEST regval = extract_signed_integer (val, partial_len, |
3761 | byte_order); | |
4246e332 | 3762 | /* Value may need to be sign extended, because |
1b13c4f6 | 3763 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3764 | |
3765 | /* A non-floating-point argument being passed in a | |
3766 | general register. If a struct or union, and if | |
3767 | the remaining length is smaller than the register | |
3768 | size, we have to adjust the register value on | |
3769 | big endian targets. | |
3770 | ||
3771 | It does not seem to be necessary to do the | |
3772 | same for integral types. | |
3773 | ||
3774 | Also don't do this adjustment on O64 binaries. | |
3775 | ||
3776 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3777 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3778 | mips_abi_regsize(), generates a left shift |
3779 | as part of storing the argument in a register | |
3780 | (the left shift isn't generated when | |
1b13c4f6 | 3781 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3782 | it is quite possible that this is GCC |
3783 | contradicting the LE/O32 ABI, GDB has not been | |
3784 | adjusted to accommodate this. Either someone | |
3785 | needs to demonstrate that the LE/O32 ABI | |
3786 | specifies such a left shift OR this new ABI gets | |
3787 | identified as such and GDB gets tweaked | |
3788 | accordingly. */ | |
3789 | ||
72a155b4 | 3790 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3791 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3792 | && (typecode == TYPE_CODE_STRUCT |
3793 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3794 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3795 | * TARGET_CHAR_BIT); |
46cac009 AC |
3796 | |
3797 | if (mips_debug) | |
3798 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3799 | argreg, | |
1a69e1e4 | 3800 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3801 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3802 | argreg++; |
3803 | ||
3804 | /* Prevent subsequent floating point arguments from | |
3805 | being passed in floating point registers. */ | |
74ed0bb4 | 3806 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
3807 | } |
3808 | ||
3809 | len -= partial_len; | |
3810 | val += partial_len; | |
3811 | ||
3812 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3813 | will copy the next parameter. |
46cac009 | 3814 | |
6d82d43b AC |
3815 | In older ABIs, the caller reserved space for |
3816 | registers that contained arguments. This was loosely | |
3817 | refered to as their "home". Consequently, space is | |
3818 | always allocated. */ | |
46cac009 | 3819 | |
1a69e1e4 | 3820 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3821 | } |
3822 | } | |
3823 | if (mips_debug) | |
3824 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3825 | } | |
3826 | ||
f10683bb | 3827 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3828 | |
46cac009 AC |
3829 | /* Return adjusted stack pointer. */ |
3830 | return sp; | |
3831 | } | |
3832 | ||
6d82d43b | 3833 | static enum return_value_convention |
c055b101 CV |
3834 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
3835 | struct type *type, struct regcache *regcache, | |
47a35522 | 3836 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3837 | { |
72a155b4 | 3838 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
3839 | |
3840 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3841 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3842 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3843 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3844 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3845 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3846 | { | |
3847 | /* A single-precision floating-point value. It fits in the | |
3848 | least significant part of FP0. */ | |
3849 | if (mips_debug) | |
3850 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3851 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3852 | gdbarch_num_regs (gdbarch) |
3853 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3854 | TYPE_LENGTH (type), |
72a155b4 | 3855 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3856 | readbuf, writebuf, 0); |
6d82d43b AC |
3857 | return RETURN_VALUE_REGISTER_CONVENTION; |
3858 | } | |
3859 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3860 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3861 | { | |
3862 | /* A double-precision floating-point value. The most | |
3863 | significant part goes in FP1, and the least significant in | |
3864 | FP0. */ | |
3865 | if (mips_debug) | |
3866 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 3867 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
3868 | { |
3869 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 3870 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3871 | gdbarch_num_regs (gdbarch) |
3872 | + mips_regnum (gdbarch)->fp0 + | |
3873 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3874 | readbuf, writebuf, 0); |
ba32f989 | 3875 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3876 | gdbarch_num_regs (gdbarch) |
3877 | + mips_regnum (gdbarch)->fp0 + 1, | |
3878 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3879 | readbuf, writebuf, 4); |
6d82d43b AC |
3880 | break; |
3881 | case BFD_ENDIAN_BIG: | |
ba32f989 | 3882 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3883 | gdbarch_num_regs (gdbarch) |
3884 | + mips_regnum (gdbarch)->fp0 + 1, | |
3885 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3886 | readbuf, writebuf, 0); |
ba32f989 | 3887 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3888 | gdbarch_num_regs (gdbarch) |
3889 | + mips_regnum (gdbarch)->fp0 + 0, | |
3890 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3891 | readbuf, writebuf, 4); |
6d82d43b AC |
3892 | break; |
3893 | default: | |
e2e0b3e5 | 3894 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3895 | } |
3896 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3897 | } | |
3898 | #if 0 | |
3899 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3900 | && TYPE_NFIELDS (type) <= 2 | |
3901 | && TYPE_NFIELDS (type) >= 1 | |
3902 | && ((TYPE_NFIELDS (type) == 1 | |
3903 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3904 | == TYPE_CODE_FLT)) | |
3905 | || (TYPE_NFIELDS (type) == 2 | |
3906 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3907 | == TYPE_CODE_FLT) | |
3908 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3909 | == TYPE_CODE_FLT))) | |
3910 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3911 | { | |
3912 | /* A struct that contains one or two floats. Each value is part | |
3913 | in the least significant part of their floating point | |
3914 | register.. */ | |
870cd05e | 3915 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3916 | int regnum; |
3917 | int field; | |
72a155b4 | 3918 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
3919 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3920 | { | |
3921 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3922 | / TARGET_CHAR_BIT); | |
3923 | if (mips_debug) | |
3924 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3925 | offset); | |
ba32f989 DJ |
3926 | mips_xfer_register (gdbarch, regcache, |
3927 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 3928 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 3929 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3930 | readbuf, writebuf, offset); |
6d82d43b AC |
3931 | } |
3932 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3933 | } | |
3934 | #endif | |
3935 | #if 0 | |
3936 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3937 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3938 | { | |
3939 | /* A structure or union. Extract the left justified value, | |
3940 | regardless of the byte order. I.e. DO NOT USE | |
3941 | mips_xfer_lower. */ | |
3942 | int offset; | |
3943 | int regnum; | |
4c7d22cb | 3944 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3945 | offset < TYPE_LENGTH (type); |
72a155b4 | 3946 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3947 | { |
72a155b4 | 3948 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3949 | if (offset + xfer > TYPE_LENGTH (type)) |
3950 | xfer = TYPE_LENGTH (type) - offset; | |
3951 | if (mips_debug) | |
3952 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3953 | offset, xfer, regnum); | |
ba32f989 DJ |
3954 | mips_xfer_register (gdbarch, regcache, |
3955 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
3956 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3957 | } | |
3958 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3959 | } | |
3960 | #endif | |
3961 | else | |
3962 | { | |
3963 | /* A scalar extract each part but least-significant-byte | |
3964 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3965 | the ISA. */ |
6d82d43b AC |
3966 | int offset; |
3967 | int regnum; | |
4c7d22cb | 3968 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3969 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3970 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3971 | { |
1a69e1e4 | 3972 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3973 | if (offset + xfer > TYPE_LENGTH (type)) |
3974 | xfer = TYPE_LENGTH (type) - offset; | |
3975 | if (mips_debug) | |
3976 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3977 | offset, xfer, regnum); | |
ba32f989 DJ |
3978 | mips_xfer_register (gdbarch, regcache, |
3979 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 3980 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3981 | readbuf, writebuf, offset); |
6d82d43b AC |
3982 | } |
3983 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3984 | } | |
3985 | } | |
3986 | ||
3987 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3988 | ABI. */ | |
46cac009 AC |
3989 | |
3990 | static CORE_ADDR | |
7d9b040b | 3991 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3992 | struct regcache *regcache, CORE_ADDR bp_addr, |
3993 | int nargs, | |
3994 | struct value **args, CORE_ADDR sp, | |
3995 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3996 | { |
3997 | int argreg; | |
3998 | int float_argreg; | |
3999 | int argnum; | |
4000 | int len = 0; | |
4001 | int stack_offset = 0; | |
480d3dd2 | 4002 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4003 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4004 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4005 | |
25ab4790 AC |
4006 | /* For shared libraries, "t9" needs to point at the function |
4007 | address. */ | |
4c7d22cb | 4008 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4009 | |
4010 | /* Set the return address register to point to the entry point of | |
4011 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4012 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4013 | |
46cac009 AC |
4014 | /* First ensure that the stack and structure return address (if any) |
4015 | are properly aligned. The stack has to be at least 64-bit | |
4016 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4017 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4018 | aligned, so we round to this widest known alignment. */ | |
4019 | ||
5b03f266 AC |
4020 | sp = align_down (sp, 16); |
4021 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4022 | |
4023 | /* Now make space on the stack for the args. */ | |
4024 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4025 | { |
4026 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4027 | int arglen = TYPE_LENGTH (arg_type); | |
4028 | ||
968b5391 | 4029 | /* Allocate space on the stack. */ |
1a69e1e4 | 4030 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4031 | } |
5b03f266 | 4032 | sp -= align_up (len, 16); |
46cac009 AC |
4033 | |
4034 | if (mips_debug) | |
6d82d43b | 4035 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4036 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4037 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4038 | |
4039 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4040 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4041 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4042 | |
4043 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4044 | if (struct_return) | |
4045 | { | |
4046 | if (mips_debug) | |
4047 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
4048 | "mips_o64_push_dummy_call: struct_return reg=%d %s\n", |
4049 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 4050 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4051 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4052 | } |
4053 | ||
4054 | /* Now load as many as possible of the first arguments into | |
4055 | registers, and push the rest onto the stack. Loop thru args | |
4056 | from first to last. */ | |
4057 | for (argnum = 0; argnum < nargs; argnum++) | |
4058 | { | |
47a35522 | 4059 | const gdb_byte *val; |
46cac009 | 4060 | struct value *arg = args[argnum]; |
4991999e | 4061 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4062 | int len = TYPE_LENGTH (arg_type); |
4063 | enum type_code typecode = TYPE_CODE (arg_type); | |
4064 | ||
4065 | if (mips_debug) | |
4066 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4067 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4068 | argnum + 1, len, (int) typecode); |
4069 | ||
47a35522 | 4070 | val = value_contents (arg); |
ebafbe83 | 4071 | |
ebafbe83 MS |
4072 | /* Floating point arguments passed in registers have to be |
4073 | treated specially. On 32-bit architectures, doubles | |
4074 | are passed in register pairs; the even register gets | |
4075 | the low word, and the odd register gets the high word. | |
4076 | On O32/O64, the first two floating point arguments are | |
4077 | also copied to general registers, because MIPS16 functions | |
4078 | don't use float registers for arguments. This duplication of | |
4079 | arguments in general registers can't hurt non-MIPS16 functions | |
4080 | because those registers are normally skipped. */ | |
4081 | ||
74ed0bb4 MD |
4082 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4083 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4084 | { |
e17a4113 | 4085 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4086 | if (mips_debug) |
4087 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4088 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4089 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4090 | if (mips_debug) |
4091 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4092 | argreg, phex (regval, len)); | |
9c9acae0 | 4093 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4094 | argreg++; |
ebafbe83 | 4095 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4096 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4097 | } |
4098 | else | |
4099 | { | |
4100 | /* Copy the argument to general registers or the stack in | |
4101 | register-sized pieces. Large arguments are split between | |
4102 | registers and stack. */ | |
1a69e1e4 | 4103 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4104 | are treated specially: Irix cc passes them in registers |
4105 | where gcc sometimes puts them on the stack. For maximum | |
4106 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4107 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4108 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4109 | while (len > 0) |
4110 | { | |
4111 | /* Remember if the argument was written to the stack. */ | |
4112 | int stack_used_p = 0; | |
1a69e1e4 | 4113 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4114 | |
4115 | if (mips_debug) | |
4116 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4117 | partial_len); | |
4118 | ||
4119 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4120 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4121 | || odd_sized_struct) |
ebafbe83 MS |
4122 | { |
4123 | /* Should shorter than int integer values be | |
4124 | promoted to int before being stored? */ | |
4125 | int longword_offset = 0; | |
4126 | CORE_ADDR addr; | |
4127 | stack_used_p = 1; | |
72a155b4 | 4128 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4129 | { |
1a69e1e4 DJ |
4130 | if ((typecode == TYPE_CODE_INT |
4131 | || typecode == TYPE_CODE_PTR | |
4132 | || typecode == TYPE_CODE_FLT) | |
4133 | && len <= 4) | |
4134 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4135 | } |
4136 | ||
4137 | if (mips_debug) | |
4138 | { | |
5af949e3 UW |
4139 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4140 | paddress (gdbarch, stack_offset)); | |
4141 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4142 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4143 | } |
4144 | ||
4145 | addr = sp + stack_offset + longword_offset; | |
4146 | ||
4147 | if (mips_debug) | |
4148 | { | |
4149 | int i; | |
5af949e3 UW |
4150 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4151 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4152 | for (i = 0; i < partial_len; i++) |
4153 | { | |
6d82d43b | 4154 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4155 | val[i] & 0xff); |
4156 | } | |
4157 | } | |
4158 | write_memory (addr, val, partial_len); | |
4159 | } | |
4160 | ||
4161 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4162 | structs may go thru BOTH paths. */ |
ebafbe83 | 4163 | /* Write this portion of the argument to a general |
6d82d43b | 4164 | purpose register. */ |
74ed0bb4 | 4165 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4166 | { |
e17a4113 UW |
4167 | LONGEST regval = extract_signed_integer (val, partial_len, |
4168 | byte_order); | |
4246e332 | 4169 | /* Value may need to be sign extended, because |
1b13c4f6 | 4170 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4171 | |
4172 | /* A non-floating-point argument being passed in a | |
4173 | general register. If a struct or union, and if | |
4174 | the remaining length is smaller than the register | |
4175 | size, we have to adjust the register value on | |
4176 | big endian targets. | |
4177 | ||
4178 | It does not seem to be necessary to do the | |
401835eb | 4179 | same for integral types. */ |
480d3dd2 | 4180 | |
72a155b4 | 4181 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4182 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4183 | && (typecode == TYPE_CODE_STRUCT |
4184 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4185 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4186 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4187 | |
4188 | if (mips_debug) | |
4189 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4190 | argreg, | |
1a69e1e4 | 4191 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4192 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4193 | argreg++; |
4194 | ||
4195 | /* Prevent subsequent floating point arguments from | |
4196 | being passed in floating point registers. */ | |
74ed0bb4 | 4197 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4198 | } |
4199 | ||
4200 | len -= partial_len; | |
4201 | val += partial_len; | |
4202 | ||
4203 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4204 | will copy the next parameter. |
ebafbe83 | 4205 | |
6d82d43b AC |
4206 | In older ABIs, the caller reserved space for |
4207 | registers that contained arguments. This was loosely | |
4208 | refered to as their "home". Consequently, space is | |
4209 | always allocated. */ | |
ebafbe83 | 4210 | |
1a69e1e4 | 4211 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4212 | } |
4213 | } | |
4214 | if (mips_debug) | |
4215 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4216 | } | |
4217 | ||
f10683bb | 4218 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4219 | |
ebafbe83 MS |
4220 | /* Return adjusted stack pointer. */ |
4221 | return sp; | |
4222 | } | |
4223 | ||
9c8fdbfa | 4224 | static enum return_value_convention |
c055b101 | 4225 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4226 | struct type *type, struct regcache *regcache, |
47a35522 | 4227 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4228 | { |
72a155b4 | 4229 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4230 | |
4231 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4232 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4233 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4234 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4235 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4236 | { |
4237 | /* A floating-point value. It fits in the least significant | |
4238 | part of FP0. */ | |
4239 | if (mips_debug) | |
4240 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4241 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4242 | gdbarch_num_regs (gdbarch) |
4243 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4244 | TYPE_LENGTH (type), |
72a155b4 | 4245 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4246 | readbuf, writebuf, 0); |
7a076fd2 FF |
4247 | return RETURN_VALUE_REGISTER_CONVENTION; |
4248 | } | |
4249 | else | |
4250 | { | |
4251 | /* A scalar extract each part but least-significant-byte | |
4252 | justified. */ | |
4253 | int offset; | |
4254 | int regnum; | |
4255 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4256 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4257 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4258 | { |
1a69e1e4 | 4259 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4260 | if (offset + xfer > TYPE_LENGTH (type)) |
4261 | xfer = TYPE_LENGTH (type) - offset; | |
4262 | if (mips_debug) | |
4263 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4264 | offset, xfer, regnum); | |
ba32f989 DJ |
4265 | mips_xfer_register (gdbarch, regcache, |
4266 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4267 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4268 | readbuf, writebuf, offset); |
7a076fd2 FF |
4269 | } |
4270 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4271 | } | |
6d82d43b AC |
4272 | } |
4273 | ||
dd824b04 DJ |
4274 | /* Floating point register management. |
4275 | ||
4276 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4277 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4278 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4279 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4280 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4281 | double precision floats into two 32-bit chunks and store them in | |
4282 | consecutive fp regs. To display 64-bit floats stored in this | |
4283 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4284 | Throw in user-configurable endianness and you have a real mess. | |
4285 | ||
4286 | The way this works is: | |
4287 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4288 | double-precision value will be split across two logical registers. | |
4289 | The lower-numbered logical register will hold the low-order bits, | |
4290 | regardless of the processor's endianness. | |
4291 | - If we are on a 64-bit processor, and we are looking for a | |
4292 | single-precision value, it will be in the low ordered bits | |
4293 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4294 | save slot in memory. | |
4295 | - If we are in 64-bit mode, everything is straightforward. | |
4296 | ||
4297 | Note that this code only deals with "live" registers at the top of the | |
4298 | stack. We will attempt to deal with saved registers later, when | |
4299 | the raw/cooked register interface is in place. (We need a general | |
4300 | interface that can deal with dynamic saved register sizes -- fp | |
4301 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4302 | and below). */ | |
4303 | ||
4304 | /* Copy a 32-bit single-precision value from the current frame | |
4305 | into rare_buffer. */ | |
4306 | ||
4307 | static void | |
e11c53d2 | 4308 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4309 | gdb_byte *rare_buffer) |
dd824b04 | 4310 | { |
72a155b4 UW |
4311 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4312 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4313 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4314 | |
e11c53d2 | 4315 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4316 | error (_("can't read register %d (%s)"), |
72a155b4 | 4317 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4318 | if (raw_size == 8) |
4319 | { | |
4320 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4321 | 32 bits. */ |
dd824b04 DJ |
4322 | int offset; |
4323 | ||
72a155b4 | 4324 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4325 | offset = 4; |
4326 | else | |
4327 | offset = 0; | |
4328 | ||
4329 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4330 | } | |
4331 | else | |
4332 | { | |
4333 | memcpy (rare_buffer, raw_buffer, 4); | |
4334 | } | |
4335 | } | |
4336 | ||
4337 | /* Copy a 64-bit double-precision value from the current frame into | |
4338 | rare_buffer. This may include getting half of it from the next | |
4339 | register. */ | |
4340 | ||
4341 | static void | |
e11c53d2 | 4342 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4343 | gdb_byte *rare_buffer) |
dd824b04 | 4344 | { |
72a155b4 UW |
4345 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4346 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4347 | |
9c9acae0 | 4348 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4349 | { |
4350 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4351 | all 64 bits. */ |
e11c53d2 | 4352 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4353 | error (_("can't read register %d (%s)"), |
72a155b4 | 4354 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4355 | } |
4356 | else | |
4357 | { | |
72a155b4 | 4358 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4359 | |
72a155b4 | 4360 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4361 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4362 | _("mips_read_fp_register_double: bad access to " |
4363 | "odd-numbered FP register")); | |
dd824b04 DJ |
4364 | |
4365 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4366 | each register. */ |
72a155b4 | 4367 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4368 | { |
e11c53d2 AC |
4369 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4370 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4371 | } |
361d1df0 | 4372 | else |
dd824b04 | 4373 | { |
e11c53d2 AC |
4374 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4375 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4376 | } |
4377 | } | |
4378 | } | |
4379 | ||
c906108c | 4380 | static void |
e11c53d2 AC |
4381 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4382 | int regnum) | |
c5aa993b | 4383 | { /* do values for FP (float) regs */ |
72a155b4 | 4384 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4385 | gdb_byte *raw_buffer; |
3903d437 AC |
4386 | double doub, flt1; /* doubles extracted from raw hex data */ |
4387 | int inv1, inv2; | |
c5aa993b | 4388 | |
72a155b4 | 4389 | raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)); |
c906108c | 4390 | |
72a155b4 | 4391 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4392 | fprintf_filtered (file, "%*s", |
72a155b4 | 4393 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4394 | ""); |
f0ef6b29 | 4395 | |
72a155b4 | 4396 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4397 | { |
79a45b7d TT |
4398 | struct value_print_options opts; |
4399 | ||
f0ef6b29 KB |
4400 | /* 4-byte registers: Print hex and floating. Also print even |
4401 | numbered registers as doubles. */ | |
e11c53d2 | 4402 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 | 4403 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer, &inv1); |
c5aa993b | 4404 | |
79a45b7d | 4405 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4406 | print_scalar_formatted (raw_buffer, |
4407 | builtin_type (gdbarch)->builtin_uint32, | |
4408 | &opts, 'w', file); | |
dd824b04 | 4409 | |
e11c53d2 | 4410 | fprintf_filtered (file, " flt: "); |
1adad886 | 4411 | if (inv1) |
e11c53d2 | 4412 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4413 | else |
e11c53d2 | 4414 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4415 | |
72a155b4 | 4416 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4417 | { |
e11c53d2 | 4418 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4419 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4420 | raw_buffer, &inv2); | |
1adad886 | 4421 | |
e11c53d2 | 4422 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4423 | if (inv2) |
e11c53d2 | 4424 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4425 | else |
e11c53d2 | 4426 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4427 | } |
c906108c SS |
4428 | } |
4429 | else | |
dd824b04 | 4430 | { |
79a45b7d TT |
4431 | struct value_print_options opts; |
4432 | ||
f0ef6b29 | 4433 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4434 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4435 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4436 | raw_buffer, &inv1); | |
c906108c | 4437 | |
e11c53d2 | 4438 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4439 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4440 | raw_buffer, &inv2); | |
f0ef6b29 | 4441 | |
79a45b7d | 4442 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4443 | print_scalar_formatted (raw_buffer, |
4444 | builtin_type (gdbarch)->builtin_uint64, | |
4445 | &opts, 'g', file); | |
f0ef6b29 | 4446 | |
e11c53d2 | 4447 | fprintf_filtered (file, " flt: "); |
1adad886 | 4448 | if (inv1) |
e11c53d2 | 4449 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4450 | else |
e11c53d2 | 4451 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4452 | |
e11c53d2 | 4453 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4454 | if (inv2) |
e11c53d2 | 4455 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4456 | else |
e11c53d2 | 4457 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4458 | } |
4459 | } | |
4460 | ||
4461 | static void | |
e11c53d2 | 4462 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4463 | int regnum) |
f0ef6b29 | 4464 | { |
a4b8ebc8 | 4465 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4466 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4467 | int offset; |
79a45b7d | 4468 | struct value_print_options opts; |
1adad886 | 4469 | |
7b9ee6a8 | 4470 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4471 | { |
e11c53d2 | 4472 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4473 | return; |
4474 | } | |
4475 | ||
4476 | /* Get the data in raw format. */ | |
e11c53d2 | 4477 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4478 | { |
c9f4d572 | 4479 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4480 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4481 | return; |
c906108c | 4482 | } |
f0ef6b29 | 4483 | |
72a155b4 | 4484 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4485 | |
4486 | /* The problem with printing numeric register names (r26, etc.) is that | |
4487 | the user can't use them on input. Probably the best solution is to | |
4488 | fix it so that either the numeric or the funky (a2, etc.) names | |
4489 | are accepted on input. */ | |
4490 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4491 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4492 | else |
e11c53d2 | 4493 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4494 | |
72a155b4 | 4495 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4496 | offset = |
72a155b4 | 4497 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
f0ef6b29 KB |
4498 | else |
4499 | offset = 0; | |
4500 | ||
79a45b7d | 4501 | get_formatted_print_options (&opts, 'x'); |
6d82d43b | 4502 | print_scalar_formatted (raw_buffer + offset, |
79a45b7d | 4503 | register_type (gdbarch, regnum), &opts, 0, |
6d82d43b | 4504 | file); |
c906108c SS |
4505 | } |
4506 | ||
f0ef6b29 KB |
4507 | /* Replacement for generic do_registers_info. |
4508 | Print regs in pretty columns. */ | |
4509 | ||
4510 | static int | |
e11c53d2 AC |
4511 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4512 | int regnum) | |
f0ef6b29 | 4513 | { |
e11c53d2 AC |
4514 | fprintf_filtered (file, " "); |
4515 | mips_print_fp_register (file, frame, regnum); | |
4516 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4517 | return regnum + 1; |
4518 | } | |
4519 | ||
4520 | ||
c906108c SS |
4521 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4522 | ||
4523 | static int | |
e11c53d2 | 4524 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4525 | int start_regnum) |
c906108c | 4526 | { |
a4b8ebc8 | 4527 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4528 | /* do values for GP (int) regs */ |
47a35522 | 4529 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4530 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4531 | int col, byte; |
a4b8ebc8 | 4532 | int regnum; |
c906108c SS |
4533 | |
4534 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4535 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4536 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4537 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4538 | regnum++) |
c906108c | 4539 | { |
72a155b4 | 4540 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4541 | continue; /* unused register */ |
7b9ee6a8 | 4542 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4543 | TYPE_CODE_FLT) |
c5aa993b | 4544 | break; /* end the row: reached FP register */ |
0cc93a06 | 4545 | /* Large registers are handled separately. */ |
72a155b4 | 4546 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4547 | { |
4548 | if (col > 0) | |
4549 | break; /* End the row before this register. */ | |
4550 | ||
4551 | /* Print this register on a row by itself. */ | |
4552 | mips_print_register (file, frame, regnum); | |
4553 | fprintf_filtered (file, "\n"); | |
4554 | return regnum + 1; | |
4555 | } | |
d05f6826 DJ |
4556 | if (col == 0) |
4557 | fprintf_filtered (file, " "); | |
6d82d43b | 4558 | fprintf_filtered (file, |
72a155b4 UW |
4559 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4560 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4561 | col++; |
4562 | } | |
d05f6826 DJ |
4563 | |
4564 | if (col == 0) | |
4565 | return regnum; | |
4566 | ||
a4b8ebc8 | 4567 | /* print the R0 to R31 names */ |
72a155b4 | 4568 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4569 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4570 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4571 | else |
4572 | fprintf_filtered (file, "\n "); | |
c906108c | 4573 | |
c906108c | 4574 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4575 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4576 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4577 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4578 | regnum++) |
c906108c | 4579 | { |
72a155b4 | 4580 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4581 | continue; /* unused register */ |
7b9ee6a8 | 4582 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4583 | TYPE_CODE_FLT) |
c5aa993b | 4584 | break; /* end row: reached FP register */ |
72a155b4 | 4585 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4586 | break; /* End row: large register. */ |
4587 | ||
c906108c | 4588 | /* OK: get the data in raw format. */ |
e11c53d2 | 4589 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4590 | error (_("can't read register %d (%s)"), |
72a155b4 | 4591 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4592 | /* pad small registers */ |
4246e332 | 4593 | for (byte = 0; |
72a155b4 UW |
4594 | byte < (mips_abi_regsize (gdbarch) |
4595 | - register_size (gdbarch, regnum)); byte++) | |
c906108c SS |
4596 | printf_filtered (" "); |
4597 | /* Now print the register value in hex, endian order. */ | |
72a155b4 | 4598 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4599 | for (byte = |
72a155b4 UW |
4600 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4601 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4602 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4603 | else |
72a155b4 | 4604 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4605 | byte >= 0; byte--) |
47a35522 | 4606 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4607 | fprintf_filtered (file, " "); |
c906108c SS |
4608 | col++; |
4609 | } | |
c5aa993b | 4610 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4611 | fprintf_filtered (file, "\n"); |
c906108c SS |
4612 | |
4613 | return regnum; | |
4614 | } | |
4615 | ||
4616 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4617 | ||
bf1f5b4c | 4618 | static void |
e11c53d2 AC |
4619 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4620 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4621 | { |
c5aa993b | 4622 | if (regnum != -1) /* do one specified register */ |
c906108c | 4623 | { |
72a155b4 UW |
4624 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4625 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4626 | error (_("Not a valid register for the current processor type")); |
c906108c | 4627 | |
0cc93a06 | 4628 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4629 | fprintf_filtered (file, "\n"); |
c906108c | 4630 | } |
c5aa993b JM |
4631 | else |
4632 | /* do all (or most) registers */ | |
c906108c | 4633 | { |
72a155b4 UW |
4634 | regnum = gdbarch_num_regs (gdbarch); |
4635 | while (regnum < gdbarch_num_regs (gdbarch) | |
4636 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4637 | { |
7b9ee6a8 | 4638 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4639 | TYPE_CODE_FLT) |
e11c53d2 AC |
4640 | { |
4641 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4642 | regnum = print_fp_register_row (file, frame, regnum); | |
4643 | else | |
4644 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4645 | } | |
c906108c | 4646 | else |
e11c53d2 | 4647 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4648 | } |
4649 | } | |
4650 | } | |
4651 | ||
c906108c SS |
4652 | /* Is this a branch with a delay slot? */ |
4653 | ||
c906108c | 4654 | static int |
acdb74a0 | 4655 | is_delayed (unsigned long insn) |
c906108c SS |
4656 | { |
4657 | int i; | |
4658 | for (i = 0; i < NUMOPCODES; ++i) | |
4659 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4660 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4661 | break; | |
4662 | return (i < NUMOPCODES | |
4663 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4664 | | INSN_COND_BRANCH_DELAY | |
4665 | | INSN_COND_BRANCH_LIKELY))); | |
4666 | } | |
4667 | ||
63807e1d | 4668 | static int |
3352ef37 AC |
4669 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4670 | struct frame_info *frame) | |
c906108c | 4671 | { |
e17a4113 | 4672 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 4673 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4674 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4675 | |
4676 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4677 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4678 | return 0; |
4679 | ||
06648491 MK |
4680 | if (!breakpoint_here_p (pc + 4)) |
4681 | return 0; | |
4682 | ||
3352ef37 AC |
4683 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4684 | /* If error reading memory, guess that it is not a delayed | |
4685 | branch. */ | |
c906108c | 4686 | return 0; |
e17a4113 | 4687 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
4688 | } |
4689 | ||
6d82d43b AC |
4690 | /* To skip prologues, I use this predicate. Returns either PC itself |
4691 | if the code at PC does not look like a function prologue; otherwise | |
4692 | returns an address that (if we're lucky) follows the prologue. If | |
4693 | LENIENT, then we must skip everything which is involved in setting | |
4694 | up the frame (it's OK to skip more, just so long as we don't skip | |
4695 | anything which might clobber the registers which are being saved. | |
4696 | We must skip more in the case where part of the prologue is in the | |
4697 | delay slot of a non-prologue instruction). */ | |
4698 | ||
4699 | static CORE_ADDR | |
6093d2eb | 4700 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4701 | { |
8b622e6a AC |
4702 | CORE_ADDR limit_pc; |
4703 | CORE_ADDR func_addr; | |
4704 | ||
6d82d43b AC |
4705 | /* See if we can determine the end of the prologue via the symbol table. |
4706 | If so, then return either PC, or the PC after the prologue, whichever | |
4707 | is greater. */ | |
8b622e6a AC |
4708 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4709 | { | |
d80b854b UW |
4710 | CORE_ADDR post_prologue_pc |
4711 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
4712 | if (post_prologue_pc != 0) |
4713 | return max (pc, post_prologue_pc); | |
4714 | } | |
6d82d43b AC |
4715 | |
4716 | /* Can't determine prologue from the symbol table, need to examine | |
4717 | instructions. */ | |
4718 | ||
98b4dd94 JB |
4719 | /* Find an upper limit on the function prologue using the debug |
4720 | information. If the debug information could not be used to provide | |
4721 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 4722 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
4723 | if (limit_pc == 0) |
4724 | limit_pc = pc + 100; /* Magic. */ | |
4725 | ||
0fe7e7c8 | 4726 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 4727 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 4728 | else |
e17a4113 | 4729 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
4730 | } |
4731 | ||
97ab0fdd MR |
4732 | /* Check whether the PC is in a function epilogue (32-bit version). |
4733 | This is a helper function for mips_in_function_epilogue_p. */ | |
4734 | static int | |
e17a4113 | 4735 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4736 | { |
4737 | CORE_ADDR func_addr = 0, func_end = 0; | |
4738 | ||
4739 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4740 | { | |
4741 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4742 | CORE_ADDR addr = func_end - 12; | |
4743 | ||
4744 | if (addr < func_addr + 4) | |
4745 | addr = func_addr + 4; | |
4746 | if (pc < addr) | |
4747 | return 0; | |
4748 | ||
4749 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4750 | { | |
4751 | unsigned long high_word; | |
4752 | unsigned long inst; | |
4753 | ||
e17a4113 | 4754 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4755 | high_word = (inst >> 16) & 0xffff; |
4756 | ||
4757 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4758 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4759 | && inst != 0x03e00008 /* jr $ra */ | |
4760 | && inst != 0x00000000) /* nop */ | |
4761 | return 0; | |
4762 | } | |
4763 | ||
4764 | return 1; | |
4765 | } | |
4766 | ||
4767 | return 0; | |
4768 | } | |
4769 | ||
4770 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4771 | This is a helper function for mips_in_function_epilogue_p. */ | |
4772 | static int | |
e17a4113 | 4773 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4774 | { |
4775 | CORE_ADDR func_addr = 0, func_end = 0; | |
4776 | ||
4777 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4778 | { | |
4779 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4780 | CORE_ADDR addr = func_end - 12; | |
4781 | ||
4782 | if (addr < func_addr + 4) | |
4783 | addr = func_addr + 4; | |
4784 | if (pc < addr) | |
4785 | return 0; | |
4786 | ||
4787 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4788 | { | |
4789 | unsigned short inst; | |
4790 | ||
e17a4113 | 4791 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4792 | |
4793 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4794 | continue; | |
4795 | ||
4796 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4797 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4798 | && inst != 0xe820 /* jr $ra */ | |
4799 | && inst != 0xe8a0 /* jrc $ra */ | |
4800 | && inst != 0x6500) /* nop */ | |
4801 | return 0; | |
4802 | } | |
4803 | ||
4804 | return 1; | |
4805 | } | |
4806 | ||
4807 | return 0; | |
4808 | } | |
4809 | ||
4810 | /* The epilogue is defined here as the area at the end of a function, | |
4811 | after an instruction which destroys the function's stack frame. */ | |
4812 | static int | |
4813 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4814 | { | |
4815 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 4816 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 4817 | else |
e17a4113 | 4818 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
4819 | } |
4820 | ||
a5ea2558 AC |
4821 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4822 | used for all MIPS-specific commands. */ | |
4823 | ||
a5ea2558 | 4824 | static void |
acdb74a0 | 4825 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4826 | { |
4827 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4828 | } | |
4829 | ||
a5ea2558 | 4830 | static void |
acdb74a0 | 4831 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4832 | { |
6d82d43b AC |
4833 | printf_unfiltered |
4834 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4835 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4836 | } | |
4837 | ||
c906108c SS |
4838 | /* Commands to show/set the MIPS FPU type. */ |
4839 | ||
c906108c | 4840 | static void |
acdb74a0 | 4841 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4842 | { |
c906108c | 4843 | char *fpu; |
6ca0852e | 4844 | |
1cf3db46 | 4845 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
4846 | { |
4847 | printf_unfiltered | |
4848 | ("The MIPS floating-point coprocessor is unknown " | |
4849 | "because the current architecture is not MIPS.\n"); | |
4850 | return; | |
4851 | } | |
4852 | ||
1cf3db46 | 4853 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
4854 | { |
4855 | case MIPS_FPU_SINGLE: | |
4856 | fpu = "single-precision"; | |
4857 | break; | |
4858 | case MIPS_FPU_DOUBLE: | |
4859 | fpu = "double-precision"; | |
4860 | break; | |
4861 | case MIPS_FPU_NONE: | |
4862 | fpu = "absent (none)"; | |
4863 | break; | |
93d56215 | 4864 | default: |
e2e0b3e5 | 4865 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4866 | } |
4867 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4868 | printf_unfiltered |
4869 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4870 | fpu); | |
c906108c | 4871 | else |
6d82d43b AC |
4872 | printf_unfiltered |
4873 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4874 | } |
4875 | ||
4876 | ||
c906108c | 4877 | static void |
acdb74a0 | 4878 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4879 | { |
6d82d43b AC |
4880 | printf_unfiltered |
4881 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4882 | show_mipsfpu_command (args, from_tty); |
4883 | } | |
4884 | ||
c906108c | 4885 | static void |
acdb74a0 | 4886 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4887 | { |
8d5838b5 AC |
4888 | struct gdbarch_info info; |
4889 | gdbarch_info_init (&info); | |
c906108c SS |
4890 | mips_fpu_type = MIPS_FPU_SINGLE; |
4891 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4892 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4893 | instead of relying on globals. Doing that would let generic code | |
4894 | handle the search for this specific architecture. */ | |
4895 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4896 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4897 | } |
4898 | ||
c906108c | 4899 | static void |
acdb74a0 | 4900 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4901 | { |
8d5838b5 AC |
4902 | struct gdbarch_info info; |
4903 | gdbarch_info_init (&info); | |
c906108c SS |
4904 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4905 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4906 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4907 | instead of relying on globals. Doing that would let generic code | |
4908 | handle the search for this specific architecture. */ | |
4909 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4910 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4911 | } |
4912 | ||
c906108c | 4913 | static void |
acdb74a0 | 4914 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4915 | { |
8d5838b5 AC |
4916 | struct gdbarch_info info; |
4917 | gdbarch_info_init (&info); | |
c906108c SS |
4918 | mips_fpu_type = MIPS_FPU_NONE; |
4919 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4920 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4921 | instead of relying on globals. Doing that would let generic code | |
4922 | handle the search for this specific architecture. */ | |
4923 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4924 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4925 | } |
4926 | ||
c906108c | 4927 | static void |
acdb74a0 | 4928 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4929 | { |
4930 | mips_fpu_type_auto = 1; | |
4931 | } | |
4932 | ||
c906108c | 4933 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4934 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4935 | the relevant processor still exists (it dates back to '94) and | |
4936 | secondly this is not the way to do this. The processor type should | |
4937 | be set by forcing an architecture change. */ | |
c906108c | 4938 | |
691c0433 AC |
4939 | void |
4940 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4941 | { |
bb486190 UW |
4942 | struct regcache *regcache = get_current_regcache (); |
4943 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
4944 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 4945 | ULONGEST prid; |
c906108c | 4946 | |
bb486190 | 4947 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 4948 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4949 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4950 | } |
4951 | ||
4952 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4953 | callable as an sfunc. */ | |
4954 | ||
4955 | static void | |
acdb74a0 AC |
4956 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4957 | struct cmd_list_element *c) | |
c906108c SS |
4958 | { |
4959 | reinit_frame_cache (); | |
4960 | } | |
4961 | ||
a89aa300 AC |
4962 | static int |
4963 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4964 | { |
d31431ed AC |
4965 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4966 | disassembler needs to be able to locally determine the ISA, and | |
4967 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4968 | work. */ | |
ec4045ea AC |
4969 | if (mips_pc_is_mips16 (memaddr)) |
4970 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4971 | |
4972 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4973 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4974 | |
e5ab0dce | 4975 | /* Set the disassembler options. */ |
9dae60cc | 4976 | if (!info->disassembler_options) |
e5ab0dce AC |
4977 | /* This string is not recognized explicitly by the disassembler, |
4978 | but it tells the disassembler to not try to guess the ABI from | |
4979 | the bfd elf headers, such that, if the user overrides the ABI | |
4980 | of a program linked as NewABI, the disassembly will follow the | |
4981 | register naming conventions specified by the user. */ | |
4982 | info->disassembler_options = "gpr-names=32"; | |
4983 | ||
c906108c | 4984 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 4985 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
4986 | return print_insn_big_mips (memaddr, info); |
4987 | else | |
4988 | return print_insn_little_mips (memaddr, info); | |
4989 | } | |
4990 | ||
9dae60cc UW |
4991 | static int |
4992 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
4993 | { | |
4994 | /* Set up the disassembler info, so that we get the right | |
4995 | register names from libopcodes. */ | |
4996 | info->disassembler_options = "gpr-names=n32"; | |
4997 | info->flavour = bfd_target_elf_flavour; | |
4998 | ||
4999 | return gdb_print_insn_mips (memaddr, info); | |
5000 | } | |
5001 | ||
5002 | static int | |
5003 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5004 | { | |
5005 | /* Set up the disassembler info, so that we get the right | |
5006 | register names from libopcodes. */ | |
5007 | info->disassembler_options = "gpr-names=64"; | |
5008 | info->flavour = bfd_target_elf_flavour; | |
5009 | ||
5010 | return gdb_print_insn_mips (memaddr, info); | |
5011 | } | |
5012 | ||
3b3b875c UW |
5013 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
5014 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
5015 | It returns a pointer to a string of bytes that encode a breakpoint | |
5016 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
5017 | necessary) to point to the actual memory location where the breakpoint | |
5018 | should be inserted. */ | |
c906108c | 5019 | |
47a35522 | 5020 | static const gdb_byte * |
67d57894 | 5021 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5022 | { |
67d57894 | 5023 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5024 | { |
0fe7e7c8 | 5025 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5026 | { |
47a35522 | 5027 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5028 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5029 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5030 | return mips16_big_breakpoint; |
5031 | } | |
5032 | else | |
5033 | { | |
aaab4dba AC |
5034 | /* The IDT board uses an unusual breakpoint value, and |
5035 | sometimes gets confused when it sees the usual MIPS | |
5036 | breakpoint instruction. */ | |
47a35522 MK |
5037 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5038 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5039 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5040 | |
c5aa993b | 5041 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5042 | |
5043 | if (strcmp (target_shortname, "mips") == 0) | |
5044 | return idt_big_breakpoint; | |
5045 | else if (strcmp (target_shortname, "ddb") == 0 | |
5046 | || strcmp (target_shortname, "pmon") == 0 | |
5047 | || strcmp (target_shortname, "lsi") == 0) | |
5048 | return pmon_big_breakpoint; | |
5049 | else | |
5050 | return big_breakpoint; | |
5051 | } | |
5052 | } | |
5053 | else | |
5054 | { | |
0fe7e7c8 | 5055 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5056 | { |
47a35522 | 5057 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5058 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5059 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5060 | return mips16_little_breakpoint; |
5061 | } | |
5062 | else | |
5063 | { | |
47a35522 MK |
5064 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5065 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5066 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5067 | |
c5aa993b | 5068 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5069 | |
5070 | if (strcmp (target_shortname, "mips") == 0) | |
5071 | return idt_little_breakpoint; | |
5072 | else if (strcmp (target_shortname, "ddb") == 0 | |
5073 | || strcmp (target_shortname, "pmon") == 0 | |
5074 | || strcmp (target_shortname, "lsi") == 0) | |
5075 | return pmon_little_breakpoint; | |
5076 | else | |
5077 | return little_breakpoint; | |
5078 | } | |
5079 | } | |
5080 | } | |
5081 | ||
5082 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5083 | PC, which is either the callee or the caller. There are several | |
5084 | cases which must be handled: | |
5085 | ||
5086 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5087 | target PC is in $31 ($ra). |
c906108c | 5088 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5089 | and the target PC is in $2. |
c906108c | 5090 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5091 | before the jal instruction, this is effectively a call stub |
5092 | and the the target PC is in $2. Otherwise this is effectively | |
5093 | a return stub and the target PC is in $18. | |
c906108c SS |
5094 | |
5095 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5096 | gory details. */ |
c906108c | 5097 | |
757a7cc6 | 5098 | static CORE_ADDR |
db5f024e | 5099 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5100 | { |
e17a4113 | 5101 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c SS |
5102 | char *name; |
5103 | CORE_ADDR start_addr; | |
5104 | ||
5105 | /* Find the starting address and name of the function containing the PC. */ | |
5106 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5107 | return 0; | |
5108 | ||
5109 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5110 | target PC is in $31 ($ra). */ | |
5111 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5112 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5113 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5114 | |
5115 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5116 | { | |
5117 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5118 | and the target PC is in $2. */ | |
5119 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5120 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5121 | |
5122 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5123 | before the jal instruction, this is effectively a call stub |
5124 | and the the target PC is in $2. Otherwise this is effectively | |
5125 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5126 | else if (name[19] == 's' || name[19] == 'd') |
5127 | { | |
5128 | if (pc == start_addr) | |
5129 | { | |
5130 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5131 | stub. Such a stub for a function bar might have a name |
5132 | like __fn_stub_bar, and might look like this: | |
5133 | mfc1 $4,$f13 | |
5134 | mfc1 $5,$f12 | |
5135 | mfc1 $6,$f15 | |
5136 | mfc1 $7,$f14 | |
5137 | la $1,bar (becomes a lui/addiu pair) | |
5138 | jr $1 | |
5139 | So scan down to the lui/addi and extract the target | |
5140 | address from those two instructions. */ | |
c906108c | 5141 | |
52f729a7 | 5142 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 5143 | ULONGEST inst; |
c906108c SS |
5144 | int i; |
5145 | ||
5146 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5147 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5148 | 0) | |
c906108c SS |
5149 | return target_pc; |
5150 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5151 | && strcmp (name, "etext") != 0 | |
5152 | && strcmp (name, "_etext") != 0) | |
5153 | return target_pc; | |
5154 | ||
5155 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5156 | The limit on the search is arbitrarily set to 20 |
5157 | instructions. FIXME. */ | |
95ac2dcf | 5158 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5159 | { |
e17a4113 | 5160 | inst = mips_fetch_instruction (gdbarch, target_pc); |
c5aa993b JM |
5161 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
5162 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5163 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5164 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5165 | } |
5166 | ||
5167 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5168 | return target_pc; | |
5169 | } | |
5170 | else | |
5171 | /* This is the 'return' part of a call stub. The return | |
5172 | address is in $r18. */ | |
52f729a7 | 5173 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5174 | } |
5175 | } | |
c5aa993b | 5176 | return 0; /* not a stub */ |
c906108c SS |
5177 | } |
5178 | ||
db5f024e DJ |
5179 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5180 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5181 | so that $t9 has the correct value at function entry. */ | |
5182 | ||
5183 | static CORE_ADDR | |
5184 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5185 | { | |
e17a4113 UW |
5186 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5187 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
5188 | struct minimal_symbol *msym; |
5189 | int i; | |
5190 | gdb_byte stub_code[16]; | |
5191 | int32_t stub_words[4]; | |
5192 | ||
5193 | /* The stub for foo is named ".pic.foo", and is either two | |
5194 | instructions inserted before foo or a three instruction sequence | |
5195 | which jumps to foo. */ | |
5196 | msym = lookup_minimal_symbol_by_pc (pc); | |
5197 | if (msym == NULL | |
5198 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5199 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5200 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5201 | return 0; | |
5202 | ||
5203 | /* A two-instruction header. */ | |
5204 | if (MSYMBOL_SIZE (msym) == 8) | |
5205 | return pc + 8; | |
5206 | ||
5207 | /* A three-instruction (plus delay slot) trampoline. */ | |
5208 | if (MSYMBOL_SIZE (msym) == 16) | |
5209 | { | |
5210 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5211 | return 0; | |
5212 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
5213 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
5214 | 4, byte_order); | |
db5f024e DJ |
5215 | |
5216 | /* A stub contains these instructions: | |
5217 | lui t9, %hi(target) | |
5218 | j target | |
5219 | addiu t9, t9, %lo(target) | |
5220 | nop | |
5221 | ||
5222 | This works even for N64, since stubs are only generated with | |
5223 | -msym32. */ | |
5224 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5225 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5226 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5227 | && stub_words[3] == 0x00000000) | |
5228 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5229 | + (stub_words[2] & 0x0000ffff)); | |
5230 | } | |
5231 | ||
5232 | /* Not a recognized stub. */ | |
5233 | return 0; | |
5234 | } | |
5235 | ||
5236 | static CORE_ADDR | |
5237 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5238 | { | |
5239 | CORE_ADDR target_pc; | |
5240 | ||
5241 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5242 | if (target_pc) | |
5243 | return target_pc; | |
5244 | ||
5245 | target_pc = find_solib_trampoline_target (frame, pc); | |
5246 | if (target_pc) | |
5247 | return target_pc; | |
5248 | ||
5249 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5250 | if (target_pc) | |
5251 | return target_pc; | |
5252 | ||
5253 | return 0; | |
5254 | } | |
5255 | ||
a4b8ebc8 | 5256 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5257 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5258 | |
5259 | static int | |
d3f73121 | 5260 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5261 | { |
a4b8ebc8 | 5262 | int regnum; |
2f38ef89 | 5263 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5264 | regnum = num; |
2f38ef89 | 5265 | else if (num >= 38 && num < 70) |
d3f73121 | 5266 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5267 | else if (num == 70) |
d3f73121 | 5268 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5269 | else if (num == 71) |
d3f73121 | 5270 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5271 | else |
a4b8ebc8 AC |
5272 | /* This will hopefully (eventually) provoke a warning. Should |
5273 | we be calling complaint() here? */ | |
d3f73121 MD |
5274 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5275 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5276 | } |
5277 | ||
2f38ef89 | 5278 | |
a4b8ebc8 | 5279 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5280 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5281 | |
5282 | static int | |
d3f73121 | 5283 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5284 | { |
a4b8ebc8 | 5285 | int regnum; |
2f38ef89 | 5286 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5287 | regnum = num; |
2f38ef89 | 5288 | else if (num >= 32 && num < 64) |
d3f73121 | 5289 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5290 | else if (num == 64) |
d3f73121 | 5291 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5292 | else if (num == 65) |
d3f73121 | 5293 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5294 | else |
a4b8ebc8 AC |
5295 | /* This will hopefully (eventually) provoke a warning. Should we |
5296 | be calling complaint() here? */ | |
d3f73121 MD |
5297 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5298 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5299 | } |
5300 | ||
5301 | static int | |
e7faf938 | 5302 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5303 | { |
5304 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5305 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5306 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5307 | decide if it is valid. Should instead define a standard sim/gdb | |
5308 | register numbering scheme. */ | |
e7faf938 MD |
5309 | if (gdbarch_register_name (gdbarch, |
5310 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5311 | && gdbarch_register_name (gdbarch, | |
5312 | gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5313 | return regnum; |
5314 | else | |
6d82d43b | 5315 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5316 | } |
5317 | ||
2f38ef89 | 5318 | |
4844f454 CV |
5319 | /* Convert an integer into an address. Extracting the value signed |
5320 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5321 | |
5322 | static CORE_ADDR | |
79dd2d24 | 5323 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5324 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5325 | { |
e17a4113 UW |
5326 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
5327 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
5328 | } |
5329 | ||
82e91389 DJ |
5330 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5331 | than most other architectures; we just need to be explicit about it, | |
5332 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5333 | an assertion failure. */ | |
5334 | ||
5335 | static void | |
a54fba4c MD |
5336 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5337 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5338 | { |
5339 | *reg = MIPS_SP_REGNUM; | |
5340 | *offset = 0; | |
5341 | } | |
5342 | ||
caaa3122 DJ |
5343 | static void |
5344 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5345 | { | |
5346 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5347 | const char *name = bfd_get_section_name (abfd, sect); | |
5348 | ||
5349 | if (*abip != MIPS_ABI_UNKNOWN) | |
5350 | return; | |
5351 | ||
5352 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5353 | return; | |
5354 | ||
5355 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5356 | *abip = MIPS_ABI_O32; | |
5357 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5358 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5359 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5360 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5361 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5362 | *abip = MIPS_ABI_O64; | |
5363 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5364 | *abip = MIPS_ABI_EABI32; | |
5365 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5366 | *abip = MIPS_ABI_EABI64; | |
5367 | else | |
8a3fe4f8 | 5368 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5369 | } |
5370 | ||
22e47e37 FF |
5371 | static void |
5372 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5373 | { | |
5374 | int *lbp = (int *) obj; | |
5375 | const char *name = bfd_get_section_name (abfd, sect); | |
5376 | ||
5377 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5378 | *lbp = 32; | |
5379 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5380 | *lbp = 64; | |
5381 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5382 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5383 | } | |
5384 | ||
2e4ebe70 DJ |
5385 | static enum mips_abi |
5386 | global_mips_abi (void) | |
5387 | { | |
5388 | int i; | |
5389 | ||
5390 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5391 | if (mips_abi_strings[i] == mips_abi_string) | |
5392 | return (enum mips_abi) i; | |
5393 | ||
e2e0b3e5 | 5394 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5395 | } |
5396 | ||
29709017 DJ |
5397 | static void |
5398 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5399 | { | |
29709017 DJ |
5400 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5401 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5402 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5403 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5404 | |
5405 | /* If the size matches the full set of registers GDB traditionally | |
5406 | knows about, including floating point, for either 32-bit or | |
5407 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5408 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5409 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5410 | |
5411 | /* Otherwise we don't have a useful guess. */ | |
5412 | } | |
5413 | ||
f8b73d13 DJ |
5414 | static struct value * |
5415 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5416 | { | |
5417 | const int *reg_p = baton; | |
5418 | return value_of_register (*reg_p, frame); | |
5419 | } | |
5420 | ||
c2d11a7d | 5421 | static struct gdbarch * |
6d82d43b | 5422 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5423 | { |
c2d11a7d JM |
5424 | struct gdbarch *gdbarch; |
5425 | struct gdbarch_tdep *tdep; | |
5426 | int elf_flags; | |
2e4ebe70 | 5427 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5428 | int i, num_regs; |
8d5838b5 | 5429 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5430 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5431 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5432 | |
5433 | /* Check any target description for validity. */ | |
5434 | if (tdesc_has_registers (info.target_desc)) | |
5435 | { | |
5436 | static const char *const mips_gprs[] = { | |
5437 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5438 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5439 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5440 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5441 | }; | |
5442 | static const char *const mips_fprs[] = { | |
5443 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5444 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5445 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5446 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5447 | }; | |
5448 | ||
5449 | const struct tdesc_feature *feature; | |
5450 | int valid_p; | |
5451 | ||
5452 | feature = tdesc_find_feature (info.target_desc, | |
5453 | "org.gnu.gdb.mips.cpu"); | |
5454 | if (feature == NULL) | |
5455 | return NULL; | |
5456 | ||
5457 | tdesc_data = tdesc_data_alloc (); | |
5458 | ||
5459 | valid_p = 1; | |
5460 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5461 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5462 | mips_gprs[i]); | |
5463 | ||
5464 | ||
5465 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5466 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5467 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5468 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5469 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5470 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5471 | ||
5472 | if (!valid_p) | |
5473 | { | |
5474 | tdesc_data_cleanup (tdesc_data); | |
5475 | return NULL; | |
5476 | } | |
5477 | ||
5478 | feature = tdesc_find_feature (info.target_desc, | |
5479 | "org.gnu.gdb.mips.cp0"); | |
5480 | if (feature == NULL) | |
5481 | { | |
5482 | tdesc_data_cleanup (tdesc_data); | |
5483 | return NULL; | |
5484 | } | |
5485 | ||
5486 | valid_p = 1; | |
5487 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5488 | MIPS_EMBED_BADVADDR_REGNUM, | |
5489 | "badvaddr"); | |
5490 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5491 | MIPS_PS_REGNUM, "status"); | |
5492 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5493 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5494 | ||
5495 | if (!valid_p) | |
5496 | { | |
5497 | tdesc_data_cleanup (tdesc_data); | |
5498 | return NULL; | |
5499 | } | |
5500 | ||
5501 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5502 | backend is not prepared for that, though. */ | |
5503 | feature = tdesc_find_feature (info.target_desc, | |
5504 | "org.gnu.gdb.mips.fpu"); | |
5505 | if (feature == NULL) | |
5506 | { | |
5507 | tdesc_data_cleanup (tdesc_data); | |
5508 | return NULL; | |
5509 | } | |
5510 | ||
5511 | valid_p = 1; | |
5512 | for (i = 0; i < 32; i++) | |
5513 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5514 | i + MIPS_EMBED_FP0_REGNUM, | |
5515 | mips_fprs[i]); | |
5516 | ||
5517 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5518 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5519 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5520 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5521 | ||
5522 | if (!valid_p) | |
5523 | { | |
5524 | tdesc_data_cleanup (tdesc_data); | |
5525 | return NULL; | |
5526 | } | |
5527 | ||
5528 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5529 | when only 32-bit registers are provided. */ | |
5530 | } | |
c2d11a7d | 5531 | |
ec03c1ac AC |
5532 | /* First of all, extract the elf_flags, if available. */ |
5533 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5534 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5535 | else if (arches != NULL) |
5536 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5537 | else |
5538 | elf_flags = 0; | |
5539 | if (gdbarch_debug) | |
5540 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5541 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5542 | |
102182a9 | 5543 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5544 | switch ((elf_flags & EF_MIPS_ABI)) |
5545 | { | |
5546 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5547 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5548 | break; |
5549 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5550 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5551 | break; |
5552 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5553 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5554 | break; |
5555 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5556 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5557 | break; |
5558 | default: | |
acdb74a0 | 5559 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5560 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5561 | else |
ec03c1ac | 5562 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5563 | break; |
5564 | } | |
acdb74a0 | 5565 | |
caaa3122 | 5566 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5567 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5568 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5569 | |
dc305454 | 5570 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5571 | MIPS architecture (if there is one). */ |
5572 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5573 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5574 | |
32a6503c | 5575 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5576 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5577 | && info.bfd_arch_info != NULL |
5578 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5579 | { | |
5580 | switch (info.bfd_arch_info->mach) | |
5581 | { | |
5582 | case bfd_mach_mips3900: | |
ec03c1ac | 5583 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5584 | break; |
5585 | case bfd_mach_mips4100: | |
5586 | case bfd_mach_mips5000: | |
ec03c1ac | 5587 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5588 | break; |
1d06468c EZ |
5589 | case bfd_mach_mips8000: |
5590 | case bfd_mach_mips10000: | |
32a6503c KB |
5591 | /* On Irix, ELF64 executables use the N64 ABI. The |
5592 | pseudo-sections which describe the ABI aren't present | |
5593 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5594 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5595 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5596 | found_abi = MIPS_ABI_N64; |
28d169de | 5597 | else |
ec03c1ac | 5598 | found_abi = MIPS_ABI_N32; |
1d06468c | 5599 | break; |
bf64bfd6 AC |
5600 | } |
5601 | } | |
2e4ebe70 | 5602 | |
26c53e50 DJ |
5603 | /* Default 64-bit objects to N64 instead of O32. */ |
5604 | if (found_abi == MIPS_ABI_UNKNOWN | |
5605 | && info.abfd != NULL | |
5606 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5607 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5608 | found_abi = MIPS_ABI_N64; | |
5609 | ||
ec03c1ac AC |
5610 | if (gdbarch_debug) |
5611 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5612 | found_abi); | |
5613 | ||
5614 | /* What has the user specified from the command line? */ | |
5615 | wanted_abi = global_mips_abi (); | |
5616 | if (gdbarch_debug) | |
5617 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5618 | wanted_abi); | |
2e4ebe70 DJ |
5619 | |
5620 | /* Now that we have found what the ABI for this binary would be, | |
5621 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5622 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5623 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5624 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5625 | mips_abi = found_abi; | |
5626 | else | |
5627 | mips_abi = MIPS_ABI_O32; | |
5628 | if (gdbarch_debug) | |
5629 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5630 | mips_abi); | |
2e4ebe70 | 5631 | |
ec03c1ac | 5632 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5633 | if (gdbarch_debug) |
ec03c1ac AC |
5634 | fprintf_unfiltered (gdb_stdlog, |
5635 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5636 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5637 | |
8d5838b5 | 5638 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5639 | #ifdef HAVE_ELF |
5640 | if (info.abfd | |
5641 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5642 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5643 | Tag_GNU_MIPS_ABI_FP); | |
5644 | #endif /* HAVE_ELF */ | |
5645 | ||
8d5838b5 AC |
5646 | if (!mips_fpu_type_auto) |
5647 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5648 | else if (elf_fpu_type != 0) |
5649 | { | |
5650 | switch (elf_fpu_type) | |
5651 | { | |
5652 | case 1: | |
5653 | fpu_type = MIPS_FPU_DOUBLE; | |
5654 | break; | |
5655 | case 2: | |
5656 | fpu_type = MIPS_FPU_SINGLE; | |
5657 | break; | |
5658 | case 3: | |
5659 | default: | |
5660 | /* Soft float or unknown. */ | |
5661 | fpu_type = MIPS_FPU_NONE; | |
5662 | break; | |
5663 | } | |
5664 | } | |
8d5838b5 AC |
5665 | else if (info.bfd_arch_info != NULL |
5666 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5667 | switch (info.bfd_arch_info->mach) | |
5668 | { | |
5669 | case bfd_mach_mips3900: | |
5670 | case bfd_mach_mips4100: | |
5671 | case bfd_mach_mips4111: | |
a9d61c86 | 5672 | case bfd_mach_mips4120: |
8d5838b5 AC |
5673 | fpu_type = MIPS_FPU_NONE; |
5674 | break; | |
5675 | case bfd_mach_mips4650: | |
5676 | fpu_type = MIPS_FPU_SINGLE; | |
5677 | break; | |
5678 | default: | |
5679 | fpu_type = MIPS_FPU_DOUBLE; | |
5680 | break; | |
5681 | } | |
5682 | else if (arches != NULL) | |
5683 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5684 | else | |
5685 | fpu_type = MIPS_FPU_DOUBLE; | |
5686 | if (gdbarch_debug) | |
5687 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5688 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5689 | |
29709017 DJ |
5690 | /* Check for blatant incompatibilities. */ |
5691 | ||
5692 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5693 | ABI. */ | |
5694 | if (info.target_desc | |
5695 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5696 | && mips_abi != MIPS_ABI_EABI32 | |
5697 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5698 | { |
5699 | if (tdesc_data != NULL) | |
5700 | tdesc_data_cleanup (tdesc_data); | |
5701 | return NULL; | |
5702 | } | |
29709017 | 5703 | |
c2d11a7d JM |
5704 | /* try to find a pre-existing architecture */ |
5705 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5706 | arches != NULL; | |
5707 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5708 | { | |
5709 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5710 | using. */ |
9103eae0 | 5711 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5712 | continue; |
9103eae0 | 5713 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5714 | continue; |
719ec221 AC |
5715 | /* Need to be pedantic about which register virtual size is |
5716 | used. */ | |
5717 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5718 | != mips64_transfers_32bit_regs_p) | |
5719 | continue; | |
8d5838b5 AC |
5720 | /* Be pedantic about which FPU is selected. */ |
5721 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5722 | continue; | |
f8b73d13 DJ |
5723 | |
5724 | if (tdesc_data != NULL) | |
5725 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5726 | return arches->gdbarch; |
c2d11a7d JM |
5727 | } |
5728 | ||
102182a9 | 5729 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5730 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5731 | gdbarch = gdbarch_alloc (&info, tdep); | |
5732 | tdep->elf_flags = elf_flags; | |
719ec221 | 5733 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5734 | tdep->found_abi = found_abi; |
5735 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5736 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5737 | tdep->register_size_valid_p = 0; |
5738 | tdep->register_size = 0; | |
5739 | ||
5740 | if (info.target_desc) | |
5741 | { | |
5742 | /* Some useful properties can be inferred from the target. */ | |
5743 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5744 | { | |
5745 | tdep->register_size_valid_p = 1; | |
5746 | tdep->register_size = 4; | |
5747 | } | |
5748 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5749 | { | |
5750 | tdep->register_size_valid_p = 1; | |
5751 | tdep->register_size = 8; | |
5752 | } | |
5753 | } | |
c2d11a7d | 5754 | |
102182a9 | 5755 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5756 | set_gdbarch_short_bit (gdbarch, 16); |
5757 | set_gdbarch_int_bit (gdbarch, 32); | |
5758 | set_gdbarch_float_bit (gdbarch, 32); | |
5759 | set_gdbarch_double_bit (gdbarch, 64); | |
5760 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5761 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5762 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5763 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5764 | |
6d82d43b | 5765 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5766 | mips_elf_make_msymbol_special); |
5767 | ||
16e109ca | 5768 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5769 | { |
16e109ca | 5770 | const char **reg_names; |
56cea623 AC |
5771 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5772 | struct mips_regnum); | |
f8b73d13 DJ |
5773 | if (tdesc_has_registers (info.target_desc)) |
5774 | { | |
5775 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5776 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5777 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5778 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5779 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5780 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5781 | regnum->fp_control_status = 70; | |
5782 | regnum->fp_implementation_revision = 71; | |
5783 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5784 | reg_names = NULL; | |
5785 | } | |
5786 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5787 | { |
5788 | regnum->fp0 = 32; | |
5789 | regnum->pc = 64; | |
5790 | regnum->cause = 65; | |
5791 | regnum->badvaddr = 66; | |
5792 | regnum->hi = 67; | |
5793 | regnum->lo = 68; | |
5794 | regnum->fp_control_status = 69; | |
5795 | regnum->fp_implementation_revision = 70; | |
5796 | num_regs = 71; | |
16e109ca | 5797 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5798 | } |
5799 | else | |
5800 | { | |
5801 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5802 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5803 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5804 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5805 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5806 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5807 | regnum->fp_control_status = 70; | |
5808 | regnum->fp_implementation_revision = 71; | |
5809 | num_regs = 90; | |
16e109ca AC |
5810 | if (info.bfd_arch_info != NULL |
5811 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5812 | reg_names = mips_tx39_reg_names; | |
5813 | else | |
5814 | reg_names = mips_generic_reg_names; | |
56cea623 | 5815 | } |
3e8c568d | 5816 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
fb14de7b | 5817 | replaced by gdbarch_read_pc? */ |
f10683bb MH |
5818 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5819 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5820 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5821 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5822 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5823 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5824 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5825 | tdep->mips_processor_reg_names = reg_names; |
5826 | tdep->regnum = regnum; | |
56cea623 | 5827 | } |
fe29b929 | 5828 | |
0dadbba0 | 5829 | switch (mips_abi) |
c2d11a7d | 5830 | { |
0dadbba0 | 5831 | case MIPS_ABI_O32: |
25ab4790 | 5832 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5833 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5834 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5835 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5836 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5837 | set_gdbarch_long_bit (gdbarch, 32); |
5838 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5839 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5840 | break; | |
0dadbba0 | 5841 | case MIPS_ABI_O64: |
25ab4790 | 5842 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5843 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5844 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5845 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5846 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5847 | set_gdbarch_long_bit (gdbarch, 32); |
5848 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5849 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5850 | break; | |
0dadbba0 | 5851 | case MIPS_ABI_EABI32: |
25ab4790 | 5852 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5853 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5854 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5855 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5856 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5857 | set_gdbarch_long_bit (gdbarch, 32); |
5858 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5859 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5860 | break; | |
0dadbba0 | 5861 | case MIPS_ABI_EABI64: |
25ab4790 | 5862 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5863 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5864 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5865 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5866 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5867 | set_gdbarch_long_bit (gdbarch, 64); |
5868 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5869 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5870 | break; | |
0dadbba0 | 5871 | case MIPS_ABI_N32: |
25ab4790 | 5872 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5873 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5874 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5875 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5876 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5877 | set_gdbarch_long_bit (gdbarch, 32); |
5878 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5879 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5880 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5881 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
5882 | break; |
5883 | case MIPS_ABI_N64: | |
25ab4790 | 5884 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5885 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5886 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5887 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5888 | tdep->default_mask_address_p = 0; |
5889 | set_gdbarch_long_bit (gdbarch, 64); | |
5890 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5891 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5892 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5893 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 5894 | break; |
c2d11a7d | 5895 | default: |
e2e0b3e5 | 5896 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5897 | } |
5898 | ||
22e47e37 FF |
5899 | /* GCC creates a pseudo-section whose name specifies the size of |
5900 | longs, since -mlong32 or -mlong64 may be used independent of | |
5901 | other options. How those options affect pointer sizes is ABI and | |
5902 | architecture dependent, so use them to override the default sizes | |
5903 | set by the ABI. This table shows the relationship between ABI, | |
5904 | -mlongXX, and size of pointers: | |
5905 | ||
5906 | ABI -mlongXX ptr bits | |
5907 | --- -------- -------- | |
5908 | o32 32 32 | |
5909 | o32 64 32 | |
5910 | n32 32 32 | |
5911 | n32 64 64 | |
5912 | o64 32 32 | |
5913 | o64 64 64 | |
5914 | n64 32 32 | |
5915 | n64 64 64 | |
5916 | eabi32 32 32 | |
5917 | eabi32 64 32 | |
5918 | eabi64 32 32 | |
5919 | eabi64 64 64 | |
5920 | ||
5921 | Note that for o32 and eabi32, pointers are always 32 bits | |
5922 | regardless of any -mlongXX option. For all others, pointers and | |
5923 | longs are the same, as set by -mlongXX or set by defaults. | |
5924 | */ | |
5925 | ||
5926 | if (info.abfd != NULL) | |
5927 | { | |
5928 | int long_bit = 0; | |
5929 | ||
5930 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5931 | if (long_bit) | |
5932 | { | |
5933 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5934 | switch (mips_abi) | |
5935 | { | |
5936 | case MIPS_ABI_O32: | |
5937 | case MIPS_ABI_EABI32: | |
5938 | break; | |
5939 | case MIPS_ABI_N32: | |
5940 | case MIPS_ABI_O64: | |
5941 | case MIPS_ABI_N64: | |
5942 | case MIPS_ABI_EABI64: | |
5943 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5944 | break; | |
5945 | default: | |
5946 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5947 | } | |
5948 | } | |
5949 | } | |
5950 | ||
a5ea2558 AC |
5951 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5952 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5953 | comment: | |
5954 | ||
5955 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5956 | flag in object files because to do so would make it impossible to | |
102182a9 | 5957 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5958 | unnecessarily restrictive. |
361d1df0 | 5959 | |
a5ea2558 AC |
5960 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5961 | but to set this flag before gcc is built with such multilibs will | |
5962 | break too many systems.'' | |
5963 | ||
5964 | But even more unhelpfully, the default linker output target for | |
5965 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5966 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5967 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5968 | this flag to detect 32-bit mode would do the wrong thing given |
5969 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5970 | as 32-bit programs by default. */ |
a5ea2558 | 5971 | |
6c997a34 | 5972 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5973 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5974 | |
102182a9 MS |
5975 | /* Add/remove bits from an address. The MIPS needs be careful to |
5976 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5977 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5978 | ||
58dfe9ff AC |
5979 | /* Unwind the frame. */ |
5980 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5981 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 5982 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 5983 | |
102182a9 | 5984 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5985 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5986 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5987 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
5988 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
5989 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5990 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5991 | |
c2d11a7d JM |
5992 | /* MIPS version of CALL_DUMMY */ |
5993 | ||
9710e734 AC |
5994 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5995 | replaced by a command, and all targets will default to on stack | |
5996 | (regardless of the stack's execute status). */ | |
5997 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5998 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5999 | |
87783b8b AC |
6000 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6001 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6002 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6003 | ||
f7b9e9fc AC |
6004 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6005 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6006 | |
6007 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6008 | |
97ab0fdd MR |
6009 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6010 | ||
fc0c74b1 AC |
6011 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6012 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6013 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6014 | |
a4b8ebc8 | 6015 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6016 | |
e11c53d2 | 6017 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6018 | |
9dae60cc UW |
6019 | if (mips_abi == MIPS_ABI_N32) |
6020 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
6021 | else if (mips_abi == MIPS_ABI_N64) | |
6022 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
6023 | else | |
6024 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 6025 | |
d92524f1 PM |
6026 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6027 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6028 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6029 | being used as guards for target_stopped_by_watchpoint, why not have |
6030 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6031 | is sitting on? */ |
6032 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6033 | ||
e7d6a6d2 | 6034 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6035 | |
3352ef37 AC |
6036 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
6037 | ||
0d5de010 DJ |
6038 | /* Virtual tables. */ |
6039 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6040 | ||
29709017 DJ |
6041 | mips_register_g_packet_guesses (gdbarch); |
6042 | ||
6de918a6 | 6043 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6044 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6045 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6046 | |
5792a79b | 6047 | /* Unwind the frame. */ |
b8a22b94 DJ |
6048 | dwarf2_append_unwinders (gdbarch); |
6049 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6050 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6051 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6052 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6053 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6054 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6055 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6056 | |
f8b73d13 DJ |
6057 | if (tdesc_data) |
6058 | { | |
6059 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6060 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6061 | |
6062 | /* Override the normal target description methods to handle our | |
6063 | dual real and pseudo registers. */ | |
6064 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6065 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
6066 | ||
6067 | num_regs = gdbarch_num_regs (gdbarch); | |
6068 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6069 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6070 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6071 | } | |
6072 | ||
6073 | /* Add ABI-specific aliases for the registers. */ | |
6074 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6075 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6076 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6077 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6078 | else | |
6079 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6080 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6081 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6082 | ||
6083 | /* Add some other standard aliases. */ | |
6084 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6085 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6086 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6087 | ||
865093a3 AR |
6088 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6089 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6090 | value_of_mips_user_reg, | |
6091 | &mips_numeric_register_aliases[i].regnum); | |
6092 | ||
4b9b3959 AC |
6093 | return gdbarch; |
6094 | } | |
6095 | ||
2e4ebe70 | 6096 | static void |
6d82d43b | 6097 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6098 | { |
6099 | struct gdbarch_info info; | |
6100 | ||
6101 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6102 | mips_gdbarch_init will take care of the rest. */ | |
6103 | gdbarch_info_init (&info); | |
6104 | gdbarch_update_p (info); | |
6105 | } | |
6106 | ||
ad188201 KB |
6107 | /* Print out which MIPS ABI is in use. */ |
6108 | ||
6109 | static void | |
1f8ca57c JB |
6110 | show_mips_abi (struct ui_file *file, |
6111 | int from_tty, | |
6112 | struct cmd_list_element *ignored_cmd, | |
6113 | const char *ignored_value) | |
ad188201 | 6114 | { |
1cf3db46 | 6115 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6116 | fprintf_filtered |
6117 | (file, | |
6118 | "The MIPS ABI is unknown because the current architecture " | |
6119 | "is not MIPS.\n"); | |
ad188201 KB |
6120 | else |
6121 | { | |
6122 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6123 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6124 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6125 | ||
6126 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6127 | fprintf_filtered |
6128 | (file, | |
6129 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6130 | actual_abi_str); |
ad188201 | 6131 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6132 | fprintf_filtered |
6133 | (file, | |
6134 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6135 | actual_abi_str); |
ad188201 KB |
6136 | else |
6137 | { | |
6138 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
6139 | fprintf_filtered |
6140 | (file, | |
6141 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 6142 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6143 | } |
6144 | } | |
6145 | } | |
6146 | ||
4b9b3959 | 6147 | static void |
72a155b4 | 6148 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6149 | { |
72a155b4 | 6150 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6151 | if (tdep != NULL) |
c2d11a7d | 6152 | { |
acdb74a0 AC |
6153 | int ef_mips_arch; |
6154 | int ef_mips_32bitmode; | |
f49e4e6d | 6155 | /* Determine the ISA. */ |
acdb74a0 AC |
6156 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6157 | { | |
6158 | case E_MIPS_ARCH_1: | |
6159 | ef_mips_arch = 1; | |
6160 | break; | |
6161 | case E_MIPS_ARCH_2: | |
6162 | ef_mips_arch = 2; | |
6163 | break; | |
6164 | case E_MIPS_ARCH_3: | |
6165 | ef_mips_arch = 3; | |
6166 | break; | |
6167 | case E_MIPS_ARCH_4: | |
93d56215 | 6168 | ef_mips_arch = 4; |
acdb74a0 AC |
6169 | break; |
6170 | default: | |
93d56215 | 6171 | ef_mips_arch = 0; |
acdb74a0 AC |
6172 | break; |
6173 | } | |
f49e4e6d | 6174 | /* Determine the size of a pointer. */ |
acdb74a0 | 6175 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6176 | fprintf_unfiltered (file, |
6177 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6178 | tdep->elf_flags); |
4b9b3959 | 6179 | fprintf_unfiltered (file, |
acdb74a0 AC |
6180 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6181 | ef_mips_32bitmode); | |
6182 | fprintf_unfiltered (file, | |
6183 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6184 | ef_mips_arch); | |
6185 | fprintf_unfiltered (file, | |
6186 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6187 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6188 | fprintf_unfiltered (file, |
6189 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6190 | mips_mask_address_p (tdep), |
4014092b | 6191 | tdep->default_mask_address_p); |
c2d11a7d | 6192 | } |
4b9b3959 AC |
6193 | fprintf_unfiltered (file, |
6194 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6195 | MIPS_DEFAULT_FPU_TYPE, | |
6196 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6197 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6198 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6199 | : "???")); | |
74ed0bb4 MD |
6200 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6201 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6202 | fprintf_unfiltered (file, |
6203 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6204 | MIPS_FPU_TYPE (gdbarch), |
6205 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6206 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6207 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6208 | : "???")); |
c2d11a7d JM |
6209 | } |
6210 | ||
6d82d43b | 6211 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6212 | |
c906108c | 6213 | void |
acdb74a0 | 6214 | _initialize_mips_tdep (void) |
c906108c SS |
6215 | { |
6216 | static struct cmd_list_element *mipsfpulist = NULL; | |
6217 | struct cmd_list_element *c; | |
6218 | ||
6d82d43b | 6219 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6220 | if (MIPS_ABI_LAST + 1 |
6221 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6222 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6223 | |
4b9b3959 | 6224 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6225 | |
8d5f9dcb DJ |
6226 | mips_pdr_data = register_objfile_data (); |
6227 | ||
4eb0ad19 DJ |
6228 | /* Create feature sets with the appropriate properties. The values |
6229 | are not important. */ | |
6230 | mips_tdesc_gp32 = allocate_target_description (); | |
6231 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6232 | ||
6233 | mips_tdesc_gp64 = allocate_target_description (); | |
6234 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6235 | ||
a5ea2558 AC |
6236 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6237 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 6238 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6239 | &setmipscmdlist, "set mips ", 0, &setlist); |
6240 | ||
6241 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6242 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6243 | &showmipscmdlist, "show mips ", 0, &showlist); |
6244 | ||
2e4ebe70 | 6245 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6246 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6247 | &mips_abi_string, _("\ | |
6248 | Set the MIPS ABI used by this program."), _("\ | |
6249 | Show the MIPS ABI used by this program."), _("\ | |
6250 | This option can be set to one of:\n\ | |
6251 | auto - the default ABI associated with the current binary\n\ | |
6252 | o32\n\ | |
6253 | o64\n\ | |
6254 | n32\n\ | |
6255 | n64\n\ | |
6256 | eabi32\n\ | |
6257 | eabi64"), | |
6258 | mips_abi_update, | |
6259 | show_mips_abi, | |
6260 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6261 | |
c906108c SS |
6262 | /* Let the user turn off floating point and set the fence post for |
6263 | heuristic_proc_start. */ | |
6264 | ||
6265 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6266 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6267 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6268 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6269 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6270 | &mipsfpulist); |
6271 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6272 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6273 | &mipsfpulist); |
6274 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6275 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6276 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6277 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6278 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6279 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6280 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6281 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6282 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6283 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6284 | &mipsfpulist); |
6285 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6286 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6287 | &showlist); |
6288 | ||
c906108c SS |
6289 | /* We really would like to have both "0" and "unlimited" work, but |
6290 | command.c doesn't deal with that. So make it a var_zinteger | |
6291 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6292 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6293 | &heuristic_fence_post, _("\ |
6294 | Set the distance searched for the start of a function."), _("\ | |
6295 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6296 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6297 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6298 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6299 | reinit_frame_cache_sfunc, |
7915a72c | 6300 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 6301 | &setlist, &showlist); |
c906108c SS |
6302 | |
6303 | /* Allow the user to control whether the upper bits of 64-bit | |
6304 | addresses should be zeroed. */ | |
7915a72c AC |
6305 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6306 | &mask_address_var, _("\ | |
6307 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6308 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 6309 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 6310 | allow GDB to determine the correct value."), |
08546159 AC |
6311 | NULL, show_mask_address, |
6312 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6313 | |
6314 | /* Allow the user to control the size of 32 bit registers within the | |
6315 | raw remote packet. */ | |
b3f42336 | 6316 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6317 | &mips64_transfers_32bit_regs_p, _("\ |
6318 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6319 | _("\ | |
6320 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6321 | _("\ | |
719ec221 AC |
6322 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6323 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6324 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6325 | set_mips64_transfers_32bit_regs, |
7915a72c | 6326 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 6327 | &setlist, &showlist); |
9ace0497 AC |
6328 | |
6329 | /* Debug this files internals. */ | |
6bcadd06 | 6330 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6331 | &mips_debug, _("\ |
6332 | Set mips debugging."), _("\ | |
6333 | Show mips debugging."), _("\ | |
6334 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6335 | NULL, |
7915a72c | 6336 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 6337 | &setdebuglist, &showdebuglist); |
c906108c | 6338 | } |