Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a AC |
3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
4 | 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. | |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
28 | #include "frame.h" | |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
c906108c SS |
42 | |
43 | #include "opcode/mips.h" | |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
c906108c | 47 | |
dd824b04 DJ |
48 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
49 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
50 | #define ST0_FR (1 << 26) | |
51 | ||
b0069a17 AC |
52 | /* The sizes of floating point registers. */ |
53 | ||
54 | enum | |
55 | { | |
56 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
57 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
58 | }; | |
59 | ||
0dadbba0 AC |
60 | /* All the possible MIPS ABIs. */ |
61 | ||
62 | enum mips_abi | |
63 | { | |
2e4ebe70 | 64 | MIPS_ABI_UNKNOWN = 0, |
0dadbba0 AC |
65 | MIPS_ABI_N32, |
66 | MIPS_ABI_O32, | |
67 | MIPS_ABI_O64, | |
68 | MIPS_ABI_EABI32, | |
2e4ebe70 DJ |
69 | MIPS_ABI_EABI64, |
70 | MIPS_ABI_LAST | |
0dadbba0 AC |
71 | }; |
72 | ||
2e4ebe70 DJ |
73 | static const char *mips_abi_string; |
74 | ||
75 | static const char *mips_abi_strings[] = { | |
76 | "auto", | |
77 | "n32", | |
78 | "o32", | |
79 | "o64", | |
80 | "eabi32", | |
81 | "eabi64", | |
82 | NULL | |
83 | }; | |
84 | ||
cce74817 | 85 | struct frame_extra_info |
c5aa993b JM |
86 | { |
87 | mips_extra_func_info_t proc_desc; | |
88 | int num_args; | |
89 | }; | |
cce74817 | 90 | |
d929b26f AC |
91 | /* Various MIPS ISA options (related to stack analysis) can be |
92 | overridden dynamically. Establish an enum/array for managing | |
93 | them. */ | |
94 | ||
53904c9e AC |
95 | static const char size_auto[] = "auto"; |
96 | static const char size_32[] = "32"; | |
97 | static const char size_64[] = "64"; | |
d929b26f | 98 | |
53904c9e | 99 | static const char *size_enums[] = { |
d929b26f AC |
100 | size_auto, |
101 | size_32, | |
102 | size_64, | |
a5ea2558 AC |
103 | 0 |
104 | }; | |
105 | ||
7a292a7a SS |
106 | /* Some MIPS boards don't support floating point while others only |
107 | support single-precision floating-point operations. See also | |
108 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
109 | |
110 | enum mips_fpu_type | |
c5aa993b JM |
111 | { |
112 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
113 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
114 | MIPS_FPU_NONE /* No floating point. */ | |
115 | }; | |
c906108c SS |
116 | |
117 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
118 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
119 | #endif | |
120 | static int mips_fpu_type_auto = 1; | |
121 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 122 | |
9ace0497 | 123 | static int mips_debug = 0; |
7a292a7a | 124 | |
c2d11a7d JM |
125 | /* MIPS specific per-architecture information */ |
126 | struct gdbarch_tdep | |
127 | { | |
128 | /* from the elf header */ | |
129 | int elf_flags; | |
70f80edf | 130 | |
c2d11a7d | 131 | /* mips options */ |
0dadbba0 | 132 | enum mips_abi mips_abi; |
2e4ebe70 | 133 | enum mips_abi found_abi; |
c2d11a7d JM |
134 | enum mips_fpu_type mips_fpu_type; |
135 | int mips_last_arg_regnum; | |
136 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 137 | int mips_default_saved_regsize; |
c2d11a7d | 138 | int mips_fp_register_double; |
d929b26f AC |
139 | int mips_regs_have_home_p; |
140 | int mips_default_stack_argsize; | |
5213ab06 | 141 | int gdb_target_is_mips64; |
4014092b | 142 | int default_mask_address_p; |
70f80edf JT |
143 | |
144 | enum gdb_osabi osabi; | |
c2d11a7d JM |
145 | }; |
146 | ||
0dadbba0 | 147 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 148 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 149 | |
c2d11a7d | 150 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 151 | |
c2d11a7d | 152 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 153 | |
c2d11a7d | 154 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 155 | |
d929b26f AC |
156 | /* Return the currently configured (or set) saved register size. */ |
157 | ||
a5ea2558 | 158 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 159 | |
53904c9e | 160 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
161 | |
162 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
163 | ||
164 | static unsigned int | |
acdb74a0 | 165 | mips_saved_regsize (void) |
d929b26f AC |
166 | { |
167 | if (mips_saved_regsize_string == size_auto) | |
168 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
169 | else if (mips_saved_regsize_string == size_64) | |
170 | return 8; | |
171 | else /* if (mips_saved_regsize_string == size_32) */ | |
172 | return 4; | |
173 | } | |
174 | ||
dd824b04 DJ |
175 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
176 | compatiblity mode. A return value of 1 means that we have | |
177 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
178 | ||
179 | static int | |
180 | mips2_fp_compat (void) | |
181 | { | |
182 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
183 | meaningful. */ | |
184 | if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4) | |
185 | return 0; | |
186 | ||
187 | #if 0 | |
188 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
189 | in all the places we deal with FP registers. PR gdb/413. */ | |
190 | /* Otherwise check the FR bit in the status register - it controls | |
191 | the FP compatiblity mode. If it is clear we are in compatibility | |
192 | mode. */ | |
193 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
194 | return 1; | |
195 | #endif | |
361d1df0 | 196 | |
dd824b04 DJ |
197 | return 0; |
198 | } | |
199 | ||
c2d11a7d JM |
200 | /* Indicate that the ABI makes use of double-precision registers |
201 | provided by the FPU (rather than combining pairs of registers to | |
202 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
203 | determine if the ABI is using double-precision registers. See also | |
204 | MIPS_FPU_TYPE. */ | |
c2d11a7d | 205 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 206 | |
d929b26f AC |
207 | /* Does the caller allocate a ``home'' for each register used in the |
208 | function call? The N32 ABI and MIPS_EABI do not, the others do. */ | |
209 | ||
d929b26f | 210 | #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p) |
d929b26f AC |
211 | |
212 | /* The amount of space reserved on the stack for registers. This is | |
213 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
214 | data allocated after the registers have run out. */ | |
215 | ||
0dadbba0 | 216 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
217 | |
218 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
219 | ||
53904c9e | 220 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
221 | |
222 | static unsigned int | |
223 | mips_stack_argsize (void) | |
224 | { | |
225 | if (mips_stack_argsize_string == size_auto) | |
226 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
227 | else if (mips_stack_argsize_string == size_64) | |
228 | return 8; | |
229 | else /* if (mips_stack_argsize_string == size_32) */ | |
230 | return 4; | |
231 | } | |
232 | ||
5213ab06 | 233 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) |
c2d11a7d | 234 | |
92e1c15c | 235 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 236 | |
7a292a7a | 237 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 238 | |
a14ed312 | 239 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 240 | |
a14ed312 | 241 | static void mips_print_register (int, int); |
c906108c SS |
242 | |
243 | static mips_extra_func_info_t | |
479412cd | 244 | heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int); |
c906108c | 245 | |
a14ed312 | 246 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 247 | |
a14ed312 | 248 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 249 | |
a14ed312 | 250 | int mips_set_processor_type (char *); |
c906108c | 251 | |
a14ed312 | 252 | static void mips_show_processor_type_command (char *, int); |
c906108c | 253 | |
a14ed312 | 254 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c SS |
255 | |
256 | static mips_extra_func_info_t | |
479412cd | 257 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame); |
c906108c | 258 | |
a14ed312 KB |
259 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
260 | mips_extra_func_info_t proc_desc); | |
c906108c | 261 | |
dd824b04 DJ |
262 | static void mips_read_fp_register_single (int regno, char *rare_buffer); |
263 | static void mips_read_fp_register_double (int regno, char *rare_buffer); | |
264 | ||
67b2c998 DJ |
265 | static struct type *mips_float_register_type (void); |
266 | static struct type *mips_double_register_type (void); | |
267 | ||
c906108c SS |
268 | /* This value is the model of MIPS in use. It is derived from the value |
269 | of the PrID register. */ | |
270 | ||
271 | char *mips_processor_type; | |
272 | ||
273 | char *tmp_mips_processor_type; | |
274 | ||
acdb74a0 AC |
275 | /* The list of available "set mips " and "show mips " commands */ |
276 | ||
277 | static struct cmd_list_element *setmipscmdlist = NULL; | |
278 | static struct cmd_list_element *showmipscmdlist = NULL; | |
279 | ||
c906108c SS |
280 | /* A set of original names, to be used when restoring back to generic |
281 | registers from a specific set. */ | |
282 | ||
cce74817 JM |
283 | char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
284 | char **mips_processor_reg_names = mips_generic_reg_names; | |
285 | ||
fa88f677 | 286 | const char * |
fba45db2 | 287 | mips_register_name (int i) |
cce74817 JM |
288 | { |
289 | return mips_processor_reg_names[i]; | |
290 | } | |
9846de1b | 291 | /* *INDENT-OFF* */ |
c906108c SS |
292 | /* Names of IDT R3041 registers. */ |
293 | ||
294 | char *mips_r3041_reg_names[] = { | |
295 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
296 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
297 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
298 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
299 | "sr", "lo", "hi", "bad", "cause","pc", | |
300 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
301 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
302 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
303 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
304 | "fsr", "fir", "fp", "", | |
305 | "", "", "bus", "ccfg", "", "", "", "", | |
306 | "", "", "port", "cmp", "", "", "epc", "prid", | |
307 | }; | |
308 | ||
309 | /* Names of IDT R3051 registers. */ | |
310 | ||
311 | char *mips_r3051_reg_names[] = { | |
312 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
313 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
314 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
315 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
316 | "sr", "lo", "hi", "bad", "cause","pc", | |
317 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
318 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
319 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
320 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
321 | "fsr", "fir", "fp", "", | |
322 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
323 | "", "", "ehi", "", "", "", "epc", "prid", | |
324 | }; | |
325 | ||
326 | /* Names of IDT R3081 registers. */ | |
327 | ||
328 | char *mips_r3081_reg_names[] = { | |
329 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
330 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
331 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
332 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
333 | "sr", "lo", "hi", "bad", "cause","pc", | |
334 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
335 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
336 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
337 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
338 | "fsr", "fir", "fp", "", | |
339 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
340 | "", "", "ehi", "", "", "", "epc", "prid", | |
341 | }; | |
342 | ||
343 | /* Names of LSI 33k registers. */ | |
344 | ||
345 | char *mips_lsi33k_reg_names[] = { | |
346 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
347 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
348 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
349 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
350 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
351 | "dcic", "bpc", "bda", "", "", "", "", "", | |
352 | "", "", "", "", "", "", "", "", | |
353 | "", "", "", "", "", "", "", "", | |
354 | "", "", "", "", "", "", "", "", | |
355 | "", "", "", "", | |
356 | "", "", "", "", "", "", "", "", | |
357 | "", "", "", "", "", "", "", "", | |
358 | }; | |
359 | ||
360 | struct { | |
361 | char *name; | |
362 | char **regnames; | |
363 | } mips_processor_type_table[] = { | |
364 | { "generic", mips_generic_reg_names }, | |
365 | { "r3041", mips_r3041_reg_names }, | |
366 | { "r3051", mips_r3051_reg_names }, | |
367 | { "r3071", mips_r3081_reg_names }, | |
368 | { "r3081", mips_r3081_reg_names }, | |
369 | { "lsi33k", mips_lsi33k_reg_names }, | |
370 | { NULL, NULL } | |
371 | }; | |
9846de1b | 372 | /* *INDENT-ON* */ |
c906108c | 373 | |
c5aa993b JM |
374 | |
375 | ||
376 | ||
c906108c | 377 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
378 | static int mips16_to_32_reg[8] = |
379 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
380 | |
381 | /* Heuristic_proc_start may hunt through the text section for a long | |
382 | time across a 2400 baud serial line. Allows the user to limit this | |
383 | search. */ | |
384 | ||
385 | static unsigned int heuristic_fence_post = 0; | |
386 | ||
c5aa993b JM |
387 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
388 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
389 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
390 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
391 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
392 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
393 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
394 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
395 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
396 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
397 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
398 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
399 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
400 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
401 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
402 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
403 | ||
404 | struct linked_proc_info | |
c5aa993b JM |
405 | { |
406 | struct mips_extra_func_info info; | |
407 | struct linked_proc_info *next; | |
408 | } | |
409 | *linked_proc_desc_table = NULL; | |
c906108c | 410 | |
cce74817 | 411 | void |
acdb74a0 | 412 | mips_print_extra_frame_info (struct frame_info *fi) |
cce74817 JM |
413 | { |
414 | if (fi | |
415 | && fi->extra_info | |
416 | && fi->extra_info->proc_desc | |
417 | && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 418 | printf_filtered (" frame pointer is at %s+%s\n", |
cce74817 | 419 | REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), |
d4f3574e | 420 | paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); |
cce74817 | 421 | } |
c906108c | 422 | |
46cd78fb AC |
423 | /* Number of bytes of storage in the actual machine representation for |
424 | register N. NOTE: This indirectly defines the register size | |
425 | transfered by the GDB protocol. */ | |
43e526b9 JM |
426 | |
427 | static int mips64_transfers_32bit_regs_p = 0; | |
428 | ||
429 | int | |
acdb74a0 | 430 | mips_register_raw_size (int reg_nr) |
43e526b9 JM |
431 | { |
432 | if (mips64_transfers_32bit_regs_p) | |
433 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
d02ee681 AC |
434 | else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32 |
435 | && FP_REGISTER_DOUBLE) | |
436 | /* For MIPS_ABI_N32 (for example) we need 8 byte floating point | |
437 | registers. */ | |
438 | return 8; | |
43e526b9 JM |
439 | else |
440 | return MIPS_REGSIZE; | |
441 | } | |
442 | ||
46cd78fb AC |
443 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
444 | defines the remote-gdb packet. */ | |
445 | ||
43e526b9 | 446 | int |
acdb74a0 | 447 | mips_register_convertible (int reg_nr) |
43e526b9 JM |
448 | { |
449 | if (mips64_transfers_32bit_regs_p) | |
450 | return 0; | |
451 | else | |
452 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
453 | } | |
454 | ||
455 | void | |
acdb74a0 AC |
456 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
457 | char *raw_buf, char *virt_buf) | |
43e526b9 | 458 | { |
d7449b42 | 459 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
460 | memcpy (virt_buf, |
461 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
462 | TYPE_LENGTH (virtual_type)); | |
463 | else | |
464 | memcpy (virt_buf, | |
465 | raw_buf, | |
466 | TYPE_LENGTH (virtual_type)); | |
467 | } | |
468 | ||
469 | void | |
acdb74a0 AC |
470 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
471 | char *virt_buf, char *raw_buf) | |
43e526b9 JM |
472 | { |
473 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
d7449b42 | 474 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
475 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
476 | virt_buf, | |
477 | TYPE_LENGTH (virtual_type)); | |
478 | else | |
479 | memcpy (raw_buf, | |
480 | virt_buf, | |
481 | TYPE_LENGTH (virtual_type)); | |
482 | } | |
483 | ||
c906108c | 484 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 485 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
486 | |
487 | static int | |
488 | mips_mask_address_p (void) | |
489 | { | |
490 | switch (mask_address_var) | |
491 | { | |
7f19b9a2 | 492 | case AUTO_BOOLEAN_TRUE: |
4014092b | 493 | return 1; |
7f19b9a2 | 494 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
495 | return 0; |
496 | break; | |
7f19b9a2 | 497 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 498 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 499 | default: |
8e65ff28 AC |
500 | internal_error (__FILE__, __LINE__, |
501 | "mips_mask_address_p: bad switch"); | |
4014092b | 502 | return -1; |
361d1df0 | 503 | } |
4014092b AC |
504 | } |
505 | ||
506 | static void | |
e9e68a56 | 507 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
508 | { |
509 | switch (mask_address_var) | |
510 | { | |
7f19b9a2 | 511 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
512 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
513 | break; | |
7f19b9a2 | 514 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
515 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
516 | break; | |
7f19b9a2 | 517 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
518 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
519 | mips_mask_address_p () ? "enabled" : "disabled"); | |
520 | break; | |
521 | default: | |
8e65ff28 AC |
522 | internal_error (__FILE__, __LINE__, |
523 | "show_mask_address: bad switch"); | |
4014092b | 524 | break; |
361d1df0 | 525 | } |
4014092b | 526 | } |
c906108c SS |
527 | |
528 | /* Should call_function allocate stack space for a struct return? */ | |
529 | int | |
fba45db2 | 530 | mips_use_struct_convention (int gcc_p, struct type *type) |
c906108c SS |
531 | { |
532 | if (MIPS_EABI) | |
7a292a7a | 533 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
c906108c | 534 | else |
c5aa993b | 535 | return 1; /* Structures are returned by ref in extra arg0 */ |
c906108c SS |
536 | } |
537 | ||
538 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ | |
539 | ||
540 | static int | |
541 | pc_is_mips16 (bfd_vma memaddr) | |
542 | { | |
543 | struct minimal_symbol *sym; | |
544 | ||
545 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
546 | if (IS_MIPS16_ADDR (memaddr)) | |
547 | return 1; | |
548 | ||
549 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
550 | the high bit of the info field. Use this to decide if the function is | |
551 | MIPS16 or normal MIPS. */ | |
552 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
553 | if (sym) | |
554 | return MSYMBOL_IS_SPECIAL (sym); | |
555 | else | |
556 | return 0; | |
557 | } | |
558 | ||
6c997a34 AC |
559 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
560 | all registers should be sign extended for simplicity? */ | |
561 | ||
562 | static CORE_ADDR | |
39f77062 | 563 | mips_read_pc (ptid_t ptid) |
6c997a34 | 564 | { |
39f77062 | 565 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 566 | } |
c906108c SS |
567 | |
568 | /* This returns the PC of the first inst after the prologue. If we can't | |
569 | find the prologue, then return 0. */ | |
570 | ||
571 | static CORE_ADDR | |
acdb74a0 AC |
572 | after_prologue (CORE_ADDR pc, |
573 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
574 | { |
575 | struct symtab_and_line sal; | |
576 | CORE_ADDR func_addr, func_end; | |
577 | ||
479412cd DJ |
578 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
579 | to read the stack pointer from the current machine state, because | |
580 | the current machine state has nothing to do with the information | |
581 | we need from the proc_desc; and the process may or may not exist | |
582 | right now. */ | |
c906108c | 583 | if (!proc_desc) |
479412cd | 584 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
585 | |
586 | if (proc_desc) | |
587 | { | |
588 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 589 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
590 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
591 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
592 | return 0; | |
593 | } | |
594 | ||
595 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
596 | return 0; /* Unknown */ | |
597 | ||
598 | sal = find_pc_line (func_addr, 0); | |
599 | ||
600 | if (sal.end < func_end) | |
601 | return sal.end; | |
602 | ||
603 | /* The line after the prologue is after the end of the function. In this | |
604 | case, tell the caller to find the prologue the hard way. */ | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
609 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
610 | set the appropriate bit in the general register mask or float register mask | |
611 | to indicate which register is saved. This is a helper function | |
612 | for mips_find_saved_regs. */ | |
613 | ||
614 | static void | |
acdb74a0 AC |
615 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
616 | unsigned long *float_mask) | |
c906108c SS |
617 | { |
618 | int reg; | |
619 | ||
620 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
621 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
622 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
623 | { | |
624 | /* It might be possible to use the instruction to | |
c5aa993b JM |
625 | find the offset, rather than the code below which |
626 | is based on things being in a certain order in the | |
627 | frame, but figuring out what the instruction's offset | |
628 | is relative to might be a little tricky. */ | |
c906108c SS |
629 | reg = (inst & 0x001f0000) >> 16; |
630 | *gen_mask |= (1 << reg); | |
631 | } | |
632 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
633 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
634 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
635 | |
636 | { | |
637 | reg = ((inst & 0x001f0000) >> 16); | |
638 | *float_mask |= (1 << reg); | |
639 | } | |
640 | } | |
641 | ||
642 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
643 | set the appropriate bit in the general register or float register mask | |
644 | to indicate which register is saved. This is a helper function | |
645 | for mips_find_saved_regs. */ | |
646 | ||
647 | static void | |
acdb74a0 | 648 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 649 | { |
c5aa993b | 650 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
651 | { |
652 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
653 | *gen_mask |= (1 << reg); | |
654 | } | |
c5aa993b | 655 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
656 | { |
657 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
658 | *gen_mask |= (1 << reg); | |
659 | } | |
c5aa993b | 660 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
661 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
662 | *gen_mask |= (1 << RA_REGNUM); | |
663 | } | |
664 | ||
665 | ||
666 | /* Fetch and return instruction from the specified location. If the PC | |
667 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
668 | ||
669 | static t_inst | |
acdb74a0 | 670 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
671 | { |
672 | char buf[MIPS_INSTLEN]; | |
673 | int instlen; | |
674 | int status; | |
675 | ||
676 | if (pc_is_mips16 (addr)) | |
677 | { | |
678 | instlen = MIPS16_INSTLEN; | |
679 | addr = UNMAKE_MIPS16_ADDR (addr); | |
680 | } | |
681 | else | |
c5aa993b | 682 | instlen = MIPS_INSTLEN; |
c906108c SS |
683 | status = read_memory_nobpt (addr, buf, instlen); |
684 | if (status) | |
685 | memory_error (status, addr); | |
686 | return extract_unsigned_integer (buf, instlen); | |
687 | } | |
688 | ||
689 | ||
690 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
691 | #define mips32_op(x) (x >> 26) |
692 | #define itype_op(x) (x >> 26) | |
693 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 694 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 695 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 696 | |
e135b889 DJ |
697 | #define jtype_op(x) (x >> 26) |
698 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 699 | |
e135b889 DJ |
700 | #define rtype_op(x) (x >> 26) |
701 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
702 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
703 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
704 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
705 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
706 | |
707 | static CORE_ADDR | |
c5aa993b JM |
708 | mips32_relative_offset (unsigned long inst) |
709 | { | |
710 | long x; | |
711 | x = itype_immediate (inst); | |
712 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 713 | { |
c5aa993b | 714 | x |= 0xffff0000; /* sign extension */ |
c906108c | 715 | } |
c5aa993b JM |
716 | x = x << 2; |
717 | return x; | |
c906108c SS |
718 | } |
719 | ||
720 | /* Determine whate to set a single step breakpoint while considering | |
721 | branch prediction */ | |
722 | CORE_ADDR | |
c5aa993b JM |
723 | mips32_next_pc (CORE_ADDR pc) |
724 | { | |
725 | unsigned long inst; | |
726 | int op; | |
727 | inst = mips_fetch_instruction (pc); | |
e135b889 | 728 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 729 | { |
e135b889 DJ |
730 | if (itype_op (inst) >> 2 == 5) |
731 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 732 | { |
e135b889 | 733 | op = (itype_op (inst) & 0x03); |
c906108c SS |
734 | switch (op) |
735 | { | |
e135b889 DJ |
736 | case 0: /* BEQL */ |
737 | goto equal_branch; | |
738 | case 1: /* BNEL */ | |
739 | goto neq_branch; | |
740 | case 2: /* BLEZL */ | |
741 | goto less_branch; | |
742 | case 3: /* BGTZ */ | |
743 | goto greater_branch; | |
c5aa993b JM |
744 | default: |
745 | pc += 4; | |
c906108c SS |
746 | } |
747 | } | |
e135b889 DJ |
748 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
749 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
750 | { | |
751 | int tf = itype_rt (inst) & 0x01; | |
752 | int cnum = itype_rt (inst) >> 2; | |
753 | int fcrcs = read_signed_register (FCRCS_REGNUM); | |
754 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); | |
755 | ||
756 | if (((cond >> cnum) & 0x01) == tf) | |
757 | pc += mips32_relative_offset (inst) + 4; | |
758 | else | |
759 | pc += 8; | |
760 | } | |
c5aa993b JM |
761 | else |
762 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
763 | } |
764 | else | |
c5aa993b JM |
765 | { /* This gets way messy */ |
766 | ||
c906108c | 767 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 768 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 769 | { |
c5aa993b JM |
770 | case 0: /* SPECIAL */ |
771 | op = rtype_funct (inst); | |
772 | switch (op) | |
773 | { | |
774 | case 8: /* JR */ | |
775 | case 9: /* JALR */ | |
6c997a34 AC |
776 | /* Set PC to that address */ |
777 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
778 | break; |
779 | default: | |
780 | pc += 4; | |
781 | } | |
782 | ||
e135b889 | 783 | break; /* end SPECIAL */ |
c5aa993b | 784 | case 1: /* REGIMM */ |
c906108c | 785 | { |
e135b889 DJ |
786 | op = itype_rt (inst); /* branch condition */ |
787 | switch (op) | |
c906108c | 788 | { |
c5aa993b | 789 | case 0: /* BLTZ */ |
e135b889 DJ |
790 | case 2: /* BLTZL */ |
791 | case 16: /* BLTZAL */ | |
c5aa993b | 792 | case 18: /* BLTZALL */ |
c906108c | 793 | less_branch: |
6c997a34 | 794 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
795 | pc += mips32_relative_offset (inst) + 4; |
796 | else | |
797 | pc += 8; /* after the delay slot */ | |
798 | break; | |
e135b889 | 799 | case 1: /* BGEZ */ |
c5aa993b JM |
800 | case 3: /* BGEZL */ |
801 | case 17: /* BGEZAL */ | |
802 | case 19: /* BGEZALL */ | |
c906108c | 803 | greater_equal_branch: |
6c997a34 | 804 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
805 | pc += mips32_relative_offset (inst) + 4; |
806 | else | |
807 | pc += 8; /* after the delay slot */ | |
808 | break; | |
e135b889 | 809 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
810 | default: |
811 | pc += 4; | |
c906108c SS |
812 | } |
813 | } | |
e135b889 | 814 | break; /* end REGIMM */ |
c5aa993b JM |
815 | case 2: /* J */ |
816 | case 3: /* JAL */ | |
817 | { | |
818 | unsigned long reg; | |
819 | reg = jtype_target (inst) << 2; | |
e135b889 | 820 | /* Upper four bits get never changed... */ |
c5aa993b | 821 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 822 | } |
c5aa993b JM |
823 | break; |
824 | /* FIXME case JALX : */ | |
825 | { | |
826 | unsigned long reg; | |
827 | reg = jtype_target (inst) << 2; | |
828 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
829 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
830 | } | |
c5aa993b | 831 | break; /* The new PC will be alternate mode */ |
e135b889 | 832 | case 4: /* BEQ, BEQL */ |
c5aa993b | 833 | equal_branch: |
6c997a34 AC |
834 | if (read_signed_register (itype_rs (inst)) == |
835 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
836 | pc += mips32_relative_offset (inst) + 4; |
837 | else | |
838 | pc += 8; | |
839 | break; | |
e135b889 | 840 | case 5: /* BNE, BNEL */ |
c5aa993b | 841 | neq_branch: |
6c997a34 | 842 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 843 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
844 | pc += mips32_relative_offset (inst) + 4; |
845 | else | |
846 | pc += 8; | |
847 | break; | |
e135b889 | 848 | case 6: /* BLEZ, BLEZL */ |
c906108c | 849 | less_zero_branch: |
6c997a34 | 850 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
851 | pc += mips32_relative_offset (inst) + 4; |
852 | else | |
853 | pc += 8; | |
854 | break; | |
855 | case 7: | |
e135b889 DJ |
856 | default: |
857 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 858 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
859 | pc += mips32_relative_offset (inst) + 4; |
860 | else | |
861 | pc += 8; | |
862 | break; | |
c5aa993b JM |
863 | } /* switch */ |
864 | } /* else */ | |
865 | return pc; | |
866 | } /* mips32_next_pc */ | |
c906108c SS |
867 | |
868 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 869 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
870 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
871 | We dont want to set a single step instruction on the extend instruction | |
872 | either. | |
c5aa993b | 873 | */ |
c906108c SS |
874 | |
875 | /* Lots of mips16 instruction formats */ | |
876 | /* Predicting jumps requires itype,ritype,i8type | |
877 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 878 | */ |
c906108c SS |
879 | enum mips16_inst_fmts |
880 | { | |
c5aa993b JM |
881 | itype, /* 0 immediate 5,10 */ |
882 | ritype, /* 1 5,3,8 */ | |
883 | rrtype, /* 2 5,3,3,5 */ | |
884 | rritype, /* 3 5,3,3,5 */ | |
885 | rrrtype, /* 4 5,3,3,3,2 */ | |
886 | rriatype, /* 5 5,3,3,1,4 */ | |
887 | shifttype, /* 6 5,3,3,3,2 */ | |
888 | i8type, /* 7 5,3,8 */ | |
889 | i8movtype, /* 8 5,3,3,5 */ | |
890 | i8mov32rtype, /* 9 5,3,5,3 */ | |
891 | i64type, /* 10 5,3,8 */ | |
892 | ri64type, /* 11 5,3,3,5 */ | |
893 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
894 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
895 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
896 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
897 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
898 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
899 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
900 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
901 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
902 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
903 | }; | |
12f02c2a AC |
904 | /* I am heaping all the fields of the formats into one structure and |
905 | then, only the fields which are involved in instruction extension */ | |
c906108c | 906 | struct upk_mips16 |
c5aa993b | 907 | { |
12f02c2a | 908 | CORE_ADDR offset; |
c5aa993b JM |
909 | unsigned int regx; /* Function in i8 type */ |
910 | unsigned int regy; | |
911 | }; | |
c906108c SS |
912 | |
913 | ||
12f02c2a AC |
914 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
915 | for the bits which make up the immediatate extension. */ | |
c906108c | 916 | |
12f02c2a AC |
917 | static CORE_ADDR |
918 | extended_offset (unsigned int extension) | |
c906108c | 919 | { |
12f02c2a | 920 | CORE_ADDR value; |
c5aa993b JM |
921 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
922 | value = value << 6; | |
923 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
924 | value = value << 5; | |
925 | value |= extension & 0x01f; /* extract 4:0 */ | |
926 | return value; | |
c906108c SS |
927 | } |
928 | ||
929 | /* Only call this function if you know that this is an extendable | |
930 | instruction, It wont malfunction, but why make excess remote memory references? | |
931 | If the immediate operands get sign extended or somthing, do it after | |
932 | the extension is performed. | |
c5aa993b | 933 | */ |
c906108c SS |
934 | /* FIXME: Every one of these cases needs to worry about sign extension |
935 | when the offset is to be used in relative addressing */ | |
936 | ||
937 | ||
12f02c2a | 938 | static unsigned int |
c5aa993b | 939 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 940 | { |
c5aa993b JM |
941 | char buf[8]; |
942 | pc &= 0xfffffffe; /* clear the low order bit */ | |
943 | target_read_memory (pc, buf, 2); | |
944 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
945 | } |
946 | ||
947 | static void | |
c5aa993b | 948 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
949 | unsigned int extension, |
950 | unsigned int inst, | |
951 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 952 | struct upk_mips16 *upk) |
c906108c | 953 | { |
12f02c2a AC |
954 | CORE_ADDR offset; |
955 | int regx; | |
956 | int regy; | |
957 | switch (insn_format) | |
c906108c | 958 | { |
c5aa993b | 959 | case itype: |
c906108c | 960 | { |
12f02c2a AC |
961 | CORE_ADDR value; |
962 | if (extension) | |
c5aa993b JM |
963 | { |
964 | value = extended_offset (extension); | |
965 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 966 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
967 | } |
968 | else | |
c5aa993b | 969 | { |
12f02c2a | 970 | value = inst & 0x7ff; |
c5aa993b | 971 | /* FIXME : Consider sign extension */ |
c906108c | 972 | } |
12f02c2a AC |
973 | offset = value; |
974 | regx = -1; | |
975 | regy = -1; | |
c906108c | 976 | } |
c5aa993b JM |
977 | break; |
978 | case ritype: | |
979 | case i8type: | |
980 | { /* A register identifier and an offset */ | |
c906108c SS |
981 | /* Most of the fields are the same as I type but the |
982 | immediate value is of a different length */ | |
12f02c2a AC |
983 | CORE_ADDR value; |
984 | if (extension) | |
c906108c | 985 | { |
c5aa993b JM |
986 | value = extended_offset (extension); |
987 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
988 | value |= inst & 0xff; /* eleven bits from instruction */ |
989 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
990 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
991 | { | |
992 | value &= ~0x3fff; /* remove the sign bit */ | |
993 | value = -value; | |
c906108c SS |
994 | } |
995 | } | |
c5aa993b JM |
996 | else |
997 | { | |
12f02c2a AC |
998 | value = inst & 0xff; /* 8 bits */ |
999 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1000 | /* FIXME: Do sign extension , this format needs it */ |
1001 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1002 | { | |
1003 | value &= 0xef; /* remove the sign bit */ | |
1004 | value = -value; | |
1005 | } | |
c5aa993b | 1006 | } |
12f02c2a AC |
1007 | offset = value; |
1008 | regy = -1; | |
c5aa993b | 1009 | break; |
c906108c | 1010 | } |
c5aa993b | 1011 | case jalxtype: |
c906108c | 1012 | { |
c5aa993b | 1013 | unsigned long value; |
12f02c2a AC |
1014 | unsigned int nexthalf; |
1015 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1016 | value = value << 16; |
1017 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1018 | value |= nexthalf; | |
12f02c2a AC |
1019 | offset = value; |
1020 | regx = -1; | |
1021 | regy = -1; | |
c5aa993b | 1022 | break; |
c906108c SS |
1023 | } |
1024 | default: | |
8e65ff28 AC |
1025 | internal_error (__FILE__, __LINE__, |
1026 | "bad switch"); | |
c906108c | 1027 | } |
12f02c2a AC |
1028 | upk->offset = offset; |
1029 | upk->regx = regx; | |
1030 | upk->regy = regy; | |
c906108c SS |
1031 | } |
1032 | ||
1033 | ||
c5aa993b JM |
1034 | static CORE_ADDR |
1035 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1036 | { |
c5aa993b JM |
1037 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
1038 | ||
c906108c SS |
1039 | } |
1040 | ||
12f02c2a AC |
1041 | static CORE_ADDR |
1042 | extended_mips16_next_pc (CORE_ADDR pc, | |
1043 | unsigned int extension, | |
1044 | unsigned int insn) | |
c906108c | 1045 | { |
12f02c2a AC |
1046 | int op = (insn >> 11); |
1047 | switch (op) | |
c906108c | 1048 | { |
12f02c2a AC |
1049 | case 2: /* Branch */ |
1050 | { | |
1051 | CORE_ADDR offset; | |
1052 | struct upk_mips16 upk; | |
1053 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1054 | offset = upk.offset; | |
1055 | if (offset & 0x800) | |
1056 | { | |
1057 | offset &= 0xeff; | |
1058 | offset = -offset; | |
1059 | } | |
1060 | pc += (offset << 1) + 2; | |
1061 | break; | |
1062 | } | |
1063 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1064 | { | |
1065 | struct upk_mips16 upk; | |
1066 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1067 | pc = add_offset_16 (pc, upk.offset); | |
1068 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1069 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1070 | else | |
1071 | pc |= 0x01; | |
1072 | break; | |
1073 | } | |
1074 | case 4: /* beqz */ | |
1075 | { | |
1076 | struct upk_mips16 upk; | |
1077 | int reg; | |
1078 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1079 | reg = read_signed_register (upk.regx); | |
1080 | if (reg == 0) | |
1081 | pc += (upk.offset << 1) + 2; | |
1082 | else | |
1083 | pc += 2; | |
1084 | break; | |
1085 | } | |
1086 | case 5: /* bnez */ | |
1087 | { | |
1088 | struct upk_mips16 upk; | |
1089 | int reg; | |
1090 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1091 | reg = read_signed_register (upk.regx); | |
1092 | if (reg != 0) | |
1093 | pc += (upk.offset << 1) + 2; | |
1094 | else | |
1095 | pc += 2; | |
1096 | break; | |
1097 | } | |
1098 | case 12: /* I8 Formats btez btnez */ | |
1099 | { | |
1100 | struct upk_mips16 upk; | |
1101 | int reg; | |
1102 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1103 | /* upk.regx contains the opcode */ | |
1104 | reg = read_signed_register (24); /* Test register is 24 */ | |
1105 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1106 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1107 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1108 | pc += (upk.offset << 1) + 2; | |
1109 | else | |
1110 | pc += 2; | |
1111 | break; | |
1112 | } | |
1113 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1114 | { | |
1115 | struct upk_mips16 upk; | |
1116 | /* upk.fmt = rrtype; */ | |
1117 | op = insn & 0x1f; | |
1118 | if (op == 0) | |
c5aa993b | 1119 | { |
12f02c2a AC |
1120 | int reg; |
1121 | upk.regx = (insn >> 8) & 0x07; | |
1122 | upk.regy = (insn >> 5) & 0x07; | |
1123 | switch (upk.regy) | |
c5aa993b | 1124 | { |
12f02c2a AC |
1125 | case 0: |
1126 | reg = upk.regx; | |
1127 | break; | |
1128 | case 1: | |
1129 | reg = 31; | |
1130 | break; /* Function return instruction */ | |
1131 | case 2: | |
1132 | reg = upk.regx; | |
1133 | break; | |
1134 | default: | |
1135 | reg = 31; | |
1136 | break; /* BOGUS Guess */ | |
c906108c | 1137 | } |
12f02c2a | 1138 | pc = read_signed_register (reg); |
c906108c | 1139 | } |
12f02c2a | 1140 | else |
c5aa993b | 1141 | pc += 2; |
12f02c2a AC |
1142 | break; |
1143 | } | |
1144 | case 30: | |
1145 | /* This is an instruction extension. Fetch the real instruction | |
1146 | (which follows the extension) and decode things based on | |
1147 | that. */ | |
1148 | { | |
1149 | pc += 2; | |
1150 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1151 | break; | |
1152 | } | |
1153 | default: | |
1154 | { | |
1155 | pc += 2; | |
1156 | break; | |
1157 | } | |
c906108c | 1158 | } |
c5aa993b | 1159 | return pc; |
12f02c2a | 1160 | } |
c906108c | 1161 | |
12f02c2a AC |
1162 | CORE_ADDR |
1163 | mips16_next_pc (CORE_ADDR pc) | |
1164 | { | |
1165 | unsigned int insn = fetch_mips_16 (pc); | |
1166 | return extended_mips16_next_pc (pc, 0, insn); | |
1167 | } | |
1168 | ||
1169 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1170 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1171 | It works by decoding the current instruction and predicting where a |
1172 | branch will go. This isnt hard because all the data is available. | |
1173 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1174 | CORE_ADDR |
1175 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1176 | { |
c5aa993b JM |
1177 | if (pc & 0x01) |
1178 | return mips16_next_pc (pc); | |
1179 | else | |
1180 | return mips32_next_pc (pc); | |
12f02c2a | 1181 | } |
c906108c SS |
1182 | |
1183 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it | |
1184 | NULL). */ | |
1185 | ||
1186 | void | |
acdb74a0 | 1187 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1188 | { |
1189 | int ireg; | |
1190 | CORE_ADDR reg_position; | |
1191 | /* r0 bit means kernel trap */ | |
1192 | int kernel_trap; | |
1193 | /* What registers have been saved? Bitmasks. */ | |
1194 | unsigned long gen_mask, float_mask; | |
1195 | mips_extra_func_info_t proc_desc; | |
1196 | t_inst inst; | |
1197 | ||
1198 | frame_saved_regs_zalloc (fci); | |
1199 | ||
1200 | /* If it is the frame for sigtramp, the saved registers are located | |
1201 | in a sigcontext structure somewhere on the stack. | |
1202 | If the stack layout for sigtramp changes we might have to change these | |
1203 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
1204 | #ifndef SIGFRAME_BASE | |
1205 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
1206 | above the sigtramp frame. */ | |
1207 | #define SIGFRAME_BASE MIPS_REGSIZE | |
1208 | /* FIXME! Are these correct?? */ | |
1209 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1210 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1211 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1212 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1213 | #endif | |
1214 | #ifndef SIGFRAME_REG_SIZE | |
1215 | /* FIXME! Is this correct?? */ | |
1216 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
1217 | #endif | |
1218 | if (fci->signal_handler_caller) | |
1219 | { | |
1220 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1221 | { | |
c5aa993b JM |
1222 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF |
1223 | + ireg * SIGFRAME_REG_SIZE; | |
1224 | fci->saved_regs[ireg] = reg_position; | |
c906108c SS |
1225 | } |
1226 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1227 | { | |
c5aa993b JM |
1228 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF |
1229 | + ireg * SIGFRAME_REG_SIZE; | |
1230 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; | |
c906108c SS |
1231 | } |
1232 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
1233 | return; | |
1234 | } | |
1235 | ||
cce74817 | 1236 | proc_desc = fci->extra_info->proc_desc; |
c906108c SS |
1237 | if (proc_desc == NULL) |
1238 | /* I'm not sure how/whether this can happen. Normally when we can't | |
1239 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
1240 | and set the saved_regs right away. */ | |
1241 | return; | |
1242 | ||
c5aa993b JM |
1243 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1244 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1245 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1246 | |
c5aa993b JM |
1247 | if ( /* In any frame other than the innermost or a frame interrupted by |
1248 | a signal, we assume that all registers have been saved. | |
1249 | This assumes that all register saves in a function happen before | |
1250 | the first function call. */ | |
1251 | (fci->next == NULL || fci->next->signal_handler_caller) | |
c906108c | 1252 | |
c5aa993b JM |
1253 | /* In a dummy frame we know exactly where things are saved. */ |
1254 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
c906108c | 1255 | |
c5aa993b JM |
1256 | /* Don't bother unless we are inside a function prologue. Outside the |
1257 | prologue, we know where everything is. */ | |
c906108c | 1258 | |
c5aa993b | 1259 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) |
c906108c | 1260 | |
c5aa993b JM |
1261 | /* Not sure exactly what kernel_trap means, but if it means |
1262 | the kernel saves the registers without a prologue doing it, | |
1263 | we better not examine the prologue to see whether registers | |
1264 | have been saved yet. */ | |
1265 | && !kernel_trap) | |
c906108c SS |
1266 | { |
1267 | /* We need to figure out whether the registers that the proc_desc | |
c5aa993b | 1268 | claims are saved have been saved yet. */ |
c906108c SS |
1269 | |
1270 | CORE_ADDR addr; | |
1271 | ||
1272 | /* Bitmasks; set if we have found a save for the register. */ | |
1273 | unsigned long gen_save_found = 0; | |
1274 | unsigned long float_save_found = 0; | |
1275 | int instlen; | |
1276 | ||
1277 | /* If the address is odd, assume this is MIPS16 code. */ | |
1278 | addr = PROC_LOW_ADDR (proc_desc); | |
1279 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1280 | ||
1281 | /* Scan through this function's instructions preceding the current | |
1282 | PC, and look for those that save registers. */ | |
1283 | while (addr < fci->pc) | |
1284 | { | |
1285 | inst = mips_fetch_instruction (addr); | |
1286 | if (pc_is_mips16 (addr)) | |
1287 | mips16_decode_reg_save (inst, &gen_save_found); | |
1288 | else | |
1289 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1290 | addr += instlen; | |
1291 | } | |
1292 | gen_mask = gen_save_found; | |
1293 | float_mask = float_save_found; | |
1294 | } | |
1295 | ||
1296 | /* Fill in the offsets for the registers which gen_mask says | |
1297 | were saved. */ | |
1298 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
c5aa993b | 1299 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
c906108c SS |
1300 | if (gen_mask & 0x80000000) |
1301 | { | |
1302 | fci->saved_regs[ireg] = reg_position; | |
7a292a7a | 1303 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1304 | } |
1305 | ||
1306 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
1307 | of that normally used by gcc. Therefore, we have to fetch the first | |
1308 | instruction of the function, and if it's an entry instruction that | |
1309 | saves $s0 or $s1, correct their saved addresses. */ | |
1310 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1311 | { | |
1312 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
c5aa993b | 1313 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
c906108c SS |
1314 | { |
1315 | int reg; | |
1316 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1317 | |
c906108c SS |
1318 | /* Check if the ra register was pushed on the stack. */ |
1319 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
1320 | if (inst & 0x20) | |
7a292a7a | 1321 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1322 | |
1323 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c5aa993b | 1324 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c SS |
1325 | { |
1326 | fci->saved_regs[reg] = reg_position; | |
7a292a7a | 1327 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1328 | } |
1329 | } | |
1330 | } | |
1331 | ||
1332 | /* Fill in the offsets for the registers which float_mask says | |
1333 | were saved. */ | |
1334 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
1335 | ||
1336 | /* The freg_offset points to where the first *double* register | |
1337 | is saved. So skip to the high-order word. */ | |
c5aa993b | 1338 | if (!GDB_TARGET_IS_MIPS64) |
7a292a7a | 1339 | reg_position += MIPS_SAVED_REGSIZE; |
c906108c SS |
1340 | |
1341 | /* Fill in the offsets for the float registers which float_mask says | |
1342 | were saved. */ | |
c5aa993b | 1343 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) |
c906108c SS |
1344 | if (float_mask & 0x80000000) |
1345 | { | |
c5aa993b | 1346 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
7a292a7a | 1347 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1348 | } |
1349 | ||
1350 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; | |
1351 | } | |
1352 | ||
1353 | static CORE_ADDR | |
acdb74a0 | 1354 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c SS |
1355 | { |
1356 | for (; fi; fi = fi->next) | |
1357 | { | |
1358 | /* We have to get the saved sp from the sigcontext | |
c5aa993b | 1359 | if it is a signal handler frame. */ |
c906108c SS |
1360 | if (regno == SP_REGNUM && !fi->signal_handler_caller) |
1361 | return fi->frame; | |
1362 | else | |
1363 | { | |
1364 | if (fi->saved_regs == NULL) | |
1365 | mips_find_saved_regs (fi); | |
1366 | if (fi->saved_regs[regno]) | |
2acceee2 | 1367 | return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE); |
c906108c SS |
1368 | } |
1369 | } | |
6c997a34 | 1370 | return read_signed_register (regno); |
c906108c SS |
1371 | } |
1372 | ||
1373 | /* mips_addr_bits_remove - remove useless address bits */ | |
1374 | ||
875e1767 | 1375 | static CORE_ADDR |
acdb74a0 | 1376 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1377 | { |
5213ab06 AC |
1378 | if (GDB_TARGET_IS_MIPS64) |
1379 | { | |
4014092b | 1380 | if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
5213ab06 AC |
1381 | { |
1382 | /* This hack is a work-around for existing boards using | |
1383 | PMON, the simulator, and any other 64-bit targets that | |
1384 | doesn't have true 64-bit addressing. On these targets, | |
1385 | the upper 32 bits of addresses are ignored by the | |
1386 | hardware. Thus, the PC or SP are likely to have been | |
1387 | sign extended to all 1s by instruction sequences that | |
1388 | load 32-bit addresses. For example, a typical piece of | |
4014092b AC |
1389 | code that loads an address is this: |
1390 | lui $r2, <upper 16 bits> | |
1391 | ori $r2, <lower 16 bits> | |
1392 | But the lui sign-extends the value such that the upper 32 | |
1393 | bits may be all 1s. The workaround is simply to mask off | |
1394 | these bits. In the future, gcc may be changed to support | |
1395 | true 64-bit addressing, and this masking will have to be | |
1396 | disabled. */ | |
5213ab06 AC |
1397 | addr &= (CORE_ADDR) 0xffffffff; |
1398 | } | |
1399 | } | |
4014092b | 1400 | else if (mips_mask_address_p ()) |
5213ab06 | 1401 | { |
4014092b AC |
1402 | /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be |
1403 | masking off bits, instead, the actual target should be asking | |
1404 | for the address to be converted to a valid pointer. */ | |
5213ab06 AC |
1405 | /* Even when GDB is configured for some 32-bit targets |
1406 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1407 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1408 | useless bits from addresses. */ | |
c5aa993b | 1409 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1410 | } |
c906108c SS |
1411 | return addr; |
1412 | } | |
1413 | ||
9022177c DJ |
1414 | /* mips_software_single_step() is called just before we want to resume |
1415 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1416 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1417 | the target of the coming instruction and breakpoint it. |
1418 | ||
1419 | single_step is also called just after the inferior stops. If we had | |
1420 | set up a simulated single-step, we undo our damage. */ | |
1421 | ||
1422 | void | |
1423 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1424 | { | |
1425 | static CORE_ADDR next_pc; | |
1426 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1427 | static binsn_quantum break_mem; | |
1428 | CORE_ADDR pc; | |
1429 | ||
1430 | if (insert_breakpoints_p) | |
1431 | { | |
1432 | pc = read_register (PC_REGNUM); | |
1433 | next_pc = mips_next_pc (pc); | |
1434 | ||
1435 | target_insert_breakpoint (next_pc, break_mem); | |
1436 | } | |
1437 | else | |
1438 | target_remove_breakpoint (next_pc, break_mem); | |
1439 | } | |
1440 | ||
10312cc4 | 1441 | static void |
acdb74a0 | 1442 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1443 | { |
1444 | CORE_ADDR pc, tmp; | |
1445 | ||
1446 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
c5aa993b | 1447 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); |
c906108c | 1448 | tmp = mips_skip_stub (pc); |
c5aa993b | 1449 | prev->pc = tmp ? tmp : pc; |
c906108c SS |
1450 | } |
1451 | ||
1452 | ||
1453 | CORE_ADDR | |
acdb74a0 | 1454 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1455 | { |
1456 | CORE_ADDR saved_pc; | |
cce74817 | 1457 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c SS |
1458 | /* We have to get the saved pc from the sigcontext |
1459 | if it is a signal handler frame. */ | |
1460 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
c5aa993b | 1461 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1462 | |
c5aa993b | 1463 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
7a292a7a | 1464 | saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1465 | else |
7a292a7a | 1466 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1467 | |
1468 | return ADDR_BITS_REMOVE (saved_pc); | |
1469 | } | |
1470 | ||
1471 | static struct mips_extra_func_info temp_proc_desc; | |
cce74817 | 1472 | static CORE_ADDR temp_saved_regs[NUM_REGS]; |
c906108c SS |
1473 | |
1474 | /* Set a register's saved stack address in temp_saved_regs. If an address | |
1475 | has already been set for this register, do nothing; this way we will | |
1476 | only recognize the first save of a given register in a function prologue. | |
1477 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ | |
1478 | ||
1479 | static void | |
acdb74a0 | 1480 | set_reg_offset (int regno, CORE_ADDR offset) |
c906108c | 1481 | { |
cce74817 JM |
1482 | if (temp_saved_regs[regno] == 0) |
1483 | temp_saved_regs[regno] = offset; | |
c906108c SS |
1484 | } |
1485 | ||
1486 | ||
1487 | /* Test whether the PC points to the return instruction at the | |
1488 | end of a function. */ | |
1489 | ||
c5aa993b | 1490 | static int |
acdb74a0 | 1491 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1492 | { |
1493 | if (pc_is_mips16 (pc)) | |
1494 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1495 | generates a "jr $ra"; other times it generates code to load | |
1496 | the return address from the stack to an accessible register (such | |
1497 | as $a3), then a "jr" using that register. This second case | |
1498 | is almost impossible to distinguish from an indirect jump | |
1499 | used for switch statements, so we don't even try. */ | |
1500 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1501 | else | |
1502 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1503 | } | |
1504 | ||
1505 | ||
1506 | /* This fencepost looks highly suspicious to me. Removing it also | |
1507 | seems suspicious as it could affect remote debugging across serial | |
1508 | lines. */ | |
1509 | ||
1510 | static CORE_ADDR | |
acdb74a0 | 1511 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1512 | { |
c5aa993b JM |
1513 | CORE_ADDR start_pc; |
1514 | CORE_ADDR fence; | |
1515 | int instlen; | |
1516 | int seen_adjsp = 0; | |
c906108c | 1517 | |
c5aa993b JM |
1518 | pc = ADDR_BITS_REMOVE (pc); |
1519 | start_pc = pc; | |
1520 | fence = start_pc - heuristic_fence_post; | |
1521 | if (start_pc == 0) | |
1522 | return 0; | |
c906108c | 1523 | |
c5aa993b JM |
1524 | if (heuristic_fence_post == UINT_MAX |
1525 | || fence < VM_MIN_ADDRESS) | |
1526 | fence = VM_MIN_ADDRESS; | |
c906108c | 1527 | |
c5aa993b | 1528 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1529 | |
c5aa993b JM |
1530 | /* search back for previous return */ |
1531 | for (start_pc -= instlen;; start_pc -= instlen) | |
1532 | if (start_pc < fence) | |
1533 | { | |
1534 | /* It's not clear to me why we reach this point when | |
1535 | stop_soon_quietly, but with this test, at least we | |
1536 | don't print out warnings for every child forked (eg, on | |
1537 | decstation). 22apr93 rich@cygnus.com. */ | |
1538 | if (!stop_soon_quietly) | |
c906108c | 1539 | { |
c5aa993b JM |
1540 | static int blurb_printed = 0; |
1541 | ||
1542 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1543 | paddr_nz (pc)); | |
1544 | ||
1545 | if (!blurb_printed) | |
c906108c | 1546 | { |
c5aa993b JM |
1547 | /* This actually happens frequently in embedded |
1548 | development, when you first connect to a board | |
1549 | and your stack pointer and pc are nowhere in | |
1550 | particular. This message needs to give people | |
1551 | in that situation enough information to | |
1552 | determine that it's no big deal. */ | |
1553 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1554 | GDB is unable to find the start of the function at 0x%s\n\ |
1555 | and thus can't determine the size of that function's stack frame.\n\ | |
1556 | This means that GDB may be unable to access that stack frame, or\n\ | |
1557 | the frames below it.\n\ | |
1558 | This problem is most likely caused by an invalid program counter or\n\ | |
1559 | stack pointer.\n\ | |
1560 | However, if you think GDB should simply search farther back\n\ | |
1561 | from 0x%s for code which looks like the beginning of a\n\ | |
1562 | function, you can increase the range of the search using the `set\n\ | |
1563 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1564 | paddr_nz (pc), paddr_nz (pc)); |
1565 | blurb_printed = 1; | |
c906108c | 1566 | } |
c906108c SS |
1567 | } |
1568 | ||
c5aa993b JM |
1569 | return 0; |
1570 | } | |
1571 | else if (pc_is_mips16 (start_pc)) | |
1572 | { | |
1573 | unsigned short inst; | |
1574 | ||
1575 | /* On MIPS16, any one of the following is likely to be the | |
1576 | start of a function: | |
1577 | entry | |
1578 | addiu sp,-n | |
1579 | daddiu sp,-n | |
1580 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1581 | inst = mips_fetch_instruction (start_pc); | |
1582 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1583 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1584 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1585 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1586 | break; | |
1587 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1588 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1589 | seen_adjsp = 1; | |
1590 | else | |
1591 | seen_adjsp = 0; | |
1592 | } | |
1593 | else if (mips_about_to_return (start_pc)) | |
1594 | { | |
1595 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1596 | break; | |
1597 | } | |
1598 | ||
c5aa993b | 1599 | return start_pc; |
c906108c SS |
1600 | } |
1601 | ||
1602 | /* Fetch the immediate value from a MIPS16 instruction. | |
1603 | If the previous instruction was an EXTEND, use it to extend | |
1604 | the upper bits of the immediate value. This is a helper function | |
1605 | for mips16_heuristic_proc_desc. */ | |
1606 | ||
1607 | static int | |
acdb74a0 AC |
1608 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1609 | unsigned short inst, /* current instruction */ | |
1610 | int nbits, /* number of bits in imm field */ | |
1611 | int scale, /* scale factor to be applied to imm */ | |
1612 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1613 | { |
1614 | int offset; | |
1615 | ||
1616 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1617 | { | |
1618 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1619 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1620 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1621 | return offset | (inst & 0x1f); | |
1622 | } | |
1623 | else | |
1624 | { | |
1625 | int max_imm = 1 << nbits; | |
1626 | int mask = max_imm - 1; | |
1627 | int sign_bit = max_imm >> 1; | |
1628 | ||
1629 | offset = inst & mask; | |
1630 | if (is_signed && (offset & sign_bit)) | |
1631 | offset = 0 - (max_imm - offset); | |
1632 | return offset * scale; | |
1633 | } | |
1634 | } | |
1635 | ||
1636 | ||
1637 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1638 | stream from start_pc to limit_pc. */ | |
1639 | ||
1640 | static void | |
acdb74a0 AC |
1641 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1642 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1643 | { |
1644 | CORE_ADDR cur_pc; | |
1645 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1646 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1647 | unsigned inst = 0; /* current instruction */ | |
1648 | unsigned entry_inst = 0; /* the entry instruction */ | |
1649 | int reg, offset; | |
1650 | ||
c5aa993b JM |
1651 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1652 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1653 | |
1654 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1655 | { | |
1656 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1657 | the immediate offset extension from it in mips16_get_imm. */ | |
1658 | prev_inst = inst; | |
1659 | ||
1660 | /* Fetch and decode the instruction. */ | |
1661 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1662 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1663 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1664 | { | |
1665 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1666 | if (offset < 0) /* negative stack adjustment? */ |
1667 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1668 | else |
1669 | /* Exit loop if a positive stack adjustment is found, which | |
1670 | usually means that the stack cleanup code in the function | |
1671 | epilogue is reached. */ | |
1672 | break; | |
1673 | } | |
1674 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1675 | { | |
1676 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1677 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1678 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1679 | set_reg_offset (reg, sp + offset); |
1680 | } | |
1681 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1682 | { | |
1683 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1684 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1685 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1686 | set_reg_offset (reg, sp + offset); |
1687 | } | |
1688 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1689 | { | |
1690 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 1691 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1692 | set_reg_offset (RA_REGNUM, sp + offset); |
1693 | } | |
1694 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1695 | { | |
1696 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 1697 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1698 | set_reg_offset (RA_REGNUM, sp + offset); |
1699 | } | |
c5aa993b | 1700 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
1701 | { |
1702 | frame_addr = sp; | |
1703 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1704 | } | |
1705 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1706 | { | |
1707 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1708 | frame_addr = sp + offset; | |
1709 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1710 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
1711 | } | |
1712 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1713 | { | |
1714 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1715 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1716 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1717 | set_reg_offset (reg, frame_addr + offset); |
1718 | } | |
1719 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1720 | { | |
1721 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1722 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1723 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1724 | set_reg_offset (reg, frame_addr + offset); |
1725 | } | |
c5aa993b JM |
1726 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
1727 | entry_inst = inst; /* save for later processing */ | |
c906108c | 1728 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 1729 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
1730 | } |
1731 | ||
c5aa993b JM |
1732 | /* The entry instruction is typically the first instruction in a function, |
1733 | and it stores registers at offsets relative to the value of the old SP | |
1734 | (before the prologue). But the value of the sp parameter to this | |
1735 | function is the new SP (after the prologue has been executed). So we | |
1736 | can't calculate those offsets until we've seen the entire prologue, | |
1737 | and can calculate what the old SP must have been. */ | |
1738 | if (entry_inst != 0) | |
1739 | { | |
1740 | int areg_count = (entry_inst >> 8) & 7; | |
1741 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 1742 | |
c5aa993b JM |
1743 | /* The entry instruction always subtracts 32 from the SP. */ |
1744 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 1745 | |
c5aa993b JM |
1746 | /* Now we can calculate what the SP must have been at the |
1747 | start of the function prologue. */ | |
1748 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 1749 | |
c5aa993b JM |
1750 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
1751 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1752 | { | |
1753 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1754 | set_reg_offset (reg, sp + offset); | |
1755 | offset += MIPS_SAVED_REGSIZE; | |
1756 | } | |
c906108c | 1757 | |
c5aa993b JM |
1758 | /* Check if the ra register was pushed on the stack. */ |
1759 | offset = -4; | |
1760 | if (entry_inst & 0x20) | |
1761 | { | |
1762 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
1763 | set_reg_offset (RA_REGNUM, sp + offset); | |
1764 | offset -= MIPS_SAVED_REGSIZE; | |
1765 | } | |
c906108c | 1766 | |
c5aa993b JM |
1767 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
1768 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1769 | { | |
1770 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1771 | set_reg_offset (reg, sp + offset); | |
1772 | offset -= MIPS_SAVED_REGSIZE; | |
1773 | } | |
1774 | } | |
c906108c SS |
1775 | } |
1776 | ||
1777 | static void | |
fba45db2 KB |
1778 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1779 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1780 | { |
1781 | CORE_ADDR cur_pc; | |
c5aa993b | 1782 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 1783 | restart: |
cce74817 | 1784 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 1785 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
1786 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
1787 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
1788 | { | |
1789 | unsigned long inst, high_word, low_word; | |
1790 | int reg; | |
1791 | ||
1792 | /* Fetch the instruction. */ | |
1793 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
1794 | ||
1795 | /* Save some code by pre-extracting some useful fields. */ | |
1796 | high_word = (inst >> 16) & 0xffff; | |
1797 | low_word = inst & 0xffff; | |
1798 | reg = high_word & 0x1f; | |
1799 | ||
c5aa993b | 1800 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
1801 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
1802 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1803 | { | |
1804 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 1805 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
1806 | else |
1807 | /* Exit loop if a positive stack adjustment is found, which | |
1808 | usually means that the stack cleanup code in the function | |
1809 | epilogue is reached. */ | |
1810 | break; | |
1811 | } | |
1812 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1813 | { | |
c5aa993b | 1814 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1815 | set_reg_offset (reg, sp + low_word); |
1816 | } | |
1817 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1818 | { | |
1819 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
1820 | but the register size used is only 32 bits. Make the address | |
1821 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 1822 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1823 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
1824 | } | |
c5aa993b | 1825 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
1826 | { |
1827 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
1828 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
1829 | frame_addr = sp + low_word; | |
c906108c SS |
1830 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
1831 | { | |
1832 | unsigned alloca_adjust; | |
1833 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1834 | frame_addr = read_next_frame_reg (next_frame, 30); |
1835 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
1836 | if (alloca_adjust > 0) |
1837 | { | |
1838 | /* FP > SP + frame_size. This may be because | |
1839 | * of an alloca or somethings similar. | |
1840 | * Fix sp to "pre-alloca" value, and try again. | |
1841 | */ | |
1842 | sp += alloca_adjust; | |
1843 | goto restart; | |
1844 | } | |
1845 | } | |
1846 | } | |
c5aa993b JM |
1847 | /* move $30,$sp. With different versions of gas this will be either |
1848 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1849 | Accept any one of these. */ | |
c906108c SS |
1850 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
1851 | { | |
1852 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1853 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
1854 | { | |
1855 | unsigned alloca_adjust; | |
1856 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1857 | frame_addr = read_next_frame_reg (next_frame, 30); |
1858 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
1859 | if (alloca_adjust > 0) |
1860 | { | |
1861 | /* FP > SP + frame_size. This may be because | |
1862 | * of an alloca or somethings similar. | |
1863 | * Fix sp to "pre-alloca" value, and try again. | |
1864 | */ | |
1865 | sp += alloca_adjust; | |
1866 | goto restart; | |
1867 | } | |
1868 | } | |
1869 | } | |
c5aa993b | 1870 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 1871 | { |
c5aa993b | 1872 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1873 | set_reg_offset (reg, frame_addr + low_word); |
1874 | } | |
1875 | } | |
1876 | } | |
1877 | ||
1878 | static mips_extra_func_info_t | |
acdb74a0 | 1879 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 1880 | struct frame_info *next_frame, int cur_frame) |
c906108c | 1881 | { |
479412cd DJ |
1882 | CORE_ADDR sp; |
1883 | ||
1884 | if (cur_frame) | |
1885 | sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
1886 | else | |
1887 | sp = 0; | |
c906108c | 1888 | |
c5aa993b JM |
1889 | if (start_pc == 0) |
1890 | return NULL; | |
1891 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
cce74817 | 1892 | memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
1893 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
1894 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
1895 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
1896 | ||
1897 | if (start_pc + 200 < limit_pc) | |
1898 | limit_pc = start_pc + 200; | |
1899 | if (pc_is_mips16 (start_pc)) | |
1900 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1901 | else | |
1902 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1903 | return &temp_proc_desc; | |
1904 | } | |
1905 | ||
6c0d6680 DJ |
1906 | struct mips_objfile_private |
1907 | { | |
1908 | bfd_size_type size; | |
1909 | char *contents; | |
1910 | }; | |
1911 | ||
1912 | /* Global used to communicate between non_heuristic_proc_desc and | |
1913 | compare_pdr_entries within qsort (). */ | |
1914 | static bfd *the_bfd; | |
1915 | ||
1916 | static int | |
1917 | compare_pdr_entries (const void *a, const void *b) | |
1918 | { | |
1919 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
1920 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
1921 | ||
1922 | if (lhs < rhs) | |
1923 | return -1; | |
1924 | else if (lhs == rhs) | |
1925 | return 0; | |
1926 | else | |
1927 | return 1; | |
1928 | } | |
1929 | ||
c906108c | 1930 | static mips_extra_func_info_t |
acdb74a0 | 1931 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
1932 | { |
1933 | CORE_ADDR startaddr; | |
1934 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 1935 | struct block *b = block_for_pc (pc); |
c906108c | 1936 | struct symbol *sym; |
6c0d6680 DJ |
1937 | struct obj_section *sec; |
1938 | struct mips_objfile_private *priv; | |
1939 | ||
1940 | if (PC_IN_CALL_DUMMY (pc, 0, 0)) | |
1941 | return NULL; | |
c906108c SS |
1942 | |
1943 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
1944 | if (addrptr) | |
1945 | *addrptr = startaddr; | |
6c0d6680 DJ |
1946 | |
1947 | priv = NULL; | |
1948 | ||
1949 | sec = find_pc_section (pc); | |
1950 | if (sec != NULL) | |
c906108c | 1951 | { |
6c0d6680 DJ |
1952 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
1953 | ||
1954 | /* Search the ".pdr" section generated by GAS. This includes most of | |
1955 | the information normally found in ECOFF PDRs. */ | |
1956 | ||
1957 | the_bfd = sec->objfile->obfd; | |
1958 | if (priv == NULL | |
1959 | && (the_bfd->format == bfd_object | |
1960 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
1961 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
1962 | { | |
1963 | /* Right now GAS only outputs the address as a four-byte sequence. | |
1964 | This means that we should not bother with this method on 64-bit | |
1965 | targets (until that is fixed). */ | |
1966 | ||
1967 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
1968 | sizeof (struct mips_objfile_private)); | |
1969 | priv->size = 0; | |
1970 | sec->objfile->obj_private = priv; | |
1971 | } | |
1972 | else if (priv == NULL) | |
1973 | { | |
1974 | asection *bfdsec; | |
1975 | ||
1976 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
1977 | sizeof (struct mips_objfile_private)); | |
1978 | ||
1979 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
1980 | if (bfdsec != NULL) | |
1981 | { | |
1982 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
1983 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
1984 | priv->size); | |
1985 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
1986 | priv->contents, 0, priv->size); | |
1987 | ||
1988 | /* In general, the .pdr section is sorted. However, in the | |
1989 | presence of multiple code sections (and other corner cases) | |
1990 | it can become unsorted. Sort it so that we can use a faster | |
1991 | binary search. */ | |
1992 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
1993 | } | |
1994 | else | |
1995 | priv->size = 0; | |
1996 | ||
1997 | sec->objfile->obj_private = priv; | |
1998 | } | |
1999 | the_bfd = NULL; | |
2000 | ||
2001 | if (priv->size != 0) | |
2002 | { | |
2003 | int low, mid, high; | |
2004 | char *ptr; | |
2005 | ||
2006 | low = 0; | |
2007 | high = priv->size / 32; | |
2008 | ||
2009 | do | |
2010 | { | |
2011 | CORE_ADDR pdr_pc; | |
2012 | ||
2013 | mid = (low + high) / 2; | |
2014 | ||
2015 | ptr = priv->contents + mid * 32; | |
2016 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2017 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2018 | SECT_OFF_TEXT (sec->objfile)); | |
2019 | if (pdr_pc == startaddr) | |
2020 | break; | |
2021 | if (pdr_pc > startaddr) | |
2022 | high = mid; | |
2023 | else | |
2024 | low = mid + 1; | |
2025 | } | |
2026 | while (low != high); | |
2027 | ||
2028 | if (low != high) | |
2029 | { | |
2030 | struct symbol *sym = find_pc_function (pc); | |
2031 | ||
2032 | /* Fill in what we need of the proc_desc. */ | |
2033 | proc_desc = (mips_extra_func_info_t) | |
2034 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2035 | sizeof (struct mips_extra_func_info)); | |
2036 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2037 | ||
2038 | /* Only used for dummy frames. */ | |
2039 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2040 | ||
2041 | PROC_FRAME_OFFSET (proc_desc) | |
2042 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2043 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2044 | ptr + 24); | |
2045 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2046 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2047 | ptr + 4); | |
2048 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2049 | ptr + 12); | |
2050 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2051 | ptr + 8); | |
2052 | PROC_FREG_OFFSET (proc_desc) | |
2053 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2054 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2055 | ptr + 28); | |
2056 | proc_desc->pdr.isym = (long) sym; | |
2057 | ||
2058 | return proc_desc; | |
2059 | } | |
2060 | } | |
c906108c SS |
2061 | } |
2062 | ||
6c0d6680 DJ |
2063 | if (b == NULL) |
2064 | return NULL; | |
2065 | ||
2066 | if (startaddr > BLOCK_START (b)) | |
2067 | { | |
2068 | /* This is the "pathological" case referred to in a comment in | |
2069 | print_frame_info. It might be better to move this check into | |
2070 | symbol reading. */ | |
2071 | return NULL; | |
2072 | } | |
2073 | ||
2074 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); | |
2075 | ||
c906108c SS |
2076 | /* If we never found a PDR for this function in symbol reading, then |
2077 | examine prologues to find the information. */ | |
2078 | if (sym) | |
2079 | { | |
2080 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2081 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2082 | return NULL; | |
2083 | else | |
2084 | return proc_desc; | |
2085 | } | |
2086 | else | |
2087 | return NULL; | |
2088 | } | |
2089 | ||
2090 | ||
2091 | static mips_extra_func_info_t | |
479412cd | 2092 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2093 | { |
2094 | mips_extra_func_info_t proc_desc; | |
2095 | CORE_ADDR startaddr; | |
2096 | ||
2097 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2098 | ||
2099 | if (proc_desc) | |
2100 | { | |
2101 | /* IF this is the topmost frame AND | |
2102 | * (this proc does not have debugging information OR | |
2103 | * the PC is in the procedure prologue) | |
2104 | * THEN create a "heuristic" proc_desc (by analyzing | |
2105 | * the actual code) to replace the "official" proc_desc. | |
2106 | */ | |
2107 | if (next_frame == NULL) | |
2108 | { | |
2109 | struct symtab_and_line val; | |
2110 | struct symbol *proc_symbol = | |
c5aa993b | 2111 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2112 | |
2113 | if (proc_symbol) | |
2114 | { | |
2115 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2116 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2117 | 0); |
2118 | val.pc = val.end ? val.end : pc; | |
2119 | } | |
2120 | if (!proc_symbol || pc < val.pc) | |
2121 | { | |
2122 | mips_extra_func_info_t found_heuristic = | |
c5aa993b | 2123 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
479412cd | 2124 | pc, next_frame, cur_frame); |
c906108c SS |
2125 | if (found_heuristic) |
2126 | proc_desc = found_heuristic; | |
2127 | } | |
2128 | } | |
2129 | } | |
2130 | else | |
2131 | { | |
2132 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2133 | by procedure call dummys. However, the procedures being called ought |
2134 | to have their own proc_descs, and even if they don't, | |
2135 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
2136 | |
2137 | register struct linked_proc_info *link; | |
2138 | ||
2139 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2140 | if (PROC_LOW_ADDR (&link->info) <= pc |
2141 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2142 | return &link->info; |
2143 | ||
2144 | if (startaddr == 0) | |
2145 | startaddr = heuristic_proc_start (pc); | |
2146 | ||
2147 | proc_desc = | |
479412cd | 2148 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2149 | } |
2150 | return proc_desc; | |
2151 | } | |
2152 | ||
2153 | static CORE_ADDR | |
acdb74a0 AC |
2154 | get_frame_pointer (struct frame_info *frame, |
2155 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
2156 | { |
2157 | return ADDR_BITS_REMOVE ( | |
c5aa993b JM |
2158 | read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) + |
2159 | PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2160 | } |
2161 | ||
2162 | mips_extra_func_info_t cached_proc_desc; | |
2163 | ||
2164 | CORE_ADDR | |
acdb74a0 | 2165 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2166 | { |
2167 | mips_extra_func_info_t proc_desc; | |
2168 | CORE_ADDR tmp; | |
c5aa993b | 2169 | CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); |
c906108c SS |
2170 | |
2171 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
2172 | return 0; | |
2173 | ||
2174 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2175 | PC of the caller of that stub. */ | |
2176 | if ((tmp = mips_skip_stub (saved_pc)) != 0) | |
2177 | saved_pc = tmp; | |
2178 | ||
2179 | /* Look up the procedure descriptor for this PC. */ | |
479412cd | 2180 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2181 | if (!proc_desc) |
2182 | return 0; | |
2183 | ||
2184 | cached_proc_desc = proc_desc; | |
2185 | ||
2186 | /* If no frame pointer and frame size is zero, we must be at end | |
2187 | of stack (or otherwise hosed). If we don't check frame size, | |
2188 | we loop forever if we see a zero size frame. */ | |
2189 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2190 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
c5aa993b JM |
2191 | /* The previous frame from a sigtramp frame might be frameless |
2192 | and have frame size zero. */ | |
c906108c SS |
2193 | && !frame->signal_handler_caller) |
2194 | return 0; | |
2195 | else | |
2196 | return get_frame_pointer (frame, proc_desc); | |
2197 | } | |
2198 | ||
2199 | void | |
acdb74a0 | 2200 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2201 | { |
2202 | int regnum; | |
2203 | ||
2204 | /* Use proc_desc calculated in frame_chain */ | |
2205 | mips_extra_func_info_t proc_desc = | |
479412cd | 2206 | fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1); |
c906108c | 2207 | |
cce74817 JM |
2208 | fci->extra_info = (struct frame_extra_info *) |
2209 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
2210 | ||
c906108c | 2211 | fci->saved_regs = NULL; |
cce74817 | 2212 | fci->extra_info->proc_desc = |
c906108c SS |
2213 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2214 | if (proc_desc) | |
2215 | { | |
2216 | /* Fixup frame-pointer - only needed for top frame */ | |
2217 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2218 | Get the value of the frame relative sp, procedure might have been |
2219 | interrupted by a signal at it's very start. */ | |
c906108c SS |
2220 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
2221 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
2222 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
2223 | else | |
2224 | fci->frame = get_frame_pointer (fci->next, proc_desc); | |
2225 | ||
2226 | if (proc_desc == &temp_proc_desc) | |
2227 | { | |
2228 | char *name; | |
2229 | ||
2230 | /* Do not set the saved registers for a sigtramp frame, | |
2231 | mips_find_saved_registers will do that for us. | |
2232 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
2233 | find_pc_partial_function (fci->pc, &name, | |
c5aa993b | 2234 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
d7bd68ca | 2235 | if (!PC_IN_SIGTRAMP (fci->pc, name)) |
c906108c | 2236 | { |
c5aa993b | 2237 | frame_saved_regs_zalloc (fci); |
cce74817 | 2238 | memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2239 | fci->saved_regs[PC_REGNUM] |
2240 | = fci->saved_regs[RA_REGNUM]; | |
2241 | } | |
2242 | } | |
2243 | ||
2244 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 JM |
2245 | /* assume we can't tell how many args for now */ |
2246 | fci->extra_info->num_args = -1; | |
c906108c SS |
2247 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2248 | { | |
c5aa993b | 2249 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2250 | { |
cce74817 | 2251 | fci->extra_info->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2252 | break; |
2253 | } | |
c5aa993b | 2254 | } |
c906108c SS |
2255 | } |
2256 | } | |
2257 | ||
2258 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2259 | we basically have to look at symbol information for the function | |
2260 | that we stopped in, which tells us *which* register (if any) is | |
2261 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2262 | the frame itself is at. |
c906108c SS |
2263 | |
2264 | This presents a problem when trying to examine a stack in memory | |
2265 | (that isn't executing at the moment), using the "frame" command. We | |
2266 | don't have a PC, nor do we have any registers except SP. | |
2267 | ||
2268 | This routine takes two arguments, SP and PC, and tries to make the | |
2269 | cached frames look as if these two arguments defined a frame on the | |
2270 | cache. This allows the rest of info frame to extract the important | |
2271 | arguments without difficulty. */ | |
2272 | ||
2273 | struct frame_info * | |
acdb74a0 | 2274 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2275 | { |
2276 | if (argc != 2) | |
2277 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2278 | ||
2279 | return create_new_frame (argv[0], argv[1]); | |
2280 | } | |
2281 | ||
f09ded24 AC |
2282 | /* According to the current ABI, should the type be passed in a |
2283 | floating-point register (assuming that there is space)? When there | |
2284 | is no FPU, FP are not even considered as possibile candidates for | |
2285 | FP registers and, consequently this returns false - forces FP | |
2286 | arguments into integer registers. */ | |
2287 | ||
2288 | static int | |
2289 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2290 | { | |
2291 | return ((typecode == TYPE_CODE_FLT | |
2292 | || (MIPS_EABI | |
2293 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2294 | && TYPE_NFIELDS (arg_type) == 1 | |
2295 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
2296 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); | |
2297 | } | |
2298 | ||
49e790b0 DJ |
2299 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2300 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2301 | ||
2302 | static int | |
2303 | mips_type_needs_double_align (struct type *type) | |
2304 | { | |
2305 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2306 | |
49e790b0 DJ |
2307 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2308 | return 1; | |
2309 | else if (typecode == TYPE_CODE_STRUCT) | |
2310 | { | |
2311 | if (TYPE_NFIELDS (type) < 1) | |
2312 | return 0; | |
2313 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2314 | } | |
2315 | else if (typecode == TYPE_CODE_UNION) | |
2316 | { | |
361d1df0 | 2317 | int i, n; |
49e790b0 DJ |
2318 | |
2319 | n = TYPE_NFIELDS (type); | |
2320 | for (i = 0; i < n; i++) | |
2321 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2322 | return 1; | |
2323 | return 0; | |
2324 | } | |
2325 | return 0; | |
2326 | } | |
2327 | ||
c906108c | 2328 | CORE_ADDR |
acdb74a0 | 2329 | mips_push_arguments (int nargs, |
ea7c478f | 2330 | struct value **args, |
acdb74a0 AC |
2331 | CORE_ADDR sp, |
2332 | int struct_return, | |
2333 | CORE_ADDR struct_addr) | |
c906108c SS |
2334 | { |
2335 | int argreg; | |
2336 | int float_argreg; | |
2337 | int argnum; | |
2338 | int len = 0; | |
2339 | int stack_offset = 0; | |
2340 | ||
2341 | /* Macros to round N up or down to the next A boundary; A must be | |
2342 | a power of two. */ | |
2343 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2344 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
c5aa993b | 2345 | |
c906108c SS |
2346 | /* First ensure that the stack and structure return address (if any) |
2347 | are properly aligned. The stack has to be at least 64-bit aligned | |
2348 | even on 32-bit machines, because doubles must be 64-bit aligned. | |
2349 | On at least one MIPS variant, stack frames need to be 128-bit | |
2350 | aligned, so we round to this widest known alignment. */ | |
2351 | sp = ROUND_DOWN (sp, 16); | |
cce41527 | 2352 | struct_addr = ROUND_DOWN (struct_addr, 16); |
c5aa993b | 2353 | |
c906108c SS |
2354 | /* Now make space on the stack for the args. We allocate more |
2355 | than necessary for EABI, because the first few arguments are | |
2356 | passed in registers, but that's OK. */ | |
2357 | for (argnum = 0; argnum < nargs; argnum++) | |
cce41527 | 2358 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_STACK_ARGSIZE); |
c906108c SS |
2359 | sp -= ROUND_UP (len, 16); |
2360 | ||
9ace0497 AC |
2361 | if (mips_debug) |
2362 | fprintf_unfiltered (gdb_stdlog, "mips_push_arguments: sp=0x%lx allocated %d\n", | |
2363 | (long) sp, ROUND_UP (len, 16)); | |
2364 | ||
c906108c SS |
2365 | /* Initialize the integer and float register pointers. */ |
2366 | argreg = A0_REGNUM; | |
2367 | float_argreg = FPA0_REGNUM; | |
2368 | ||
2369 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
2370 | if (struct_return) | |
9ace0497 AC |
2371 | { |
2372 | if (mips_debug) | |
2373 | fprintf_unfiltered (gdb_stdlog, | |
cce41527 | 2374 | "mips_push_arguments: struct_return reg=%d 0x%lx\n", |
9ace0497 AC |
2375 | argreg, (long) struct_addr); |
2376 | write_register (argreg++, struct_addr); | |
cce41527 AC |
2377 | if (MIPS_REGS_HAVE_HOME_P) |
2378 | stack_offset += MIPS_STACK_ARGSIZE; | |
9ace0497 | 2379 | } |
c906108c SS |
2380 | |
2381 | /* Now load as many as possible of the first arguments into | |
2382 | registers, and push the rest onto the stack. Loop thru args | |
2383 | from first to last. */ | |
2384 | for (argnum = 0; argnum < nargs; argnum++) | |
2385 | { | |
2386 | char *val; | |
2387 | char valbuf[MAX_REGISTER_RAW_SIZE]; | |
ea7c478f | 2388 | struct value *arg = args[argnum]; |
c906108c SS |
2389 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2390 | int len = TYPE_LENGTH (arg_type); | |
2391 | enum type_code typecode = TYPE_CODE (arg_type); | |
2392 | ||
9ace0497 AC |
2393 | if (mips_debug) |
2394 | fprintf_unfiltered (gdb_stdlog, | |
2395 | "mips_push_arguments: %d len=%d type=%d", | |
acdb74a0 | 2396 | argnum + 1, len, (int) typecode); |
9ace0497 | 2397 | |
c906108c | 2398 | /* The EABI passes structures that do not fit in a register by |
c5aa993b | 2399 | reference. In all other cases, pass the structure by value. */ |
9ace0497 AC |
2400 | if (MIPS_EABI |
2401 | && len > MIPS_SAVED_REGSIZE | |
2402 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
c906108c | 2403 | { |
7a292a7a | 2404 | store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2405 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2406 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2407 | val = valbuf; |
9ace0497 AC |
2408 | if (mips_debug) |
2409 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2410 | } |
2411 | else | |
c5aa993b | 2412 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2413 | |
2414 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2415 | even-numbered floating point register. Round the FP register |
2416 | up before the check to see if there are any FP registers | |
2417 | left. Non MIPS_EABI targets also pass the FP in the integer | |
2418 | registers so also round up normal registers. */ | |
2419 | if (!FP_REGISTER_DOUBLE | |
2420 | && fp_register_arg_p (typecode, arg_type)) | |
2421 | { | |
2422 | if ((float_argreg & 1)) | |
2423 | float_argreg++; | |
2424 | } | |
c906108c SS |
2425 | |
2426 | /* Floating point arguments passed in registers have to be | |
2427 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2428 | are passed in register pairs; the even register gets |
2429 | the low word, and the odd register gets the high word. | |
2430 | On non-EABI processors, the first two floating point arguments are | |
2431 | also copied to general registers, because MIPS16 functions | |
2432 | don't use float registers for arguments. This duplication of | |
2433 | arguments in general registers can't hurt non-MIPS16 functions | |
2434 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2435 | /* MIPS_EABI squeezes a struct that contains a single floating |
2436 | point value into an FP register instead of pushing it onto the | |
9a0149c6 | 2437 | stack. */ |
f09ded24 AC |
2438 | if (fp_register_arg_p (typecode, arg_type) |
2439 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2440 | { |
2441 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2442 | { | |
d7449b42 | 2443 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2444 | unsigned long regval; |
2445 | ||
2446 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2447 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2448 | if (mips_debug) |
acdb74a0 | 2449 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2450 | float_argreg, phex (regval, 4)); |
c906108c SS |
2451 | write_register (float_argreg++, regval); |
2452 | if (!MIPS_EABI) | |
9ace0497 AC |
2453 | { |
2454 | if (mips_debug) | |
acdb74a0 | 2455 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2456 | argreg, phex (regval, 4)); |
2457 | write_register (argreg++, regval); | |
2458 | } | |
c906108c SS |
2459 | |
2460 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2461 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2462 | if (mips_debug) |
acdb74a0 | 2463 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2464 | float_argreg, phex (regval, 4)); |
c906108c SS |
2465 | write_register (float_argreg++, regval); |
2466 | if (!MIPS_EABI) | |
c5aa993b | 2467 | { |
9ace0497 | 2468 | if (mips_debug) |
acdb74a0 | 2469 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2470 | argreg, phex (regval, 4)); |
2471 | write_register (argreg++, regval); | |
c906108c SS |
2472 | } |
2473 | ||
2474 | } | |
2475 | else | |
2476 | { | |
2477 | /* This is a floating point value that fits entirely | |
2478 | in a single register. */ | |
53a5351d JM |
2479 | /* On 32 bit ABI's the float_argreg is further adjusted |
2480 | above to ensure that it is even register aligned. */ | |
9ace0497 AC |
2481 | LONGEST regval = extract_unsigned_integer (val, len); |
2482 | if (mips_debug) | |
acdb74a0 | 2483 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2484 | float_argreg, phex (regval, len)); |
c906108c SS |
2485 | write_register (float_argreg++, regval); |
2486 | if (!MIPS_EABI) | |
c5aa993b | 2487 | { |
53a5351d JM |
2488 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
2489 | registers for each argument. The below is (my | |
2490 | guess) to ensure that the corresponding integer | |
2491 | register has reserved the same space. */ | |
9ace0497 | 2492 | if (mips_debug) |
acdb74a0 | 2493 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2494 | argreg, phex (regval, len)); |
c906108c SS |
2495 | write_register (argreg, regval); |
2496 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
2497 | } | |
2498 | } | |
cce41527 AC |
2499 | /* Reserve space for the FP register. */ |
2500 | if (MIPS_REGS_HAVE_HOME_P) | |
2501 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
c906108c SS |
2502 | } |
2503 | else | |
2504 | { | |
2505 | /* Copy the argument to general registers or the stack in | |
2506 | register-sized pieces. Large arguments are split between | |
2507 | registers and stack. */ | |
2508 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2509 | are treated specially: Irix cc passes them in registers | |
2510 | where gcc sometimes puts them on the stack. For maximum | |
2511 | compatibility, we will put them in both places. */ | |
c5aa993b | 2512 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2513 | (len % MIPS_SAVED_REGSIZE != 0)); |
49e790b0 DJ |
2514 | /* Structures should be aligned to eight bytes (even arg registers) |
2515 | on MIPS_ABI_O32 if their first member has double precision. */ | |
2516 | if (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_O32 | |
2517 | && mips_type_needs_double_align (arg_type)) | |
2518 | { | |
2519 | if ((argreg & 1)) | |
2520 | argreg++; | |
2521 | } | |
f09ded24 AC |
2522 | /* Note: Floating-point values that didn't fit into an FP |
2523 | register are only written to memory. */ | |
c906108c SS |
2524 | while (len > 0) |
2525 | { | |
566f0f7a AC |
2526 | /* Rememer if the argument was written to the stack. */ |
2527 | int stack_used_p = 0; | |
7a292a7a | 2528 | int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; |
c906108c | 2529 | |
acdb74a0 AC |
2530 | if (mips_debug) |
2531 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2532 | partial_len); | |
2533 | ||
566f0f7a | 2534 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2535 | if (argreg > MIPS_LAST_ARG_REGNUM |
2536 | || odd_sized_struct | |
2537 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2538 | { |
c906108c SS |
2539 | /* Should shorter than int integer values be |
2540 | promoted to int before being stored? */ | |
c906108c | 2541 | int longword_offset = 0; |
9ace0497 | 2542 | CORE_ADDR addr; |
566f0f7a | 2543 | stack_used_p = 1; |
d7449b42 | 2544 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2545 | { |
d929b26f | 2546 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2547 | (typecode == TYPE_CODE_INT || |
2548 | typecode == TYPE_CODE_PTR || | |
2549 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2550 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2551 | else if ((typecode == TYPE_CODE_STRUCT || |
2552 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2553 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2554 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2555 | } |
c5aa993b | 2556 | |
9ace0497 AC |
2557 | if (mips_debug) |
2558 | { | |
acdb74a0 | 2559 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%lx", |
9ace0497 AC |
2560 | (long) stack_offset); |
2561 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%lx", | |
2562 | (long) longword_offset); | |
2563 | } | |
361d1df0 | 2564 | |
9ace0497 AC |
2565 | addr = sp + stack_offset + longword_offset; |
2566 | ||
2567 | if (mips_debug) | |
2568 | { | |
2569 | int i; | |
2570 | fprintf_unfiltered (gdb_stdlog, " @0x%lx ", (long) addr); | |
2571 | for (i = 0; i < partial_len; i++) | |
2572 | { | |
2573 | fprintf_unfiltered (gdb_stdlog, "%02x", val[i] & 0xff); | |
2574 | } | |
2575 | } | |
2576 | write_memory (addr, val, partial_len); | |
c906108c SS |
2577 | } |
2578 | ||
f09ded24 AC |
2579 | /* Note!!! This is NOT an else clause. Odd sized |
2580 | structs may go thru BOTH paths. Floating point | |
2581 | arguments will not. */ | |
566f0f7a AC |
2582 | /* Write this portion of the argument to a general |
2583 | purpose register. */ | |
f09ded24 AC |
2584 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2585 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2586 | { |
9ace0497 | 2587 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2588 | |
361d1df0 | 2589 | /* A non-floating-point argument being passed in a |
c906108c SS |
2590 | general register. If a struct or union, and if |
2591 | the remaining length is smaller than the register | |
2592 | size, we have to adjust the register value on | |
2593 | big endian targets. | |
2594 | ||
2595 | It does not seem to be necessary to do the | |
2596 | same for integral types. | |
2597 | ||
2598 | Also don't do this adjustment on EABI and O64 | |
675fb869 AC |
2599 | binaries. |
2600 | ||
2601 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
2602 | outputting LE O32 with sizeof (struct) < | |
2603 | MIPS_SAVED_REGSIZE, generates a left shift as | |
2604 | part of storing the argument in a register a | |
2605 | register (the left shift isn't generated when | |
2606 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
2607 | is quite possible that this is GCC contradicting | |
2608 | the LE/O32 ABI, GDB has not been adjusted to | |
2609 | accommodate this. Either someone needs to | |
2610 | demonstrate that the LE/O32 ABI specifies such a | |
2611 | left shift OR this new ABI gets identified as | |
2612 | such and GDB gets tweaked accordingly. */ | |
c906108c SS |
2613 | |
2614 | if (!MIPS_EABI | |
7a292a7a | 2615 | && MIPS_SAVED_REGSIZE < 8 |
d7449b42 | 2616 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a | 2617 | && partial_len < MIPS_SAVED_REGSIZE |
c906108c SS |
2618 | && (typecode == TYPE_CODE_STRUCT || |
2619 | typecode == TYPE_CODE_UNION)) | |
c5aa993b | 2620 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * |
c906108c SS |
2621 | TARGET_CHAR_BIT); |
2622 | ||
9ace0497 | 2623 | if (mips_debug) |
acdb74a0 | 2624 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2625 | argreg, |
2626 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2627 | write_register (argreg, regval); |
2628 | argreg++; | |
c5aa993b | 2629 | |
c906108c SS |
2630 | /* If this is the old ABI, prevent subsequent floating |
2631 | point arguments from being passed in floating point | |
2632 | registers. */ | |
2633 | if (!MIPS_EABI) | |
2634 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
2635 | } | |
c5aa993b | 2636 | |
c906108c SS |
2637 | len -= partial_len; |
2638 | val += partial_len; | |
2639 | ||
566f0f7a AC |
2640 | /* Compute the the offset into the stack at which we |
2641 | will copy the next parameter. | |
2642 | ||
2643 | In older ABIs, the caller reserved space for | |
2644 | registers that contained arguments. This was loosely | |
2645 | refered to as their "home". Consequently, space is | |
2646 | always allocated. | |
c906108c | 2647 | |
566f0f7a AC |
2648 | In the new EABI (and the NABI32), the stack_offset |
2649 | only needs to be adjusted when it has been used.. */ | |
c906108c | 2650 | |
566f0f7a | 2651 | if (MIPS_REGS_HAVE_HOME_P || stack_used_p) |
d929b26f | 2652 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2653 | } |
2654 | } | |
9ace0497 AC |
2655 | if (mips_debug) |
2656 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2657 | } |
2658 | ||
0f71a2f6 JM |
2659 | /* Return adjusted stack pointer. */ |
2660 | return sp; | |
2661 | } | |
2662 | ||
2663 | CORE_ADDR | |
acdb74a0 | 2664 | mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
0f71a2f6 | 2665 | { |
c906108c SS |
2666 | /* Set the return address register to point to the entry |
2667 | point of the program, where a breakpoint lies in wait. */ | |
c5aa993b | 2668 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); |
c906108c SS |
2669 | return sp; |
2670 | } | |
2671 | ||
2672 | static void | |
c5aa993b | 2673 | mips_push_register (CORE_ADDR * sp, int regno) |
c906108c SS |
2674 | { |
2675 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
7a292a7a SS |
2676 | int regsize; |
2677 | int offset; | |
2678 | if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) | |
2679 | { | |
2680 | regsize = MIPS_SAVED_REGSIZE; | |
d7449b42 | 2681 | offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
2682 | ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE |
2683 | : 0); | |
2684 | } | |
2685 | else | |
2686 | { | |
2687 | regsize = REGISTER_RAW_SIZE (regno); | |
2688 | offset = 0; | |
2689 | } | |
c906108c SS |
2690 | *sp -= regsize; |
2691 | read_register_gen (regno, buffer); | |
7a292a7a | 2692 | write_memory (*sp, buffer + offset, regsize); |
c906108c SS |
2693 | } |
2694 | ||
2695 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
2696 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) | |
2697 | ||
2698 | void | |
acdb74a0 | 2699 | mips_push_dummy_frame (void) |
c906108c SS |
2700 | { |
2701 | int ireg; | |
c5aa993b JM |
2702 | struct linked_proc_info *link = (struct linked_proc_info *) |
2703 | xmalloc (sizeof (struct linked_proc_info)); | |
c906108c | 2704 | mips_extra_func_info_t proc_desc = &link->info; |
6c997a34 | 2705 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM)); |
c906108c SS |
2706 | CORE_ADDR old_sp = sp; |
2707 | link->next = linked_proc_desc_table; | |
2708 | linked_proc_desc_table = link; | |
2709 | ||
2710 | /* FIXME! are these correct ? */ | |
c5aa993b | 2711 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
c906108c SS |
2712 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
2713 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
2714 | #define FLOAT_SINGLE_REG_SAVE_MASK \ | |
2715 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
2716 | /* | |
2717 | * The registers we must save are all those not preserved across | |
2718 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
2719 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI | |
2720 | * and FP Control/Status registers. | |
361d1df0 | 2721 | * |
c906108c SS |
2722 | * |
2723 | * Dummy frame layout: | |
2724 | * (high memory) | |
c5aa993b JM |
2725 | * Saved PC |
2726 | * Saved MMHI, MMLO, FPC_CSR | |
2727 | * Saved R31 | |
2728 | * Saved R28 | |
2729 | * ... | |
2730 | * Saved R1 | |
c906108c SS |
2731 | * Saved D18 (i.e. F19, F18) |
2732 | * ... | |
2733 | * Saved D0 (i.e. F1, F0) | |
c5aa993b | 2734 | * Argument build area and stack arguments written via mips_push_arguments |
c906108c SS |
2735 | * (low memory) |
2736 | */ | |
2737 | ||
2738 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
c5aa993b JM |
2739 | PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; |
2740 | PROC_FRAME_OFFSET (proc_desc) = 0; | |
2741 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
c906108c SS |
2742 | mips_push_register (&sp, PC_REGNUM); |
2743 | mips_push_register (&sp, HI_REGNUM); | |
2744 | mips_push_register (&sp, LO_REGNUM); | |
2745 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
2746 | ||
2747 | /* Save general CPU registers */ | |
c5aa993b | 2748 | PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; |
c906108c | 2749 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
c5aa993b JM |
2750 | PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; |
2751 | for (ireg = 32; --ireg >= 0;) | |
2752 | if (PROC_REG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2753 | mips_push_register (&sp, ireg); |
2754 | ||
2755 | /* Save floating point registers starting with high order word */ | |
c5aa993b | 2756 | PROC_FREG_MASK (proc_desc) = |
c906108c SS |
2757 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
2758 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
2759 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register | |
2760 | from FP. */ | |
c5aa993b JM |
2761 | PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; |
2762 | for (ireg = 32; --ireg >= 0;) | |
2763 | if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2764 | mips_push_register (&sp, ireg + FP0_REGNUM); |
2765 | ||
2766 | /* Update the frame pointer for the call dummy and the stack pointer. | |
2767 | Set the procedure's starting and ending addresses to point to the | |
2768 | call dummy address at the entry point. */ | |
2769 | write_register (PUSH_FP_REGNUM, old_sp); | |
2770 | write_register (SP_REGNUM, sp); | |
c5aa993b JM |
2771 | PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); |
2772 | PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; | |
2773 | SET_PROC_DESC_IS_DUMMY (proc_desc); | |
2774 | PROC_PC_REG (proc_desc) = RA_REGNUM; | |
c906108c SS |
2775 | } |
2776 | ||
2777 | void | |
acdb74a0 | 2778 | mips_pop_frame (void) |
c906108c SS |
2779 | { |
2780 | register int regnum; | |
2781 | struct frame_info *frame = get_current_frame (); | |
2782 | CORE_ADDR new_sp = FRAME_FP (frame); | |
2783 | ||
cce74817 | 2784 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c | 2785 | |
c5aa993b | 2786 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
c906108c SS |
2787 | if (frame->saved_regs == NULL) |
2788 | mips_find_saved_regs (frame); | |
2789 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
2790 | { | |
2791 | if (regnum != SP_REGNUM && regnum != PC_REGNUM | |
2792 | && frame->saved_regs[regnum]) | |
2793 | write_register (regnum, | |
2794 | read_memory_integer (frame->saved_regs[regnum], | |
c5aa993b | 2795 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2796 | } |
2797 | write_register (SP_REGNUM, new_sp); | |
2798 | flush_cached_frames (); | |
2799 | ||
c5aa993b | 2800 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
2801 | { |
2802 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
2803 | ||
2804 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
2805 | pi_ptr != NULL; | |
2806 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
2807 | { | |
2808 | if (&pi_ptr->info == proc_desc) | |
2809 | break; | |
2810 | } | |
2811 | ||
2812 | if (pi_ptr == NULL) | |
2813 | error ("Can't locate dummy extra frame info\n"); | |
2814 | ||
2815 | if (prev_ptr != NULL) | |
2816 | prev_ptr->next = pi_ptr->next; | |
2817 | else | |
2818 | linked_proc_desc_table = pi_ptr->next; | |
2819 | ||
b8c9b27d | 2820 | xfree (pi_ptr); |
c906108c SS |
2821 | |
2822 | write_register (HI_REGNUM, | |
c5aa993b | 2823 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2824 | MIPS_SAVED_REGSIZE)); |
c906108c | 2825 | write_register (LO_REGNUM, |
c5aa993b | 2826 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2827 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2828 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
2829 | write_register (FCRCS_REGNUM, | |
c5aa993b | 2830 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2831 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2832 | } |
2833 | } | |
2834 | ||
dd824b04 DJ |
2835 | /* Floating point register management. |
2836 | ||
2837 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
2838 | 64bit operations, these early MIPS cpus treat fp register pairs | |
2839 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
2840 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
2841 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
2842 | double precision floats into two 32-bit chunks and store them in | |
2843 | consecutive fp regs. To display 64-bit floats stored in this | |
2844 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
2845 | Throw in user-configurable endianness and you have a real mess. | |
2846 | ||
2847 | The way this works is: | |
2848 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
2849 | double-precision value will be split across two logical registers. | |
2850 | The lower-numbered logical register will hold the low-order bits, | |
2851 | regardless of the processor's endianness. | |
2852 | - If we are on a 64-bit processor, and we are looking for a | |
2853 | single-precision value, it will be in the low ordered bits | |
2854 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
2855 | save slot in memory. | |
2856 | - If we are in 64-bit mode, everything is straightforward. | |
2857 | ||
2858 | Note that this code only deals with "live" registers at the top of the | |
2859 | stack. We will attempt to deal with saved registers later, when | |
2860 | the raw/cooked register interface is in place. (We need a general | |
2861 | interface that can deal with dynamic saved register sizes -- fp | |
2862 | regs could be 32 bits wide in one frame and 64 on the frame above | |
2863 | and below). */ | |
2864 | ||
67b2c998 DJ |
2865 | static struct type * |
2866 | mips_float_register_type (void) | |
2867 | { | |
361d1df0 | 2868 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
2869 | return builtin_type_ieee_single_big; |
2870 | else | |
2871 | return builtin_type_ieee_single_little; | |
2872 | } | |
2873 | ||
2874 | static struct type * | |
2875 | mips_double_register_type (void) | |
2876 | { | |
361d1df0 | 2877 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
2878 | return builtin_type_ieee_double_big; |
2879 | else | |
2880 | return builtin_type_ieee_double_little; | |
2881 | } | |
2882 | ||
dd824b04 DJ |
2883 | /* Copy a 32-bit single-precision value from the current frame |
2884 | into rare_buffer. */ | |
2885 | ||
2886 | static void | |
2887 | mips_read_fp_register_single (int regno, char *rare_buffer) | |
2888 | { | |
2889 | int raw_size = REGISTER_RAW_SIZE (regno); | |
2890 | char *raw_buffer = alloca (raw_size); | |
2891 | ||
cda5a58a | 2892 | if (!frame_register_read (selected_frame, regno, raw_buffer)) |
dd824b04 DJ |
2893 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
2894 | if (raw_size == 8) | |
2895 | { | |
2896 | /* We have a 64-bit value for this register. Find the low-order | |
2897 | 32 bits. */ | |
2898 | int offset; | |
2899 | ||
2900 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2901 | offset = 4; | |
2902 | else | |
2903 | offset = 0; | |
2904 | ||
2905 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
2906 | } | |
2907 | else | |
2908 | { | |
2909 | memcpy (rare_buffer, raw_buffer, 4); | |
2910 | } | |
2911 | } | |
2912 | ||
2913 | /* Copy a 64-bit double-precision value from the current frame into | |
2914 | rare_buffer. This may include getting half of it from the next | |
2915 | register. */ | |
2916 | ||
2917 | static void | |
2918 | mips_read_fp_register_double (int regno, char *rare_buffer) | |
2919 | { | |
2920 | int raw_size = REGISTER_RAW_SIZE (regno); | |
2921 | ||
2922 | if (raw_size == 8 && !mips2_fp_compat ()) | |
2923 | { | |
2924 | /* We have a 64-bit value for this register, and we should use | |
2925 | all 64 bits. */ | |
cda5a58a | 2926 | if (!frame_register_read (selected_frame, regno, rare_buffer)) |
dd824b04 DJ |
2927 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
2928 | } | |
2929 | else | |
2930 | { | |
2931 | if ((regno - FP0_REGNUM) & 1) | |
2932 | internal_error (__FILE__, __LINE__, | |
2933 | "mips_read_fp_register_double: bad access to " | |
2934 | "odd-numbered FP register"); | |
2935 | ||
2936 | /* mips_read_fp_register_single will find the correct 32 bits from | |
2937 | each register. */ | |
2938 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2939 | { | |
2940 | mips_read_fp_register_single (regno, rare_buffer + 4); | |
2941 | mips_read_fp_register_single (regno + 1, rare_buffer); | |
2942 | } | |
361d1df0 | 2943 | else |
dd824b04 DJ |
2944 | { |
2945 | mips_read_fp_register_single (regno, rare_buffer); | |
2946 | mips_read_fp_register_single (regno + 1, rare_buffer + 4); | |
2947 | } | |
2948 | } | |
2949 | } | |
2950 | ||
c906108c | 2951 | static void |
acdb74a0 | 2952 | mips_print_register (int regnum, int all) |
c906108c SS |
2953 | { |
2954 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2955 | ||
2956 | /* Get the data in raw format. */ | |
cda5a58a | 2957 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
c906108c SS |
2958 | { |
2959 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); | |
2960 | return; | |
2961 | } | |
2962 | ||
dd824b04 DJ |
2963 | /* If we have a actual 32-bit floating point register (or we are in |
2964 | 32-bit compatibility mode), and the register is even-numbered, | |
2965 | also print it as a double (spanning two registers). */ | |
c906108c | 2966 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT |
dd824b04 DJ |
2967 | && (REGISTER_RAW_SIZE (regnum) == 4 |
2968 | || mips2_fp_compat ()) | |
c5aa993b | 2969 | && !((regnum - FP0_REGNUM) & 1)) |
dd824b04 DJ |
2970 | { |
2971 | char dbuffer[2 * MAX_REGISTER_RAW_SIZE]; | |
c906108c | 2972 | |
dd824b04 | 2973 | mips_read_fp_register_double (regnum, dbuffer); |
c906108c | 2974 | |
dd824b04 | 2975 | printf_filtered ("(d%d: ", regnum - FP0_REGNUM); |
67b2c998 | 2976 | val_print (mips_double_register_type (), dbuffer, 0, 0, |
dd824b04 DJ |
2977 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
2978 | printf_filtered ("); "); | |
2979 | } | |
c906108c SS |
2980 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); |
2981 | ||
2982 | /* The problem with printing numeric register names (r26, etc.) is that | |
2983 | the user can't use them on input. Probably the best solution is to | |
2984 | fix it so that either the numeric or the funky (a2, etc.) names | |
2985 | are accepted on input. */ | |
2986 | if (regnum < MIPS_NUMREGS) | |
2987 | printf_filtered ("(r%d): ", regnum); | |
2988 | else | |
2989 | printf_filtered (": "); | |
2990 | ||
2991 | /* If virtual format is floating, print it that way. */ | |
2992 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
dd824b04 DJ |
2993 | if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ()) |
2994 | { | |
2995 | /* We have a meaningful 64-bit value in this register. Show | |
2996 | it as a 32-bit float and a 64-bit double. */ | |
d7449b42 | 2997 | int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG); |
c906108c SS |
2998 | |
2999 | printf_filtered (" (float) "); | |
67b2c998 | 3000 | val_print (mips_float_register_type (), raw_buffer + offset, 0, 0, |
c906108c SS |
3001 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
3002 | printf_filtered (", (double) "); | |
67b2c998 | 3003 | val_print (mips_double_register_type (), raw_buffer, 0, 0, |
c906108c SS |
3004 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
3005 | } | |
3006 | else | |
3007 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
3008 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
3009 | /* Else print as integer in hex. */ | |
3010 | else | |
ed9a39eb JM |
3011 | { |
3012 | int offset; | |
3013 | ||
d7449b42 | 3014 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
ed9a39eb JM |
3015 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
3016 | else | |
3017 | offset = 0; | |
361d1df0 | 3018 | |
ed9a39eb JM |
3019 | print_scalar_formatted (raw_buffer + offset, |
3020 | REGISTER_VIRTUAL_TYPE (regnum), | |
3021 | 'x', 0, gdb_stdout); | |
3022 | } | |
c906108c SS |
3023 | } |
3024 | ||
361d1df0 | 3025 | /* Replacement for generic do_registers_info. |
c906108c SS |
3026 | Print regs in pretty columns. */ |
3027 | ||
3028 | static int | |
acdb74a0 | 3029 | do_fp_register_row (int regnum) |
c5aa993b | 3030 | { /* do values for FP (float) regs */ |
dd824b04 | 3031 | char *raw_buffer; |
c906108c SS |
3032 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
3033 | int inv1, inv2, inv3; | |
c5aa993b | 3034 | |
dd824b04 | 3035 | raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c906108c | 3036 | |
dd824b04 | 3037 | if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ()) |
c906108c | 3038 | { |
dd824b04 DJ |
3039 | /* 4-byte registers: we can fit two registers per row. */ |
3040 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
3041 | mips_read_fp_register_single (regnum, raw_buffer); | |
67b2c998 | 3042 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 3043 | |
dd824b04 | 3044 | mips_read_fp_register_single (regnum + 1, raw_buffer); |
67b2c998 | 3045 | flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2); |
dd824b04 DJ |
3046 | |
3047 | mips_read_fp_register_double (regnum, raw_buffer); | |
67b2c998 | 3048 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); |
361d1df0 | 3049 | |
1adad886 AC |
3050 | printf_filtered (" %-5s", REGISTER_NAME (regnum)); |
3051 | if (inv1) | |
3052 | printf_filtered (": <invalid float>"); | |
3053 | else | |
3054 | printf_filtered ("%-17.9g", flt1); | |
3055 | ||
3056 | printf_filtered (" %-5s", REGISTER_NAME (regnum + 1)); | |
3057 | if (inv2) | |
3058 | printf_filtered (": <invalid float>"); | |
3059 | else | |
3060 | printf_filtered ("%-17.9g", flt2); | |
3061 | ||
3062 | printf_filtered (" dbl: "); | |
3063 | if (inv3) | |
3064 | printf_filtered ("<invalid double>"); | |
3065 | else | |
3066 | printf_filtered ("%-24.17g", doub); | |
3067 | printf_filtered ("\n"); | |
3068 | ||
c906108c | 3069 | /* may want to do hex display here (future enhancement) */ |
c5aa993b | 3070 | regnum += 2; |
c906108c SS |
3071 | } |
3072 | else | |
dd824b04 DJ |
3073 | { |
3074 | /* Eight byte registers: print each one as float AND as double. */ | |
3075 | mips_read_fp_register_single (regnum, raw_buffer); | |
67b2c998 | 3076 | flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1); |
c906108c | 3077 | |
dd824b04 | 3078 | mips_read_fp_register_double (regnum, raw_buffer); |
67b2c998 | 3079 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); |
361d1df0 | 3080 | |
1adad886 AC |
3081 | printf_filtered (" %-5s: ", REGISTER_NAME (regnum)); |
3082 | if (inv1) | |
3083 | printf_filtered ("<invalid float>"); | |
3084 | else | |
3085 | printf_filtered ("flt: %-17.9g", flt1); | |
3086 | ||
3087 | printf_filtered (" dbl: "); | |
3088 | if (inv3) | |
3089 | printf_filtered ("<invalid double>"); | |
3090 | else | |
3091 | printf_filtered ("%-24.17g", doub); | |
3092 | ||
3093 | printf_filtered ("\n"); | |
c906108c SS |
3094 | /* may want to do hex display here (future enhancement) */ |
3095 | regnum++; | |
3096 | } | |
3097 | return regnum; | |
3098 | } | |
3099 | ||
3100 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
3101 | ||
3102 | static int | |
acdb74a0 | 3103 | do_gp_register_row (int regnum) |
c906108c SS |
3104 | { |
3105 | /* do values for GP (int) regs */ | |
3106 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
3107 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ | |
3108 | int col, byte; | |
3109 | int start_regnum = regnum; | |
3110 | int numregs = NUM_REGS; | |
3111 | ||
3112 | ||
3113 | /* For GP registers, we print a separate row of names above the vals */ | |
3114 | printf_filtered (" "); | |
3115 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
3116 | { | |
3117 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 3118 | continue; /* unused register */ |
c906108c | 3119 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b JM |
3120 | break; /* end the row: reached FP register */ |
3121 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
c906108c SS |
3122 | REGISTER_NAME (regnum)); |
3123 | col++; | |
3124 | } | |
c5aa993b | 3125 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", |
c906108c SS |
3126 | start_regnum); /* print the R0 to R31 names */ |
3127 | ||
3128 | regnum = start_regnum; /* go back to start of row */ | |
3129 | /* now print the values in hex, 4 or 8 to the row */ | |
3130 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
3131 | { | |
3132 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 3133 | continue; /* unused register */ |
c906108c | 3134 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 3135 | break; /* end row: reached FP register */ |
c906108c | 3136 | /* OK: get the data in raw format. */ |
cda5a58a | 3137 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
c906108c SS |
3138 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
3139 | /* pad small registers */ | |
43e526b9 | 3140 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
3141 | printf_filtered (" "); |
3142 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 3143 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
3144 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
3145 | byte < REGISTER_RAW_SIZE (regnum); | |
3146 | byte++) | |
c906108c SS |
3147 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
3148 | else | |
43e526b9 JM |
3149 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
3150 | byte >= 0; | |
3151 | byte--) | |
c906108c SS |
3152 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
3153 | printf_filtered (" "); | |
3154 | col++; | |
3155 | } | |
c5aa993b | 3156 | if (col > 0) /* ie. if we actually printed anything... */ |
c906108c SS |
3157 | printf_filtered ("\n"); |
3158 | ||
3159 | return regnum; | |
3160 | } | |
3161 | ||
3162 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
3163 | ||
3164 | void | |
acdb74a0 | 3165 | mips_do_registers_info (int regnum, int fpregs) |
c906108c | 3166 | { |
c5aa993b | 3167 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
3168 | { |
3169 | if (*(REGISTER_NAME (regnum)) == '\0') | |
3170 | error ("Not a valid register for the current processor type"); | |
3171 | ||
3172 | mips_print_register (regnum, 0); | |
3173 | printf_filtered ("\n"); | |
3174 | } | |
c5aa993b JM |
3175 | else |
3176 | /* do all (or most) registers */ | |
c906108c SS |
3177 | { |
3178 | regnum = 0; | |
3179 | while (regnum < NUM_REGS) | |
3180 | { | |
c5aa993b JM |
3181 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
3182 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
c906108c SS |
3183 | regnum = do_fp_register_row (regnum); /* FP regs */ |
3184 | else | |
3185 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
3186 | else | |
3187 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ | |
3188 | } | |
3189 | } | |
3190 | } | |
3191 | ||
3192 | /* Return number of args passed to a frame. described by FIP. | |
3193 | Can return -1, meaning no way to tell. */ | |
3194 | ||
3195 | int | |
acdb74a0 | 3196 | mips_frame_num_args (struct frame_info *frame) |
c906108c | 3197 | { |
c906108c SS |
3198 | return -1; |
3199 | } | |
3200 | ||
3201 | /* Is this a branch with a delay slot? */ | |
3202 | ||
a14ed312 | 3203 | static int is_delayed (unsigned long); |
c906108c SS |
3204 | |
3205 | static int | |
acdb74a0 | 3206 | is_delayed (unsigned long insn) |
c906108c SS |
3207 | { |
3208 | int i; | |
3209 | for (i = 0; i < NUMOPCODES; ++i) | |
3210 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
3211 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
3212 | break; | |
3213 | return (i < NUMOPCODES | |
3214 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3215 | | INSN_COND_BRANCH_DELAY | |
3216 | | INSN_COND_BRANCH_LIKELY))); | |
3217 | } | |
3218 | ||
3219 | int | |
acdb74a0 | 3220 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
3221 | { |
3222 | char buf[MIPS_INSTLEN]; | |
3223 | ||
3224 | /* There is no branch delay slot on MIPS16. */ | |
3225 | if (pc_is_mips16 (pc)) | |
3226 | return 0; | |
3227 | ||
3228 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
3229 | /* If error reading memory, guess that it is not a delayed branch. */ | |
3230 | return 0; | |
c5aa993b | 3231 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
3232 | } |
3233 | ||
3234 | ||
3235 | /* Skip the PC past function prologue instructions (32-bit version). | |
3236 | This is a helper function for mips_skip_prologue. */ | |
3237 | ||
3238 | static CORE_ADDR | |
f7b9e9fc | 3239 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 3240 | { |
c5aa993b JM |
3241 | t_inst inst; |
3242 | CORE_ADDR end_pc; | |
3243 | int seen_sp_adjust = 0; | |
3244 | int load_immediate_bytes = 0; | |
3245 | ||
3246 | /* Skip the typical prologue instructions. These are the stack adjustment | |
3247 | instruction and the instructions that save registers on the stack | |
3248 | or in the gcc frame. */ | |
3249 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
3250 | { | |
3251 | unsigned long high_word; | |
c906108c | 3252 | |
c5aa993b JM |
3253 | inst = mips_fetch_instruction (pc); |
3254 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 3255 | |
c5aa993b JM |
3256 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
3257 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
3258 | seen_sp_adjust = 1; | |
3259 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
3260 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
3261 | seen_sp_adjust = 1; | |
3262 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
3263 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
3264 | && (inst & 0x001F0000)) /* reg != $zero */ | |
3265 | continue; | |
3266 | ||
3267 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
3268 | continue; | |
3269 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
3270 | /* sx reg,n($s8) */ | |
3271 | continue; /* reg != $zero */ | |
3272 | ||
3273 | /* move $s8,$sp. With different versions of gas this will be either | |
3274 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
3275 | Accept any one of these. */ | |
3276 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3277 | continue; | |
3278 | ||
3279 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
3280 | continue; | |
3281 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
3282 | continue; | |
3283 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
3284 | continue; | |
3285 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3286 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
3287 | continue; | |
3288 | /* The following instructions load $at or $t0 with an immediate | |
3289 | value in preparation for a stack adjustment via | |
3290 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
3291 | a local variable, so we accept them only before a stack adjustment | |
3292 | instruction was seen. */ | |
3293 | else if (!seen_sp_adjust) | |
3294 | { | |
3295 | if (high_word == 0x3c01 || /* lui $at,n */ | |
3296 | high_word == 0x3c08) /* lui $t0,n */ | |
3297 | { | |
3298 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
3299 | continue; | |
3300 | } | |
3301 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
3302 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
3303 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
3304 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
3305 | { | |
3306 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
3307 | continue; | |
3308 | } | |
3309 | else | |
3310 | break; | |
3311 | } | |
3312 | else | |
3313 | break; | |
c906108c SS |
3314 | } |
3315 | ||
c5aa993b JM |
3316 | /* In a frameless function, we might have incorrectly |
3317 | skipped some load immediate instructions. Undo the skipping | |
3318 | if the load immediate was not followed by a stack adjustment. */ | |
3319 | if (load_immediate_bytes && !seen_sp_adjust) | |
3320 | pc -= load_immediate_bytes; | |
3321 | return pc; | |
c906108c SS |
3322 | } |
3323 | ||
3324 | /* Skip the PC past function prologue instructions (16-bit version). | |
3325 | This is a helper function for mips_skip_prologue. */ | |
3326 | ||
3327 | static CORE_ADDR | |
f7b9e9fc | 3328 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 3329 | { |
c5aa993b JM |
3330 | CORE_ADDR end_pc; |
3331 | int extend_bytes = 0; | |
3332 | int prev_extend_bytes; | |
c906108c | 3333 | |
c5aa993b JM |
3334 | /* Table of instructions likely to be found in a function prologue. */ |
3335 | static struct | |
c906108c SS |
3336 | { |
3337 | unsigned short inst; | |
3338 | unsigned short mask; | |
c5aa993b JM |
3339 | } |
3340 | table[] = | |
3341 | { | |
c906108c | 3342 | { |
c5aa993b JM |
3343 | 0x6300, 0xff00 |
3344 | } | |
3345 | , /* addiu $sp,offset */ | |
3346 | { | |
3347 | 0xfb00, 0xff00 | |
3348 | } | |
3349 | , /* daddiu $sp,offset */ | |
3350 | { | |
3351 | 0xd000, 0xf800 | |
3352 | } | |
3353 | , /* sw reg,n($sp) */ | |
3354 | { | |
3355 | 0xf900, 0xff00 | |
3356 | } | |
3357 | , /* sd reg,n($sp) */ | |
3358 | { | |
3359 | 0x6200, 0xff00 | |
3360 | } | |
3361 | , /* sw $ra,n($sp) */ | |
3362 | { | |
3363 | 0xfa00, 0xff00 | |
3364 | } | |
3365 | , /* sd $ra,n($sp) */ | |
3366 | { | |
3367 | 0x673d, 0xffff | |
3368 | } | |
3369 | , /* move $s1,sp */ | |
3370 | { | |
3371 | 0xd980, 0xff80 | |
3372 | } | |
3373 | , /* sw $a0-$a3,n($s1) */ | |
3374 | { | |
3375 | 0x6704, 0xff1c | |
3376 | } | |
3377 | , /* move reg,$a0-$a3 */ | |
3378 | { | |
3379 | 0xe809, 0xf81f | |
3380 | } | |
3381 | , /* entry pseudo-op */ | |
3382 | { | |
3383 | 0x0100, 0xff00 | |
3384 | } | |
3385 | , /* addiu $s1,$sp,n */ | |
3386 | { | |
3387 | 0, 0 | |
3388 | } /* end of table marker */ | |
3389 | }; | |
3390 | ||
3391 | /* Skip the typical prologue instructions. These are the stack adjustment | |
3392 | instruction and the instructions that save registers on the stack | |
3393 | or in the gcc frame. */ | |
3394 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
3395 | { | |
3396 | unsigned short inst; | |
3397 | int i; | |
c906108c | 3398 | |
c5aa993b | 3399 | inst = mips_fetch_instruction (pc); |
c906108c | 3400 | |
c5aa993b JM |
3401 | /* Normally we ignore an extend instruction. However, if it is |
3402 | not followed by a valid prologue instruction, we must adjust | |
3403 | the pc back over the extend so that it won't be considered | |
3404 | part of the prologue. */ | |
3405 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
3406 | { | |
3407 | extend_bytes = MIPS16_INSTLEN; | |
3408 | continue; | |
3409 | } | |
3410 | prev_extend_bytes = extend_bytes; | |
3411 | extend_bytes = 0; | |
c906108c | 3412 | |
c5aa993b JM |
3413 | /* Check for other valid prologue instructions besides extend. */ |
3414 | for (i = 0; table[i].mask != 0; i++) | |
3415 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
3416 | break; | |
3417 | if (table[i].mask != 0) /* it was in table? */ | |
3418 | continue; /* ignore it */ | |
3419 | else | |
3420 | /* non-prologue */ | |
3421 | { | |
3422 | /* Return the current pc, adjusted backwards by 2 if | |
3423 | the previous instruction was an extend. */ | |
3424 | return pc - prev_extend_bytes; | |
3425 | } | |
c906108c SS |
3426 | } |
3427 | return pc; | |
3428 | } | |
3429 | ||
3430 | /* To skip prologues, I use this predicate. Returns either PC itself | |
3431 | if the code at PC does not look like a function prologue; otherwise | |
3432 | returns an address that (if we're lucky) follows the prologue. If | |
3433 | LENIENT, then we must skip everything which is involved in setting | |
3434 | up the frame (it's OK to skip more, just so long as we don't skip | |
3435 | anything which might clobber the registers which are being saved. | |
3436 | We must skip more in the case where part of the prologue is in the | |
3437 | delay slot of a non-prologue instruction). */ | |
3438 | ||
3439 | CORE_ADDR | |
f7b9e9fc | 3440 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
3441 | { |
3442 | /* See if we can determine the end of the prologue via the symbol table. | |
3443 | If so, then return either PC, or the PC after the prologue, whichever | |
3444 | is greater. */ | |
3445 | ||
3446 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
3447 | ||
3448 | if (post_prologue_pc != 0) | |
3449 | return max (pc, post_prologue_pc); | |
3450 | ||
3451 | /* Can't determine prologue from the symbol table, need to examine | |
3452 | instructions. */ | |
3453 | ||
3454 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 3455 | return mips16_skip_prologue (pc); |
c906108c | 3456 | else |
f7b9e9fc | 3457 | return mips32_skip_prologue (pc); |
c906108c | 3458 | } |
c906108c | 3459 | |
7a292a7a SS |
3460 | /* Determine how a return value is stored within the MIPS register |
3461 | file, given the return type `valtype'. */ | |
3462 | ||
3463 | struct return_value_word | |
3464 | { | |
3465 | int len; | |
3466 | int reg; | |
3467 | int reg_offset; | |
3468 | int buf_offset; | |
3469 | }; | |
3470 | ||
7a292a7a | 3471 | static void |
acdb74a0 AC |
3472 | return_value_location (struct type *valtype, |
3473 | struct return_value_word *hi, | |
3474 | struct return_value_word *lo) | |
7a292a7a SS |
3475 | { |
3476 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 3477 | |
7a292a7a SS |
3478 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
3479 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
3480 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
3481 | { | |
3482 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3483 | { | |
3484 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 3485 | spread them across a floating-point register pair. */ |
d7449b42 AC |
3486 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
3487 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
3488 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
7a292a7a SS |
3489 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) |
3490 | ? 4 : 0); | |
3491 | hi->reg_offset = lo->reg_offset; | |
3492 | lo->reg = FP0_REGNUM + 0; | |
3493 | hi->reg = FP0_REGNUM + 1; | |
3494 | lo->len = 4; | |
3495 | hi->len = 4; | |
3496 | } | |
3497 | else | |
3498 | { | |
3499 | /* The floating point value fits in a single floating-point | |
c5aa993b | 3500 | register. */ |
d7449b42 | 3501 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
3502 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 |
3503 | && len == 4) | |
3504 | ? 4 : 0); | |
3505 | lo->reg = FP0_REGNUM; | |
3506 | lo->len = len; | |
3507 | lo->buf_offset = 0; | |
3508 | hi->len = 0; | |
3509 | hi->reg_offset = 0; | |
3510 | hi->buf_offset = 0; | |
3511 | hi->reg = 0; | |
3512 | } | |
3513 | } | |
3514 | else | |
3515 | { | |
3516 | /* Locate a result possibly spread across two registers. */ | |
3517 | int regnum = 2; | |
3518 | lo->reg = regnum + 0; | |
3519 | hi->reg = regnum + 1; | |
d7449b42 | 3520 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
3521 | && len < MIPS_SAVED_REGSIZE) |
3522 | { | |
3523 | /* "un-left-justify" the value in the low register */ | |
3524 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
3525 | lo->len = len; | |
3526 | hi->reg_offset = 0; | |
3527 | hi->len = 0; | |
3528 | } | |
d7449b42 | 3529 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
3530 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
3531 | && len < MIPS_SAVED_REGSIZE * 2 | |
3532 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
3533 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3534 | { | |
3535 | /* "un-left-justify" the value spread across two registers. */ | |
3536 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
3537 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
3538 | hi->reg_offset = 0; | |
3539 | hi->len = len - lo->len; | |
3540 | } | |
3541 | else | |
3542 | { | |
3543 | /* Only perform a partial copy of the second register. */ | |
3544 | lo->reg_offset = 0; | |
3545 | hi->reg_offset = 0; | |
3546 | if (len > MIPS_SAVED_REGSIZE) | |
3547 | { | |
3548 | lo->len = MIPS_SAVED_REGSIZE; | |
3549 | hi->len = len - MIPS_SAVED_REGSIZE; | |
3550 | } | |
3551 | else | |
3552 | { | |
3553 | lo->len = len; | |
3554 | hi->len = 0; | |
3555 | } | |
3556 | } | |
d7449b42 | 3557 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
3558 | && REGISTER_RAW_SIZE (regnum) == 8 |
3559 | && MIPS_SAVED_REGSIZE == 4) | |
3560 | { | |
3561 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 3562 | of the register is being used */ |
7a292a7a SS |
3563 | lo->reg_offset += 4; |
3564 | hi->reg_offset += 4; | |
3565 | } | |
3566 | lo->buf_offset = 0; | |
3567 | hi->buf_offset = lo->len; | |
3568 | } | |
3569 | } | |
3570 | ||
3571 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
3572 | copy its value into `valbuf'. */ | |
3573 | ||
c906108c | 3574 | void |
acdb74a0 AC |
3575 | mips_extract_return_value (struct type *valtype, |
3576 | char regbuf[REGISTER_BYTES], | |
3577 | char *valbuf) | |
c906108c | 3578 | { |
7a292a7a SS |
3579 | struct return_value_word lo; |
3580 | struct return_value_word hi; | |
99567b1b | 3581 | return_value_location (valtype, &hi, &lo); |
7a292a7a SS |
3582 | |
3583 | memcpy (valbuf + lo.buf_offset, | |
3584 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
3585 | lo.len); | |
3586 | ||
3587 | if (hi.len > 0) | |
3588 | memcpy (valbuf + hi.buf_offset, | |
3589 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
3590 | hi.len); | |
c906108c SS |
3591 | } |
3592 | ||
7a292a7a SS |
3593 | /* Given a return value in `valbuf' with a type `valtype', write it's |
3594 | value into the appropriate register. */ | |
3595 | ||
c906108c | 3596 | void |
acdb74a0 | 3597 | mips_store_return_value (struct type *valtype, char *valbuf) |
c906108c | 3598 | { |
7a292a7a SS |
3599 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
3600 | struct return_value_word lo; | |
3601 | struct return_value_word hi; | |
99567b1b | 3602 | return_value_location (valtype, &hi, &lo); |
7a292a7a SS |
3603 | |
3604 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3605 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3606 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
3607 | raw_buffer, | |
3608 | REGISTER_RAW_SIZE (lo.reg)); | |
c5aa993b | 3609 | |
7a292a7a SS |
3610 | if (hi.len > 0) |
3611 | { | |
3612 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3613 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3614 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
3615 | raw_buffer, | |
3616 | REGISTER_RAW_SIZE (hi.reg)); | |
3617 | } | |
c906108c SS |
3618 | } |
3619 | ||
3620 | /* Exported procedure: Is PC in the signal trampoline code */ | |
3621 | ||
3622 | int | |
acdb74a0 | 3623 | in_sigtramp (CORE_ADDR pc, char *ignore) |
c906108c SS |
3624 | { |
3625 | if (sigtramp_address == 0) | |
3626 | fixup_sigtramp (); | |
3627 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
3628 | } | |
3629 | ||
a5ea2558 AC |
3630 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
3631 | used for all MIPS-specific commands. */ | |
3632 | ||
a5ea2558 | 3633 | static void |
acdb74a0 | 3634 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
3635 | { |
3636 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
3637 | } | |
3638 | ||
a5ea2558 | 3639 | static void |
acdb74a0 | 3640 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
3641 | { |
3642 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
3643 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
3644 | } | |
3645 | ||
c906108c SS |
3646 | /* Commands to show/set the MIPS FPU type. */ |
3647 | ||
c906108c | 3648 | static void |
acdb74a0 | 3649 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 3650 | { |
c906108c SS |
3651 | char *fpu; |
3652 | switch (MIPS_FPU_TYPE) | |
3653 | { | |
3654 | case MIPS_FPU_SINGLE: | |
3655 | fpu = "single-precision"; | |
3656 | break; | |
3657 | case MIPS_FPU_DOUBLE: | |
3658 | fpu = "double-precision"; | |
3659 | break; | |
3660 | case MIPS_FPU_NONE: | |
3661 | fpu = "absent (none)"; | |
3662 | break; | |
93d56215 AC |
3663 | default: |
3664 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
3665 | } |
3666 | if (mips_fpu_type_auto) | |
3667 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
3668 | fpu); | |
3669 | else | |
3670 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
3671 | fpu); | |
3672 | } | |
3673 | ||
3674 | ||
c906108c | 3675 | static void |
acdb74a0 | 3676 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
3677 | { |
3678 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
3679 | show_mipsfpu_command (args, from_tty); | |
3680 | } | |
3681 | ||
c906108c | 3682 | static void |
acdb74a0 | 3683 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
3684 | { |
3685 | mips_fpu_type = MIPS_FPU_SINGLE; | |
3686 | mips_fpu_type_auto = 0; | |
9e364162 | 3687 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
3688 | } |
3689 | ||
c906108c | 3690 | static void |
acdb74a0 | 3691 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
3692 | { |
3693 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
3694 | mips_fpu_type_auto = 0; | |
9e364162 | 3695 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
3696 | } |
3697 | ||
c906108c | 3698 | static void |
acdb74a0 | 3699 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
3700 | { |
3701 | mips_fpu_type = MIPS_FPU_NONE; | |
3702 | mips_fpu_type_auto = 0; | |
9e364162 | 3703 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
3704 | } |
3705 | ||
c906108c | 3706 | static void |
acdb74a0 | 3707 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
3708 | { |
3709 | mips_fpu_type_auto = 1; | |
3710 | } | |
3711 | ||
3712 | /* Command to set the processor type. */ | |
3713 | ||
3714 | void | |
acdb74a0 | 3715 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
3716 | { |
3717 | int i; | |
3718 | ||
3719 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
3720 | { | |
3721 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
3722 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3723 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
3724 | ||
3725 | /* Restore the value. */ | |
4fcf66da | 3726 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
3727 | |
3728 | return; | |
3729 | } | |
c5aa993b | 3730 | |
c906108c SS |
3731 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
3732 | { | |
3733 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
3734 | /* Restore its value. */ | |
4fcf66da | 3735 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
3736 | } |
3737 | } | |
3738 | ||
3739 | static void | |
acdb74a0 | 3740 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
3741 | { |
3742 | } | |
3743 | ||
3744 | /* Modify the actual processor type. */ | |
3745 | ||
3746 | int | |
acdb74a0 | 3747 | mips_set_processor_type (char *str) |
c906108c | 3748 | { |
1012bd0e | 3749 | int i; |
c906108c SS |
3750 | |
3751 | if (str == NULL) | |
3752 | return 0; | |
3753 | ||
3754 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3755 | { | |
3756 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
3757 | { | |
3758 | mips_processor_type = str; | |
cce74817 | 3759 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 3760 | return 1; |
c906108c SS |
3761 | /* FIXME tweak fpu flag too */ |
3762 | } | |
3763 | } | |
3764 | ||
3765 | return 0; | |
3766 | } | |
3767 | ||
3768 | /* Attempt to identify the particular processor model by reading the | |
3769 | processor id. */ | |
3770 | ||
3771 | char * | |
acdb74a0 | 3772 | mips_read_processor_type (void) |
c906108c SS |
3773 | { |
3774 | CORE_ADDR prid; | |
3775 | ||
3776 | prid = read_register (PRID_REGNUM); | |
3777 | ||
3778 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 3779 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
3780 | |
3781 | return NULL; | |
3782 | } | |
3783 | ||
3784 | /* Just like reinit_frame_cache, but with the right arguments to be | |
3785 | callable as an sfunc. */ | |
3786 | ||
3787 | static void | |
acdb74a0 AC |
3788 | reinit_frame_cache_sfunc (char *args, int from_tty, |
3789 | struct cmd_list_element *c) | |
c906108c SS |
3790 | { |
3791 | reinit_frame_cache (); | |
3792 | } | |
3793 | ||
3794 | int | |
acdb74a0 | 3795 | gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
3796 | { |
3797 | mips_extra_func_info_t proc_desc; | |
3798 | ||
3799 | /* Search for the function containing this address. Set the low bit | |
3800 | of the address when searching, in case we were given an even address | |
3801 | that is the start of a 16-bit function. If we didn't do this, | |
3802 | the search would fail because the symbol table says the function | |
3803 | starts at an odd address, i.e. 1 byte past the given address. */ | |
3804 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
3805 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
3806 | ||
3807 | /* Make an attempt to determine if this is a 16-bit function. If | |
3808 | the procedure descriptor exists and the address therein is odd, | |
3809 | it's definitely a 16-bit function. Otherwise, we have to just | |
3810 | guess that if the address passed in is odd, it's 16-bits. */ | |
3811 | if (proc_desc) | |
361d1df0 | 3812 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? |
65c11066 | 3813 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c | 3814 | else |
361d1df0 | 3815 | info->mach = pc_is_mips16 (memaddr) ? |
65c11066 | 3816 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c SS |
3817 | |
3818 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 3819 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 3820 | |
c906108c | 3821 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 3822 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
3823 | return print_insn_big_mips (memaddr, info); |
3824 | else | |
3825 | return print_insn_little_mips (memaddr, info); | |
3826 | } | |
3827 | ||
3828 | /* Old-style breakpoint macros. | |
3829 | The IDT board uses an unusual breakpoint value, and sometimes gets | |
3830 | confused when it sees the usual MIPS breakpoint instruction. */ | |
3831 | ||
3832 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} | |
3833 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} | |
3834 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} | |
3835 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} | |
3836 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} | |
3837 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} | |
3838 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} | |
3839 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} | |
3840 | ||
3841 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
3842 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
3843 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
3844 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
3845 | (if necessary) to point to the actual memory location where the | |
3846 | breakpoint should be inserted. */ | |
3847 | ||
f4f9705a | 3848 | const unsigned char * |
acdb74a0 | 3849 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 3850 | { |
d7449b42 | 3851 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
3852 | { |
3853 | if (pc_is_mips16 (*pcptr)) | |
3854 | { | |
1012bd0e EZ |
3855 | static unsigned char mips16_big_breakpoint[] = |
3856 | MIPS16_BIG_BREAKPOINT; | |
c906108c | 3857 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 3858 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
3859 | return mips16_big_breakpoint; |
3860 | } | |
3861 | else | |
3862 | { | |
1012bd0e EZ |
3863 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
3864 | static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; | |
3865 | static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
c906108c | 3866 | |
c5aa993b | 3867 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
3868 | |
3869 | if (strcmp (target_shortname, "mips") == 0) | |
3870 | return idt_big_breakpoint; | |
3871 | else if (strcmp (target_shortname, "ddb") == 0 | |
3872 | || strcmp (target_shortname, "pmon") == 0 | |
3873 | || strcmp (target_shortname, "lsi") == 0) | |
3874 | return pmon_big_breakpoint; | |
3875 | else | |
3876 | return big_breakpoint; | |
3877 | } | |
3878 | } | |
3879 | else | |
3880 | { | |
3881 | if (pc_is_mips16 (*pcptr)) | |
3882 | { | |
1012bd0e EZ |
3883 | static unsigned char mips16_little_breakpoint[] = |
3884 | MIPS16_LITTLE_BREAKPOINT; | |
c906108c | 3885 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 3886 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
3887 | return mips16_little_breakpoint; |
3888 | } | |
3889 | else | |
3890 | { | |
1012bd0e EZ |
3891 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; |
3892 | static unsigned char pmon_little_breakpoint[] = | |
3893 | PMON_LITTLE_BREAKPOINT; | |
3894 | static unsigned char idt_little_breakpoint[] = | |
3895 | IDT_LITTLE_BREAKPOINT; | |
c906108c | 3896 | |
c5aa993b | 3897 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
3898 | |
3899 | if (strcmp (target_shortname, "mips") == 0) | |
3900 | return idt_little_breakpoint; | |
3901 | else if (strcmp (target_shortname, "ddb") == 0 | |
3902 | || strcmp (target_shortname, "pmon") == 0 | |
3903 | || strcmp (target_shortname, "lsi") == 0) | |
3904 | return pmon_little_breakpoint; | |
3905 | else | |
3906 | return little_breakpoint; | |
3907 | } | |
3908 | } | |
3909 | } | |
3910 | ||
3911 | /* If PC is in a mips16 call or return stub, return the address of the target | |
3912 | PC, which is either the callee or the caller. There are several | |
3913 | cases which must be handled: | |
3914 | ||
3915 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 3916 | target PC is in $31 ($ra). |
c906108c | 3917 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 3918 | and the target PC is in $2. |
c906108c | 3919 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
3920 | before the jal instruction, this is effectively a call stub |
3921 | and the the target PC is in $2. Otherwise this is effectively | |
3922 | a return stub and the target PC is in $18. | |
c906108c SS |
3923 | |
3924 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
3925 | gory details. | |
3926 | ||
3927 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 3928 | */ |
c906108c SS |
3929 | |
3930 | CORE_ADDR | |
acdb74a0 | 3931 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
3932 | { |
3933 | char *name; | |
3934 | CORE_ADDR start_addr; | |
3935 | ||
3936 | /* Find the starting address and name of the function containing the PC. */ | |
3937 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
3938 | return 0; | |
3939 | ||
3940 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
3941 | target PC is in $31 ($ra). */ | |
3942 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3943 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 3944 | return read_signed_register (RA_REGNUM); |
c906108c SS |
3945 | |
3946 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3947 | { | |
3948 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
3949 | and the target PC is in $2. */ | |
3950 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 3951 | return read_signed_register (2); |
c906108c SS |
3952 | |
3953 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
3954 | before the jal instruction, this is effectively a call stub |
3955 | and the the target PC is in $2. Otherwise this is effectively | |
3956 | a return stub and the target PC is in $18. */ | |
c906108c SS |
3957 | else if (name[19] == 's' || name[19] == 'd') |
3958 | { | |
3959 | if (pc == start_addr) | |
3960 | { | |
3961 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
3962 | stub. Such a stub for a function bar might have a name |
3963 | like __fn_stub_bar, and might look like this: | |
3964 | mfc1 $4,$f13 | |
3965 | mfc1 $5,$f12 | |
3966 | mfc1 $6,$f15 | |
3967 | mfc1 $7,$f14 | |
3968 | la $1,bar (becomes a lui/addiu pair) | |
3969 | jr $1 | |
3970 | So scan down to the lui/addi and extract the target | |
3971 | address from those two instructions. */ | |
c906108c | 3972 | |
6c997a34 | 3973 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
3974 | t_inst inst; |
3975 | int i; | |
3976 | ||
3977 | /* See if the name of the target function is __fn_stub_*. */ | |
3978 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
3979 | return target_pc; | |
3980 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
3981 | && strcmp (name, "etext") != 0 | |
3982 | && strcmp (name, "_etext") != 0) | |
3983 | return target_pc; | |
3984 | ||
3985 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
3986 | The limit on the search is arbitrarily set to 20 |
3987 | instructions. FIXME. */ | |
c906108c SS |
3988 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
3989 | { | |
c5aa993b JM |
3990 | inst = mips_fetch_instruction (target_pc); |
3991 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
3992 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
3993 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
3994 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
3995 | } |
3996 | ||
3997 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
3998 | return target_pc; | |
3999 | } | |
4000 | else | |
4001 | /* This is the 'return' part of a call stub. The return | |
4002 | address is in $r18. */ | |
6c997a34 | 4003 | return read_signed_register (18); |
c906108c SS |
4004 | } |
4005 | } | |
c5aa993b | 4006 | return 0; /* not a stub */ |
c906108c SS |
4007 | } |
4008 | ||
4009 | ||
4010 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
4011 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
4012 | ||
4013 | int | |
acdb74a0 | 4014 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
4015 | { |
4016 | CORE_ADDR start_addr; | |
4017 | ||
4018 | /* Find the starting address of the function containing the PC. If the | |
4019 | caller didn't give us a name, look it up at the same time. */ | |
4020 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
4021 | return 0; | |
4022 | ||
4023 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4024 | { | |
4025 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
4026 | if (name[19] >= '0' && name[19] <= '9') | |
4027 | return 1; | |
4028 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 4029 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
4030 | else if (name[19] == 's' || name[19] == 'd') |
4031 | return pc == start_addr; | |
4032 | } | |
4033 | ||
c5aa993b | 4034 | return 0; /* not a stub */ |
c906108c SS |
4035 | } |
4036 | ||
4037 | ||
4038 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
4039 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
4040 | ||
4041 | int | |
acdb74a0 | 4042 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
4043 | { |
4044 | CORE_ADDR start_addr; | |
4045 | ||
4046 | /* Find the starting address of the function containing the PC. */ | |
4047 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
4048 | return 0; | |
4049 | ||
4050 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
4051 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4052 | || strcmp (name, "__mips16_ret_df") == 0) | |
4053 | return 1; | |
4054 | ||
4055 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 4056 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
4057 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
4058 | && (name[19] == 's' || name[19] == 'd') | |
4059 | && pc != start_addr) | |
4060 | return 1; | |
4061 | ||
c5aa993b | 4062 | return 0; /* not a stub */ |
c906108c SS |
4063 | } |
4064 | ||
4065 | ||
4066 | /* Return non-zero if the PC is in a library helper function that should | |
4067 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
4068 | ||
4069 | int | |
acdb74a0 | 4070 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
4071 | { |
4072 | char *name; | |
4073 | ||
4074 | /* Find the starting address and name of the function containing the PC. */ | |
4075 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
4076 | return 0; | |
4077 | ||
4078 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
4079 | that we want to ignore. */ | |
4080 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
4081 | || strcmp (name, "__mips16_ret_df") == 0); | |
4082 | } | |
4083 | ||
4084 | ||
4085 | /* Return a location where we can set a breakpoint that will be hit | |
4086 | when an inferior function call returns. This is normally the | |
4087 | program's entry point. Executables that don't have an entry | |
4088 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
4089 | whose address is the location where the breakpoint should be placed. */ | |
4090 | ||
4091 | CORE_ADDR | |
acdb74a0 | 4092 | mips_call_dummy_address (void) |
c906108c SS |
4093 | { |
4094 | struct minimal_symbol *sym; | |
4095 | ||
4096 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
4097 | if (sym) | |
4098 | return SYMBOL_VALUE_ADDRESS (sym); | |
4099 | else | |
4100 | return entry_point_address (); | |
4101 | } | |
4102 | ||
4103 | ||
9dcb560c | 4104 | /* If the current gcc for this target does not produce correct debugging |
b9a8e3bf JB |
4105 | information for float parameters, both prototyped and unprototyped, then |
4106 | define this macro. This forces gdb to always assume that floats are | |
4107 | passed as doubles and then converted in the callee. | |
4108 | ||
4109 | For the mips chip, it appears that the debug info marks the parameters as | |
4110 | floats regardless of whether the function is prototyped, but the actual | |
4111 | values are passed as doubles for the non-prototyped case and floats for | |
4112 | the prototyped case. Thus we choose to make the non-prototyped case work | |
4113 | for C and break the prototyped case, since the non-prototyped case is | |
4114 | probably much more common. (FIXME). */ | |
4115 | ||
4116 | static int | |
4117 | mips_coerce_float_to_double (struct type *formal, struct type *actual) | |
4118 | { | |
4119 | return current_language->la_language == language_c; | |
4120 | } | |
4121 | ||
47a8d4ba AC |
4122 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
4123 | the register stored on the stack (32) is different to its real raw | |
4124 | size (64). The below ensures that registers are fetched from the | |
4125 | stack using their ABI size and then stored into the RAW_BUFFER | |
4126 | using their raw size. | |
4127 | ||
4128 | The alternative to adding this function would be to add an ABI | |
4129 | macro - REGISTER_STACK_SIZE(). */ | |
4130 | ||
4131 | static void | |
acdb74a0 AC |
4132 | mips_get_saved_register (char *raw_buffer, |
4133 | int *optimized, | |
4134 | CORE_ADDR *addrp, | |
4135 | struct frame_info *frame, | |
4136 | int regnum, | |
4137 | enum lval_type *lval) | |
47a8d4ba AC |
4138 | { |
4139 | CORE_ADDR addr; | |
4140 | ||
4141 | if (!target_has_registers) | |
4142 | error ("No registers."); | |
4143 | ||
4144 | /* Normal systems don't optimize out things with register numbers. */ | |
4145 | if (optimized != NULL) | |
4146 | *optimized = 0; | |
4147 | addr = find_saved_register (frame, regnum); | |
4148 | if (addr != 0) | |
4149 | { | |
4150 | if (lval != NULL) | |
4151 | *lval = lval_memory; | |
4152 | if (regnum == SP_REGNUM) | |
4153 | { | |
4154 | if (raw_buffer != NULL) | |
4155 | { | |
4156 | /* Put it back in target format. */ | |
4157 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
4158 | (LONGEST) addr); | |
4159 | } | |
4160 | if (addrp != NULL) | |
4161 | *addrp = 0; | |
4162 | return; | |
4163 | } | |
4164 | if (raw_buffer != NULL) | |
4165 | { | |
4166 | LONGEST val; | |
4167 | if (regnum < 32) | |
4168 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
4169 | saved. */ | |
4170 | val = read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
4171 | else | |
4172 | val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum)); | |
4173 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); | |
4174 | } | |
4175 | } | |
4176 | else | |
4177 | { | |
4178 | if (lval != NULL) | |
4179 | *lval = lval_register; | |
4180 | addr = REGISTER_BYTE (regnum); | |
4181 | if (raw_buffer != NULL) | |
4182 | read_register_gen (regnum, raw_buffer); | |
4183 | } | |
4184 | if (addrp != NULL) | |
4185 | *addrp = addr; | |
4186 | } | |
2acceee2 | 4187 | |
f7b9e9fc AC |
4188 | /* Immediately after a function call, return the saved pc. |
4189 | Can't always go through the frames for this because on some machines | |
4190 | the new frame is not set up until the new function executes | |
4191 | some instructions. */ | |
4192 | ||
4193 | static CORE_ADDR | |
4194 | mips_saved_pc_after_call (struct frame_info *frame) | |
4195 | { | |
6c997a34 | 4196 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
4197 | } |
4198 | ||
4199 | ||
88c72b7d AC |
4200 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
4201 | REGNUM */ | |
4202 | ||
4203 | static int | |
4204 | mips_stab_reg_to_regnum (int num) | |
4205 | { | |
4206 | if (num < 32) | |
4207 | return num; | |
361d1df0 | 4208 | else |
88c72b7d AC |
4209 | return num + FP0_REGNUM - 38; |
4210 | } | |
4211 | ||
4212 | /* Convert a ecoff register number to a gdb REGNUM */ | |
4213 | ||
4214 | static int | |
4215 | mips_ecoff_reg_to_regnum (int num) | |
4216 | { | |
4217 | if (num < 32) | |
4218 | return num; | |
4219 | else | |
4220 | return num + FP0_REGNUM - 32; | |
4221 | } | |
4222 | ||
fc0c74b1 AC |
4223 | /* Convert an integer into an address. By first converting the value |
4224 | into a pointer and then extracting it signed, the address is | |
4225 | guarenteed to be correctly sign extended. */ | |
4226 | ||
4227 | static CORE_ADDR | |
4228 | mips_integer_to_address (struct type *type, void *buf) | |
4229 | { | |
4230 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
4231 | LONGEST val = unpack_long (type, buf); | |
4232 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
4233 | return extract_signed_integer (tmp, | |
4234 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
4235 | } | |
4236 | ||
caaa3122 DJ |
4237 | static void |
4238 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4239 | { | |
4240 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4241 | const char *name = bfd_get_section_name (abfd, sect); | |
4242 | ||
4243 | if (*abip != MIPS_ABI_UNKNOWN) | |
4244 | return; | |
4245 | ||
4246 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4247 | return; | |
4248 | ||
4249 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4250 | *abip = MIPS_ABI_O32; | |
4251 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4252 | *abip = MIPS_ABI_N32; | |
4253 | else if (strcmp (name, ".mdebug.abiO64") == 0) | |
4254 | *abip = MIPS_ABI_O64; | |
4255 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4256 | *abip = MIPS_ABI_EABI32; | |
4257 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4258 | *abip = MIPS_ABI_EABI64; | |
4259 | else | |
4260 | warning ("unsupported ABI %s.", name + 8); | |
4261 | } | |
4262 | ||
2e4ebe70 DJ |
4263 | static enum mips_abi |
4264 | global_mips_abi (void) | |
4265 | { | |
4266 | int i; | |
4267 | ||
4268 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4269 | if (mips_abi_strings[i] == mips_abi_string) | |
4270 | return (enum mips_abi) i; | |
4271 | ||
4272 | internal_error (__FILE__, __LINE__, | |
4273 | "unknown ABI string"); | |
4274 | } | |
4275 | ||
c2d11a7d | 4276 | static struct gdbarch * |
acdb74a0 AC |
4277 | mips_gdbarch_init (struct gdbarch_info info, |
4278 | struct gdbarch_list *arches) | |
c2d11a7d JM |
4279 | { |
4280 | static LONGEST mips_call_dummy_words[] = | |
4281 | {0}; | |
4282 | struct gdbarch *gdbarch; | |
4283 | struct gdbarch_tdep *tdep; | |
4284 | int elf_flags; | |
2e4ebe70 | 4285 | enum mips_abi mips_abi, found_abi, wanted_abi; |
70f80edf | 4286 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
c2d11a7d | 4287 | |
1d06468c EZ |
4288 | /* Reset the disassembly info, in case it was set to something |
4289 | non-default. */ | |
4290 | tm_print_insn_info.flavour = bfd_target_unknown_flavour; | |
4291 | tm_print_insn_info.arch = bfd_arch_unknown; | |
4292 | tm_print_insn_info.mach = 0; | |
4293 | ||
70f80edf JT |
4294 | elf_flags = 0; |
4295 | ||
4296 | if (info.abfd) | |
4297 | { | |
4298 | /* First of all, extract the elf_flags, if available. */ | |
4299 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
4300 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
4301 | ||
4302 | /* Try to determine the OS ABI of the object we are loading. If | |
4303 | we end up with `unknown', just leave it that way. */ | |
4304 | osabi = gdbarch_lookup_osabi (info.abfd); | |
4305 | } | |
c2d11a7d | 4306 | |
0dadbba0 AC |
4307 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
4308 | switch ((elf_flags & EF_MIPS_ABI)) | |
4309 | { | |
4310 | case E_MIPS_ABI_O32: | |
4311 | mips_abi = MIPS_ABI_O32; | |
4312 | break; | |
4313 | case E_MIPS_ABI_O64: | |
4314 | mips_abi = MIPS_ABI_O64; | |
4315 | break; | |
4316 | case E_MIPS_ABI_EABI32: | |
4317 | mips_abi = MIPS_ABI_EABI32; | |
4318 | break; | |
4319 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 4320 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
4321 | break; |
4322 | default: | |
acdb74a0 AC |
4323 | if ((elf_flags & EF_MIPS_ABI2)) |
4324 | mips_abi = MIPS_ABI_N32; | |
4325 | else | |
4326 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
4327 | break; |
4328 | } | |
acdb74a0 | 4329 | |
caaa3122 DJ |
4330 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
4331 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
4332 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
4333 | ||
2e4ebe70 DJ |
4334 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
4335 | Use the ABI from the last architecture if there is one. */ | |
4336 | if (info.abfd == NULL && arches != NULL) | |
4337 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
4338 | ||
bf64bfd6 AC |
4339 | /* Try the architecture for any hint of the corect ABI */ |
4340 | if (mips_abi == MIPS_ABI_UNKNOWN | |
4341 | && info.bfd_arch_info != NULL | |
4342 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4343 | { | |
4344 | switch (info.bfd_arch_info->mach) | |
4345 | { | |
4346 | case bfd_mach_mips3900: | |
4347 | mips_abi = MIPS_ABI_EABI32; | |
4348 | break; | |
4349 | case bfd_mach_mips4100: | |
4350 | case bfd_mach_mips5000: | |
4351 | mips_abi = MIPS_ABI_EABI64; | |
4352 | break; | |
1d06468c EZ |
4353 | case bfd_mach_mips8000: |
4354 | case bfd_mach_mips10000: | |
4355 | mips_abi = MIPS_ABI_N32; | |
4356 | break; | |
bf64bfd6 AC |
4357 | } |
4358 | } | |
2e4ebe70 | 4359 | |
0dadbba0 AC |
4360 | #ifdef MIPS_DEFAULT_ABI |
4361 | if (mips_abi == MIPS_ABI_UNKNOWN) | |
4362 | mips_abi = MIPS_DEFAULT_ABI; | |
4363 | #endif | |
4b9b3959 | 4364 | |
2e4ebe70 DJ |
4365 | if (mips_abi == MIPS_ABI_UNKNOWN) |
4366 | mips_abi = MIPS_ABI_O32; | |
4367 | ||
4368 | /* Now that we have found what the ABI for this binary would be, | |
4369 | check whether the user is overriding it. */ | |
4370 | found_abi = mips_abi; | |
4371 | wanted_abi = global_mips_abi (); | |
4372 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
4373 | mips_abi = wanted_abi; | |
4374 | ||
4b9b3959 AC |
4375 | if (gdbarch_debug) |
4376 | { | |
4377 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 4378 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 4379 | elf_flags); |
4b9b3959 AC |
4380 | fprintf_unfiltered (gdb_stdlog, |
4381 | "mips_gdbarch_init: mips_abi = %d\n", | |
4382 | mips_abi); | |
2e4ebe70 DJ |
4383 | fprintf_unfiltered (gdb_stdlog, |
4384 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
4385 | found_abi); | |
4b9b3959 | 4386 | } |
0dadbba0 | 4387 | |
c2d11a7d JM |
4388 | /* try to find a pre-existing architecture */ |
4389 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
4390 | arches != NULL; | |
4391 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4392 | { | |
4393 | /* MIPS needs to be pedantic about which ABI the object is | |
4394 | using. */ | |
9103eae0 | 4395 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 4396 | continue; |
9103eae0 | 4397 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 4398 | continue; |
70f80edf JT |
4399 | if (gdbarch_tdep (arches->gdbarch)->osabi == osabi) |
4400 | return arches->gdbarch; | |
c2d11a7d JM |
4401 | } |
4402 | ||
4403 | /* Need a new architecture. Fill in a target specific vector. */ | |
4404 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4405 | gdbarch = gdbarch_alloc (&info, tdep); | |
4406 | tdep->elf_flags = elf_flags; | |
70f80edf | 4407 | tdep->osabi = osabi; |
c2d11a7d | 4408 | |
46cd78fb | 4409 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
4410 | set_gdbarch_short_bit (gdbarch, 16); |
4411 | set_gdbarch_int_bit (gdbarch, 32); | |
4412 | set_gdbarch_float_bit (gdbarch, 32); | |
4413 | set_gdbarch_double_bit (gdbarch, 64); | |
4414 | set_gdbarch_long_double_bit (gdbarch, 64); | |
46cd78fb | 4415 | set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size); |
2e4ebe70 | 4416 | tdep->found_abi = found_abi; |
0dadbba0 | 4417 | tdep->mips_abi = mips_abi; |
1d06468c | 4418 | |
0dadbba0 | 4419 | switch (mips_abi) |
c2d11a7d | 4420 | { |
0dadbba0 | 4421 | case MIPS_ABI_O32: |
a5ea2558 | 4422 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 4423 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 4424 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
4425 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
4426 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
0dadbba0 | 4427 | tdep->mips_regs_have_home_p = 1; |
5213ab06 | 4428 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4429 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4430 | set_gdbarch_long_bit (gdbarch, 32); |
4431 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4432 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4433 | break; | |
0dadbba0 | 4434 | case MIPS_ABI_O64: |
a5ea2558 | 4435 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 4436 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 4437 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
4438 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
4439 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
0dadbba0 | 4440 | tdep->mips_regs_have_home_p = 1; |
5213ab06 | 4441 | tdep->gdb_target_is_mips64 = 1; |
361d1df0 | 4442 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4443 | set_gdbarch_long_bit (gdbarch, 32); |
4444 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4445 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4446 | break; | |
0dadbba0 | 4447 | case MIPS_ABI_EABI32: |
a5ea2558 | 4448 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 4449 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 4450 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
4451 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4452 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4453 | tdep->mips_regs_have_home_p = 0; |
5213ab06 | 4454 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4455 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4456 | set_gdbarch_long_bit (gdbarch, 32); |
4457 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4458 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4459 | break; | |
0dadbba0 | 4460 | case MIPS_ABI_EABI64: |
a5ea2558 | 4461 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 4462 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 4463 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
4464 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4465 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4466 | tdep->mips_regs_have_home_p = 0; |
5213ab06 | 4467 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 4468 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4469 | set_gdbarch_long_bit (gdbarch, 64); |
4470 | set_gdbarch_ptr_bit (gdbarch, 64); | |
4471 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4472 | break; | |
0dadbba0 | 4473 | case MIPS_ABI_N32: |
0dadbba0 AC |
4474 | tdep->mips_default_saved_regsize = 4; |
4475 | tdep->mips_default_stack_argsize = 8; | |
4476 | tdep->mips_fp_register_double = 1; | |
acdb74a0 AC |
4477 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4478 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4479 | tdep->mips_regs_have_home_p = 0; |
5213ab06 | 4480 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4481 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
4482 | set_gdbarch_long_bit (gdbarch, 32); |
4483 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4484 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1d06468c EZ |
4485 | |
4486 | /* Set up the disassembler info, so that we get the right | |
4487 | register names from libopcodes. */ | |
4488 | tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
4489 | tm_print_insn_info.arch = bfd_arch_mips; | |
4490 | if (info.bfd_arch_info != NULL | |
4491 | && info.bfd_arch_info->arch == bfd_arch_mips | |
4492 | && info.bfd_arch_info->mach) | |
4493 | tm_print_insn_info.mach = info.bfd_arch_info->mach; | |
4494 | else | |
4495 | tm_print_insn_info.mach = bfd_mach_mips8000; | |
0dadbba0 | 4496 | break; |
c2d11a7d | 4497 | default: |
2e4ebe70 DJ |
4498 | internal_error (__FILE__, __LINE__, |
4499 | "unknown ABI in switch"); | |
c2d11a7d JM |
4500 | } |
4501 | ||
a5ea2558 AC |
4502 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
4503 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
4504 | comment: | |
4505 | ||
4506 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
4507 | flag in object files because to do so would make it impossible to | |
4508 | link with libraries compiled without "-gp32". This is | |
4509 | unnecessarily restrictive. | |
361d1df0 | 4510 | |
a5ea2558 AC |
4511 | We could solve this problem by adding "-gp32" multilibs to gcc, |
4512 | but to set this flag before gcc is built with such multilibs will | |
4513 | break too many systems.'' | |
4514 | ||
4515 | But even more unhelpfully, the default linker output target for | |
4516 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
4517 | for 64-bit programs - you need to change the ABI to change this, | |
4518 | and not all gcc targets support that currently. Therefore using | |
4519 | this flag to detect 32-bit mode would do the wrong thing given | |
4520 | the current gcc - it would make GDB treat these 64-bit programs | |
4521 | as 32-bit programs by default. */ | |
4522 | ||
c2d11a7d JM |
4523 | /* enable/disable the MIPS FPU */ |
4524 | if (!mips_fpu_type_auto) | |
4525 | tdep->mips_fpu_type = mips_fpu_type; | |
4526 | else if (info.bfd_arch_info != NULL | |
4527 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4528 | switch (info.bfd_arch_info->mach) | |
4529 | { | |
b0069a17 | 4530 | case bfd_mach_mips3900: |
c2d11a7d | 4531 | case bfd_mach_mips4100: |
ed9a39eb | 4532 | case bfd_mach_mips4111: |
c2d11a7d JM |
4533 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
4534 | break; | |
bf64bfd6 AC |
4535 | case bfd_mach_mips4650: |
4536 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
4537 | break; | |
c2d11a7d JM |
4538 | default: |
4539 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4540 | break; | |
4541 | } | |
4542 | else | |
4543 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4544 | ||
4545 | /* MIPS version of register names. NOTE: At present the MIPS | |
4546 | register name management is part way between the old - | |
4547 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
4548 | Further work on it is required. */ | |
4549 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6c997a34 | 4550 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d JM |
4551 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
4552 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
c2d11a7d JM |
4553 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
4554 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
4555 | ||
875e1767 AC |
4556 | /* Add/remove bits from an address. The MIPS needs be careful to |
4557 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
4558 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); | |
4559 | ||
10312cc4 AC |
4560 | /* There's a mess in stack frame creation. See comments in |
4561 | blockframe.c near reference to INIT_FRAME_PC_FIRST. */ | |
4562 | set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
7824d2f2 | 4563 | set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop); |
10312cc4 | 4564 | |
88c72b7d AC |
4565 | /* Map debug register numbers onto internal register numbers. */ |
4566 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); | |
4567 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum); | |
4568 | ||
c2d11a7d JM |
4569 | /* Initialize a frame */ |
4570 | set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); | |
4571 | ||
4572 | /* MIPS version of CALL_DUMMY */ | |
4573 | ||
4574 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
4575 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
4576 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); | |
4577 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
4578 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); | |
4579 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
4580 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
4581 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
4582 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
4583 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); | |
4584 | set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); | |
4585 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); | |
4586 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); | |
4587 | set_gdbarch_push_arguments (gdbarch, mips_push_arguments); | |
4588 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); | |
b9a8e3bf | 4589 | set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double); |
c2d11a7d | 4590 | |
c4093a6a | 4591 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
47a8d4ba | 4592 | set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 4593 | |
f7b9e9fc AC |
4594 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
4595 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
4596 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
4597 | |
4598 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
4599 | set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); | |
4600 | ||
fc0c74b1 AC |
4601 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
4602 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
4603 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf JT |
4604 | |
4605 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
4606 | gdbarch_init_osabi (info, gdbarch, osabi); | |
4607 | ||
4b9b3959 AC |
4608 | return gdbarch; |
4609 | } | |
4610 | ||
2e4ebe70 DJ |
4611 | static void |
4612 | mips_abi_update (char *ignore_args, int from_tty, | |
4613 | struct cmd_list_element *c) | |
4614 | { | |
4615 | struct gdbarch_info info; | |
4616 | ||
4617 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
4618 | mips_gdbarch_init will take care of the rest. */ | |
4619 | gdbarch_info_init (&info); | |
4620 | gdbarch_update_p (info); | |
4621 | } | |
4622 | ||
4b9b3959 AC |
4623 | static void |
4624 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
4625 | { | |
4626 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4627 | if (tdep != NULL) | |
c2d11a7d | 4628 | { |
acdb74a0 AC |
4629 | int ef_mips_arch; |
4630 | int ef_mips_32bitmode; | |
4631 | /* determine the ISA */ | |
4632 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
4633 | { | |
4634 | case E_MIPS_ARCH_1: | |
4635 | ef_mips_arch = 1; | |
4636 | break; | |
4637 | case E_MIPS_ARCH_2: | |
4638 | ef_mips_arch = 2; | |
4639 | break; | |
4640 | case E_MIPS_ARCH_3: | |
4641 | ef_mips_arch = 3; | |
4642 | break; | |
4643 | case E_MIPS_ARCH_4: | |
93d56215 | 4644 | ef_mips_arch = 4; |
acdb74a0 AC |
4645 | break; |
4646 | default: | |
93d56215 | 4647 | ef_mips_arch = 0; |
acdb74a0 AC |
4648 | break; |
4649 | } | |
4650 | /* determine the size of a pointer */ | |
4651 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
4652 | fprintf_unfiltered (file, |
4653 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 4654 | tdep->elf_flags); |
4b9b3959 | 4655 | fprintf_unfiltered (file, |
acdb74a0 AC |
4656 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
4657 | ef_mips_32bitmode); | |
4658 | fprintf_unfiltered (file, | |
4659 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
4660 | ef_mips_arch); | |
4661 | fprintf_unfiltered (file, | |
4662 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
4663 | tdep->mips_abi, | |
2e4ebe70 | 4664 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
4665 | fprintf_unfiltered (file, |
4666 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
4667 | mips_mask_address_p (), | |
4668 | tdep->default_mask_address_p); | |
c2d11a7d | 4669 | } |
4b9b3959 AC |
4670 | fprintf_unfiltered (file, |
4671 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
4672 | FP_REGISTER_DOUBLE); | |
4673 | fprintf_unfiltered (file, | |
4674 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
4675 | MIPS_DEFAULT_FPU_TYPE, | |
4676 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
4677 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
4678 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
4679 | : "???")); | |
4680 | fprintf_unfiltered (file, | |
4681 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
4682 | MIPS_EABI); | |
4683 | fprintf_unfiltered (file, | |
acdb74a0 AC |
4684 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n", |
4685 | MIPS_LAST_FP_ARG_REGNUM, | |
4686 | MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1); | |
4b9b3959 AC |
4687 | fprintf_unfiltered (file, |
4688 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
4689 | MIPS_FPU_TYPE, | |
4690 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
4691 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
4692 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
4693 | : "???")); | |
4694 | fprintf_unfiltered (file, | |
4695 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
4696 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
4697 | fprintf_unfiltered (file, |
4698 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
4699 | FP_REGISTER_DOUBLE); | |
4700 | fprintf_unfiltered (file, | |
4701 | "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n", | |
4702 | MIPS_REGS_HAVE_HOME_P); | |
4703 | fprintf_unfiltered (file, | |
4704 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
4705 | MIPS_DEFAULT_STACK_ARGSIZE); | |
4706 | fprintf_unfiltered (file, | |
4707 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
4708 | MIPS_STACK_ARGSIZE); | |
4709 | fprintf_unfiltered (file, | |
4710 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
4711 | MIPS_REGSIZE); | |
2475bac3 AC |
4712 | fprintf_unfiltered (file, |
4713 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
4714 | A0_REGNUM); | |
4715 | fprintf_unfiltered (file, | |
4716 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
4717 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
4718 | fprintf_unfiltered (file, | |
4719 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
4720 | XSTRING (ATTACH_DETACH)); | |
4721 | fprintf_unfiltered (file, | |
4722 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
4723 | BADVADDR_REGNUM); | |
4724 | fprintf_unfiltered (file, | |
4725 | "mips_dump_tdep: BIG_BREAKPOINT = delete?\n"); | |
4726 | fprintf_unfiltered (file, | |
4727 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
4728 | CAUSE_REGNUM); | |
4729 | fprintf_unfiltered (file, | |
4730 | "mips_dump_tdep: CPLUS_MARKER = %c\n", | |
4731 | CPLUS_MARKER); | |
4732 | fprintf_unfiltered (file, | |
4733 | "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n", | |
4734 | DEFAULT_MIPS_TYPE); | |
4735 | fprintf_unfiltered (file, | |
4736 | "mips_dump_tdep: DO_REGISTERS_INFO # %s\n", | |
4737 | XSTRING (DO_REGISTERS_INFO)); | |
4738 | fprintf_unfiltered (file, | |
4739 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
4740 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
4741 | fprintf_unfiltered (file, | |
4742 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
4743 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
4744 | fprintf_unfiltered (file, | |
4745 | "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n", | |
4746 | XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM))); | |
4747 | fprintf_unfiltered (file, | |
4748 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
4749 | FCRCS_REGNUM); | |
4750 | fprintf_unfiltered (file, | |
4751 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
4752 | FCRIR_REGNUM); | |
4753 | fprintf_unfiltered (file, | |
4754 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
4755 | FIRST_EMBED_REGNUM); | |
4756 | fprintf_unfiltered (file, | |
4757 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
4758 | FPA0_REGNUM); | |
4759 | fprintf_unfiltered (file, | |
4760 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
4761 | GDB_TARGET_IS_MIPS64); | |
4762 | fprintf_unfiltered (file, | |
4763 | "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n", | |
4764 | XSTRING (GDB_TARGET_MASK_DISAS_PC (PC))); | |
4765 | fprintf_unfiltered (file, | |
4766 | "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n", | |
4767 | XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC))); | |
4768 | fprintf_unfiltered (file, | |
4769 | "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n", | |
4770 | GEN_REG_SAVE_MASK); | |
4771 | fprintf_unfiltered (file, | |
4772 | "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", | |
4773 | XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); | |
4774 | fprintf_unfiltered (file, | |
4775 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
4776 | HI_REGNUM); | |
4777 | fprintf_unfiltered (file, | |
4778 | "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n"); | |
4779 | fprintf_unfiltered (file, | |
4780 | "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n"); | |
4781 | fprintf_unfiltered (file, | |
4782 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
4783 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
4784 | fprintf_unfiltered (file, |
4785 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
4786 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
4787 | fprintf_unfiltered (file, | |
4788 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
4789 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
4790 | fprintf_unfiltered (file, | |
4791 | "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n"); | |
4792 | fprintf_unfiltered (file, | |
4793 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
4794 | LAST_EMBED_REGNUM); | |
4795 | fprintf_unfiltered (file, | |
4796 | "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n"); | |
4797 | fprintf_unfiltered (file, | |
4798 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
4799 | LO_REGNUM); | |
4800 | #ifdef MACHINE_CPROC_FP_OFFSET | |
4801 | fprintf_unfiltered (file, | |
4802 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
4803 | MACHINE_CPROC_FP_OFFSET); | |
4804 | #endif | |
4805 | #ifdef MACHINE_CPROC_PC_OFFSET | |
4806 | fprintf_unfiltered (file, | |
4807 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
4808 | MACHINE_CPROC_PC_OFFSET); | |
4809 | #endif | |
4810 | #ifdef MACHINE_CPROC_SP_OFFSET | |
4811 | fprintf_unfiltered (file, | |
4812 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
4813 | MACHINE_CPROC_SP_OFFSET); | |
4814 | #endif | |
4815 | fprintf_unfiltered (file, | |
4816 | "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n"); | |
4817 | fprintf_unfiltered (file, | |
4818 | "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n"); | |
4819 | fprintf_unfiltered (file, | |
4820 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
4821 | MIPS16_INSTLEN); | |
4822 | fprintf_unfiltered (file, | |
4823 | "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n"); | |
4824 | fprintf_unfiltered (file, | |
4825 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
4826 | fprintf_unfiltered (file, | |
4827 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
4828 | fprintf_unfiltered (file, | |
4829 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
4830 | MIPS_INSTLEN); | |
4831 | fprintf_unfiltered (file, | |
acdb74a0 AC |
4832 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
4833 | MIPS_LAST_ARG_REGNUM, | |
4834 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
4835 | fprintf_unfiltered (file, |
4836 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
4837 | MIPS_NUMREGS); | |
4838 | fprintf_unfiltered (file, | |
4839 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
4840 | fprintf_unfiltered (file, | |
4841 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
4842 | MIPS_SAVED_REGSIZE); | |
4843 | fprintf_unfiltered (file, | |
4844 | "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n"); | |
4845 | fprintf_unfiltered (file, | |
4846 | "mips_dump_tdep: MSYMBOL_SIZE # %s\n", | |
4847 | XSTRING (MSYMBOL_SIZE (MSYM))); | |
4848 | fprintf_unfiltered (file, | |
4849 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
4850 | fprintf_unfiltered (file, | |
4851 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
4852 | fprintf_unfiltered (file, | |
4853 | "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n"); | |
4854 | fprintf_unfiltered (file, | |
4855 | "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n"); | |
4856 | fprintf_unfiltered (file, | |
4857 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
4858 | PRID_REGNUM); | |
4859 | fprintf_unfiltered (file, | |
4860 | "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n", | |
4861 | XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME))); | |
4862 | fprintf_unfiltered (file, | |
4863 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
4864 | fprintf_unfiltered (file, | |
4865 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
4866 | fprintf_unfiltered (file, | |
4867 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
4868 | fprintf_unfiltered (file, | |
4869 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
4870 | fprintf_unfiltered (file, | |
4871 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
4872 | fprintf_unfiltered (file, | |
4873 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
4874 | fprintf_unfiltered (file, | |
4875 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
4876 | fprintf_unfiltered (file, | |
4877 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
4878 | fprintf_unfiltered (file, | |
4879 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
4880 | fprintf_unfiltered (file, | |
4881 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
4882 | fprintf_unfiltered (file, | |
4883 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
4884 | fprintf_unfiltered (file, | |
4885 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
4886 | fprintf_unfiltered (file, | |
4887 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
4888 | PS_REGNUM); | |
4889 | fprintf_unfiltered (file, | |
4890 | "mips_dump_tdep: PUSH_FP_REGNUM = %d\n", | |
4891 | PUSH_FP_REGNUM); | |
4892 | fprintf_unfiltered (file, | |
4893 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
4894 | RA_REGNUM); | |
4895 | fprintf_unfiltered (file, | |
4896 | "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n", | |
4897 | XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
4898 | fprintf_unfiltered (file, | |
4899 | "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n", | |
4900 | XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
4901 | fprintf_unfiltered (file, | |
4902 | "mips_dump_tdep: REGISTER_NAMES = delete?\n"); | |
4903 | fprintf_unfiltered (file, | |
4904 | "mips_dump_tdep: ROUND_DOWN = function?\n"); | |
4905 | fprintf_unfiltered (file, | |
4906 | "mips_dump_tdep: ROUND_UP = function?\n"); | |
4907 | #ifdef SAVED_BYTES | |
4908 | fprintf_unfiltered (file, | |
4909 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
4910 | SAVED_BYTES); | |
4911 | #endif | |
4912 | #ifdef SAVED_FP | |
4913 | fprintf_unfiltered (file, | |
4914 | "mips_dump_tdep: SAVED_FP = %d\n", | |
4915 | SAVED_FP); | |
4916 | #endif | |
4917 | #ifdef SAVED_PC | |
4918 | fprintf_unfiltered (file, | |
4919 | "mips_dump_tdep: SAVED_PC = %d\n", | |
4920 | SAVED_PC); | |
4921 | #endif | |
4922 | fprintf_unfiltered (file, | |
4923 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
4924 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
4925 | fprintf_unfiltered (file, | |
4926 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
4927 | fprintf_unfiltered (file, | |
4928 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
4929 | SIGFRAME_BASE); | |
4930 | fprintf_unfiltered (file, | |
4931 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
4932 | SIGFRAME_FPREGSAVE_OFF); | |
4933 | fprintf_unfiltered (file, | |
4934 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
4935 | SIGFRAME_PC_OFF); | |
4936 | fprintf_unfiltered (file, | |
4937 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
4938 | SIGFRAME_REGSAVE_OFF); | |
4939 | fprintf_unfiltered (file, | |
4940 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
4941 | SIGFRAME_REG_SIZE); | |
4942 | fprintf_unfiltered (file, | |
4943 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
4944 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
4945 | fprintf_unfiltered (file, | |
4946 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
4947 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
4948 | fprintf_unfiltered (file, | |
b0ed3589 AC |
4949 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
4950 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
4951 | fprintf_unfiltered (file, |
4952 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
4953 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
4954 | #ifdef STACK_END_ADDR | |
4955 | fprintf_unfiltered (file, | |
4956 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
4957 | STACK_END_ADDR); | |
4958 | #endif | |
4959 | fprintf_unfiltered (file, | |
4960 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
4961 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
4962 | fprintf_unfiltered (file, | |
4963 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
4964 | STEP_SKIPS_DELAY_P); | |
4965 | fprintf_unfiltered (file, | |
4966 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
4967 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
4968 | fprintf_unfiltered (file, | |
4969 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
4970 | T9_REGNUM); | |
4971 | fprintf_unfiltered (file, | |
4972 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
4973 | fprintf_unfiltered (file, | |
4974 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
4975 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
4976 | fprintf_unfiltered (file, | |
4977 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
4978 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
4979 | fprintf_unfiltered (file, | |
4980 | "mips_dump_tdep: TARGET_MIPS = used?\n"); | |
4981 | fprintf_unfiltered (file, | |
4982 | "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n", | |
4983 | XSTRING (TM_PRINT_INSN_MACH)); | |
4984 | #ifdef TRACE_CLEAR | |
4985 | fprintf_unfiltered (file, | |
4986 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
4987 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
4988 | #endif | |
4989 | #ifdef TRACE_FLAVOR | |
4990 | fprintf_unfiltered (file, | |
4991 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
4992 | TRACE_FLAVOR); | |
4993 | #endif | |
4994 | #ifdef TRACE_FLAVOR_SIZE | |
4995 | fprintf_unfiltered (file, | |
4996 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
4997 | TRACE_FLAVOR_SIZE); | |
4998 | #endif | |
4999 | #ifdef TRACE_SET | |
5000 | fprintf_unfiltered (file, | |
5001 | "mips_dump_tdep: TRACE_SET # %s\n", | |
5002 | XSTRING (TRACE_SET (X,STATE))); | |
5003 | #endif | |
5004 | fprintf_unfiltered (file, | |
5005 | "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n"); | |
5006 | #ifdef UNUSED_REGNUM | |
5007 | fprintf_unfiltered (file, | |
5008 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
5009 | UNUSED_REGNUM); | |
5010 | #endif | |
5011 | fprintf_unfiltered (file, | |
5012 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
5013 | V0_REGNUM); | |
5014 | fprintf_unfiltered (file, | |
5015 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
5016 | (long) VM_MIN_ADDRESS); | |
5017 | #ifdef VX_NUM_REGS | |
5018 | fprintf_unfiltered (file, | |
5019 | "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n", | |
5020 | VX_NUM_REGS); | |
5021 | #endif | |
5022 | fprintf_unfiltered (file, | |
5023 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
5024 | ZERO_REGNUM); | |
5025 | fprintf_unfiltered (file, | |
5026 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
5027 | _PROC_MAGIC_); | |
70f80edf JT |
5028 | |
5029 | fprintf_unfiltered (file, | |
5030 | "mips_dump_tdep: OS ABI = %s\n", | |
5031 | gdbarch_osabi_name (tdep->osabi)); | |
c2d11a7d JM |
5032 | } |
5033 | ||
c906108c | 5034 | void |
acdb74a0 | 5035 | _initialize_mips_tdep (void) |
c906108c SS |
5036 | { |
5037 | static struct cmd_list_element *mipsfpulist = NULL; | |
5038 | struct cmd_list_element *c; | |
5039 | ||
2e4ebe70 DJ |
5040 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
5041 | if (MIPS_ABI_LAST + 1 | |
5042 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
5043 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
5044 | ||
4b9b3959 | 5045 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c5aa993b | 5046 | if (!tm_print_insn) /* Someone may have already set it */ |
c906108c SS |
5047 | tm_print_insn = gdb_print_insn_mips; |
5048 | ||
a5ea2558 AC |
5049 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5050 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
5051 | "Various MIPS specific commands.", | |
5052 | &setmipscmdlist, "set mips ", 0, &setlist); | |
5053 | ||
5054 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
5055 | "Various MIPS specific commands.", | |
5056 | &showmipscmdlist, "show mips ", 0, &showlist); | |
5057 | ||
5058 | /* Allow the user to override the saved register size. */ | |
5059 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
5060 | class_obscure, |
5061 | size_enums, | |
5062 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
5063 | Set size of general purpose registers saved on the stack.\n\ |
5064 | This option can be set to one of:\n\ | |
5065 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
5066 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
5067 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
5068 | saved GP register size from information contained in the executable.\n\ | |
5069 | (default: auto)", | |
1ed2a135 | 5070 | &setmipscmdlist), |
a5ea2558 AC |
5071 | &showmipscmdlist); |
5072 | ||
d929b26f AC |
5073 | /* Allow the user to override the argument stack size. */ |
5074 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
5075 | class_obscure, | |
5076 | size_enums, | |
1ed2a135 | 5077 | &mips_stack_argsize_string, "\ |
d929b26f AC |
5078 | Set the amount of stack space reserved for each argument.\n\ |
5079 | This option can be set to one of:\n\ | |
5080 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
5081 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
5082 | auto - Allow GDB to determine the correct setting from the current\n\ | |
5083 | target and executable (default)", | |
5084 | &setmipscmdlist), | |
5085 | &showmipscmdlist); | |
5086 | ||
2e4ebe70 DJ |
5087 | /* Allow the user to override the ABI. */ |
5088 | c = add_set_enum_cmd | |
5089 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
5090 | "Set the ABI used by this program.\n" | |
5091 | "This option can be set to one of:\n" | |
5092 | " auto - the default ABI associated with the current binary\n" | |
5093 | " o32\n" | |
5094 | " o64\n" | |
5095 | " n32\n" | |
5096 | " eabi32\n" | |
5097 | " eabi64", | |
5098 | &setmipscmdlist); | |
5099 | add_show_from_set (c, &showmipscmdlist); | |
5100 | set_cmd_sfunc (c, mips_abi_update); | |
5101 | ||
c906108c SS |
5102 | /* Let the user turn off floating point and set the fence post for |
5103 | heuristic_proc_start. */ | |
5104 | ||
5105 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
5106 | "Set use of MIPS floating-point coprocessor.", | |
5107 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
5108 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
5109 | "Select single-precision MIPS floating-point coprocessor.", | |
5110 | &mipsfpulist); | |
5111 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 5112 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
5113 | &mipsfpulist); |
5114 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5115 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5116 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5117 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
5118 | "Select no MIPS floating-point coprocessor.", | |
5119 | &mipsfpulist); | |
5120 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
5121 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5122 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5123 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
5124 | "Select MIPS floating-point coprocessor automatically.", | |
5125 | &mipsfpulist); | |
5126 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
5127 | "Show current use of MIPS floating-point coprocessor target.", | |
5128 | &showlist); | |
5129 | ||
c906108c SS |
5130 | /* We really would like to have both "0" and "unlimited" work, but |
5131 | command.c doesn't deal with that. So make it a var_zinteger | |
5132 | because the user can always use "999999" or some such for unlimited. */ | |
5133 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
5134 | (char *) &heuristic_fence_post, | |
5135 | "\ | |
5136 | Set the distance searched for the start of a function.\n\ | |
5137 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
5138 | program for the start of a function. This command sets the distance of the\n\ | |
5139 | search. The only need to set it is when debugging a stripped executable.", | |
5140 | &setlist); | |
5141 | /* We need to throw away the frame cache when we set this, since it | |
5142 | might change our ability to get backtraces. */ | |
9f60d481 | 5143 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
5144 | add_show_from_set (c, &showlist); |
5145 | ||
5146 | /* Allow the user to control whether the upper bits of 64-bit | |
5147 | addresses should be zeroed. */ | |
e9e68a56 AC |
5148 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
5149 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
5150 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
5151 | allow GDB to determine the correct value.\n", "\ | |
5152 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
5153 | NULL, show_mask_address, | |
5154 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5155 | |
5156 | /* Allow the user to control the size of 32 bit registers within the | |
5157 | raw remote packet. */ | |
5158 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
5159 | class_obscure, | |
5160 | var_boolean, | |
5161 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
5162 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
5163 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
5164 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
5165 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
5166 | &setlist), | |
5167 | &showlist); | |
9ace0497 AC |
5168 | |
5169 | /* Debug this files internals. */ | |
5170 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
5171 | &mips_debug, "Set mips debugging.\n\ | |
5172 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
5173 | &showdebuglist); | |
c906108c | 5174 | } |