Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
c906108c | 56 | |
e0f7ec59 | 57 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 58 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 59 | |
dd824b04 DJ |
60 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
61 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
62 | #define ST0_FR (1 << 26) | |
63 | ||
b0069a17 AC |
64 | /* The sizes of floating point registers. */ |
65 | ||
66 | enum | |
67 | { | |
68 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
69 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
70 | }; | |
71 | ||
0dadbba0 | 72 | |
2e4ebe70 DJ |
73 | static const char *mips_abi_string; |
74 | ||
75 | static const char *mips_abi_strings[] = { | |
76 | "auto", | |
77 | "n32", | |
78 | "o32", | |
28d169de | 79 | "n64", |
2e4ebe70 DJ |
80 | "o64", |
81 | "eabi32", | |
82 | "eabi64", | |
83 | NULL | |
84 | }; | |
85 | ||
cce74817 | 86 | struct frame_extra_info |
6d82d43b AC |
87 | { |
88 | mips_extra_func_info_t proc_desc; | |
89 | int num_args; | |
90 | }; | |
cce74817 | 91 | |
d929b26f AC |
92 | /* Various MIPS ISA options (related to stack analysis) can be |
93 | overridden dynamically. Establish an enum/array for managing | |
94 | them. */ | |
95 | ||
53904c9e AC |
96 | static const char size_auto[] = "auto"; |
97 | static const char size_32[] = "32"; | |
98 | static const char size_64[] = "64"; | |
d929b26f | 99 | |
53904c9e | 100 | static const char *size_enums[] = { |
d929b26f AC |
101 | size_auto, |
102 | size_32, | |
103 | size_64, | |
a5ea2558 AC |
104 | 0 |
105 | }; | |
106 | ||
7a292a7a SS |
107 | /* Some MIPS boards don't support floating point while others only |
108 | support single-precision floating-point operations. See also | |
109 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
110 | |
111 | enum mips_fpu_type | |
6d82d43b AC |
112 | { |
113 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
114 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
115 | MIPS_FPU_NONE /* No floating point. */ | |
116 | }; | |
c906108c SS |
117 | |
118 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
119 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
120 | #endif | |
121 | static int mips_fpu_type_auto = 1; | |
122 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 123 | |
9ace0497 | 124 | static int mips_debug = 0; |
7a292a7a | 125 | |
c2d11a7d JM |
126 | /* MIPS specific per-architecture information */ |
127 | struct gdbarch_tdep | |
6d82d43b AC |
128 | { |
129 | /* from the elf header */ | |
130 | int elf_flags; | |
131 | ||
132 | /* mips options */ | |
133 | enum mips_abi mips_abi; | |
134 | enum mips_abi found_abi; | |
135 | enum mips_fpu_type mips_fpu_type; | |
136 | int mips_last_arg_regnum; | |
137 | int mips_last_fp_arg_regnum; | |
138 | int mips_default_saved_regsize; | |
139 | int mips_fp_register_double; | |
140 | int mips_default_stack_argsize; | |
141 | int default_mask_address_p; | |
142 | /* Is the target using 64-bit raw integer registers but only | |
143 | storing a left-aligned 32-bit value in each? */ | |
144 | int mips64_transfers_32bit_regs_p; | |
145 | /* Indexes for various registers. IRIX and embedded have | |
146 | different values. This contains the "public" fields. Don't | |
147 | add any that do not need to be public. */ | |
148 | const struct mips_regnum *regnum; | |
149 | /* Register names table for the current register set. */ | |
150 | const char **mips_processor_reg_names; | |
151 | }; | |
c2d11a7d | 152 | |
56cea623 AC |
153 | const struct mips_regnum * |
154 | mips_regnum (struct gdbarch *gdbarch) | |
155 | { | |
156 | return gdbarch_tdep (gdbarch)->regnum; | |
157 | } | |
158 | ||
159 | static int | |
160 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
161 | { | |
162 | return mips_regnum (gdbarch)->fp0 + 12; | |
163 | } | |
164 | ||
0dadbba0 | 165 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 166 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 167 | |
c2d11a7d | 168 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 169 | |
c2d11a7d | 170 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 171 | |
c2d11a7d | 172 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 173 | |
95404a3e AC |
174 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
175 | functions to test, set, or clear bit 0 of addresses. */ | |
176 | ||
177 | static CORE_ADDR | |
178 | is_mips16_addr (CORE_ADDR addr) | |
179 | { | |
180 | return ((addr) & 1); | |
181 | } | |
182 | ||
183 | static CORE_ADDR | |
184 | make_mips16_addr (CORE_ADDR addr) | |
185 | { | |
186 | return ((addr) | 1); | |
187 | } | |
188 | ||
189 | static CORE_ADDR | |
190 | unmake_mips16_addr (CORE_ADDR addr) | |
191 | { | |
192 | return ((addr) & ~1); | |
193 | } | |
194 | ||
22540ece AC |
195 | /* Return the contents of register REGNUM as a signed integer. */ |
196 | ||
197 | static LONGEST | |
198 | read_signed_register (int regnum) | |
199 | { | |
719ec221 | 200 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 201 | deprecated_read_register_gen (regnum, buf); |
6d82d43b AC |
202 | return (extract_signed_integer |
203 | (buf, register_size (current_gdbarch, regnum))); | |
22540ece AC |
204 | } |
205 | ||
206 | static LONGEST | |
207 | read_signed_register_pid (int regnum, ptid_t ptid) | |
208 | { | |
209 | ptid_t save_ptid; | |
210 | LONGEST retval; | |
211 | ||
212 | if (ptid_equal (ptid, inferior_ptid)) | |
213 | return read_signed_register (regnum); | |
214 | ||
215 | save_ptid = inferior_ptid; | |
216 | ||
217 | inferior_ptid = ptid; | |
218 | ||
219 | retval = read_signed_register (regnum); | |
220 | ||
221 | inferior_ptid = save_ptid; | |
222 | ||
223 | return retval; | |
224 | } | |
225 | ||
d1973055 KB |
226 | /* Return the MIPS ABI associated with GDBARCH. */ |
227 | enum mips_abi | |
228 | mips_abi (struct gdbarch *gdbarch) | |
229 | { | |
230 | return gdbarch_tdep (gdbarch)->mips_abi; | |
231 | } | |
232 | ||
4246e332 AC |
233 | int |
234 | mips_regsize (struct gdbarch *gdbarch) | |
235 | { | |
236 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
237 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
238 | } | |
239 | ||
480d3dd2 AC |
240 | /* Return the currently configured (or set) saved register size. */ |
241 | ||
242 | static const char *mips_saved_regsize_string = size_auto; | |
243 | ||
d929b26f | 244 | static unsigned int |
480d3dd2 | 245 | mips_saved_regsize (struct gdbarch_tdep *tdep) |
d929b26f AC |
246 | { |
247 | if (mips_saved_regsize_string == size_auto) | |
480d3dd2 | 248 | return tdep->mips_default_saved_regsize; |
d929b26f AC |
249 | else if (mips_saved_regsize_string == size_64) |
250 | return 8; | |
6d82d43b | 251 | else /* if (mips_saved_regsize_string == size_32) */ |
d929b26f AC |
252 | return 4; |
253 | } | |
254 | ||
71b8ef93 | 255 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 256 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 257 | "info" field is used for this purpose. |
5a89d8aa MS |
258 | |
259 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
260 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
261 | minimal symbol to mark it as a 16-bit function | |
262 | ||
f594e5e9 | 263 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 264 | |
5a89d8aa | 265 | static void |
6d82d43b AC |
266 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
267 | { | |
268 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
269 | { | |
270 | MSYMBOL_INFO (msym) = (char *) | |
271 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
272 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
273 | } | |
5a89d8aa MS |
274 | } |
275 | ||
71b8ef93 MS |
276 | static int |
277 | msymbol_is_special (struct minimal_symbol *msym) | |
278 | { | |
279 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
280 | } | |
281 | ||
88658117 AC |
282 | /* XFER a value from the big/little/left end of the register. |
283 | Depending on the size of the value it might occupy the entire | |
284 | register or just part of it. Make an allowance for this, aligning | |
285 | things accordingly. */ | |
286 | ||
287 | static void | |
288 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
289 | enum bfd_endian endian, bfd_byte * in, |
290 | const bfd_byte * out, int buf_offset) | |
88658117 | 291 | { |
88658117 | 292 | int reg_offset = 0; |
a4b8ebc8 | 293 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
294 | /* Need to transfer the left or right part of the register, based on |
295 | the targets byte order. */ | |
88658117 AC |
296 | switch (endian) |
297 | { | |
298 | case BFD_ENDIAN_BIG: | |
719ec221 | 299 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
300 | break; |
301 | case BFD_ENDIAN_LITTLE: | |
302 | reg_offset = 0; | |
303 | break; | |
6d82d43b | 304 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
305 | reg_offset = 0; |
306 | break; | |
307 | default: | |
308 | internal_error (__FILE__, __LINE__, "bad switch"); | |
309 | } | |
310 | if (mips_debug) | |
cb1d2653 AC |
311 | fprintf_unfiltered (gdb_stderr, |
312 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
313 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
314 | if (mips_debug && out != NULL) |
315 | { | |
316 | int i; | |
cb1d2653 | 317 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 318 | for (i = 0; i < length; i++) |
cb1d2653 | 319 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
320 | } |
321 | if (in != NULL) | |
6d82d43b AC |
322 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
323 | in + buf_offset); | |
88658117 | 324 | if (out != NULL) |
6d82d43b AC |
325 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
326 | out + buf_offset); | |
88658117 AC |
327 | if (mips_debug && in != NULL) |
328 | { | |
329 | int i; | |
cb1d2653 | 330 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 331 | for (i = 0; i < length; i++) |
cb1d2653 | 332 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
333 | } |
334 | if (mips_debug) | |
335 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
336 | } | |
337 | ||
dd824b04 DJ |
338 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
339 | compatiblity mode. A return value of 1 means that we have | |
340 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
341 | ||
342 | static int | |
343 | mips2_fp_compat (void) | |
344 | { | |
345 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
346 | meaningful. */ | |
6d82d43b AC |
347 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
348 | 4) | |
dd824b04 DJ |
349 | return 0; |
350 | ||
351 | #if 0 | |
352 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
353 | in all the places we deal with FP registers. PR gdb/413. */ | |
354 | /* Otherwise check the FR bit in the status register - it controls | |
355 | the FP compatiblity mode. If it is clear we are in compatibility | |
356 | mode. */ | |
357 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
358 | return 1; | |
359 | #endif | |
361d1df0 | 360 | |
dd824b04 DJ |
361 | return 0; |
362 | } | |
363 | ||
c2d11a7d JM |
364 | /* Indicate that the ABI makes use of double-precision registers |
365 | provided by the FPU (rather than combining pairs of registers to | |
8fa9cfa1 | 366 | form double-precision values). See also MIPS_FPU_TYPE. */ |
c2d11a7d | 367 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 368 | |
d929b26f AC |
369 | /* The amount of space reserved on the stack for registers. This is |
370 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
371 | data allocated after the registers have run out. */ | |
372 | ||
53904c9e | 373 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
374 | |
375 | static unsigned int | |
480d3dd2 | 376 | mips_stack_argsize (struct gdbarch_tdep *tdep) |
d929b26f AC |
377 | { |
378 | if (mips_stack_argsize_string == size_auto) | |
480d3dd2 | 379 | return tdep->mips_default_stack_argsize; |
d929b26f AC |
380 | else if (mips_stack_argsize_string == size_64) |
381 | return 8; | |
6d82d43b | 382 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
383 | return 4; |
384 | } | |
385 | ||
7a292a7a | 386 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 387 | |
570b8f7c AC |
388 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
389 | struct frame_info *, int); | |
c906108c | 390 | |
a14ed312 | 391 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 392 | |
a14ed312 | 393 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 394 | |
a14ed312 | 395 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 396 | |
570b8f7c AC |
397 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
398 | struct frame_info *next_frame, | |
399 | int cur_frame); | |
c906108c | 400 | |
a14ed312 KB |
401 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
402 | mips_extra_func_info_t proc_desc); | |
c906108c | 403 | |
67b2c998 DJ |
404 | static struct type *mips_float_register_type (void); |
405 | static struct type *mips_double_register_type (void); | |
406 | ||
acdb74a0 AC |
407 | /* The list of available "set mips " and "show mips " commands */ |
408 | ||
409 | static struct cmd_list_element *setmipscmdlist = NULL; | |
410 | static struct cmd_list_element *showmipscmdlist = NULL; | |
411 | ||
5e2e9765 KB |
412 | /* Integer registers 0 thru 31 are handled explicitly by |
413 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
414 | are listed in the followign tables. */ |
415 | ||
6d82d43b AC |
416 | enum |
417 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
418 | |
419 | /* Generic MIPS. */ | |
420 | ||
421 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
422 | "sr", "lo", "hi", "bad", "cause", "pc", |
423 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
424 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
425 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
426 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
427 | "fsr", "fir", "" /*"fp" */ , "", | |
428 | "", "", "", "", "", "", "", "", | |
429 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
430 | }; |
431 | ||
432 | /* Names of IDT R3041 registers. */ | |
433 | ||
434 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
435 | "sr", "lo", "hi", "bad", "cause", "pc", |
436 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
437 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
438 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
439 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
440 | "fsr", "fir", "", /*"fp" */ "", | |
441 | "", "", "bus", "ccfg", "", "", "", "", | |
442 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
443 | }; |
444 | ||
445 | /* Names of tx39 registers. */ | |
446 | ||
447 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
448 | "sr", "lo", "hi", "bad", "cause", "pc", |
449 | "", "", "", "", "", "", "", "", | |
450 | "", "", "", "", "", "", "", "", | |
451 | "", "", "", "", "", "", "", "", | |
452 | "", "", "", "", "", "", "", "", | |
453 | "", "", "", "", | |
454 | "", "", "", "", "", "", "", "", | |
455 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
456 | }; |
457 | ||
458 | /* Names of IRIX registers. */ | |
459 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
460 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
461 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
462 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
463 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
464 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
465 | }; |
466 | ||
cce74817 | 467 | |
5e2e9765 | 468 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 469 | static const char * |
5e2e9765 | 470 | mips_register_name (int regno) |
cce74817 | 471 | { |
691c0433 | 472 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
473 | /* GPR names for all ABIs other than n32/n64. */ |
474 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
475 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
476 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
477 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
478 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
479 | }; |
480 | ||
481 | /* GPR names for n32 and n64 ABIs. */ | |
482 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
483 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
484 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
485 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
486 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
487 | }; |
488 | ||
489 | enum mips_abi abi = mips_abi (current_gdbarch); | |
490 | ||
a4b8ebc8 AC |
491 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
492 | don't make the raw register names visible. */ | |
493 | int rawnum = regno % NUM_REGS; | |
494 | if (regno < NUM_REGS) | |
495 | return ""; | |
496 | ||
5e2e9765 KB |
497 | /* The MIPS integer registers are always mapped from 0 to 31. The |
498 | names of the registers (which reflects the conventions regarding | |
499 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 500 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
501 | { |
502 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 503 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 504 | else |
a4b8ebc8 | 505 | return mips_gpr_names[rawnum]; |
5e2e9765 | 506 | } |
a4b8ebc8 | 507 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
508 | { |
509 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
510 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
511 | } | |
5e2e9765 KB |
512 | else |
513 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 514 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 515 | } |
5e2e9765 | 516 | |
a4b8ebc8 | 517 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 518 | |
a4b8ebc8 AC |
519 | static int |
520 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
521 | struct reggroup *reggroup) | |
522 | { | |
523 | int vector_p; | |
524 | int float_p; | |
525 | int raw_p; | |
526 | int rawnum = regnum % NUM_REGS; | |
527 | int pseudo = regnum / NUM_REGS; | |
528 | if (reggroup == all_reggroup) | |
529 | return pseudo; | |
530 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
531 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
532 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
533 | (gdbarch), as not all architectures are multi-arch. */ | |
534 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 535 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
536 | return 0; |
537 | if (reggroup == float_reggroup) | |
538 | return float_p && pseudo; | |
539 | if (reggroup == vector_reggroup) | |
540 | return vector_p && pseudo; | |
541 | if (reggroup == general_reggroup) | |
542 | return (!vector_p && !float_p) && pseudo; | |
543 | /* Save the pseudo registers. Need to make certain that any code | |
544 | extracting register values from a saved register cache also uses | |
545 | pseudo registers. */ | |
546 | if (reggroup == save_reggroup) | |
547 | return raw_p && pseudo; | |
548 | /* Restore the same pseudo register. */ | |
549 | if (reggroup == restore_reggroup) | |
550 | return raw_p && pseudo; | |
6d82d43b | 551 | return 0; |
a4b8ebc8 AC |
552 | } |
553 | ||
554 | /* Map the symbol table registers which live in the range [1 * | |
555 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 556 | registers. Take care of alignment and size problems. */ |
c5aa993b | 557 | |
a4b8ebc8 AC |
558 | static void |
559 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
560 | int cookednum, void *buf) | |
561 | { | |
47ebcfbe | 562 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 563 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 564 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 565 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
566 | else if (register_size (gdbarch, rawnum) > |
567 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
568 | { |
569 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
570 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
571 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
572 | else | |
573 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
574 | } | |
575 | else | |
576 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
577 | } |
578 | ||
579 | static void | |
6d82d43b AC |
580 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
581 | struct regcache *regcache, int cookednum, | |
582 | const void *buf) | |
a4b8ebc8 | 583 | { |
47ebcfbe | 584 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 585 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 586 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 587 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
588 | else if (register_size (gdbarch, rawnum) > |
589 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
590 | { |
591 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
592 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
593 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
594 | else | |
595 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
596 | } | |
597 | else | |
598 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 599 | } |
c5aa993b | 600 | |
c906108c | 601 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 602 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
603 | |
604 | /* Heuristic_proc_start may hunt through the text section for a long | |
605 | time across a 2400 baud serial line. Allows the user to limit this | |
606 | search. */ | |
607 | ||
608 | static unsigned int heuristic_fence_post = 0; | |
609 | ||
c5aa993b JM |
610 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
611 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
612 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
613 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
614 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
615 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
616 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
617 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
618 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
619 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
620 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
621 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
622 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
623 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
624 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
625 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
626 | ||
627 | struct linked_proc_info | |
6d82d43b AC |
628 | { |
629 | struct mips_extra_func_info info; | |
630 | struct linked_proc_info *next; | |
631 | } | |
c5aa993b | 632 | *linked_proc_desc_table = NULL; |
c906108c | 633 | |
46cd78fb | 634 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
635 | register N. NOTE: This defines the pseudo register type so need to |
636 | rebuild the architecture vector. */ | |
43e526b9 JM |
637 | |
638 | static int mips64_transfers_32bit_regs_p = 0; | |
639 | ||
719ec221 AC |
640 | static void |
641 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
642 | struct cmd_list_element *c) | |
43e526b9 | 643 | { |
719ec221 AC |
644 | struct gdbarch_info info; |
645 | gdbarch_info_init (&info); | |
646 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
647 | instead of relying on globals. Doing that would let generic code | |
648 | handle the search for this specific architecture. */ | |
649 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 650 | { |
719ec221 AC |
651 | mips64_transfers_32bit_regs_p = 0; |
652 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 653 | } |
a4b8ebc8 AC |
654 | } |
655 | ||
47ebcfbe | 656 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 657 | |
ff2e87ac AC |
658 | static int |
659 | mips_convert_register_p (int regnum, struct type *type) | |
660 | { | |
661 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 662 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
663 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
664 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 665 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
666 | } |
667 | ||
42c466d7 | 668 | static void |
ff2e87ac AC |
669 | mips_register_to_value (struct frame_info *frame, int regnum, |
670 | struct type *type, void *to) | |
102182a9 | 671 | { |
7f5f525d AC |
672 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
673 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
674 | } |
675 | ||
42c466d7 | 676 | static void |
ff2e87ac AC |
677 | mips_value_to_register (struct frame_info *frame, int regnum, |
678 | struct type *type, const void *from) | |
102182a9 | 679 | { |
ff2e87ac AC |
680 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
681 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
682 | } |
683 | ||
a4b8ebc8 AC |
684 | /* Return the GDB type object for the "standard" data type of data in |
685 | register REG. */ | |
78fde5f8 KB |
686 | |
687 | static struct type * | |
a4b8ebc8 AC |
688 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
689 | { | |
5ef80fb0 | 690 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
691 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
692 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 693 | { |
5ef80fb0 AC |
694 | /* The floating-point registers raw, or cooked, always match |
695 | mips_regsize(), and also map 1:1, byte for byte. */ | |
696 | switch (gdbarch_byte_order (gdbarch)) | |
697 | { | |
698 | case BFD_ENDIAN_BIG: | |
699 | if (mips_regsize (gdbarch) == 4) | |
700 | return builtin_type_ieee_single_big; | |
701 | else | |
702 | return builtin_type_ieee_double_big; | |
703 | case BFD_ENDIAN_LITTLE: | |
704 | if (mips_regsize (gdbarch) == 4) | |
705 | return builtin_type_ieee_single_little; | |
706 | else | |
707 | return builtin_type_ieee_double_little; | |
708 | case BFD_ENDIAN_UNKNOWN: | |
709 | default: | |
710 | internal_error (__FILE__, __LINE__, "bad switch"); | |
711 | } | |
a6425924 | 712 | } |
6d82d43b AC |
713 | else if (regnum >= |
714 | (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status) | |
5ef80fb0 AC |
715 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) |
716 | /* The pseudo/cooked view of the embedded registers is always | |
717 | 32-bit. The raw view is handled below. */ | |
718 | return builtin_type_int32; | |
719ec221 AC |
719 | else if (regnum >= NUM_REGS && mips_regsize (gdbarch) |
720 | && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
721 | /* The target, while using a 64-bit register buffer, is only | |
722 | transfering 32-bits of each integer register. Reflect this in | |
723 | the cooked/pseudo register value. */ | |
724 | return builtin_type_int32; | |
5ef80fb0 AC |
725 | else if (mips_regsize (gdbarch) == 8) |
726 | /* 64-bit ISA. */ | |
727 | return builtin_type_int64; | |
78fde5f8 | 728 | else |
5ef80fb0 AC |
729 | /* 32-bit ISA. */ |
730 | return builtin_type_int32; | |
78fde5f8 KB |
731 | } |
732 | ||
bcb0cc15 MS |
733 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
734 | ||
735 | static CORE_ADDR | |
736 | mips_read_sp (void) | |
737 | { | |
e227b13c | 738 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
739 | } |
740 | ||
c906108c | 741 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 742 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
743 | |
744 | static int | |
480d3dd2 | 745 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
746 | { |
747 | switch (mask_address_var) | |
748 | { | |
7f19b9a2 | 749 | case AUTO_BOOLEAN_TRUE: |
4014092b | 750 | return 1; |
7f19b9a2 | 751 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
752 | return 0; |
753 | break; | |
7f19b9a2 | 754 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 755 | return tdep->default_mask_address_p; |
4014092b | 756 | default: |
6d82d43b | 757 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 758 | return -1; |
361d1df0 | 759 | } |
4014092b AC |
760 | } |
761 | ||
762 | static void | |
e9e68a56 | 763 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 764 | { |
480d3dd2 | 765 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
766 | switch (mask_address_var) |
767 | { | |
7f19b9a2 | 768 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
769 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
770 | break; | |
7f19b9a2 | 771 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
772 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
773 | break; | |
7f19b9a2 | 774 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
775 | printf_filtered |
776 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
777 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
778 | break; |
779 | default: | |
6d82d43b | 780 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 781 | break; |
361d1df0 | 782 | } |
4014092b | 783 | } |
c906108c | 784 | |
c906108c SS |
785 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
786 | ||
787 | static int | |
788 | pc_is_mips16 (bfd_vma memaddr) | |
789 | { | |
790 | struct minimal_symbol *sym; | |
791 | ||
792 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 793 | if (is_mips16_addr (memaddr)) |
c906108c SS |
794 | return 1; |
795 | ||
796 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
797 | the high bit of the info field. Use this to decide if the function is | |
798 | MIPS16 or normal MIPS. */ | |
799 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
800 | if (sym) | |
71b8ef93 | 801 | return msymbol_is_special (sym); |
c906108c SS |
802 | else |
803 | return 0; | |
804 | } | |
805 | ||
6c997a34 AC |
806 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
807 | all registers should be sign extended for simplicity? */ | |
808 | ||
809 | static CORE_ADDR | |
39f77062 | 810 | mips_read_pc (ptid_t ptid) |
6c997a34 | 811 | { |
b6cb9035 AC |
812 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
813 | } | |
814 | ||
58dfe9ff AC |
815 | static CORE_ADDR |
816 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
817 | { | |
edfae063 AC |
818 | return frame_unwind_register_signed (next_frame, |
819 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
820 | } | |
821 | ||
822 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
823 | dummy frame. The frame ID's base needs to match the TOS value | |
824 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
825 | breakpoint. */ | |
826 | ||
827 | static struct frame_id | |
828 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
829 | { | |
830 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + SP_REGNUM), | |
831 | frame_pc_unwind (next_frame)); | |
58dfe9ff AC |
832 | } |
833 | ||
b6cb9035 AC |
834 | static void |
835 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
836 | { | |
837 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 838 | } |
c906108c SS |
839 | |
840 | /* This returns the PC of the first inst after the prologue. If we can't | |
841 | find the prologue, then return 0. */ | |
842 | ||
843 | static CORE_ADDR | |
6d82d43b | 844 | after_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc) |
c906108c SS |
845 | { |
846 | struct symtab_and_line sal; | |
847 | CORE_ADDR func_addr, func_end; | |
848 | ||
479412cd DJ |
849 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
850 | to read the stack pointer from the current machine state, because | |
851 | the current machine state has nothing to do with the information | |
852 | we need from the proc_desc; and the process may or may not exist | |
853 | right now. */ | |
c906108c | 854 | if (!proc_desc) |
479412cd | 855 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
856 | |
857 | if (proc_desc) | |
858 | { | |
859 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 860 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
861 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
862 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
863 | return 0; | |
864 | } | |
865 | ||
866 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
867 | return 0; /* Unknown */ | |
868 | ||
869 | sal = find_pc_line (func_addr, 0); | |
870 | ||
871 | if (sal.end < func_end) | |
872 | return sal.end; | |
873 | ||
874 | /* The line after the prologue is after the end of the function. In this | |
875 | case, tell the caller to find the prologue the hard way. */ | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
880 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
881 | set the appropriate bit in the general register mask or float register mask | |
882 | to indicate which register is saved. This is a helper function | |
883 | for mips_find_saved_regs. */ | |
884 | ||
885 | static void | |
acdb74a0 AC |
886 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
887 | unsigned long *float_mask) | |
c906108c SS |
888 | { |
889 | int reg; | |
890 | ||
6d82d43b | 891 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ |
c906108c SS |
892 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ |
893 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
894 | { | |
895 | /* It might be possible to use the instruction to | |
c5aa993b JM |
896 | find the offset, rather than the code below which |
897 | is based on things being in a certain order in the | |
898 | frame, but figuring out what the instruction's offset | |
899 | is relative to might be a little tricky. */ | |
c906108c SS |
900 | reg = (inst & 0x001f0000) >> 16; |
901 | *gen_mask |= (1 << reg); | |
902 | } | |
903 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
6d82d43b | 904 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
c5aa993b | 905 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ |
c906108c SS |
906 | |
907 | { | |
908 | reg = ((inst & 0x001f0000) >> 16); | |
909 | *float_mask |= (1 << reg); | |
910 | } | |
911 | } | |
912 | ||
913 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
914 | set the appropriate bit in the general register or float register mask | |
915 | to indicate which register is saved. This is a helper function | |
916 | for mips_find_saved_regs. */ | |
917 | ||
918 | static void | |
acdb74a0 | 919 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 920 | { |
c5aa993b | 921 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
922 | { |
923 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
924 | *gen_mask |= (1 << reg); | |
925 | } | |
c5aa993b | 926 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
927 | { |
928 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
929 | *gen_mask |= (1 << reg); | |
930 | } | |
c5aa993b | 931 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
932 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
933 | *gen_mask |= (1 << RA_REGNUM); | |
934 | } | |
935 | ||
936 | ||
937 | /* Fetch and return instruction from the specified location. If the PC | |
938 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
939 | ||
940 | static t_inst | |
acdb74a0 | 941 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
942 | { |
943 | char buf[MIPS_INSTLEN]; | |
944 | int instlen; | |
945 | int status; | |
946 | ||
947 | if (pc_is_mips16 (addr)) | |
948 | { | |
949 | instlen = MIPS16_INSTLEN; | |
95404a3e | 950 | addr = unmake_mips16_addr (addr); |
c906108c SS |
951 | } |
952 | else | |
c5aa993b | 953 | instlen = MIPS_INSTLEN; |
c906108c SS |
954 | status = read_memory_nobpt (addr, buf, instlen); |
955 | if (status) | |
956 | memory_error (status, addr); | |
957 | return extract_unsigned_integer (buf, instlen); | |
958 | } | |
959 | ||
edfae063 AC |
960 | static ULONGEST |
961 | mips16_fetch_instruction (CORE_ADDR addr) | |
962 | { | |
963 | char buf[MIPS_INSTLEN]; | |
964 | int instlen; | |
965 | int status; | |
966 | ||
967 | instlen = MIPS16_INSTLEN; | |
968 | addr = unmake_mips16_addr (addr); | |
969 | status = read_memory_nobpt (addr, buf, instlen); | |
970 | if (status) | |
971 | memory_error (status, addr); | |
972 | return extract_unsigned_integer (buf, instlen); | |
973 | } | |
974 | ||
975 | static ULONGEST | |
976 | mips32_fetch_instruction (CORE_ADDR addr) | |
977 | { | |
978 | char buf[MIPS_INSTLEN]; | |
979 | int instlen; | |
980 | int status; | |
981 | instlen = MIPS_INSTLEN; | |
982 | status = read_memory_nobpt (addr, buf, instlen); | |
983 | if (status) | |
984 | memory_error (status, addr); | |
985 | return extract_unsigned_integer (buf, instlen); | |
986 | } | |
987 | ||
c906108c SS |
988 | |
989 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
990 | #define mips32_op(x) (x >> 26) |
991 | #define itype_op(x) (x >> 26) | |
992 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 993 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 994 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 995 | |
e135b889 DJ |
996 | #define jtype_op(x) (x >> 26) |
997 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 998 | |
e135b889 DJ |
999 | #define rtype_op(x) (x >> 26) |
1000 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1001 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1002 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1003 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1004 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
1005 | |
1006 | static CORE_ADDR | |
c5aa993b JM |
1007 | mips32_relative_offset (unsigned long inst) |
1008 | { | |
1009 | long x; | |
1010 | x = itype_immediate (inst); | |
1011 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 1012 | { |
c5aa993b | 1013 | x |= 0xffff0000; /* sign extension */ |
c906108c | 1014 | } |
c5aa993b JM |
1015 | x = x << 2; |
1016 | return x; | |
c906108c SS |
1017 | } |
1018 | ||
1019 | /* Determine whate to set a single step breakpoint while considering | |
1020 | branch prediction */ | |
5a89d8aa | 1021 | static CORE_ADDR |
c5aa993b JM |
1022 | mips32_next_pc (CORE_ADDR pc) |
1023 | { | |
1024 | unsigned long inst; | |
1025 | int op; | |
1026 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1027 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1028 | { |
e135b889 | 1029 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1030 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1031 | { |
e135b889 | 1032 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1033 | switch (op) |
1034 | { | |
e135b889 DJ |
1035 | case 0: /* BEQL */ |
1036 | goto equal_branch; | |
1037 | case 1: /* BNEL */ | |
1038 | goto neq_branch; | |
1039 | case 2: /* BLEZL */ | |
1040 | goto less_branch; | |
1041 | case 3: /* BGTZ */ | |
1042 | goto greater_branch; | |
c5aa993b JM |
1043 | default: |
1044 | pc += 4; | |
c906108c SS |
1045 | } |
1046 | } | |
e135b889 | 1047 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1048 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1049 | { |
1050 | int tf = itype_rt (inst) & 0x01; | |
1051 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1052 | int fcrcs = |
1053 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1054 | fp_control_status); | |
e135b889 DJ |
1055 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1056 | ||
1057 | if (((cond >> cnum) & 0x01) == tf) | |
1058 | pc += mips32_relative_offset (inst) + 4; | |
1059 | else | |
1060 | pc += 8; | |
1061 | } | |
c5aa993b JM |
1062 | else |
1063 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1064 | } |
1065 | else | |
c5aa993b JM |
1066 | { /* This gets way messy */ |
1067 | ||
c906108c | 1068 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1069 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1070 | { |
c5aa993b JM |
1071 | case 0: /* SPECIAL */ |
1072 | op = rtype_funct (inst); | |
1073 | switch (op) | |
1074 | { | |
1075 | case 8: /* JR */ | |
1076 | case 9: /* JALR */ | |
6c997a34 AC |
1077 | /* Set PC to that address */ |
1078 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1079 | break; |
1080 | default: | |
1081 | pc += 4; | |
1082 | } | |
1083 | ||
6d82d43b | 1084 | break; /* end SPECIAL */ |
c5aa993b | 1085 | case 1: /* REGIMM */ |
c906108c | 1086 | { |
e135b889 DJ |
1087 | op = itype_rt (inst); /* branch condition */ |
1088 | switch (op) | |
c906108c | 1089 | { |
c5aa993b | 1090 | case 0: /* BLTZ */ |
e135b889 DJ |
1091 | case 2: /* BLTZL */ |
1092 | case 16: /* BLTZAL */ | |
c5aa993b | 1093 | case 18: /* BLTZALL */ |
c906108c | 1094 | less_branch: |
6c997a34 | 1095 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1096 | pc += mips32_relative_offset (inst) + 4; |
1097 | else | |
1098 | pc += 8; /* after the delay slot */ | |
1099 | break; | |
e135b889 | 1100 | case 1: /* BGEZ */ |
c5aa993b JM |
1101 | case 3: /* BGEZL */ |
1102 | case 17: /* BGEZAL */ | |
1103 | case 19: /* BGEZALL */ | |
6c997a34 | 1104 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1105 | pc += mips32_relative_offset (inst) + 4; |
1106 | else | |
1107 | pc += 8; /* after the delay slot */ | |
1108 | break; | |
e135b889 | 1109 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1110 | default: |
1111 | pc += 4; | |
c906108c SS |
1112 | } |
1113 | } | |
6d82d43b | 1114 | break; /* end REGIMM */ |
c5aa993b JM |
1115 | case 2: /* J */ |
1116 | case 3: /* JAL */ | |
1117 | { | |
1118 | unsigned long reg; | |
1119 | reg = jtype_target (inst) << 2; | |
e135b889 | 1120 | /* Upper four bits get never changed... */ |
c5aa993b | 1121 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1122 | } |
c5aa993b JM |
1123 | break; |
1124 | /* FIXME case JALX : */ | |
1125 | { | |
1126 | unsigned long reg; | |
1127 | reg = jtype_target (inst) << 2; | |
1128 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1129 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1130 | } | |
c5aa993b | 1131 | break; /* The new PC will be alternate mode */ |
e135b889 | 1132 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1133 | equal_branch: |
6c997a34 AC |
1134 | if (read_signed_register (itype_rs (inst)) == |
1135 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1136 | pc += mips32_relative_offset (inst) + 4; |
1137 | else | |
1138 | pc += 8; | |
1139 | break; | |
e135b889 | 1140 | case 5: /* BNE, BNEL */ |
c5aa993b | 1141 | neq_branch: |
6c997a34 | 1142 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1143 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1144 | pc += mips32_relative_offset (inst) + 4; |
1145 | else | |
1146 | pc += 8; | |
1147 | break; | |
e135b889 | 1148 | case 6: /* BLEZ, BLEZL */ |
6c997a34 | 1149 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1150 | pc += mips32_relative_offset (inst) + 4; |
1151 | else | |
1152 | pc += 8; | |
1153 | break; | |
1154 | case 7: | |
e135b889 DJ |
1155 | default: |
1156 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1157 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1158 | pc += mips32_relative_offset (inst) + 4; |
1159 | else | |
1160 | pc += 8; | |
1161 | break; | |
c5aa993b JM |
1162 | } /* switch */ |
1163 | } /* else */ | |
1164 | return pc; | |
1165 | } /* mips32_next_pc */ | |
c906108c SS |
1166 | |
1167 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1168 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1169 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1170 | We dont want to set a single step instruction on the extend instruction | |
1171 | either. | |
c5aa993b | 1172 | */ |
c906108c SS |
1173 | |
1174 | /* Lots of mips16 instruction formats */ | |
1175 | /* Predicting jumps requires itype,ritype,i8type | |
1176 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1177 | */ |
c906108c SS |
1178 | enum mips16_inst_fmts |
1179 | { | |
c5aa993b JM |
1180 | itype, /* 0 immediate 5,10 */ |
1181 | ritype, /* 1 5,3,8 */ | |
1182 | rrtype, /* 2 5,3,3,5 */ | |
1183 | rritype, /* 3 5,3,3,5 */ | |
1184 | rrrtype, /* 4 5,3,3,3,2 */ | |
1185 | rriatype, /* 5 5,3,3,1,4 */ | |
1186 | shifttype, /* 6 5,3,3,3,2 */ | |
1187 | i8type, /* 7 5,3,8 */ | |
1188 | i8movtype, /* 8 5,3,3,5 */ | |
1189 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1190 | i64type, /* 10 5,3,8 */ | |
1191 | ri64type, /* 11 5,3,3,5 */ | |
1192 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1193 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1194 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1195 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1196 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1197 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1198 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1199 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1200 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1201 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1202 | }; | |
12f02c2a AC |
1203 | /* I am heaping all the fields of the formats into one structure and |
1204 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1205 | struct upk_mips16 |
6d82d43b AC |
1206 | { |
1207 | CORE_ADDR offset; | |
1208 | unsigned int regx; /* Function in i8 type */ | |
1209 | unsigned int regy; | |
1210 | }; | |
c906108c SS |
1211 | |
1212 | ||
12f02c2a AC |
1213 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1214 | for the bits which make up the immediatate extension. */ | |
c906108c | 1215 | |
12f02c2a AC |
1216 | static CORE_ADDR |
1217 | extended_offset (unsigned int extension) | |
c906108c | 1218 | { |
12f02c2a | 1219 | CORE_ADDR value; |
c5aa993b JM |
1220 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1221 | value = value << 6; | |
1222 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1223 | value = value << 5; | |
1224 | value |= extension & 0x01f; /* extract 4:0 */ | |
1225 | return value; | |
c906108c SS |
1226 | } |
1227 | ||
1228 | /* Only call this function if you know that this is an extendable | |
1229 | instruction, It wont malfunction, but why make excess remote memory references? | |
1230 | If the immediate operands get sign extended or somthing, do it after | |
1231 | the extension is performed. | |
c5aa993b | 1232 | */ |
c906108c SS |
1233 | /* FIXME: Every one of these cases needs to worry about sign extension |
1234 | when the offset is to be used in relative addressing */ | |
1235 | ||
1236 | ||
12f02c2a | 1237 | static unsigned int |
c5aa993b | 1238 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1239 | { |
c5aa993b JM |
1240 | char buf[8]; |
1241 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1242 | target_read_memory (pc, buf, 2); | |
1243 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1244 | } |
1245 | ||
1246 | static void | |
c5aa993b | 1247 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1248 | unsigned int extension, |
1249 | unsigned int inst, | |
6d82d43b | 1250 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1251 | { |
12f02c2a AC |
1252 | CORE_ADDR offset; |
1253 | int regx; | |
1254 | int regy; | |
1255 | switch (insn_format) | |
c906108c | 1256 | { |
c5aa993b | 1257 | case itype: |
c906108c | 1258 | { |
12f02c2a AC |
1259 | CORE_ADDR value; |
1260 | if (extension) | |
c5aa993b JM |
1261 | { |
1262 | value = extended_offset (extension); | |
1263 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1264 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1265 | } |
1266 | else | |
c5aa993b | 1267 | { |
12f02c2a | 1268 | value = inst & 0x7ff; |
c5aa993b | 1269 | /* FIXME : Consider sign extension */ |
c906108c | 1270 | } |
12f02c2a AC |
1271 | offset = value; |
1272 | regx = -1; | |
1273 | regy = -1; | |
c906108c | 1274 | } |
c5aa993b JM |
1275 | break; |
1276 | case ritype: | |
1277 | case i8type: | |
1278 | { /* A register identifier and an offset */ | |
c906108c SS |
1279 | /* Most of the fields are the same as I type but the |
1280 | immediate value is of a different length */ | |
12f02c2a AC |
1281 | CORE_ADDR value; |
1282 | if (extension) | |
c906108c | 1283 | { |
c5aa993b JM |
1284 | value = extended_offset (extension); |
1285 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1286 | value |= inst & 0xff; /* eleven bits from instruction */ |
1287 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1288 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1289 | { | |
1290 | value &= ~0x3fff; /* remove the sign bit */ | |
1291 | value = -value; | |
c906108c SS |
1292 | } |
1293 | } | |
c5aa993b JM |
1294 | else |
1295 | { | |
12f02c2a AC |
1296 | value = inst & 0xff; /* 8 bits */ |
1297 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1298 | /* FIXME: Do sign extension , this format needs it */ |
1299 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1300 | { | |
1301 | value &= 0xef; /* remove the sign bit */ | |
1302 | value = -value; | |
1303 | } | |
c5aa993b | 1304 | } |
12f02c2a AC |
1305 | offset = value; |
1306 | regy = -1; | |
c5aa993b | 1307 | break; |
c906108c | 1308 | } |
c5aa993b | 1309 | case jalxtype: |
c906108c | 1310 | { |
c5aa993b | 1311 | unsigned long value; |
12f02c2a AC |
1312 | unsigned int nexthalf; |
1313 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1314 | value = value << 16; |
1315 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1316 | value |= nexthalf; | |
12f02c2a AC |
1317 | offset = value; |
1318 | regx = -1; | |
1319 | regy = -1; | |
c5aa993b | 1320 | break; |
c906108c SS |
1321 | } |
1322 | default: | |
6d82d43b | 1323 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1324 | } |
12f02c2a AC |
1325 | upk->offset = offset; |
1326 | upk->regx = regx; | |
1327 | upk->regy = regy; | |
c906108c SS |
1328 | } |
1329 | ||
1330 | ||
c5aa993b JM |
1331 | static CORE_ADDR |
1332 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1333 | { |
c5aa993b | 1334 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1335 | } |
1336 | ||
12f02c2a AC |
1337 | static CORE_ADDR |
1338 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1339 | unsigned int extension, unsigned int insn) |
c906108c | 1340 | { |
12f02c2a AC |
1341 | int op = (insn >> 11); |
1342 | switch (op) | |
c906108c | 1343 | { |
6d82d43b | 1344 | case 2: /* Branch */ |
12f02c2a AC |
1345 | { |
1346 | CORE_ADDR offset; | |
1347 | struct upk_mips16 upk; | |
1348 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1349 | offset = upk.offset; | |
1350 | if (offset & 0x800) | |
1351 | { | |
1352 | offset &= 0xeff; | |
1353 | offset = -offset; | |
1354 | } | |
1355 | pc += (offset << 1) + 2; | |
1356 | break; | |
1357 | } | |
6d82d43b | 1358 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1359 | { |
1360 | struct upk_mips16 upk; | |
1361 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1362 | pc = add_offset_16 (pc, upk.offset); | |
1363 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1364 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1365 | else | |
1366 | pc |= 0x01; | |
1367 | break; | |
1368 | } | |
6d82d43b | 1369 | case 4: /* beqz */ |
12f02c2a AC |
1370 | { |
1371 | struct upk_mips16 upk; | |
1372 | int reg; | |
1373 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1374 | reg = read_signed_register (upk.regx); | |
1375 | if (reg == 0) | |
1376 | pc += (upk.offset << 1) + 2; | |
1377 | else | |
1378 | pc += 2; | |
1379 | break; | |
1380 | } | |
6d82d43b | 1381 | case 5: /* bnez */ |
12f02c2a AC |
1382 | { |
1383 | struct upk_mips16 upk; | |
1384 | int reg; | |
1385 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1386 | reg = read_signed_register (upk.regx); | |
1387 | if (reg != 0) | |
1388 | pc += (upk.offset << 1) + 2; | |
1389 | else | |
1390 | pc += 2; | |
1391 | break; | |
1392 | } | |
6d82d43b | 1393 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1394 | { |
1395 | struct upk_mips16 upk; | |
1396 | int reg; | |
1397 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1398 | /* upk.regx contains the opcode */ | |
1399 | reg = read_signed_register (24); /* Test register is 24 */ | |
1400 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1401 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1402 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1403 | pc += (upk.offset << 1) + 2; | |
1404 | else | |
1405 | pc += 2; | |
1406 | break; | |
1407 | } | |
6d82d43b | 1408 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1409 | { |
1410 | struct upk_mips16 upk; | |
1411 | /* upk.fmt = rrtype; */ | |
1412 | op = insn & 0x1f; | |
1413 | if (op == 0) | |
c5aa993b | 1414 | { |
12f02c2a AC |
1415 | int reg; |
1416 | upk.regx = (insn >> 8) & 0x07; | |
1417 | upk.regy = (insn >> 5) & 0x07; | |
1418 | switch (upk.regy) | |
c5aa993b | 1419 | { |
12f02c2a AC |
1420 | case 0: |
1421 | reg = upk.regx; | |
1422 | break; | |
1423 | case 1: | |
1424 | reg = 31; | |
6d82d43b | 1425 | break; /* Function return instruction */ |
12f02c2a AC |
1426 | case 2: |
1427 | reg = upk.regx; | |
1428 | break; | |
1429 | default: | |
1430 | reg = 31; | |
6d82d43b | 1431 | break; /* BOGUS Guess */ |
c906108c | 1432 | } |
12f02c2a | 1433 | pc = read_signed_register (reg); |
c906108c | 1434 | } |
12f02c2a | 1435 | else |
c5aa993b | 1436 | pc += 2; |
12f02c2a AC |
1437 | break; |
1438 | } | |
1439 | case 30: | |
1440 | /* This is an instruction extension. Fetch the real instruction | |
1441 | (which follows the extension) and decode things based on | |
1442 | that. */ | |
1443 | { | |
1444 | pc += 2; | |
1445 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1446 | break; | |
1447 | } | |
1448 | default: | |
1449 | { | |
1450 | pc += 2; | |
1451 | break; | |
1452 | } | |
c906108c | 1453 | } |
c5aa993b | 1454 | return pc; |
12f02c2a | 1455 | } |
c906108c | 1456 | |
5a89d8aa | 1457 | static CORE_ADDR |
12f02c2a AC |
1458 | mips16_next_pc (CORE_ADDR pc) |
1459 | { | |
1460 | unsigned int insn = fetch_mips_16 (pc); | |
1461 | return extended_mips16_next_pc (pc, 0, insn); | |
1462 | } | |
1463 | ||
1464 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1465 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1466 | It works by decoding the current instruction and predicting where a |
1467 | branch will go. This isnt hard because all the data is available. | |
1468 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1469 | CORE_ADDR |
1470 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1471 | { |
c5aa993b JM |
1472 | if (pc & 0x01) |
1473 | return mips16_next_pc (pc); | |
1474 | else | |
1475 | return mips32_next_pc (pc); | |
12f02c2a | 1476 | } |
c906108c | 1477 | |
edfae063 AC |
1478 | struct mips_frame_cache |
1479 | { | |
1480 | CORE_ADDR base; | |
1481 | struct trad_frame_saved_reg *saved_regs; | |
1482 | }; | |
1483 | ||
1484 | ||
1485 | static struct mips_frame_cache * | |
1486 | mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1487 | { | |
1488 | mips_extra_func_info_t proc_desc; | |
1489 | struct mips_frame_cache *cache; | |
1490 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1491 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1492 | /* r0 bit means kernel trap */ | |
1493 | int kernel_trap; | |
1494 | /* What registers have been saved? Bitmasks. */ | |
1495 | unsigned long gen_mask, float_mask; | |
1496 | ||
1497 | if ((*this_cache) != NULL) | |
1498 | return (*this_cache); | |
1499 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1500 | (*this_cache) = cache; | |
1501 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1502 | ||
1503 | /* Get the mdebug proc descriptor. */ | |
1504 | proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame, 1); | |
1505 | if (proc_desc == NULL) | |
1506 | /* I'm not sure how/whether this can happen. Normally when we | |
1507 | can't find a proc_desc, we "synthesize" one using | |
1508 | heuristic_proc_desc and set the saved_regs right away. */ | |
1509 | return cache; | |
1510 | ||
1511 | /* Extract the frame's base. */ | |
1512 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1513 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1514 | ||
1515 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1516 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1517 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1518 | ||
1519 | /* In any frame other than the innermost or a frame interrupted by a | |
1520 | signal, we assume that all registers have been saved. This | |
1521 | assumes that all register saves in a function happen before the | |
1522 | first function call. */ | |
1523 | if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1524 | /* Not sure exactly what kernel_trap means, but if it means the | |
1525 | kernel saves the registers without a prologue doing it, we | |
1526 | better not examine the prologue to see whether registers | |
1527 | have been saved yet. */ | |
1528 | && !kernel_trap) | |
1529 | { | |
1530 | /* We need to figure out whether the registers that the | |
1531 | proc_desc claims are saved have been saved yet. */ | |
1532 | ||
1533 | CORE_ADDR addr; | |
1534 | ||
1535 | /* Bitmasks; set if we have found a save for the register. */ | |
1536 | unsigned long gen_save_found = 0; | |
1537 | unsigned long float_save_found = 0; | |
1538 | int mips16; | |
1539 | ||
1540 | /* If the address is odd, assume this is MIPS16 code. */ | |
1541 | addr = PROC_LOW_ADDR (proc_desc); | |
1542 | mips16 = pc_is_mips16 (addr); | |
1543 | ||
1544 | /* Scan through this function's instructions preceding the | |
1545 | current PC, and look for those that save registers. */ | |
1546 | while (addr < frame_pc_unwind (next_frame)) | |
1547 | { | |
1548 | if (mips16) | |
1549 | { | |
1550 | mips16_decode_reg_save (mips16_fetch_instruction (addr), | |
1551 | &gen_save_found); | |
1552 | addr += MIPS16_INSTLEN; | |
1553 | } | |
1554 | else | |
1555 | { | |
1556 | mips32_decode_reg_save (mips32_fetch_instruction (addr), | |
1557 | &gen_save_found, &float_save_found); | |
1558 | addr += MIPS_INSTLEN; | |
1559 | } | |
1560 | } | |
1561 | gen_mask = gen_save_found; | |
1562 | float_mask = float_save_found; | |
1563 | } | |
1564 | ||
1565 | /* Fill in the offsets for the registers which gen_mask says were | |
1566 | saved. */ | |
1567 | { | |
1568 | CORE_ADDR reg_position = (cache->base | |
1569 | + PROC_REG_OFFSET (proc_desc)); | |
1570 | int ireg; | |
1571 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1572 | if (gen_mask & 0x80000000) | |
1573 | { | |
1574 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
1575 | reg_position -= mips_saved_regsize (tdep); | |
1576 | } | |
1577 | } | |
1578 | ||
1579 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1580 | order of that normally used by gcc. Therefore, we have to fetch | |
1581 | the first instruction of the function, and if it's an entry | |
1582 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
1583 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1584 | { | |
1585 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1586 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1587 | /* entry */ | |
1588 | { | |
1589 | int reg; | |
1590 | int sreg_count = (inst >> 6) & 3; | |
1591 | ||
1592 | /* Check if the ra register was pushed on the stack. */ | |
1593 | CORE_ADDR reg_position = (cache->base | |
1594 | + PROC_REG_OFFSET (proc_desc)); | |
1595 | if (inst & 0x20) | |
1596 | reg_position -= mips_saved_regsize (tdep); | |
1597 | ||
1598 | /* Check if the s0 and s1 registers were pushed on the | |
1599 | stack. */ | |
1600 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1601 | check. */ | |
1602 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1603 | { | |
1604 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
1605 | reg_position -= mips_saved_regsize (tdep); | |
1606 | } | |
1607 | } | |
1608 | } | |
1609 | ||
1610 | /* Fill in the offsets for the registers which float_mask says were | |
1611 | saved. */ | |
1612 | { | |
1613 | CORE_ADDR reg_position = (cache->base | |
1614 | + PROC_FREG_OFFSET (proc_desc)); | |
1615 | int ireg; | |
1616 | /* Fill in the offsets for the float registers which float_mask | |
1617 | says were saved. */ | |
1618 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1619 | if (float_mask & 0x80000000) | |
1620 | { | |
1621 | if (mips_saved_regsize (tdep) == 4 | |
1622 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1623 | { | |
1624 | /* On a big endian 32 bit ABI, floating point registers | |
1625 | are paired to form doubles such that the most | |
1626 | significant part is in $f[N+1] and the least | |
1627 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1628 | registers are also spilled as a pair and stored as a | |
1629 | double. | |
1630 | ||
1631 | When little-endian the least significant part is | |
1632 | stored first leading to the memory order $f[N] and | |
1633 | then $f[N+1]. | |
1634 | ||
1635 | Unfortunately, when big-endian the most significant | |
1636 | part of the double is stored first, and the least | |
1637 | significant is stored second. This leads to the | |
1638 | registers being ordered in memory as firt $f[N+1] and | |
1639 | then $f[N]. | |
1640 | ||
1641 | For the big-endian case make certain that the | |
1642 | addresses point at the correct (swapped) locations | |
1643 | $f[N] and $f[N+1] pair (keep in mind that | |
1644 | reg_position is decremented each time through the | |
1645 | loop). */ | |
1646 | if ((ireg & 1)) | |
1647 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1648 | .addr = reg_position - mips_saved_regsize (tdep); | |
1649 | else | |
1650 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1651 | .addr = reg_position + mips_saved_regsize (tdep); | |
1652 | } | |
1653 | else | |
1654 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1655 | .addr = reg_position; | |
1656 | reg_position -= mips_saved_regsize (tdep); | |
1657 | } | |
1658 | ||
1659 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
1660 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
1661 | } | |
1662 | ||
1663 | /* SP_REGNUM, contains the value and not the address. */ | |
1664 | trad_frame_set_value (cache->saved_regs, NUM_REGS + SP_REGNUM, cache->base); | |
1665 | ||
1666 | return (*this_cache); | |
1667 | } | |
1668 | ||
1669 | static void | |
1670 | mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1671 | struct frame_id *this_id) | |
1672 | { | |
1673 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1674 | this_cache); | |
1675 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1676 | } | |
1677 | ||
1678 | static void | |
1679 | mips_mdebug_frame_prev_register (struct frame_info *next_frame, | |
1680 | void **this_cache, | |
1681 | int regnum, int *optimizedp, | |
1682 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1683 | int *realnump, void *valuep) | |
1684 | { | |
1685 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1686 | this_cache); | |
1687 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
1688 | optimizedp, lvalp, addrp, realnump, valuep); | |
1689 | } | |
1690 | ||
1691 | static const struct frame_unwind mips_mdebug_frame_unwind = | |
1692 | { | |
1693 | NORMAL_FRAME, | |
1694 | mips_mdebug_frame_this_id, | |
1695 | mips_mdebug_frame_prev_register | |
1696 | }; | |
1697 | ||
1698 | static const struct frame_unwind * | |
1699 | mips_mdebug_frame_sniffer (struct frame_info *next_frame) | |
1700 | { | |
1701 | return &mips_mdebug_frame_unwind; | |
1702 | } | |
1703 | ||
1704 | static CORE_ADDR | |
1705 | mips_mdebug_frame_base_address (struct frame_info *next_frame, | |
1706 | void **this_cache) | |
1707 | { | |
1708 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1709 | this_cache); | |
1710 | return info->base; | |
1711 | } | |
1712 | ||
1713 | static const struct frame_base mips_mdebug_frame_base = { | |
1714 | &mips_mdebug_frame_unwind, | |
1715 | mips_mdebug_frame_base_address, | |
1716 | mips_mdebug_frame_base_address, | |
1717 | mips_mdebug_frame_base_address | |
1718 | }; | |
1719 | ||
1720 | static const struct frame_base * | |
1721 | mips_mdebug_frame_base_sniffer (struct frame_info *next_frame) | |
1722 | { | |
1723 | return &mips_mdebug_frame_base; | |
1724 | } | |
1725 | ||
c906108c | 1726 | static CORE_ADDR |
acdb74a0 | 1727 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1728 | { |
a4b8ebc8 AC |
1729 | /* Always a pseudo. */ |
1730 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 1731 | if (fi == NULL) |
c906108c | 1732 | { |
a4b8ebc8 AC |
1733 | LONGEST val; |
1734 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
1735 | return val; | |
f796e4be | 1736 | } |
a4b8ebc8 AC |
1737 | else if ((regno % NUM_REGS) == SP_REGNUM) |
1738 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
1739 | In fact, it is so special that it can even only be fetched | |
1740 | using a raw register number! Once this code as been converted | |
1741 | to frame-unwind the problem goes away. */ | |
1742 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 1743 | else |
a4b8ebc8 | 1744 | return frame_unwind_register_signed (fi, regno); |
64159455 | 1745 | |
c906108c SS |
1746 | } |
1747 | ||
1748 | /* mips_addr_bits_remove - remove useless address bits */ | |
1749 | ||
875e1767 | 1750 | static CORE_ADDR |
acdb74a0 | 1751 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1752 | { |
480d3dd2 | 1753 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
6d82d43b | 1754 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
8fa9cfa1 AC |
1755 | /* This hack is a work-around for existing boards using PMON, the |
1756 | simulator, and any other 64-bit targets that doesn't have true | |
1757 | 64-bit addressing. On these targets, the upper 32 bits of | |
1758 | addresses are ignored by the hardware. Thus, the PC or SP are | |
1759 | likely to have been sign extended to all 1s by instruction | |
1760 | sequences that load 32-bit addresses. For example, a typical | |
1761 | piece of code that loads an address is this: | |
1762 | ||
1763 | lui $r2, <upper 16 bits> | |
1764 | ori $r2, <lower 16 bits> | |
1765 | ||
1766 | But the lui sign-extends the value such that the upper 32 bits | |
1767 | may be all 1s. The workaround is simply to mask off these | |
1768 | bits. In the future, gcc may be changed to support true 64-bit | |
1769 | addressing, and this masking will have to be disabled. */ | |
1770 | return addr &= 0xffffffffUL; | |
1771 | else | |
1772 | return addr; | |
c906108c SS |
1773 | } |
1774 | ||
9022177c DJ |
1775 | /* mips_software_single_step() is called just before we want to resume |
1776 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1777 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1778 | the target of the coming instruction and breakpoint it. |
1779 | ||
1780 | single_step is also called just after the inferior stops. If we had | |
1781 | set up a simulated single-step, we undo our damage. */ | |
1782 | ||
1783 | void | |
1784 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1785 | { | |
1786 | static CORE_ADDR next_pc; | |
1787 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1788 | static binsn_quantum break_mem; | |
1789 | CORE_ADDR pc; | |
1790 | ||
1791 | if (insert_breakpoints_p) | |
1792 | { | |
b6cb9035 | 1793 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
9022177c DJ |
1794 | next_pc = mips_next_pc (pc); |
1795 | ||
1796 | target_insert_breakpoint (next_pc, break_mem); | |
1797 | } | |
1798 | else | |
1799 | target_remove_breakpoint (next_pc, break_mem); | |
1800 | } | |
1801 | ||
c906108c | 1802 | static struct mips_extra_func_info temp_proc_desc; |
fe29b929 KB |
1803 | |
1804 | /* This hack will go away once the get_prev_frame() code has been | |
1805 | modified to set the frame's type first. That is BEFORE init extra | |
1806 | frame info et.al. is called. This is because it will become | |
1807 | possible to skip the init extra info call for sigtramp and dummy | |
1808 | frames. */ | |
1809 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1810 | |
e0f7ec59 AC |
1811 | /* Set a register's saved stack address in temp_saved_regs. If an |
1812 | address has already been set for this register, do nothing; this | |
1813 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
1814 | function prologue. |
1815 | ||
1816 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
1817 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1818 | is used as it is only second range (the ABI instead of ISA | |
1819 | registers) that comes into play when finding saved registers in a | |
1820 | frame. */ | |
c906108c SS |
1821 | |
1822 | static void | |
e0f7ec59 | 1823 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1824 | { |
e0f7ec59 | 1825 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
1826 | { |
1827 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
1828 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
1829 | } | |
c906108c SS |
1830 | } |
1831 | ||
1832 | ||
1833 | /* Test whether the PC points to the return instruction at the | |
1834 | end of a function. */ | |
1835 | ||
c5aa993b | 1836 | static int |
acdb74a0 | 1837 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1838 | { |
1839 | if (pc_is_mips16 (pc)) | |
1840 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1841 | generates a "jr $ra"; other times it generates code to load | |
1842 | the return address from the stack to an accessible register (such | |
1843 | as $a3), then a "jr" using that register. This second case | |
1844 | is almost impossible to distinguish from an indirect jump | |
1845 | used for switch statements, so we don't even try. */ | |
1846 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1847 | else | |
1848 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1849 | } | |
1850 | ||
1851 | ||
1852 | /* This fencepost looks highly suspicious to me. Removing it also | |
1853 | seems suspicious as it could affect remote debugging across serial | |
1854 | lines. */ | |
1855 | ||
1856 | static CORE_ADDR | |
acdb74a0 | 1857 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1858 | { |
c5aa993b JM |
1859 | CORE_ADDR start_pc; |
1860 | CORE_ADDR fence; | |
1861 | int instlen; | |
1862 | int seen_adjsp = 0; | |
c906108c | 1863 | |
c5aa993b JM |
1864 | pc = ADDR_BITS_REMOVE (pc); |
1865 | start_pc = pc; | |
1866 | fence = start_pc - heuristic_fence_post; | |
1867 | if (start_pc == 0) | |
1868 | return 0; | |
c906108c | 1869 | |
6d82d43b | 1870 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
c5aa993b | 1871 | fence = VM_MIN_ADDRESS; |
c906108c | 1872 | |
c5aa993b | 1873 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1874 | |
c5aa993b JM |
1875 | /* search back for previous return */ |
1876 | for (start_pc -= instlen;; start_pc -= instlen) | |
1877 | if (start_pc < fence) | |
1878 | { | |
1879 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1880 | stop_soon, but with this test, at least we |
c5aa993b JM |
1881 | don't print out warnings for every child forked (eg, on |
1882 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1883 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1884 | { |
c5aa993b JM |
1885 | static int blurb_printed = 0; |
1886 | ||
6d82d43b AC |
1887 | warning |
1888 | ("Warning: GDB can't find the start of the function at 0x%s.", | |
1889 | paddr_nz (pc)); | |
c5aa993b JM |
1890 | |
1891 | if (!blurb_printed) | |
c906108c | 1892 | { |
c5aa993b JM |
1893 | /* This actually happens frequently in embedded |
1894 | development, when you first connect to a board | |
1895 | and your stack pointer and pc are nowhere in | |
1896 | particular. This message needs to give people | |
1897 | in that situation enough information to | |
1898 | determine that it's no big deal. */ | |
1899 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1900 | GDB is unable to find the start of the function at 0x%s\n\ |
1901 | and thus can't determine the size of that function's stack frame.\n\ | |
1902 | This means that GDB may be unable to access that stack frame, or\n\ | |
1903 | the frames below it.\n\ | |
1904 | This problem is most likely caused by an invalid program counter or\n\ | |
1905 | stack pointer.\n\ | |
1906 | However, if you think GDB should simply search farther back\n\ | |
1907 | from 0x%s for code which looks like the beginning of a\n\ | |
1908 | function, you can increase the range of the search using the `set\n\ | |
6d82d43b | 1909 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); |
c5aa993b | 1910 | blurb_printed = 1; |
c906108c | 1911 | } |
c906108c SS |
1912 | } |
1913 | ||
c5aa993b JM |
1914 | return 0; |
1915 | } | |
1916 | else if (pc_is_mips16 (start_pc)) | |
1917 | { | |
1918 | unsigned short inst; | |
1919 | ||
1920 | /* On MIPS16, any one of the following is likely to be the | |
1921 | start of a function: | |
1922 | entry | |
1923 | addiu sp,-n | |
1924 | daddiu sp,-n | |
1925 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1926 | inst = mips_fetch_instruction (start_pc); | |
1927 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1928 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1929 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1930 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1931 | break; | |
1932 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1933 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1934 | seen_adjsp = 1; | |
1935 | else | |
1936 | seen_adjsp = 0; | |
1937 | } | |
1938 | else if (mips_about_to_return (start_pc)) | |
1939 | { | |
1940 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1941 | break; | |
1942 | } | |
1943 | ||
c5aa993b | 1944 | return start_pc; |
c906108c SS |
1945 | } |
1946 | ||
1947 | /* Fetch the immediate value from a MIPS16 instruction. | |
1948 | If the previous instruction was an EXTEND, use it to extend | |
1949 | the upper bits of the immediate value. This is a helper function | |
1950 | for mips16_heuristic_proc_desc. */ | |
1951 | ||
1952 | static int | |
acdb74a0 AC |
1953 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1954 | unsigned short inst, /* current instruction */ | |
6d82d43b AC |
1955 | int nbits, /* number of bits in imm field */ |
1956 | int scale, /* scale factor to be applied to imm */ | |
1957 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1958 | { |
1959 | int offset; | |
1960 | ||
1961 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1962 | { | |
1963 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1964 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1965 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1966 | return offset | (inst & 0x1f); | |
1967 | } | |
1968 | else | |
1969 | { | |
1970 | int max_imm = 1 << nbits; | |
1971 | int mask = max_imm - 1; | |
1972 | int sign_bit = max_imm >> 1; | |
1973 | ||
1974 | offset = inst & mask; | |
1975 | if (is_signed && (offset & sign_bit)) | |
1976 | offset = 0 - (max_imm - offset); | |
1977 | return offset * scale; | |
1978 | } | |
1979 | } | |
1980 | ||
1981 | ||
1982 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1983 | stream from start_pc to limit_pc. */ | |
1984 | ||
1985 | static void | |
acdb74a0 AC |
1986 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1987 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1988 | { |
1989 | CORE_ADDR cur_pc; | |
1990 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1991 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1992 | unsigned inst = 0; /* current instruction */ | |
1993 | unsigned entry_inst = 0; /* the entry instruction */ | |
1994 | int reg, offset; | |
480d3dd2 | 1995 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1996 | |
c5aa993b JM |
1997 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1998 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1999 | |
2000 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2001 | { | |
2002 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2003 | the immediate offset extension from it in mips16_get_imm. */ | |
2004 | prev_inst = inst; | |
2005 | ||
2006 | /* Fetch and decode the instruction. */ | |
2007 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2008 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
6d82d43b | 2009 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
c906108c SS |
2010 | { |
2011 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2012 | if (offset < 0) /* negative stack adjustment? */ |
2013 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2014 | else |
2015 | /* Exit loop if a positive stack adjustment is found, which | |
2016 | usually means that the stack cleanup code in the function | |
2017 | epilogue is reached. */ | |
2018 | break; | |
2019 | } | |
2020 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2021 | { | |
2022 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2023 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2024 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2025 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2026 | } |
2027 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2028 | { | |
2029 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2030 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2031 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2032 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2033 | } |
2034 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2035 | { | |
2036 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2037 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2038 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2039 | } |
2040 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2041 | { | |
2042 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2043 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2044 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2045 | } |
c5aa993b | 2046 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2047 | { |
2048 | frame_addr = sp; | |
2049 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2050 | } | |
2051 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2052 | { | |
2053 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2054 | frame_addr = sp + offset; | |
2055 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2056 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2057 | } | |
2058 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2059 | { | |
2060 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2061 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2062 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2063 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2064 | } |
2065 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2066 | { | |
2067 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2068 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2069 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2070 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2071 | } |
c5aa993b JM |
2072 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2073 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2074 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2075 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2076 | } |
2077 | ||
c5aa993b JM |
2078 | /* The entry instruction is typically the first instruction in a function, |
2079 | and it stores registers at offsets relative to the value of the old SP | |
2080 | (before the prologue). But the value of the sp parameter to this | |
2081 | function is the new SP (after the prologue has been executed). So we | |
2082 | can't calculate those offsets until we've seen the entire prologue, | |
2083 | and can calculate what the old SP must have been. */ | |
2084 | if (entry_inst != 0) | |
2085 | { | |
2086 | int areg_count = (entry_inst >> 8) & 7; | |
2087 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2088 | |
c5aa993b JM |
2089 | /* The entry instruction always subtracts 32 from the SP. */ |
2090 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2091 | |
c5aa993b JM |
2092 | /* Now we can calculate what the SP must have been at the |
2093 | start of the function prologue. */ | |
2094 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2095 | |
c5aa993b JM |
2096 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2097 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2098 | { | |
2099 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2100 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
480d3dd2 | 2101 | offset += mips_saved_regsize (tdep); |
c5aa993b | 2102 | } |
c906108c | 2103 | |
c5aa993b JM |
2104 | /* Check if the ra register was pushed on the stack. */ |
2105 | offset = -4; | |
2106 | if (entry_inst & 0x20) | |
2107 | { | |
2108 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2109 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
480d3dd2 | 2110 | offset -= mips_saved_regsize (tdep); |
c5aa993b | 2111 | } |
c906108c | 2112 | |
c5aa993b JM |
2113 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2114 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2115 | { | |
2116 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2117 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
480d3dd2 | 2118 | offset -= mips_saved_regsize (tdep); |
c5aa993b JM |
2119 | } |
2120 | } | |
c906108c SS |
2121 | } |
2122 | ||
2123 | static void | |
fba45db2 KB |
2124 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2125 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2126 | { |
2127 | CORE_ADDR cur_pc; | |
c5aa993b | 2128 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2129 | restart: |
fe29b929 | 2130 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2131 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2132 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2133 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2134 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2135 | { | |
2136 | unsigned long inst, high_word, low_word; | |
2137 | int reg; | |
2138 | ||
2139 | /* Fetch the instruction. */ | |
2140 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2141 | ||
2142 | /* Save some code by pre-extracting some useful fields. */ | |
2143 | high_word = (inst >> 16) & 0xffff; | |
2144 | low_word = inst & 0xffff; | |
2145 | reg = high_word & 0x1f; | |
2146 | ||
c5aa993b | 2147 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2148 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2149 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2150 | { | |
2151 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2152 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2153 | else |
2154 | /* Exit loop if a positive stack adjustment is found, which | |
2155 | usually means that the stack cleanup code in the function | |
2156 | epilogue is reached. */ | |
2157 | break; | |
2158 | } | |
2159 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2160 | { | |
c5aa993b | 2161 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2162 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2163 | } |
2164 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2165 | { | |
2166 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2167 | but the register size used is only 32 bits. Make the address | |
2168 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2169 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
6d82d43b AC |
2170 | set_reg_offset (temp_saved_regs, reg, |
2171 | sp + low_word + 8 - mips_regsize (current_gdbarch)); | |
c906108c | 2172 | } |
c5aa993b | 2173 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2174 | { |
2175 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2176 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2177 | frame_addr = sp + low_word; | |
c906108c SS |
2178 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2179 | { | |
2180 | unsigned alloca_adjust; | |
2181 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2182 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2183 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2184 | if (alloca_adjust > 0) |
2185 | { | |
2186 | /* FP > SP + frame_size. This may be because | |
2187 | * of an alloca or somethings similar. | |
2188 | * Fix sp to "pre-alloca" value, and try again. | |
2189 | */ | |
2190 | sp += alloca_adjust; | |
2191 | goto restart; | |
2192 | } | |
2193 | } | |
2194 | } | |
c5aa993b JM |
2195 | /* move $30,$sp. With different versions of gas this will be either |
2196 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2197 | Accept any one of these. */ | |
c906108c SS |
2198 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2199 | { | |
2200 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2201 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2202 | { | |
2203 | unsigned alloca_adjust; | |
2204 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2205 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2206 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2207 | if (alloca_adjust > 0) |
2208 | { | |
2209 | /* FP > SP + frame_size. This may be because | |
2210 | * of an alloca or somethings similar. | |
2211 | * Fix sp to "pre-alloca" value, and try again. | |
2212 | */ | |
2213 | sp += alloca_adjust; | |
2214 | goto restart; | |
2215 | } | |
2216 | } | |
2217 | } | |
c5aa993b | 2218 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2219 | { |
c5aa993b | 2220 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2221 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2222 | } |
2223 | } | |
2224 | } | |
2225 | ||
2226 | static mips_extra_func_info_t | |
acdb74a0 | 2227 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2228 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2229 | { |
479412cd DJ |
2230 | CORE_ADDR sp; |
2231 | ||
2232 | if (cur_frame) | |
a4b8ebc8 | 2233 | sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); |
479412cd DJ |
2234 | else |
2235 | sp = 0; | |
c906108c | 2236 | |
c5aa993b JM |
2237 | if (start_pc == 0) |
2238 | return NULL; | |
2239 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2240 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2241 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2242 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2243 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2244 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2245 | ||
2246 | if (start_pc + 200 < limit_pc) | |
2247 | limit_pc = start_pc + 200; | |
2248 | if (pc_is_mips16 (start_pc)) | |
2249 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2250 | else | |
2251 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2252 | return &temp_proc_desc; | |
2253 | } | |
2254 | ||
6c0d6680 DJ |
2255 | struct mips_objfile_private |
2256 | { | |
2257 | bfd_size_type size; | |
2258 | char *contents; | |
2259 | }; | |
2260 | ||
2261 | /* Global used to communicate between non_heuristic_proc_desc and | |
2262 | compare_pdr_entries within qsort (). */ | |
2263 | static bfd *the_bfd; | |
2264 | ||
2265 | static int | |
2266 | compare_pdr_entries (const void *a, const void *b) | |
2267 | { | |
2268 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2269 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2270 | ||
2271 | if (lhs < rhs) | |
2272 | return -1; | |
2273 | else if (lhs == rhs) | |
2274 | return 0; | |
2275 | else | |
2276 | return 1; | |
2277 | } | |
2278 | ||
c906108c | 2279 | static mips_extra_func_info_t |
acdb74a0 | 2280 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2281 | { |
2282 | CORE_ADDR startaddr; | |
2283 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2284 | struct block *b = block_for_pc (pc); |
c906108c | 2285 | struct symbol *sym; |
6c0d6680 DJ |
2286 | struct obj_section *sec; |
2287 | struct mips_objfile_private *priv; | |
2288 | ||
ae45cd16 | 2289 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2290 | return NULL; |
c906108c SS |
2291 | |
2292 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2293 | if (addrptr) | |
2294 | *addrptr = startaddr; | |
6c0d6680 DJ |
2295 | |
2296 | priv = NULL; | |
2297 | ||
2298 | sec = find_pc_section (pc); | |
2299 | if (sec != NULL) | |
c906108c | 2300 | { |
6c0d6680 DJ |
2301 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2302 | ||
2303 | /* Search the ".pdr" section generated by GAS. This includes most of | |
6d82d43b | 2304 | the information normally found in ECOFF PDRs. */ |
6c0d6680 DJ |
2305 | |
2306 | the_bfd = sec->objfile->obfd; | |
2307 | if (priv == NULL | |
2308 | && (the_bfd->format == bfd_object | |
2309 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2310 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2311 | { | |
2312 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2313 | This means that we should not bother with this method on 64-bit | |
2314 | targets (until that is fixed). */ | |
2315 | ||
8b92e4d5 | 2316 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2317 | sizeof (struct mips_objfile_private)); |
2318 | priv->size = 0; | |
2319 | sec->objfile->obj_private = priv; | |
2320 | } | |
2321 | else if (priv == NULL) | |
2322 | { | |
2323 | asection *bfdsec; | |
2324 | ||
8b92e4d5 | 2325 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2326 | sizeof (struct mips_objfile_private)); |
2327 | ||
2328 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2329 | if (bfdsec != NULL) | |
2330 | { | |
2331 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
8b92e4d5 | 2332 | priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2333 | priv->size); |
2334 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2335 | priv->contents, 0, priv->size); | |
2336 | ||
2337 | /* In general, the .pdr section is sorted. However, in the | |
6d82d43b AC |
2338 | presence of multiple code sections (and other corner cases) |
2339 | it can become unsorted. Sort it so that we can use a faster | |
2340 | binary search. */ | |
2341 | qsort (priv->contents, priv->size / 32, 32, | |
2342 | compare_pdr_entries); | |
6c0d6680 DJ |
2343 | } |
2344 | else | |
2345 | priv->size = 0; | |
2346 | ||
2347 | sec->objfile->obj_private = priv; | |
2348 | } | |
2349 | the_bfd = NULL; | |
2350 | ||
2351 | if (priv->size != 0) | |
2352 | { | |
2353 | int low, mid, high; | |
2354 | char *ptr; | |
2355 | ||
2356 | low = 0; | |
2357 | high = priv->size / 32; | |
2358 | ||
2359 | do | |
2360 | { | |
2361 | CORE_ADDR pdr_pc; | |
2362 | ||
2363 | mid = (low + high) / 2; | |
2364 | ||
2365 | ptr = priv->contents + mid * 32; | |
2366 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2367 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2368 | SECT_OFF_TEXT (sec->objfile)); | |
2369 | if (pdr_pc == startaddr) | |
2370 | break; | |
2371 | if (pdr_pc > startaddr) | |
2372 | high = mid; | |
2373 | else | |
2374 | low = mid + 1; | |
2375 | } | |
2376 | while (low != high); | |
2377 | ||
2378 | if (low != high) | |
2379 | { | |
2380 | struct symbol *sym = find_pc_function (pc); | |
2381 | ||
2382 | /* Fill in what we need of the proc_desc. */ | |
2383 | proc_desc = (mips_extra_func_info_t) | |
8b92e4d5 | 2384 | obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2385 | sizeof (struct mips_extra_func_info)); |
2386 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2387 | ||
2388 | /* Only used for dummy frames. */ | |
2389 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2390 | ||
2391 | PROC_FRAME_OFFSET (proc_desc) | |
2392 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2393 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2394 | ptr + 24); | |
2395 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2396 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2397 | ptr + 4); | |
2398 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2399 | ptr + 12); | |
2400 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2401 | ptr + 8); | |
2402 | PROC_FREG_OFFSET (proc_desc) | |
2403 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2404 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2405 | ptr + 28); | |
2406 | proc_desc->pdr.isym = (long) sym; | |
2407 | ||
2408 | return proc_desc; | |
2409 | } | |
2410 | } | |
c906108c SS |
2411 | } |
2412 | ||
6c0d6680 DJ |
2413 | if (b == NULL) |
2414 | return NULL; | |
2415 | ||
2416 | if (startaddr > BLOCK_START (b)) | |
2417 | { | |
2418 | /* This is the "pathological" case referred to in a comment in | |
6d82d43b AC |
2419 | print_frame_info. It might be better to move this check into |
2420 | symbol reading. */ | |
6c0d6680 DJ |
2421 | return NULL; |
2422 | } | |
2423 | ||
176620f1 | 2424 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2425 | |
c906108c SS |
2426 | /* If we never found a PDR for this function in symbol reading, then |
2427 | examine prologues to find the information. */ | |
2428 | if (sym) | |
2429 | { | |
2430 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2431 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2432 | return NULL; | |
2433 | else | |
2434 | return proc_desc; | |
2435 | } | |
2436 | else | |
2437 | return NULL; | |
2438 | } | |
2439 | ||
2440 | ||
2441 | static mips_extra_func_info_t | |
479412cd | 2442 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2443 | { |
2444 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2445 | CORE_ADDR startaddr = 0; |
c906108c SS |
2446 | |
2447 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2448 | ||
2449 | if (proc_desc) | |
2450 | { | |
2451 | /* IF this is the topmost frame AND | |
2452 | * (this proc does not have debugging information OR | |
2453 | * the PC is in the procedure prologue) | |
2454 | * THEN create a "heuristic" proc_desc (by analyzing | |
2455 | * the actual code) to replace the "official" proc_desc. | |
2456 | */ | |
2457 | if (next_frame == NULL) | |
2458 | { | |
2459 | struct symtab_and_line val; | |
2460 | struct symbol *proc_symbol = | |
c86b5b38 | 2461 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2462 | |
2463 | if (proc_symbol) | |
2464 | { | |
2465 | val = find_pc_line (BLOCK_START | |
6d82d43b | 2466 | (SYMBOL_BLOCK_VALUE (proc_symbol)), 0); |
c906108c SS |
2467 | val.pc = val.end ? val.end : pc; |
2468 | } | |
2469 | if (!proc_symbol || pc < val.pc) | |
2470 | { | |
2471 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2472 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2473 | pc, next_frame, cur_frame); | |
c906108c SS |
2474 | if (found_heuristic) |
2475 | proc_desc = found_heuristic; | |
2476 | } | |
2477 | } | |
2478 | } | |
2479 | else | |
2480 | { | |
2481 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2482 | by procedure call dummys. However, the procedures being called ought |
2483 | to have their own proc_descs, and even if they don't, | |
2484 | heuristic_proc_desc knows how to create them! */ | |
c906108c | 2485 | |
aa1ee363 | 2486 | struct linked_proc_info *link; |
c906108c SS |
2487 | |
2488 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2489 | if (PROC_LOW_ADDR (&link->info) <= pc |
2490 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2491 | return &link->info; |
2492 | ||
2493 | if (startaddr == 0) | |
2494 | startaddr = heuristic_proc_start (pc); | |
2495 | ||
6d82d43b | 2496 | proc_desc = heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2497 | } |
2498 | return proc_desc; | |
2499 | } | |
2500 | ||
c906108c SS |
2501 | /* MIPS stack frames are almost impenetrable. When execution stops, |
2502 | we basically have to look at symbol information for the function | |
2503 | that we stopped in, which tells us *which* register (if any) is | |
2504 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2505 | the frame itself is at. |
c906108c SS |
2506 | |
2507 | This presents a problem when trying to examine a stack in memory | |
2508 | (that isn't executing at the moment), using the "frame" command. We | |
2509 | don't have a PC, nor do we have any registers except SP. | |
2510 | ||
2511 | This routine takes two arguments, SP and PC, and tries to make the | |
2512 | cached frames look as if these two arguments defined a frame on the | |
2513 | cache. This allows the rest of info frame to extract the important | |
2514 | arguments without difficulty. */ | |
2515 | ||
2516 | struct frame_info * | |
acdb74a0 | 2517 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2518 | { |
2519 | if (argc != 2) | |
2520 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2521 | ||
2522 | return create_new_frame (argv[0], argv[1]); | |
2523 | } | |
2524 | ||
f09ded24 AC |
2525 | /* According to the current ABI, should the type be passed in a |
2526 | floating-point register (assuming that there is space)? When there | |
2527 | is no FPU, FP are not even considered as possibile candidates for | |
2528 | FP registers and, consequently this returns false - forces FP | |
2529 | arguments into integer registers. */ | |
2530 | ||
2531 | static int | |
2532 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2533 | { | |
2534 | return ((typecode == TYPE_CODE_FLT | |
2535 | || (MIPS_EABI | |
6d82d43b AC |
2536 | && (typecode == TYPE_CODE_STRUCT |
2537 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
2538 | && TYPE_NFIELDS (arg_type) == 1 |
2539 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2540 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2541 | } |
2542 | ||
49e790b0 DJ |
2543 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2544 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2545 | ||
2546 | static int | |
2547 | mips_type_needs_double_align (struct type *type) | |
2548 | { | |
2549 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2550 | |
49e790b0 DJ |
2551 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2552 | return 1; | |
2553 | else if (typecode == TYPE_CODE_STRUCT) | |
2554 | { | |
2555 | if (TYPE_NFIELDS (type) < 1) | |
2556 | return 0; | |
2557 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2558 | } | |
2559 | else if (typecode == TYPE_CODE_UNION) | |
2560 | { | |
361d1df0 | 2561 | int i, n; |
49e790b0 DJ |
2562 | |
2563 | n = TYPE_NFIELDS (type); | |
2564 | for (i = 0; i < n; i++) | |
2565 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2566 | return 1; | |
2567 | return 0; | |
2568 | } | |
2569 | return 0; | |
2570 | } | |
2571 | ||
dc604539 AC |
2572 | /* Adjust the address downward (direction of stack growth) so that it |
2573 | is correctly aligned for a new stack frame. */ | |
2574 | static CORE_ADDR | |
2575 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2576 | { | |
5b03f266 | 2577 | return align_down (addr, 16); |
dc604539 AC |
2578 | } |
2579 | ||
6d82d43b AC |
2580 | /* Determine how a return value is stored within the MIPS register |
2581 | file, given the return type `valtype'. */ | |
2582 | ||
2583 | struct return_value_word | |
2584 | { | |
2585 | int len; | |
2586 | int reg; | |
2587 | int reg_offset; | |
2588 | int buf_offset; | |
2589 | }; | |
2590 | ||
2591 | static void | |
2592 | return_value_location (struct type *valtype, | |
2593 | struct return_value_word *hi, | |
2594 | struct return_value_word *lo) | |
2595 | { | |
2596 | int len = TYPE_LENGTH (valtype); | |
2597 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2598 | ||
2599 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
2600 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
2601 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
2602 | { | |
2603 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2604 | { | |
2605 | /* We need to break a 64bit float in two 32 bit halves and | |
2606 | spread them across a floating-point register pair. */ | |
2607 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
2608 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
2609 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2610 | && register_size (current_gdbarch, | |
2611 | mips_regnum (current_gdbarch)-> | |
2612 | fp0) == 8) ? 4 : 0); | |
2613 | hi->reg_offset = lo->reg_offset; | |
2614 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; | |
2615 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
2616 | lo->len = 4; | |
2617 | hi->len = 4; | |
2618 | } | |
2619 | else | |
2620 | { | |
2621 | /* The floating point value fits in a single floating-point | |
2622 | register. */ | |
2623 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2624 | && register_size (current_gdbarch, | |
2625 | mips_regnum (current_gdbarch)-> | |
2626 | fp0) == 8 | |
2627 | && len == 4) ? 4 : 0); | |
2628 | lo->reg = mips_regnum (current_gdbarch)->fp0; | |
2629 | lo->len = len; | |
2630 | lo->buf_offset = 0; | |
2631 | hi->len = 0; | |
2632 | hi->reg_offset = 0; | |
2633 | hi->buf_offset = 0; | |
2634 | hi->reg = 0; | |
2635 | } | |
2636 | } | |
2637 | else | |
2638 | { | |
2639 | /* Locate a result possibly spread across two registers. */ | |
2640 | int regnum = 2; | |
2641 | lo->reg = regnum + 0; | |
2642 | hi->reg = regnum + 1; | |
2643 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2644 | && len < mips_saved_regsize (tdep)) | |
2645 | { | |
2646 | /* "un-left-justify" the value in the low register */ | |
2647 | lo->reg_offset = mips_saved_regsize (tdep) - len; | |
2648 | lo->len = len; | |
2649 | hi->reg_offset = 0; | |
2650 | hi->len = 0; | |
2651 | } | |
2652 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_saved_regsize (tdep) /* odd-size structs */ | |
2653 | && len < mips_saved_regsize (tdep) * 2 | |
2654 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
2655 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
2656 | { | |
2657 | /* "un-left-justify" the value spread across two registers. */ | |
2658 | lo->reg_offset = 2 * mips_saved_regsize (tdep) - len; | |
2659 | lo->len = mips_saved_regsize (tdep) - lo->reg_offset; | |
2660 | hi->reg_offset = 0; | |
2661 | hi->len = len - lo->len; | |
2662 | } | |
2663 | else | |
2664 | { | |
2665 | /* Only perform a partial copy of the second register. */ | |
2666 | lo->reg_offset = 0; | |
2667 | hi->reg_offset = 0; | |
2668 | if (len > mips_saved_regsize (tdep)) | |
2669 | { | |
2670 | lo->len = mips_saved_regsize (tdep); | |
2671 | hi->len = len - mips_saved_regsize (tdep); | |
2672 | } | |
2673 | else | |
2674 | { | |
2675 | lo->len = len; | |
2676 | hi->len = 0; | |
2677 | } | |
2678 | } | |
2679 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2680 | && register_size (current_gdbarch, regnum) == 8 | |
2681 | && mips_saved_regsize (tdep) == 4) | |
2682 | { | |
2683 | /* Account for the fact that only the least-signficant part | |
2684 | of the register is being used */ | |
2685 | lo->reg_offset += 4; | |
2686 | hi->reg_offset += 4; | |
2687 | } | |
2688 | lo->buf_offset = 0; | |
2689 | hi->buf_offset = lo->len; | |
2690 | } | |
2691 | } | |
2692 | ||
2693 | /* Should call_function allocate stack space for a struct return? */ | |
2694 | ||
2695 | static int | |
2696 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) | |
2697 | { | |
2698 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2699 | return (TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep)); | |
2700 | } | |
2701 | ||
2702 | /* Should call_function pass struct by reference? | |
2703 | For each architecture, structs are passed either by | |
2704 | value or by reference, depending on their size. */ | |
2705 | ||
2706 | static int | |
2707 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
2708 | { | |
2709 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
2710 | int len = TYPE_LENGTH (check_typedef (type)); | |
2711 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2712 | ||
2713 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2714 | return (len > mips_saved_regsize (tdep)); | |
2715 | ||
2716 | return 0; | |
2717 | } | |
2718 | ||
f7ab6ec6 | 2719 | static CORE_ADDR |
25ab4790 | 2720 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
6d82d43b AC |
2721 | struct regcache *regcache, CORE_ADDR bp_addr, |
2722 | int nargs, struct value **args, CORE_ADDR sp, | |
2723 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2724 | { |
2725 | int argreg; | |
2726 | int float_argreg; | |
2727 | int argnum; | |
2728 | int len = 0; | |
2729 | int stack_offset = 0; | |
480d3dd2 | 2730 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c906108c | 2731 | |
25ab4790 AC |
2732 | /* For shared libraries, "t9" needs to point at the function |
2733 | address. */ | |
2734 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2735 | ||
2736 | /* Set the return address register to point to the entry point of | |
2737 | the program, where a breakpoint lies in wait. */ | |
2738 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2739 | ||
c906108c | 2740 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2741 | are properly aligned. The stack has to be at least 64-bit |
2742 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2743 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2744 | aligned, so we round to this widest known alignment. */ | |
2745 | ||
5b03f266 AC |
2746 | sp = align_down (sp, 16); |
2747 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2748 | |
46e0f506 | 2749 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2750 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2751 | passed in registers, but that's OK. */ |
c906108c | 2752 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 2753 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 2754 | mips_stack_argsize (tdep)); |
5b03f266 | 2755 | sp -= align_up (len, 16); |
c906108c | 2756 | |
9ace0497 | 2757 | if (mips_debug) |
6d82d43b | 2758 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2759 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2760 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2761 | |
c906108c SS |
2762 | /* Initialize the integer and float register pointers. */ |
2763 | argreg = A0_REGNUM; | |
56cea623 | 2764 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2765 | |
46e0f506 | 2766 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2767 | if (struct_return) |
9ace0497 AC |
2768 | { |
2769 | if (mips_debug) | |
2770 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2771 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2772 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2773 | write_register (argreg++, struct_addr); |
2774 | } | |
c906108c SS |
2775 | |
2776 | /* Now load as many as possible of the first arguments into | |
2777 | registers, and push the rest onto the stack. Loop thru args | |
2778 | from first to last. */ | |
2779 | for (argnum = 0; argnum < nargs; argnum++) | |
2780 | { | |
2781 | char *val; | |
d9d9c31f | 2782 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2783 | struct value *arg = args[argnum]; |
c906108c SS |
2784 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2785 | int len = TYPE_LENGTH (arg_type); | |
2786 | enum type_code typecode = TYPE_CODE (arg_type); | |
2787 | ||
9ace0497 AC |
2788 | if (mips_debug) |
2789 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2790 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2791 | argnum + 1, len, (int) typecode); |
9ace0497 | 2792 | |
c906108c | 2793 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2794 | reference. */ |
480d3dd2 | 2795 | if (len > mips_saved_regsize (tdep) |
9ace0497 | 2796 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2797 | { |
480d3dd2 AC |
2798 | store_unsigned_integer (valbuf, mips_saved_regsize (tdep), |
2799 | VALUE_ADDRESS (arg)); | |
c906108c | 2800 | typecode = TYPE_CODE_PTR; |
480d3dd2 | 2801 | len = mips_saved_regsize (tdep); |
c906108c | 2802 | val = valbuf; |
9ace0497 AC |
2803 | if (mips_debug) |
2804 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2805 | } |
2806 | else | |
c5aa993b | 2807 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2808 | |
2809 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2810 | even-numbered floating point register. Round the FP register |
2811 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2812 | left. Non MIPS_EABI targets also pass the FP in the integer |
2813 | registers so also round up normal registers. */ | |
6d82d43b | 2814 | if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2815 | { |
2816 | if ((float_argreg & 1)) | |
2817 | float_argreg++; | |
2818 | } | |
c906108c SS |
2819 | |
2820 | /* Floating point arguments passed in registers have to be | |
2821 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2822 | are passed in register pairs; the even register gets |
2823 | the low word, and the odd register gets the high word. | |
2824 | On non-EABI processors, the first two floating point arguments are | |
2825 | also copied to general registers, because MIPS16 functions | |
2826 | don't use float registers for arguments. This duplication of | |
2827 | arguments in general registers can't hurt non-MIPS16 functions | |
2828 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2829 | /* MIPS_EABI squeezes a struct that contains a single floating |
2830 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2831 | stack. */ |
f09ded24 AC |
2832 | if (fp_register_arg_p (typecode, arg_type) |
2833 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2834 | { |
2835 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2836 | { | |
d7449b42 | 2837 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2838 | unsigned long regval; |
2839 | ||
2840 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2841 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2842 | if (mips_debug) |
acdb74a0 | 2843 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2844 | float_argreg, phex (regval, 4)); |
c906108c | 2845 | write_register (float_argreg++, regval); |
c906108c SS |
2846 | |
2847 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2848 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2849 | if (mips_debug) |
acdb74a0 | 2850 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2851 | float_argreg, phex (regval, 4)); |
c906108c | 2852 | write_register (float_argreg++, regval); |
c906108c SS |
2853 | } |
2854 | else | |
2855 | { | |
2856 | /* This is a floating point value that fits entirely | |
2857 | in a single register. */ | |
53a5351d | 2858 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2859 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2860 | LONGEST regval = extract_unsigned_integer (val, len); |
2861 | if (mips_debug) | |
acdb74a0 | 2862 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2863 | float_argreg, phex (regval, len)); |
c906108c | 2864 | write_register (float_argreg++, regval); |
c906108c SS |
2865 | } |
2866 | } | |
2867 | else | |
2868 | { | |
2869 | /* Copy the argument to general registers or the stack in | |
2870 | register-sized pieces. Large arguments are split between | |
2871 | registers and stack. */ | |
4246e332 AC |
2872 | /* Note: structs whose size is not a multiple of |
2873 | mips_regsize() are treated specially: Irix cc passes them | |
2874 | in registers where gcc sometimes puts them on the stack. | |
2875 | For maximum compatibility, we will put them in both | |
2876 | places. */ | |
480d3dd2 AC |
2877 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
2878 | && (len % mips_saved_regsize (tdep) != 0)); | |
46e0f506 | 2879 | |
f09ded24 | 2880 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2881 | register are only written to memory. */ |
c906108c SS |
2882 | while (len > 0) |
2883 | { | |
ebafbe83 | 2884 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2885 | int stack_used_p = 0; |
480d3dd2 AC |
2886 | int partial_len = (len < mips_saved_regsize (tdep) |
2887 | ? len : mips_saved_regsize (tdep)); | |
c906108c | 2888 | |
acdb74a0 AC |
2889 | if (mips_debug) |
2890 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2891 | partial_len); | |
2892 | ||
566f0f7a | 2893 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2894 | if (argreg > MIPS_LAST_ARG_REGNUM |
2895 | || odd_sized_struct | |
2896 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2897 | { |
c906108c SS |
2898 | /* Should shorter than int integer values be |
2899 | promoted to int before being stored? */ | |
c906108c | 2900 | int longword_offset = 0; |
9ace0497 | 2901 | CORE_ADDR addr; |
566f0f7a | 2902 | stack_used_p = 1; |
d7449b42 | 2903 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2904 | { |
480d3dd2 AC |
2905 | if (mips_stack_argsize (tdep) == 8 |
2906 | && (typecode == TYPE_CODE_INT | |
2907 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2908 | || typecode == TYPE_CODE_FLT) && len <= 4) |
480d3dd2 AC |
2909 | longword_offset = mips_stack_argsize (tdep) - len; |
2910 | else if ((typecode == TYPE_CODE_STRUCT | |
2911 | || typecode == TYPE_CODE_UNION) | |
2912 | && (TYPE_LENGTH (arg_type) | |
2913 | < mips_stack_argsize (tdep))) | |
2914 | longword_offset = mips_stack_argsize (tdep) - len; | |
7a292a7a | 2915 | } |
c5aa993b | 2916 | |
9ace0497 AC |
2917 | if (mips_debug) |
2918 | { | |
cb3d25d1 MS |
2919 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2920 | paddr_nz (stack_offset)); | |
2921 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2922 | paddr_nz (longword_offset)); | |
9ace0497 | 2923 | } |
361d1df0 | 2924 | |
9ace0497 AC |
2925 | addr = sp + stack_offset + longword_offset; |
2926 | ||
2927 | if (mips_debug) | |
2928 | { | |
2929 | int i; | |
6d82d43b | 2930 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2931 | paddr_nz (addr)); |
9ace0497 AC |
2932 | for (i = 0; i < partial_len; i++) |
2933 | { | |
6d82d43b | 2934 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2935 | val[i] & 0xff); |
9ace0497 AC |
2936 | } |
2937 | } | |
2938 | write_memory (addr, val, partial_len); | |
c906108c SS |
2939 | } |
2940 | ||
f09ded24 AC |
2941 | /* Note!!! This is NOT an else clause. Odd sized |
2942 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2943 | arguments will not. */ |
566f0f7a | 2944 | /* Write this portion of the argument to a general |
6d82d43b | 2945 | purpose register. */ |
f09ded24 AC |
2946 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2947 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2948 | { |
6d82d43b AC |
2949 | LONGEST regval = |
2950 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2951 | |
9ace0497 | 2952 | if (mips_debug) |
acdb74a0 | 2953 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2954 | argreg, |
6d82d43b AC |
2955 | phex (regval, |
2956 | mips_saved_regsize (tdep))); | |
c906108c SS |
2957 | write_register (argreg, regval); |
2958 | argreg++; | |
c906108c | 2959 | } |
c5aa993b | 2960 | |
c906108c SS |
2961 | len -= partial_len; |
2962 | val += partial_len; | |
2963 | ||
566f0f7a | 2964 | /* Compute the the offset into the stack at which we |
6d82d43b | 2965 | will copy the next parameter. |
566f0f7a | 2966 | |
566f0f7a | 2967 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2968 | only needs to be adjusted when it has been used. */ |
c906108c | 2969 | |
46e0f506 | 2970 | if (stack_used_p) |
480d3dd2 AC |
2971 | stack_offset += align_up (partial_len, |
2972 | mips_stack_argsize (tdep)); | |
c906108c SS |
2973 | } |
2974 | } | |
9ace0497 AC |
2975 | if (mips_debug) |
2976 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2977 | } |
2978 | ||
310e9b6a AC |
2979 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
2980 | ||
0f71a2f6 JM |
2981 | /* Return adjusted stack pointer. */ |
2982 | return sp; | |
2983 | } | |
2984 | ||
6d82d43b AC |
2985 | /* Given a return value in `regbuf' with a type `valtype', extract and |
2986 | copy its value into `valbuf'. */ | |
2987 | ||
2988 | static void | |
2989 | mips_eabi_extract_return_value (struct type *valtype, | |
2990 | char regbuf[], char *valbuf) | |
2991 | { | |
2992 | struct return_value_word lo; | |
2993 | struct return_value_word hi; | |
2994 | return_value_location (valtype, &hi, &lo); | |
2995 | ||
2996 | memcpy (valbuf + lo.buf_offset, | |
2997 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
2998 | lo.reg_offset, lo.len); | |
2999 | ||
3000 | if (hi.len > 0) | |
3001 | memcpy (valbuf + hi.buf_offset, | |
3002 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
3003 | hi.reg_offset, hi.len); | |
3004 | } | |
3005 | ||
3006 | /* Given a return value in `valbuf' with a type `valtype', write it's | |
3007 | value into the appropriate register. */ | |
3008 | ||
3009 | static void | |
3010 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
3011 | { | |
3012 | char raw_buffer[MAX_REGISTER_SIZE]; | |
3013 | struct return_value_word lo; | |
3014 | struct return_value_word hi; | |
3015 | return_value_location (valtype, &hi, &lo); | |
3016 | ||
3017 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3018 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3019 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
3020 | raw_buffer, register_size (current_gdbarch, | |
3021 | lo.reg)); | |
3022 | ||
3023 | if (hi.len > 0) | |
3024 | { | |
3025 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3026 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3027 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
3028 | raw_buffer, | |
3029 | register_size (current_gdbarch, | |
3030 | hi.reg)); | |
3031 | } | |
3032 | } | |
3033 | ||
3034 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3035 | |
f7ab6ec6 | 3036 | static CORE_ADDR |
25ab4790 | 3037 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
6d82d43b AC |
3038 | struct regcache *regcache, CORE_ADDR bp_addr, |
3039 | int nargs, struct value **args, CORE_ADDR sp, | |
3040 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3041 | { |
3042 | int argreg; | |
3043 | int float_argreg; | |
3044 | int argnum; | |
3045 | int len = 0; | |
3046 | int stack_offset = 0; | |
480d3dd2 | 3047 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cb3d25d1 | 3048 | |
25ab4790 AC |
3049 | /* For shared libraries, "t9" needs to point at the function |
3050 | address. */ | |
3051 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3052 | ||
3053 | /* Set the return address register to point to the entry point of | |
3054 | the program, where a breakpoint lies in wait. */ | |
3055 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3056 | ||
cb3d25d1 MS |
3057 | /* First ensure that the stack and structure return address (if any) |
3058 | are properly aligned. The stack has to be at least 64-bit | |
3059 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3060 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3061 | aligned, so we round to this widest known alignment. */ | |
3062 | ||
5b03f266 AC |
3063 | sp = align_down (sp, 16); |
3064 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3065 | |
3066 | /* Now make space on the stack for the args. */ | |
3067 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3068 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 3069 | mips_stack_argsize (tdep)); |
5b03f266 | 3070 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3071 | |
3072 | if (mips_debug) | |
6d82d43b | 3073 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3074 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3075 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3076 | |
3077 | /* Initialize the integer and float register pointers. */ | |
3078 | argreg = A0_REGNUM; | |
56cea623 | 3079 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3080 | |
46e0f506 | 3081 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3082 | if (struct_return) |
3083 | { | |
3084 | if (mips_debug) | |
3085 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3086 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3087 | argreg, paddr_nz (struct_addr)); |
3088 | write_register (argreg++, struct_addr); | |
3089 | } | |
3090 | ||
3091 | /* Now load as many as possible of the first arguments into | |
3092 | registers, and push the rest onto the stack. Loop thru args | |
3093 | from first to last. */ | |
3094 | for (argnum = 0; argnum < nargs; argnum++) | |
3095 | { | |
3096 | char *val; | |
cb3d25d1 MS |
3097 | struct value *arg = args[argnum]; |
3098 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3099 | int len = TYPE_LENGTH (arg_type); | |
3100 | enum type_code typecode = TYPE_CODE (arg_type); | |
3101 | ||
3102 | if (mips_debug) | |
3103 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3104 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3105 | argnum + 1, len, (int) typecode); |
3106 | ||
3107 | val = (char *) VALUE_CONTENTS (arg); | |
3108 | ||
3109 | if (fp_register_arg_p (typecode, arg_type) | |
3110 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3111 | { | |
3112 | /* This is a floating point value that fits entirely | |
3113 | in a single register. */ | |
3114 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3115 | above to ensure that it is even register aligned. */ | |
3116 | LONGEST regval = extract_unsigned_integer (val, len); | |
3117 | if (mips_debug) | |
3118 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3119 | float_argreg, phex (regval, len)); | |
3120 | write_register (float_argreg++, regval); | |
3121 | ||
3122 | if (mips_debug) | |
3123 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3124 | argreg, phex (regval, len)); | |
3125 | write_register (argreg, regval); | |
3126 | argreg += 1; | |
3127 | } | |
3128 | else | |
3129 | { | |
3130 | /* Copy the argument to general registers or the stack in | |
3131 | register-sized pieces. Large arguments are split between | |
3132 | registers and stack. */ | |
4246e332 AC |
3133 | /* Note: structs whose size is not a multiple of |
3134 | mips_regsize() are treated specially: Irix cc passes them | |
3135 | in registers where gcc sometimes puts them on the stack. | |
3136 | For maximum compatibility, we will put them in both | |
3137 | places. */ | |
480d3dd2 AC |
3138 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
3139 | && (len % mips_saved_regsize (tdep) != 0)); | |
cb3d25d1 | 3140 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3141 | register are only written to memory. */ |
cb3d25d1 MS |
3142 | while (len > 0) |
3143 | { | |
3144 | /* Rememer if the argument was written to the stack. */ | |
3145 | int stack_used_p = 0; | |
480d3dd2 AC |
3146 | int partial_len = (len < mips_saved_regsize (tdep) |
3147 | ? len : mips_saved_regsize (tdep)); | |
cb3d25d1 MS |
3148 | |
3149 | if (mips_debug) | |
3150 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3151 | partial_len); | |
3152 | ||
3153 | /* Write this portion of the argument to the stack. */ | |
3154 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3155 | || odd_sized_struct | |
3156 | || fp_register_arg_p (typecode, arg_type)) | |
3157 | { | |
3158 | /* Should shorter than int integer values be | |
3159 | promoted to int before being stored? */ | |
3160 | int longword_offset = 0; | |
3161 | CORE_ADDR addr; | |
3162 | stack_used_p = 1; | |
3163 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3164 | { | |
480d3dd2 AC |
3165 | if (mips_stack_argsize (tdep) == 8 |
3166 | && (typecode == TYPE_CODE_INT | |
3167 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3168 | || typecode == TYPE_CODE_FLT) && len <= 4) |
480d3dd2 | 3169 | longword_offset = mips_stack_argsize (tdep) - len; |
cb3d25d1 MS |
3170 | } |
3171 | ||
3172 | if (mips_debug) | |
3173 | { | |
3174 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3175 | paddr_nz (stack_offset)); | |
3176 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3177 | paddr_nz (longword_offset)); | |
3178 | } | |
3179 | ||
3180 | addr = sp + stack_offset + longword_offset; | |
3181 | ||
3182 | if (mips_debug) | |
3183 | { | |
3184 | int i; | |
6d82d43b | 3185 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3186 | paddr_nz (addr)); |
3187 | for (i = 0; i < partial_len; i++) | |
3188 | { | |
6d82d43b | 3189 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3190 | val[i] & 0xff); |
3191 | } | |
3192 | } | |
3193 | write_memory (addr, val, partial_len); | |
3194 | } | |
3195 | ||
3196 | /* Note!!! This is NOT an else clause. Odd sized | |
3197 | structs may go thru BOTH paths. Floating point | |
3198 | arguments will not. */ | |
3199 | /* Write this portion of the argument to a general | |
6d82d43b | 3200 | purpose register. */ |
cb3d25d1 MS |
3201 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3202 | && !fp_register_arg_p (typecode, arg_type)) | |
3203 | { | |
6d82d43b AC |
3204 | LONGEST regval = |
3205 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3206 | |
3207 | /* A non-floating-point argument being passed in a | |
3208 | general register. If a struct or union, and if | |
3209 | the remaining length is smaller than the register | |
3210 | size, we have to adjust the register value on | |
3211 | big endian targets. | |
3212 | ||
3213 | It does not seem to be necessary to do the | |
3214 | same for integral types. | |
3215 | ||
3216 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3217 | outputting LE O32 with sizeof (struct) < | |
480d3dd2 | 3218 | mips_saved_regsize(), generates a left shift as |
cb3d25d1 MS |
3219 | part of storing the argument in a register a |
3220 | register (the left shift isn't generated when | |
480d3dd2 AC |
3221 | sizeof (struct) >= mips_saved_regsize()). Since |
3222 | it is quite possible that this is GCC | |
3223 | contradicting the LE/O32 ABI, GDB has not been | |
3224 | adjusted to accommodate this. Either someone | |
3225 | needs to demonstrate that the LE/O32 ABI | |
3226 | specifies such a left shift OR this new ABI gets | |
3227 | identified as such and GDB gets tweaked | |
3228 | accordingly. */ | |
cb3d25d1 MS |
3229 | |
3230 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
480d3dd2 | 3231 | && partial_len < mips_saved_regsize (tdep) |
cb3d25d1 MS |
3232 | && (typecode == TYPE_CODE_STRUCT || |
3233 | typecode == TYPE_CODE_UNION)) | |
480d3dd2 | 3234 | regval <<= ((mips_saved_regsize (tdep) - partial_len) * |
cb3d25d1 MS |
3235 | TARGET_CHAR_BIT); |
3236 | ||
3237 | if (mips_debug) | |
3238 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3239 | argreg, | |
6d82d43b AC |
3240 | phex (regval, |
3241 | mips_saved_regsize (tdep))); | |
cb3d25d1 MS |
3242 | write_register (argreg, regval); |
3243 | argreg++; | |
3244 | } | |
3245 | ||
3246 | len -= partial_len; | |
3247 | val += partial_len; | |
3248 | ||
3249 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3250 | will copy the next parameter. |
cb3d25d1 MS |
3251 | |
3252 | In N32 (N64?), the stack_offset only needs to be | |
3253 | adjusted when it has been used. */ | |
3254 | ||
3255 | if (stack_used_p) | |
480d3dd2 AC |
3256 | stack_offset += align_up (partial_len, |
3257 | mips_stack_argsize (tdep)); | |
cb3d25d1 MS |
3258 | } |
3259 | } | |
3260 | if (mips_debug) | |
3261 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3262 | } | |
3263 | ||
310e9b6a AC |
3264 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3265 | ||
cb3d25d1 MS |
3266 | /* Return adjusted stack pointer. */ |
3267 | return sp; | |
3268 | } | |
3269 | ||
6d82d43b AC |
3270 | static enum return_value_convention |
3271 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3272 | struct type *type, struct regcache *regcache, | |
3273 | void *readbuf, const void *writebuf) | |
ebafbe83 | 3274 | { |
6d82d43b AC |
3275 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3276 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3277 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3278 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
3279 | || TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep)) | |
3280 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3281 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3282 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3283 | { | |
3284 | /* A floating-point value belongs in the least significant part | |
3285 | of FP0. */ | |
3286 | if (mips_debug) | |
3287 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3288 | mips_xfer_register (regcache, | |
3289 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3290 | TYPE_LENGTH (type), | |
3291 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3292 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3293 | } | |
3294 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3295 | && TYPE_NFIELDS (type) <= 2 | |
3296 | && TYPE_NFIELDS (type) >= 1 | |
3297 | && ((TYPE_NFIELDS (type) == 1 | |
3298 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3299 | == TYPE_CODE_FLT)) | |
3300 | || (TYPE_NFIELDS (type) == 2 | |
3301 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3302 | == TYPE_CODE_FLT) | |
3303 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3304 | == TYPE_CODE_FLT))) | |
3305 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3306 | { | |
3307 | /* A struct that contains one or two floats. Each value is part | |
3308 | in the least significant part of their floating point | |
3309 | register.. */ | |
6d82d43b AC |
3310 | int regnum; |
3311 | int field; | |
3312 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3313 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3314 | { | |
3315 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3316 | / TARGET_CHAR_BIT); | |
3317 | if (mips_debug) | |
3318 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3319 | offset); | |
3320 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3321 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3322 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3323 | } | |
3324 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3325 | } | |
3326 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3327 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3328 | { | |
3329 | /* A structure or union. Extract the left justified value, | |
3330 | regardless of the byte order. I.e. DO NOT USE | |
3331 | mips_xfer_lower. */ | |
3332 | int offset; | |
3333 | int regnum; | |
3334 | for (offset = 0, regnum = V0_REGNUM; | |
3335 | offset < TYPE_LENGTH (type); | |
3336 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3337 | { | |
3338 | int xfer = register_size (current_gdbarch, regnum); | |
3339 | if (offset + xfer > TYPE_LENGTH (type)) | |
3340 | xfer = TYPE_LENGTH (type) - offset; | |
3341 | if (mips_debug) | |
3342 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3343 | offset, xfer, regnum); | |
3344 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3345 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3346 | } | |
3347 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3348 | } | |
3349 | else | |
3350 | { | |
3351 | /* A scalar extract each part but least-significant-byte | |
3352 | justified. */ | |
3353 | int offset; | |
3354 | int regnum; | |
3355 | for (offset = 0, regnum = V0_REGNUM; | |
3356 | offset < TYPE_LENGTH (type); | |
3357 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3358 | { | |
3359 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3360 | if (offset + xfer > TYPE_LENGTH (type)) |
3361 | xfer = TYPE_LENGTH (type) - offset; | |
3362 | if (mips_debug) | |
3363 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3364 | offset, xfer, regnum); | |
3365 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3366 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3367 | } | |
3368 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3369 | } | |
3370 | } | |
3371 | ||
3372 | /* O32 ABI stuff. */ | |
3373 | ||
3374 | static CORE_ADDR | |
3375 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, | |
3376 | struct regcache *regcache, CORE_ADDR bp_addr, | |
3377 | int nargs, struct value **args, CORE_ADDR sp, | |
3378 | int struct_return, CORE_ADDR struct_addr) | |
3379 | { | |
3380 | int argreg; | |
3381 | int float_argreg; | |
3382 | int argnum; | |
3383 | int len = 0; | |
3384 | int stack_offset = 0; | |
3385 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3386 | ||
3387 | /* For shared libraries, "t9" needs to point at the function | |
3388 | address. */ | |
3389 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3390 | ||
3391 | /* Set the return address register to point to the entry point of | |
3392 | the program, where a breakpoint lies in wait. */ | |
3393 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3394 | ||
3395 | /* First ensure that the stack and structure return address (if any) | |
3396 | are properly aligned. The stack has to be at least 64-bit | |
3397 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3398 | aligned. For n32 and n64, stack frames need to be 128-bit |
3399 | aligned, so we round to this widest known alignment. */ | |
3400 | ||
5b03f266 AC |
3401 | sp = align_down (sp, 16); |
3402 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3403 | |
3404 | /* Now make space on the stack for the args. */ | |
3405 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3406 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 3407 | mips_stack_argsize (tdep)); |
5b03f266 | 3408 | sp -= align_up (len, 16); |
ebafbe83 MS |
3409 | |
3410 | if (mips_debug) | |
6d82d43b | 3411 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3412 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3413 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3414 | |
3415 | /* Initialize the integer and float register pointers. */ | |
3416 | argreg = A0_REGNUM; | |
56cea623 | 3417 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3418 | |
bcb0cc15 | 3419 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3420 | if (struct_return) |
3421 | { | |
3422 | if (mips_debug) | |
3423 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3424 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3425 | argreg, paddr_nz (struct_addr)); |
3426 | write_register (argreg++, struct_addr); | |
480d3dd2 | 3427 | stack_offset += mips_stack_argsize (tdep); |
ebafbe83 MS |
3428 | } |
3429 | ||
3430 | /* Now load as many as possible of the first arguments into | |
3431 | registers, and push the rest onto the stack. Loop thru args | |
3432 | from first to last. */ | |
3433 | for (argnum = 0; argnum < nargs; argnum++) | |
3434 | { | |
3435 | char *val; | |
ebafbe83 MS |
3436 | struct value *arg = args[argnum]; |
3437 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3438 | int len = TYPE_LENGTH (arg_type); | |
3439 | enum type_code typecode = TYPE_CODE (arg_type); | |
3440 | ||
3441 | if (mips_debug) | |
3442 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3443 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3444 | argnum + 1, len, (int) typecode); |
3445 | ||
3446 | val = (char *) VALUE_CONTENTS (arg); | |
3447 | ||
3448 | /* 32-bit ABIs always start floating point arguments in an | |
3449 | even-numbered floating point register. Round the FP register | |
3450 | up before the check to see if there are any FP registers | |
3451 | left. O32/O64 targets also pass the FP in the integer | |
3452 | registers so also round up normal registers. */ | |
6d82d43b | 3453 | if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3454 | { |
3455 | if ((float_argreg & 1)) | |
3456 | float_argreg++; | |
3457 | } | |
3458 | ||
3459 | /* Floating point arguments passed in registers have to be | |
3460 | treated specially. On 32-bit architectures, doubles | |
3461 | are passed in register pairs; the even register gets | |
3462 | the low word, and the odd register gets the high word. | |
3463 | On O32/O64, the first two floating point arguments are | |
3464 | also copied to general registers, because MIPS16 functions | |
3465 | don't use float registers for arguments. This duplication of | |
3466 | arguments in general registers can't hurt non-MIPS16 functions | |
3467 | because those registers are normally skipped. */ | |
3468 | ||
3469 | if (fp_register_arg_p (typecode, arg_type) | |
3470 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3471 | { | |
3472 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3473 | { | |
3474 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3475 | unsigned long regval; | |
3476 | ||
3477 | /* Write the low word of the double to the even register(s). */ | |
3478 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3479 | if (mips_debug) | |
3480 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3481 | float_argreg, phex (regval, 4)); | |
3482 | write_register (float_argreg++, regval); | |
3483 | if (mips_debug) | |
3484 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3485 | argreg, phex (regval, 4)); | |
3486 | write_register (argreg++, regval); | |
3487 | ||
3488 | /* Write the high word of the double to the odd register(s). */ | |
3489 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3490 | if (mips_debug) | |
3491 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3492 | float_argreg, phex (regval, 4)); | |
3493 | write_register (float_argreg++, regval); | |
3494 | ||
3495 | if (mips_debug) | |
3496 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3497 | argreg, phex (regval, 4)); | |
3498 | write_register (argreg++, regval); | |
3499 | } | |
3500 | else | |
3501 | { | |
3502 | /* This is a floating point value that fits entirely | |
3503 | in a single register. */ | |
3504 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3505 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3506 | LONGEST regval = extract_unsigned_integer (val, len); |
3507 | if (mips_debug) | |
3508 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3509 | float_argreg, phex (regval, len)); | |
3510 | write_register (float_argreg++, regval); | |
3511 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3512 | registers for each argument. The below is (my |
3513 | guess) to ensure that the corresponding integer | |
3514 | register has reserved the same space. */ | |
46cac009 AC |
3515 | if (mips_debug) |
3516 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3517 | argreg, phex (regval, len)); | |
3518 | write_register (argreg, regval); | |
3519 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3520 | } | |
3521 | /* Reserve space for the FP register. */ | |
480d3dd2 | 3522 | stack_offset += align_up (len, mips_stack_argsize (tdep)); |
46cac009 AC |
3523 | } |
3524 | else | |
3525 | { | |
3526 | /* Copy the argument to general registers or the stack in | |
3527 | register-sized pieces. Large arguments are split between | |
3528 | registers and stack. */ | |
4246e332 AC |
3529 | /* Note: structs whose size is not a multiple of |
3530 | mips_regsize() are treated specially: Irix cc passes them | |
3531 | in registers where gcc sometimes puts them on the stack. | |
3532 | For maximum compatibility, we will put them in both | |
3533 | places. */ | |
480d3dd2 AC |
3534 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
3535 | && (len % mips_saved_regsize (tdep) != 0)); | |
46cac009 AC |
3536 | /* Structures should be aligned to eight bytes (even arg registers) |
3537 | on MIPS_ABI_O32, if their first member has double precision. */ | |
480d3dd2 | 3538 | if (mips_saved_regsize (tdep) < 8 |
46cac009 AC |
3539 | && mips_type_needs_double_align (arg_type)) |
3540 | { | |
3541 | if ((argreg & 1)) | |
6d82d43b | 3542 | argreg++; |
46cac009 AC |
3543 | } |
3544 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3545 | register are only written to memory. */ |
46cac009 AC |
3546 | while (len > 0) |
3547 | { | |
3548 | /* Remember if the argument was written to the stack. */ | |
3549 | int stack_used_p = 0; | |
480d3dd2 AC |
3550 | int partial_len = (len < mips_saved_regsize (tdep) |
3551 | ? len : mips_saved_regsize (tdep)); | |
46cac009 AC |
3552 | |
3553 | if (mips_debug) | |
3554 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3555 | partial_len); | |
3556 | ||
3557 | /* Write this portion of the argument to the stack. */ | |
3558 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3559 | || odd_sized_struct | |
3560 | || fp_register_arg_p (typecode, arg_type)) | |
3561 | { | |
3562 | /* Should shorter than int integer values be | |
3563 | promoted to int before being stored? */ | |
3564 | int longword_offset = 0; | |
3565 | CORE_ADDR addr; | |
3566 | stack_used_p = 1; | |
3567 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3568 | { | |
480d3dd2 AC |
3569 | if (mips_stack_argsize (tdep) == 8 |
3570 | && (typecode == TYPE_CODE_INT | |
3571 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3572 | || typecode == TYPE_CODE_FLT) && len <= 4) |
480d3dd2 | 3573 | longword_offset = mips_stack_argsize (tdep) - len; |
46cac009 AC |
3574 | } |
3575 | ||
3576 | if (mips_debug) | |
3577 | { | |
3578 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3579 | paddr_nz (stack_offset)); | |
3580 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3581 | paddr_nz (longword_offset)); | |
3582 | } | |
3583 | ||
3584 | addr = sp + stack_offset + longword_offset; | |
3585 | ||
3586 | if (mips_debug) | |
3587 | { | |
3588 | int i; | |
6d82d43b | 3589 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3590 | paddr_nz (addr)); |
3591 | for (i = 0; i < partial_len; i++) | |
3592 | { | |
6d82d43b | 3593 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3594 | val[i] & 0xff); |
3595 | } | |
3596 | } | |
3597 | write_memory (addr, val, partial_len); | |
3598 | } | |
3599 | ||
3600 | /* Note!!! This is NOT an else clause. Odd sized | |
3601 | structs may go thru BOTH paths. Floating point | |
3602 | arguments will not. */ | |
3603 | /* Write this portion of the argument to a general | |
6d82d43b | 3604 | purpose register. */ |
46cac009 AC |
3605 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3606 | && !fp_register_arg_p (typecode, arg_type)) | |
3607 | { | |
3608 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3609 | /* Value may need to be sign extended, because |
480d3dd2 | 3610 | mips_regsize() != mips_saved_regsize(). */ |
46cac009 AC |
3611 | |
3612 | /* A non-floating-point argument being passed in a | |
3613 | general register. If a struct or union, and if | |
3614 | the remaining length is smaller than the register | |
3615 | size, we have to adjust the register value on | |
3616 | big endian targets. | |
3617 | ||
3618 | It does not seem to be necessary to do the | |
3619 | same for integral types. | |
3620 | ||
3621 | Also don't do this adjustment on O64 binaries. | |
3622 | ||
3623 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3624 | outputting LE O32 with sizeof (struct) < | |
480d3dd2 | 3625 | mips_saved_regsize(), generates a left shift as |
46cac009 AC |
3626 | part of storing the argument in a register a |
3627 | register (the left shift isn't generated when | |
480d3dd2 AC |
3628 | sizeof (struct) >= mips_saved_regsize()). Since |
3629 | it is quite possible that this is GCC | |
3630 | contradicting the LE/O32 ABI, GDB has not been | |
3631 | adjusted to accommodate this. Either someone | |
3632 | needs to demonstrate that the LE/O32 ABI | |
3633 | specifies such a left shift OR this new ABI gets | |
3634 | identified as such and GDB gets tweaked | |
3635 | accordingly. */ | |
3636 | ||
3637 | if (mips_saved_regsize (tdep) < 8 | |
46cac009 | 3638 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
480d3dd2 | 3639 | && partial_len < mips_saved_regsize (tdep) |
46cac009 AC |
3640 | && (typecode == TYPE_CODE_STRUCT || |
3641 | typecode == TYPE_CODE_UNION)) | |
480d3dd2 | 3642 | regval <<= ((mips_saved_regsize (tdep) - partial_len) * |
46cac009 AC |
3643 | TARGET_CHAR_BIT); |
3644 | ||
3645 | if (mips_debug) | |
3646 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3647 | argreg, | |
6d82d43b AC |
3648 | phex (regval, |
3649 | mips_saved_regsize (tdep))); | |
46cac009 AC |
3650 | write_register (argreg, regval); |
3651 | argreg++; | |
3652 | ||
3653 | /* Prevent subsequent floating point arguments from | |
3654 | being passed in floating point registers. */ | |
3655 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3656 | } | |
3657 | ||
3658 | len -= partial_len; | |
3659 | val += partial_len; | |
3660 | ||
3661 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3662 | will copy the next parameter. |
46cac009 | 3663 | |
6d82d43b AC |
3664 | In older ABIs, the caller reserved space for |
3665 | registers that contained arguments. This was loosely | |
3666 | refered to as their "home". Consequently, space is | |
3667 | always allocated. */ | |
46cac009 | 3668 | |
480d3dd2 AC |
3669 | stack_offset += align_up (partial_len, |
3670 | mips_stack_argsize (tdep)); | |
46cac009 AC |
3671 | } |
3672 | } | |
3673 | if (mips_debug) | |
3674 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3675 | } | |
3676 | ||
310e9b6a AC |
3677 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3678 | ||
46cac009 AC |
3679 | /* Return adjusted stack pointer. */ |
3680 | return sp; | |
3681 | } | |
3682 | ||
6d82d43b AC |
3683 | static enum return_value_convention |
3684 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3685 | struct regcache *regcache, | |
3686 | void *readbuf, const void *writebuf) | |
3687 | { | |
3688 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3689 | ||
3690 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3691 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3692 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3693 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3694 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3695 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3696 | { | |
3697 | /* A single-precision floating-point value. It fits in the | |
3698 | least significant part of FP0. */ | |
3699 | if (mips_debug) | |
3700 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3701 | mips_xfer_register (regcache, | |
3702 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3703 | TYPE_LENGTH (type), | |
3704 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3705 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3706 | } | |
3707 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3708 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3709 | { | |
3710 | /* A double-precision floating-point value. The most | |
3711 | significant part goes in FP1, and the least significant in | |
3712 | FP0. */ | |
3713 | if (mips_debug) | |
3714 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
3715 | switch (TARGET_BYTE_ORDER) | |
3716 | { | |
3717 | case BFD_ENDIAN_LITTLE: | |
3718 | mips_xfer_register (regcache, | |
3719 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3720 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3721 | mips_xfer_register (regcache, | |
3722 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3723 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3724 | break; | |
3725 | case BFD_ENDIAN_BIG: | |
3726 | mips_xfer_register (regcache, | |
3727 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3728 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3729 | mips_xfer_register (regcache, | |
3730 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3731 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3732 | break; | |
3733 | default: | |
3734 | internal_error (__FILE__, __LINE__, "bad switch"); | |
3735 | } | |
3736 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3737 | } | |
3738 | #if 0 | |
3739 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3740 | && TYPE_NFIELDS (type) <= 2 | |
3741 | && TYPE_NFIELDS (type) >= 1 | |
3742 | && ((TYPE_NFIELDS (type) == 1 | |
3743 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3744 | == TYPE_CODE_FLT)) | |
3745 | || (TYPE_NFIELDS (type) == 2 | |
3746 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3747 | == TYPE_CODE_FLT) | |
3748 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3749 | == TYPE_CODE_FLT))) | |
3750 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3751 | { | |
3752 | /* A struct that contains one or two floats. Each value is part | |
3753 | in the least significant part of their floating point | |
3754 | register.. */ | |
3755 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
3756 | int regnum; | |
3757 | int field; | |
3758 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3759 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3760 | { | |
3761 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3762 | / TARGET_CHAR_BIT); | |
3763 | if (mips_debug) | |
3764 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3765 | offset); | |
3766 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3767 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3768 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3769 | } | |
3770 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3771 | } | |
3772 | #endif | |
3773 | #if 0 | |
3774 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3775 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3776 | { | |
3777 | /* A structure or union. Extract the left justified value, | |
3778 | regardless of the byte order. I.e. DO NOT USE | |
3779 | mips_xfer_lower. */ | |
3780 | int offset; | |
3781 | int regnum; | |
3782 | for (offset = 0, regnum = V0_REGNUM; | |
3783 | offset < TYPE_LENGTH (type); | |
3784 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3785 | { | |
3786 | int xfer = register_size (current_gdbarch, regnum); | |
3787 | if (offset + xfer > TYPE_LENGTH (type)) | |
3788 | xfer = TYPE_LENGTH (type) - offset; | |
3789 | if (mips_debug) | |
3790 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3791 | offset, xfer, regnum); | |
3792 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3793 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3794 | } | |
3795 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3796 | } | |
3797 | #endif | |
3798 | else | |
3799 | { | |
3800 | /* A scalar extract each part but least-significant-byte | |
3801 | justified. o32 thinks registers are 4 byte, regardless of | |
3802 | the ISA. mips_stack_argsize controls this. */ | |
3803 | int offset; | |
3804 | int regnum; | |
3805 | for (offset = 0, regnum = V0_REGNUM; | |
3806 | offset < TYPE_LENGTH (type); | |
3807 | offset += mips_stack_argsize (tdep), regnum++) | |
3808 | { | |
3809 | int xfer = mips_stack_argsize (tdep); | |
6d82d43b AC |
3810 | if (offset + xfer > TYPE_LENGTH (type)) |
3811 | xfer = TYPE_LENGTH (type) - offset; | |
3812 | if (mips_debug) | |
3813 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3814 | offset, xfer, regnum); | |
3815 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3816 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3817 | } | |
3818 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3819 | } | |
3820 | } | |
3821 | ||
3822 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3823 | ABI. */ | |
46cac009 AC |
3824 | |
3825 | static CORE_ADDR | |
25ab4790 | 3826 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
6d82d43b AC |
3827 | struct regcache *regcache, CORE_ADDR bp_addr, |
3828 | int nargs, | |
3829 | struct value **args, CORE_ADDR sp, | |
3830 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3831 | { |
3832 | int argreg; | |
3833 | int float_argreg; | |
3834 | int argnum; | |
3835 | int len = 0; | |
3836 | int stack_offset = 0; | |
480d3dd2 | 3837 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
46cac009 | 3838 | |
25ab4790 AC |
3839 | /* For shared libraries, "t9" needs to point at the function |
3840 | address. */ | |
3841 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3842 | ||
3843 | /* Set the return address register to point to the entry point of | |
3844 | the program, where a breakpoint lies in wait. */ | |
3845 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3846 | ||
46cac009 AC |
3847 | /* First ensure that the stack and structure return address (if any) |
3848 | are properly aligned. The stack has to be at least 64-bit | |
3849 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3850 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3851 | aligned, so we round to this widest known alignment. */ | |
3852 | ||
5b03f266 AC |
3853 | sp = align_down (sp, 16); |
3854 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3855 | |
3856 | /* Now make space on the stack for the args. */ | |
3857 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3858 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 3859 | mips_stack_argsize (tdep)); |
5b03f266 | 3860 | sp -= align_up (len, 16); |
46cac009 AC |
3861 | |
3862 | if (mips_debug) | |
6d82d43b | 3863 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3864 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3865 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3866 | |
3867 | /* Initialize the integer and float register pointers. */ | |
3868 | argreg = A0_REGNUM; | |
56cea623 | 3869 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3870 | |
3871 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3872 | if (struct_return) | |
3873 | { | |
3874 | if (mips_debug) | |
3875 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3876 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3877 | argreg, paddr_nz (struct_addr)); |
3878 | write_register (argreg++, struct_addr); | |
480d3dd2 | 3879 | stack_offset += mips_stack_argsize (tdep); |
46cac009 AC |
3880 | } |
3881 | ||
3882 | /* Now load as many as possible of the first arguments into | |
3883 | registers, and push the rest onto the stack. Loop thru args | |
3884 | from first to last. */ | |
3885 | for (argnum = 0; argnum < nargs; argnum++) | |
3886 | { | |
3887 | char *val; | |
46cac009 AC |
3888 | struct value *arg = args[argnum]; |
3889 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3890 | int len = TYPE_LENGTH (arg_type); | |
3891 | enum type_code typecode = TYPE_CODE (arg_type); | |
3892 | ||
3893 | if (mips_debug) | |
3894 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3895 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3896 | argnum + 1, len, (int) typecode); |
3897 | ||
3898 | val = (char *) VALUE_CONTENTS (arg); | |
3899 | ||
3900 | /* 32-bit ABIs always start floating point arguments in an | |
3901 | even-numbered floating point register. Round the FP register | |
3902 | up before the check to see if there are any FP registers | |
3903 | left. O32/O64 targets also pass the FP in the integer | |
3904 | registers so also round up normal registers. */ | |
6d82d43b | 3905 | if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type)) |
ebafbe83 MS |
3906 | { |
3907 | if ((float_argreg & 1)) | |
3908 | float_argreg++; | |
3909 | } | |
3910 | ||
3911 | /* Floating point arguments passed in registers have to be | |
3912 | treated specially. On 32-bit architectures, doubles | |
3913 | are passed in register pairs; the even register gets | |
3914 | the low word, and the odd register gets the high word. | |
3915 | On O32/O64, the first two floating point arguments are | |
3916 | also copied to general registers, because MIPS16 functions | |
3917 | don't use float registers for arguments. This duplication of | |
3918 | arguments in general registers can't hurt non-MIPS16 functions | |
3919 | because those registers are normally skipped. */ | |
3920 | ||
3921 | if (fp_register_arg_p (typecode, arg_type) | |
3922 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3923 | { | |
3924 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3925 | { | |
3926 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3927 | unsigned long regval; | |
3928 | ||
3929 | /* Write the low word of the double to the even register(s). */ | |
3930 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3931 | if (mips_debug) | |
3932 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3933 | float_argreg, phex (regval, 4)); | |
3934 | write_register (float_argreg++, regval); | |
3935 | if (mips_debug) | |
3936 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3937 | argreg, phex (regval, 4)); | |
3938 | write_register (argreg++, regval); | |
3939 | ||
3940 | /* Write the high word of the double to the odd register(s). */ | |
3941 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3942 | if (mips_debug) | |
3943 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3944 | float_argreg, phex (regval, 4)); | |
3945 | write_register (float_argreg++, regval); | |
3946 | ||
3947 | if (mips_debug) | |
3948 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3949 | argreg, phex (regval, 4)); | |
3950 | write_register (argreg++, regval); | |
3951 | } | |
3952 | else | |
3953 | { | |
3954 | /* This is a floating point value that fits entirely | |
3955 | in a single register. */ | |
3956 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3957 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
3958 | LONGEST regval = extract_unsigned_integer (val, len); |
3959 | if (mips_debug) | |
3960 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3961 | float_argreg, phex (regval, len)); | |
3962 | write_register (float_argreg++, regval); | |
3963 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3964 | registers for each argument. The below is (my |
3965 | guess) to ensure that the corresponding integer | |
3966 | register has reserved the same space. */ | |
ebafbe83 MS |
3967 | if (mips_debug) |
3968 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3969 | argreg, phex (regval, len)); | |
3970 | write_register (argreg, regval); | |
3971 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3972 | } | |
3973 | /* Reserve space for the FP register. */ | |
480d3dd2 | 3974 | stack_offset += align_up (len, mips_stack_argsize (tdep)); |
ebafbe83 MS |
3975 | } |
3976 | else | |
3977 | { | |
3978 | /* Copy the argument to general registers or the stack in | |
3979 | register-sized pieces. Large arguments are split between | |
3980 | registers and stack. */ | |
4246e332 AC |
3981 | /* Note: structs whose size is not a multiple of |
3982 | mips_regsize() are treated specially: Irix cc passes them | |
3983 | in registers where gcc sometimes puts them on the stack. | |
3984 | For maximum compatibility, we will put them in both | |
3985 | places. */ | |
480d3dd2 AC |
3986 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
3987 | && (len % mips_saved_regsize (tdep) != 0)); | |
ebafbe83 MS |
3988 | /* Structures should be aligned to eight bytes (even arg registers) |
3989 | on MIPS_ABI_O32, if their first member has double precision. */ | |
480d3dd2 | 3990 | if (mips_saved_regsize (tdep) < 8 |
ebafbe83 MS |
3991 | && mips_type_needs_double_align (arg_type)) |
3992 | { | |
3993 | if ((argreg & 1)) | |
6d82d43b | 3994 | argreg++; |
ebafbe83 MS |
3995 | } |
3996 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3997 | register are only written to memory. */ |
ebafbe83 MS |
3998 | while (len > 0) |
3999 | { | |
4000 | /* Remember if the argument was written to the stack. */ | |
4001 | int stack_used_p = 0; | |
480d3dd2 AC |
4002 | int partial_len = (len < mips_saved_regsize (tdep) |
4003 | ? len : mips_saved_regsize (tdep)); | |
ebafbe83 MS |
4004 | |
4005 | if (mips_debug) | |
4006 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4007 | partial_len); | |
4008 | ||
4009 | /* Write this portion of the argument to the stack. */ | |
4010 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4011 | || odd_sized_struct | |
4012 | || fp_register_arg_p (typecode, arg_type)) | |
4013 | { | |
4014 | /* Should shorter than int integer values be | |
4015 | promoted to int before being stored? */ | |
4016 | int longword_offset = 0; | |
4017 | CORE_ADDR addr; | |
4018 | stack_used_p = 1; | |
4019 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4020 | { | |
480d3dd2 AC |
4021 | if (mips_stack_argsize (tdep) == 8 |
4022 | && (typecode == TYPE_CODE_INT | |
4023 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4024 | || typecode == TYPE_CODE_FLT) && len <= 4) |
480d3dd2 | 4025 | longword_offset = mips_stack_argsize (tdep) - len; |
ebafbe83 MS |
4026 | } |
4027 | ||
4028 | if (mips_debug) | |
4029 | { | |
4030 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4031 | paddr_nz (stack_offset)); | |
4032 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4033 | paddr_nz (longword_offset)); | |
4034 | } | |
4035 | ||
4036 | addr = sp + stack_offset + longword_offset; | |
4037 | ||
4038 | if (mips_debug) | |
4039 | { | |
4040 | int i; | |
6d82d43b | 4041 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4042 | paddr_nz (addr)); |
4043 | for (i = 0; i < partial_len; i++) | |
4044 | { | |
6d82d43b | 4045 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4046 | val[i] & 0xff); |
4047 | } | |
4048 | } | |
4049 | write_memory (addr, val, partial_len); | |
4050 | } | |
4051 | ||
4052 | /* Note!!! This is NOT an else clause. Odd sized | |
4053 | structs may go thru BOTH paths. Floating point | |
4054 | arguments will not. */ | |
4055 | /* Write this portion of the argument to a general | |
6d82d43b | 4056 | purpose register. */ |
ebafbe83 MS |
4057 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4058 | && !fp_register_arg_p (typecode, arg_type)) | |
4059 | { | |
4060 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4061 | /* Value may need to be sign extended, because |
480d3dd2 | 4062 | mips_regsize() != mips_saved_regsize(). */ |
ebafbe83 MS |
4063 | |
4064 | /* A non-floating-point argument being passed in a | |
4065 | general register. If a struct or union, and if | |
4066 | the remaining length is smaller than the register | |
4067 | size, we have to adjust the register value on | |
4068 | big endian targets. | |
4069 | ||
4070 | It does not seem to be necessary to do the | |
4071 | same for integral types. | |
4072 | ||
4073 | Also don't do this adjustment on O64 binaries. | |
4074 | ||
4075 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4076 | outputting LE O32 with sizeof (struct) < | |
480d3dd2 | 4077 | mips_saved_regsize(), generates a left shift as |
ebafbe83 MS |
4078 | part of storing the argument in a register a |
4079 | register (the left shift isn't generated when | |
480d3dd2 AC |
4080 | sizeof (struct) >= mips_saved_regsize()). Since |
4081 | it is quite possible that this is GCC | |
4082 | contradicting the LE/O32 ABI, GDB has not been | |
4083 | adjusted to accommodate this. Either someone | |
4084 | needs to demonstrate that the LE/O32 ABI | |
4085 | specifies such a left shift OR this new ABI gets | |
4086 | identified as such and GDB gets tweaked | |
4087 | accordingly. */ | |
4088 | ||
4089 | if (mips_saved_regsize (tdep) < 8 | |
ebafbe83 | 4090 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
480d3dd2 | 4091 | && partial_len < mips_saved_regsize (tdep) |
ebafbe83 MS |
4092 | && (typecode == TYPE_CODE_STRUCT || |
4093 | typecode == TYPE_CODE_UNION)) | |
480d3dd2 | 4094 | regval <<= ((mips_saved_regsize (tdep) - partial_len) * |
ebafbe83 MS |
4095 | TARGET_CHAR_BIT); |
4096 | ||
4097 | if (mips_debug) | |
4098 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4099 | argreg, | |
6d82d43b AC |
4100 | phex (regval, |
4101 | mips_saved_regsize (tdep))); | |
ebafbe83 MS |
4102 | write_register (argreg, regval); |
4103 | argreg++; | |
4104 | ||
4105 | /* Prevent subsequent floating point arguments from | |
4106 | being passed in floating point registers. */ | |
4107 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4108 | } | |
4109 | ||
4110 | len -= partial_len; | |
4111 | val += partial_len; | |
4112 | ||
4113 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4114 | will copy the next parameter. |
ebafbe83 | 4115 | |
6d82d43b AC |
4116 | In older ABIs, the caller reserved space for |
4117 | registers that contained arguments. This was loosely | |
4118 | refered to as their "home". Consequently, space is | |
4119 | always allocated. */ | |
ebafbe83 | 4120 | |
480d3dd2 AC |
4121 | stack_offset += align_up (partial_len, |
4122 | mips_stack_argsize (tdep)); | |
ebafbe83 MS |
4123 | } |
4124 | } | |
4125 | if (mips_debug) | |
4126 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4127 | } | |
4128 | ||
310e9b6a AC |
4129 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
4130 | ||
ebafbe83 MS |
4131 | /* Return adjusted stack pointer. */ |
4132 | return sp; | |
4133 | } | |
4134 | ||
f7ab6ec6 | 4135 | static void |
6d82d43b AC |
4136 | mips_o64_extract_return_value (struct type *valtype, |
4137 | char regbuf[], char *valbuf) | |
c906108c | 4138 | { |
6d82d43b AC |
4139 | struct return_value_word lo; |
4140 | struct return_value_word hi; | |
4141 | return_value_location (valtype, &hi, &lo); | |
c906108c | 4142 | |
6d82d43b AC |
4143 | memcpy (valbuf + lo.buf_offset, |
4144 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
4145 | lo.reg_offset, lo.len); | |
4146 | ||
4147 | if (hi.len > 0) | |
4148 | memcpy (valbuf + hi.buf_offset, | |
4149 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
4150 | hi.reg_offset, hi.len); | |
4151 | } | |
4152 | ||
4153 | static void | |
4154 | mips_o64_store_return_value (struct type *valtype, char *valbuf) | |
4155 | { | |
4156 | char raw_buffer[MAX_REGISTER_SIZE]; | |
4157 | struct return_value_word lo; | |
4158 | struct return_value_word hi; | |
4159 | return_value_location (valtype, &hi, &lo); | |
4160 | ||
4161 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4162 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4163 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
4164 | raw_buffer, register_size (current_gdbarch, | |
4165 | lo.reg)); | |
4166 | ||
4167 | if (hi.len > 0) | |
4168 | { | |
4169 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4170 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4171 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
4172 | raw_buffer, | |
4173 | register_size (current_gdbarch, | |
4174 | hi.reg)); | |
4175 | } | |
4176 | } | |
4177 | ||
dd824b04 DJ |
4178 | /* Floating point register management. |
4179 | ||
4180 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4181 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4182 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4183 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4184 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4185 | double precision floats into two 32-bit chunks and store them in | |
4186 | consecutive fp regs. To display 64-bit floats stored in this | |
4187 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4188 | Throw in user-configurable endianness and you have a real mess. | |
4189 | ||
4190 | The way this works is: | |
4191 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4192 | double-precision value will be split across two logical registers. | |
4193 | The lower-numbered logical register will hold the low-order bits, | |
4194 | regardless of the processor's endianness. | |
4195 | - If we are on a 64-bit processor, and we are looking for a | |
4196 | single-precision value, it will be in the low ordered bits | |
4197 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4198 | save slot in memory. | |
4199 | - If we are in 64-bit mode, everything is straightforward. | |
4200 | ||
4201 | Note that this code only deals with "live" registers at the top of the | |
4202 | stack. We will attempt to deal with saved registers later, when | |
4203 | the raw/cooked register interface is in place. (We need a general | |
4204 | interface that can deal with dynamic saved register sizes -- fp | |
4205 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4206 | and below). */ | |
4207 | ||
67b2c998 DJ |
4208 | static struct type * |
4209 | mips_float_register_type (void) | |
4210 | { | |
361d1df0 | 4211 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4212 | return builtin_type_ieee_single_big; |
4213 | else | |
4214 | return builtin_type_ieee_single_little; | |
4215 | } | |
4216 | ||
4217 | static struct type * | |
4218 | mips_double_register_type (void) | |
4219 | { | |
361d1df0 | 4220 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4221 | return builtin_type_ieee_double_big; |
4222 | else | |
4223 | return builtin_type_ieee_double_little; | |
4224 | } | |
4225 | ||
dd824b04 DJ |
4226 | /* Copy a 32-bit single-precision value from the current frame |
4227 | into rare_buffer. */ | |
4228 | ||
4229 | static void | |
e11c53d2 AC |
4230 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4231 | char *rare_buffer) | |
dd824b04 | 4232 | { |
719ec221 | 4233 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4234 | char *raw_buffer = alloca (raw_size); |
4235 | ||
e11c53d2 | 4236 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4237 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4238 | if (raw_size == 8) | |
4239 | { | |
4240 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4241 | 32 bits. */ |
dd824b04 DJ |
4242 | int offset; |
4243 | ||
4244 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4245 | offset = 4; | |
4246 | else | |
4247 | offset = 0; | |
4248 | ||
4249 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4250 | } | |
4251 | else | |
4252 | { | |
4253 | memcpy (rare_buffer, raw_buffer, 4); | |
4254 | } | |
4255 | } | |
4256 | ||
4257 | /* Copy a 64-bit double-precision value from the current frame into | |
4258 | rare_buffer. This may include getting half of it from the next | |
4259 | register. */ | |
4260 | ||
4261 | static void | |
e11c53d2 AC |
4262 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4263 | char *rare_buffer) | |
dd824b04 | 4264 | { |
719ec221 | 4265 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4266 | |
4267 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4268 | { | |
4269 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4270 | all 64 bits. */ |
e11c53d2 | 4271 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4272 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4273 | } | |
4274 | else | |
4275 | { | |
56cea623 | 4276 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4277 | internal_error (__FILE__, __LINE__, |
4278 | "mips_read_fp_register_double: bad access to " | |
4279 | "odd-numbered FP register"); | |
4280 | ||
4281 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4282 | each register. */ |
dd824b04 DJ |
4283 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
4284 | { | |
e11c53d2 AC |
4285 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4286 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4287 | } |
361d1df0 | 4288 | else |
dd824b04 | 4289 | { |
e11c53d2 AC |
4290 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4291 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4292 | } |
4293 | } | |
4294 | } | |
4295 | ||
c906108c | 4296 | static void |
e11c53d2 AC |
4297 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4298 | int regnum) | |
c5aa993b | 4299 | { /* do values for FP (float) regs */ |
dd824b04 | 4300 | char *raw_buffer; |
3903d437 AC |
4301 | double doub, flt1; /* doubles extracted from raw hex data */ |
4302 | int inv1, inv2; | |
c5aa993b | 4303 | |
6d82d43b AC |
4304 | raw_buffer = |
4305 | (char *) alloca (2 * | |
4306 | register_size (current_gdbarch, | |
4307 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4308 | |
e11c53d2 AC |
4309 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4310 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4311 | ""); | |
f0ef6b29 | 4312 | |
719ec221 | 4313 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4314 | { |
f0ef6b29 KB |
4315 | /* 4-byte registers: Print hex and floating. Also print even |
4316 | numbered registers as doubles. */ | |
e11c53d2 | 4317 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4318 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4319 | |
6d82d43b AC |
4320 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4321 | file); | |
dd824b04 | 4322 | |
e11c53d2 | 4323 | fprintf_filtered (file, " flt: "); |
1adad886 | 4324 | if (inv1) |
e11c53d2 | 4325 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4326 | else |
e11c53d2 | 4327 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4328 | |
f0ef6b29 KB |
4329 | if (regnum % 2 == 0) |
4330 | { | |
e11c53d2 | 4331 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4332 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4333 | &inv2); |
1adad886 | 4334 | |
e11c53d2 | 4335 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4336 | if (inv2) |
e11c53d2 | 4337 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4338 | else |
e11c53d2 | 4339 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4340 | } |
c906108c SS |
4341 | } |
4342 | else | |
dd824b04 | 4343 | { |
f0ef6b29 | 4344 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4345 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4346 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4347 | |
e11c53d2 | 4348 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4349 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4350 | ||
361d1df0 | 4351 | |
6d82d43b AC |
4352 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4353 | file); | |
f0ef6b29 | 4354 | |
e11c53d2 | 4355 | fprintf_filtered (file, " flt: "); |
1adad886 | 4356 | if (inv1) |
e11c53d2 | 4357 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4358 | else |
e11c53d2 | 4359 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4360 | |
e11c53d2 | 4361 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4362 | if (inv2) |
e11c53d2 | 4363 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4364 | else |
e11c53d2 | 4365 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4366 | } |
4367 | } | |
4368 | ||
4369 | static void | |
e11c53d2 AC |
4370 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4371 | int regnum, int all) | |
f0ef6b29 | 4372 | { |
a4b8ebc8 | 4373 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4374 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4375 | int offset; |
1adad886 | 4376 | |
a4b8ebc8 | 4377 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4378 | { |
e11c53d2 | 4379 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4380 | return; |
4381 | } | |
4382 | ||
4383 | /* Get the data in raw format. */ | |
e11c53d2 | 4384 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4385 | { |
e11c53d2 | 4386 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4387 | return; |
c906108c | 4388 | } |
f0ef6b29 | 4389 | |
e11c53d2 | 4390 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4391 | |
4392 | /* The problem with printing numeric register names (r26, etc.) is that | |
4393 | the user can't use them on input. Probably the best solution is to | |
4394 | fix it so that either the numeric or the funky (a2, etc.) names | |
4395 | are accepted on input. */ | |
4396 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4397 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4398 | else |
e11c53d2 | 4399 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4400 | |
4401 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
4402 | offset = |
4403 | register_size (current_gdbarch, | |
4404 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4405 | else |
4406 | offset = 0; | |
4407 | ||
6d82d43b AC |
4408 | print_scalar_formatted (raw_buffer + offset, |
4409 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
4410 | file); | |
c906108c SS |
4411 | } |
4412 | ||
f0ef6b29 KB |
4413 | /* Replacement for generic do_registers_info. |
4414 | Print regs in pretty columns. */ | |
4415 | ||
4416 | static int | |
e11c53d2 AC |
4417 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4418 | int regnum) | |
f0ef6b29 | 4419 | { |
e11c53d2 AC |
4420 | fprintf_filtered (file, " "); |
4421 | mips_print_fp_register (file, frame, regnum); | |
4422 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4423 | return regnum + 1; |
4424 | } | |
4425 | ||
4426 | ||
c906108c SS |
4427 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4428 | ||
4429 | static int | |
e11c53d2 | 4430 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4431 | int start_regnum) |
c906108c | 4432 | { |
a4b8ebc8 | 4433 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4434 | /* do values for GP (int) regs */ |
d9d9c31f | 4435 | char raw_buffer[MAX_REGISTER_SIZE]; |
4246e332 | 4436 | int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4437 | int col, byte; |
a4b8ebc8 | 4438 | int regnum; |
c906108c SS |
4439 | |
4440 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4441 | fprintf_filtered (file, " "); |
a4b8ebc8 | 4442 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4443 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4444 | { |
4445 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4446 | continue; /* unused register */ |
6d82d43b AC |
4447 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4448 | TYPE_CODE_FLT) | |
c5aa993b | 4449 | break; /* end the row: reached FP register */ |
6d82d43b AC |
4450 | fprintf_filtered (file, |
4451 | mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", | |
e11c53d2 | 4452 | REGISTER_NAME (regnum)); |
c906108c SS |
4453 | col++; |
4454 | } | |
a4b8ebc8 | 4455 | /* print the R0 to R31 names */ |
20e6603c AC |
4456 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4457 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4458 | else | |
4459 | fprintf_filtered (file, "\n "); | |
c906108c | 4460 | |
c906108c | 4461 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4462 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4463 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4464 | { |
4465 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4466 | continue; /* unused register */ |
6d82d43b AC |
4467 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4468 | TYPE_CODE_FLT) | |
c5aa993b | 4469 | break; /* end row: reached FP register */ |
c906108c | 4470 | /* OK: get the data in raw format. */ |
e11c53d2 | 4471 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4472 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4473 | /* pad small registers */ | |
4246e332 AC |
4474 | for (byte = 0; |
4475 | byte < (mips_regsize (current_gdbarch) | |
6d82d43b | 4476 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4477 | printf_filtered (" "); |
4478 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4479 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
4480 | for (byte = |
4481 | register_size (current_gdbarch, | |
4482 | regnum) - register_size (current_gdbarch, regnum); | |
4483 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 4484 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4485 | else |
c73e8f27 | 4486 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4487 | byte >= 0; byte--) |
e11c53d2 AC |
4488 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4489 | fprintf_filtered (file, " "); | |
c906108c SS |
4490 | col++; |
4491 | } | |
c5aa993b | 4492 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4493 | fprintf_filtered (file, "\n"); |
c906108c SS |
4494 | |
4495 | return regnum; | |
4496 | } | |
4497 | ||
4498 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4499 | ||
bf1f5b4c | 4500 | static void |
e11c53d2 AC |
4501 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4502 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4503 | { |
c5aa993b | 4504 | if (regnum != -1) /* do one specified register */ |
c906108c | 4505 | { |
a4b8ebc8 | 4506 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4507 | if (*(REGISTER_NAME (regnum)) == '\0') |
4508 | error ("Not a valid register for the current processor type"); | |
4509 | ||
e11c53d2 AC |
4510 | mips_print_register (file, frame, regnum, 0); |
4511 | fprintf_filtered (file, "\n"); | |
c906108c | 4512 | } |
c5aa993b JM |
4513 | else |
4514 | /* do all (or most) registers */ | |
c906108c | 4515 | { |
a4b8ebc8 AC |
4516 | regnum = NUM_REGS; |
4517 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4518 | { |
6d82d43b AC |
4519 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4520 | TYPE_CODE_FLT) | |
e11c53d2 AC |
4521 | { |
4522 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4523 | regnum = print_fp_register_row (file, frame, regnum); | |
4524 | else | |
4525 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4526 | } | |
c906108c | 4527 | else |
e11c53d2 | 4528 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4529 | } |
4530 | } | |
4531 | } | |
4532 | ||
c906108c SS |
4533 | /* Is this a branch with a delay slot? */ |
4534 | ||
a14ed312 | 4535 | static int is_delayed (unsigned long); |
c906108c SS |
4536 | |
4537 | static int | |
acdb74a0 | 4538 | is_delayed (unsigned long insn) |
c906108c SS |
4539 | { |
4540 | int i; | |
4541 | for (i = 0; i < NUMOPCODES; ++i) | |
4542 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4543 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4544 | break; | |
4545 | return (i < NUMOPCODES | |
4546 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4547 | | INSN_COND_BRANCH_DELAY | |
4548 | | INSN_COND_BRANCH_LIKELY))); | |
4549 | } | |
4550 | ||
4551 | int | |
acdb74a0 | 4552 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4553 | { |
4554 | char buf[MIPS_INSTLEN]; | |
4555 | ||
4556 | /* There is no branch delay slot on MIPS16. */ | |
4557 | if (pc_is_mips16 (pc)) | |
4558 | return 0; | |
4559 | ||
4560 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4561 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4562 | return 0; | |
6d82d43b AC |
4563 | return is_delayed ((unsigned long) |
4564 | extract_unsigned_integer (buf, MIPS_INSTLEN)); | |
c906108c SS |
4565 | } |
4566 | ||
4567 | ||
74da7425 AC |
4568 | /* Given PC at the function's start address, attempt to find the |
4569 | prologue end using SAL information. Return zero if the skip fails. | |
4570 | ||
4571 | A non-optimized prologue traditionally has one SAL for the function | |
4572 | and a second for the function body. A single line function has | |
4573 | them both pointing at the same line. | |
4574 | ||
4575 | An optimized prologue is similar but the prologue may contain | |
4576 | instructions (SALs) from the instruction body. Need to skip those | |
4577 | while not getting into the function body. | |
4578 | ||
4579 | The functions end point and an increasing SAL line are used as | |
4580 | indicators of the prologue's endpoint. | |
4581 | ||
4582 | This code is based on the function refine_prologue_limit (versions | |
4583 | found in both ia64 and ppc). */ | |
4584 | ||
4585 | static CORE_ADDR | |
4586 | skip_prologue_using_sal (CORE_ADDR func_addr) | |
4587 | { | |
4588 | struct symtab_and_line prologue_sal; | |
4589 | CORE_ADDR start_pc; | |
4590 | CORE_ADDR end_pc; | |
4591 | ||
4592 | /* Get an initial range for the function. */ | |
4593 | find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc); | |
4594 | start_pc += FUNCTION_START_OFFSET; | |
4595 | ||
4596 | prologue_sal = find_pc_line (start_pc, 0); | |
4597 | if (prologue_sal.line != 0) | |
4598 | { | |
4599 | while (prologue_sal.end < end_pc) | |
4600 | { | |
4601 | struct symtab_and_line sal; | |
4602 | ||
4603 | sal = find_pc_line (prologue_sal.end, 0); | |
4604 | if (sal.line == 0) | |
4605 | break; | |
4606 | /* Assume that a consecutive SAL for the same (or larger) | |
6d82d43b | 4607 | line mark the prologue -> body transition. */ |
74da7425 AC |
4608 | if (sal.line >= prologue_sal.line) |
4609 | break; | |
4610 | /* The case in which compiler's optimizer/scheduler has | |
4611 | moved instructions into the prologue. We look ahead in | |
4612 | the function looking for address ranges whose | |
4613 | corresponding line number is less the first one that we | |
4614 | found for the function. This is more conservative then | |
4615 | refine_prologue_limit which scans a large number of SALs | |
4616 | looking for any in the prologue */ | |
4617 | prologue_sal = sal; | |
4618 | } | |
4619 | } | |
4620 | return prologue_sal.end; | |
4621 | } | |
4622 | ||
c906108c SS |
4623 | /* Skip the PC past function prologue instructions (32-bit version). |
4624 | This is a helper function for mips_skip_prologue. */ | |
4625 | ||
4626 | static CORE_ADDR | |
f7b9e9fc | 4627 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4628 | { |
c5aa993b JM |
4629 | t_inst inst; |
4630 | CORE_ADDR end_pc; | |
4631 | int seen_sp_adjust = 0; | |
4632 | int load_immediate_bytes = 0; | |
4633 | ||
74da7425 AC |
4634 | /* Find an upper bound on the prologue. */ |
4635 | end_pc = skip_prologue_using_sal (pc); | |
4636 | if (end_pc == 0) | |
6d82d43b | 4637 | end_pc = pc + 100; /* Magic. */ |
74da7425 | 4638 | |
c5aa993b JM |
4639 | /* Skip the typical prologue instructions. These are the stack adjustment |
4640 | instruction and the instructions that save registers on the stack | |
4641 | or in the gcc frame. */ | |
74da7425 | 4642 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
4643 | { |
4644 | unsigned long high_word; | |
c906108c | 4645 | |
c5aa993b JM |
4646 | inst = mips_fetch_instruction (pc); |
4647 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4648 | |
c5aa993b JM |
4649 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4650 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4651 | seen_sp_adjust = 1; | |
4652 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4653 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4654 | seen_sp_adjust = 1; | |
4655 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4656 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4657 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4658 | continue; | |
4659 | ||
4660 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4661 | continue; | |
4662 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4663 | /* sx reg,n($s8) */ | |
4664 | continue; /* reg != $zero */ | |
4665 | ||
4666 | /* move $s8,$sp. With different versions of gas this will be either | |
4667 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4668 | Accept any one of these. */ | |
4669 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4670 | continue; | |
4671 | ||
4672 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4673 | continue; | |
6d82d43b AC |
4674 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
4675 | continue; | |
4676 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4677 | continue; | |
4678 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4679 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4680 | continue; | |
4681 | /* The following instructions load $at or $t0 with an immediate | |
4682 | value in preparation for a stack adjustment via | |
4683 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4684 | a local variable, so we accept them only before a stack adjustment | |
4685 | instruction was seen. */ | |
4686 | else if (!seen_sp_adjust) | |
cb1d2653 | 4687 | { |
6d82d43b AC |
4688 | if (high_word == 0x3c01 || /* lui $at,n */ |
4689 | high_word == 0x3c08) /* lui $t0,n */ | |
4690 | { | |
4691 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4692 | continue; | |
4693 | } | |
4694 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4695 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4696 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4697 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4698 | { | |
4699 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4700 | continue; | |
4701 | } | |
4702 | else | |
4703 | break; | |
cb1d2653 | 4704 | } |
6d82d43b AC |
4705 | else |
4706 | break; | |
46cac009 | 4707 | } |
6d82d43b AC |
4708 | |
4709 | /* In a frameless function, we might have incorrectly | |
4710 | skipped some load immediate instructions. Undo the skipping | |
4711 | if the load immediate was not followed by a stack adjustment. */ | |
4712 | if (load_immediate_bytes && !seen_sp_adjust) | |
4713 | pc -= load_immediate_bytes; | |
4714 | return pc; | |
46cac009 AC |
4715 | } |
4716 | ||
6d82d43b AC |
4717 | /* Skip the PC past function prologue instructions (16-bit version). |
4718 | This is a helper function for mips_skip_prologue. */ | |
cb1d2653 | 4719 | |
6d82d43b AC |
4720 | static CORE_ADDR |
4721 | mips16_skip_prologue (CORE_ADDR pc) | |
c906108c | 4722 | { |
6d82d43b AC |
4723 | CORE_ADDR end_pc; |
4724 | int extend_bytes = 0; | |
4725 | int prev_extend_bytes; | |
4726 | ||
4727 | /* Table of instructions likely to be found in a function prologue. */ | |
4728 | static struct | |
4729 | { | |
4730 | unsigned short inst; | |
4731 | unsigned short mask; | |
4732 | } | |
4733 | table[] = | |
4734 | { | |
7a292a7a | 4735 | { |
6d82d43b AC |
4736 | 0x6300, 0xff00} |
4737 | , /* addiu $sp,offset */ | |
88658117 | 4738 | { |
6d82d43b AC |
4739 | 0xfb00, 0xff00} |
4740 | , /* daddiu $sp,offset */ | |
88658117 | 4741 | { |
6d82d43b AC |
4742 | 0xd000, 0xf800} |
4743 | , /* sw reg,n($sp) */ | |
4744 | { | |
4745 | 0xf900, 0xff00} | |
4746 | , /* sd reg,n($sp) */ | |
4747 | { | |
4748 | 0x6200, 0xff00} | |
4749 | , /* sw $ra,n($sp) */ | |
4750 | { | |
4751 | 0xfa00, 0xff00} | |
4752 | , /* sd $ra,n($sp) */ | |
4753 | { | |
4754 | 0x673d, 0xffff} | |
4755 | , /* move $s1,sp */ | |
4756 | { | |
4757 | 0xd980, 0xff80} | |
4758 | , /* sw $a0-$a3,n($s1) */ | |
4759 | { | |
4760 | 0x6704, 0xff1c} | |
4761 | , /* move reg,$a0-$a3 */ | |
4762 | { | |
4763 | 0xe809, 0xf81f} | |
4764 | , /* entry pseudo-op */ | |
4765 | { | |
4766 | 0x0100, 0xff00} | |
4767 | , /* addiu $s1,$sp,n */ | |
4768 | { | |
4769 | 0, 0} /* end of table marker */ | |
4770 | }; | |
4771 | ||
4772 | /* Find an upper bound on the prologue. */ | |
4773 | end_pc = skip_prologue_using_sal (pc); | |
4774 | if (end_pc == 0) | |
4775 | end_pc = pc + 100; /* Magic. */ | |
4776 | ||
4777 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4778 | instruction and the instructions that save registers on the stack | |
4779 | or in the gcc frame. */ | |
4780 | for (; pc < end_pc; pc += MIPS16_INSTLEN) | |
4781 | { | |
4782 | unsigned short inst; | |
4783 | int i; | |
4784 | ||
4785 | inst = mips_fetch_instruction (pc); | |
4786 | ||
4787 | /* Normally we ignore an extend instruction. However, if it is | |
4788 | not followed by a valid prologue instruction, we must adjust | |
4789 | the pc back over the extend so that it won't be considered | |
4790 | part of the prologue. */ | |
4791 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
88658117 | 4792 | { |
6d82d43b AC |
4793 | extend_bytes = MIPS16_INSTLEN; |
4794 | continue; | |
88658117 | 4795 | } |
6d82d43b AC |
4796 | prev_extend_bytes = extend_bytes; |
4797 | extend_bytes = 0; | |
4798 | ||
4799 | /* Check for other valid prologue instructions besides extend. */ | |
4800 | for (i = 0; table[i].mask != 0; i++) | |
4801 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4802 | break; | |
4803 | if (table[i].mask != 0) /* it was in table? */ | |
4804 | continue; /* ignore it */ | |
4805 | else | |
4806 | /* non-prologue */ | |
88658117 | 4807 | { |
6d82d43b AC |
4808 | /* Return the current pc, adjusted backwards by 2 if |
4809 | the previous instruction was an extend. */ | |
4810 | return pc - prev_extend_bytes; | |
88658117 AC |
4811 | } |
4812 | } | |
6d82d43b AC |
4813 | return pc; |
4814 | } | |
4815 | ||
4816 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4817 | if the code at PC does not look like a function prologue; otherwise | |
4818 | returns an address that (if we're lucky) follows the prologue. If | |
4819 | LENIENT, then we must skip everything which is involved in setting | |
4820 | up the frame (it's OK to skip more, just so long as we don't skip | |
4821 | anything which might clobber the registers which are being saved. | |
4822 | We must skip more in the case where part of the prologue is in the | |
4823 | delay slot of a non-prologue instruction). */ | |
4824 | ||
4825 | static CORE_ADDR | |
4826 | mips_skip_prologue (CORE_ADDR pc) | |
4827 | { | |
4828 | /* See if we can determine the end of the prologue via the symbol table. | |
4829 | If so, then return either PC, or the PC after the prologue, whichever | |
4830 | is greater. */ | |
4831 | ||
4832 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4833 | ||
4834 | if (post_prologue_pc != 0) | |
4835 | return max (pc, post_prologue_pc); | |
4836 | ||
4837 | /* Can't determine prologue from the symbol table, need to examine | |
4838 | instructions. */ | |
4839 | ||
4840 | if (pc_is_mips16 (pc)) | |
4841 | return mips16_skip_prologue (pc); | |
4842 | else | |
4843 | return mips32_skip_prologue (pc); | |
88658117 AC |
4844 | } |
4845 | ||
c906108c SS |
4846 | /* Exported procedure: Is PC in the signal trampoline code */ |
4847 | ||
102182a9 MS |
4848 | static int |
4849 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
4850 | { |
4851 | if (sigtramp_address == 0) | |
4852 | fixup_sigtramp (); | |
4853 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
4854 | } | |
4855 | ||
a5ea2558 AC |
4856 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4857 | used for all MIPS-specific commands. */ | |
4858 | ||
a5ea2558 | 4859 | static void |
acdb74a0 | 4860 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4861 | { |
4862 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4863 | } | |
4864 | ||
a5ea2558 | 4865 | static void |
acdb74a0 | 4866 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4867 | { |
6d82d43b AC |
4868 | printf_unfiltered |
4869 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4870 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4871 | } | |
4872 | ||
c906108c SS |
4873 | /* Commands to show/set the MIPS FPU type. */ |
4874 | ||
c906108c | 4875 | static void |
acdb74a0 | 4876 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4877 | { |
c906108c SS |
4878 | char *fpu; |
4879 | switch (MIPS_FPU_TYPE) | |
4880 | { | |
4881 | case MIPS_FPU_SINGLE: | |
4882 | fpu = "single-precision"; | |
4883 | break; | |
4884 | case MIPS_FPU_DOUBLE: | |
4885 | fpu = "double-precision"; | |
4886 | break; | |
4887 | case MIPS_FPU_NONE: | |
4888 | fpu = "absent (none)"; | |
4889 | break; | |
93d56215 AC |
4890 | default: |
4891 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4892 | } |
4893 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4894 | printf_unfiltered |
4895 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4896 | fpu); | |
c906108c | 4897 | else |
6d82d43b AC |
4898 | printf_unfiltered |
4899 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4900 | } |
4901 | ||
4902 | ||
c906108c | 4903 | static void |
acdb74a0 | 4904 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4905 | { |
6d82d43b AC |
4906 | printf_unfiltered |
4907 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4908 | show_mipsfpu_command (args, from_tty); |
4909 | } | |
4910 | ||
c906108c | 4911 | static void |
acdb74a0 | 4912 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4913 | { |
8d5838b5 AC |
4914 | struct gdbarch_info info; |
4915 | gdbarch_info_init (&info); | |
c906108c SS |
4916 | mips_fpu_type = MIPS_FPU_SINGLE; |
4917 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4918 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4919 | instead of relying on globals. Doing that would let generic code | |
4920 | handle the search for this specific architecture. */ | |
4921 | if (!gdbarch_update_p (info)) | |
4922 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4923 | } |
4924 | ||
c906108c | 4925 | static void |
acdb74a0 | 4926 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4927 | { |
8d5838b5 AC |
4928 | struct gdbarch_info info; |
4929 | gdbarch_info_init (&info); | |
c906108c SS |
4930 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4931 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4932 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4933 | instead of relying on globals. Doing that would let generic code | |
4934 | handle the search for this specific architecture. */ | |
4935 | if (!gdbarch_update_p (info)) | |
4936 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4937 | } |
4938 | ||
c906108c | 4939 | static void |
acdb74a0 | 4940 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4941 | { |
8d5838b5 AC |
4942 | struct gdbarch_info info; |
4943 | gdbarch_info_init (&info); | |
c906108c SS |
4944 | mips_fpu_type = MIPS_FPU_NONE; |
4945 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4946 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4947 | instead of relying on globals. Doing that would let generic code | |
4948 | handle the search for this specific architecture. */ | |
4949 | if (!gdbarch_update_p (info)) | |
4950 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4951 | } |
4952 | ||
c906108c | 4953 | static void |
acdb74a0 | 4954 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4955 | { |
4956 | mips_fpu_type_auto = 1; | |
4957 | } | |
4958 | ||
c906108c | 4959 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4960 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4961 | the relevant processor still exists (it dates back to '94) and | |
4962 | secondly this is not the way to do this. The processor type should | |
4963 | be set by forcing an architecture change. */ | |
c906108c | 4964 | |
691c0433 AC |
4965 | void |
4966 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4967 | { |
691c0433 | 4968 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4969 | CORE_ADDR prid; |
4970 | ||
4971 | prid = read_register (PRID_REGNUM); | |
4972 | ||
4973 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 4974 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4975 | } |
4976 | ||
4977 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4978 | callable as an sfunc. */ | |
4979 | ||
4980 | static void | |
acdb74a0 AC |
4981 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4982 | struct cmd_list_element *c) | |
c906108c SS |
4983 | { |
4984 | reinit_frame_cache (); | |
4985 | } | |
4986 | ||
a89aa300 AC |
4987 | static int |
4988 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4989 | { |
e5ab0dce | 4990 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4991 | mips_extra_func_info_t proc_desc; |
4992 | ||
4993 | /* Search for the function containing this address. Set the low bit | |
4994 | of the address when searching, in case we were given an even address | |
4995 | that is the start of a 16-bit function. If we didn't do this, | |
4996 | the search would fail because the symbol table says the function | |
4997 | starts at an odd address, i.e. 1 byte past the given address. */ | |
4998 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 4999 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5000 | |
5001 | /* Make an attempt to determine if this is a 16-bit function. If | |
5002 | the procedure descriptor exists and the address therein is odd, | |
5003 | it's definitely a 16-bit function. Otherwise, we have to just | |
5004 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5005 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5006 | disassembler needs to be able to locally determine the ISA, and | |
5007 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5008 | work. */ | |
c906108c | 5009 | if (proc_desc) |
d31431ed AC |
5010 | { |
5011 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
6d82d43b | 5012 | info->mach = bfd_mach_mips16; |
d31431ed | 5013 | } |
c906108c | 5014 | else |
d31431ed AC |
5015 | { |
5016 | if (pc_is_mips16 (memaddr)) | |
6d82d43b AC |
5017 | info->mach = bfd_mach_mips16; |
5018 | } | |
c906108c SS |
5019 | |
5020 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5021 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5022 | |
e5ab0dce | 5023 | /* Set the disassembler options. */ |
6d82d43b | 5024 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
5025 | { |
5026 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 5027 | register names from libopcodes. */ |
e5ab0dce AC |
5028 | if (tdep->mips_abi == MIPS_ABI_N32) |
5029 | info->disassembler_options = "gpr-names=n32"; | |
5030 | else | |
5031 | info->disassembler_options = "gpr-names=64"; | |
5032 | info->flavour = bfd_target_elf_flavour; | |
5033 | } | |
5034 | else | |
5035 | /* This string is not recognized explicitly by the disassembler, | |
5036 | but it tells the disassembler to not try to guess the ABI from | |
5037 | the bfd elf headers, such that, if the user overrides the ABI | |
5038 | of a program linked as NewABI, the disassembly will follow the | |
5039 | register naming conventions specified by the user. */ | |
5040 | info->disassembler_options = "gpr-names=32"; | |
5041 | ||
c906108c | 5042 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5043 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5044 | return print_insn_big_mips (memaddr, info); |
5045 | else | |
5046 | return print_insn_little_mips (memaddr, info); | |
5047 | } | |
5048 | ||
c906108c SS |
5049 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5050 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5051 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5052 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5053 | (if necessary) to point to the actual memory location where the | |
5054 | breakpoint should be inserted. */ | |
5055 | ||
f7ab6ec6 | 5056 | static const unsigned char * |
6d82d43b | 5057 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5058 | { |
d7449b42 | 5059 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5060 | { |
5061 | if (pc_is_mips16 (*pcptr)) | |
5062 | { | |
6d82d43b | 5063 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5064 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5065 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5066 | return mips16_big_breakpoint; |
5067 | } | |
5068 | else | |
5069 | { | |
aaab4dba AC |
5070 | /* The IDT board uses an unusual breakpoint value, and |
5071 | sometimes gets confused when it sees the usual MIPS | |
5072 | breakpoint instruction. */ | |
6d82d43b AC |
5073 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5074 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5075 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5076 | |
c5aa993b | 5077 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5078 | |
5079 | if (strcmp (target_shortname, "mips") == 0) | |
5080 | return idt_big_breakpoint; | |
5081 | else if (strcmp (target_shortname, "ddb") == 0 | |
5082 | || strcmp (target_shortname, "pmon") == 0 | |
5083 | || strcmp (target_shortname, "lsi") == 0) | |
5084 | return pmon_big_breakpoint; | |
5085 | else | |
5086 | return big_breakpoint; | |
5087 | } | |
5088 | } | |
5089 | else | |
5090 | { | |
5091 | if (pc_is_mips16 (*pcptr)) | |
5092 | { | |
6d82d43b | 5093 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5094 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5095 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5096 | return mips16_little_breakpoint; |
5097 | } | |
5098 | else | |
5099 | { | |
6d82d43b AC |
5100 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5101 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5102 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5103 | |
c5aa993b | 5104 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5105 | |
5106 | if (strcmp (target_shortname, "mips") == 0) | |
5107 | return idt_little_breakpoint; | |
5108 | else if (strcmp (target_shortname, "ddb") == 0 | |
5109 | || strcmp (target_shortname, "pmon") == 0 | |
5110 | || strcmp (target_shortname, "lsi") == 0) | |
5111 | return pmon_little_breakpoint; | |
5112 | else | |
5113 | return little_breakpoint; | |
5114 | } | |
5115 | } | |
5116 | } | |
5117 | ||
5118 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5119 | PC, which is either the callee or the caller. There are several | |
5120 | cases which must be handled: | |
5121 | ||
5122 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5123 | target PC is in $31 ($ra). |
c906108c | 5124 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5125 | and the target PC is in $2. |
c906108c | 5126 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5127 | before the jal instruction, this is effectively a call stub |
5128 | and the the target PC is in $2. Otherwise this is effectively | |
5129 | a return stub and the target PC is in $18. | |
c906108c SS |
5130 | |
5131 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5132 | gory details. | |
5133 | ||
5134 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5135 | */ |
c906108c | 5136 | |
757a7cc6 | 5137 | static CORE_ADDR |
acdb74a0 | 5138 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5139 | { |
5140 | char *name; | |
5141 | CORE_ADDR start_addr; | |
5142 | ||
5143 | /* Find the starting address and name of the function containing the PC. */ | |
5144 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5145 | return 0; | |
5146 | ||
5147 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5148 | target PC is in $31 ($ra). */ | |
5149 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5150 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5151 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5152 | |
5153 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5154 | { | |
5155 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5156 | and the target PC is in $2. */ | |
5157 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5158 | return read_signed_register (2); |
c906108c SS |
5159 | |
5160 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5161 | before the jal instruction, this is effectively a call stub |
5162 | and the the target PC is in $2. Otherwise this is effectively | |
5163 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5164 | else if (name[19] == 's' || name[19] == 'd') |
5165 | { | |
5166 | if (pc == start_addr) | |
5167 | { | |
5168 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5169 | stub. Such a stub for a function bar might have a name |
5170 | like __fn_stub_bar, and might look like this: | |
5171 | mfc1 $4,$f13 | |
5172 | mfc1 $5,$f12 | |
5173 | mfc1 $6,$f15 | |
5174 | mfc1 $7,$f14 | |
5175 | la $1,bar (becomes a lui/addiu pair) | |
5176 | jr $1 | |
5177 | So scan down to the lui/addi and extract the target | |
5178 | address from those two instructions. */ | |
c906108c | 5179 | |
6c997a34 | 5180 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5181 | t_inst inst; |
5182 | int i; | |
5183 | ||
5184 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5185 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5186 | 0) | |
c906108c SS |
5187 | return target_pc; |
5188 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5189 | && strcmp (name, "etext") != 0 | |
5190 | && strcmp (name, "_etext") != 0) | |
5191 | return target_pc; | |
5192 | ||
5193 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5194 | The limit on the search is arbitrarily set to 20 |
5195 | instructions. FIXME. */ | |
c906108c SS |
5196 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5197 | { | |
c5aa993b JM |
5198 | inst = mips_fetch_instruction (target_pc); |
5199 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5200 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5201 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5202 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5203 | } |
5204 | ||
5205 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5206 | return target_pc; | |
5207 | } | |
5208 | else | |
5209 | /* This is the 'return' part of a call stub. The return | |
5210 | address is in $r18. */ | |
6c997a34 | 5211 | return read_signed_register (18); |
c906108c SS |
5212 | } |
5213 | } | |
c5aa993b | 5214 | return 0; /* not a stub */ |
c906108c SS |
5215 | } |
5216 | ||
5217 | ||
5218 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5219 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5220 | ||
757a7cc6 | 5221 | static int |
acdb74a0 | 5222 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5223 | { |
5224 | CORE_ADDR start_addr; | |
5225 | ||
5226 | /* Find the starting address of the function containing the PC. If the | |
5227 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
5228 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
5229 | 0) | |
c906108c SS |
5230 | return 0; |
5231 | ||
5232 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5233 | { | |
5234 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5235 | if (name[19] >= '0' && name[19] <= '9') | |
5236 | return 1; | |
5237 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5238 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5239 | else if (name[19] == 's' || name[19] == 'd') |
5240 | return pc == start_addr; | |
5241 | } | |
5242 | ||
c5aa993b | 5243 | return 0; /* not a stub */ |
c906108c SS |
5244 | } |
5245 | ||
5246 | ||
5247 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5248 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5249 | ||
e41b17f0 | 5250 | static int |
acdb74a0 | 5251 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5252 | { |
5253 | CORE_ADDR start_addr; | |
5254 | ||
5255 | /* Find the starting address of the function containing the PC. */ | |
5256 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5257 | return 0; | |
5258 | ||
5259 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5260 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5261 | || strcmp (name, "__mips16_ret_df") == 0) | |
5262 | return 1; | |
5263 | ||
5264 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5265 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 5266 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 5267 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
5268 | return 1; |
5269 | ||
c5aa993b | 5270 | return 0; /* not a stub */ |
c906108c SS |
5271 | } |
5272 | ||
5273 | ||
5274 | /* Return non-zero if the PC is in a library helper function that should | |
5275 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5276 | ||
5277 | int | |
acdb74a0 | 5278 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5279 | { |
5280 | char *name; | |
5281 | ||
5282 | /* Find the starting address and name of the function containing the PC. */ | |
5283 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5284 | return 0; | |
5285 | ||
5286 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5287 | that we want to ignore. */ | |
5288 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5289 | || strcmp (name, "__mips16_ret_df") == 0); | |
5290 | } | |
5291 | ||
5292 | ||
a4b8ebc8 AC |
5293 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5294 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5295 | |
5296 | static int | |
5297 | mips_stab_reg_to_regnum (int num) | |
5298 | { | |
a4b8ebc8 | 5299 | int regnum; |
2f38ef89 | 5300 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5301 | regnum = num; |
2f38ef89 | 5302 | else if (num >= 38 && num < 70) |
56cea623 | 5303 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5304 | else if (num == 70) |
56cea623 | 5305 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5306 | else if (num == 71) |
56cea623 | 5307 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5308 | else |
a4b8ebc8 AC |
5309 | /* This will hopefully (eventually) provoke a warning. Should |
5310 | we be calling complaint() here? */ | |
5311 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5312 | return NUM_REGS + regnum; | |
88c72b7d AC |
5313 | } |
5314 | ||
2f38ef89 | 5315 | |
a4b8ebc8 AC |
5316 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5317 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5318 | |
5319 | static int | |
2f38ef89 | 5320 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5321 | { |
a4b8ebc8 | 5322 | int regnum; |
2f38ef89 | 5323 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5324 | regnum = num; |
2f38ef89 | 5325 | else if (num >= 32 && num < 64) |
56cea623 | 5326 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5327 | else if (num == 64) |
56cea623 | 5328 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5329 | else if (num == 65) |
56cea623 | 5330 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5331 | else |
a4b8ebc8 AC |
5332 | /* This will hopefully (eventually) provoke a warning. Should we |
5333 | be calling complaint() here? */ | |
5334 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5335 | return NUM_REGS + regnum; | |
5336 | } | |
5337 | ||
5338 | static int | |
5339 | mips_register_sim_regno (int regnum) | |
5340 | { | |
5341 | /* Only makes sense to supply raw registers. */ | |
5342 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5343 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5344 | decide if it is valid. Should instead define a standard sim/gdb | |
5345 | register numbering scheme. */ | |
5346 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5347 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5348 | return regnum; | |
5349 | else | |
6d82d43b | 5350 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5351 | } |
5352 | ||
2f38ef89 | 5353 | |
fc0c74b1 AC |
5354 | /* Convert an integer into an address. By first converting the value |
5355 | into a pointer and then extracting it signed, the address is | |
5356 | guarenteed to be correctly sign extended. */ | |
5357 | ||
5358 | static CORE_ADDR | |
5359 | mips_integer_to_address (struct type *type, void *buf) | |
5360 | { | |
5361 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5362 | LONGEST val = unpack_long (type, buf); | |
5363 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5364 | return extract_signed_integer (tmp, | |
5365 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5366 | } | |
5367 | ||
caaa3122 DJ |
5368 | static void |
5369 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5370 | { | |
5371 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5372 | const char *name = bfd_get_section_name (abfd, sect); | |
5373 | ||
5374 | if (*abip != MIPS_ABI_UNKNOWN) | |
5375 | return; | |
5376 | ||
5377 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5378 | return; | |
5379 | ||
5380 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5381 | *abip = MIPS_ABI_O32; | |
5382 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5383 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5384 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5385 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5386 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5387 | *abip = MIPS_ABI_O64; | |
5388 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5389 | *abip = MIPS_ABI_EABI32; | |
5390 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5391 | *abip = MIPS_ABI_EABI64; | |
5392 | else | |
5393 | warning ("unsupported ABI %s.", name + 8); | |
5394 | } | |
5395 | ||
2e4ebe70 DJ |
5396 | static enum mips_abi |
5397 | global_mips_abi (void) | |
5398 | { | |
5399 | int i; | |
5400 | ||
5401 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5402 | if (mips_abi_strings[i] == mips_abi_string) | |
5403 | return (enum mips_abi) i; | |
5404 | ||
6d82d43b | 5405 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
5406 | } |
5407 | ||
c2d11a7d | 5408 | static struct gdbarch * |
6d82d43b | 5409 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5410 | { |
c2d11a7d JM |
5411 | struct gdbarch *gdbarch; |
5412 | struct gdbarch_tdep *tdep; | |
5413 | int elf_flags; | |
2e4ebe70 | 5414 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5415 | int num_regs; |
8d5838b5 | 5416 | enum mips_fpu_type fpu_type; |
c2d11a7d | 5417 | |
ec03c1ac AC |
5418 | /* First of all, extract the elf_flags, if available. */ |
5419 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5420 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5421 | else if (arches != NULL) |
5422 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5423 | else |
5424 | elf_flags = 0; | |
5425 | if (gdbarch_debug) | |
5426 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5427 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5428 | |
102182a9 | 5429 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5430 | switch ((elf_flags & EF_MIPS_ABI)) |
5431 | { | |
5432 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5433 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5434 | break; |
5435 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5436 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5437 | break; |
5438 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5439 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5440 | break; |
5441 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5442 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5443 | break; |
5444 | default: | |
acdb74a0 | 5445 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5446 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5447 | else |
ec03c1ac | 5448 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5449 | break; |
5450 | } | |
acdb74a0 | 5451 | |
caaa3122 | 5452 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5453 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5454 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5455 | |
ec03c1ac AC |
5456 | /* If we have no usefu BFD information, use the ABI from the last |
5457 | MIPS architecture (if there is one). */ | |
5458 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5459 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5460 | |
32a6503c | 5461 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5462 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5463 | && info.bfd_arch_info != NULL |
5464 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5465 | { | |
5466 | switch (info.bfd_arch_info->mach) | |
5467 | { | |
5468 | case bfd_mach_mips3900: | |
ec03c1ac | 5469 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5470 | break; |
5471 | case bfd_mach_mips4100: | |
5472 | case bfd_mach_mips5000: | |
ec03c1ac | 5473 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5474 | break; |
1d06468c EZ |
5475 | case bfd_mach_mips8000: |
5476 | case bfd_mach_mips10000: | |
32a6503c KB |
5477 | /* On Irix, ELF64 executables use the N64 ABI. The |
5478 | pseudo-sections which describe the ABI aren't present | |
5479 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5480 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5481 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5482 | found_abi = MIPS_ABI_N64; |
28d169de | 5483 | else |
ec03c1ac | 5484 | found_abi = MIPS_ABI_N32; |
1d06468c | 5485 | break; |
bf64bfd6 AC |
5486 | } |
5487 | } | |
2e4ebe70 | 5488 | |
ec03c1ac AC |
5489 | if (gdbarch_debug) |
5490 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5491 | found_abi); | |
5492 | ||
5493 | /* What has the user specified from the command line? */ | |
5494 | wanted_abi = global_mips_abi (); | |
5495 | if (gdbarch_debug) | |
5496 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5497 | wanted_abi); | |
2e4ebe70 DJ |
5498 | |
5499 | /* Now that we have found what the ABI for this binary would be, | |
5500 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5501 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5502 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5503 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5504 | mips_abi = found_abi; | |
5505 | else | |
5506 | mips_abi = MIPS_ABI_O32; | |
5507 | if (gdbarch_debug) | |
5508 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5509 | mips_abi); | |
2e4ebe70 | 5510 | |
ec03c1ac | 5511 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5512 | if (gdbarch_debug) |
ec03c1ac AC |
5513 | fprintf_unfiltered (gdb_stdlog, |
5514 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5515 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5516 | |
8d5838b5 AC |
5517 | /* Determine the MIPS FPU type. */ |
5518 | if (!mips_fpu_type_auto) | |
5519 | fpu_type = mips_fpu_type; | |
5520 | else if (info.bfd_arch_info != NULL | |
5521 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5522 | switch (info.bfd_arch_info->mach) | |
5523 | { | |
5524 | case bfd_mach_mips3900: | |
5525 | case bfd_mach_mips4100: | |
5526 | case bfd_mach_mips4111: | |
5527 | fpu_type = MIPS_FPU_NONE; | |
5528 | break; | |
5529 | case bfd_mach_mips4650: | |
5530 | fpu_type = MIPS_FPU_SINGLE; | |
5531 | break; | |
5532 | default: | |
5533 | fpu_type = MIPS_FPU_DOUBLE; | |
5534 | break; | |
5535 | } | |
5536 | else if (arches != NULL) | |
5537 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5538 | else | |
5539 | fpu_type = MIPS_FPU_DOUBLE; | |
5540 | if (gdbarch_debug) | |
5541 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5542 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5543 | |
c2d11a7d JM |
5544 | /* try to find a pre-existing architecture */ |
5545 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5546 | arches != NULL; | |
5547 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5548 | { | |
5549 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5550 | using. */ |
9103eae0 | 5551 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5552 | continue; |
9103eae0 | 5553 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5554 | continue; |
719ec221 AC |
5555 | /* Need to be pedantic about which register virtual size is |
5556 | used. */ | |
5557 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5558 | != mips64_transfers_32bit_regs_p) | |
5559 | continue; | |
8d5838b5 AC |
5560 | /* Be pedantic about which FPU is selected. */ |
5561 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5562 | continue; | |
4be87837 | 5563 | return arches->gdbarch; |
c2d11a7d JM |
5564 | } |
5565 | ||
102182a9 | 5566 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5567 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5568 | gdbarch = gdbarch_alloc (&info, tdep); | |
5569 | tdep->elf_flags = elf_flags; | |
719ec221 | 5570 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5571 | tdep->found_abi = found_abi; |
5572 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5573 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 5574 | |
102182a9 | 5575 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5576 | set_gdbarch_short_bit (gdbarch, 16); |
5577 | set_gdbarch_int_bit (gdbarch, 32); | |
5578 | set_gdbarch_float_bit (gdbarch, 32); | |
5579 | set_gdbarch_double_bit (gdbarch, 64); | |
5580 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5581 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5582 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5583 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5584 | |
6d82d43b | 5585 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5586 | mips_elf_make_msymbol_special); |
5587 | ||
16e109ca | 5588 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5589 | { |
16e109ca | 5590 | const char **reg_names; |
56cea623 AC |
5591 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5592 | struct mips_regnum); | |
56cea623 AC |
5593 | if (info.osabi == GDB_OSABI_IRIX) |
5594 | { | |
5595 | regnum->fp0 = 32; | |
5596 | regnum->pc = 64; | |
5597 | regnum->cause = 65; | |
5598 | regnum->badvaddr = 66; | |
5599 | regnum->hi = 67; | |
5600 | regnum->lo = 68; | |
5601 | regnum->fp_control_status = 69; | |
5602 | regnum->fp_implementation_revision = 70; | |
5603 | num_regs = 71; | |
16e109ca | 5604 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5605 | } |
5606 | else | |
5607 | { | |
5608 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5609 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5610 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5611 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5612 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5613 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5614 | regnum->fp_control_status = 70; | |
5615 | regnum->fp_implementation_revision = 71; | |
5616 | num_regs = 90; | |
16e109ca AC |
5617 | if (info.bfd_arch_info != NULL |
5618 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5619 | reg_names = mips_tx39_reg_names; | |
5620 | else | |
5621 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5622 | } |
5623 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5624 | replaced by read_pc? */ | |
5625 | set_gdbarch_pc_regnum (gdbarch, regnum->pc); | |
5626 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); | |
5627 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5628 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5629 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5630 | tdep->mips_processor_reg_names = reg_names; | |
5631 | tdep->regnum = regnum; | |
56cea623 | 5632 | } |
fe29b929 | 5633 | |
0dadbba0 | 5634 | switch (mips_abi) |
c2d11a7d | 5635 | { |
0dadbba0 | 5636 | case MIPS_ABI_O32: |
25ab4790 | 5637 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5638 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
a5ea2558 | 5639 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5640 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5641 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5642 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5643 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5644 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5645 | set_gdbarch_long_bit (gdbarch, 32); |
5646 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5647 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5648 | break; | |
0dadbba0 | 5649 | case MIPS_ABI_O64: |
25ab4790 | 5650 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
6d82d43b AC |
5651 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5652 | mips_o64_store_return_value); | |
5653 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5654 | mips_o64_extract_return_value); | |
a5ea2558 | 5655 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5656 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5657 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5658 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5659 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5660 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5661 | set_gdbarch_long_bit (gdbarch, 32); |
5662 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5663 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6d82d43b AC |
5664 | set_gdbarch_use_struct_convention (gdbarch, |
5665 | always_use_struct_convention); | |
c2d11a7d | 5666 | break; |
0dadbba0 | 5667 | case MIPS_ABI_EABI32: |
25ab4790 | 5668 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
5669 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5670 | mips_eabi_store_return_value); | |
5671 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5672 | mips_eabi_extract_return_value); | |
a5ea2558 | 5673 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5674 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5675 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5676 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5677 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5678 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5679 | set_gdbarch_long_bit (gdbarch, 32); |
5680 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5681 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5682 | set_gdbarch_deprecated_reg_struct_has_addr |
5683 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
6d82d43b | 5684 | set_gdbarch_use_struct_convention (gdbarch, |
cb811fe7 | 5685 | mips_eabi_use_struct_convention); |
c2d11a7d | 5686 | break; |
0dadbba0 | 5687 | case MIPS_ABI_EABI64: |
25ab4790 | 5688 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
5689 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5690 | mips_eabi_store_return_value); | |
5691 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5692 | mips_eabi_extract_return_value); | |
a5ea2558 | 5693 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5694 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5695 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5696 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5697 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5698 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5699 | set_gdbarch_long_bit (gdbarch, 64); |
5700 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5701 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5702 | set_gdbarch_deprecated_reg_struct_has_addr |
5703 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
6d82d43b | 5704 | set_gdbarch_use_struct_convention (gdbarch, |
cb811fe7 | 5705 | mips_eabi_use_struct_convention); |
c2d11a7d | 5706 | break; |
0dadbba0 | 5707 | case MIPS_ABI_N32: |
25ab4790 | 5708 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5709 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
63db5580 | 5710 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5711 | tdep->mips_default_stack_argsize = 8; |
5712 | tdep->mips_fp_register_double = 1; | |
acdb74a0 | 5713 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5714 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5715 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5716 | set_gdbarch_long_bit (gdbarch, 32); |
5717 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5718 | set_gdbarch_long_long_bit (gdbarch, 64); | |
28d169de KB |
5719 | break; |
5720 | case MIPS_ABI_N64: | |
25ab4790 | 5721 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5722 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de KB |
5723 | tdep->mips_default_saved_regsize = 8; |
5724 | tdep->mips_default_stack_argsize = 8; | |
5725 | tdep->mips_fp_register_double = 1; | |
5726 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
56cea623 | 5727 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5728 | tdep->default_mask_address_p = 0; |
5729 | set_gdbarch_long_bit (gdbarch, 64); | |
5730 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5731 | set_gdbarch_long_long_bit (gdbarch, 64); | |
0dadbba0 | 5732 | break; |
c2d11a7d | 5733 | default: |
6d82d43b | 5734 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
5735 | } |
5736 | ||
a5ea2558 AC |
5737 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5738 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5739 | comment: | |
5740 | ||
5741 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5742 | flag in object files because to do so would make it impossible to | |
102182a9 | 5743 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5744 | unnecessarily restrictive. |
361d1df0 | 5745 | |
a5ea2558 AC |
5746 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5747 | but to set this flag before gcc is built with such multilibs will | |
5748 | break too many systems.'' | |
5749 | ||
5750 | But even more unhelpfully, the default linker output target for | |
5751 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5752 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5753 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5754 | this flag to detect 32-bit mode would do the wrong thing given |
5755 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5756 | as 32-bit programs by default. */ |
a5ea2558 | 5757 | |
6c997a34 | 5758 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5759 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 5760 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5761 | |
102182a9 MS |
5762 | /* Add/remove bits from an address. The MIPS needs be careful to |
5763 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5764 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5765 | ||
58dfe9ff AC |
5766 | /* Unwind the frame. */ |
5767 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 AC |
5768 | frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer); |
5769 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); | |
5770 | frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer); | |
10312cc4 | 5771 | |
102182a9 | 5772 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5773 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5774 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5775 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5776 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5777 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5778 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5779 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5780 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5781 | |
c2d11a7d JM |
5782 | /* MIPS version of CALL_DUMMY */ |
5783 | ||
9710e734 AC |
5784 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5785 | replaced by a command, and all targets will default to on stack | |
5786 | (regardless of the stack's execute status). */ | |
5787 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5788 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5789 | |
87783b8b AC |
5790 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5791 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5792 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5793 | ||
f7b9e9fc AC |
5794 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5795 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5796 | |
5797 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5798 | |
fc0c74b1 AC |
5799 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5800 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5801 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5802 | |
a4b8ebc8 | 5803 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5804 | |
e11c53d2 | 5805 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 5806 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 5807 | |
e5ab0dce AC |
5808 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5809 | ||
3a3bc038 AC |
5810 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5811 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5812 | need to all be folded into the target vector. Since they are | |
5813 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5814 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5815 | is sitting on? */ | |
5816 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5817 | ||
757a7cc6 MS |
5818 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); |
5819 | ||
6de918a6 DJ |
5820 | /* NOTE drow/2004-02-11: We overload the core solib trampoline code |
5821 | to support MIPS16. This is a bad thing. Make sure not to do it | |
5822 | if we have an OS ABI that actually supports shared libraries, since | |
5823 | shared library support is more important. If we have an OS someday | |
5824 | that supports both shared libraries and MIPS16, we'll have to find | |
5825 | a better place for these. */ | |
5826 | if (info.osabi == GDB_OSABI_UNKNOWN) | |
5827 | { | |
5828 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
5829 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
5830 | } | |
5831 | ||
5832 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
5833 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 5834 | |
4b9b3959 AC |
5835 | return gdbarch; |
5836 | } | |
5837 | ||
2e4ebe70 | 5838 | static void |
6d82d43b | 5839 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5840 | { |
5841 | struct gdbarch_info info; | |
5842 | ||
5843 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5844 | mips_gdbarch_init will take care of the rest. */ | |
5845 | gdbarch_info_init (&info); | |
5846 | gdbarch_update_p (info); | |
5847 | } | |
5848 | ||
ad188201 KB |
5849 | /* Print out which MIPS ABI is in use. */ |
5850 | ||
5851 | static void | |
5852 | show_mips_abi (char *ignore_args, int from_tty) | |
5853 | { | |
5854 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
5855 | printf_filtered |
5856 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
5857 | else |
5858 | { | |
5859 | enum mips_abi global_abi = global_mips_abi (); | |
5860 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5861 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5862 | ||
5863 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
5864 | printf_filtered |
5865 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
5866 | actual_abi_str); | |
ad188201 | 5867 | else if (global_abi == actual_abi) |
6d82d43b AC |
5868 | printf_filtered |
5869 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
5870 | actual_abi_str); | |
ad188201 KB |
5871 | else |
5872 | { | |
5873 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
5874 | printf_filtered |
5875 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
5876 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
5877 | } |
5878 | } | |
5879 | } | |
5880 | ||
4b9b3959 AC |
5881 | static void |
5882 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5883 | { | |
5884 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5885 | if (tdep != NULL) | |
c2d11a7d | 5886 | { |
acdb74a0 AC |
5887 | int ef_mips_arch; |
5888 | int ef_mips_32bitmode; | |
5889 | /* determine the ISA */ | |
5890 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
5891 | { | |
5892 | case E_MIPS_ARCH_1: | |
5893 | ef_mips_arch = 1; | |
5894 | break; | |
5895 | case E_MIPS_ARCH_2: | |
5896 | ef_mips_arch = 2; | |
5897 | break; | |
5898 | case E_MIPS_ARCH_3: | |
5899 | ef_mips_arch = 3; | |
5900 | break; | |
5901 | case E_MIPS_ARCH_4: | |
93d56215 | 5902 | ef_mips_arch = 4; |
acdb74a0 AC |
5903 | break; |
5904 | default: | |
93d56215 | 5905 | ef_mips_arch = 0; |
acdb74a0 AC |
5906 | break; |
5907 | } | |
5908 | /* determine the size of a pointer */ | |
5909 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
5910 | fprintf_unfiltered (file, |
5911 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5912 | tdep->elf_flags); |
4b9b3959 | 5913 | fprintf_unfiltered (file, |
acdb74a0 AC |
5914 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5915 | ef_mips_32bitmode); | |
5916 | fprintf_unfiltered (file, | |
5917 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5918 | ef_mips_arch); | |
5919 | fprintf_unfiltered (file, | |
5920 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5921 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5922 | fprintf_unfiltered (file, |
5923 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5924 | mips_mask_address_p (tdep), |
4014092b | 5925 | tdep->default_mask_address_p); |
c2d11a7d | 5926 | } |
4b9b3959 AC |
5927 | fprintf_unfiltered (file, |
5928 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
5929 | FP_REGISTER_DOUBLE); | |
5930 | fprintf_unfiltered (file, | |
5931 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5932 | MIPS_DEFAULT_FPU_TYPE, | |
5933 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5934 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5935 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5936 | : "???")); | |
6d82d43b | 5937 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5938 | fprintf_unfiltered (file, |
5939 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5940 | MIPS_FPU_TYPE, | |
5941 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5942 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5943 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5944 | : "???")); | |
4b9b3959 AC |
5945 | fprintf_unfiltered (file, |
5946 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
5947 | FP_REGISTER_DOUBLE); | |
4b9b3959 | 5948 | fprintf_unfiltered (file, |
480d3dd2 AC |
5949 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
5950 | mips_stack_argsize (tdep)); | |
6d82d43b | 5951 | fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM); |
2475bac3 AC |
5952 | fprintf_unfiltered (file, |
5953 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 5954 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
5955 | fprintf_unfiltered (file, |
5956 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
5957 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
5958 | fprintf_unfiltered (file, |
5959 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
5960 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
5961 | fprintf_unfiltered (file, | |
5962 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
5963 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
5964 | fprintf_unfiltered (file, |
5965 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
5966 | FIRST_EMBED_REGNUM); | |
2475bac3 AC |
5967 | fprintf_unfiltered (file, |
5968 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
5969 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
5970 | fprintf_unfiltered (file, |
5971 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
5972 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
5973 | fprintf_unfiltered (file, | |
5974 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
5975 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
5976 | fprintf_unfiltered (file, |
5977 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
5978 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
5979 | #ifdef MACHINE_CPROC_FP_OFFSET |
5980 | fprintf_unfiltered (file, | |
5981 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
5982 | MACHINE_CPROC_FP_OFFSET); | |
5983 | #endif | |
5984 | #ifdef MACHINE_CPROC_PC_OFFSET | |
5985 | fprintf_unfiltered (file, | |
5986 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
5987 | MACHINE_CPROC_PC_OFFSET); | |
5988 | #endif | |
5989 | #ifdef MACHINE_CPROC_SP_OFFSET | |
5990 | fprintf_unfiltered (file, | |
5991 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
5992 | MACHINE_CPROC_SP_OFFSET); | |
5993 | #endif | |
2475bac3 AC |
5994 | fprintf_unfiltered (file, |
5995 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
5996 | MIPS16_INSTLEN); | |
6d82d43b | 5997 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
5998 | fprintf_unfiltered (file, |
5999 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6000 | fprintf_unfiltered (file, | |
6d82d43b | 6001 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN); |
2475bac3 | 6002 | fprintf_unfiltered (file, |
acdb74a0 AC |
6003 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6004 | MIPS_LAST_ARG_REGNUM, | |
6005 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 | 6006 | fprintf_unfiltered (file, |
6d82d43b | 6007 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 6008 | fprintf_unfiltered (file, |
480d3dd2 AC |
6009 | "mips_dump_tdep: mips_saved_regsize() = %d\n", |
6010 | mips_saved_regsize (tdep)); | |
2475bac3 | 6011 | fprintf_unfiltered (file, |
6d82d43b | 6012 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
6013 | fprintf_unfiltered (file, |
6014 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6015 | fprintf_unfiltered (file, | |
6016 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6017 | fprintf_unfiltered (file, | |
6018 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
6019 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
6020 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6021 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6022 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6023 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6024 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6025 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6026 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6027 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6028 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
6029 | fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM); | |
2475bac3 AC |
6030 | #ifdef SAVED_BYTES |
6031 | fprintf_unfiltered (file, | |
6d82d43b | 6032 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
6033 | #endif |
6034 | #ifdef SAVED_FP | |
6d82d43b | 6035 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
6036 | #endif |
6037 | #ifdef SAVED_PC | |
6d82d43b | 6038 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
6039 | #endif |
6040 | fprintf_unfiltered (file, | |
6041 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6042 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6043 | fprintf_unfiltered (file, | |
6044 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
2475bac3 AC |
6045 | fprintf_unfiltered (file, |
6046 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6047 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6048 | fprintf_unfiltered (file, | |
6049 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6050 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6051 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6052 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6053 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6054 | fprintf_unfiltered (file, |
6055 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6056 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6057 | #ifdef STACK_END_ADDR | |
6058 | fprintf_unfiltered (file, | |
6059 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6060 | STACK_END_ADDR); | |
6061 | #endif | |
6062 | fprintf_unfiltered (file, | |
6063 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6064 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6065 | fprintf_unfiltered (file, | |
6066 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6067 | STEP_SKIPS_DELAY_P); | |
6068 | fprintf_unfiltered (file, | |
6069 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6070 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6d82d43b | 6071 | fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM); |
2475bac3 AC |
6072 | fprintf_unfiltered (file, |
6073 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6074 | fprintf_unfiltered (file, | |
6075 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
6076 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
6077 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
6078 | fprintf_unfiltered (file, |
6079 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6080 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6081 | #ifdef TRACE_CLEAR |
6082 | fprintf_unfiltered (file, | |
6083 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6084 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6085 | #endif | |
6086 | #ifdef TRACE_FLAVOR | |
6087 | fprintf_unfiltered (file, | |
6d82d43b | 6088 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
6089 | #endif |
6090 | #ifdef TRACE_FLAVOR_SIZE | |
6091 | fprintf_unfiltered (file, | |
6092 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6093 | TRACE_FLAVOR_SIZE); | |
6094 | #endif | |
6095 | #ifdef TRACE_SET | |
6096 | fprintf_unfiltered (file, | |
6097 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 6098 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 6099 | #endif |
2475bac3 AC |
6100 | #ifdef UNUSED_REGNUM |
6101 | fprintf_unfiltered (file, | |
6d82d43b | 6102 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 6103 | #endif |
6d82d43b | 6104 | fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM); |
2475bac3 AC |
6105 | fprintf_unfiltered (file, |
6106 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6107 | (long) VM_MIN_ADDRESS); | |
2475bac3 | 6108 | fprintf_unfiltered (file, |
6d82d43b | 6109 | "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM); |
2475bac3 | 6110 | fprintf_unfiltered (file, |
6d82d43b | 6111 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_); |
c2d11a7d JM |
6112 | } |
6113 | ||
6d82d43b | 6114 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6115 | |
c906108c | 6116 | void |
acdb74a0 | 6117 | _initialize_mips_tdep (void) |
c906108c SS |
6118 | { |
6119 | static struct cmd_list_element *mipsfpulist = NULL; | |
6120 | struct cmd_list_element *c; | |
6121 | ||
6d82d43b | 6122 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6123 | if (MIPS_ABI_LAST + 1 |
6124 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6125 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6126 | ||
4b9b3959 | 6127 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6128 | |
a5ea2558 AC |
6129 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6130 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6131 | "Various MIPS specific commands.", | |
6132 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6133 | ||
6134 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6135 | "Various MIPS specific commands.", | |
6136 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6137 | ||
6138 | /* Allow the user to override the saved register size. */ | |
6139 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6140 | class_obscure, |
6141 | size_enums, | |
6142 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6143 | Set size of general purpose registers saved on the stack.\n\ |
6144 | This option can be set to one of:\n\ | |
6145 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6146 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6147 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6148 | saved GP register size from information contained in the executable.\n\ | |
6d82d43b | 6149 | (default: auto)", &setmipscmdlist), &showmipscmdlist); |
a5ea2558 | 6150 | |
d929b26f AC |
6151 | /* Allow the user to override the argument stack size. */ |
6152 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6153 | class_obscure, | |
6154 | size_enums, | |
1ed2a135 | 6155 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6156 | Set the amount of stack space reserved for each argument.\n\ |
6157 | This option can be set to one of:\n\ | |
6158 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6159 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6160 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6d82d43b | 6161 | target and executable (default)", &setmipscmdlist), &showmipscmdlist); |
d929b26f | 6162 | |
2e4ebe70 DJ |
6163 | /* Allow the user to override the ABI. */ |
6164 | c = add_set_enum_cmd | |
6165 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6166 | "Set the ABI used by this program.\n" | |
6167 | "This option can be set to one of:\n" | |
6168 | " auto - the default ABI associated with the current binary\n" | |
6169 | " o32\n" | |
6d82d43b | 6170 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 6171 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 6172 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 6173 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 6174 | |
c906108c SS |
6175 | /* Let the user turn off floating point and set the fence post for |
6176 | heuristic_proc_start. */ | |
6177 | ||
6178 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6179 | "Set use of MIPS floating-point coprocessor.", | |
6180 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6181 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6182 | "Select single-precision MIPS floating-point coprocessor.", | |
6183 | &mipsfpulist); | |
6184 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6185 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6186 | &mipsfpulist); |
6187 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6188 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6189 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6190 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 6191 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
6192 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6193 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6194 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6195 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6196 | "Select MIPS floating-point coprocessor automatically.", | |
6197 | &mipsfpulist); | |
6198 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6199 | "Show current use of MIPS floating-point coprocessor target.", | |
6200 | &showlist); | |
6201 | ||
c906108c SS |
6202 | /* We really would like to have both "0" and "unlimited" work, but |
6203 | command.c doesn't deal with that. So make it a var_zinteger | |
6204 | because the user can always use "999999" or some such for unlimited. */ | |
6205 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6d82d43b | 6206 | (char *) &heuristic_fence_post, "\ |
c906108c SS |
6207 | Set the distance searched for the start of a function.\n\ |
6208 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6209 | program for the start of a function. This command sets the distance of the\n\ | |
6d82d43b | 6210 | search. The only need to set it is when debugging a stripped executable.", &setlist); |
c906108c SS |
6211 | /* We need to throw away the frame cache when we set this, since it |
6212 | might change our ability to get backtraces. */ | |
9f60d481 | 6213 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6214 | add_show_from_set (c, &showlist); |
6215 | ||
6216 | /* Allow the user to control whether the upper bits of 64-bit | |
6217 | addresses should be zeroed. */ | |
e9e68a56 AC |
6218 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6219 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6220 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6221 | allow GDB to determine the correct value.\n", "\ | |
6222 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6d82d43b | 6223 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
6224 | |
6225 | /* Allow the user to control the size of 32 bit registers within the | |
6226 | raw remote packet. */ | |
719ec221 AC |
6227 | add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6228 | var_boolean, &mips64_transfers_32bit_regs_p, "\ | |
6229 | Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
6230 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6231 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6232 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
719ec221 | 6233 | Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ |
43e526b9 JM |
6234 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6235 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6236 | 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); |
9ace0497 AC |
6237 | |
6238 | /* Debug this files internals. */ | |
6239 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6240 | &mips_debug, "Set mips debugging.\n\ | |
6d82d43b | 6241 | When non-zero, mips specific debugging is enabled.", &setdebuglist), &showdebuglist); |
c906108c | 6242 | } |