Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "gdb_string.h" | |
5e2e9765 | 25 | #include "gdb_assert.h" |
c906108c SS |
26 | #include "frame.h" |
27 | #include "inferior.h" | |
28 | #include "symtab.h" | |
29 | #include "value.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "language.h" | |
32 | #include "gdbcore.h" | |
33 | #include "symfile.h" | |
34 | #include "objfiles.h" | |
35 | #include "gdbtypes.h" | |
36 | #include "target.h" | |
28d069e6 | 37 | #include "arch-utils.h" |
4e052eda | 38 | #include "regcache.h" |
70f80edf | 39 | #include "osabi.h" |
d1973055 | 40 | #include "mips-tdep.h" |
fe898f56 | 41 | #include "block.h" |
a4b8ebc8 | 42 | #include "reggroups.h" |
c906108c | 43 | #include "opcode/mips.h" |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
a4b8ebc8 | 47 | #include "sim-regno.h" |
a89aa300 | 48 | #include "dis-asm.h" |
edfae063 AC |
49 | #include "frame-unwind.h" |
50 | #include "frame-base.h" | |
51 | #include "trad-frame.h" | |
7d9b040b | 52 | #include "infcall.h" |
fed7ba43 | 53 | #include "floatformat.h" |
29709017 DJ |
54 | #include "remote.h" |
55 | #include "target-descriptions.h" | |
2bd0c3d7 | 56 | #include "dwarf2-frame.h" |
f8b73d13 | 57 | #include "user-regs.h" |
79a45b7d | 58 | #include "valprint.h" |
175ff332 | 59 | #include "ax.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
24e05951 | 65 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
66 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 | #define ST0_FR (1 << 26) | |
68 | ||
b0069a17 AC |
69 | /* The sizes of floating point registers. */ |
70 | ||
71 | enum | |
72 | { | |
73 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
74 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
75 | }; | |
76 | ||
1a69e1e4 DJ |
77 | enum |
78 | { | |
79 | MIPS32_REGSIZE = 4, | |
80 | MIPS64_REGSIZE = 8 | |
81 | }; | |
0dadbba0 | 82 | |
2e4ebe70 DJ |
83 | static const char *mips_abi_string; |
84 | ||
85 | static const char *mips_abi_strings[] = { | |
86 | "auto", | |
87 | "n32", | |
88 | "o32", | |
28d169de | 89 | "n64", |
2e4ebe70 DJ |
90 | "o64", |
91 | "eabi32", | |
92 | "eabi64", | |
93 | NULL | |
94 | }; | |
95 | ||
f8b73d13 DJ |
96 | /* The standard register names, and all the valid aliases for them. */ |
97 | struct register_alias | |
98 | { | |
99 | const char *name; | |
100 | int regnum; | |
101 | }; | |
102 | ||
103 | /* Aliases for o32 and most other ABIs. */ | |
104 | const struct register_alias mips_o32_aliases[] = { | |
105 | { "ta0", 12 }, | |
106 | { "ta1", 13 }, | |
107 | { "ta2", 14 }, | |
108 | { "ta3", 15 } | |
109 | }; | |
110 | ||
111 | /* Aliases for n32 and n64. */ | |
112 | const struct register_alias mips_n32_n64_aliases[] = { | |
113 | { "ta0", 8 }, | |
114 | { "ta1", 9 }, | |
115 | { "ta2", 10 }, | |
116 | { "ta3", 11 } | |
117 | }; | |
118 | ||
119 | /* Aliases for ABI-independent registers. */ | |
120 | const struct register_alias mips_register_aliases[] = { | |
121 | /* The architecture manuals specify these ABI-independent names for | |
122 | the GPRs. */ | |
123 | #define R(n) { "r" #n, n } | |
124 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
125 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
126 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
127 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
128 | #undef R | |
129 | ||
130 | /* k0 and k1 are sometimes called these instead (for "kernel | |
131 | temp"). */ | |
132 | { "kt0", 26 }, | |
133 | { "kt1", 27 }, | |
134 | ||
135 | /* This is the traditional GDB name for the CP0 status register. */ | |
136 | { "sr", MIPS_PS_REGNUM }, | |
137 | ||
138 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
139 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
140 | ||
141 | /* This is the traditional GDB name for the FCSR. */ | |
142 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
143 | }; | |
144 | ||
865093a3 AR |
145 | const struct register_alias mips_numeric_register_aliases[] = { |
146 | #define R(n) { #n, n } | |
147 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
148 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
149 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
150 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
151 | #undef R | |
152 | }; | |
153 | ||
c906108c SS |
154 | #ifndef MIPS_DEFAULT_FPU_TYPE |
155 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
156 | #endif | |
157 | static int mips_fpu_type_auto = 1; | |
158 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 159 | |
9ace0497 | 160 | static int mips_debug = 0; |
7a292a7a | 161 | |
29709017 DJ |
162 | /* Properties (for struct target_desc) describing the g/G packet |
163 | layout. */ | |
164 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
165 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
166 | ||
4eb0ad19 DJ |
167 | struct target_desc *mips_tdesc_gp32; |
168 | struct target_desc *mips_tdesc_gp64; | |
169 | ||
56cea623 AC |
170 | const struct mips_regnum * |
171 | mips_regnum (struct gdbarch *gdbarch) | |
172 | { | |
173 | return gdbarch_tdep (gdbarch)->regnum; | |
174 | } | |
175 | ||
176 | static int | |
177 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
178 | { | |
179 | return mips_regnum (gdbarch)->fp0 + 12; | |
180 | } | |
181 | ||
74ed0bb4 MD |
182 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
183 | == MIPS_ABI_EABI32 \ | |
184 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 185 | |
025bb325 MS |
186 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
187 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 188 | |
025bb325 MS |
189 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
190 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 191 | |
74ed0bb4 | 192 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 193 | |
95404a3e AC |
194 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
195 | functions to test, set, or clear bit 0 of addresses. */ | |
196 | ||
197 | static CORE_ADDR | |
198 | is_mips16_addr (CORE_ADDR addr) | |
199 | { | |
200 | return ((addr) & 1); | |
201 | } | |
202 | ||
95404a3e AC |
203 | static CORE_ADDR |
204 | unmake_mips16_addr (CORE_ADDR addr) | |
205 | { | |
5b652102 | 206 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
207 | } |
208 | ||
930bd0e0 KB |
209 | static CORE_ADDR |
210 | make_mips16_addr (CORE_ADDR addr) | |
211 | { | |
212 | return ((addr) | (CORE_ADDR) 1); | |
213 | } | |
214 | ||
d1973055 KB |
215 | /* Return the MIPS ABI associated with GDBARCH. */ |
216 | enum mips_abi | |
217 | mips_abi (struct gdbarch *gdbarch) | |
218 | { | |
219 | return gdbarch_tdep (gdbarch)->mips_abi; | |
220 | } | |
221 | ||
4246e332 | 222 | int |
1b13c4f6 | 223 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 224 | { |
29709017 DJ |
225 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
226 | ||
227 | /* If we know how big the registers are, use that size. */ | |
228 | if (tdep->register_size_valid_p) | |
229 | return tdep->register_size; | |
230 | ||
231 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
232 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
233 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
234 | } | |
235 | ||
025bb325 | 236 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 237 | |
e6bc2e8a | 238 | unsigned int |
13326b4e | 239 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 240 | { |
1a69e1e4 DJ |
241 | switch (mips_abi (gdbarch)) |
242 | { | |
243 | case MIPS_ABI_EABI32: | |
244 | case MIPS_ABI_O32: | |
245 | return 4; | |
246 | case MIPS_ABI_N32: | |
247 | case MIPS_ABI_N64: | |
248 | case MIPS_ABI_O64: | |
249 | case MIPS_ABI_EABI64: | |
250 | return 8; | |
251 | case MIPS_ABI_UNKNOWN: | |
252 | case MIPS_ABI_LAST: | |
253 | default: | |
254 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
255 | } | |
d929b26f AC |
256 | } |
257 | ||
71b8ef93 | 258 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 259 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 260 | "info" field is used for this purpose. |
5a89d8aa | 261 | |
95f1da47 | 262 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
263 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
264 | minimal symbol to mark it as a 16-bit function | |
265 | ||
f594e5e9 | 266 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 267 | |
5a89d8aa | 268 | static void |
6d82d43b AC |
269 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
270 | { | |
271 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
272 | { | |
b887350f | 273 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b | 274 | } |
5a89d8aa MS |
275 | } |
276 | ||
71b8ef93 MS |
277 | static int |
278 | msymbol_is_special (struct minimal_symbol *msym) | |
279 | { | |
b887350f | 280 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
281 | } |
282 | ||
88658117 AC |
283 | /* XFER a value from the big/little/left end of the register. |
284 | Depending on the size of the value it might occupy the entire | |
285 | register or just part of it. Make an allowance for this, aligning | |
286 | things accordingly. */ | |
287 | ||
288 | static void | |
ba32f989 DJ |
289 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
290 | int reg_num, int length, | |
870cd05e MK |
291 | enum bfd_endian endian, gdb_byte *in, |
292 | const gdb_byte *out, int buf_offset) | |
88658117 | 293 | { |
88658117 | 294 | int reg_offset = 0; |
72a155b4 UW |
295 | |
296 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
297 | /* Need to transfer the left or right part of the register, based on |
298 | the targets byte order. */ | |
88658117 AC |
299 | switch (endian) |
300 | { | |
301 | case BFD_ENDIAN_BIG: | |
72a155b4 | 302 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
303 | break; |
304 | case BFD_ENDIAN_LITTLE: | |
305 | reg_offset = 0; | |
306 | break; | |
6d82d43b | 307 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
308 | reg_offset = 0; |
309 | break; | |
310 | default: | |
e2e0b3e5 | 311 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
312 | } |
313 | if (mips_debug) | |
cb1d2653 AC |
314 | fprintf_unfiltered (gdb_stderr, |
315 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
316 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
317 | if (mips_debug && out != NULL) |
318 | { | |
319 | int i; | |
cb1d2653 | 320 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 321 | for (i = 0; i < length; i++) |
cb1d2653 | 322 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
323 | } |
324 | if (in != NULL) | |
6d82d43b AC |
325 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
326 | in + buf_offset); | |
88658117 | 327 | if (out != NULL) |
6d82d43b AC |
328 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
329 | out + buf_offset); | |
88658117 AC |
330 | if (mips_debug && in != NULL) |
331 | { | |
332 | int i; | |
cb1d2653 | 333 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 334 | for (i = 0; i < length; i++) |
cb1d2653 | 335 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
336 | } |
337 | if (mips_debug) | |
338 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
339 | } | |
340 | ||
dd824b04 DJ |
341 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
342 | compatiblity mode. A return value of 1 means that we have | |
343 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
344 | ||
345 | static int | |
9c9acae0 | 346 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 347 | { |
72a155b4 | 348 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
349 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
350 | meaningful. */ | |
72a155b4 | 351 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
352 | return 0; |
353 | ||
354 | #if 0 | |
355 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
356 | in all the places we deal with FP registers. PR gdb/413. */ | |
357 | /* Otherwise check the FR bit in the status register - it controls | |
358 | the FP compatiblity mode. If it is clear we are in compatibility | |
359 | mode. */ | |
9c9acae0 | 360 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
361 | return 1; |
362 | #endif | |
361d1df0 | 363 | |
dd824b04 DJ |
364 | return 0; |
365 | } | |
366 | ||
7a292a7a | 367 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 368 | |
74ed0bb4 | 369 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 370 | |
a14ed312 | 371 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 372 | |
025bb325 | 373 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
374 | |
375 | static struct cmd_list_element *setmipscmdlist = NULL; | |
376 | static struct cmd_list_element *showmipscmdlist = NULL; | |
377 | ||
5e2e9765 KB |
378 | /* Integer registers 0 thru 31 are handled explicitly by |
379 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 380 | are listed in the following tables. */ |
691c0433 | 381 | |
6d82d43b AC |
382 | enum |
383 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
384 | |
385 | /* Generic MIPS. */ | |
386 | ||
387 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
388 | "sr", "lo", "hi", "bad", "cause", "pc", |
389 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
390 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
391 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
392 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
393 | "fsr", "fir", "" /*"fp" */ , "", | |
394 | "", "", "", "", "", "", "", "", | |
395 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
396 | }; |
397 | ||
398 | /* Names of IDT R3041 registers. */ | |
399 | ||
400 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
401 | "sr", "lo", "hi", "bad", "cause", "pc", |
402 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
403 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
404 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
405 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
406 | "fsr", "fir", "", /*"fp" */ "", | |
407 | "", "", "bus", "ccfg", "", "", "", "", | |
408 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
409 | }; |
410 | ||
411 | /* Names of tx39 registers. */ | |
412 | ||
413 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
414 | "sr", "lo", "hi", "bad", "cause", "pc", |
415 | "", "", "", "", "", "", "", "", | |
416 | "", "", "", "", "", "", "", "", | |
417 | "", "", "", "", "", "", "", "", | |
418 | "", "", "", "", "", "", "", "", | |
419 | "", "", "", "", | |
420 | "", "", "", "", "", "", "", "", | |
421 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
422 | }; |
423 | ||
424 | /* Names of IRIX registers. */ | |
425 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
426 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
427 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
428 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
429 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
430 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
431 | }; |
432 | ||
cce74817 | 433 | |
5e2e9765 | 434 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 435 | static const char * |
d93859e2 | 436 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 437 | { |
d93859e2 | 438 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
439 | /* GPR names for all ABIs other than n32/n64. */ |
440 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
441 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
442 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
443 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
444 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
445 | }; |
446 | ||
447 | /* GPR names for n32 and n64 ABIs. */ | |
448 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
449 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
450 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
451 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
452 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
453 | }; |
454 | ||
d93859e2 | 455 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 456 | |
f57d151a | 457 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
458 | but then don't make the raw register names visible. This (upper) |
459 | range of user visible register numbers are the pseudo-registers. | |
460 | ||
461 | This approach was adopted accommodate the following scenario: | |
462 | It is possible to debug a 64-bit device using a 32-bit | |
463 | programming model. In such instances, the raw registers are | |
464 | configured to be 64-bits wide, while the pseudo registers are | |
465 | configured to be 32-bits wide. The registers that the user | |
466 | sees - the pseudo registers - match the users expectations | |
467 | given the programming model being used. */ | |
d93859e2 UW |
468 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
469 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
470 | return ""; |
471 | ||
5e2e9765 KB |
472 | /* The MIPS integer registers are always mapped from 0 to 31. The |
473 | names of the registers (which reflects the conventions regarding | |
474 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 475 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
476 | { |
477 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 478 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 479 | else |
a4b8ebc8 | 480 | return mips_gpr_names[rawnum]; |
5e2e9765 | 481 | } |
d93859e2 UW |
482 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
483 | return tdesc_register_name (gdbarch, rawnum); | |
484 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
485 | { |
486 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
487 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
488 | } | |
5e2e9765 KB |
489 | else |
490 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 491 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 492 | } |
5e2e9765 | 493 | |
a4b8ebc8 | 494 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 495 | |
a4b8ebc8 AC |
496 | static int |
497 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
498 | struct reggroup *reggroup) | |
499 | { | |
500 | int vector_p; | |
501 | int float_p; | |
502 | int raw_p; | |
72a155b4 UW |
503 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
504 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
505 | if (reggroup == all_reggroup) |
506 | return pseudo; | |
507 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
508 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
509 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
510 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
511 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
512 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
513 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
514 | return 0; |
515 | if (reggroup == float_reggroup) | |
516 | return float_p && pseudo; | |
517 | if (reggroup == vector_reggroup) | |
518 | return vector_p && pseudo; | |
519 | if (reggroup == general_reggroup) | |
520 | return (!vector_p && !float_p) && pseudo; | |
521 | /* Save the pseudo registers. Need to make certain that any code | |
522 | extracting register values from a saved register cache also uses | |
523 | pseudo registers. */ | |
524 | if (reggroup == save_reggroup) | |
525 | return raw_p && pseudo; | |
526 | /* Restore the same pseudo register. */ | |
527 | if (reggroup == restore_reggroup) | |
528 | return raw_p && pseudo; | |
6d82d43b | 529 | return 0; |
a4b8ebc8 AC |
530 | } |
531 | ||
f8b73d13 DJ |
532 | /* Return the groups that a MIPS register can be categorised into. |
533 | This version is only used if we have a target description which | |
534 | describes real registers (and their groups). */ | |
535 | ||
536 | static int | |
537 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
538 | struct reggroup *reggroup) | |
539 | { | |
540 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
541 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
542 | int ret; | |
543 | ||
544 | /* Only save, restore, and display the pseudo registers. Need to | |
545 | make certain that any code extracting register values from a | |
546 | saved register cache also uses pseudo registers. | |
547 | ||
548 | Note: saving and restoring the pseudo registers is slightly | |
549 | strange; if we have 64 bits, we should save and restore all | |
550 | 64 bits. But this is hard and has little benefit. */ | |
551 | if (!pseudo) | |
552 | return 0; | |
553 | ||
554 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
555 | if (ret != -1) | |
556 | return ret; | |
557 | ||
558 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
559 | } | |
560 | ||
a4b8ebc8 | 561 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 562 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 563 | registers. Take care of alignment and size problems. */ |
c5aa993b | 564 | |
05d1431c | 565 | static enum register_status |
a4b8ebc8 | 566 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 567 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 568 | { |
72a155b4 UW |
569 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
570 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
571 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 572 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 573 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
574 | else if (register_size (gdbarch, rawnum) > |
575 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 576 | { |
8bdf35dc | 577 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 578 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 579 | else |
8bdf35dc KB |
580 | { |
581 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
582 | LONGEST regval; | |
05d1431c PA |
583 | enum register_status status; |
584 | ||
585 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
586 | if (status == REG_VALID) | |
587 | store_signed_integer (buf, 4, byte_order, regval); | |
588 | return status; | |
8bdf35dc | 589 | } |
47ebcfbe AC |
590 | } |
591 | else | |
e2e0b3e5 | 592 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
593 | } |
594 | ||
595 | static void | |
6d82d43b AC |
596 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
597 | struct regcache *regcache, int cookednum, | |
47a35522 | 598 | const gdb_byte *buf) |
a4b8ebc8 | 599 | { |
72a155b4 UW |
600 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
601 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
602 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 603 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 604 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
605 | else if (register_size (gdbarch, rawnum) > |
606 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 607 | { |
8bdf35dc | 608 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
609 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
610 | else | |
8bdf35dc KB |
611 | { |
612 | /* Sign extend the shortened version of the register prior | |
613 | to placing it in the raw register. This is required for | |
614 | some mips64 parts in order to avoid unpredictable behavior. */ | |
615 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
616 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
617 | regcache_raw_write_signed (regcache, rawnum, regval); | |
618 | } | |
47ebcfbe AC |
619 | } |
620 | else | |
e2e0b3e5 | 621 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 622 | } |
c5aa993b | 623 | |
175ff332 HZ |
624 | static int |
625 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
626 | struct agent_expr *ax, int reg) | |
627 | { | |
628 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
629 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
630 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
631 | ||
632 | ax_reg_mask (ax, rawnum); | |
633 | ||
634 | return 0; | |
635 | } | |
636 | ||
637 | static int | |
638 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
639 | struct agent_expr *ax, int reg) | |
640 | { | |
641 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
642 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
643 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
644 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
645 | { | |
646 | ax_reg (ax, rawnum); | |
647 | ||
648 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
649 | { | |
650 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
651 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
652 | { | |
653 | ax_const_l (ax, 32); | |
654 | ax_simple (ax, aop_lsh); | |
655 | } | |
656 | ax_const_l (ax, 32); | |
657 | ax_simple (ax, aop_rsh_signed); | |
658 | } | |
659 | } | |
660 | else | |
661 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
c906108c | 666 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 667 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
668 | |
669 | /* Heuristic_proc_start may hunt through the text section for a long | |
670 | time across a 2400 baud serial line. Allows the user to limit this | |
671 | search. */ | |
672 | ||
673 | static unsigned int heuristic_fence_post = 0; | |
674 | ||
46cd78fb | 675 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
676 | register N. NOTE: This defines the pseudo register type so need to |
677 | rebuild the architecture vector. */ | |
43e526b9 JM |
678 | |
679 | static int mips64_transfers_32bit_regs_p = 0; | |
680 | ||
719ec221 AC |
681 | static void |
682 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
683 | struct cmd_list_element *c) | |
43e526b9 | 684 | { |
719ec221 AC |
685 | struct gdbarch_info info; |
686 | gdbarch_info_init (&info); | |
687 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
688 | instead of relying on globals. Doing that would let generic code | |
689 | handle the search for this specific architecture. */ | |
690 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 691 | { |
719ec221 | 692 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 693 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 694 | } |
a4b8ebc8 AC |
695 | } |
696 | ||
47ebcfbe | 697 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 698 | |
ee51a8c7 KB |
699 | /* This predicate tests for the case of an 8 byte floating point |
700 | value that is being transferred to or from a pair of floating point | |
701 | registers each of which are (or are considered to be) only 4 bytes | |
702 | wide. */ | |
ff2e87ac | 703 | static int |
ee51a8c7 KB |
704 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
705 | struct type *type) | |
ff2e87ac | 706 | { |
0abe36f5 MD |
707 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
708 | && register_size (gdbarch, regnum) == 4 | |
709 | && (regnum % gdbarch_num_regs (gdbarch)) | |
710 | >= mips_regnum (gdbarch)->fp0 | |
711 | && (regnum % gdbarch_num_regs (gdbarch)) | |
712 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 713 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
714 | } |
715 | ||
ee51a8c7 KB |
716 | /* This predicate tests for the case of a value of less than 8 |
717 | bytes in width that is being transfered to or from an 8 byte | |
718 | general purpose register. */ | |
719 | static int | |
720 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
721 | struct type *type) | |
722 | { | |
723 | int num_regs = gdbarch_num_regs (gdbarch); | |
724 | ||
725 | return (register_size (gdbarch, regnum) == 8 | |
726 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
727 | && TYPE_LENGTH (type) < 8); | |
728 | } | |
729 | ||
730 | static int | |
025bb325 MS |
731 | mips_convert_register_p (struct gdbarch *gdbarch, |
732 | int regnum, struct type *type) | |
ee51a8c7 KB |
733 | { |
734 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
735 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
736 | } | |
737 | ||
8dccd430 | 738 | static int |
ff2e87ac | 739 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
740 | struct type *type, gdb_byte *to, |
741 | int *optimizedp, int *unavailablep) | |
102182a9 | 742 | { |
ee51a8c7 KB |
743 | struct gdbarch *gdbarch = get_frame_arch (frame); |
744 | ||
745 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
746 | { | |
747 | get_frame_register (frame, regnum + 0, to + 4); | |
748 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
749 | |
750 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
751 | optimizedp, unavailablep)) | |
752 | return 0; | |
753 | ||
754 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
755 | optimizedp, unavailablep)) | |
756 | return 0; | |
757 | *optimizedp = *unavailablep = 0; | |
758 | return 1; | |
ee51a8c7 KB |
759 | } |
760 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
761 | { | |
762 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
763 | CORE_ADDR offset; |
764 | ||
765 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
766 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
767 | optimizedp, unavailablep)) | |
768 | return 0; | |
769 | ||
770 | *optimizedp = *unavailablep = 0; | |
771 | return 1; | |
ee51a8c7 KB |
772 | } |
773 | else | |
774 | { | |
775 | internal_error (__FILE__, __LINE__, | |
776 | _("mips_register_to_value: unrecognized case")); | |
777 | } | |
102182a9 MS |
778 | } |
779 | ||
42c466d7 | 780 | static void |
ff2e87ac | 781 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 782 | struct type *type, const gdb_byte *from) |
102182a9 | 783 | { |
ee51a8c7 KB |
784 | struct gdbarch *gdbarch = get_frame_arch (frame); |
785 | ||
786 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
787 | { | |
788 | put_frame_register (frame, regnum + 0, from + 4); | |
789 | put_frame_register (frame, regnum + 1, from + 0); | |
790 | } | |
791 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
792 | { | |
793 | gdb_byte fill[8]; | |
794 | int len = TYPE_LENGTH (type); | |
795 | ||
796 | /* Sign extend values, irrespective of type, that are stored to | |
797 | a 64-bit general purpose register. (32-bit unsigned values | |
798 | are stored as signed quantities within a 64-bit register. | |
799 | When performing an operation, in compiled code, that combines | |
800 | a 32-bit unsigned value with a signed 64-bit value, a type | |
801 | conversion is first performed that zeroes out the high 32 bits.) */ | |
802 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
803 | { | |
804 | if (from[0] & 0x80) | |
805 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
806 | else | |
807 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
808 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
809 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
810 | } | |
811 | else | |
812 | { | |
813 | if (from[len-1] & 0x80) | |
814 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
815 | else | |
816 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
817 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
818 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
819 | } | |
820 | } | |
821 | else | |
822 | { | |
823 | internal_error (__FILE__, __LINE__, | |
824 | _("mips_value_to_register: unrecognized case")); | |
825 | } | |
102182a9 MS |
826 | } |
827 | ||
a4b8ebc8 AC |
828 | /* Return the GDB type object for the "standard" data type of data in |
829 | register REG. */ | |
78fde5f8 KB |
830 | |
831 | static struct type * | |
a4b8ebc8 AC |
832 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
833 | { | |
72a155b4 UW |
834 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
835 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
836 | && (regnum % gdbarch_num_regs (gdbarch)) | |
837 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 838 | { |
5ef80fb0 | 839 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 840 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 841 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 842 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 843 | else |
27067745 | 844 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 845 | } |
72a155b4 | 846 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
847 | { |
848 | /* The raw or ISA registers. These are all sized according to | |
849 | the ISA regsize. */ | |
850 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 851 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 852 | else |
df4df182 | 853 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 854 | } |
78fde5f8 | 855 | else |
d5ac5a39 AC |
856 | { |
857 | /* The cooked or ABI registers. These are sized according to | |
858 | the ABI (with a few complications). */ | |
72a155b4 UW |
859 | if (regnum >= (gdbarch_num_regs (gdbarch) |
860 | + mips_regnum (gdbarch)->fp_control_status) | |
861 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
862 | /* The pseudo/cooked view of the embedded registers is always |
863 | 32-bit. The raw view is handled below. */ | |
df4df182 | 864 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
865 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
866 | /* The target, while possibly using a 64-bit register buffer, | |
867 | is only transfering 32-bits of each integer register. | |
868 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 869 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
870 | else if (mips_abi_regsize (gdbarch) == 4) |
871 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
872 | 32- or 64-bit). */ | |
df4df182 | 873 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
874 | else |
875 | /* 64-bit ABI. */ | |
df4df182 | 876 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 877 | } |
78fde5f8 KB |
878 | } |
879 | ||
f8b73d13 DJ |
880 | /* Return the GDB type for the pseudo register REGNUM, which is the |
881 | ABI-level view. This function is only called if there is a target | |
882 | description which includes registers, so we know precisely the | |
883 | types of hardware registers. */ | |
884 | ||
885 | static struct type * | |
886 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
887 | { | |
888 | const int num_regs = gdbarch_num_regs (gdbarch); | |
889 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
890 | int rawnum = regnum % num_regs; | |
891 | struct type *rawtype; | |
892 | ||
893 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
894 | ||
895 | /* Absent registers are still absent. */ | |
896 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
897 | if (TYPE_LENGTH (rawtype) == 0) | |
898 | return rawtype; | |
899 | ||
900 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
901 | /* Present the floating point registers however the hardware did; | |
902 | do not try to convert between FPU layouts. */ | |
903 | return rawtype; | |
904 | ||
905 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
906 | { | |
907 | /* The pseudo/cooked view of embedded registers is always | |
908 | 32-bit, even if the target transfers 64-bit values for them. | |
909 | New targets relying on XML descriptions should only transfer | |
910 | the necessary 32 bits, but older versions of GDB expected 64, | |
911 | so allow the target to provide 64 bits without interfering | |
912 | with the displayed type. */ | |
df4df182 | 913 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
914 | } |
915 | ||
916 | /* Use pointer types for registers if we can. For n32 we can not, | |
917 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
918 | if (mips_abi_regsize (gdbarch) |
919 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
920 | { |
921 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 922 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 923 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 924 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
925 | } |
926 | ||
927 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
928 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
df4df182 | 929 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
930 | |
931 | /* For all other registers, pass through the hardware type. */ | |
932 | return rawtype; | |
933 | } | |
bcb0cc15 | 934 | |
025bb325 | 935 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 936 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
937 | |
938 | static int | |
480d3dd2 | 939 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
940 | { |
941 | switch (mask_address_var) | |
942 | { | |
7f19b9a2 | 943 | case AUTO_BOOLEAN_TRUE: |
4014092b | 944 | return 1; |
7f19b9a2 | 945 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
946 | return 0; |
947 | break; | |
7f19b9a2 | 948 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 949 | return tdep->default_mask_address_p; |
4014092b | 950 | default: |
025bb325 MS |
951 | internal_error (__FILE__, __LINE__, |
952 | _("mips_mask_address_p: bad switch")); | |
4014092b | 953 | return -1; |
361d1df0 | 954 | } |
4014092b AC |
955 | } |
956 | ||
957 | static void | |
08546159 AC |
958 | show_mask_address (struct ui_file *file, int from_tty, |
959 | struct cmd_list_element *c, const char *value) | |
4014092b | 960 | { |
1cf3db46 | 961 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
962 | |
963 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
964 | switch (mask_address_var) |
965 | { | |
7f19b9a2 | 966 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
967 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
968 | break; | |
7f19b9a2 | 969 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
970 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
971 | break; | |
7f19b9a2 | 972 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
973 | printf_filtered |
974 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
975 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
976 | break; |
977 | default: | |
e2e0b3e5 | 978 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 979 | break; |
361d1df0 | 980 | } |
4014092b | 981 | } |
c906108c | 982 | |
c906108c SS |
983 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
984 | ||
0fe7e7c8 AC |
985 | int |
986 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
987 | { |
988 | struct minimal_symbol *sym; | |
989 | ||
91912e4d MR |
990 | /* A flag indicating that this is a MIPS16 function is stored by |
991 | elfread.c in the high bit of the info field. Use this to decide | |
992 | if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of | |
993 | the address is set, assume this is a MIPS16 address. */ | |
c906108c SS |
994 | sym = lookup_minimal_symbol_by_pc (memaddr); |
995 | if (sym) | |
71b8ef93 | 996 | return msymbol_is_special (sym); |
c906108c | 997 | else |
91912e4d | 998 | return is_mips16_addr (memaddr); |
c906108c SS |
999 | } |
1000 | ||
b2fa5097 | 1001 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1002 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1003 | |
1004 | static CORE_ADDR | |
61a1198a | 1005 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1006 | { |
61a1198a UW |
1007 | ULONGEST pc; |
1008 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
1009 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
930bd0e0 KB |
1010 | if (is_mips16_addr (pc)) |
1011 | pc = unmake_mips16_addr (pc); | |
61a1198a | 1012 | return pc; |
b6cb9035 AC |
1013 | } |
1014 | ||
58dfe9ff AC |
1015 | static CORE_ADDR |
1016 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1017 | { | |
930bd0e0 KB |
1018 | ULONGEST pc; |
1019 | ||
1020 | pc = frame_unwind_register_signed | |
1021 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
1022 | if (is_mips16_addr (pc)) | |
1023 | pc = unmake_mips16_addr (pc); | |
1024 | return pc; | |
edfae063 AC |
1025 | } |
1026 | ||
30244cd8 UW |
1027 | static CORE_ADDR |
1028 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1029 | { | |
72a155b4 UW |
1030 | return frame_unwind_register_signed |
1031 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1032 | } |
1033 | ||
b8a22b94 | 1034 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1035 | dummy frame. The frame ID's base needs to match the TOS value |
1036 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1037 | breakpoint. */ | |
1038 | ||
1039 | static struct frame_id | |
b8a22b94 | 1040 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1041 | { |
f57d151a | 1042 | return frame_id_build |
b8a22b94 DJ |
1043 | (get_frame_register_signed (this_frame, |
1044 | gdbarch_num_regs (gdbarch) | |
1045 | + MIPS_SP_REGNUM), | |
1046 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1047 | } |
1048 | ||
b6cb9035 | 1049 | static void |
61a1198a | 1050 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1051 | { |
61a1198a | 1052 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
930bd0e0 KB |
1053 | if (mips_pc_is_mips16 (pc)) |
1054 | regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc)); | |
1055 | else | |
1056 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 1057 | } |
c906108c | 1058 | |
c906108c SS |
1059 | /* Fetch and return instruction from the specified location. If the PC |
1060 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
1061 | ||
d37cca3d | 1062 | static ULONGEST |
e17a4113 | 1063 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 1064 | { |
e17a4113 | 1065 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1066 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1067 | int instlen; |
1068 | int status; | |
1069 | ||
0fe7e7c8 | 1070 | if (mips_pc_is_mips16 (addr)) |
c906108c | 1071 | { |
95ac2dcf | 1072 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 1073 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1074 | } |
1075 | else | |
95ac2dcf | 1076 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 1077 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
1078 | if (status) |
1079 | memory_error (status, addr); | |
e17a4113 | 1080 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1081 | } |
1082 | ||
025bb325 | 1083 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1084 | #define mips32_op(x) (x >> 26) |
1085 | #define itype_op(x) (x >> 26) | |
1086 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1087 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1088 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1089 | |
e135b889 DJ |
1090 | #define jtype_op(x) (x >> 26) |
1091 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1092 | |
e135b889 DJ |
1093 | #define rtype_op(x) (x >> 26) |
1094 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1095 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1096 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1097 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1098 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1099 | |
06987e64 MK |
1100 | static LONGEST |
1101 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1102 | { |
06987e64 | 1103 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1104 | } |
1105 | ||
f49e4e6d MS |
1106 | /* Determine where to set a single step breakpoint while considering |
1107 | branch prediction. */ | |
5a89d8aa | 1108 | static CORE_ADDR |
0b1b3e42 | 1109 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1110 | { |
e17a4113 | 1111 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1112 | unsigned long inst; |
1113 | int op; | |
e17a4113 | 1114 | inst = mips_fetch_instruction (gdbarch, pc); |
025bb325 MS |
1115 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1116 | instruction. */ | |
c5aa993b | 1117 | { |
e135b889 | 1118 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1119 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1120 | { |
e135b889 | 1121 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1122 | switch (op) |
1123 | { | |
e135b889 DJ |
1124 | case 0: /* BEQL */ |
1125 | goto equal_branch; | |
1126 | case 1: /* BNEL */ | |
1127 | goto neq_branch; | |
1128 | case 2: /* BLEZL */ | |
1129 | goto less_branch; | |
313628cc | 1130 | case 3: /* BGTZL */ |
e135b889 | 1131 | goto greater_branch; |
c5aa993b JM |
1132 | default: |
1133 | pc += 4; | |
c906108c SS |
1134 | } |
1135 | } | |
e135b889 | 1136 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1137 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1138 | { |
1139 | int tf = itype_rt (inst) & 0x01; | |
1140 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 1141 | int fcrcs = |
72a155b4 UW |
1142 | get_frame_register_signed (frame, |
1143 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 1144 | fp_control_status); |
040dff2a | 1145 | int cond = ((fcrcs >> 24) & 0xfe) | ((fcrcs >> 23) & 0x01); |
e135b889 DJ |
1146 | |
1147 | if (((cond >> cnum) & 0x01) == tf) | |
1148 | pc += mips32_relative_offset (inst) + 4; | |
1149 | else | |
1150 | pc += 8; | |
1151 | } | |
c5aa993b | 1152 | else |
025bb325 | 1153 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1154 | } |
1155 | else | |
025bb325 | 1156 | { /* This gets way messy. */ |
c5aa993b | 1157 | |
025bb325 MS |
1158 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
1159 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | |
c906108c | 1160 | { |
c5aa993b JM |
1161 | case 0: /* SPECIAL */ |
1162 | op = rtype_funct (inst); | |
1163 | switch (op) | |
1164 | { | |
1165 | case 8: /* JR */ | |
1166 | case 9: /* JALR */ | |
025bb325 | 1167 | /* Set PC to that address. */ |
0b1b3e42 | 1168 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1169 | break; |
e38d4e1a DJ |
1170 | case 12: /* SYSCALL */ |
1171 | { | |
1172 | struct gdbarch_tdep *tdep; | |
1173 | ||
1174 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1175 | if (tdep->syscall_next_pc != NULL) | |
1176 | pc = tdep->syscall_next_pc (frame); | |
1177 | else | |
1178 | pc += 4; | |
1179 | } | |
1180 | break; | |
c5aa993b JM |
1181 | default: |
1182 | pc += 4; | |
1183 | } | |
1184 | ||
6d82d43b | 1185 | break; /* end SPECIAL */ |
025bb325 | 1186 | case 1: /* REGIMM */ |
c906108c | 1187 | { |
e135b889 DJ |
1188 | op = itype_rt (inst); /* branch condition */ |
1189 | switch (op) | |
c906108c | 1190 | { |
c5aa993b | 1191 | case 0: /* BLTZ */ |
e135b889 DJ |
1192 | case 2: /* BLTZL */ |
1193 | case 16: /* BLTZAL */ | |
c5aa993b | 1194 | case 18: /* BLTZALL */ |
c906108c | 1195 | less_branch: |
0b1b3e42 | 1196 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1197 | pc += mips32_relative_offset (inst) + 4; |
1198 | else | |
1199 | pc += 8; /* after the delay slot */ | |
1200 | break; | |
e135b889 | 1201 | case 1: /* BGEZ */ |
c5aa993b JM |
1202 | case 3: /* BGEZL */ |
1203 | case 17: /* BGEZAL */ | |
1204 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1205 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1206 | pc += mips32_relative_offset (inst) + 4; |
1207 | else | |
1208 | pc += 8; /* after the delay slot */ | |
1209 | break; | |
e135b889 | 1210 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1211 | default: |
1212 | pc += 4; | |
c906108c SS |
1213 | } |
1214 | } | |
6d82d43b | 1215 | break; /* end REGIMM */ |
c5aa993b JM |
1216 | case 2: /* J */ |
1217 | case 3: /* JAL */ | |
1218 | { | |
1219 | unsigned long reg; | |
1220 | reg = jtype_target (inst) << 2; | |
025bb325 | 1221 | /* Upper four bits get never changed... */ |
5b652102 | 1222 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1223 | } |
c5aa993b JM |
1224 | break; |
1225 | /* FIXME case JALX : */ | |
1226 | { | |
1227 | unsigned long reg; | |
1228 | reg = jtype_target (inst) << 2; | |
025bb325 | 1229 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1230 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1231 | } | |
c5aa993b | 1232 | break; /* The new PC will be alternate mode */ |
e135b889 | 1233 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1234 | equal_branch: |
0b1b3e42 UW |
1235 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1236 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1237 | pc += mips32_relative_offset (inst) + 4; |
1238 | else | |
1239 | pc += 8; | |
1240 | break; | |
e135b889 | 1241 | case 5: /* BNE, BNEL */ |
c5aa993b | 1242 | neq_branch: |
0b1b3e42 UW |
1243 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1244 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1245 | pc += mips32_relative_offset (inst) + 4; |
1246 | else | |
1247 | pc += 8; | |
1248 | break; | |
e135b889 | 1249 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1250 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1251 | pc += mips32_relative_offset (inst) + 4; |
1252 | else | |
1253 | pc += 8; | |
1254 | break; | |
1255 | case 7: | |
e135b889 DJ |
1256 | default: |
1257 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1258 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1259 | pc += mips32_relative_offset (inst) + 4; |
1260 | else | |
1261 | pc += 8; | |
1262 | break; | |
c5aa993b JM |
1263 | } /* switch */ |
1264 | } /* else */ | |
1265 | return pc; | |
1266 | } /* mips32_next_pc */ | |
c906108c SS |
1267 | |
1268 | /* Decoding the next place to set a breakpoint is irregular for the | |
025bb325 MS |
1269 | mips 16 variant, but fortunately, there fewer instructions. We have |
1270 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1271 | 32 bit instructions. We dont want to set a single step instruction | |
1272 | on the extend instruction either. */ | |
c906108c SS |
1273 | |
1274 | /* Lots of mips16 instruction formats */ | |
1275 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1276 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1277 | enum mips16_inst_fmts |
1278 | { | |
c5aa993b JM |
1279 | itype, /* 0 immediate 5,10 */ |
1280 | ritype, /* 1 5,3,8 */ | |
1281 | rrtype, /* 2 5,3,3,5 */ | |
1282 | rritype, /* 3 5,3,3,5 */ | |
1283 | rrrtype, /* 4 5,3,3,3,2 */ | |
1284 | rriatype, /* 5 5,3,3,1,4 */ | |
1285 | shifttype, /* 6 5,3,3,3,2 */ | |
1286 | i8type, /* 7 5,3,8 */ | |
1287 | i8movtype, /* 8 5,3,3,5 */ | |
1288 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1289 | i64type, /* 10 5,3,8 */ | |
1290 | ri64type, /* 11 5,3,3,5 */ | |
1291 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1292 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1293 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1294 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1295 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1296 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1297 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1298 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1299 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1300 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1301 | }; | |
12f02c2a | 1302 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 1303 | then, only the fields which are involved in instruction extension. */ |
c906108c | 1304 | struct upk_mips16 |
6d82d43b AC |
1305 | { |
1306 | CORE_ADDR offset; | |
025bb325 | 1307 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
1308 | unsigned int regy; |
1309 | }; | |
c906108c SS |
1310 | |
1311 | ||
12f02c2a | 1312 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1313 | for the bits which make up the immediate extension. */ |
c906108c | 1314 | |
12f02c2a AC |
1315 | static CORE_ADDR |
1316 | extended_offset (unsigned int extension) | |
c906108c | 1317 | { |
12f02c2a | 1318 | CORE_ADDR value; |
130854df | 1319 | |
4c2051c6 | 1320 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 1321 | value = value << 6; |
4c2051c6 | 1322 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 1323 | value = value << 5; |
130854df MR |
1324 | value |= extension & 0x1f; /* Extract 4:0. */ |
1325 | ||
c5aa993b | 1326 | return value; |
c906108c SS |
1327 | } |
1328 | ||
1329 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1330 | instruction. It won't malfunction, but why make excess remote memory |
1331 | references? If the immediate operands get sign extended or something, | |
1332 | do it after the extension is performed. */ | |
c906108c | 1333 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1334 | when the offset is to be used in relative addressing. */ |
c906108c | 1335 | |
12f02c2a | 1336 | static unsigned int |
e17a4113 | 1337 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1338 | { |
e17a4113 | 1339 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1340 | gdb_byte buf[8]; |
025bb325 | 1341 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
c5aa993b | 1342 | target_read_memory (pc, buf, 2); |
e17a4113 | 1343 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1344 | } |
1345 | ||
1346 | static void | |
e17a4113 | 1347 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1348 | unsigned int extension, |
1349 | unsigned int inst, | |
6d82d43b | 1350 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1351 | { |
12f02c2a AC |
1352 | CORE_ADDR offset; |
1353 | int regx; | |
1354 | int regy; | |
1355 | switch (insn_format) | |
c906108c | 1356 | { |
c5aa993b | 1357 | case itype: |
c906108c | 1358 | { |
12f02c2a AC |
1359 | CORE_ADDR value; |
1360 | if (extension) | |
c5aa993b | 1361 | { |
4c2051c6 MR |
1362 | value = extended_offset ((extension << 16) | inst); |
1363 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
1364 | } |
1365 | else | |
c5aa993b | 1366 | { |
12f02c2a | 1367 | value = inst & 0x7ff; |
4c2051c6 | 1368 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 1369 | } |
12f02c2a AC |
1370 | offset = value; |
1371 | regx = -1; | |
1372 | regy = -1; | |
c906108c | 1373 | } |
c5aa993b JM |
1374 | break; |
1375 | case ritype: | |
1376 | case i8type: | |
025bb325 | 1377 | { /* A register identifier and an offset. */ |
c906108c | 1378 | /* Most of the fields are the same as I type but the |
025bb325 | 1379 | immediate value is of a different length. */ |
12f02c2a AC |
1380 | CORE_ADDR value; |
1381 | if (extension) | |
c906108c | 1382 | { |
4c2051c6 MR |
1383 | value = extended_offset ((extension << 16) | inst); |
1384 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 1385 | } |
c5aa993b JM |
1386 | else |
1387 | { | |
4c2051c6 MR |
1388 | value = inst & 0xff; /* 8 bits */ |
1389 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 1390 | } |
12f02c2a | 1391 | offset = value; |
4c2051c6 | 1392 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 1393 | regy = -1; |
c5aa993b | 1394 | break; |
c906108c | 1395 | } |
c5aa993b | 1396 | case jalxtype: |
c906108c | 1397 | { |
c5aa993b | 1398 | unsigned long value; |
12f02c2a AC |
1399 | unsigned int nexthalf; |
1400 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1401 | value = value << 16; |
025bb325 MS |
1402 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit |
1403 | still set. */ | |
c5aa993b | 1404 | value |= nexthalf; |
12f02c2a AC |
1405 | offset = value; |
1406 | regx = -1; | |
1407 | regy = -1; | |
c5aa993b | 1408 | break; |
c906108c SS |
1409 | } |
1410 | default: | |
e2e0b3e5 | 1411 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1412 | } |
12f02c2a AC |
1413 | upk->offset = offset; |
1414 | upk->regx = regx; | |
1415 | upk->regy = regy; | |
c906108c SS |
1416 | } |
1417 | ||
1418 | ||
c5aa993b JM |
1419 | static CORE_ADDR |
1420 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1421 | { |
5b652102 | 1422 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1423 | } |
1424 | ||
12f02c2a | 1425 | static CORE_ADDR |
0b1b3e42 | 1426 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1427 | unsigned int extension, unsigned int insn) |
c906108c | 1428 | { |
e17a4113 | 1429 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1430 | int op = (insn >> 11); |
1431 | switch (op) | |
c906108c | 1432 | { |
6d82d43b | 1433 | case 2: /* Branch */ |
12f02c2a AC |
1434 | { |
1435 | CORE_ADDR offset; | |
1436 | struct upk_mips16 upk; | |
e17a4113 | 1437 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
4c2051c6 | 1438 | pc += (upk.offset << 1) + 2; |
12f02c2a AC |
1439 | break; |
1440 | } | |
025bb325 MS |
1441 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
1442 | instructions. */ | |
12f02c2a AC |
1443 | { |
1444 | struct upk_mips16 upk; | |
e17a4113 | 1445 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1446 | pc = add_offset_16 (pc, upk.offset); |
1447 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 1448 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
1449 | else |
1450 | pc |= 0x01; | |
1451 | break; | |
1452 | } | |
6d82d43b | 1453 | case 4: /* beqz */ |
12f02c2a AC |
1454 | { |
1455 | struct upk_mips16 upk; | |
1456 | int reg; | |
e17a4113 | 1457 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4c2051c6 | 1458 | reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); |
12f02c2a AC |
1459 | if (reg == 0) |
1460 | pc += (upk.offset << 1) + 2; | |
1461 | else | |
1462 | pc += 2; | |
1463 | break; | |
1464 | } | |
6d82d43b | 1465 | case 5: /* bnez */ |
12f02c2a AC |
1466 | { |
1467 | struct upk_mips16 upk; | |
1468 | int reg; | |
e17a4113 | 1469 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4c2051c6 | 1470 | reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); |
12f02c2a AC |
1471 | if (reg != 0) |
1472 | pc += (upk.offset << 1) + 2; | |
1473 | else | |
1474 | pc += 2; | |
1475 | break; | |
1476 | } | |
6d82d43b | 1477 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1478 | { |
1479 | struct upk_mips16 upk; | |
1480 | int reg; | |
e17a4113 | 1481 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1482 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1483 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1484 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1485 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1486 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1487 | pc += (upk.offset << 1) + 2; | |
1488 | else | |
1489 | pc += 2; | |
1490 | break; | |
1491 | } | |
6d82d43b | 1492 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1493 | { |
1494 | struct upk_mips16 upk; | |
1495 | /* upk.fmt = rrtype; */ | |
1496 | op = insn & 0x1f; | |
1497 | if (op == 0) | |
c5aa993b | 1498 | { |
12f02c2a AC |
1499 | int reg; |
1500 | upk.regx = (insn >> 8) & 0x07; | |
1501 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 MR |
1502 | if ((upk.regy & 1) == 0) |
1503 | reg = mips16_to_32_reg[upk.regx]; | |
1504 | else | |
1505 | reg = 31; /* Function return instruction. */ | |
0b1b3e42 | 1506 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1507 | } |
12f02c2a | 1508 | else |
c5aa993b | 1509 | pc += 2; |
12f02c2a AC |
1510 | break; |
1511 | } | |
1512 | case 30: | |
1513 | /* This is an instruction extension. Fetch the real instruction | |
1514 | (which follows the extension) and decode things based on | |
025bb325 | 1515 | that. */ |
12f02c2a AC |
1516 | { |
1517 | pc += 2; | |
e17a4113 UW |
1518 | pc = extended_mips16_next_pc (frame, pc, insn, |
1519 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1520 | break; |
1521 | } | |
1522 | default: | |
1523 | { | |
1524 | pc += 2; | |
1525 | break; | |
1526 | } | |
c906108c | 1527 | } |
c5aa993b | 1528 | return pc; |
12f02c2a | 1529 | } |
c906108c | 1530 | |
5a89d8aa | 1531 | static CORE_ADDR |
0b1b3e42 | 1532 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1533 | { |
e17a4113 UW |
1534 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1535 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1536 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1537 | } |
1538 | ||
1539 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1540 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 1541 | It works by decoding the current instruction and predicting where a |
025bb325 | 1542 | branch will go. This isnt hard because all the data is available. |
ce1f96de | 1543 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1544 | static CORE_ADDR |
0b1b3e42 | 1545 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1546 | { |
91912e4d | 1547 | if (mips_pc_is_mips16 (pc)) |
0b1b3e42 | 1548 | return mips16_next_pc (frame, pc); |
c5aa993b | 1549 | else |
0b1b3e42 | 1550 | return mips32_next_pc (frame, pc); |
12f02c2a | 1551 | } |
c906108c | 1552 | |
edfae063 AC |
1553 | struct mips_frame_cache |
1554 | { | |
1555 | CORE_ADDR base; | |
1556 | struct trad_frame_saved_reg *saved_regs; | |
1557 | }; | |
1558 | ||
29639122 JB |
1559 | /* Set a register's saved stack address in temp_saved_regs. If an |
1560 | address has already been set for this register, do nothing; this | |
1561 | way we will only recognize the first save of a given register in a | |
1562 | function prologue. | |
eec63939 | 1563 | |
f57d151a UW |
1564 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1565 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1566 | Strictly speaking, only the second range is used as it is only second | |
1567 | range (the ABI instead of ISA registers) that comes into play when finding | |
1568 | saved registers in a frame. */ | |
eec63939 AC |
1569 | |
1570 | static void | |
74ed0bb4 MD |
1571 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1572 | int regnum, CORE_ADDR offset) | |
eec63939 | 1573 | { |
29639122 JB |
1574 | if (this_cache != NULL |
1575 | && this_cache->saved_regs[regnum].addr == -1) | |
1576 | { | |
74ed0bb4 MD |
1577 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1578 | = offset; | |
1579 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1580 | = offset; | |
29639122 | 1581 | } |
eec63939 AC |
1582 | } |
1583 | ||
eec63939 | 1584 | |
29639122 JB |
1585 | /* Fetch the immediate value from a MIPS16 instruction. |
1586 | If the previous instruction was an EXTEND, use it to extend | |
1587 | the upper bits of the immediate value. This is a helper function | |
1588 | for mips16_scan_prologue. */ | |
eec63939 | 1589 | |
29639122 JB |
1590 | static int |
1591 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1592 | unsigned short inst, /* current instruction */ | |
1593 | int nbits, /* number of bits in imm field */ | |
1594 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 1595 | int is_signed) /* is the imm field signed? */ |
eec63939 | 1596 | { |
29639122 | 1597 | int offset; |
eec63939 | 1598 | |
29639122 JB |
1599 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1600 | { | |
1601 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1602 | if (offset & 0x8000) /* check for negative extend */ | |
1603 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1604 | return offset | (inst & 0x1f); | |
1605 | } | |
eec63939 | 1606 | else |
29639122 JB |
1607 | { |
1608 | int max_imm = 1 << nbits; | |
1609 | int mask = max_imm - 1; | |
1610 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1611 | |
29639122 JB |
1612 | offset = inst & mask; |
1613 | if (is_signed && (offset & sign_bit)) | |
1614 | offset = 0 - (max_imm - offset); | |
1615 | return offset * scale; | |
1616 | } | |
1617 | } | |
eec63939 | 1618 | |
65596487 | 1619 | |
29639122 JB |
1620 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1621 | the associated FRAME_CACHE if not null. | |
1622 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1623 | |
29639122 | 1624 | static CORE_ADDR |
e17a4113 UW |
1625 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1626 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1627 | struct frame_info *this_frame, |
29639122 JB |
1628 | struct mips_frame_cache *this_cache) |
1629 | { | |
1630 | CORE_ADDR cur_pc; | |
025bb325 | 1631 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
1632 | CORE_ADDR sp; |
1633 | long frame_offset = 0; /* Size of stack frame. */ | |
1634 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1635 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 1636 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
1637 | unsigned inst = 0; /* current instruction */ |
1638 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1639 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1640 | int reg, offset; |
a343eb3c | 1641 | |
29639122 JB |
1642 | int extend_bytes = 0; |
1643 | int prev_extend_bytes; | |
1644 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1645 | |
29639122 | 1646 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1647 | THIS_FRAME. */ |
1648 | if (this_frame != NULL) | |
1649 | sp = get_frame_register_signed (this_frame, | |
1650 | gdbarch_num_regs (gdbarch) | |
1651 | + MIPS_SP_REGNUM); | |
29639122 JB |
1652 | else |
1653 | sp = 0; | |
eec63939 | 1654 | |
29639122 JB |
1655 | if (limit_pc > start_pc + 200) |
1656 | limit_pc = start_pc + 200; | |
eec63939 | 1657 | |
95ac2dcf | 1658 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1659 | { |
1660 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1661 | the immediate offset extension from it in mips16_get_imm. */ | |
1662 | prev_inst = inst; | |
eec63939 | 1663 | |
025bb325 | 1664 | /* Fetch and decode the instruction. */ |
e17a4113 | 1665 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1666 | |
29639122 JB |
1667 | /* Normally we ignore extend instructions. However, if it is |
1668 | not followed by a valid prologue instruction, then this | |
1669 | instruction is not part of the prologue either. We must | |
1670 | remember in this case to adjust the end_prologue_addr back | |
1671 | over the extend. */ | |
1672 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1673 | { | |
95ac2dcf | 1674 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1675 | continue; |
1676 | } | |
eec63939 | 1677 | |
29639122 JB |
1678 | prev_extend_bytes = extend_bytes; |
1679 | extend_bytes = 0; | |
eec63939 | 1680 | |
29639122 JB |
1681 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1682 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1683 | { | |
1684 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 1685 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
1686 | frame_offset -= offset; |
1687 | else | |
1688 | /* Exit loop if a positive stack adjustment is found, which | |
1689 | usually means that the stack cleanup code in the function | |
1690 | epilogue is reached. */ | |
1691 | break; | |
1692 | } | |
1693 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1694 | { | |
1695 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1696 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1697 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1698 | } |
1699 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1700 | { | |
1701 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1702 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1703 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1704 | } |
1705 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1706 | { | |
1707 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1708 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1709 | } |
1710 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1711 | { | |
1712 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1713 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1714 | } |
1715 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1716 | { | |
1717 | frame_addr = sp; | |
1718 | frame_reg = 17; | |
1719 | } | |
1720 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1721 | { | |
1722 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1723 | frame_addr = sp + offset; | |
1724 | frame_reg = 17; | |
1725 | frame_adjust = offset; | |
1726 | } | |
1727 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1728 | { | |
1729 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1730 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1731 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1732 | } |
1733 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1734 | { | |
1735 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1736 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1737 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1738 | } |
1739 | else if ((inst & 0xf81f) == 0xe809 | |
1740 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 1741 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
1742 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1743 | { | |
025bb325 | 1744 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
1745 | if (prev_extend_bytes) /* extend */ |
1746 | save_inst |= prev_inst << 16; | |
1747 | } | |
29639122 | 1748 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1749 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1750 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1751 | { | |
1752 | /* This instruction is part of the prologue, but we don't | |
1753 | need to do anything special to handle it. */ | |
1754 | } | |
1755 | else | |
1756 | { | |
1757 | /* This instruction is not an instruction typically found | |
1758 | in a prologue, so we must have reached the end of the | |
1759 | prologue. */ | |
1760 | if (end_prologue_addr == 0) | |
1761 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1762 | } | |
1763 | } | |
eec63939 | 1764 | |
29639122 JB |
1765 | /* The entry instruction is typically the first instruction in a function, |
1766 | and it stores registers at offsets relative to the value of the old SP | |
1767 | (before the prologue). But the value of the sp parameter to this | |
1768 | function is the new SP (after the prologue has been executed). So we | |
1769 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 1770 | and can calculate what the old SP must have been. */ |
29639122 JB |
1771 | if (entry_inst != 0) |
1772 | { | |
1773 | int areg_count = (entry_inst >> 8) & 7; | |
1774 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1775 | |
29639122 JB |
1776 | /* The entry instruction always subtracts 32 from the SP. */ |
1777 | frame_offset += 32; | |
1778 | ||
1779 | /* Now we can calculate what the SP must have been at the | |
1780 | start of the function prologue. */ | |
1781 | sp += frame_offset; | |
1782 | ||
1783 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1784 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1785 | { | |
74ed0bb4 | 1786 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1787 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1788 | } |
1789 | ||
1790 | /* Check if the ra register was pushed on the stack. */ | |
1791 | offset = -4; | |
1792 | if (entry_inst & 0x20) | |
1793 | { | |
74ed0bb4 | 1794 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1795 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1796 | } |
1797 | ||
1798 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1799 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1800 | { | |
74ed0bb4 | 1801 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1802 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1803 | } |
1804 | } | |
1805 | ||
2207132d MR |
1806 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1807 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1808 | size of the frame is specified as an immediate field of instruction | |
1809 | and an extended variation exists which lets additional registers and | |
1810 | frame space to be specified. The instruction always treats registers | |
1811 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1812 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1813 | { | |
1814 | static int args_table[16] = { | |
1815 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1816 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1817 | }; | |
1818 | static int astatic_table[16] = { | |
1819 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1820 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1821 | }; | |
1822 | int aregs = (save_inst >> 16) & 0xf; | |
1823 | int xsregs = (save_inst >> 24) & 0x7; | |
1824 | int args = args_table[aregs]; | |
1825 | int astatic = astatic_table[aregs]; | |
1826 | long frame_size; | |
1827 | ||
1828 | if (args < 0) | |
1829 | { | |
1830 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1831 | args = 0; | |
1832 | } | |
1833 | if (astatic < 0) | |
1834 | { | |
1835 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1836 | astatic = 0; | |
1837 | } | |
1838 | ||
1839 | /* For standard SAVE the frame size of 0 means 128. */ | |
1840 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1841 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1842 | frame_size = 16; | |
1843 | frame_size *= 8; | |
1844 | frame_offset += frame_size; | |
1845 | ||
1846 | /* Now we can calculate what the SP must have been at the | |
1847 | start of the function prologue. */ | |
1848 | sp += frame_offset; | |
1849 | ||
1850 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1851 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1852 | { | |
74ed0bb4 | 1853 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1854 | offset += mips_abi_regsize (gdbarch); |
1855 | } | |
1856 | ||
1857 | offset = -4; | |
1858 | ||
1859 | /* Check if the RA register was pushed on the stack. */ | |
1860 | if (save_inst & 0x40) | |
1861 | { | |
74ed0bb4 | 1862 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1863 | offset -= mips_abi_regsize (gdbarch); |
1864 | } | |
1865 | ||
1866 | /* Check if the S8 register was pushed on the stack. */ | |
1867 | if (xsregs > 6) | |
1868 | { | |
74ed0bb4 | 1869 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1870 | offset -= mips_abi_regsize (gdbarch); |
1871 | xsregs--; | |
1872 | } | |
1873 | /* Check if S2-S7 were pushed on the stack. */ | |
1874 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1875 | { | |
74ed0bb4 | 1876 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1877 | offset -= mips_abi_regsize (gdbarch); |
1878 | } | |
1879 | ||
1880 | /* Check if the S1 register was pushed on the stack. */ | |
1881 | if (save_inst & 0x10) | |
1882 | { | |
74ed0bb4 | 1883 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1884 | offset -= mips_abi_regsize (gdbarch); |
1885 | } | |
1886 | /* Check if the S0 register was pushed on the stack. */ | |
1887 | if (save_inst & 0x20) | |
1888 | { | |
74ed0bb4 | 1889 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1890 | offset -= mips_abi_regsize (gdbarch); |
1891 | } | |
1892 | ||
1893 | /* Check if A0-A3 were pushed on the stack. */ | |
1894 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1895 | { | |
74ed0bb4 | 1896 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1897 | offset -= mips_abi_regsize (gdbarch); |
1898 | } | |
1899 | } | |
1900 | ||
29639122 JB |
1901 | if (this_cache != NULL) |
1902 | { | |
1903 | this_cache->base = | |
b8a22b94 DJ |
1904 | (get_frame_register_signed (this_frame, |
1905 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1906 | + frame_offset - frame_adjust); |
1907 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
025bb325 | 1908 | be able to get rid of the assignment below, evetually. But it's |
29639122 | 1909 | still needed for now. */ |
72a155b4 UW |
1910 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1911 | + mips_regnum (gdbarch)->pc] | |
1912 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1913 | } |
1914 | ||
1915 | /* If we didn't reach the end of the prologue when scanning the function | |
1916 | instructions, then set end_prologue_addr to the address of the | |
1917 | instruction immediately after the last one we scanned. */ | |
1918 | if (end_prologue_addr == 0) | |
1919 | end_prologue_addr = cur_pc; | |
1920 | ||
1921 | return end_prologue_addr; | |
eec63939 AC |
1922 | } |
1923 | ||
29639122 JB |
1924 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1925 | Procedures that use the 32-bit instruction set are handled by the | |
1926 | mips_insn32 unwinder. */ | |
1927 | ||
1928 | static struct mips_frame_cache * | |
b8a22b94 | 1929 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1930 | { |
e17a4113 | 1931 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 1932 | struct mips_frame_cache *cache; |
eec63939 AC |
1933 | |
1934 | if ((*this_cache) != NULL) | |
1935 | return (*this_cache); | |
29639122 JB |
1936 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1937 | (*this_cache) = cache; | |
b8a22b94 | 1938 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1939 | |
29639122 JB |
1940 | /* Analyze the function prologue. */ |
1941 | { | |
b8a22b94 | 1942 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1943 | CORE_ADDR start_addr; |
eec63939 | 1944 | |
29639122 JB |
1945 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1946 | if (start_addr == 0) | |
e17a4113 | 1947 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
1948 | /* We can't analyze the prologue if we couldn't find the begining |
1949 | of the function. */ | |
1950 | if (start_addr == 0) | |
1951 | return cache; | |
eec63939 | 1952 | |
e17a4113 | 1953 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1954 | } |
1955 | ||
3e8c568d | 1956 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1957 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 1958 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 1959 | cache->base); |
eec63939 | 1960 | |
29639122 | 1961 | return (*this_cache); |
eec63939 AC |
1962 | } |
1963 | ||
1964 | static void | |
b8a22b94 | 1965 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 1966 | struct frame_id *this_id) |
eec63939 | 1967 | { |
b8a22b94 | 1968 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1969 | this_cache); |
21327321 DJ |
1970 | /* This marks the outermost frame. */ |
1971 | if (info->base == 0) | |
1972 | return; | |
b8a22b94 | 1973 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
1974 | } |
1975 | ||
b8a22b94 DJ |
1976 | static struct value * |
1977 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
1978 | void **this_cache, int regnum) | |
eec63939 | 1979 | { |
b8a22b94 | 1980 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1981 | this_cache); |
b8a22b94 DJ |
1982 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1983 | } | |
1984 | ||
1985 | static int | |
1986 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
1987 | struct frame_info *this_frame, void **this_cache) | |
1988 | { | |
1989 | CORE_ADDR pc = get_frame_pc (this_frame); | |
1990 | if (mips_pc_is_mips16 (pc)) | |
1991 | return 1; | |
1992 | return 0; | |
eec63939 AC |
1993 | } |
1994 | ||
29639122 | 1995 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1996 | { |
1997 | NORMAL_FRAME, | |
8fbca658 | 1998 | default_frame_unwind_stop_reason, |
29639122 | 1999 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
2000 | mips_insn16_frame_prev_register, |
2001 | NULL, | |
2002 | mips_insn16_frame_sniffer | |
eec63939 AC |
2003 | }; |
2004 | ||
eec63939 | 2005 | static CORE_ADDR |
b8a22b94 | 2006 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 2007 | void **this_cache) |
eec63939 | 2008 | { |
b8a22b94 | 2009 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
2010 | this_cache); |
2011 | return info->base; | |
eec63939 AC |
2012 | } |
2013 | ||
29639122 | 2014 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2015 | { |
29639122 JB |
2016 | &mips_insn16_frame_unwind, |
2017 | mips_insn16_frame_base_address, | |
2018 | mips_insn16_frame_base_address, | |
2019 | mips_insn16_frame_base_address | |
eec63939 AC |
2020 | }; |
2021 | ||
2022 | static const struct frame_base * | |
b8a22b94 | 2023 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 2024 | { |
b8a22b94 DJ |
2025 | CORE_ADDR pc = get_frame_pc (this_frame); |
2026 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 2027 | return &mips_insn16_frame_base; |
eec63939 AC |
2028 | else |
2029 | return NULL; | |
edfae063 AC |
2030 | } |
2031 | ||
29639122 JB |
2032 | /* Mark all the registers as unset in the saved_regs array |
2033 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
2034 | ||
74ed0bb4 MD |
2035 | static void |
2036 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 2037 | { |
29639122 JB |
2038 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
2039 | return; | |
2040 | ||
2041 | { | |
74ed0bb4 | 2042 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 2043 | int i; |
64159455 | 2044 | |
29639122 JB |
2045 | for (i = 0; i < num_regs; i++) |
2046 | { | |
2047 | this_cache->saved_regs[i].addr = -1; | |
2048 | } | |
2049 | } | |
c906108c SS |
2050 | } |
2051 | ||
025bb325 | 2052 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
2053 | the associated FRAME_CACHE if not null. |
2054 | Return the address of the first instruction past the prologue. */ | |
c906108c | 2055 | |
875e1767 | 2056 | static CORE_ADDR |
e17a4113 UW |
2057 | mips32_scan_prologue (struct gdbarch *gdbarch, |
2058 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2059 | struct frame_info *this_frame, |
29639122 | 2060 | struct mips_frame_cache *this_cache) |
c906108c | 2061 | { |
29639122 | 2062 | CORE_ADDR cur_pc; |
025bb325 MS |
2063 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
2064 | frame-pointer. */ | |
29639122 JB |
2065 | CORE_ADDR sp; |
2066 | long frame_offset; | |
2067 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2068 | |
29639122 JB |
2069 | CORE_ADDR end_prologue_addr = 0; |
2070 | int seen_sp_adjust = 0; | |
2071 | int load_immediate_bytes = 0; | |
db5f024e | 2072 | int in_delay_slot = 0; |
7d1e6fb8 | 2073 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 2074 | |
29639122 | 2075 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2076 | THIS_FRAME. */ |
2077 | if (this_frame != NULL) | |
2078 | sp = get_frame_register_signed (this_frame, | |
2079 | gdbarch_num_regs (gdbarch) | |
2080 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2081 | else |
29639122 | 2082 | sp = 0; |
9022177c | 2083 | |
29639122 JB |
2084 | if (limit_pc > start_pc + 200) |
2085 | limit_pc = start_pc + 200; | |
9022177c | 2086 | |
29639122 | 2087 | restart: |
9022177c | 2088 | |
29639122 | 2089 | frame_offset = 0; |
95ac2dcf | 2090 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 2091 | { |
29639122 JB |
2092 | unsigned long inst, high_word, low_word; |
2093 | int reg; | |
9022177c | 2094 | |
025bb325 | 2095 | /* Fetch the instruction. */ |
e17a4113 | 2096 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 2097 | |
29639122 JB |
2098 | /* Save some code by pre-extracting some useful fields. */ |
2099 | high_word = (inst >> 16) & 0xffff; | |
2100 | low_word = inst & 0xffff; | |
2101 | reg = high_word & 0x1f; | |
fe29b929 | 2102 | |
025bb325 | 2103 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
2104 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2105 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2106 | { | |
025bb325 | 2107 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
2108 | frame_offset += 0x10000 - low_word; |
2109 | else | |
2110 | /* Exit loop if a positive stack adjustment is found, which | |
2111 | usually means that the stack cleanup code in the function | |
2112 | epilogue is reached. */ | |
2113 | break; | |
2114 | seen_sp_adjust = 1; | |
2115 | } | |
7d1e6fb8 KB |
2116 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
2117 | && !regsize_is_64_bits) | |
29639122 | 2118 | { |
74ed0bb4 | 2119 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 2120 | } |
7d1e6fb8 KB |
2121 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
2122 | && regsize_is_64_bits) | |
29639122 JB |
2123 | { |
2124 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 2125 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
2126 | } |
2127 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2128 | { | |
2129 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2130 | if ((long) low_word != frame_offset) | |
2131 | frame_addr = sp + low_word; | |
b8a22b94 | 2132 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2133 | { |
2134 | unsigned alloca_adjust; | |
a4b8ebc8 | 2135 | |
29639122 | 2136 | frame_reg = 30; |
b8a22b94 DJ |
2137 | frame_addr = get_frame_register_signed |
2138 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2139 | |
29639122 JB |
2140 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
2141 | if (alloca_adjust > 0) | |
2142 | { | |
025bb325 | 2143 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2144 | an alloca or somethings similar. Fix sp to |
2145 | "pre-alloca" value, and try again. */ | |
2146 | sp += alloca_adjust; | |
2147 | /* Need to reset the status of all registers. Otherwise, | |
2148 | we will hit a guard that prevents the new address | |
2149 | for each register to be recomputed during the second | |
2150 | pass. */ | |
74ed0bb4 | 2151 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2152 | goto restart; |
2153 | } | |
2154 | } | |
2155 | } | |
2156 | /* move $30,$sp. With different versions of gas this will be either | |
2157 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2158 | Accept any one of these. */ | |
2159 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2160 | { | |
2161 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2162 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2163 | { |
2164 | unsigned alloca_adjust; | |
c906108c | 2165 | |
29639122 | 2166 | frame_reg = 30; |
b8a22b94 DJ |
2167 | frame_addr = get_frame_register_signed |
2168 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2169 | |
29639122 JB |
2170 | alloca_adjust = (unsigned) (frame_addr - sp); |
2171 | if (alloca_adjust > 0) | |
2172 | { | |
025bb325 | 2173 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2174 | an alloca or somethings similar. Fix sp to |
2175 | "pre-alloca" value, and try again. */ | |
2176 | sp = frame_addr; | |
2177 | /* Need to reset the status of all registers. Otherwise, | |
2178 | we will hit a guard that prevents the new address | |
2179 | for each register to be recomputed during the second | |
2180 | pass. */ | |
74ed0bb4 | 2181 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2182 | goto restart; |
2183 | } | |
2184 | } | |
2185 | } | |
7d1e6fb8 KB |
2186 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2187 | && !regsize_is_64_bits) | |
29639122 | 2188 | { |
74ed0bb4 | 2189 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2190 | } |
2191 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2192 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2193 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2194 | || high_word == 0x3c1c /* lui $gp,n */ | |
2195 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2196 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2197 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2198 | ) | |
2199 | { | |
2200 | /* These instructions are part of the prologue, but we don't | |
2201 | need to do anything special to handle them. */ | |
2202 | } | |
2203 | /* The instructions below load $at or $t0 with an immediate | |
2204 | value in preparation for a stack adjustment via | |
025bb325 | 2205 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
2206 | initialize a local variable, so we accept them only before |
2207 | a stack adjustment instruction was seen. */ | |
2208 | else if (!seen_sp_adjust | |
2209 | && (high_word == 0x3c01 /* lui $at,n */ | |
2210 | || high_word == 0x3c08 /* lui $t0,n */ | |
2211 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2212 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2213 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2214 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2215 | )) | |
2216 | { | |
5436df95 MR |
2217 | if (end_prologue_addr == 0) |
2218 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ | |
29639122 JB |
2219 | } |
2220 | else | |
2221 | { | |
2222 | /* This instruction is not an instruction typically found | |
2223 | in a prologue, so we must have reached the end of the | |
2224 | prologue. */ | |
2225 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2226 | loop now? Why would we need to continue scanning the function | |
2227 | instructions? */ | |
2228 | if (end_prologue_addr == 0) | |
2229 | end_prologue_addr = cur_pc; | |
db5f024e DJ |
2230 | |
2231 | /* Check for branches and jumps. For now, only jump to | |
2232 | register are caught (i.e. returns). */ | |
2233 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2234 | in_delay_slot = 1; | |
29639122 | 2235 | } |
db5f024e DJ |
2236 | |
2237 | /* If the previous instruction was a jump, we must have reached | |
2238 | the end of the prologue by now. Stop scanning so that we do | |
2239 | not go past the function return. */ | |
2240 | if (in_delay_slot) | |
2241 | break; | |
a4b8ebc8 | 2242 | } |
c906108c | 2243 | |
29639122 JB |
2244 | if (this_cache != NULL) |
2245 | { | |
2246 | this_cache->base = | |
b8a22b94 DJ |
2247 | (get_frame_register_signed (this_frame, |
2248 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2249 | + frame_offset); |
2250 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2251 | this assignment below, eventually. But it's still needed | |
2252 | for now. */ | |
72a155b4 UW |
2253 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2254 | + mips_regnum (gdbarch)->pc] | |
2255 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2256 | + MIPS_RA_REGNUM]; |
29639122 | 2257 | } |
c906108c | 2258 | |
29639122 JB |
2259 | /* If we didn't reach the end of the prologue when scanning the function |
2260 | instructions, then set end_prologue_addr to the address of the | |
2261 | instruction immediately after the last one we scanned. */ | |
2262 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2263 | we may as well be careful and do our best if we have a null | |
2264 | end_prologue_addr. */ | |
2265 | if (end_prologue_addr == 0) | |
2266 | end_prologue_addr = cur_pc; | |
2267 | ||
2268 | /* In a frameless function, we might have incorrectly | |
025bb325 | 2269 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
2270 | if the load immediate was not followed by a stack adjustment. */ |
2271 | if (load_immediate_bytes && !seen_sp_adjust) | |
2272 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2273 | |
29639122 | 2274 | return end_prologue_addr; |
c906108c SS |
2275 | } |
2276 | ||
29639122 JB |
2277 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2278 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2279 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2280 | unwinder. */ | |
c906108c | 2281 | |
29639122 | 2282 | static struct mips_frame_cache * |
b8a22b94 | 2283 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2284 | { |
e17a4113 | 2285 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2286 | struct mips_frame_cache *cache; |
c906108c | 2287 | |
29639122 JB |
2288 | if ((*this_cache) != NULL) |
2289 | return (*this_cache); | |
c5aa993b | 2290 | |
29639122 JB |
2291 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2292 | (*this_cache) = cache; | |
b8a22b94 | 2293 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2294 | |
29639122 JB |
2295 | /* Analyze the function prologue. */ |
2296 | { | |
b8a22b94 | 2297 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2298 | CORE_ADDR start_addr; |
c906108c | 2299 | |
29639122 JB |
2300 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2301 | if (start_addr == 0) | |
e17a4113 | 2302 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2303 | /* We can't analyze the prologue if we couldn't find the begining |
2304 | of the function. */ | |
2305 | if (start_addr == 0) | |
2306 | return cache; | |
c5aa993b | 2307 | |
e17a4113 | 2308 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2309 | } |
2310 | ||
3e8c568d | 2311 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2312 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2313 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2314 | cache->base); |
c5aa993b | 2315 | |
29639122 | 2316 | return (*this_cache); |
c906108c SS |
2317 | } |
2318 | ||
29639122 | 2319 | static void |
b8a22b94 | 2320 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2321 | struct frame_id *this_id) |
c906108c | 2322 | { |
b8a22b94 | 2323 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2324 | this_cache); |
21327321 DJ |
2325 | /* This marks the outermost frame. */ |
2326 | if (info->base == 0) | |
2327 | return; | |
b8a22b94 | 2328 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2329 | } |
c906108c | 2330 | |
b8a22b94 DJ |
2331 | static struct value * |
2332 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2333 | void **this_cache, int regnum) | |
29639122 | 2334 | { |
b8a22b94 | 2335 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2336 | this_cache); |
b8a22b94 DJ |
2337 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2338 | } | |
2339 | ||
2340 | static int | |
2341 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2342 | struct frame_info *this_frame, void **this_cache) | |
2343 | { | |
2344 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2345 | if (! mips_pc_is_mips16 (pc)) | |
2346 | return 1; | |
2347 | return 0; | |
c906108c SS |
2348 | } |
2349 | ||
29639122 JB |
2350 | static const struct frame_unwind mips_insn32_frame_unwind = |
2351 | { | |
2352 | NORMAL_FRAME, | |
8fbca658 | 2353 | default_frame_unwind_stop_reason, |
29639122 | 2354 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
2355 | mips_insn32_frame_prev_register, |
2356 | NULL, | |
2357 | mips_insn32_frame_sniffer | |
29639122 | 2358 | }; |
c906108c | 2359 | |
1c645fec | 2360 | static CORE_ADDR |
b8a22b94 | 2361 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2362 | void **this_cache) |
c906108c | 2363 | { |
b8a22b94 | 2364 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2365 | this_cache); |
2366 | return info->base; | |
2367 | } | |
c906108c | 2368 | |
29639122 JB |
2369 | static const struct frame_base mips_insn32_frame_base = |
2370 | { | |
2371 | &mips_insn32_frame_unwind, | |
2372 | mips_insn32_frame_base_address, | |
2373 | mips_insn32_frame_base_address, | |
2374 | mips_insn32_frame_base_address | |
2375 | }; | |
1c645fec | 2376 | |
29639122 | 2377 | static const struct frame_base * |
b8a22b94 | 2378 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2379 | { |
b8a22b94 DJ |
2380 | CORE_ADDR pc = get_frame_pc (this_frame); |
2381 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2382 | return &mips_insn32_frame_base; |
a65bbe44 | 2383 | else |
29639122 JB |
2384 | return NULL; |
2385 | } | |
a65bbe44 | 2386 | |
29639122 | 2387 | static struct trad_frame_cache * |
b8a22b94 | 2388 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2389 | { |
2390 | CORE_ADDR pc; | |
2391 | CORE_ADDR start_addr; | |
2392 | CORE_ADDR stack_addr; | |
2393 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2394 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2395 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2396 | |
29639122 JB |
2397 | if ((*this_cache) != NULL) |
2398 | return (*this_cache); | |
b8a22b94 | 2399 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2400 | (*this_cache) = this_trad_cache; |
1c645fec | 2401 | |
29639122 | 2402 | /* The return address is in the link register. */ |
3e8c568d | 2403 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2404 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2405 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2406 | |
29639122 JB |
2407 | /* Frame ID, since it's a frameless / stackless function, no stack |
2408 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2409 | pc = get_frame_pc (this_frame); |
29639122 | 2410 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2411 | stack_addr = get_frame_register_signed (this_frame, |
2412 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2413 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2414 | |
29639122 JB |
2415 | /* Assume that the frame's base is the same as the |
2416 | stack-pointer. */ | |
2417 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2418 | |
29639122 JB |
2419 | return this_trad_cache; |
2420 | } | |
c906108c | 2421 | |
29639122 | 2422 | static void |
b8a22b94 | 2423 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2424 | struct frame_id *this_id) |
2425 | { | |
2426 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2427 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2428 | trad_frame_get_id (this_trad_cache, this_id); |
2429 | } | |
c906108c | 2430 | |
b8a22b94 DJ |
2431 | static struct value * |
2432 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2433 | void **this_cache, int regnum) | |
29639122 JB |
2434 | { |
2435 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2436 | = mips_stub_frame_cache (this_frame, this_cache); |
2437 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2438 | } |
c906108c | 2439 | |
b8a22b94 DJ |
2440 | static int |
2441 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2442 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2443 | { |
aa6c981f | 2444 | gdb_byte dummy[4]; |
979b38e0 | 2445 | struct obj_section *s; |
b8a22b94 | 2446 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2447 | struct minimal_symbol *msym; |
979b38e0 | 2448 | |
aa6c981f | 2449 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2450 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2451 | return 1; | |
aa6c981f | 2452 | |
29639122 | 2453 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2454 | return 1; |
979b38e0 DJ |
2455 | |
2456 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2457 | s = find_pc_section (pc); | |
2458 | ||
2459 | if (s != NULL | |
2460 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2461 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2462 | return 1; |
979b38e0 | 2463 | |
db5f024e DJ |
2464 | /* Calling a PIC function from a non-PIC function passes through a |
2465 | stub. The stub for foo is named ".pic.foo". */ | |
2466 | msym = lookup_minimal_symbol_by_pc (pc); | |
2467 | if (msym != NULL | |
2468 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2469 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2470 | return 1; | |
2471 | ||
b8a22b94 | 2472 | return 0; |
29639122 | 2473 | } |
c906108c | 2474 | |
b8a22b94 DJ |
2475 | static const struct frame_unwind mips_stub_frame_unwind = |
2476 | { | |
2477 | NORMAL_FRAME, | |
8fbca658 | 2478 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
2479 | mips_stub_frame_this_id, |
2480 | mips_stub_frame_prev_register, | |
2481 | NULL, | |
2482 | mips_stub_frame_sniffer | |
2483 | }; | |
2484 | ||
29639122 | 2485 | static CORE_ADDR |
b8a22b94 | 2486 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2487 | void **this_cache) |
2488 | { | |
2489 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2490 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2491 | return trad_frame_get_this_base (this_trad_cache); |
2492 | } | |
0fce0821 | 2493 | |
29639122 JB |
2494 | static const struct frame_base mips_stub_frame_base = |
2495 | { | |
2496 | &mips_stub_frame_unwind, | |
2497 | mips_stub_frame_base_address, | |
2498 | mips_stub_frame_base_address, | |
2499 | mips_stub_frame_base_address | |
2500 | }; | |
2501 | ||
2502 | static const struct frame_base * | |
b8a22b94 | 2503 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2504 | { |
b8a22b94 | 2505 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2506 | return &mips_stub_frame_base; |
2507 | else | |
2508 | return NULL; | |
2509 | } | |
2510 | ||
29639122 | 2511 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2512 | |
29639122 | 2513 | static CORE_ADDR |
24568a2c | 2514 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2515 | { |
24568a2c | 2516 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 KB |
2517 | |
2518 | if (is_mips16_addr (addr)) | |
2519 | addr = unmake_mips16_addr (addr); | |
2520 | ||
29639122 JB |
2521 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2522 | /* This hack is a work-around for existing boards using PMON, the | |
2523 | simulator, and any other 64-bit targets that doesn't have true | |
2524 | 64-bit addressing. On these targets, the upper 32 bits of | |
2525 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2526 | likely to have been sign extended to all 1s by instruction | |
2527 | sequences that load 32-bit addresses. For example, a typical | |
2528 | piece of code that loads an address is this: | |
65596487 | 2529 | |
29639122 JB |
2530 | lui $r2, <upper 16 bits> |
2531 | ori $r2, <lower 16 bits> | |
65596487 | 2532 | |
29639122 JB |
2533 | But the lui sign-extends the value such that the upper 32 bits |
2534 | may be all 1s. The workaround is simply to mask off these | |
2535 | bits. In the future, gcc may be changed to support true 64-bit | |
2536 | addressing, and this masking will have to be disabled. */ | |
2537 | return addr &= 0xffffffffUL; | |
2538 | else | |
2539 | return addr; | |
65596487 JB |
2540 | } |
2541 | ||
3d5f6d12 DJ |
2542 | /* Instructions used during single-stepping of atomic sequences. */ |
2543 | #define LL_OPCODE 0x30 | |
2544 | #define LLD_OPCODE 0x34 | |
2545 | #define SC_OPCODE 0x38 | |
2546 | #define SCD_OPCODE 0x3c | |
2547 | ||
2548 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2549 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2550 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2551 | the sequence. */ | |
2552 | ||
2553 | static int | |
6c95b8df PA |
2554 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2555 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
2556 | { |
2557 | CORE_ADDR breaks[2] = {-1, -1}; | |
2558 | CORE_ADDR loc = pc; | |
2559 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2560 | unsigned long insn; | |
2561 | int insn_count; | |
2562 | int index; | |
2563 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2564 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2565 | ||
2566 | if (pc & 0x01) | |
2567 | return 0; | |
2568 | ||
e17a4113 | 2569 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2570 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2571 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2572 | return 0; | |
2573 | ||
2574 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2575 | instructions. */ | |
2576 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2577 | { | |
2578 | int is_branch = 0; | |
2579 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2580 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2581 | |
2582 | /* Assume that there is at most one branch in the atomic | |
2583 | sequence. If a branch is found, put a breakpoint in its | |
2584 | destination address. */ | |
2585 | switch (itype_op (insn)) | |
2586 | { | |
2587 | case 0: /* SPECIAL */ | |
2588 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 2589 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2590 | break; |
2591 | case 1: /* REGIMM */ | |
754d7c78 | 2592 | is_branch = ((itype_rt (insn) & 0xc) == 0); /* B{LT,GE}Z* */ |
3d5f6d12 DJ |
2593 | break; |
2594 | case 2: /* J */ | |
2595 | case 3: /* JAL */ | |
025bb325 | 2596 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2597 | case 4: /* BEQ */ |
2598 | case 5: /* BNE */ | |
2599 | case 6: /* BLEZ */ | |
2600 | case 7: /* BGTZ */ | |
2601 | case 20: /* BEQL */ | |
2602 | case 21: /* BNEL */ | |
2603 | case 22: /* BLEZL */ | |
2604 | case 23: /* BGTTL */ | |
2605 | is_branch = 1; | |
2606 | break; | |
2607 | case 17: /* COP1 */ | |
2608 | case 18: /* COP2 */ | |
2609 | case 19: /* COP3 */ | |
2610 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2611 | break; | |
2612 | } | |
2613 | if (is_branch) | |
2614 | { | |
2615 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2616 | if (last_breakpoint >= 1) | |
2617 | return 0; /* More than one branch found, fallback to the | |
2618 | standard single-step code. */ | |
2619 | breaks[1] = branch_bp; | |
2620 | last_breakpoint++; | |
2621 | } | |
2622 | ||
2623 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2624 | break; | |
2625 | } | |
2626 | ||
2627 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2628 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2629 | return 0; | |
2630 | ||
2631 | loc += MIPS_INSN32_SIZE; | |
2632 | ||
2633 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2634 | breaks[0] = loc; | |
2635 | ||
2636 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 2637 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
2638 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
2639 | last_breakpoint = 0; | |
2640 | ||
2641 | /* Effectively inserts the breakpoints. */ | |
2642 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 2643 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
2644 | |
2645 | return 1; | |
2646 | } | |
2647 | ||
29639122 JB |
2648 | /* mips_software_single_step() is called just before we want to resume |
2649 | the inferior, if we want to single-step it but there is no hardware | |
2650 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2651 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2652 | |
e6590a1b | 2653 | int |
0b1b3e42 | 2654 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2655 | { |
a6d9a66e | 2656 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2657 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 2658 | CORE_ADDR pc, next_pc; |
65596487 | 2659 | |
0b1b3e42 | 2660 | pc = get_frame_pc (frame); |
6c95b8df | 2661 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
2662 | return 1; |
2663 | ||
0b1b3e42 | 2664 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2665 | |
6c95b8df | 2666 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 2667 | return 1; |
29639122 | 2668 | } |
a65bbe44 | 2669 | |
29639122 | 2670 | /* Test whether the PC points to the return instruction at the |
025bb325 | 2671 | end of a function. */ |
65596487 | 2672 | |
29639122 | 2673 | static int |
e17a4113 | 2674 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2675 | { |
0fe7e7c8 | 2676 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2677 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2678 | generates a "jr $ra"; other times it generates code to load | |
2679 | the return address from the stack to an accessible register (such | |
2680 | as $a3), then a "jr" using that register. This second case | |
2681 | is almost impossible to distinguish from an indirect jump | |
2682 | used for switch statements, so we don't even try. */ | |
e17a4113 | 2683 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
29639122 | 2684 | else |
e17a4113 | 2685 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
29639122 | 2686 | } |
c906108c | 2687 | |
c906108c | 2688 | |
29639122 JB |
2689 | /* This fencepost looks highly suspicious to me. Removing it also |
2690 | seems suspicious as it could affect remote debugging across serial | |
2691 | lines. */ | |
c906108c | 2692 | |
29639122 | 2693 | static CORE_ADDR |
74ed0bb4 | 2694 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2695 | { |
2696 | CORE_ADDR start_pc; | |
2697 | CORE_ADDR fence; | |
2698 | int instlen; | |
2699 | int seen_adjsp = 0; | |
d6b48e9c | 2700 | struct inferior *inf; |
65596487 | 2701 | |
74ed0bb4 | 2702 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2703 | start_pc = pc; |
2704 | fence = start_pc - heuristic_fence_post; | |
2705 | if (start_pc == 0) | |
2706 | return 0; | |
65596487 | 2707 | |
29639122 JB |
2708 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2709 | fence = VM_MIN_ADDRESS; | |
65596487 | 2710 | |
95ac2dcf | 2711 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2712 | |
d6b48e9c PA |
2713 | inf = current_inferior (); |
2714 | ||
025bb325 | 2715 | /* Search back for previous return. */ |
29639122 JB |
2716 | for (start_pc -= instlen;; start_pc -= instlen) |
2717 | if (start_pc < fence) | |
2718 | { | |
2719 | /* It's not clear to me why we reach this point when | |
2720 | stop_soon, but with this test, at least we | |
2721 | don't print out warnings for every child forked (eg, on | |
2722 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 2723 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2724 | { |
2725 | static int blurb_printed = 0; | |
98b4dd94 | 2726 | |
5af949e3 UW |
2727 | warning (_("GDB can't find the start of the function at %s."), |
2728 | paddress (gdbarch, pc)); | |
29639122 JB |
2729 | |
2730 | if (!blurb_printed) | |
2731 | { | |
2732 | /* This actually happens frequently in embedded | |
2733 | development, when you first connect to a board | |
2734 | and your stack pointer and pc are nowhere in | |
2735 | particular. This message needs to give people | |
2736 | in that situation enough information to | |
2737 | determine that it's no big deal. */ | |
2738 | printf_filtered ("\n\ | |
5af949e3 | 2739 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2740 | and thus can't determine the size of that function's stack frame.\n\ |
2741 | This means that GDB may be unable to access that stack frame, or\n\ | |
2742 | the frames below it.\n\ | |
2743 | This problem is most likely caused by an invalid program counter or\n\ | |
2744 | stack pointer.\n\ | |
2745 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2746 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2747 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2748 | heuristic-fence-post' command.\n", |
2749 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2750 | blurb_printed = 1; |
2751 | } | |
2752 | } | |
2753 | ||
2754 | return 0; | |
2755 | } | |
0fe7e7c8 | 2756 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2757 | { |
2758 | unsigned short inst; | |
2759 | ||
2760 | /* On MIPS16, any one of the following is likely to be the | |
2761 | start of a function: | |
193774b3 MR |
2762 | extend save |
2763 | save | |
29639122 JB |
2764 | entry |
2765 | addiu sp,-n | |
2766 | daddiu sp,-n | |
025bb325 | 2767 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
e17a4113 | 2768 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2769 | if ((inst & 0xff80) == 0x6480) /* save */ |
2770 | { | |
2771 | if (start_pc - instlen >= fence) | |
2772 | { | |
e17a4113 | 2773 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2774 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2775 | start_pc -= instlen; | |
2776 | } | |
2777 | break; | |
2778 | } | |
2779 | else if (((inst & 0xf81f) == 0xe809 | |
2780 | && (inst & 0x700) != 0x700) /* entry */ | |
2781 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2782 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2783 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2784 | break; |
2785 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2786 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2787 | seen_adjsp = 1; | |
2788 | else | |
2789 | seen_adjsp = 0; | |
2790 | } | |
e17a4113 | 2791 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2792 | { |
4c7d22cb | 2793 | /* Skip return and its delay slot. */ |
95ac2dcf | 2794 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2795 | break; |
2796 | } | |
2797 | ||
2798 | return start_pc; | |
c906108c SS |
2799 | } |
2800 | ||
6c0d6680 DJ |
2801 | struct mips_objfile_private |
2802 | { | |
2803 | bfd_size_type size; | |
2804 | char *contents; | |
2805 | }; | |
2806 | ||
f09ded24 AC |
2807 | /* According to the current ABI, should the type be passed in a |
2808 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2809 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 2810 | FP registers and, consequently this returns false - forces FP |
025bb325 | 2811 | arguments into integer registers. */ |
f09ded24 AC |
2812 | |
2813 | static int | |
74ed0bb4 MD |
2814 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2815 | struct type *arg_type) | |
f09ded24 AC |
2816 | { |
2817 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2818 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2819 | && (typecode == TYPE_CODE_STRUCT |
2820 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2821 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2822 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2823 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2824 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2825 | } |
2826 | ||
49e790b0 | 2827 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 2828 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
2829 | |
2830 | static int | |
2831 | mips_type_needs_double_align (struct type *type) | |
2832 | { | |
2833 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2834 | |
49e790b0 DJ |
2835 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2836 | return 1; | |
2837 | else if (typecode == TYPE_CODE_STRUCT) | |
2838 | { | |
2839 | if (TYPE_NFIELDS (type) < 1) | |
2840 | return 0; | |
2841 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2842 | } | |
2843 | else if (typecode == TYPE_CODE_UNION) | |
2844 | { | |
361d1df0 | 2845 | int i, n; |
49e790b0 DJ |
2846 | |
2847 | n = TYPE_NFIELDS (type); | |
2848 | for (i = 0; i < n; i++) | |
2849 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2850 | return 1; | |
2851 | return 0; | |
2852 | } | |
2853 | return 0; | |
2854 | } | |
2855 | ||
dc604539 AC |
2856 | /* Adjust the address downward (direction of stack growth) so that it |
2857 | is correctly aligned for a new stack frame. */ | |
2858 | static CORE_ADDR | |
2859 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2860 | { | |
5b03f266 | 2861 | return align_down (addr, 16); |
dc604539 AC |
2862 | } |
2863 | ||
f7ab6ec6 | 2864 | static CORE_ADDR |
7d9b040b | 2865 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2866 | struct regcache *regcache, CORE_ADDR bp_addr, |
2867 | int nargs, struct value **args, CORE_ADDR sp, | |
2868 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2869 | { |
2870 | int argreg; | |
2871 | int float_argreg; | |
2872 | int argnum; | |
2873 | int len = 0; | |
2874 | int stack_offset = 0; | |
480d3dd2 | 2875 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 2876 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 2877 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2878 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2879 | |
25ab4790 AC |
2880 | /* For shared libraries, "t9" needs to point at the function |
2881 | address. */ | |
4c7d22cb | 2882 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2883 | |
2884 | /* Set the return address register to point to the entry point of | |
2885 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2886 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2887 | |
c906108c | 2888 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2889 | are properly aligned. The stack has to be at least 64-bit |
2890 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2891 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2892 | aligned, so we round to this widest known alignment. */ | |
2893 | ||
5b03f266 AC |
2894 | sp = align_down (sp, 16); |
2895 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2896 | |
46e0f506 | 2897 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2898 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2899 | passed in registers, but that's OK. */ |
c906108c | 2900 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2901 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2902 | sp -= align_up (len, 16); |
c906108c | 2903 | |
9ace0497 | 2904 | if (mips_debug) |
6d82d43b | 2905 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2906 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2907 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2908 | |
c906108c | 2909 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2910 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2911 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2912 | |
46e0f506 | 2913 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2914 | if (struct_return) |
9ace0497 AC |
2915 | { |
2916 | if (mips_debug) | |
2917 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
2918 | "mips_eabi_push_dummy_call: " |
2919 | "struct_return reg=%d %s\n", | |
5af949e3 | 2920 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 2921 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2922 | } |
c906108c SS |
2923 | |
2924 | /* Now load as many as possible of the first arguments into | |
2925 | registers, and push the rest onto the stack. Loop thru args | |
2926 | from first to last. */ | |
2927 | for (argnum = 0; argnum < nargs; argnum++) | |
2928 | { | |
47a35522 MK |
2929 | const gdb_byte *val; |
2930 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2931 | struct value *arg = args[argnum]; |
4991999e | 2932 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2933 | int len = TYPE_LENGTH (arg_type); |
2934 | enum type_code typecode = TYPE_CODE (arg_type); | |
2935 | ||
9ace0497 AC |
2936 | if (mips_debug) |
2937 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2938 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2939 | argnum + 1, len, (int) typecode); |
9ace0497 | 2940 | |
930bd0e0 KB |
2941 | /* Function pointer arguments to mips16 code need to be made into |
2942 | mips16 pointers. */ | |
2943 | if (typecode == TYPE_CODE_PTR | |
2944 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
2945 | { | |
2946 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
2947 | len, byte_order); | |
2948 | if (mips_pc_is_mips16 (addr)) | |
2949 | { | |
2950 | store_signed_integer (valbuf, len, byte_order, | |
2951 | make_mips16_addr (addr)); | |
2952 | val = valbuf; | |
2953 | } | |
2954 | else | |
2955 | val = value_contents (arg); | |
2956 | } | |
c906108c | 2957 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2958 | reference. */ |
930bd0e0 | 2959 | else if (len > regsize |
9ace0497 | 2960 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2961 | { |
e17a4113 UW |
2962 | store_unsigned_integer (valbuf, regsize, byte_order, |
2963 | value_address (arg)); | |
c906108c | 2964 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2965 | len = regsize; |
c906108c | 2966 | val = valbuf; |
9ace0497 AC |
2967 | if (mips_debug) |
2968 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2969 | } |
2970 | else | |
47a35522 | 2971 | val = value_contents (arg); |
c906108c SS |
2972 | |
2973 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2974 | even-numbered floating point register. Round the FP register |
2975 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2976 | left. Non MIPS_EABI targets also pass the FP in the integer |
2977 | registers so also round up normal registers. */ | |
74ed0bb4 | 2978 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
2979 | { |
2980 | if ((float_argreg & 1)) | |
2981 | float_argreg++; | |
2982 | } | |
c906108c SS |
2983 | |
2984 | /* Floating point arguments passed in registers have to be | |
2985 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2986 | are passed in register pairs; the even register gets |
2987 | the low word, and the odd register gets the high word. | |
2988 | On non-EABI processors, the first two floating point arguments are | |
2989 | also copied to general registers, because MIPS16 functions | |
2990 | don't use float registers for arguments. This duplication of | |
2991 | arguments in general registers can't hurt non-MIPS16 functions | |
2992 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2993 | /* MIPS_EABI squeezes a struct that contains a single floating |
2994 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2995 | stack. */ |
74ed0bb4 MD |
2996 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
2997 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 2998 | { |
6da397e0 KB |
2999 | /* EABI32 will pass doubles in consecutive registers, even on |
3000 | 64-bit cores. At one time, we used to check the size of | |
3001 | `float_argreg' to determine whether or not to pass doubles | |
3002 | in consecutive registers, but this is not sufficient for | |
3003 | making the ABI determination. */ | |
3004 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 3005 | { |
72a155b4 | 3006 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3007 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 3008 | long regval; |
c906108c SS |
3009 | |
3010 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
3011 | regval = extract_signed_integer (val + low_offset, |
3012 | 4, byte_order); | |
9ace0497 | 3013 | if (mips_debug) |
acdb74a0 | 3014 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3015 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3016 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3017 | |
3018 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
3019 | regval = extract_signed_integer (val + 4 - low_offset, |
3020 | 4, byte_order); | |
9ace0497 | 3021 | if (mips_debug) |
acdb74a0 | 3022 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3023 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3024 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3025 | } |
3026 | else | |
3027 | { | |
3028 | /* This is a floating point value that fits entirely | |
3029 | in a single register. */ | |
53a5351d | 3030 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3031 | above to ensure that it is even register aligned. */ |
a8852dc5 | 3032 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 3033 | if (mips_debug) |
acdb74a0 | 3034 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3035 | float_argreg, phex (regval, len)); |
a8852dc5 | 3036 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3037 | } |
3038 | } | |
3039 | else | |
3040 | { | |
3041 | /* Copy the argument to general registers or the stack in | |
3042 | register-sized pieces. Large arguments are split between | |
3043 | registers and stack. */ | |
1a69e1e4 DJ |
3044 | /* Note: structs whose size is not a multiple of regsize |
3045 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3046 | them in registers where gcc sometimes puts them on the |
3047 | stack. For maximum compatibility, we will put them in | |
3048 | both places. */ | |
1a69e1e4 | 3049 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 3050 | |
f09ded24 | 3051 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3052 | register are only written to memory. */ |
c906108c SS |
3053 | while (len > 0) |
3054 | { | |
ebafbe83 | 3055 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3056 | int stack_used_p = 0; |
1a69e1e4 | 3057 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 3058 | |
acdb74a0 AC |
3059 | if (mips_debug) |
3060 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3061 | partial_len); | |
3062 | ||
566f0f7a | 3063 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3064 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 3065 | || odd_sized_struct |
74ed0bb4 | 3066 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 3067 | { |
c906108c | 3068 | /* Should shorter than int integer values be |
025bb325 | 3069 | promoted to int before being stored? */ |
c906108c | 3070 | int longword_offset = 0; |
9ace0497 | 3071 | CORE_ADDR addr; |
566f0f7a | 3072 | stack_used_p = 1; |
72a155b4 | 3073 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 3074 | { |
1a69e1e4 | 3075 | if (regsize == 8 |
480d3dd2 AC |
3076 | && (typecode == TYPE_CODE_INT |
3077 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3078 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 3079 | longword_offset = regsize - len; |
480d3dd2 AC |
3080 | else if ((typecode == TYPE_CODE_STRUCT |
3081 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
3082 | && TYPE_LENGTH (arg_type) < regsize) |
3083 | longword_offset = regsize - len; | |
7a292a7a | 3084 | } |
c5aa993b | 3085 | |
9ace0497 AC |
3086 | if (mips_debug) |
3087 | { | |
5af949e3 UW |
3088 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3089 | paddress (gdbarch, stack_offset)); | |
3090 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3091 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 3092 | } |
361d1df0 | 3093 | |
9ace0497 AC |
3094 | addr = sp + stack_offset + longword_offset; |
3095 | ||
3096 | if (mips_debug) | |
3097 | { | |
3098 | int i; | |
5af949e3 UW |
3099 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3100 | paddress (gdbarch, addr)); | |
9ace0497 AC |
3101 | for (i = 0; i < partial_len; i++) |
3102 | { | |
6d82d43b | 3103 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3104 | val[i] & 0xff); |
9ace0497 AC |
3105 | } |
3106 | } | |
3107 | write_memory (addr, val, partial_len); | |
c906108c SS |
3108 | } |
3109 | ||
f09ded24 AC |
3110 | /* Note!!! This is NOT an else clause. Odd sized |
3111 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3112 | arguments will not. */ |
566f0f7a | 3113 | /* Write this portion of the argument to a general |
6d82d43b | 3114 | purpose register. */ |
74ed0bb4 MD |
3115 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
3116 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 3117 | { |
6d82d43b | 3118 | LONGEST regval = |
a8852dc5 | 3119 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 3120 | |
9ace0497 | 3121 | if (mips_debug) |
acdb74a0 | 3122 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3123 | argreg, |
1a69e1e4 | 3124 | phex (regval, regsize)); |
a8852dc5 | 3125 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 3126 | argreg++; |
c906108c | 3127 | } |
c5aa993b | 3128 | |
c906108c SS |
3129 | len -= partial_len; |
3130 | val += partial_len; | |
3131 | ||
b021a221 MS |
3132 | /* Compute the offset into the stack at which we will |
3133 | copy the next parameter. | |
566f0f7a | 3134 | |
566f0f7a | 3135 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3136 | only needs to be adjusted when it has been used. */ |
c906108c | 3137 | |
46e0f506 | 3138 | if (stack_used_p) |
1a69e1e4 | 3139 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
3140 | } |
3141 | } | |
9ace0497 AC |
3142 | if (mips_debug) |
3143 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3144 | } |
3145 | ||
f10683bb | 3146 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3147 | |
0f71a2f6 JM |
3148 | /* Return adjusted stack pointer. */ |
3149 | return sp; | |
3150 | } | |
3151 | ||
a1f5b845 | 3152 | /* Determine the return value convention being used. */ |
6d82d43b | 3153 | |
9c8fdbfa | 3154 | static enum return_value_convention |
c055b101 | 3155 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 3156 | struct type *type, struct regcache *regcache, |
47a35522 | 3157 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3158 | { |
609ba780 JM |
3159 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3160 | int fp_return_type = 0; | |
3161 | int offset, regnum, xfer; | |
3162 | ||
9c8fdbfa AC |
3163 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3164 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
3165 | |
3166 | /* Floating point type? */ | |
3167 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3168 | { | |
3169 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
3170 | fp_return_type = 1; | |
3171 | /* Structs with a single field of float type | |
3172 | are returned in a floating point register. */ | |
3173 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3174 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3175 | && TYPE_NFIELDS (type) == 1) | |
3176 | { | |
3177 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
3178 | ||
3179 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
3180 | fp_return_type = 1; | |
3181 | } | |
3182 | } | |
3183 | ||
3184 | if (fp_return_type) | |
3185 | { | |
3186 | /* A floating-point value belongs in the least significant part | |
3187 | of FP0/FP1. */ | |
3188 | if (mips_debug) | |
3189 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3190 | regnum = mips_regnum (gdbarch)->fp0; | |
3191 | } | |
3192 | else | |
3193 | { | |
3194 | /* An integer value goes in V0/V1. */ | |
3195 | if (mips_debug) | |
3196 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3197 | regnum = MIPS_V0_REGNUM; | |
3198 | } | |
3199 | for (offset = 0; | |
3200 | offset < TYPE_LENGTH (type); | |
3201 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3202 | { | |
3203 | xfer = mips_abi_regsize (gdbarch); | |
3204 | if (offset + xfer > TYPE_LENGTH (type)) | |
3205 | xfer = TYPE_LENGTH (type) - offset; | |
3206 | mips_xfer_register (gdbarch, regcache, | |
3207 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3208 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3209 | offset); | |
3210 | } | |
3211 | ||
9c8fdbfa | 3212 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3213 | } |
3214 | ||
6d82d43b AC |
3215 | |
3216 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3217 | |
8d26208a DJ |
3218 | /* Search for a naturally aligned double at OFFSET inside a struct |
3219 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3220 | registers. */ | |
3221 | ||
3222 | static int | |
74ed0bb4 MD |
3223 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3224 | int offset) | |
8d26208a DJ |
3225 | { |
3226 | int i; | |
3227 | ||
3228 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3229 | return 0; | |
3230 | ||
74ed0bb4 | 3231 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3232 | return 0; |
3233 | ||
3234 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3235 | return 0; | |
3236 | ||
3237 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3238 | { | |
3239 | int pos; | |
3240 | struct type *field_type; | |
3241 | ||
3242 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3243 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3244 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3245 | continue; | |
3246 | ||
3247 | /* If we have gone past the offset, there is no double to pass. */ | |
3248 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3249 | if (pos > offset) | |
3250 | return 0; | |
3251 | ||
3252 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3253 | ||
3254 | /* If this field is entirely before the requested offset, go | |
3255 | on to the next one. */ | |
3256 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3257 | continue; | |
3258 | ||
3259 | /* If this is our special aligned double, we can stop. */ | |
3260 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3261 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3262 | return 1; | |
3263 | ||
3264 | /* This field starts at or before the requested offset, and | |
3265 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3266 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3267 | } |
3268 | ||
3269 | return 0; | |
3270 | } | |
3271 | ||
f7ab6ec6 | 3272 | static CORE_ADDR |
7d9b040b | 3273 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3274 | struct regcache *regcache, CORE_ADDR bp_addr, |
3275 | int nargs, struct value **args, CORE_ADDR sp, | |
3276 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3277 | { |
3278 | int argreg; | |
3279 | int float_argreg; | |
3280 | int argnum; | |
3281 | int len = 0; | |
3282 | int stack_offset = 0; | |
480d3dd2 | 3283 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3284 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3285 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3286 | |
25ab4790 AC |
3287 | /* For shared libraries, "t9" needs to point at the function |
3288 | address. */ | |
4c7d22cb | 3289 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3290 | |
3291 | /* Set the return address register to point to the entry point of | |
3292 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3293 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3294 | |
cb3d25d1 MS |
3295 | /* First ensure that the stack and structure return address (if any) |
3296 | are properly aligned. The stack has to be at least 64-bit | |
3297 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3298 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3299 | aligned, so we round to this widest known alignment. */ | |
3300 | ||
5b03f266 AC |
3301 | sp = align_down (sp, 16); |
3302 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3303 | |
3304 | /* Now make space on the stack for the args. */ | |
3305 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3306 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3307 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3308 | |
3309 | if (mips_debug) | |
6d82d43b | 3310 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3311 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3312 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3313 | |
3314 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3315 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3316 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3317 | |
46e0f506 | 3318 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3319 | if (struct_return) |
3320 | { | |
3321 | if (mips_debug) | |
3322 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3323 | "mips_n32n64_push_dummy_call: " |
3324 | "struct_return reg=%d %s\n", | |
5af949e3 | 3325 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3326 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3327 | } |
3328 | ||
3329 | /* Now load as many as possible of the first arguments into | |
3330 | registers, and push the rest onto the stack. Loop thru args | |
3331 | from first to last. */ | |
3332 | for (argnum = 0; argnum < nargs; argnum++) | |
3333 | { | |
47a35522 | 3334 | const gdb_byte *val; |
cb3d25d1 | 3335 | struct value *arg = args[argnum]; |
4991999e | 3336 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3337 | int len = TYPE_LENGTH (arg_type); |
3338 | enum type_code typecode = TYPE_CODE (arg_type); | |
3339 | ||
3340 | if (mips_debug) | |
3341 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3342 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3343 | argnum + 1, len, (int) typecode); |
3344 | ||
47a35522 | 3345 | val = value_contents (arg); |
cb3d25d1 | 3346 | |
5b68030f JM |
3347 | /* A 128-bit long double value requires an even-odd pair of |
3348 | floating-point registers. */ | |
3349 | if (len == 16 | |
3350 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3351 | && (float_argreg & 1)) | |
3352 | { | |
3353 | float_argreg++; | |
3354 | argreg++; | |
3355 | } | |
3356 | ||
74ed0bb4 MD |
3357 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3358 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3359 | { |
3360 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3361 | in a single register or a pair of registers. */ |
3362 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3363 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3364 | if (mips_debug) |
3365 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3366 | float_argreg, phex (regval, reglen)); |
8d26208a | 3367 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3368 | |
3369 | if (mips_debug) | |
3370 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3371 | argreg, phex (regval, reglen)); |
9c9acae0 | 3372 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3373 | float_argreg++; |
3374 | argreg++; | |
5b68030f JM |
3375 | if (len == 16) |
3376 | { | |
e17a4113 UW |
3377 | regval = extract_unsigned_integer (val + reglen, |
3378 | reglen, byte_order); | |
5b68030f JM |
3379 | if (mips_debug) |
3380 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3381 | float_argreg, phex (regval, reglen)); | |
3382 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3383 | ||
3384 | if (mips_debug) | |
3385 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3386 | argreg, phex (regval, reglen)); | |
3387 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3388 | float_argreg++; | |
3389 | argreg++; | |
3390 | } | |
cb3d25d1 MS |
3391 | } |
3392 | else | |
3393 | { | |
3394 | /* Copy the argument to general registers or the stack in | |
3395 | register-sized pieces. Large arguments are split between | |
3396 | registers and stack. */ | |
ab2e1992 MR |
3397 | /* For N32/N64, structs, unions, or other composite types are |
3398 | treated as a sequence of doublewords, and are passed in integer | |
3399 | or floating point registers as though they were simple scalar | |
3400 | parameters to the extent that they fit, with any excess on the | |
3401 | stack packed according to the normal memory layout of the | |
3402 | object. | |
3403 | The caller does not reserve space for the register arguments; | |
3404 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3405 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3406 | register are only written to memory. */ |
cb3d25d1 MS |
3407 | while (len > 0) |
3408 | { | |
ad018eee | 3409 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3410 | int stack_used_p = 0; |
1a69e1e4 | 3411 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3412 | |
3413 | if (mips_debug) | |
3414 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3415 | partial_len); | |
3416 | ||
74ed0bb4 MD |
3417 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3418 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3419 | |
cb3d25d1 | 3420 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3421 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3422 | { |
3423 | /* Should shorter than int integer values be | |
025bb325 | 3424 | promoted to int before being stored? */ |
cb3d25d1 MS |
3425 | int longword_offset = 0; |
3426 | CORE_ADDR addr; | |
3427 | stack_used_p = 1; | |
72a155b4 | 3428 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3429 | { |
1a69e1e4 | 3430 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3431 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3432 | && len <= 4) |
3433 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3434 | } |
3435 | ||
3436 | if (mips_debug) | |
3437 | { | |
5af949e3 UW |
3438 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3439 | paddress (gdbarch, stack_offset)); | |
3440 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3441 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3442 | } |
3443 | ||
3444 | addr = sp + stack_offset + longword_offset; | |
3445 | ||
3446 | if (mips_debug) | |
3447 | { | |
3448 | int i; | |
5af949e3 UW |
3449 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3450 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3451 | for (i = 0; i < partial_len; i++) |
3452 | { | |
6d82d43b | 3453 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3454 | val[i] & 0xff); |
3455 | } | |
3456 | } | |
3457 | write_memory (addr, val, partial_len); | |
3458 | } | |
3459 | ||
3460 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3461 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3462 | /* Write this portion of the argument to a general |
6d82d43b | 3463 | purpose register. */ |
74ed0bb4 | 3464 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3465 | { |
5863b5d5 MR |
3466 | LONGEST regval; |
3467 | ||
3468 | /* Sign extend pointers, 32-bit integers and signed | |
3469 | 16-bit and 8-bit integers; everything else is taken | |
3470 | as is. */ | |
3471 | ||
3472 | if ((partial_len == 4 | |
3473 | && (typecode == TYPE_CODE_PTR | |
3474 | || typecode == TYPE_CODE_INT)) | |
3475 | || (partial_len < 4 | |
3476 | && typecode == TYPE_CODE_INT | |
3477 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3478 | regval = extract_signed_integer (val, partial_len, |
3479 | byte_order); | |
5863b5d5 | 3480 | else |
e17a4113 UW |
3481 | regval = extract_unsigned_integer (val, partial_len, |
3482 | byte_order); | |
cb3d25d1 MS |
3483 | |
3484 | /* A non-floating-point argument being passed in a | |
3485 | general register. If a struct or union, and if | |
3486 | the remaining length is smaller than the register | |
3487 | size, we have to adjust the register value on | |
3488 | big endian targets. | |
3489 | ||
3490 | It does not seem to be necessary to do the | |
1a69e1e4 | 3491 | same for integral types. */ |
cb3d25d1 | 3492 | |
72a155b4 | 3493 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3494 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3495 | && (typecode == TYPE_CODE_STRUCT |
3496 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3497 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3498 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3499 | |
3500 | if (mips_debug) | |
3501 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3502 | argreg, | |
1a69e1e4 | 3503 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3504 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3505 | |
74ed0bb4 | 3506 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3507 | TYPE_LENGTH (arg_type) - len)) |
3508 | { | |
3509 | if (mips_debug) | |
3510 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3511 | float_argreg, | |
3512 | phex (regval, MIPS64_REGSIZE)); | |
3513 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3514 | regval); | |
3515 | } | |
3516 | ||
3517 | float_argreg++; | |
cb3d25d1 MS |
3518 | argreg++; |
3519 | } | |
3520 | ||
3521 | len -= partial_len; | |
3522 | val += partial_len; | |
3523 | ||
b021a221 MS |
3524 | /* Compute the offset into the stack at which we will |
3525 | copy the next parameter. | |
cb3d25d1 MS |
3526 | |
3527 | In N32 (N64?), the stack_offset only needs to be | |
3528 | adjusted when it has been used. */ | |
3529 | ||
3530 | if (stack_used_p) | |
1a69e1e4 | 3531 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3532 | } |
3533 | } | |
3534 | if (mips_debug) | |
3535 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3536 | } | |
3537 | ||
f10683bb | 3538 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3539 | |
cb3d25d1 MS |
3540 | /* Return adjusted stack pointer. */ |
3541 | return sp; | |
3542 | } | |
3543 | ||
6d82d43b | 3544 | static enum return_value_convention |
c055b101 | 3545 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3546 | struct type *type, struct regcache *regcache, |
47a35522 | 3547 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3548 | { |
72a155b4 | 3549 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3550 | |
3551 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3552 | ||
3553 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3554 | if needed), as appropriate for the type. Composite results (struct, | |
3555 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3556 | following rules: | |
3557 | ||
3558 | * A struct with only one or two floating point fields is returned in $f0 | |
3559 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3560 | case. | |
3561 | ||
f08877ba | 3562 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
3563 | $2 (first 64 bits) and $3 (remainder, if necessary). |
3564 | ||
3565 | * Larger composite results are handled by converting the function to a | |
3566 | procedure with an implicit first parameter, which is a pointer to an area | |
3567 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3568 | that all composite results be handled by conversion to implicit first | |
3569 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3570 | specific exception to return COMPLEX results in the floating point | |
3571 | registers.] */ | |
3572 | ||
f08877ba | 3573 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3574 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3575 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3576 | && TYPE_LENGTH (type) == 16 | |
3577 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3578 | { | |
3579 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3580 | two registers are used in the same as memory order, so the | |
3581 | eight bytes with the lower memory address are in $f0. */ | |
3582 | if (mips_debug) | |
3583 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3584 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3585 | gdbarch_num_regs (gdbarch) |
3586 | + mips_regnum (gdbarch)->fp0, | |
3587 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3588 | readbuf, writebuf, 0); |
ba32f989 | 3589 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3590 | gdbarch_num_regs (gdbarch) |
3591 | + mips_regnum (gdbarch)->fp0 + 2, | |
3592 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3593 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3594 | writebuf ? writebuf + 8 : writebuf, 0); |
3595 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3596 | } | |
6d82d43b AC |
3597 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3598 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3599 | { | |
59aa1faa | 3600 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3601 | if (mips_debug) |
3602 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3603 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3604 | gdbarch_num_regs (gdbarch) |
3605 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3606 | TYPE_LENGTH (type), |
72a155b4 | 3607 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3608 | readbuf, writebuf, 0); |
6d82d43b AC |
3609 | return RETURN_VALUE_REGISTER_CONVENTION; |
3610 | } | |
3611 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3612 | && TYPE_NFIELDS (type) <= 2 | |
3613 | && TYPE_NFIELDS (type) >= 1 | |
3614 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3615 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3616 | == TYPE_CODE_FLT)) |
3617 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3618 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3619 | == TYPE_CODE_FLT) |
b18bb924 | 3620 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3621 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3622 | { |
3623 | /* A struct that contains one or two floats. Each value is part | |
3624 | in the least significant part of their floating point | |
5b68030f | 3625 | register (or GPR, for soft float). */ |
6d82d43b AC |
3626 | int regnum; |
3627 | int field; | |
5b68030f JM |
3628 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3629 | ? mips_regnum (gdbarch)->fp0 | |
3630 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3631 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3632 | { | |
3633 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3634 | / TARGET_CHAR_BIT); | |
3635 | if (mips_debug) | |
3636 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3637 | offset); | |
5b68030f JM |
3638 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3639 | { | |
3640 | /* A 16-byte long double field goes in two consecutive | |
3641 | registers. */ | |
3642 | mips_xfer_register (gdbarch, regcache, | |
3643 | gdbarch_num_regs (gdbarch) + regnum, | |
3644 | 8, | |
3645 | gdbarch_byte_order (gdbarch), | |
3646 | readbuf, writebuf, offset); | |
3647 | mips_xfer_register (gdbarch, regcache, | |
3648 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3649 | 8, | |
3650 | gdbarch_byte_order (gdbarch), | |
3651 | readbuf, writebuf, offset + 8); | |
3652 | } | |
3653 | else | |
3654 | mips_xfer_register (gdbarch, regcache, | |
3655 | gdbarch_num_regs (gdbarch) + regnum, | |
3656 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3657 | gdbarch_byte_order (gdbarch), | |
3658 | readbuf, writebuf, offset); | |
6d82d43b AC |
3659 | } |
3660 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3661 | } | |
3662 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
3663 | || TYPE_CODE (type) == TYPE_CODE_UNION |
3664 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 3665 | { |
f08877ba | 3666 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
3667 | regardless of the byte order. I.e. DO NOT USE |
3668 | mips_xfer_lower. */ | |
3669 | int offset; | |
3670 | int regnum; | |
4c7d22cb | 3671 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3672 | offset < TYPE_LENGTH (type); |
72a155b4 | 3673 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3674 | { |
72a155b4 | 3675 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3676 | if (offset + xfer > TYPE_LENGTH (type)) |
3677 | xfer = TYPE_LENGTH (type) - offset; | |
3678 | if (mips_debug) | |
3679 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3680 | offset, xfer, regnum); | |
ba32f989 DJ |
3681 | mips_xfer_register (gdbarch, regcache, |
3682 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3683 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3684 | offset); | |
6d82d43b AC |
3685 | } |
3686 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3687 | } | |
3688 | else | |
3689 | { | |
3690 | /* A scalar extract each part but least-significant-byte | |
3691 | justified. */ | |
3692 | int offset; | |
3693 | int regnum; | |
4c7d22cb | 3694 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3695 | offset < TYPE_LENGTH (type); |
72a155b4 | 3696 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3697 | { |
72a155b4 | 3698 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3699 | if (offset + xfer > TYPE_LENGTH (type)) |
3700 | xfer = TYPE_LENGTH (type) - offset; | |
3701 | if (mips_debug) | |
3702 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3703 | offset, xfer, regnum); | |
ba32f989 DJ |
3704 | mips_xfer_register (gdbarch, regcache, |
3705 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3706 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3707 | readbuf, writebuf, offset); |
6d82d43b AC |
3708 | } |
3709 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3710 | } | |
3711 | } | |
3712 | ||
3713 | /* O32 ABI stuff. */ | |
3714 | ||
3715 | static CORE_ADDR | |
7d9b040b | 3716 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3717 | struct regcache *regcache, CORE_ADDR bp_addr, |
3718 | int nargs, struct value **args, CORE_ADDR sp, | |
3719 | int struct_return, CORE_ADDR struct_addr) | |
3720 | { | |
3721 | int argreg; | |
3722 | int float_argreg; | |
3723 | int argnum; | |
3724 | int len = 0; | |
3725 | int stack_offset = 0; | |
3726 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3727 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3728 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3729 | |
3730 | /* For shared libraries, "t9" needs to point at the function | |
3731 | address. */ | |
4c7d22cb | 3732 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3733 | |
3734 | /* Set the return address register to point to the entry point of | |
3735 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3736 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3737 | |
3738 | /* First ensure that the stack and structure return address (if any) | |
3739 | are properly aligned. The stack has to be at least 64-bit | |
3740 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3741 | aligned. For n32 and n64, stack frames need to be 128-bit |
3742 | aligned, so we round to this widest known alignment. */ | |
3743 | ||
5b03f266 AC |
3744 | sp = align_down (sp, 16); |
3745 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3746 | |
3747 | /* Now make space on the stack for the args. */ | |
3748 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3749 | { |
3750 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3751 | int arglen = TYPE_LENGTH (arg_type); | |
3752 | ||
3753 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3754 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3755 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3756 | /* Allocate space on the stack. */ |
1a69e1e4 | 3757 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3758 | } |
5b03f266 | 3759 | sp -= align_up (len, 16); |
ebafbe83 MS |
3760 | |
3761 | if (mips_debug) | |
6d82d43b | 3762 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3763 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3764 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3765 | |
3766 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3767 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3768 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3769 | |
bcb0cc15 | 3770 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3771 | if (struct_return) |
3772 | { | |
3773 | if (mips_debug) | |
3774 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3775 | "mips_o32_push_dummy_call: " |
3776 | "struct_return reg=%d %s\n", | |
5af949e3 | 3777 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3778 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3779 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3780 | } |
3781 | ||
3782 | /* Now load as many as possible of the first arguments into | |
3783 | registers, and push the rest onto the stack. Loop thru args | |
3784 | from first to last. */ | |
3785 | for (argnum = 0; argnum < nargs; argnum++) | |
3786 | { | |
47a35522 | 3787 | const gdb_byte *val; |
ebafbe83 | 3788 | struct value *arg = args[argnum]; |
4991999e | 3789 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3790 | int len = TYPE_LENGTH (arg_type); |
3791 | enum type_code typecode = TYPE_CODE (arg_type); | |
3792 | ||
3793 | if (mips_debug) | |
3794 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3795 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3796 | argnum + 1, len, (int) typecode); |
3797 | ||
47a35522 | 3798 | val = value_contents (arg); |
46cac009 AC |
3799 | |
3800 | /* 32-bit ABIs always start floating point arguments in an | |
3801 | even-numbered floating point register. Round the FP register | |
3802 | up before the check to see if there are any FP registers | |
3803 | left. O32/O64 targets also pass the FP in the integer | |
3804 | registers so also round up normal registers. */ | |
74ed0bb4 | 3805 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3806 | { |
3807 | if ((float_argreg & 1)) | |
3808 | float_argreg++; | |
3809 | } | |
3810 | ||
3811 | /* Floating point arguments passed in registers have to be | |
3812 | treated specially. On 32-bit architectures, doubles | |
3813 | are passed in register pairs; the even register gets | |
3814 | the low word, and the odd register gets the high word. | |
3815 | On O32/O64, the first two floating point arguments are | |
3816 | also copied to general registers, because MIPS16 functions | |
3817 | don't use float registers for arguments. This duplication of | |
3818 | arguments in general registers can't hurt non-MIPS16 functions | |
3819 | because those registers are normally skipped. */ | |
3820 | ||
74ed0bb4 MD |
3821 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3822 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3823 | { |
8b07f6d8 | 3824 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3825 | { |
72a155b4 | 3826 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3827 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3828 | unsigned long regval; |
3829 | ||
3830 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
3831 | regval = extract_unsigned_integer (val + low_offset, |
3832 | 4, byte_order); | |
46cac009 AC |
3833 | if (mips_debug) |
3834 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3835 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3836 | regcache_cooked_write_unsigned (regcache, |
3837 | float_argreg++, regval); | |
46cac009 AC |
3838 | if (mips_debug) |
3839 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3840 | argreg, phex (regval, 4)); | |
9c9acae0 | 3841 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3842 | |
3843 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
3844 | regval = extract_unsigned_integer (val + 4 - low_offset, |
3845 | 4, byte_order); | |
46cac009 AC |
3846 | if (mips_debug) |
3847 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3848 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3849 | regcache_cooked_write_unsigned (regcache, |
3850 | float_argreg++, regval); | |
46cac009 AC |
3851 | |
3852 | if (mips_debug) | |
3853 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3854 | argreg, phex (regval, 4)); | |
9c9acae0 | 3855 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3856 | } |
3857 | else | |
3858 | { | |
3859 | /* This is a floating point value that fits entirely | |
3860 | in a single register. */ | |
3861 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3862 | above to ensure that it is even register aligned. */ |
e17a4113 | 3863 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
3864 | if (mips_debug) |
3865 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3866 | float_argreg, phex (regval, len)); | |
025bb325 MS |
3867 | regcache_cooked_write_unsigned (regcache, |
3868 | float_argreg++, regval); | |
5b68030f JM |
3869 | /* Although two FP registers are reserved for each |
3870 | argument, only one corresponding integer register is | |
3871 | reserved. */ | |
46cac009 AC |
3872 | if (mips_debug) |
3873 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3874 | argreg, phex (regval, len)); | |
5b68030f | 3875 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3876 | } |
3877 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3878 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3879 | } |
3880 | else | |
3881 | { | |
3882 | /* Copy the argument to general registers or the stack in | |
3883 | register-sized pieces. Large arguments are split between | |
3884 | registers and stack. */ | |
1a69e1e4 DJ |
3885 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3886 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3887 | them in registers where gcc sometimes puts them on the |
3888 | stack. For maximum compatibility, we will put them in | |
3889 | both places. */ | |
1a69e1e4 DJ |
3890 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3891 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3892 | /* Structures should be aligned to eight bytes (even arg registers) |
3893 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3894 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3895 | { |
3896 | if ((argreg & 1)) | |
968b5391 MR |
3897 | { |
3898 | argreg++; | |
1a69e1e4 | 3899 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3900 | } |
46cac009 | 3901 | } |
46cac009 AC |
3902 | while (len > 0) |
3903 | { | |
3904 | /* Remember if the argument was written to the stack. */ | |
3905 | int stack_used_p = 0; | |
1a69e1e4 | 3906 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3907 | |
3908 | if (mips_debug) | |
3909 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3910 | partial_len); | |
3911 | ||
3912 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3913 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3914 | || odd_sized_struct) |
46cac009 AC |
3915 | { |
3916 | /* Should shorter than int integer values be | |
025bb325 | 3917 | promoted to int before being stored? */ |
46cac009 AC |
3918 | int longword_offset = 0; |
3919 | CORE_ADDR addr; | |
3920 | stack_used_p = 1; | |
46cac009 AC |
3921 | |
3922 | if (mips_debug) | |
3923 | { | |
5af949e3 UW |
3924 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3925 | paddress (gdbarch, stack_offset)); | |
3926 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3927 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
3928 | } |
3929 | ||
3930 | addr = sp + stack_offset + longword_offset; | |
3931 | ||
3932 | if (mips_debug) | |
3933 | { | |
3934 | int i; | |
5af949e3 UW |
3935 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3936 | paddress (gdbarch, addr)); | |
46cac009 AC |
3937 | for (i = 0; i < partial_len; i++) |
3938 | { | |
6d82d43b | 3939 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3940 | val[i] & 0xff); |
3941 | } | |
3942 | } | |
3943 | write_memory (addr, val, partial_len); | |
3944 | } | |
3945 | ||
3946 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3947 | structs may go thru BOTH paths. */ |
46cac009 | 3948 | /* Write this portion of the argument to a general |
6d82d43b | 3949 | purpose register. */ |
74ed0bb4 | 3950 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 3951 | { |
e17a4113 UW |
3952 | LONGEST regval = extract_signed_integer (val, partial_len, |
3953 | byte_order); | |
4246e332 | 3954 | /* Value may need to be sign extended, because |
1b13c4f6 | 3955 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3956 | |
3957 | /* A non-floating-point argument being passed in a | |
3958 | general register. If a struct or union, and if | |
3959 | the remaining length is smaller than the register | |
3960 | size, we have to adjust the register value on | |
3961 | big endian targets. | |
3962 | ||
3963 | It does not seem to be necessary to do the | |
3964 | same for integral types. | |
3965 | ||
3966 | Also don't do this adjustment on O64 binaries. | |
3967 | ||
3968 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3969 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3970 | mips_abi_regsize(), generates a left shift |
3971 | as part of storing the argument in a register | |
3972 | (the left shift isn't generated when | |
1b13c4f6 | 3973 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3974 | it is quite possible that this is GCC |
3975 | contradicting the LE/O32 ABI, GDB has not been | |
3976 | adjusted to accommodate this. Either someone | |
3977 | needs to demonstrate that the LE/O32 ABI | |
3978 | specifies such a left shift OR this new ABI gets | |
3979 | identified as such and GDB gets tweaked | |
3980 | accordingly. */ | |
3981 | ||
72a155b4 | 3982 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3983 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3984 | && (typecode == TYPE_CODE_STRUCT |
3985 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3986 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3987 | * TARGET_CHAR_BIT); |
46cac009 AC |
3988 | |
3989 | if (mips_debug) | |
3990 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3991 | argreg, | |
1a69e1e4 | 3992 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3993 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3994 | argreg++; |
3995 | ||
3996 | /* Prevent subsequent floating point arguments from | |
3997 | being passed in floating point registers. */ | |
74ed0bb4 | 3998 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
3999 | } |
4000 | ||
4001 | len -= partial_len; | |
4002 | val += partial_len; | |
4003 | ||
b021a221 MS |
4004 | /* Compute the offset into the stack at which we will |
4005 | copy the next parameter. | |
46cac009 | 4006 | |
6d82d43b AC |
4007 | In older ABIs, the caller reserved space for |
4008 | registers that contained arguments. This was loosely | |
4009 | refered to as their "home". Consequently, space is | |
4010 | always allocated. */ | |
46cac009 | 4011 | |
1a69e1e4 | 4012 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
4013 | } |
4014 | } | |
4015 | if (mips_debug) | |
4016 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4017 | } | |
4018 | ||
f10683bb | 4019 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4020 | |
46cac009 AC |
4021 | /* Return adjusted stack pointer. */ |
4022 | return sp; | |
4023 | } | |
4024 | ||
6d82d43b | 4025 | static enum return_value_convention |
c055b101 CV |
4026 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
4027 | struct type *type, struct regcache *regcache, | |
47a35522 | 4028 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4029 | { |
72a155b4 | 4030 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
4031 | |
4032 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4033 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4034 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4035 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4036 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4037 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4038 | { | |
4039 | /* A single-precision floating-point value. It fits in the | |
4040 | least significant part of FP0. */ | |
4041 | if (mips_debug) | |
4042 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4043 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4044 | gdbarch_num_regs (gdbarch) |
4045 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 4046 | TYPE_LENGTH (type), |
72a155b4 | 4047 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4048 | readbuf, writebuf, 0); |
6d82d43b AC |
4049 | return RETURN_VALUE_REGISTER_CONVENTION; |
4050 | } | |
4051 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4052 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4053 | { | |
4054 | /* A double-precision floating-point value. The most | |
4055 | significant part goes in FP1, and the least significant in | |
4056 | FP0. */ | |
4057 | if (mips_debug) | |
4058 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 4059 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
4060 | { |
4061 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 4062 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4063 | gdbarch_num_regs (gdbarch) |
4064 | + mips_regnum (gdbarch)->fp0 + | |
4065 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4066 | readbuf, writebuf, 0); |
ba32f989 | 4067 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4068 | gdbarch_num_regs (gdbarch) |
4069 | + mips_regnum (gdbarch)->fp0 + 1, | |
4070 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4071 | readbuf, writebuf, 4); |
6d82d43b AC |
4072 | break; |
4073 | case BFD_ENDIAN_BIG: | |
ba32f989 | 4074 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4075 | gdbarch_num_regs (gdbarch) |
4076 | + mips_regnum (gdbarch)->fp0 + 1, | |
4077 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4078 | readbuf, writebuf, 0); |
ba32f989 | 4079 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4080 | gdbarch_num_regs (gdbarch) |
4081 | + mips_regnum (gdbarch)->fp0 + 0, | |
4082 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4083 | readbuf, writebuf, 4); |
6d82d43b AC |
4084 | break; |
4085 | default: | |
e2e0b3e5 | 4086 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
4087 | } |
4088 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4089 | } | |
4090 | #if 0 | |
4091 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4092 | && TYPE_NFIELDS (type) <= 2 | |
4093 | && TYPE_NFIELDS (type) >= 1 | |
4094 | && ((TYPE_NFIELDS (type) == 1 | |
4095 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4096 | == TYPE_CODE_FLT)) | |
4097 | || (TYPE_NFIELDS (type) == 2 | |
4098 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4099 | == TYPE_CODE_FLT) | |
4100 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4101 | == TYPE_CODE_FLT))) | |
4102 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4103 | { | |
4104 | /* A struct that contains one or two floats. Each value is part | |
4105 | in the least significant part of their floating point | |
4106 | register.. */ | |
870cd05e | 4107 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
4108 | int regnum; |
4109 | int field; | |
72a155b4 | 4110 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
4111 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4112 | { | |
4113 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4114 | / TARGET_CHAR_BIT); | |
4115 | if (mips_debug) | |
4116 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4117 | offset); | |
ba32f989 DJ |
4118 | mips_xfer_register (gdbarch, regcache, |
4119 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 4120 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 4121 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4122 | readbuf, writebuf, offset); |
6d82d43b AC |
4123 | } |
4124 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4125 | } | |
4126 | #endif | |
4127 | #if 0 | |
4128 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4129 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4130 | { | |
4131 | /* A structure or union. Extract the left justified value, | |
4132 | regardless of the byte order. I.e. DO NOT USE | |
4133 | mips_xfer_lower. */ | |
4134 | int offset; | |
4135 | int regnum; | |
4c7d22cb | 4136 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4137 | offset < TYPE_LENGTH (type); |
72a155b4 | 4138 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 4139 | { |
72a155b4 | 4140 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
4141 | if (offset + xfer > TYPE_LENGTH (type)) |
4142 | xfer = TYPE_LENGTH (type) - offset; | |
4143 | if (mips_debug) | |
4144 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4145 | offset, xfer, regnum); | |
ba32f989 DJ |
4146 | mips_xfer_register (gdbarch, regcache, |
4147 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
4148 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
4149 | } | |
4150 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4151 | } | |
4152 | #endif | |
4153 | else | |
4154 | { | |
4155 | /* A scalar extract each part but least-significant-byte | |
4156 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 4157 | the ISA. */ |
6d82d43b AC |
4158 | int offset; |
4159 | int regnum; | |
4c7d22cb | 4160 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4161 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 4162 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 4163 | { |
1a69e1e4 | 4164 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
4165 | if (offset + xfer > TYPE_LENGTH (type)) |
4166 | xfer = TYPE_LENGTH (type) - offset; | |
4167 | if (mips_debug) | |
4168 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4169 | offset, xfer, regnum); | |
ba32f989 DJ |
4170 | mips_xfer_register (gdbarch, regcache, |
4171 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 4172 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4173 | readbuf, writebuf, offset); |
6d82d43b AC |
4174 | } |
4175 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4176 | } | |
4177 | } | |
4178 | ||
4179 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4180 | ABI. */ | |
46cac009 AC |
4181 | |
4182 | static CORE_ADDR | |
7d9b040b | 4183 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4184 | struct regcache *regcache, CORE_ADDR bp_addr, |
4185 | int nargs, | |
4186 | struct value **args, CORE_ADDR sp, | |
4187 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4188 | { |
4189 | int argreg; | |
4190 | int float_argreg; | |
4191 | int argnum; | |
4192 | int len = 0; | |
4193 | int stack_offset = 0; | |
480d3dd2 | 4194 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4195 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4196 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4197 | |
25ab4790 AC |
4198 | /* For shared libraries, "t9" needs to point at the function |
4199 | address. */ | |
4c7d22cb | 4200 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4201 | |
4202 | /* Set the return address register to point to the entry point of | |
4203 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4204 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4205 | |
46cac009 AC |
4206 | /* First ensure that the stack and structure return address (if any) |
4207 | are properly aligned. The stack has to be at least 64-bit | |
4208 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4209 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4210 | aligned, so we round to this widest known alignment. */ | |
4211 | ||
5b03f266 AC |
4212 | sp = align_down (sp, 16); |
4213 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4214 | |
4215 | /* Now make space on the stack for the args. */ | |
4216 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4217 | { |
4218 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4219 | int arglen = TYPE_LENGTH (arg_type); | |
4220 | ||
968b5391 | 4221 | /* Allocate space on the stack. */ |
1a69e1e4 | 4222 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4223 | } |
5b03f266 | 4224 | sp -= align_up (len, 16); |
46cac009 AC |
4225 | |
4226 | if (mips_debug) | |
6d82d43b | 4227 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4228 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4229 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4230 | |
4231 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4232 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4233 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4234 | |
4235 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4236 | if (struct_return) | |
4237 | { | |
4238 | if (mips_debug) | |
4239 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4240 | "mips_o64_push_dummy_call: " |
4241 | "struct_return reg=%d %s\n", | |
5af949e3 | 4242 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4243 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4244 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4245 | } |
4246 | ||
4247 | /* Now load as many as possible of the first arguments into | |
4248 | registers, and push the rest onto the stack. Loop thru args | |
4249 | from first to last. */ | |
4250 | for (argnum = 0; argnum < nargs; argnum++) | |
4251 | { | |
47a35522 | 4252 | const gdb_byte *val; |
930bd0e0 | 4253 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 4254 | struct value *arg = args[argnum]; |
4991999e | 4255 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4256 | int len = TYPE_LENGTH (arg_type); |
4257 | enum type_code typecode = TYPE_CODE (arg_type); | |
4258 | ||
4259 | if (mips_debug) | |
4260 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4261 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4262 | argnum + 1, len, (int) typecode); |
4263 | ||
47a35522 | 4264 | val = value_contents (arg); |
ebafbe83 | 4265 | |
930bd0e0 KB |
4266 | /* Function pointer arguments to mips16 code need to be made into |
4267 | mips16 pointers. */ | |
4268 | if (typecode == TYPE_CODE_PTR | |
4269 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4270 | { | |
4271 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4272 | len, byte_order); | |
4273 | if (mips_pc_is_mips16 (addr)) | |
4274 | { | |
4275 | store_signed_integer (valbuf, len, byte_order, | |
4276 | make_mips16_addr (addr)); | |
4277 | val = valbuf; | |
4278 | } | |
4279 | } | |
4280 | ||
ebafbe83 MS |
4281 | /* Floating point arguments passed in registers have to be |
4282 | treated specially. On 32-bit architectures, doubles | |
4283 | are passed in register pairs; the even register gets | |
4284 | the low word, and the odd register gets the high word. | |
4285 | On O32/O64, the first two floating point arguments are | |
4286 | also copied to general registers, because MIPS16 functions | |
4287 | don't use float registers for arguments. This duplication of | |
4288 | arguments in general registers can't hurt non-MIPS16 functions | |
4289 | because those registers are normally skipped. */ | |
4290 | ||
74ed0bb4 MD |
4291 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4292 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4293 | { |
e17a4113 | 4294 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4295 | if (mips_debug) |
4296 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4297 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4298 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4299 | if (mips_debug) |
4300 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4301 | argreg, phex (regval, len)); | |
9c9acae0 | 4302 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4303 | argreg++; |
ebafbe83 | 4304 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4305 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4306 | } |
4307 | else | |
4308 | { | |
4309 | /* Copy the argument to general registers or the stack in | |
4310 | register-sized pieces. Large arguments are split between | |
4311 | registers and stack. */ | |
1a69e1e4 | 4312 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4313 | are treated specially: Irix cc passes them in registers |
4314 | where gcc sometimes puts them on the stack. For maximum | |
4315 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4316 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4317 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4318 | while (len > 0) |
4319 | { | |
4320 | /* Remember if the argument was written to the stack. */ | |
4321 | int stack_used_p = 0; | |
1a69e1e4 | 4322 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4323 | |
4324 | if (mips_debug) | |
4325 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4326 | partial_len); | |
4327 | ||
4328 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4329 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4330 | || odd_sized_struct) |
ebafbe83 MS |
4331 | { |
4332 | /* Should shorter than int integer values be | |
025bb325 | 4333 | promoted to int before being stored? */ |
ebafbe83 MS |
4334 | int longword_offset = 0; |
4335 | CORE_ADDR addr; | |
4336 | stack_used_p = 1; | |
72a155b4 | 4337 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4338 | { |
1a69e1e4 DJ |
4339 | if ((typecode == TYPE_CODE_INT |
4340 | || typecode == TYPE_CODE_PTR | |
4341 | || typecode == TYPE_CODE_FLT) | |
4342 | && len <= 4) | |
4343 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4344 | } |
4345 | ||
4346 | if (mips_debug) | |
4347 | { | |
5af949e3 UW |
4348 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4349 | paddress (gdbarch, stack_offset)); | |
4350 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4351 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4352 | } |
4353 | ||
4354 | addr = sp + stack_offset + longword_offset; | |
4355 | ||
4356 | if (mips_debug) | |
4357 | { | |
4358 | int i; | |
5af949e3 UW |
4359 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4360 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4361 | for (i = 0; i < partial_len; i++) |
4362 | { | |
6d82d43b | 4363 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4364 | val[i] & 0xff); |
4365 | } | |
4366 | } | |
4367 | write_memory (addr, val, partial_len); | |
4368 | } | |
4369 | ||
4370 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4371 | structs may go thru BOTH paths. */ |
ebafbe83 | 4372 | /* Write this portion of the argument to a general |
6d82d43b | 4373 | purpose register. */ |
74ed0bb4 | 4374 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4375 | { |
e17a4113 UW |
4376 | LONGEST regval = extract_signed_integer (val, partial_len, |
4377 | byte_order); | |
4246e332 | 4378 | /* Value may need to be sign extended, because |
1b13c4f6 | 4379 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4380 | |
4381 | /* A non-floating-point argument being passed in a | |
4382 | general register. If a struct or union, and if | |
4383 | the remaining length is smaller than the register | |
4384 | size, we have to adjust the register value on | |
4385 | big endian targets. | |
4386 | ||
4387 | It does not seem to be necessary to do the | |
025bb325 | 4388 | same for integral types. */ |
480d3dd2 | 4389 | |
72a155b4 | 4390 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4391 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4392 | && (typecode == TYPE_CODE_STRUCT |
4393 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4394 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4395 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4396 | |
4397 | if (mips_debug) | |
4398 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4399 | argreg, | |
1a69e1e4 | 4400 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4401 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4402 | argreg++; |
4403 | ||
4404 | /* Prevent subsequent floating point arguments from | |
4405 | being passed in floating point registers. */ | |
74ed0bb4 | 4406 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4407 | } |
4408 | ||
4409 | len -= partial_len; | |
4410 | val += partial_len; | |
4411 | ||
b021a221 MS |
4412 | /* Compute the offset into the stack at which we will |
4413 | copy the next parameter. | |
ebafbe83 | 4414 | |
6d82d43b AC |
4415 | In older ABIs, the caller reserved space for |
4416 | registers that contained arguments. This was loosely | |
4417 | refered to as their "home". Consequently, space is | |
4418 | always allocated. */ | |
ebafbe83 | 4419 | |
1a69e1e4 | 4420 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4421 | } |
4422 | } | |
4423 | if (mips_debug) | |
4424 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4425 | } | |
4426 | ||
f10683bb | 4427 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4428 | |
ebafbe83 MS |
4429 | /* Return adjusted stack pointer. */ |
4430 | return sp; | |
4431 | } | |
4432 | ||
9c8fdbfa | 4433 | static enum return_value_convention |
c055b101 | 4434 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4435 | struct type *type, struct regcache *regcache, |
47a35522 | 4436 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4437 | { |
72a155b4 | 4438 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4439 | |
4440 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4441 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4442 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4443 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4444 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4445 | { |
4446 | /* A floating-point value. It fits in the least significant | |
4447 | part of FP0. */ | |
4448 | if (mips_debug) | |
4449 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4450 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4451 | gdbarch_num_regs (gdbarch) |
4452 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4453 | TYPE_LENGTH (type), |
72a155b4 | 4454 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4455 | readbuf, writebuf, 0); |
7a076fd2 FF |
4456 | return RETURN_VALUE_REGISTER_CONVENTION; |
4457 | } | |
4458 | else | |
4459 | { | |
4460 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 4461 | justified. */ |
7a076fd2 FF |
4462 | int offset; |
4463 | int regnum; | |
4464 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4465 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4466 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4467 | { |
1a69e1e4 | 4468 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4469 | if (offset + xfer > TYPE_LENGTH (type)) |
4470 | xfer = TYPE_LENGTH (type) - offset; | |
4471 | if (mips_debug) | |
4472 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4473 | offset, xfer, regnum); | |
ba32f989 DJ |
4474 | mips_xfer_register (gdbarch, regcache, |
4475 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4476 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4477 | readbuf, writebuf, offset); |
7a076fd2 FF |
4478 | } |
4479 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4480 | } | |
6d82d43b AC |
4481 | } |
4482 | ||
dd824b04 DJ |
4483 | /* Floating point register management. |
4484 | ||
4485 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4486 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4487 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4488 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4489 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4490 | double precision floats into two 32-bit chunks and store them in | |
4491 | consecutive fp regs. To display 64-bit floats stored in this | |
4492 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4493 | Throw in user-configurable endianness and you have a real mess. | |
4494 | ||
4495 | The way this works is: | |
4496 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4497 | double-precision value will be split across two logical registers. | |
4498 | The lower-numbered logical register will hold the low-order bits, | |
4499 | regardless of the processor's endianness. | |
4500 | - If we are on a 64-bit processor, and we are looking for a | |
4501 | single-precision value, it will be in the low ordered bits | |
4502 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4503 | save slot in memory. | |
4504 | - If we are in 64-bit mode, everything is straightforward. | |
4505 | ||
4506 | Note that this code only deals with "live" registers at the top of the | |
4507 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 4508 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
4509 | interface that can deal with dynamic saved register sizes -- fp |
4510 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4511 | and below). */ | |
4512 | ||
4513 | /* Copy a 32-bit single-precision value from the current frame | |
4514 | into rare_buffer. */ | |
4515 | ||
4516 | static void | |
e11c53d2 | 4517 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4518 | gdb_byte *rare_buffer) |
dd824b04 | 4519 | { |
72a155b4 UW |
4520 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4521 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4522 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4523 | |
e11c53d2 | 4524 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4525 | error (_("can't read register %d (%s)"), |
72a155b4 | 4526 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4527 | if (raw_size == 8) |
4528 | { | |
4529 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4530 | 32 bits. */ |
dd824b04 DJ |
4531 | int offset; |
4532 | ||
72a155b4 | 4533 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4534 | offset = 4; |
4535 | else | |
4536 | offset = 0; | |
4537 | ||
4538 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4539 | } | |
4540 | else | |
4541 | { | |
4542 | memcpy (rare_buffer, raw_buffer, 4); | |
4543 | } | |
4544 | } | |
4545 | ||
4546 | /* Copy a 64-bit double-precision value from the current frame into | |
4547 | rare_buffer. This may include getting half of it from the next | |
4548 | register. */ | |
4549 | ||
4550 | static void | |
e11c53d2 | 4551 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4552 | gdb_byte *rare_buffer) |
dd824b04 | 4553 | { |
72a155b4 UW |
4554 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4555 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4556 | |
9c9acae0 | 4557 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4558 | { |
4559 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4560 | all 64 bits. */ |
e11c53d2 | 4561 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4562 | error (_("can't read register %d (%s)"), |
72a155b4 | 4563 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4564 | } |
4565 | else | |
4566 | { | |
72a155b4 | 4567 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4568 | |
72a155b4 | 4569 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4570 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4571 | _("mips_read_fp_register_double: bad access to " |
4572 | "odd-numbered FP register")); | |
dd824b04 DJ |
4573 | |
4574 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4575 | each register. */ |
72a155b4 | 4576 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4577 | { |
e11c53d2 AC |
4578 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4579 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4580 | } |
361d1df0 | 4581 | else |
dd824b04 | 4582 | { |
e11c53d2 AC |
4583 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4584 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4585 | } |
4586 | } | |
4587 | } | |
4588 | ||
c906108c | 4589 | static void |
e11c53d2 AC |
4590 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4591 | int regnum) | |
025bb325 | 4592 | { /* Do values for FP (float) regs. */ |
72a155b4 | 4593 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4594 | gdb_byte *raw_buffer; |
025bb325 | 4595 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 4596 | int inv1, inv2; |
c5aa993b | 4597 | |
025bb325 MS |
4598 | raw_buffer = alloca (2 * register_size (gdbarch, |
4599 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 4600 | |
72a155b4 | 4601 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4602 | fprintf_filtered (file, "%*s", |
72a155b4 | 4603 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4604 | ""); |
f0ef6b29 | 4605 | |
72a155b4 | 4606 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4607 | { |
79a45b7d TT |
4608 | struct value_print_options opts; |
4609 | ||
f0ef6b29 KB |
4610 | /* 4-byte registers: Print hex and floating. Also print even |
4611 | numbered registers as doubles. */ | |
e11c53d2 | 4612 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
4613 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4614 | raw_buffer, &inv1); | |
c5aa993b | 4615 | |
79a45b7d | 4616 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4617 | print_scalar_formatted (raw_buffer, |
4618 | builtin_type (gdbarch)->builtin_uint32, | |
4619 | &opts, 'w', file); | |
dd824b04 | 4620 | |
e11c53d2 | 4621 | fprintf_filtered (file, " flt: "); |
1adad886 | 4622 | if (inv1) |
e11c53d2 | 4623 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4624 | else |
e11c53d2 | 4625 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4626 | |
72a155b4 | 4627 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4628 | { |
e11c53d2 | 4629 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4630 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4631 | raw_buffer, &inv2); | |
1adad886 | 4632 | |
e11c53d2 | 4633 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4634 | if (inv2) |
e11c53d2 | 4635 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4636 | else |
e11c53d2 | 4637 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4638 | } |
c906108c SS |
4639 | } |
4640 | else | |
dd824b04 | 4641 | { |
79a45b7d TT |
4642 | struct value_print_options opts; |
4643 | ||
f0ef6b29 | 4644 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4645 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4646 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4647 | raw_buffer, &inv1); | |
c906108c | 4648 | |
e11c53d2 | 4649 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4650 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4651 | raw_buffer, &inv2); | |
f0ef6b29 | 4652 | |
79a45b7d | 4653 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4654 | print_scalar_formatted (raw_buffer, |
4655 | builtin_type (gdbarch)->builtin_uint64, | |
4656 | &opts, 'g', file); | |
f0ef6b29 | 4657 | |
e11c53d2 | 4658 | fprintf_filtered (file, " flt: "); |
1adad886 | 4659 | if (inv1) |
e11c53d2 | 4660 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4661 | else |
e11c53d2 | 4662 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4663 | |
e11c53d2 | 4664 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4665 | if (inv2) |
e11c53d2 | 4666 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4667 | else |
e11c53d2 | 4668 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4669 | } |
4670 | } | |
4671 | ||
4672 | static void | |
e11c53d2 | 4673 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4674 | int regnum) |
f0ef6b29 | 4675 | { |
a4b8ebc8 | 4676 | struct gdbarch *gdbarch = get_frame_arch (frame); |
f0ef6b29 | 4677 | int offset; |
79a45b7d | 4678 | struct value_print_options opts; |
de15c4ab | 4679 | struct value *val; |
1adad886 | 4680 | |
7b9ee6a8 | 4681 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4682 | { |
e11c53d2 | 4683 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4684 | return; |
4685 | } | |
4686 | ||
de15c4ab PA |
4687 | val = get_frame_register_value (frame, regnum); |
4688 | if (value_optimized_out (val)) | |
f0ef6b29 | 4689 | { |
c9f4d572 | 4690 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4691 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4692 | return; |
c906108c | 4693 | } |
f0ef6b29 | 4694 | |
72a155b4 | 4695 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4696 | |
4697 | /* The problem with printing numeric register names (r26, etc.) is that | |
4698 | the user can't use them on input. Probably the best solution is to | |
4699 | fix it so that either the numeric or the funky (a2, etc.) names | |
4700 | are accepted on input. */ | |
4701 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4702 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4703 | else |
e11c53d2 | 4704 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4705 | |
79a45b7d | 4706 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
4707 | val_print_scalar_formatted (value_type (val), |
4708 | value_contents_for_printing (val), | |
4709 | value_embedded_offset (val), | |
4710 | val, | |
4711 | &opts, 0, file); | |
c906108c SS |
4712 | } |
4713 | ||
f0ef6b29 KB |
4714 | /* Replacement for generic do_registers_info. |
4715 | Print regs in pretty columns. */ | |
4716 | ||
4717 | static int | |
e11c53d2 AC |
4718 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4719 | int regnum) | |
f0ef6b29 | 4720 | { |
e11c53d2 AC |
4721 | fprintf_filtered (file, " "); |
4722 | mips_print_fp_register (file, frame, regnum); | |
4723 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4724 | return regnum + 1; |
4725 | } | |
4726 | ||
4727 | ||
025bb325 | 4728 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
4729 | |
4730 | static int | |
e11c53d2 | 4731 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4732 | int start_regnum) |
c906108c | 4733 | { |
a4b8ebc8 | 4734 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 4735 | /* Do values for GP (int) regs. */ |
47a35522 | 4736 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
4737 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
4738 | per row. */ | |
c906108c | 4739 | int col, byte; |
a4b8ebc8 | 4740 | int regnum; |
c906108c | 4741 | |
025bb325 | 4742 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 4743 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4744 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4745 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4746 | regnum++) |
c906108c | 4747 | { |
72a155b4 | 4748 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4749 | continue; /* unused register */ |
7b9ee6a8 | 4750 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4751 | TYPE_CODE_FLT) |
025bb325 | 4752 | break; /* End the row: reached FP register. */ |
0cc93a06 | 4753 | /* Large registers are handled separately. */ |
72a155b4 | 4754 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4755 | { |
4756 | if (col > 0) | |
4757 | break; /* End the row before this register. */ | |
4758 | ||
4759 | /* Print this register on a row by itself. */ | |
4760 | mips_print_register (file, frame, regnum); | |
4761 | fprintf_filtered (file, "\n"); | |
4762 | return regnum + 1; | |
4763 | } | |
d05f6826 DJ |
4764 | if (col == 0) |
4765 | fprintf_filtered (file, " "); | |
6d82d43b | 4766 | fprintf_filtered (file, |
72a155b4 UW |
4767 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4768 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4769 | col++; |
4770 | } | |
d05f6826 DJ |
4771 | |
4772 | if (col == 0) | |
4773 | return regnum; | |
4774 | ||
025bb325 | 4775 | /* Print the R0 to R31 names. */ |
72a155b4 | 4776 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4777 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4778 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4779 | else |
4780 | fprintf_filtered (file, "\n "); | |
c906108c | 4781 | |
025bb325 | 4782 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 4783 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4784 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4785 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4786 | regnum++) |
c906108c | 4787 | { |
72a155b4 | 4788 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4789 | continue; /* unused register */ |
7b9ee6a8 | 4790 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4791 | TYPE_CODE_FLT) |
025bb325 | 4792 | break; /* End row: reached FP register. */ |
72a155b4 | 4793 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4794 | break; /* End row: large register. */ |
4795 | ||
c906108c | 4796 | /* OK: get the data in raw format. */ |
e11c53d2 | 4797 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4798 | error (_("can't read register %d (%s)"), |
72a155b4 | 4799 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4800 | /* pad small registers */ |
4246e332 | 4801 | for (byte = 0; |
72a155b4 UW |
4802 | byte < (mips_abi_regsize (gdbarch) |
4803 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 4804 | printf_filtered (" "); |
025bb325 | 4805 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 4806 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4807 | for (byte = |
72a155b4 UW |
4808 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4809 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4810 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4811 | else |
72a155b4 | 4812 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4813 | byte >= 0; byte--) |
47a35522 | 4814 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4815 | fprintf_filtered (file, " "); |
c906108c SS |
4816 | col++; |
4817 | } | |
025bb325 | 4818 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4819 | fprintf_filtered (file, "\n"); |
c906108c SS |
4820 | |
4821 | return regnum; | |
4822 | } | |
4823 | ||
025bb325 | 4824 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 4825 | |
bf1f5b4c | 4826 | static void |
e11c53d2 AC |
4827 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4828 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4829 | { |
025bb325 | 4830 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 4831 | { |
72a155b4 UW |
4832 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4833 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4834 | error (_("Not a valid register for the current processor type")); |
c906108c | 4835 | |
0cc93a06 | 4836 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4837 | fprintf_filtered (file, "\n"); |
c906108c | 4838 | } |
c5aa993b | 4839 | else |
025bb325 | 4840 | /* Do all (or most) registers. */ |
c906108c | 4841 | { |
72a155b4 UW |
4842 | regnum = gdbarch_num_regs (gdbarch); |
4843 | while (regnum < gdbarch_num_regs (gdbarch) | |
4844 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4845 | { |
7b9ee6a8 | 4846 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4847 | TYPE_CODE_FLT) |
e11c53d2 | 4848 | { |
025bb325 | 4849 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
4850 | regnum = print_fp_register_row (file, frame, regnum); |
4851 | else | |
025bb325 | 4852 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 4853 | } |
c906108c | 4854 | else |
e11c53d2 | 4855 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4856 | } |
4857 | } | |
4858 | } | |
4859 | ||
c906108c SS |
4860 | /* Is this a branch with a delay slot? */ |
4861 | ||
c906108c | 4862 | static int |
acdb74a0 | 4863 | is_delayed (unsigned long insn) |
c906108c SS |
4864 | { |
4865 | int i; | |
4866 | for (i = 0; i < NUMOPCODES; ++i) | |
4867 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4868 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4869 | break; | |
4870 | return (i < NUMOPCODES | |
4871 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4872 | | INSN_COND_BRANCH_DELAY | |
4873 | | INSN_COND_BRANCH_LIKELY))); | |
4874 | } | |
4875 | ||
63807e1d | 4876 | static int |
3352ef37 AC |
4877 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4878 | struct frame_info *frame) | |
c906108c | 4879 | { |
e17a4113 | 4880 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 4881 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4882 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4883 | |
4884 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4885 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4886 | return 0; |
4887 | ||
6c95b8df | 4888 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
06648491 MK |
4889 | return 0; |
4890 | ||
3352ef37 AC |
4891 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4892 | /* If error reading memory, guess that it is not a delayed | |
4893 | branch. */ | |
c906108c | 4894 | return 0; |
e17a4113 | 4895 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
4896 | } |
4897 | ||
6d82d43b AC |
4898 | /* To skip prologues, I use this predicate. Returns either PC itself |
4899 | if the code at PC does not look like a function prologue; otherwise | |
4900 | returns an address that (if we're lucky) follows the prologue. If | |
4901 | LENIENT, then we must skip everything which is involved in setting | |
4902 | up the frame (it's OK to skip more, just so long as we don't skip | |
4903 | anything which might clobber the registers which are being saved. | |
4904 | We must skip more in the case where part of the prologue is in the | |
4905 | delay slot of a non-prologue instruction). */ | |
4906 | ||
4907 | static CORE_ADDR | |
6093d2eb | 4908 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4909 | { |
8b622e6a AC |
4910 | CORE_ADDR limit_pc; |
4911 | CORE_ADDR func_addr; | |
4912 | ||
6d82d43b AC |
4913 | /* See if we can determine the end of the prologue via the symbol table. |
4914 | If so, then return either PC, or the PC after the prologue, whichever | |
4915 | is greater. */ | |
8b622e6a AC |
4916 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4917 | { | |
d80b854b UW |
4918 | CORE_ADDR post_prologue_pc |
4919 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
4920 | if (post_prologue_pc != 0) |
4921 | return max (pc, post_prologue_pc); | |
4922 | } | |
6d82d43b AC |
4923 | |
4924 | /* Can't determine prologue from the symbol table, need to examine | |
4925 | instructions. */ | |
4926 | ||
98b4dd94 JB |
4927 | /* Find an upper limit on the function prologue using the debug |
4928 | information. If the debug information could not be used to provide | |
4929 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 4930 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
4931 | if (limit_pc == 0) |
4932 | limit_pc = pc + 100; /* Magic. */ | |
4933 | ||
0fe7e7c8 | 4934 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 4935 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 4936 | else |
e17a4113 | 4937 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
4938 | } |
4939 | ||
97ab0fdd MR |
4940 | /* Check whether the PC is in a function epilogue (32-bit version). |
4941 | This is a helper function for mips_in_function_epilogue_p. */ | |
4942 | static int | |
e17a4113 | 4943 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4944 | { |
4945 | CORE_ADDR func_addr = 0, func_end = 0; | |
4946 | ||
4947 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4948 | { | |
4949 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4950 | CORE_ADDR addr = func_end - 12; | |
4951 | ||
4952 | if (addr < func_addr + 4) | |
4953 | addr = func_addr + 4; | |
4954 | if (pc < addr) | |
4955 | return 0; | |
4956 | ||
4957 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4958 | { | |
4959 | unsigned long high_word; | |
4960 | unsigned long inst; | |
4961 | ||
e17a4113 | 4962 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4963 | high_word = (inst >> 16) & 0xffff; |
4964 | ||
4965 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4966 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4967 | && inst != 0x03e00008 /* jr $ra */ | |
4968 | && inst != 0x00000000) /* nop */ | |
4969 | return 0; | |
4970 | } | |
4971 | ||
4972 | return 1; | |
4973 | } | |
4974 | ||
4975 | return 0; | |
4976 | } | |
4977 | ||
4978 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4979 | This is a helper function for mips_in_function_epilogue_p. */ | |
4980 | static int | |
e17a4113 | 4981 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4982 | { |
4983 | CORE_ADDR func_addr = 0, func_end = 0; | |
4984 | ||
4985 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4986 | { | |
4987 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4988 | CORE_ADDR addr = func_end - 12; | |
4989 | ||
4990 | if (addr < func_addr + 4) | |
4991 | addr = func_addr + 4; | |
4992 | if (pc < addr) | |
4993 | return 0; | |
4994 | ||
4995 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4996 | { | |
4997 | unsigned short inst; | |
4998 | ||
e17a4113 | 4999 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
5000 | |
5001 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
5002 | continue; | |
5003 | ||
5004 | if (inst != 0x6300 /* addiu $sp,offset */ | |
5005 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
5006 | && inst != 0xe820 /* jr $ra */ | |
5007 | && inst != 0xe8a0 /* jrc $ra */ | |
5008 | && inst != 0x6500) /* nop */ | |
5009 | return 0; | |
5010 | } | |
5011 | ||
5012 | return 1; | |
5013 | } | |
5014 | ||
5015 | return 0; | |
5016 | } | |
5017 | ||
5018 | /* The epilogue is defined here as the area at the end of a function, | |
5019 | after an instruction which destroys the function's stack frame. */ | |
5020 | static int | |
5021 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
5022 | { | |
5023 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 5024 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 5025 | else |
e17a4113 | 5026 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
5027 | } |
5028 | ||
025bb325 | 5029 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
5030 | used for all MIPS-specific commands. */ |
5031 | ||
a5ea2558 | 5032 | static void |
acdb74a0 | 5033 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5034 | { |
5035 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5036 | } | |
5037 | ||
a5ea2558 | 5038 | static void |
acdb74a0 | 5039 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5040 | { |
6d82d43b AC |
5041 | printf_unfiltered |
5042 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5043 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5044 | } | |
5045 | ||
c906108c SS |
5046 | /* Commands to show/set the MIPS FPU type. */ |
5047 | ||
c906108c | 5048 | static void |
acdb74a0 | 5049 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5050 | { |
c906108c | 5051 | char *fpu; |
6ca0852e | 5052 | |
1cf3db46 | 5053 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
5054 | { |
5055 | printf_unfiltered | |
5056 | ("The MIPS floating-point coprocessor is unknown " | |
5057 | "because the current architecture is not MIPS.\n"); | |
5058 | return; | |
5059 | } | |
5060 | ||
1cf3db46 | 5061 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
5062 | { |
5063 | case MIPS_FPU_SINGLE: | |
5064 | fpu = "single-precision"; | |
5065 | break; | |
5066 | case MIPS_FPU_DOUBLE: | |
5067 | fpu = "double-precision"; | |
5068 | break; | |
5069 | case MIPS_FPU_NONE: | |
5070 | fpu = "absent (none)"; | |
5071 | break; | |
93d56215 | 5072 | default: |
e2e0b3e5 | 5073 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
5074 | } |
5075 | if (mips_fpu_type_auto) | |
025bb325 MS |
5076 | printf_unfiltered ("The MIPS floating-point coprocessor " |
5077 | "is set automatically (currently %s)\n", | |
5078 | fpu); | |
c906108c | 5079 | else |
6d82d43b AC |
5080 | printf_unfiltered |
5081 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5082 | } |
5083 | ||
5084 | ||
c906108c | 5085 | static void |
acdb74a0 | 5086 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5087 | { |
025bb325 MS |
5088 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
5089 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5090 | show_mipsfpu_command (args, from_tty); |
5091 | } | |
5092 | ||
c906108c | 5093 | static void |
acdb74a0 | 5094 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5095 | { |
8d5838b5 AC |
5096 | struct gdbarch_info info; |
5097 | gdbarch_info_init (&info); | |
c906108c SS |
5098 | mips_fpu_type = MIPS_FPU_SINGLE; |
5099 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5100 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5101 | instead of relying on globals. Doing that would let generic code | |
5102 | handle the search for this specific architecture. */ | |
5103 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5104 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5105 | } |
5106 | ||
c906108c | 5107 | static void |
acdb74a0 | 5108 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5109 | { |
8d5838b5 AC |
5110 | struct gdbarch_info info; |
5111 | gdbarch_info_init (&info); | |
c906108c SS |
5112 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5113 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5114 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5115 | instead of relying on globals. Doing that would let generic code | |
5116 | handle the search for this specific architecture. */ | |
5117 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5118 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5119 | } |
5120 | ||
c906108c | 5121 | static void |
acdb74a0 | 5122 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5123 | { |
8d5838b5 AC |
5124 | struct gdbarch_info info; |
5125 | gdbarch_info_init (&info); | |
c906108c SS |
5126 | mips_fpu_type = MIPS_FPU_NONE; |
5127 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5128 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5129 | instead of relying on globals. Doing that would let generic code | |
5130 | handle the search for this specific architecture. */ | |
5131 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5132 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5133 | } |
5134 | ||
c906108c | 5135 | static void |
acdb74a0 | 5136 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5137 | { |
5138 | mips_fpu_type_auto = 1; | |
5139 | } | |
5140 | ||
c906108c | 5141 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5142 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5143 | the relevant processor still exists (it dates back to '94) and | |
5144 | secondly this is not the way to do this. The processor type should | |
5145 | be set by forcing an architecture change. */ | |
c906108c | 5146 | |
691c0433 AC |
5147 | void |
5148 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5149 | { |
bb486190 UW |
5150 | struct regcache *regcache = get_current_regcache (); |
5151 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
5152 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 5153 | ULONGEST prid; |
c906108c | 5154 | |
bb486190 | 5155 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 5156 | if ((prid & ~0xf) == 0x700) |
691c0433 | 5157 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5158 | } |
5159 | ||
5160 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5161 | callable as an sfunc. */ | |
5162 | ||
5163 | static void | |
acdb74a0 AC |
5164 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5165 | struct cmd_list_element *c) | |
c906108c SS |
5166 | { |
5167 | reinit_frame_cache (); | |
5168 | } | |
5169 | ||
a89aa300 AC |
5170 | static int |
5171 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5172 | { |
d31431ed AC |
5173 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5174 | disassembler needs to be able to locally determine the ISA, and | |
5175 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5176 | work. */ | |
ec4045ea AC |
5177 | if (mips_pc_is_mips16 (memaddr)) |
5178 | info->mach = bfd_mach_mips16; | |
c906108c SS |
5179 | |
5180 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5181 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5182 | |
e5ab0dce | 5183 | /* Set the disassembler options. */ |
9dae60cc | 5184 | if (!info->disassembler_options) |
e5ab0dce AC |
5185 | /* This string is not recognized explicitly by the disassembler, |
5186 | but it tells the disassembler to not try to guess the ABI from | |
5187 | the bfd elf headers, such that, if the user overrides the ABI | |
5188 | of a program linked as NewABI, the disassembly will follow the | |
5189 | register naming conventions specified by the user. */ | |
5190 | info->disassembler_options = "gpr-names=32"; | |
5191 | ||
c906108c | 5192 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 5193 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
5194 | return print_insn_big_mips (memaddr, info); |
5195 | else | |
5196 | return print_insn_little_mips (memaddr, info); | |
5197 | } | |
5198 | ||
9dae60cc UW |
5199 | static int |
5200 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
5201 | { | |
5202 | /* Set up the disassembler info, so that we get the right | |
5203 | register names from libopcodes. */ | |
5204 | info->disassembler_options = "gpr-names=n32"; | |
5205 | info->flavour = bfd_target_elf_flavour; | |
5206 | ||
5207 | return gdb_print_insn_mips (memaddr, info); | |
5208 | } | |
5209 | ||
5210 | static int | |
5211 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5212 | { | |
5213 | /* Set up the disassembler info, so that we get the right | |
5214 | register names from libopcodes. */ | |
5215 | info->disassembler_options = "gpr-names=64"; | |
5216 | info->flavour = bfd_target_elf_flavour; | |
5217 | ||
5218 | return gdb_print_insn_mips (memaddr, info); | |
5219 | } | |
5220 | ||
025bb325 MS |
5221 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
5222 | program counter value to determine whether a 16- or 32-bit breakpoint | |
5223 | should be used. It returns a pointer to a string of bytes that encode a | |
5224 | breakpoint instruction, stores the length of the string to *lenptr, and | |
5225 | adjusts pc (if necessary) to point to the actual memory location where | |
5226 | the breakpoint should be inserted. */ | |
c906108c | 5227 | |
47a35522 | 5228 | static const gdb_byte * |
025bb325 MS |
5229 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
5230 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 5231 | { |
67d57894 | 5232 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5233 | { |
0fe7e7c8 | 5234 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5235 | { |
47a35522 | 5236 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5237 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5238 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5239 | return mips16_big_breakpoint; |
5240 | } | |
5241 | else | |
5242 | { | |
aaab4dba AC |
5243 | /* The IDT board uses an unusual breakpoint value, and |
5244 | sometimes gets confused when it sees the usual MIPS | |
5245 | breakpoint instruction. */ | |
47a35522 MK |
5246 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5247 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5248 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 5249 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 5250 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 5251 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 5252 | |
c5aa993b | 5253 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5254 | |
5255 | if (strcmp (target_shortname, "mips") == 0) | |
5256 | return idt_big_breakpoint; | |
5257 | else if (strcmp (target_shortname, "ddb") == 0 | |
5258 | || strcmp (target_shortname, "pmon") == 0 | |
5259 | || strcmp (target_shortname, "lsi") == 0) | |
5260 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
5261 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5262 | return irix_big_breakpoint; | |
c906108c SS |
5263 | else |
5264 | return big_breakpoint; | |
5265 | } | |
5266 | } | |
5267 | else | |
5268 | { | |
0fe7e7c8 | 5269 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5270 | { |
47a35522 | 5271 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5272 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5273 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5274 | return mips16_little_breakpoint; |
5275 | } | |
5276 | else | |
5277 | { | |
47a35522 MK |
5278 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5279 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5280 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5281 | |
c5aa993b | 5282 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5283 | |
5284 | if (strcmp (target_shortname, "mips") == 0) | |
5285 | return idt_little_breakpoint; | |
5286 | else if (strcmp (target_shortname, "ddb") == 0 | |
5287 | || strcmp (target_shortname, "pmon") == 0 | |
5288 | || strcmp (target_shortname, "lsi") == 0) | |
5289 | return pmon_little_breakpoint; | |
5290 | else | |
5291 | return little_breakpoint; | |
5292 | } | |
5293 | } | |
5294 | } | |
5295 | ||
5296 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5297 | PC, which is either the callee or the caller. There are several | |
5298 | cases which must be handled: | |
5299 | ||
5300 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5301 | target PC is in $31 ($ra). |
c906108c | 5302 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5303 | and the target PC is in $2. |
c906108c | 5304 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b | 5305 | before the jal instruction, this is effectively a call stub |
b021a221 | 5306 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5307 | a return stub and the target PC is in $18. |
c906108c SS |
5308 | |
5309 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5310 | gory details. */ |
c906108c | 5311 | |
757a7cc6 | 5312 | static CORE_ADDR |
db5f024e | 5313 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5314 | { |
e17a4113 | 5315 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c SS |
5316 | char *name; |
5317 | CORE_ADDR start_addr; | |
5318 | ||
5319 | /* Find the starting address and name of the function containing the PC. */ | |
5320 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5321 | return 0; | |
5322 | ||
5323 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5324 | target PC is in $31 ($ra). */ | |
5325 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5326 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5327 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5328 | |
5329 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5330 | { | |
5331 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5332 | and the target PC is in $2. */ | |
5333 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5334 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5335 | |
5336 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5337 | before the jal instruction, this is effectively a call stub |
b021a221 | 5338 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5339 | a return stub and the target PC is in $18. */ |
c906108c SS |
5340 | else if (name[19] == 's' || name[19] == 'd') |
5341 | { | |
5342 | if (pc == start_addr) | |
5343 | { | |
5344 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5345 | stub. Such a stub for a function bar might have a name |
5346 | like __fn_stub_bar, and might look like this: | |
5347 | mfc1 $4,$f13 | |
5348 | mfc1 $5,$f12 | |
5349 | mfc1 $6,$f15 | |
5350 | mfc1 $7,$f14 | |
5351 | la $1,bar (becomes a lui/addiu pair) | |
5352 | jr $1 | |
5353 | So scan down to the lui/addi and extract the target | |
5354 | address from those two instructions. */ | |
c906108c | 5355 | |
52f729a7 | 5356 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
c906108c SS |
5357 | int i; |
5358 | ||
5359 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5360 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5361 | 0) | |
c906108c SS |
5362 | return target_pc; |
5363 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5364 | && strcmp (name, "etext") != 0 | |
5365 | && strcmp (name, "_etext") != 0) | |
5366 | return target_pc; | |
5367 | ||
5368 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5369 | The limit on the search is arbitrarily set to 20 |
5370 | instructions. FIXME. */ | |
95ac2dcf | 5371 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5372 | { |
280711e7 MR |
5373 | ULONGEST inst = mips_fetch_instruction (gdbarch, target_pc); |
5374 | CORE_ADDR addr = inst; | |
5375 | ||
c5aa993b | 5376 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
280711e7 MR |
5377 | pc = (((addr & 0xffff) ^ 0x8000) - 0x8000) << 16; |
5378 | /* high word */ | |
c5aa993b | 5379 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ |
280711e7 MR |
5380 | return pc + ((addr & 0xffff) ^ 0x8000) - 0x8000; |
5381 | /* low word */ | |
c906108c SS |
5382 | } |
5383 | ||
5384 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5385 | return target_pc; | |
5386 | } | |
5387 | else | |
5388 | /* This is the 'return' part of a call stub. The return | |
5389 | address is in $r18. */ | |
52f729a7 | 5390 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5391 | } |
5392 | } | |
c5aa993b | 5393 | return 0; /* not a stub */ |
c906108c SS |
5394 | } |
5395 | ||
db5f024e DJ |
5396 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5397 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5398 | so that $t9 has the correct value at function entry. */ | |
5399 | ||
5400 | static CORE_ADDR | |
5401 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5402 | { | |
e17a4113 UW |
5403 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5404 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
5405 | struct minimal_symbol *msym; |
5406 | int i; | |
5407 | gdb_byte stub_code[16]; | |
5408 | int32_t stub_words[4]; | |
5409 | ||
5410 | /* The stub for foo is named ".pic.foo", and is either two | |
5411 | instructions inserted before foo or a three instruction sequence | |
5412 | which jumps to foo. */ | |
5413 | msym = lookup_minimal_symbol_by_pc (pc); | |
5414 | if (msym == NULL | |
5415 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5416 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5417 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5418 | return 0; | |
5419 | ||
5420 | /* A two-instruction header. */ | |
5421 | if (MSYMBOL_SIZE (msym) == 8) | |
5422 | return pc + 8; | |
5423 | ||
5424 | /* A three-instruction (plus delay slot) trampoline. */ | |
5425 | if (MSYMBOL_SIZE (msym) == 16) | |
5426 | { | |
5427 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5428 | return 0; | |
5429 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
5430 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
5431 | 4, byte_order); | |
db5f024e DJ |
5432 | |
5433 | /* A stub contains these instructions: | |
5434 | lui t9, %hi(target) | |
5435 | j target | |
5436 | addiu t9, t9, %lo(target) | |
5437 | nop | |
5438 | ||
5439 | This works even for N64, since stubs are only generated with | |
5440 | -msym32. */ | |
5441 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5442 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5443 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5444 | && stub_words[3] == 0x00000000) | |
5445 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5446 | + (stub_words[2] & 0x0000ffff)); | |
5447 | } | |
5448 | ||
5449 | /* Not a recognized stub. */ | |
5450 | return 0; | |
5451 | } | |
5452 | ||
5453 | static CORE_ADDR | |
5454 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5455 | { | |
5456 | CORE_ADDR target_pc; | |
5457 | ||
5458 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5459 | if (target_pc) | |
5460 | return target_pc; | |
5461 | ||
5462 | target_pc = find_solib_trampoline_target (frame, pc); | |
5463 | if (target_pc) | |
5464 | return target_pc; | |
5465 | ||
5466 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5467 | if (target_pc) | |
5468 | return target_pc; | |
5469 | ||
5470 | return 0; | |
5471 | } | |
5472 | ||
a4b8ebc8 | 5473 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5474 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5475 | |
5476 | static int | |
d3f73121 | 5477 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5478 | { |
a4b8ebc8 | 5479 | int regnum; |
2f38ef89 | 5480 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5481 | regnum = num; |
2f38ef89 | 5482 | else if (num >= 38 && num < 70) |
d3f73121 | 5483 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5484 | else if (num == 70) |
d3f73121 | 5485 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5486 | else if (num == 71) |
d3f73121 | 5487 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5488 | else |
a4b8ebc8 AC |
5489 | /* This will hopefully (eventually) provoke a warning. Should |
5490 | we be calling complaint() here? */ | |
d3f73121 MD |
5491 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5492 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5493 | } |
5494 | ||
2f38ef89 | 5495 | |
a4b8ebc8 | 5496 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5497 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5498 | |
5499 | static int | |
d3f73121 | 5500 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5501 | { |
a4b8ebc8 | 5502 | int regnum; |
2f38ef89 | 5503 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5504 | regnum = num; |
2f38ef89 | 5505 | else if (num >= 32 && num < 64) |
d3f73121 | 5506 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5507 | else if (num == 64) |
d3f73121 | 5508 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5509 | else if (num == 65) |
d3f73121 | 5510 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5511 | else |
a4b8ebc8 AC |
5512 | /* This will hopefully (eventually) provoke a warning. Should we |
5513 | be calling complaint() here? */ | |
d3f73121 MD |
5514 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5515 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5516 | } |
5517 | ||
5518 | static int | |
e7faf938 | 5519 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5520 | { |
5521 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5522 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5523 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5524 | decide if it is valid. Should instead define a standard sim/gdb | |
5525 | register numbering scheme. */ | |
e7faf938 MD |
5526 | if (gdbarch_register_name (gdbarch, |
5527 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5528 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
5529 | gdbarch_num_regs (gdbarch) |
5530 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5531 | return regnum; |
5532 | else | |
6d82d43b | 5533 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5534 | } |
5535 | ||
2f38ef89 | 5536 | |
4844f454 CV |
5537 | /* Convert an integer into an address. Extracting the value signed |
5538 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5539 | |
5540 | static CORE_ADDR | |
79dd2d24 | 5541 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5542 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5543 | { |
e17a4113 UW |
5544 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
5545 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
5546 | } |
5547 | ||
82e91389 DJ |
5548 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5549 | than most other architectures; we just need to be explicit about it, | |
5550 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5551 | an assertion failure. */ | |
5552 | ||
5553 | static void | |
a54fba4c MD |
5554 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5555 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5556 | { |
5557 | *reg = MIPS_SP_REGNUM; | |
5558 | *offset = 0; | |
5559 | } | |
5560 | ||
caaa3122 DJ |
5561 | static void |
5562 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5563 | { | |
5564 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5565 | const char *name = bfd_get_section_name (abfd, sect); | |
5566 | ||
5567 | if (*abip != MIPS_ABI_UNKNOWN) | |
5568 | return; | |
5569 | ||
5570 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5571 | return; | |
5572 | ||
5573 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5574 | *abip = MIPS_ABI_O32; | |
5575 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5576 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5577 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5578 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5579 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5580 | *abip = MIPS_ABI_O64; | |
5581 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5582 | *abip = MIPS_ABI_EABI32; | |
5583 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5584 | *abip = MIPS_ABI_EABI64; | |
5585 | else | |
8a3fe4f8 | 5586 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5587 | } |
5588 | ||
22e47e37 FF |
5589 | static void |
5590 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5591 | { | |
5592 | int *lbp = (int *) obj; | |
5593 | const char *name = bfd_get_section_name (abfd, sect); | |
5594 | ||
5595 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5596 | *lbp = 32; | |
5597 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5598 | *lbp = 64; | |
5599 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5600 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5601 | } | |
5602 | ||
2e4ebe70 DJ |
5603 | static enum mips_abi |
5604 | global_mips_abi (void) | |
5605 | { | |
5606 | int i; | |
5607 | ||
5608 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5609 | if (mips_abi_strings[i] == mips_abi_string) | |
5610 | return (enum mips_abi) i; | |
5611 | ||
e2e0b3e5 | 5612 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5613 | } |
5614 | ||
29709017 DJ |
5615 | static void |
5616 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5617 | { | |
29709017 DJ |
5618 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5619 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5620 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5621 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5622 | |
5623 | /* If the size matches the full set of registers GDB traditionally | |
5624 | knows about, including floating point, for either 32-bit or | |
5625 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5626 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5627 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5628 | |
5629 | /* Otherwise we don't have a useful guess. */ | |
5630 | } | |
5631 | ||
f8b73d13 DJ |
5632 | static struct value * |
5633 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5634 | { | |
5635 | const int *reg_p = baton; | |
5636 | return value_of_register (*reg_p, frame); | |
5637 | } | |
5638 | ||
c2d11a7d | 5639 | static struct gdbarch * |
6d82d43b | 5640 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5641 | { |
c2d11a7d JM |
5642 | struct gdbarch *gdbarch; |
5643 | struct gdbarch_tdep *tdep; | |
5644 | int elf_flags; | |
2e4ebe70 | 5645 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5646 | int i, num_regs; |
8d5838b5 | 5647 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5648 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5649 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5650 | |
5651 | /* Check any target description for validity. */ | |
5652 | if (tdesc_has_registers (info.target_desc)) | |
5653 | { | |
5654 | static const char *const mips_gprs[] = { | |
5655 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5656 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5657 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5658 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5659 | }; | |
5660 | static const char *const mips_fprs[] = { | |
5661 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5662 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5663 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5664 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5665 | }; | |
5666 | ||
5667 | const struct tdesc_feature *feature; | |
5668 | int valid_p; | |
5669 | ||
5670 | feature = tdesc_find_feature (info.target_desc, | |
5671 | "org.gnu.gdb.mips.cpu"); | |
5672 | if (feature == NULL) | |
5673 | return NULL; | |
5674 | ||
5675 | tdesc_data = tdesc_data_alloc (); | |
5676 | ||
5677 | valid_p = 1; | |
5678 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5679 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5680 | mips_gprs[i]); | |
5681 | ||
5682 | ||
5683 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5684 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5685 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5686 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5687 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5688 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5689 | ||
5690 | if (!valid_p) | |
5691 | { | |
5692 | tdesc_data_cleanup (tdesc_data); | |
5693 | return NULL; | |
5694 | } | |
5695 | ||
5696 | feature = tdesc_find_feature (info.target_desc, | |
5697 | "org.gnu.gdb.mips.cp0"); | |
5698 | if (feature == NULL) | |
5699 | { | |
5700 | tdesc_data_cleanup (tdesc_data); | |
5701 | return NULL; | |
5702 | } | |
5703 | ||
5704 | valid_p = 1; | |
5705 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5706 | MIPS_EMBED_BADVADDR_REGNUM, | |
5707 | "badvaddr"); | |
5708 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5709 | MIPS_PS_REGNUM, "status"); | |
5710 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5711 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5712 | ||
5713 | if (!valid_p) | |
5714 | { | |
5715 | tdesc_data_cleanup (tdesc_data); | |
5716 | return NULL; | |
5717 | } | |
5718 | ||
5719 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5720 | backend is not prepared for that, though. */ | |
5721 | feature = tdesc_find_feature (info.target_desc, | |
5722 | "org.gnu.gdb.mips.fpu"); | |
5723 | if (feature == NULL) | |
5724 | { | |
5725 | tdesc_data_cleanup (tdesc_data); | |
5726 | return NULL; | |
5727 | } | |
5728 | ||
5729 | valid_p = 1; | |
5730 | for (i = 0; i < 32; i++) | |
5731 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5732 | i + MIPS_EMBED_FP0_REGNUM, | |
5733 | mips_fprs[i]); | |
5734 | ||
5735 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5736 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5737 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5738 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5739 | ||
5740 | if (!valid_p) | |
5741 | { | |
5742 | tdesc_data_cleanup (tdesc_data); | |
5743 | return NULL; | |
5744 | } | |
5745 | ||
5746 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5747 | when only 32-bit registers are provided. */ | |
5748 | } | |
c2d11a7d | 5749 | |
ec03c1ac AC |
5750 | /* First of all, extract the elf_flags, if available. */ |
5751 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5752 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5753 | else if (arches != NULL) |
5754 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5755 | else |
5756 | elf_flags = 0; | |
5757 | if (gdbarch_debug) | |
5758 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5759 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5760 | |
102182a9 | 5761 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5762 | switch ((elf_flags & EF_MIPS_ABI)) |
5763 | { | |
5764 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5765 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5766 | break; |
5767 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5768 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5769 | break; |
5770 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5771 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5772 | break; |
5773 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5774 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5775 | break; |
5776 | default: | |
acdb74a0 | 5777 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5778 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5779 | else |
ec03c1ac | 5780 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5781 | break; |
5782 | } | |
acdb74a0 | 5783 | |
caaa3122 | 5784 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5785 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5786 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5787 | |
dc305454 | 5788 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5789 | MIPS architecture (if there is one). */ |
5790 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5791 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5792 | |
32a6503c | 5793 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5794 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5795 | && info.bfd_arch_info != NULL |
5796 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5797 | { | |
5798 | switch (info.bfd_arch_info->mach) | |
5799 | { | |
5800 | case bfd_mach_mips3900: | |
ec03c1ac | 5801 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5802 | break; |
5803 | case bfd_mach_mips4100: | |
5804 | case bfd_mach_mips5000: | |
ec03c1ac | 5805 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5806 | break; |
1d06468c EZ |
5807 | case bfd_mach_mips8000: |
5808 | case bfd_mach_mips10000: | |
32a6503c KB |
5809 | /* On Irix, ELF64 executables use the N64 ABI. The |
5810 | pseudo-sections which describe the ABI aren't present | |
5811 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5812 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5813 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5814 | found_abi = MIPS_ABI_N64; |
28d169de | 5815 | else |
ec03c1ac | 5816 | found_abi = MIPS_ABI_N32; |
1d06468c | 5817 | break; |
bf64bfd6 AC |
5818 | } |
5819 | } | |
2e4ebe70 | 5820 | |
26c53e50 DJ |
5821 | /* Default 64-bit objects to N64 instead of O32. */ |
5822 | if (found_abi == MIPS_ABI_UNKNOWN | |
5823 | && info.abfd != NULL | |
5824 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5825 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5826 | found_abi = MIPS_ABI_N64; | |
5827 | ||
ec03c1ac AC |
5828 | if (gdbarch_debug) |
5829 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5830 | found_abi); | |
5831 | ||
5832 | /* What has the user specified from the command line? */ | |
5833 | wanted_abi = global_mips_abi (); | |
5834 | if (gdbarch_debug) | |
5835 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5836 | wanted_abi); | |
2e4ebe70 DJ |
5837 | |
5838 | /* Now that we have found what the ABI for this binary would be, | |
5839 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5840 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5841 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5842 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5843 | mips_abi = found_abi; | |
5844 | else | |
5845 | mips_abi = MIPS_ABI_O32; | |
5846 | if (gdbarch_debug) | |
5847 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5848 | mips_abi); | |
2e4ebe70 | 5849 | |
ec03c1ac | 5850 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5851 | if (gdbarch_debug) |
ec03c1ac | 5852 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
5853 | "mips_gdbarch_init: " |
5854 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 5855 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 5856 | |
8d5838b5 | 5857 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5858 | #ifdef HAVE_ELF |
5859 | if (info.abfd | |
5860 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5861 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5862 | Tag_GNU_MIPS_ABI_FP); | |
5863 | #endif /* HAVE_ELF */ | |
5864 | ||
8d5838b5 AC |
5865 | if (!mips_fpu_type_auto) |
5866 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5867 | else if (elf_fpu_type != 0) |
5868 | { | |
5869 | switch (elf_fpu_type) | |
5870 | { | |
5871 | case 1: | |
5872 | fpu_type = MIPS_FPU_DOUBLE; | |
5873 | break; | |
5874 | case 2: | |
5875 | fpu_type = MIPS_FPU_SINGLE; | |
5876 | break; | |
5877 | case 3: | |
5878 | default: | |
5879 | /* Soft float or unknown. */ | |
5880 | fpu_type = MIPS_FPU_NONE; | |
5881 | break; | |
5882 | } | |
5883 | } | |
8d5838b5 AC |
5884 | else if (info.bfd_arch_info != NULL |
5885 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5886 | switch (info.bfd_arch_info->mach) | |
5887 | { | |
5888 | case bfd_mach_mips3900: | |
5889 | case bfd_mach_mips4100: | |
5890 | case bfd_mach_mips4111: | |
a9d61c86 | 5891 | case bfd_mach_mips4120: |
8d5838b5 AC |
5892 | fpu_type = MIPS_FPU_NONE; |
5893 | break; | |
5894 | case bfd_mach_mips4650: | |
5895 | fpu_type = MIPS_FPU_SINGLE; | |
5896 | break; | |
5897 | default: | |
5898 | fpu_type = MIPS_FPU_DOUBLE; | |
5899 | break; | |
5900 | } | |
5901 | else if (arches != NULL) | |
5902 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5903 | else | |
5904 | fpu_type = MIPS_FPU_DOUBLE; | |
5905 | if (gdbarch_debug) | |
5906 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5907 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5908 | |
29709017 DJ |
5909 | /* Check for blatant incompatibilities. */ |
5910 | ||
5911 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5912 | ABI. */ | |
5913 | if (info.target_desc | |
5914 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5915 | && mips_abi != MIPS_ABI_EABI32 | |
5916 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5917 | { |
5918 | if (tdesc_data != NULL) | |
5919 | tdesc_data_cleanup (tdesc_data); | |
5920 | return NULL; | |
5921 | } | |
29709017 | 5922 | |
025bb325 | 5923 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
5924 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
5925 | arches != NULL; | |
5926 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5927 | { | |
5928 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5929 | using. */ |
9103eae0 | 5930 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5931 | continue; |
9103eae0 | 5932 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5933 | continue; |
719ec221 AC |
5934 | /* Need to be pedantic about which register virtual size is |
5935 | used. */ | |
5936 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5937 | != mips64_transfers_32bit_regs_p) | |
5938 | continue; | |
8d5838b5 AC |
5939 | /* Be pedantic about which FPU is selected. */ |
5940 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5941 | continue; | |
f8b73d13 DJ |
5942 | |
5943 | if (tdesc_data != NULL) | |
5944 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5945 | return arches->gdbarch; |
c2d11a7d JM |
5946 | } |
5947 | ||
102182a9 | 5948 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5949 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5950 | gdbarch = gdbarch_alloc (&info, tdep); | |
5951 | tdep->elf_flags = elf_flags; | |
719ec221 | 5952 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5953 | tdep->found_abi = found_abi; |
5954 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5955 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5956 | tdep->register_size_valid_p = 0; |
5957 | tdep->register_size = 0; | |
50e8a0d5 HZ |
5958 | tdep->gregset = NULL; |
5959 | tdep->gregset64 = NULL; | |
5960 | tdep->fpregset = NULL; | |
5961 | tdep->fpregset64 = NULL; | |
29709017 DJ |
5962 | |
5963 | if (info.target_desc) | |
5964 | { | |
5965 | /* Some useful properties can be inferred from the target. */ | |
5966 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5967 | { | |
5968 | tdep->register_size_valid_p = 1; | |
5969 | tdep->register_size = 4; | |
5970 | } | |
5971 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5972 | { | |
5973 | tdep->register_size_valid_p = 1; | |
5974 | tdep->register_size = 8; | |
5975 | } | |
5976 | } | |
c2d11a7d | 5977 | |
102182a9 | 5978 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5979 | set_gdbarch_short_bit (gdbarch, 16); |
5980 | set_gdbarch_int_bit (gdbarch, 32); | |
5981 | set_gdbarch_float_bit (gdbarch, 32); | |
5982 | set_gdbarch_double_bit (gdbarch, 64); | |
5983 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5984 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5985 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5986 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5987 | |
175ff332 HZ |
5988 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
5989 | mips_ax_pseudo_register_collect); | |
5990 | set_gdbarch_ax_pseudo_register_push_stack | |
5991 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
5992 | ||
6d82d43b | 5993 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5994 | mips_elf_make_msymbol_special); |
5995 | ||
16e109ca | 5996 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5997 | { |
16e109ca | 5998 | const char **reg_names; |
56cea623 AC |
5999 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
6000 | struct mips_regnum); | |
f8b73d13 DJ |
6001 | if (tdesc_has_registers (info.target_desc)) |
6002 | { | |
6003 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6004 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6005 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6006 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6007 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6008 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6009 | regnum->fp_control_status = 70; | |
6010 | regnum->fp_implementation_revision = 71; | |
6011 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
6012 | reg_names = NULL; | |
6013 | } | |
6014 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
6015 | { |
6016 | regnum->fp0 = 32; | |
6017 | regnum->pc = 64; | |
6018 | regnum->cause = 65; | |
6019 | regnum->badvaddr = 66; | |
6020 | regnum->hi = 67; | |
6021 | regnum->lo = 68; | |
6022 | regnum->fp_control_status = 69; | |
6023 | regnum->fp_implementation_revision = 70; | |
6024 | num_regs = 71; | |
16e109ca | 6025 | reg_names = mips_irix_reg_names; |
56cea623 AC |
6026 | } |
6027 | else | |
6028 | { | |
6029 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6030 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6031 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6032 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6033 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6034 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6035 | regnum->fp_control_status = 70; | |
6036 | regnum->fp_implementation_revision = 71; | |
6037 | num_regs = 90; | |
16e109ca AC |
6038 | if (info.bfd_arch_info != NULL |
6039 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6040 | reg_names = mips_tx39_reg_names; | |
6041 | else | |
6042 | reg_names = mips_generic_reg_names; | |
56cea623 | 6043 | } |
3e8c568d | 6044 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
fb14de7b | 6045 | replaced by gdbarch_read_pc? */ |
f10683bb MH |
6046 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
6047 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
6048 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
6049 | set_gdbarch_num_regs (gdbarch, num_regs); | |
6050 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 6051 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 6052 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
6053 | tdep->mips_processor_reg_names = reg_names; |
6054 | tdep->regnum = regnum; | |
56cea623 | 6055 | } |
fe29b929 | 6056 | |
0dadbba0 | 6057 | switch (mips_abi) |
c2d11a7d | 6058 | { |
0dadbba0 | 6059 | case MIPS_ABI_O32: |
25ab4790 | 6060 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6061 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 6062 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6063 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6064 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6065 | set_gdbarch_long_bit (gdbarch, 32); |
6066 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6067 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6068 | break; | |
0dadbba0 | 6069 | case MIPS_ABI_O64: |
25ab4790 | 6070 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 6071 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 6072 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6073 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6074 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6075 | set_gdbarch_long_bit (gdbarch, 32); |
6076 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6077 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6078 | break; | |
0dadbba0 | 6079 | case MIPS_ABI_EABI32: |
25ab4790 | 6080 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6081 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6082 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6083 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6084 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6085 | set_gdbarch_long_bit (gdbarch, 32); |
6086 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6087 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6088 | break; | |
0dadbba0 | 6089 | case MIPS_ABI_EABI64: |
25ab4790 | 6090 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6091 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6092 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6093 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6094 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6095 | set_gdbarch_long_bit (gdbarch, 64); |
6096 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6097 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6098 | break; | |
0dadbba0 | 6099 | case MIPS_ABI_N32: |
25ab4790 | 6100 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6101 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6102 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6103 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6104 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6105 | set_gdbarch_long_bit (gdbarch, 32); |
6106 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6107 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6108 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6109 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
6110 | break; |
6111 | case MIPS_ABI_N64: | |
25ab4790 | 6112 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6113 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6114 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6115 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6116 | tdep->default_mask_address_p = 0; |
6117 | set_gdbarch_long_bit (gdbarch, 64); | |
6118 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6119 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6120 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6121 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 6122 | break; |
c2d11a7d | 6123 | default: |
e2e0b3e5 | 6124 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
6125 | } |
6126 | ||
22e47e37 FF |
6127 | /* GCC creates a pseudo-section whose name specifies the size of |
6128 | longs, since -mlong32 or -mlong64 may be used independent of | |
6129 | other options. How those options affect pointer sizes is ABI and | |
6130 | architecture dependent, so use them to override the default sizes | |
6131 | set by the ABI. This table shows the relationship between ABI, | |
6132 | -mlongXX, and size of pointers: | |
6133 | ||
6134 | ABI -mlongXX ptr bits | |
6135 | --- -------- -------- | |
6136 | o32 32 32 | |
6137 | o32 64 32 | |
6138 | n32 32 32 | |
6139 | n32 64 64 | |
6140 | o64 32 32 | |
6141 | o64 64 64 | |
6142 | n64 32 32 | |
6143 | n64 64 64 | |
6144 | eabi32 32 32 | |
6145 | eabi32 64 32 | |
6146 | eabi64 32 32 | |
6147 | eabi64 64 64 | |
6148 | ||
6149 | Note that for o32 and eabi32, pointers are always 32 bits | |
6150 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 6151 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
6152 | |
6153 | if (info.abfd != NULL) | |
6154 | { | |
6155 | int long_bit = 0; | |
6156 | ||
6157 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
6158 | if (long_bit) | |
6159 | { | |
6160 | set_gdbarch_long_bit (gdbarch, long_bit); | |
6161 | switch (mips_abi) | |
6162 | { | |
6163 | case MIPS_ABI_O32: | |
6164 | case MIPS_ABI_EABI32: | |
6165 | break; | |
6166 | case MIPS_ABI_N32: | |
6167 | case MIPS_ABI_O64: | |
6168 | case MIPS_ABI_N64: | |
6169 | case MIPS_ABI_EABI64: | |
6170 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
6171 | break; | |
6172 | default: | |
6173 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
6174 | } | |
6175 | } | |
6176 | } | |
6177 | ||
a5ea2558 AC |
6178 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6179 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6180 | comment: | |
6181 | ||
6182 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6183 | flag in object files because to do so would make it impossible to | |
102182a9 | 6184 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6185 | unnecessarily restrictive. |
361d1df0 | 6186 | |
a5ea2558 AC |
6187 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6188 | but to set this flag before gcc is built with such multilibs will | |
6189 | break too many systems.'' | |
6190 | ||
6191 | But even more unhelpfully, the default linker output target for | |
6192 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6193 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6194 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6195 | this flag to detect 32-bit mode would do the wrong thing given |
6196 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6197 | as 32-bit programs by default. */ |
a5ea2558 | 6198 | |
6c997a34 | 6199 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6200 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 6201 | |
102182a9 MS |
6202 | /* Add/remove bits from an address. The MIPS needs be careful to |
6203 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6204 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6205 | ||
58dfe9ff AC |
6206 | /* Unwind the frame. */ |
6207 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 6208 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 6209 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 6210 | |
102182a9 | 6211 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6212 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6213 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6214 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
6215 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
6216 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6217 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6218 | |
025bb325 | 6219 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 6220 | |
9710e734 AC |
6221 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6222 | replaced by a command, and all targets will default to on stack | |
6223 | (regardless of the stack's execute status). */ | |
6224 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6225 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6226 | |
87783b8b AC |
6227 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6228 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6229 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6230 | ||
f7b9e9fc AC |
6231 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6232 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6233 | |
6234 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6235 | |
97ab0fdd MR |
6236 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6237 | ||
fc0c74b1 AC |
6238 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6239 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6240 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6241 | |
a4b8ebc8 | 6242 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6243 | |
e11c53d2 | 6244 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6245 | |
9dae60cc UW |
6246 | if (mips_abi == MIPS_ABI_N32) |
6247 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
6248 | else if (mips_abi == MIPS_ABI_N64) | |
6249 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
6250 | else | |
6251 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 6252 | |
d92524f1 PM |
6253 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6254 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6255 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6256 | being used as guards for target_stopped_by_watchpoint, why not have |
6257 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6258 | is sitting on? */ |
6259 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6260 | ||
e7d6a6d2 | 6261 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6262 | |
025bb325 MS |
6263 | set_gdbarch_single_step_through_delay (gdbarch, |
6264 | mips_single_step_through_delay); | |
3352ef37 | 6265 | |
0d5de010 DJ |
6266 | /* Virtual tables. */ |
6267 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6268 | ||
29709017 DJ |
6269 | mips_register_g_packet_guesses (gdbarch); |
6270 | ||
6de918a6 | 6271 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6272 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6273 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6274 | |
5792a79b | 6275 | /* Unwind the frame. */ |
b8a22b94 DJ |
6276 | dwarf2_append_unwinders (gdbarch); |
6277 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6278 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6279 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6280 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6281 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6282 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6283 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6284 | |
f8b73d13 DJ |
6285 | if (tdesc_data) |
6286 | { | |
6287 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6288 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6289 | |
6290 | /* Override the normal target description methods to handle our | |
6291 | dual real and pseudo registers. */ | |
6292 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
6293 | set_gdbarch_register_reggroup_p (gdbarch, |
6294 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
6295 | |
6296 | num_regs = gdbarch_num_regs (gdbarch); | |
6297 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6298 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6299 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6300 | } | |
6301 | ||
6302 | /* Add ABI-specific aliases for the registers. */ | |
6303 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6304 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6305 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6306 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6307 | else | |
6308 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6309 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6310 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6311 | ||
6312 | /* Add some other standard aliases. */ | |
6313 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6314 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6315 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6316 | ||
865093a3 AR |
6317 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6318 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6319 | value_of_mips_user_reg, | |
6320 | &mips_numeric_register_aliases[i].regnum); | |
6321 | ||
4b9b3959 AC |
6322 | return gdbarch; |
6323 | } | |
6324 | ||
2e4ebe70 | 6325 | static void |
6d82d43b | 6326 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6327 | { |
6328 | struct gdbarch_info info; | |
6329 | ||
6330 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6331 | mips_gdbarch_init will take care of the rest. */ | |
6332 | gdbarch_info_init (&info); | |
6333 | gdbarch_update_p (info); | |
6334 | } | |
6335 | ||
ad188201 KB |
6336 | /* Print out which MIPS ABI is in use. */ |
6337 | ||
6338 | static void | |
1f8ca57c JB |
6339 | show_mips_abi (struct ui_file *file, |
6340 | int from_tty, | |
6341 | struct cmd_list_element *ignored_cmd, | |
6342 | const char *ignored_value) | |
ad188201 | 6343 | { |
1cf3db46 | 6344 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6345 | fprintf_filtered |
6346 | (file, | |
6347 | "The MIPS ABI is unknown because the current architecture " | |
6348 | "is not MIPS.\n"); | |
ad188201 KB |
6349 | else |
6350 | { | |
6351 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6352 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6353 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6354 | ||
6355 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6356 | fprintf_filtered |
6357 | (file, | |
6358 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6359 | actual_abi_str); |
ad188201 | 6360 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6361 | fprintf_filtered |
6362 | (file, | |
6363 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6364 | actual_abi_str); |
ad188201 KB |
6365 | else |
6366 | { | |
6367 | /* Probably shouldn't happen... */ | |
025bb325 MS |
6368 | fprintf_filtered (file, |
6369 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
6370 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 6371 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6372 | } |
6373 | } | |
6374 | } | |
6375 | ||
4b9b3959 | 6376 | static void |
72a155b4 | 6377 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6378 | { |
72a155b4 | 6379 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6380 | if (tdep != NULL) |
c2d11a7d | 6381 | { |
acdb74a0 AC |
6382 | int ef_mips_arch; |
6383 | int ef_mips_32bitmode; | |
f49e4e6d | 6384 | /* Determine the ISA. */ |
acdb74a0 AC |
6385 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6386 | { | |
6387 | case E_MIPS_ARCH_1: | |
6388 | ef_mips_arch = 1; | |
6389 | break; | |
6390 | case E_MIPS_ARCH_2: | |
6391 | ef_mips_arch = 2; | |
6392 | break; | |
6393 | case E_MIPS_ARCH_3: | |
6394 | ef_mips_arch = 3; | |
6395 | break; | |
6396 | case E_MIPS_ARCH_4: | |
93d56215 | 6397 | ef_mips_arch = 4; |
acdb74a0 AC |
6398 | break; |
6399 | default: | |
93d56215 | 6400 | ef_mips_arch = 0; |
acdb74a0 AC |
6401 | break; |
6402 | } | |
f49e4e6d | 6403 | /* Determine the size of a pointer. */ |
acdb74a0 | 6404 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6405 | fprintf_unfiltered (file, |
6406 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6407 | tdep->elf_flags); |
4b9b3959 | 6408 | fprintf_unfiltered (file, |
acdb74a0 AC |
6409 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6410 | ef_mips_32bitmode); | |
6411 | fprintf_unfiltered (file, | |
6412 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6413 | ef_mips_arch); | |
6414 | fprintf_unfiltered (file, | |
6415 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6416 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 6417 | fprintf_unfiltered (file, |
025bb325 MS |
6418 | "mips_dump_tdep: " |
6419 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6420 | mips_mask_address_p (tdep), |
4014092b | 6421 | tdep->default_mask_address_p); |
c2d11a7d | 6422 | } |
4b9b3959 AC |
6423 | fprintf_unfiltered (file, |
6424 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6425 | MIPS_DEFAULT_FPU_TYPE, | |
6426 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6427 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6428 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6429 | : "???")); | |
74ed0bb4 MD |
6430 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6431 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6432 | fprintf_unfiltered (file, |
6433 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6434 | MIPS_FPU_TYPE (gdbarch), |
6435 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6436 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6437 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6438 | : "???")); |
c2d11a7d JM |
6439 | } |
6440 | ||
025bb325 | 6441 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6442 | |
c906108c | 6443 | void |
acdb74a0 | 6444 | _initialize_mips_tdep (void) |
c906108c SS |
6445 | { |
6446 | static struct cmd_list_element *mipsfpulist = NULL; | |
6447 | struct cmd_list_element *c; | |
6448 | ||
6d82d43b | 6449 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6450 | if (MIPS_ABI_LAST + 1 |
6451 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6452 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6453 | |
4b9b3959 | 6454 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6455 | |
8d5f9dcb DJ |
6456 | mips_pdr_data = register_objfile_data (); |
6457 | ||
4eb0ad19 DJ |
6458 | /* Create feature sets with the appropriate properties. The values |
6459 | are not important. */ | |
6460 | mips_tdesc_gp32 = allocate_target_description (); | |
6461 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6462 | ||
6463 | mips_tdesc_gp64 = allocate_target_description (); | |
6464 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6465 | ||
025bb325 | 6466 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 6467 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 6468 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6469 | &setmipscmdlist, "set mips ", 0, &setlist); |
6470 | ||
6471 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6472 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6473 | &showmipscmdlist, "show mips ", 0, &showlist); |
6474 | ||
025bb325 | 6475 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6476 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6477 | &mips_abi_string, _("\ | |
6478 | Set the MIPS ABI used by this program."), _("\ | |
6479 | Show the MIPS ABI used by this program."), _("\ | |
6480 | This option can be set to one of:\n\ | |
6481 | auto - the default ABI associated with the current binary\n\ | |
6482 | o32\n\ | |
6483 | o64\n\ | |
6484 | n32\n\ | |
6485 | n64\n\ | |
6486 | eabi32\n\ | |
6487 | eabi64"), | |
6488 | mips_abi_update, | |
6489 | show_mips_abi, | |
6490 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6491 | |
c906108c SS |
6492 | /* Let the user turn off floating point and set the fence post for |
6493 | heuristic_proc_start. */ | |
6494 | ||
6495 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6496 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6497 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6498 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6499 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6500 | &mipsfpulist); |
6501 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6502 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6503 | &mipsfpulist); |
6504 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6505 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6506 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6507 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6508 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6509 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6510 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6511 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6512 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6513 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6514 | &mipsfpulist); |
6515 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6516 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6517 | &showlist); |
6518 | ||
c906108c SS |
6519 | /* We really would like to have both "0" and "unlimited" work, but |
6520 | command.c doesn't deal with that. So make it a var_zinteger | |
6521 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6522 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6523 | &heuristic_fence_post, _("\ |
6524 | Set the distance searched for the start of a function."), _("\ | |
6525 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6526 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6527 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6528 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6529 | reinit_frame_cache_sfunc, |
025bb325 MS |
6530 | NULL, /* FIXME: i18n: The distance searched for |
6531 | the start of a function is %s. */ | |
6bcadd06 | 6532 | &setlist, &showlist); |
c906108c SS |
6533 | |
6534 | /* Allow the user to control whether the upper bits of 64-bit | |
6535 | addresses should be zeroed. */ | |
7915a72c AC |
6536 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6537 | &mask_address_var, _("\ | |
6538 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6539 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 6540 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 6541 | allow GDB to determine the correct value."), |
08546159 AC |
6542 | NULL, show_mask_address, |
6543 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6544 | |
6545 | /* Allow the user to control the size of 32 bit registers within the | |
6546 | raw remote packet. */ | |
b3f42336 | 6547 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6548 | &mips64_transfers_32bit_regs_p, _("\ |
6549 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6550 | _("\ | |
6551 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6552 | _("\ | |
719ec221 AC |
6553 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6554 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6555 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6556 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
6557 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
6558 | MIPS target that transfers 32-bit | |
6559 | quantities is %s. */ | |
7915a72c | 6560 | &setlist, &showlist); |
9ace0497 | 6561 | |
025bb325 | 6562 | /* Debug this files internals. */ |
6bcadd06 | 6563 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6564 | &mips_debug, _("\ |
6565 | Set mips debugging."), _("\ | |
6566 | Show mips debugging."), _("\ | |
6567 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6568 | NULL, |
025bb325 MS |
6569 | NULL, /* FIXME: i18n: Mips debugging is |
6570 | currently %s. */ | |
6bcadd06 | 6571 | &setdebuglist, &showdebuglist); |
c906108c | 6572 | } |