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7d9884b9 | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
97e091b2 | 2 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996 |
0434c1a0 | 3 | Free Software Foundation, Inc. |
bd5635a1 RP |
4 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
5 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
361bf6ee | 9 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 10 | it under the terms of the GNU General Public License as published by |
361bf6ee JG |
11 | the Free Software Foundation; either version 2 of the License, or |
12 | (at your option) any later version. | |
bd5635a1 | 13 | |
361bf6ee | 14 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
361bf6ee | 20 | along with this program; if not, write to the Free Software |
09af5868 | 21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
bd5635a1 | 22 | |
bd5635a1 | 23 | #include "defs.h" |
09af5868 | 24 | #include "gdb_string.h" |
bd5635a1 RP |
25 | #include "frame.h" |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "value.h" | |
29 | #include "gdbcmd.h" | |
ef08856f | 30 | #include "language.h" |
bd5635a1 | 31 | #include "gdbcore.h" |
62a469e1 SG |
32 | #include "symfile.h" |
33 | #include "objfiles.h" | |
3fed1c4a | 34 | #include "gdbtypes.h" |
28444bf3 | 35 | #include "target.h" |
bd5635a1 | 36 | |
ee5fb959 JK |
37 | #include "opcode/mips.h" |
38 | ||
28444bf3 | 39 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
70126bf9 KH |
40 | |
41 | /* FIXME: Put this declaration in frame.h. */ | |
42 | extern struct obstack frame_cache_obstack; | |
28444bf3 DP |
43 | |
44 | /* FIXME! this code assumes 4-byte instructions. */ | |
96431497 MA |
45 | #define MIPS_INSTLEN 4 /* Length of an instruction */ |
46 | #define MIPS_NUMREGS 32 /* Number of integer or float registers */ | |
47 | typedef unsigned long t_inst; /* Integer big enough to hold an instruction */ | |
28444bf3 | 48 | |
002a422b | 49 | #if 0 |
ee5fb959 | 50 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
002a422b | 51 | #endif |
ee5fb959 | 52 | |
28444bf3 DP |
53 | static int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *)); |
54 | ||
f2bf454e FF |
55 | static void mips_print_register PARAMS ((int, int)); |
56 | ||
57 | static mips_extra_func_info_t | |
58 | heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *)); | |
59 | ||
60 | static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR)); | |
61 | ||
28444bf3 | 62 | static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int)); |
f2bf454e | 63 | |
e4dbd248 PS |
64 | static void mips_set_fpu_command PARAMS ((char *, int, |
65 | struct cmd_list_element *)); | |
66 | ||
67 | static void mips_show_fpu_command PARAMS ((char *, int, | |
68 | struct cmd_list_element *)); | |
69 | ||
9f9f94aa SS |
70 | void mips_set_processor_type_command PARAMS ((char *, int)); |
71 | ||
1d9489c1 JK |
72 | int mips_set_processor_type PARAMS ((char *)); |
73 | ||
74 | static void mips_show_processor_type_command PARAMS ((char *, int)); | |
75 | ||
9f9f94aa SS |
76 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, |
77 | struct cmd_list_element *)); | |
78 | ||
f2bf454e FF |
79 | static mips_extra_func_info_t |
80 | find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info *next_frame)); | |
81 | ||
82 | static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc, | |
83 | mips_extra_func_info_t proc_desc)); | |
84 | ||
9f9f94aa SS |
85 | /* This value is the model of MIPS in use. It is derived from the value |
86 | of the PrID register. */ | |
87 | ||
88 | char *mips_processor_type; | |
89 | ||
90 | char *tmp_mips_processor_type; | |
91 | ||
c2a0f1cb ILT |
92 | /* Some MIPS boards don't support floating point, so we permit the |
93 | user to turn it off. */ | |
9f9f94aa | 94 | |
e4dbd248 PS |
95 | enum mips_fpu_type mips_fpu; |
96 | ||
97 | static char *mips_fpu_string; | |
c2a0f1cb | 98 | |
9f9f94aa SS |
99 | /* A set of original names, to be used when restoring back to generic |
100 | registers from a specific set. */ | |
101 | ||
102 | char *mips_generic_reg_names[] = REGISTER_NAMES; | |
103 | ||
104 | /* Names of IDT R3041 registers. */ | |
105 | ||
106 | char *mips_r3041_reg_names[] = { | |
107 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
108 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
109 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
110 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
111 | "sr", "lo", "hi", "bad", "cause","pc", | |
112 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
113 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
114 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
115 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
116 | "fsr", "fir", "fp", "", | |
117 | "", "", "bus", "ccfg", "", "", "", "", | |
118 | "", "", "port", "cmp", "", "", "epc", "prid", | |
119 | }; | |
120 | ||
121 | /* Names of IDT R3051 registers. */ | |
122 | ||
123 | char *mips_r3051_reg_names[] = { | |
124 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
125 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
126 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
127 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
128 | "sr", "lo", "hi", "bad", "cause","pc", | |
129 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
130 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
131 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
132 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
133 | "fsr", "fir", "fp", "", | |
134 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
135 | "", "", "ehi", "", "", "", "epc", "prid", | |
136 | }; | |
137 | ||
138 | /* Names of IDT R3081 registers. */ | |
139 | ||
140 | char *mips_r3081_reg_names[] = { | |
141 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
142 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
143 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
144 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
145 | "sr", "lo", "hi", "bad", "cause","pc", | |
146 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
147 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
148 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
149 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
150 | "fsr", "fir", "fp", "", | |
151 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
152 | "", "", "ehi", "", "", "", "epc", "prid", | |
153 | }; | |
154 | ||
e4dbd248 PS |
155 | /* Names of LSI 33k registers. */ |
156 | ||
157 | char *mips_lsi33k_reg_names[] = { | |
158 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
159 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
160 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
161 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
162 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
163 | "dcic", "bpc", "bda", "", "", "", "", "", | |
164 | "", "", "", "", "", "", "", "", | |
165 | "", "", "", "", "", "", "", "", | |
166 | "", "", "", "", "", "", "", "", | |
167 | "", "", "", "", | |
168 | "", "", "", "", "", "", "", "", | |
169 | "", "", "", "", "", "", "", "", | |
170 | }; | |
171 | ||
9f9f94aa SS |
172 | struct { |
173 | char *name; | |
174 | char **regnames; | |
175 | } mips_processor_type_table[] = { | |
176 | { "generic", mips_generic_reg_names }, | |
177 | { "r3041", mips_r3041_reg_names }, | |
178 | { "r3051", mips_r3051_reg_names }, | |
179 | { "r3071", mips_r3081_reg_names }, | |
180 | { "r3081", mips_r3081_reg_names }, | |
e4dbd248 | 181 | { "lsi33k", mips_lsi33k_reg_names }, |
9f9f94aa SS |
182 | { NULL, NULL } |
183 | }; | |
184 | ||
3127785a RP |
185 | /* Heuristic_proc_start may hunt through the text section for a long |
186 | time across a 2400 baud serial line. Allows the user to limit this | |
187 | search. */ | |
9f9f94aa | 188 | |
3127785a RP |
189 | static unsigned int heuristic_fence_post = 0; |
190 | ||
0f552c5f | 191 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
28444bf3 | 192 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ |
0f552c5f JG |
193 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
194 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
195 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
196 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
197 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
198 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
199 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
200 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
bd5635a1 | 201 | #define _PROC_MAGIC_ 0x0F0F0F0F |
0f552c5f JG |
202 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
203 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
bd5635a1 RP |
204 | |
205 | struct linked_proc_info | |
206 | { | |
207 | struct mips_extra_func_info info; | |
208 | struct linked_proc_info *next; | |
dac4929a | 209 | } *linked_proc_desc_table = NULL; |
bd5635a1 | 210 | |
f2bf454e FF |
211 | |
212 | /* This returns the PC of the first inst after the prologue. If we can't | |
213 | find the prologue, then return 0. */ | |
214 | ||
215 | static CORE_ADDR | |
216 | after_prologue (pc, proc_desc) | |
217 | CORE_ADDR pc; | |
218 | mips_extra_func_info_t proc_desc; | |
219 | { | |
220 | struct symtab_and_line sal; | |
221 | CORE_ADDR func_addr, func_end; | |
222 | ||
223 | if (!proc_desc) | |
224 | proc_desc = find_proc_desc (pc, NULL); | |
225 | ||
226 | if (proc_desc) | |
227 | { | |
228 | /* If function is frameless, then we need to do it the hard way. I | |
229 | strongly suspect that frameless always means prologueless... */ | |
230 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
231 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
232 | return 0; | |
233 | } | |
234 | ||
235 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
236 | return 0; /* Unknown */ | |
237 | ||
238 | sal = find_pc_line (func_addr, 0); | |
239 | ||
240 | if (sal.end < func_end) | |
241 | return sal.end; | |
242 | ||
243 | /* The line after the prologue is after the end of the function. In this | |
244 | case, tell the caller to find the prologue the hard way. */ | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
70126bf9 KH |
249 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
250 | NULL). */ | |
251 | ||
252 | void | |
253 | mips_find_saved_regs (fci) | |
9f9f94aa | 254 | struct frame_info *fci; |
70126bf9 KH |
255 | { |
256 | int ireg; | |
257 | CORE_ADDR reg_position; | |
258 | /* r0 bit means kernel trap */ | |
259 | int kernel_trap; | |
260 | /* What registers have been saved? Bitmasks. */ | |
261 | unsigned long gen_mask, float_mask; | |
262 | mips_extra_func_info_t proc_desc; | |
263 | ||
264 | fci->saved_regs = (struct frame_saved_regs *) | |
265 | obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs)); | |
266 | memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs)); | |
267 | ||
e4dbd248 PS |
268 | /* If it is the frame for sigtramp, the saved registers are located |
269 | in a sigcontext structure somewhere on the stack. | |
270 | If the stack layout for sigtramp changes we might have to change these | |
271 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
272 | #ifndef SIGFRAME_BASE | |
273 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
274 | above the sigtramp frame. */ | |
28444bf3 DP |
275 | #define SIGFRAME_BASE MIPS_REGSIZE |
276 | /* FIXME! Are these correct?? */ | |
277 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
278 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
279 | #define SIGFRAME_FPREGSAVE_OFF \ | |
280 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
e4dbd248 PS |
281 | #endif |
282 | #ifndef SIGFRAME_REG_SIZE | |
28444bf3 DP |
283 | /* FIXME! Is this correct?? */ |
284 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
e4dbd248 PS |
285 | #endif |
286 | if (fci->signal_handler_caller) | |
287 | { | |
28444bf3 | 288 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
289 | { |
290 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF | |
291 | + ireg * SIGFRAME_REG_SIZE; | |
292 | fci->saved_regs->regs[ireg] = reg_position; | |
293 | } | |
28444bf3 | 294 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
295 | { |
296 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF | |
297 | + ireg * SIGFRAME_REG_SIZE; | |
298 | fci->saved_regs->regs[FP0_REGNUM + ireg] = reg_position; | |
299 | } | |
300 | fci->saved_regs->regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
301 | return; | |
302 | } | |
303 | ||
70126bf9 KH |
304 | proc_desc = fci->proc_desc; |
305 | if (proc_desc == NULL) | |
306 | /* I'm not sure how/whether this can happen. Normally when we can't | |
307 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
308 | and set the saved_regs right away. */ | |
309 | return; | |
310 | ||
311 | kernel_trap = PROC_REG_MASK(proc_desc) & 1; | |
312 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); | |
313 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); | |
314 | ||
315 | if (/* In any frame other than the innermost, we assume that all | |
316 | registers have been saved. This assumes that all register | |
317 | saves in a function happen before the first function | |
318 | call. */ | |
319 | fci->next == NULL | |
320 | ||
321 | /* In a dummy frame we know exactly where things are saved. */ | |
322 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
323 | ||
f2bf454e FF |
324 | /* Don't bother unless we are inside a function prologue. Outside the |
325 | prologue, we know where everything is. */ | |
326 | ||
327 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) | |
328 | ||
70126bf9 KH |
329 | /* Not sure exactly what kernel_trap means, but if it means |
330 | the kernel saves the registers without a prologue doing it, | |
331 | we better not examine the prologue to see whether registers | |
332 | have been saved yet. */ | |
333 | && !kernel_trap) | |
334 | { | |
335 | /* We need to figure out whether the registers that the proc_desc | |
336 | claims are saved have been saved yet. */ | |
337 | ||
338 | CORE_ADDR addr; | |
339 | int status; | |
28444bf3 DP |
340 | char buf[MIPS_INSTLEN]; |
341 | t_inst inst; | |
70126bf9 KH |
342 | |
343 | /* Bitmasks; set if we have found a save for the register. */ | |
344 | unsigned long gen_save_found = 0; | |
345 | unsigned long float_save_found = 0; | |
346 | ||
347 | for (addr = PROC_LOW_ADDR (proc_desc); | |
348 | addr < fci->pc /*&& (gen_mask != gen_save_found | |
349 | || float_mask != float_save_found)*/; | |
28444bf3 | 350 | addr += MIPS_INSTLEN) |
70126bf9 | 351 | { |
28444bf3 | 352 | status = read_memory_nobpt (addr, buf, MIPS_INSTLEN); |
70126bf9 KH |
353 | if (status) |
354 | memory_error (status, addr); | |
28444bf3 | 355 | inst = extract_unsigned_integer (buf, MIPS_INSTLEN); |
70126bf9 KH |
356 | if (/* sw reg,n($sp) */ |
357 | (inst & 0xffe00000) == 0xafa00000 | |
358 | ||
359 | /* sw reg,n($r30) */ | |
360 | || (inst & 0xffe00000) == 0xafc00000 | |
361 | ||
362 | /* sd reg,n($sp) */ | |
363 | || (inst & 0xffe00000) == 0xffa00000) | |
364 | { | |
365 | /* It might be possible to use the instruction to | |
366 | find the offset, rather than the code below which | |
367 | is based on things being in a certain order in the | |
368 | frame, but figuring out what the instruction's offset | |
369 | is relative to might be a little tricky. */ | |
370 | int reg = (inst & 0x001f0000) >> 16; | |
371 | gen_save_found |= (1 << reg); | |
372 | } | |
373 | else if (/* swc1 freg,n($sp) */ | |
374 | (inst & 0xffe00000) == 0xe7a00000 | |
375 | ||
376 | /* swc1 freg,n($r30) */ | |
377 | || (inst & 0xffe00000) == 0xe7c00000 | |
378 | ||
379 | /* sdc1 freg,n($sp) */ | |
380 | || (inst & 0xffe00000) == 0xf7a00000) | |
381 | ||
382 | { | |
383 | int reg = ((inst & 0x001f0000) >> 16); | |
384 | float_save_found |= (1 << reg); | |
385 | } | |
386 | } | |
387 | gen_mask = gen_save_found; | |
388 | float_mask = float_save_found; | |
389 | } | |
390 | ||
391 | /* Fill in the offsets for the registers which gen_mask says | |
392 | were saved. */ | |
393 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
28444bf3 | 394 | for (ireg= MIPS_NUMREGS-1; gen_mask; --ireg, gen_mask <<= 1) |
70126bf9 KH |
395 | if (gen_mask & 0x80000000) |
396 | { | |
397 | fci->saved_regs->regs[ireg] = reg_position; | |
398 | reg_position -= MIPS_REGSIZE; | |
399 | } | |
400 | /* Fill in the offsets for the registers which float_mask says | |
401 | were saved. */ | |
402 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
403 | ||
404 | /* The freg_offset points to where the first *double* register | |
405 | is saved. So skip to the high-order word. */ | |
28444bf3 DP |
406 | if (! GDB_TARGET_IS_MIPS64) |
407 | reg_position += 4; | |
408 | ||
409 | /* FIXME! this code looks scary... | |
410 | * Looks like it's trying to do stuff with a register, | |
411 | * but .... ??? | |
412 | */ | |
413 | for (ireg = MIPS_NUMREGS-1; float_mask; --ireg, float_mask <<= 1) | |
70126bf9 KH |
414 | if (float_mask & 0x80000000) |
415 | { | |
416 | fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position; | |
417 | reg_position -= MIPS_REGSIZE; | |
418 | } | |
419 | ||
420 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; | |
421 | } | |
bd5635a1 | 422 | |
28444bf3 | 423 | static CORE_ADDR |
bd5635a1 | 424 | read_next_frame_reg(fi, regno) |
9f9f94aa | 425 | struct frame_info *fi; |
bd5635a1 RP |
426 | int regno; |
427 | { | |
bd5635a1 | 428 | for (; fi; fi = fi->next) |
70126bf9 | 429 | { |
e4dbd248 PS |
430 | /* We have to get the saved sp from the sigcontext |
431 | if it is a signal handler frame. */ | |
432 | if (regno == SP_REGNUM && !fi->signal_handler_caller) | |
433 | return fi->frame; | |
70126bf9 KH |
434 | else |
435 | { | |
436 | if (fi->saved_regs == NULL) | |
437 | mips_find_saved_regs (fi); | |
438 | if (fi->saved_regs->regs[regno]) | |
439 | return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE); | |
440 | } | |
441 | } | |
442 | return read_register (regno); | |
bd5635a1 RP |
443 | } |
444 | ||
96431497 MA |
445 | /* mips_addr_bits_remove - remove useless address bits */ |
446 | ||
447 | CORE_ADDR | |
448 | mips_addr_bits_remove (addr) | |
449 | CORE_ADDR addr; | |
450 | { | |
97e091b2 MA |
451 | #if GDB_TARGET_IS_MIPS64 |
452 | if ((addr >> 32 == (CORE_ADDR)0xffffffff) | |
96431497 MA |
453 | && (strcmp(target_shortname,"pmon")==0 |
454 | || strcmp(target_shortname,"ddb")==0 | |
455 | || strcmp(target_shortname,"sim")==0)) | |
456 | { | |
457 | /* This hack is a work-around for existing boards using PMON, | |
458 | the simulator, and any other 64-bit targets that doesn't have | |
459 | true 64-bit addressing. On these targets, the upper 32 bits | |
460 | of addresses are ignored by the hardware. Thus, the PC or SP | |
461 | are likely to have been sign extended to all 1s by instruction | |
462 | sequences that load 32-bit addresses. For example, a typical | |
463 | piece of code that loads an address is this: | |
464 | lui $r2, <upper 16 bits> | |
465 | ori $r2, <lower 16 bits> | |
466 | But the lui sign-extends the value such that the upper 32 bits | |
467 | may be all 1s. The workaround is simply to mask off these bits. | |
468 | In the future, gcc may be changed to support true 64-bit | |
469 | addressing, and this masking will have to be disabled. */ | |
470 | addr &= (CORE_ADDR)0xffffffff; | |
471 | } | |
97e091b2 | 472 | #endif |
96431497 MA |
473 | |
474 | return addr; | |
475 | } | |
476 | ||
28444bf3 | 477 | CORE_ADDR |
bd5635a1 | 478 | mips_frame_saved_pc(frame) |
9f9f94aa | 479 | struct frame_info *frame; |
bd5635a1 | 480 | { |
28444bf3 | 481 | CORE_ADDR saved_pc; |
0f552c5f | 482 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
0434c1a0 PS |
483 | /* We have to get the saved pc from the sigcontext |
484 | if it is a signal handler frame. */ | |
485 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
486 | : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); | |
0f552c5f | 487 | |
bd5635a1 | 488 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
28444bf3 DP |
489 | saved_pc = read_memory_integer(frame->frame - MIPS_REGSIZE, MIPS_REGSIZE); |
490 | else | |
491 | saved_pc = read_next_frame_reg(frame, pcreg); | |
0f552c5f | 492 | |
96431497 | 493 | return ADDR_BITS_REMOVE (saved_pc); |
bd5635a1 RP |
494 | } |
495 | ||
496 | static struct mips_extra_func_info temp_proc_desc; | |
497 | static struct frame_saved_regs temp_saved_regs; | |
498 | ||
a8172eea RP |
499 | /* This fencepost looks highly suspicious to me. Removing it also |
500 | seems suspicious as it could affect remote debugging across serial | |
3127785a | 501 | lines. */ |
a8172eea | 502 | |
0f552c5f JG |
503 | static CORE_ADDR |
504 | heuristic_proc_start(pc) | |
bd5635a1 RP |
505 | CORE_ADDR pc; |
506 | { | |
bd5635a1 | 507 | CORE_ADDR start_pc = pc; |
3127785a | 508 | CORE_ADDR fence = start_pc - heuristic_fence_post; |
0f552c5f JG |
509 | |
510 | if (start_pc == 0) return 0; | |
3127785a RP |
511 | |
512 | if (heuristic_fence_post == UINT_MAX | |
513 | || fence < VM_MIN_ADDRESS) | |
514 | fence = VM_MIN_ADDRESS; | |
0f552c5f | 515 | |
bd5635a1 | 516 | /* search back for previous return */ |
28444bf3 | 517 | for (start_pc -= MIPS_INSTLEN; ; start_pc -= MIPS_INSTLEN) /* FIXME!! */ |
a8172eea RP |
518 | if (start_pc < fence) |
519 | { | |
3127785a RP |
520 | /* It's not clear to me why we reach this point when |
521 | stop_soon_quietly, but with this test, at least we | |
522 | don't print out warnings for every child forked (eg, on | |
523 | decstation). 22apr93 rich@cygnus.com. */ | |
524 | if (!stop_soon_quietly) | |
525 | { | |
23d35572 JK |
526 | static int blurb_printed = 0; |
527 | ||
3127785a RP |
528 | if (fence == VM_MIN_ADDRESS) |
529 | warning("Hit beginning of text section without finding"); | |
530 | else | |
531 | warning("Hit heuristic-fence-post without finding"); | |
532 | ||
96431497 | 533 | warning("enclosing function for address 0x%s", paddr (pc)); |
23d35572 JK |
534 | if (!blurb_printed) |
535 | { | |
536 | printf_filtered ("\ | |
537 | This warning occurs if you are debugging a function without any symbols\n\ | |
538 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
539 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
540 | \n\ | |
541 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
542 | (more likely) you have encountered a bug in GDB.\n"); | |
543 | blurb_printed = 1; | |
544 | } | |
3127785a RP |
545 | } |
546 | ||
a8172eea RP |
547 | return 0; |
548 | } | |
bd5635a1 RP |
549 | else if (ABOUT_TO_RETURN(start_pc)) |
550 | break; | |
551 | ||
96431497 | 552 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ |
bd5635a1 RP |
553 | #if 0 |
554 | /* skip nops (usually 1) 0 - is this */ | |
28444bf3 DP |
555 | while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) |
556 | start_pc += MIPS_INSTLEN; | |
bd5635a1 RP |
557 | #endif |
558 | return start_pc; | |
559 | } | |
560 | ||
0f552c5f | 561 | static mips_extra_func_info_t |
bd5635a1 RP |
562 | heuristic_proc_desc(start_pc, limit_pc, next_frame) |
563 | CORE_ADDR start_pc, limit_pc; | |
9f9f94aa | 564 | struct frame_info *next_frame; |
bd5635a1 | 565 | { |
ac57e5ad | 566 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); |
bd5635a1 | 567 | CORE_ADDR cur_pc; |
28444bf3 | 568 | unsigned long frame_size; |
97e091b2 | 569 | unsigned long r30_frame_size = 0; |
bd5635a1 | 570 | int has_frame_reg = 0; |
28444bf3 | 571 | CORE_ADDR reg30 = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
bd5635a1 RP |
572 | unsigned long reg_mask = 0; |
573 | ||
574 | if (start_pc == 0) return NULL; | |
9f9f94aa SS |
575 | memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); |
576 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); | |
577 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; | |
a70dc898 | 578 | |
9f9f94aa SS |
579 | if (start_pc + 200 < limit_pc) |
580 | limit_pc = start_pc + 200; | |
bd5635a1 RP |
581 | restart: |
582 | frame_size = 0; | |
28444bf3 DP |
583 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) { |
584 | char buf[MIPS_INSTLEN]; | |
bd5635a1 RP |
585 | unsigned long word; |
586 | int status; | |
587 | ||
28444bf3 | 588 | status = (unsigned long) read_memory_nobpt (cur_pc, buf, MIPS_INSTLEN); /* FIXME!! */ |
34df79fc | 589 | if (status) memory_error (status, cur_pc); |
28444bf3 | 590 | word = (unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN); /* FIXME!! */ |
34df79fc | 591 | |
96431497 MA |
592 | if ((word & 0xFFFF0000) == 0x27bd0000 /* addiu $sp,$sp,-i */ |
593 | || (word & 0xFFFF0000) == 0x23bd0000 /* addi $sp,$sp,-i */ | |
97e091b2 MA |
594 | || (word & 0xFFFF0000) == 0x67bd0000) { /* daddiu $sp,$sp,-i */ |
595 | if (word & 0x8000) | |
596 | frame_size += (-word) & 0xffff; | |
597 | else | |
598 | /* Exit loop if a positive stack adjustment is found, which | |
599 | usually means that the stack cleanup code in the function | |
600 | epilogue is reached. */ | |
601 | break; | |
602 | } | |
603 | else if ((word & 0xFFE00000) == 0xafa00000) { /* sw reg,offset($sp) */ | |
bd5635a1 RP |
604 | int reg = (word & 0x001F0000) >> 16; |
605 | reg_mask |= 1 << reg; | |
002a422b | 606 | temp_saved_regs.regs[reg] = sp + (word & 0xffff); |
bd5635a1 | 607 | } |
97e091b2 MA |
608 | else if ((word & 0xFFE00000) == 0xffa00000) { /* sd reg,offset($sp) */ |
609 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
610 | but the register size used is only 32 bits. Make the address | |
611 | for the saved register point to the lower 32 bits. */ | |
612 | int reg = (word & 0x001F0000) >> 16; | |
613 | reg_mask |= 1 << reg; | |
614 | temp_saved_regs.regs[reg] = sp + (word & 0xffff) + 8 - MIPS_REGSIZE; | |
615 | } | |
bd5635a1 | 616 | else if ((word & 0xFFFF0000) == 0x27be0000) { /* addiu $30,$sp,size */ |
97e091b2 | 617 | /* Old gcc frame, r30 is virtual frame pointer. */ |
002a422b JK |
618 | if ((word & 0xffff) != frame_size) |
619 | reg30 = sp + (word & 0xffff); | |
bd5635a1 | 620 | else if (!has_frame_reg) { |
28444bf3 | 621 | unsigned alloca_adjust; |
bd5635a1 RP |
622 | has_frame_reg = 1; |
623 | reg30 = read_next_frame_reg(next_frame, 30); | |
28444bf3 | 624 | alloca_adjust = (unsigned)(reg30 - (sp + (word & 0xffff))); |
bd5635a1 RP |
625 | if (alloca_adjust > 0) { |
626 | /* FP > SP + frame_size. This may be because | |
e03c0cc6 | 627 | * of an alloca or somethings similar. |
bd5635a1 RP |
628 | * Fix sp to "pre-alloca" value, and try again. |
629 | */ | |
630 | sp += alloca_adjust; | |
631 | goto restart; | |
632 | } | |
633 | } | |
634 | } | |
97e091b2 MA |
635 | else if ((word & 0xFFFFFFFB) == 0x03a0f021) { /* mov $30,$sp */ |
636 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
637 | if (!has_frame_reg) { | |
638 | unsigned alloca_adjust; | |
639 | has_frame_reg = 1; | |
640 | reg30 = read_next_frame_reg(next_frame, 30); | |
641 | r30_frame_size = frame_size; | |
642 | alloca_adjust = (unsigned)(reg30 - sp); | |
643 | if (alloca_adjust > 0) { | |
644 | /* FP > SP + frame_size. This may be because | |
645 | * of an alloca or somethings similar. | |
646 | * Fix sp to "pre-alloca" value, and try again. | |
647 | */ | |
648 | sp += alloca_adjust; | |
649 | goto restart; | |
650 | } | |
651 | } | |
652 | } | |
bd5635a1 RP |
653 | else if ((word & 0xFFE00000) == 0xafc00000) { /* sw reg,offset($30) */ |
654 | int reg = (word & 0x001F0000) >> 16; | |
655 | reg_mask |= 1 << reg; | |
002a422b | 656 | temp_saved_regs.regs[reg] = reg30 + (word & 0xffff); |
bd5635a1 RP |
657 | } |
658 | } | |
659 | if (has_frame_reg) { | |
660 | PROC_FRAME_REG(&temp_proc_desc) = 30; | |
97e091b2 | 661 | PROC_FRAME_OFFSET(&temp_proc_desc) = r30_frame_size; |
bd5635a1 RP |
662 | } |
663 | else { | |
664 | PROC_FRAME_REG(&temp_proc_desc) = SP_REGNUM; | |
665 | PROC_FRAME_OFFSET(&temp_proc_desc) = frame_size; | |
666 | } | |
667 | PROC_REG_MASK(&temp_proc_desc) = reg_mask; | |
668 | PROC_PC_REG(&temp_proc_desc) = RA_REGNUM; | |
669 | return &temp_proc_desc; | |
670 | } | |
671 | ||
0f552c5f | 672 | static mips_extra_func_info_t |
9f9f94aa SS |
673 | find_proc_desc (pc, next_frame) |
674 | CORE_ADDR pc; | |
675 | struct frame_info *next_frame; | |
bd5635a1 RP |
676 | { |
677 | mips_extra_func_info_t proc_desc; | |
0f552c5f | 678 | struct block *b = block_for_pc(pc); |
48be4c35 JK |
679 | struct symbol *sym; |
680 | CORE_ADDR startaddr; | |
681 | ||
682 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
97e091b2 | 683 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) |
48be4c35 JK |
684 | sym = NULL; |
685 | else | |
686 | { | |
687 | if (startaddr > BLOCK_START (b)) | |
688 | /* This is the "pathological" case referred to in a comment in | |
689 | print_frame_info. It might be better to move this check into | |
690 | symbol reading. */ | |
691 | sym = NULL; | |
692 | else | |
693 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, | |
694 | 0, NULL); | |
695 | } | |
0f552c5f | 696 | |
e4dbd248 PS |
697 | /* If we never found a PDR for this function in symbol reading, then |
698 | examine prologues to find the information. */ | |
699 | if (sym && ((mips_extra_func_info_t) SYMBOL_VALUE (sym))->pdr.framereg == -1) | |
700 | sym = NULL; | |
701 | ||
0f552c5f | 702 | if (sym) |
bd5635a1 RP |
703 | { |
704 | /* IF this is the topmost frame AND | |
705 | * (this proc does not have debugging information OR | |
706 | * the PC is in the procedure prologue) | |
be772100 | 707 | * THEN create a "heuristic" proc_desc (by analyzing |
bd5635a1 RP |
708 | * the actual code) to replace the "official" proc_desc. |
709 | */ | |
9f9f94aa | 710 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
bd5635a1 RP |
711 | if (next_frame == NULL) { |
712 | struct symtab_and_line val; | |
713 | struct symbol *proc_symbol = | |
714 | PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); | |
0f552c5f | 715 | |
bd5635a1 RP |
716 | if (proc_symbol) { |
717 | val = find_pc_line (BLOCK_START | |
718 | (SYMBOL_BLOCK_VALUE(proc_symbol)), | |
719 | 0); | |
720 | val.pc = val.end ? val.end : pc; | |
721 | } | |
722 | if (!proc_symbol || pc < val.pc) { | |
723 | mips_extra_func_info_t found_heuristic = | |
9f9f94aa SS |
724 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
725 | pc, next_frame); | |
726 | if (found_heuristic) | |
727 | proc_desc = found_heuristic; | |
bd5635a1 RP |
728 | } |
729 | } | |
730 | } | |
731 | else | |
732 | { | |
0f552c5f JG |
733 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
734 | by procedure call dummys. However, the procedures being called ought | |
735 | to have their own proc_descs, and even if they don't, | |
736 | heuristic_proc_desc knows how to create them! */ | |
737 | ||
bd5635a1 | 738 | register struct linked_proc_info *link; |
9f9f94aa | 739 | |
bd5635a1 | 740 | for (link = linked_proc_desc_table; link; link = link->next) |
9f9f94aa SS |
741 | if (PROC_LOW_ADDR(&link->info) <= pc |
742 | && PROC_HIGH_ADDR(&link->info) > pc) | |
743 | return &link->info; | |
23d35572 | 744 | |
48be4c35 JK |
745 | if (startaddr == 0) |
746 | startaddr = heuristic_proc_start (pc); | |
747 | ||
bd5635a1 | 748 | proc_desc = |
48be4c35 | 749 | heuristic_proc_desc (startaddr, pc, next_frame); |
bd5635a1 RP |
750 | } |
751 | return proc_desc; | |
752 | } | |
753 | ||
96431497 MA |
754 | static CORE_ADDR |
755 | get_frame_pointer(frame, proc_desc) | |
756 | struct frame_info *frame; | |
757 | mips_extra_func_info_t proc_desc; | |
758 | { | |
759 | return ADDR_BITS_REMOVE (read_next_frame_reg (frame, | |
760 | PROC_FRAME_REG(proc_desc)) + PROC_FRAME_OFFSET(proc_desc)); | |
761 | } | |
762 | ||
bd5635a1 RP |
763 | mips_extra_func_info_t cached_proc_desc; |
764 | ||
9f9f94aa | 765 | CORE_ADDR |
0f552c5f | 766 | mips_frame_chain(frame) |
9f9f94aa | 767 | struct frame_info *frame; |
bd5635a1 | 768 | { |
bd5635a1 RP |
769 | mips_extra_func_info_t proc_desc; |
770 | CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); | |
be772100 | 771 | |
0f552c5f JG |
772 | if (saved_pc == 0 || inside_entry_file (saved_pc)) |
773 | return 0; | |
774 | ||
bd5635a1 | 775 | proc_desc = find_proc_desc(saved_pc, frame); |
0f552c5f JG |
776 | if (!proc_desc) |
777 | return 0; | |
778 | ||
bd5635a1 | 779 | cached_proc_desc = proc_desc; |
e797b4bc JK |
780 | |
781 | /* If no frame pointer and frame size is zero, we must be at end | |
782 | of stack (or otherwise hosed). If we don't check frame size, | |
783 | we loop forever if we see a zero size frame. */ | |
784 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
3f528883 | 785 | && PROC_FRAME_OFFSET (proc_desc) == 0 |
199b2450 TL |
786 | /* The previous frame from a sigtramp frame might be frameless |
787 | and have frame size zero. */ | |
788 | && !frame->signal_handler_caller) | |
bdef72d2 JK |
789 | return 0; |
790 | else | |
96431497 | 791 | return get_frame_pointer (frame, proc_desc); |
bd5635a1 RP |
792 | } |
793 | ||
794 | void | |
795 | init_extra_frame_info(fci) | |
796 | struct frame_info *fci; | |
797 | { | |
96431497 MA |
798 | int regnum; |
799 | ||
bd5635a1 | 800 | /* Use proc_desc calculated in frame_chain */ |
ee5fb959 JK |
801 | mips_extra_func_info_t proc_desc = |
802 | fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); | |
0f552c5f | 803 | |
70126bf9 | 804 | fci->saved_regs = NULL; |
bd5635a1 | 805 | fci->proc_desc = |
ee5fb959 | 806 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
bd5635a1 RP |
807 | if (proc_desc) |
808 | { | |
c2a0f1cb | 809 | /* Fixup frame-pointer - only needed for top frame */ |
5efd597b PS |
810 | /* This may not be quite right, if proc has a real frame register. |
811 | Get the value of the frame relative sp, procedure might have been | |
812 | interrupted by a signal at it's very start. */ | |
70126bf9 KH |
813 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
814 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
815 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
c2a0f1cb | 816 | else |
96431497 | 817 | fci->frame = get_frame_pointer (fci->next, proc_desc); |
bd5635a1 | 818 | |
48be4c35 | 819 | if (proc_desc == &temp_proc_desc) |
ee5fb959 | 820 | { |
09af5868 PS |
821 | char *name; |
822 | ||
823 | /* Do not set the saved registers for a sigtramp frame, | |
824 | mips_find_saved_registers will do that for us. | |
825 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
826 | find_pc_partial_function (fci->pc, &name, | |
827 | (CORE_ADDR *)NULL,(CORE_ADDR *)NULL); | |
828 | if (!IN_SIGTRAMP (fci->pc, name)) | |
829 | { | |
830 | fci->saved_regs = (struct frame_saved_regs*) | |
831 | obstack_alloc (&frame_cache_obstack, | |
832 | sizeof (struct frame_saved_regs)); | |
833 | *fci->saved_regs = temp_saved_regs; | |
834 | fci->saved_regs->regs[PC_REGNUM] | |
835 | = fci->saved_regs->regs[RA_REGNUM]; | |
836 | } | |
ee5fb959 | 837 | } |
bd5635a1 RP |
838 | |
839 | /* hack: if argument regs are saved, guess these contain args */ | |
96431497 MA |
840 | fci->num_args = -1; /* assume we can't tell how many args for now */ |
841 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) | |
842 | { | |
843 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) | |
844 | { | |
845 | fci->num_args = regnum - A0_REGNUM + 1; | |
846 | break; | |
847 | } | |
848 | } | |
bd5635a1 | 849 | } |
bd5635a1 RP |
850 | } |
851 | ||
a70dc898 RP |
852 | /* MIPS stack frames are almost impenetrable. When execution stops, |
853 | we basically have to look at symbol information for the function | |
854 | that we stopped in, which tells us *which* register (if any) is | |
855 | the base of the frame pointer, and what offset from that register | |
856 | the frame itself is at. | |
857 | ||
858 | This presents a problem when trying to examine a stack in memory | |
859 | (that isn't executing at the moment), using the "frame" command. We | |
860 | don't have a PC, nor do we have any registers except SP. | |
861 | ||
862 | This routine takes two arguments, SP and PC, and tries to make the | |
863 | cached frames look as if these two arguments defined a frame on the | |
864 | cache. This allows the rest of info frame to extract the important | |
865 | arguments without difficulty. */ | |
866 | ||
9f9f94aa | 867 | struct frame_info * |
c2a0f1cb ILT |
868 | setup_arbitrary_frame (argc, argv) |
869 | int argc; | |
9f9f94aa | 870 | CORE_ADDR *argv; |
a70dc898 | 871 | { |
c2a0f1cb ILT |
872 | if (argc != 2) |
873 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
874 | ||
875 | return create_new_frame (argv[0], argv[1]); | |
a70dc898 RP |
876 | } |
877 | ||
0f552c5f JG |
878 | CORE_ADDR |
879 | mips_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
97e091b2 MA |
880 | int nargs; |
881 | value_ptr *args; | |
882 | CORE_ADDR sp; | |
883 | int struct_return; | |
884 | CORE_ADDR struct_addr; | |
bd5635a1 | 885 | { |
97e091b2 MA |
886 | int argreg; |
887 | int float_argreg; | |
888 | int argnum; | |
889 | int len = 0; | |
890 | int stack_offset; | |
891 | ||
892 | /* Macros to round N up or down to the next A boundary; A must be | |
893 | a power of two. */ | |
894 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
895 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
28444bf3 DP |
896 | |
897 | /* First ensure that the stack and structure return address (if any) | |
97e091b2 MA |
898 | are properly aligned. The stack has to be 64-bit aligned even |
899 | on 32-bit machines, because doubles must be 64-bit aligned. */ | |
900 | sp = ROUND_DOWN (sp, 8); | |
901 | struct_addr = ROUND_DOWN (struct_addr, MIPS_REGSIZE); | |
28444bf3 | 902 | |
97e091b2 MA |
903 | /* Now make space on the stack for the args. We allocate more |
904 | than necessary for EABI, because the first few arguments are | |
905 | passed in registers, but that's OK. */ | |
906 | for (argnum = 0; argnum < nargs; argnum++) | |
907 | len += ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args[argnum])), MIPS_REGSIZE); | |
61d2d19a | 908 | sp -= ROUND_UP (len, 8); |
97e091b2 MA |
909 | |
910 | /* Initialize the integer and float register pointers. */ | |
911 | argreg = A0_REGNUM; | |
912 | float_argreg = FPA0_REGNUM; | |
913 | ||
914 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
5efd597b | 915 | if (struct_return) |
97e091b2 MA |
916 | write_register (argreg++, struct_addr); |
917 | ||
918 | /* The offset onto the stack at which we will start copying parameters | |
919 | (after the registers are used up) begins at 16 in the old ABI. | |
920 | This leaves room for the "home" area for register parameters. */ | |
921 | stack_offset = MIPS_EABI ? 0 : MIPS_REGSIZE * 4; | |
922 | ||
923 | /* Now load as many as possible of the first arguments into | |
924 | registers, and push the rest onto the stack. Loop thru args | |
925 | from first to last. */ | |
926 | for (argnum = 0; argnum < nargs; argnum++) | |
5efd597b | 927 | { |
97e091b2 MA |
928 | char *val; |
929 | char valbuf[REGISTER_RAW_SIZE(A0_REGNUM)]; | |
930 | value_ptr arg = args[argnum]; | |
931 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
932 | int len = TYPE_LENGTH (arg_type); | |
933 | enum type_code typecode = TYPE_CODE (arg_type); | |
934 | ||
61d2d19a PS |
935 | /* The EABI passes structures that do not fit in a register by |
936 | reference. In all other cases, pass the structure by value. */ | |
937 | if (typecode == TYPE_CODE_STRUCT && MIPS_EABI && len > MIPS_REGSIZE) | |
97e091b2 MA |
938 | { |
939 | store_address (valbuf, MIPS_REGSIZE, VALUE_ADDRESS (arg)); | |
940 | len = MIPS_REGSIZE; | |
941 | val = valbuf; | |
942 | } | |
943 | else | |
944 | val = (char *)VALUE_CONTENTS (arg); | |
945 | ||
946 | /* 32-bit ABIs always start floating point arguments in an | |
947 | even-numbered floating point register. */ | |
948 | if (!GDB_TARGET_IS_MIPS64 && typecode == TYPE_CODE_FLT | |
949 | && (float_argreg & 1)) | |
950 | float_argreg++; | |
951 | ||
952 | /* Floating point arguments passed in registers have to be | |
953 | treated specially. On 32-bit architectures, doubles | |
954 | are passed in register pairs; the even register gets | |
955 | the low word, and the odd register gets the high word. */ | |
956 | if (typecode == TYPE_CODE_FLT | |
957 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM | |
958 | && mips_fpu != MIPS_FPU_NONE) | |
959 | { | |
960 | if (!GDB_TARGET_IS_MIPS64 && len == 8) | |
961 | { | |
962 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; | |
963 | unsigned long regval; | |
964 | ||
965 | regval = extract_unsigned_integer (val+low_offset, 4); | |
966 | write_register (float_argreg++, regval); /* low word */ | |
967 | regval = extract_unsigned_integer (val+4-low_offset, 4); | |
968 | write_register (float_argreg++, regval); /* high word */ | |
969 | ||
970 | } | |
971 | else | |
972 | { | |
973 | CORE_ADDR regval = extract_address (val, len); | |
974 | write_register (float_argreg++, regval); | |
975 | } | |
5efd597b | 976 | |
97e091b2 MA |
977 | /* If this is the old ABI, skip one or two general registers. */ |
978 | if (!MIPS_EABI) | |
979 | argreg += GDB_TARGET_IS_MIPS64 ? 1 : 2; | |
980 | } | |
981 | else | |
982 | { | |
983 | /* Copy the argument to general registers or the stack in | |
984 | register-sized pieces. Large arguments are split between | |
985 | registers and stack. */ | |
986 | while (len > 0) | |
987 | { | |
988 | int partial_len = len < MIPS_REGSIZE ? len : MIPS_REGSIZE; | |
61d2d19a | 989 | |
97e091b2 MA |
990 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
991 | { | |
61d2d19a PS |
992 | CORE_ADDR regval = extract_address (val, partial_len); |
993 | ||
994 | /* It's a simple argument being passed in a general | |
995 | register. | |
996 | If the argument length is smaller than the register size, | |
997 | we have to adjust the argument on big endian targets. */ | |
998 | if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
999 | && partial_len < MIPS_REGSIZE) | |
1000 | regval <<= ((MIPS_REGSIZE - partial_len) * TARGET_CHAR_BIT); | |
97e091b2 MA |
1001 | write_register (argreg, regval); |
1002 | argreg++; | |
1003 | ||
1004 | /* If this is the old ABI, prevent subsequent floating | |
1005 | point arguments from being passed in floating point | |
1006 | registers. */ | |
1007 | if (!MIPS_EABI) | |
1008 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
1009 | } | |
1010 | else | |
1011 | { | |
61d2d19a PS |
1012 | /* Write this portion of the argument to the stack. */ |
1013 | partial_len = len; | |
1014 | write_memory (sp + stack_offset, val, partial_len); | |
1015 | stack_offset += ROUND_UP (partial_len, MIPS_REGSIZE); | |
97e091b2 MA |
1016 | } |
1017 | ||
1018 | len -= partial_len; | |
1019 | val += partial_len; | |
1020 | } | |
1021 | } | |
5efd597b | 1022 | } |
97e091b2 MA |
1023 | |
1024 | /* Set the return address register to point to the entry | |
1025 | point of the program, where a breakpoint lies in wait. */ | |
1026 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS()); | |
1027 | ||
1028 | /* Return adjusted stack pointer. */ | |
bd5635a1 RP |
1029 | return sp; |
1030 | } | |
1031 | ||
28444bf3 DP |
1032 | void |
1033 | mips_push_register(CORE_ADDR *sp, int regno) | |
1034 | { | |
1035 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
1036 | int regsize = REGISTER_RAW_SIZE (regno); | |
1037 | ||
1038 | *sp -= regsize; | |
1039 | read_register_gen (regno, buffer); | |
1040 | write_memory (*sp, buffer, regsize); | |
1041 | } | |
1042 | ||
1043 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
e03c0cc6 | 1044 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
bd5635a1 RP |
1045 | |
1046 | void | |
1047 | mips_push_dummy_frame() | |
1048 | { | |
1049 | int ireg; | |
1050 | struct linked_proc_info *link = (struct linked_proc_info*) | |
1051 | xmalloc(sizeof(struct linked_proc_info)); | |
1052 | mips_extra_func_info_t proc_desc = &link->info; | |
96431497 | 1053 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM)); |
28444bf3 | 1054 | CORE_ADDR old_sp = sp; |
bd5635a1 RP |
1055 | link->next = linked_proc_desc_table; |
1056 | linked_proc_desc_table = link; | |
28444bf3 DP |
1057 | |
1058 | /* FIXME! are these correct ? */ | |
bd5635a1 | 1059 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
28444bf3 | 1060 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
bd5635a1 | 1061 | #define FLOAT_REG_SAVE_MASK MASK(0,19) |
e4dbd248 PS |
1062 | #define FLOAT_SINGLE_REG_SAVE_MASK \ |
1063 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
bd5635a1 RP |
1064 | /* |
1065 | * The registers we must save are all those not preserved across | |
1066 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
28444bf3 DP |
1067 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI |
1068 | * and FP Control/Status registers. | |
1069 | * | |
bd5635a1 RP |
1070 | * |
1071 | * Dummy frame layout: | |
1072 | * (high memory) | |
1073 | * Saved PC | |
1074 | * Saved MMHI, MMLO, FPC_CSR | |
1075 | * Saved R31 | |
1076 | * Saved R28 | |
1077 | * ... | |
1078 | * Saved R1 | |
1079 | * Saved D18 (i.e. F19, F18) | |
1080 | * ... | |
1081 | * Saved D0 (i.e. F1, F0) | |
c2a0f1cb | 1082 | * CALL_DUMMY (subroutine stub; see tm-mips.h) |
bd5635a1 RP |
1083 | * Parameter build area (not yet implemented) |
1084 | * (low memory) | |
1085 | */ | |
28444bf3 DP |
1086 | |
1087 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
1088 | write_register (PUSH_FP_REGNUM, sp); | |
1089 | PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; | |
1090 | PROC_FRAME_OFFSET(proc_desc) = 0; | |
1091 | mips_push_register (&sp, PC_REGNUM); | |
1092 | mips_push_register (&sp, HI_REGNUM); | |
1093 | mips_push_register (&sp, LO_REGNUM); | |
1094 | mips_push_register (&sp, mips_fpu == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
1095 | ||
1096 | /* Save general CPU registers */ | |
bd5635a1 | 1097 | PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; |
28444bf3 | 1098 | PROC_REG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved R31) from FP */ |
bd5635a1 RP |
1099 | for (ireg = 32; --ireg >= 0; ) |
1100 | if (PROC_REG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1101 | mips_push_register (&sp, ireg); |
3fed1c4a | 1102 | |
28444bf3 DP |
1103 | /* Save floating point registers starting with high order word */ |
1104 | PROC_FREG_MASK(proc_desc) = | |
1105 | mips_fpu == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK | |
1106 | : mips_fpu == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
1107 | PROC_FREG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved D18) from FP */ | |
bd5635a1 RP |
1108 | for (ireg = 32; --ireg >= 0; ) |
1109 | if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1110 | mips_push_register (&sp, ireg + FP0_REGNUM); |
3fed1c4a | 1111 | |
28444bf3 DP |
1112 | /* Update the stack pointer. Set the procedure's starting and ending |
1113 | addresses to point to the place on the stack where we'll be writing the | |
1114 | dummy code (in mips_push_arguments). */ | |
bd5635a1 | 1115 | write_register (SP_REGNUM, sp); |
97e091b2 MA |
1116 | PROC_LOW_ADDR(proc_desc) = CALL_DUMMY_ADDRESS(); |
1117 | PROC_HIGH_ADDR(proc_desc) = CALL_DUMMY_ADDRESS() + 4; | |
bd5635a1 RP |
1118 | SET_PROC_DESC_IS_DUMMY(proc_desc); |
1119 | PROC_PC_REG(proc_desc) = RA_REGNUM; | |
1120 | } | |
1121 | ||
1122 | void | |
1123 | mips_pop_frame() | |
dac4929a SG |
1124 | { |
1125 | register int regnum; | |
9f9f94aa SS |
1126 | struct frame_info *frame = get_current_frame (); |
1127 | CORE_ADDR new_sp = FRAME_FP (frame); | |
dac4929a | 1128 | |
a70dc898 | 1129 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
dac4929a SG |
1130 | |
1131 | write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); | |
70126bf9 KH |
1132 | if (frame->saved_regs == NULL) |
1133 | mips_find_saved_regs (frame); | |
61d2d19a | 1134 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
dac4929a | 1135 | { |
61d2d19a PS |
1136 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1137 | && frame->saved_regs->regs[regnum]) | |
1138 | write_register (regnum, | |
1139 | read_memory_integer (frame->saved_regs->regs[regnum], | |
1140 | MIPS_REGSIZE)); | |
dac4929a SG |
1141 | } |
1142 | write_register (SP_REGNUM, new_sp); | |
1143 | flush_cached_frames (); | |
dac4929a | 1144 | |
199b2450 | 1145 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
bd5635a1 | 1146 | { |
dac4929a SG |
1147 | struct linked_proc_info *pi_ptr, *prev_ptr; |
1148 | ||
1149 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
1150 | pi_ptr != NULL; | |
1151 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
1152 | { | |
1153 | if (&pi_ptr->info == proc_desc) | |
1154 | break; | |
1155 | } | |
1156 | ||
1157 | if (pi_ptr == NULL) | |
1158 | error ("Can't locate dummy extra frame info\n"); | |
1159 | ||
1160 | if (prev_ptr != NULL) | |
1161 | prev_ptr->next = pi_ptr->next; | |
1162 | else | |
1163 | linked_proc_desc_table = pi_ptr->next; | |
1164 | ||
1165 | free (pi_ptr); | |
1166 | ||
28444bf3 DP |
1167 | write_register (HI_REGNUM, |
1168 | read_memory_integer (new_sp - 2*MIPS_REGSIZE, MIPS_REGSIZE)); | |
1169 | write_register (LO_REGNUM, | |
1170 | read_memory_integer (new_sp - 3*MIPS_REGSIZE, MIPS_REGSIZE)); | |
e4dbd248 | 1171 | if (mips_fpu != MIPS_FPU_NONE) |
28444bf3 DP |
1172 | write_register (FCRCS_REGNUM, |
1173 | read_memory_integer (new_sp - 4*MIPS_REGSIZE, MIPS_REGSIZE)); | |
bd5635a1 | 1174 | } |
bd5635a1 RP |
1175 | } |
1176 | ||
0f552c5f | 1177 | static void |
a70dc898 | 1178 | mips_print_register (regnum, all) |
bd5635a1 RP |
1179 | int regnum, all; |
1180 | { | |
e4dbd248 | 1181 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
bd5635a1 | 1182 | |
48be4c35 JK |
1183 | /* Get the data in raw format. */ |
1184 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
1185 | { | |
1186 | printf_filtered ("%s: [Invalid]", reg_names[regnum]); | |
1187 | return; | |
1188 | } | |
1189 | ||
1190 | /* If an even floating pointer register, also print as double. */ | |
28444bf3 | 1191 | if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+MIPS_NUMREGS |
e4dbd248 PS |
1192 | && !((regnum-FP0_REGNUM) & 1)) |
1193 | { | |
1194 | char dbuffer[MAX_REGISTER_RAW_SIZE]; | |
48be4c35 | 1195 | |
e4dbd248 | 1196 | read_relative_register_raw_bytes (regnum, dbuffer); |
28444bf3 | 1197 | read_relative_register_raw_bytes (regnum+1, dbuffer+4); /* FIXME!! */ |
ac8cf67d | 1198 | #ifdef REGISTER_CONVERT_TO_TYPE |
e4dbd248 | 1199 | REGISTER_CONVERT_TO_TYPE(regnum, builtin_type_double, dbuffer); |
ac8cf67d | 1200 | #endif |
e4dbd248 PS |
1201 | printf_filtered ("(d%d: ", regnum-FP0_REGNUM); |
1202 | val_print (builtin_type_double, dbuffer, 0, | |
1203 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
1204 | printf_filtered ("); "); | |
1205 | } | |
199b2450 | 1206 | fputs_filtered (reg_names[regnum], gdb_stdout); |
48be4c35 JK |
1207 | |
1208 | /* The problem with printing numeric register names (r26, etc.) is that | |
1209 | the user can't use them on input. Probably the best solution is to | |
1210 | fix it so that either the numeric or the funky (a2, etc.) names | |
1211 | are accepted on input. */ | |
28444bf3 | 1212 | if (regnum < MIPS_NUMREGS) |
48be4c35 JK |
1213 | printf_filtered ("(r%d): ", regnum); |
1214 | else | |
1215 | printf_filtered (": "); | |
bd5635a1 | 1216 | |
48be4c35 | 1217 | /* If virtual format is floating, print it that way. */ |
ac57e5ad | 1218 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
48be4c35 | 1219 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, |
199b2450 | 1220 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
48be4c35 JK |
1221 | /* Else print as integer in hex. */ |
1222 | else | |
ac57e5ad SS |
1223 | print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), |
1224 | 'x', 0, gdb_stdout); | |
bd5635a1 RP |
1225 | } |
1226 | ||
d8b3b00e | 1227 | /* Replacement for generic do_registers_info. */ |
9f9f94aa | 1228 | |
0f552c5f | 1229 | void |
361bf6ee | 1230 | mips_do_registers_info (regnum, fpregs) |
bd5635a1 | 1231 | int regnum; |
361bf6ee | 1232 | int fpregs; |
bd5635a1 | 1233 | { |
9f9f94aa SS |
1234 | if (regnum != -1) |
1235 | { | |
1236 | if (*(reg_names[regnum]) == '\0') | |
1237 | error ("Not a valid register for the current processor type"); | |
1238 | ||
bd5635a1 RP |
1239 | mips_print_register (regnum, 0); |
1240 | printf_filtered ("\n"); | |
9f9f94aa SS |
1241 | } |
1242 | else | |
1243 | { | |
09af5868 | 1244 | int did_newline = 0; |
9f9f94aa SS |
1245 | |
1246 | for (regnum = 0; regnum < NUM_REGS; ) | |
1247 | { | |
1248 | if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM) | |
1249 | || *(reg_names[regnum]) == '\0') | |
1250 | { | |
1251 | regnum++; | |
1252 | continue; | |
1253 | } | |
bd5635a1 RP |
1254 | mips_print_register (regnum, 1); |
1255 | regnum++; | |
9f9f94aa SS |
1256 | printf_filtered ("; "); |
1257 | did_newline = 0; | |
1258 | if ((regnum & 3) == 0) | |
1259 | { | |
1260 | printf_filtered ("\n"); | |
1261 | did_newline = 1; | |
1262 | } | |
1263 | } | |
1264 | if (!did_newline) | |
1265 | printf_filtered ("\n"); | |
1266 | } | |
bd5635a1 | 1267 | } |
9f9f94aa | 1268 | |
bd5635a1 RP |
1269 | /* Return number of args passed to a frame. described by FIP. |
1270 | Can return -1, meaning no way to tell. */ | |
1271 | ||
0f552c5f | 1272 | int |
9f9f94aa SS |
1273 | mips_frame_num_args (frame) |
1274 | struct frame_info *frame; | |
bd5635a1 | 1275 | { |
9f9f94aa SS |
1276 | #if 0 /* FIXME Use or lose this! */ |
1277 | struct chain_info_t *p; | |
bd5635a1 | 1278 | |
9f9f94aa SS |
1279 | p = mips_find_cached_frame (FRAME_FP (frame)); |
1280 | if (p->valid) | |
1281 | return p->the_info.numargs; | |
bd5635a1 | 1282 | #endif |
9f9f94aa | 1283 | return -1; |
bd5635a1 | 1284 | } |
96431497 | 1285 | |
427fec5d | 1286 | /* Is this a branch with a delay slot? */ |
9f9f94aa | 1287 | |
b5aff268 JK |
1288 | static int is_delayed PARAMS ((unsigned long)); |
1289 | ||
ee5fb959 JK |
1290 | static int |
1291 | is_delayed (insn) | |
1292 | unsigned long insn; | |
1293 | { | |
1294 | int i; | |
1295 | for (i = 0; i < NUMOPCODES; ++i) | |
1296 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
1297 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
1298 | break; | |
427fec5d JK |
1299 | return (i < NUMOPCODES |
1300 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
1301 | | INSN_COND_BRANCH_DELAY | |
1302 | | INSN_COND_BRANCH_LIKELY))); | |
ee5fb959 | 1303 | } |
b5aff268 JK |
1304 | |
1305 | int | |
1306 | mips_step_skips_delay (pc) | |
1307 | CORE_ADDR pc; | |
1308 | { | |
96431497 | 1309 | char buf[MIPS_INSTLEN]; |
b5aff268 | 1310 | |
96431497 | 1311 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) |
b5aff268 JK |
1312 | /* If error reading memory, guess that it is not a delayed branch. */ |
1313 | return 0; | |
96431497 | 1314 | return is_delayed ((unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN)); |
b5aff268 | 1315 | } |
ee5fb959 JK |
1316 | |
1317 | /* To skip prologues, I use this predicate. Returns either PC itself | |
1318 | if the code at PC does not look like a function prologue; otherwise | |
1319 | returns an address that (if we're lucky) follows the prologue. If | |
1320 | LENIENT, then we must skip everything which is involved in setting | |
1321 | up the frame (it's OK to skip more, just so long as we don't skip | |
1322 | anything which might clobber the registers which are being saved. | |
1323 | We must skip more in the case where part of the prologue is in the | |
1324 | delay slot of a non-prologue instruction). */ | |
bd5635a1 | 1325 | |
be772100 | 1326 | CORE_ADDR |
ee5fb959 | 1327 | mips_skip_prologue (pc, lenient) |
bd5635a1 | 1328 | CORE_ADDR pc; |
ee5fb959 | 1329 | int lenient; |
bd5635a1 | 1330 | { |
28444bf3 DP |
1331 | t_inst inst; |
1332 | unsigned offset; | |
0b0d6c3f | 1333 | int seen_sp_adjust = 0; |
ac57e5ad | 1334 | int load_immediate_bytes = 0; |
f2bf454e FF |
1335 | CORE_ADDR post_prologue_pc; |
1336 | ||
1337 | /* See if we can determine the end of the prologue via the symbol table. | |
1338 | If so, then return either PC, or the PC after the prologue, whichever | |
1339 | is greater. */ | |
1340 | ||
1341 | post_prologue_pc = after_prologue (pc, NULL); | |
1342 | ||
1343 | if (post_prologue_pc != 0) | |
1344 | return max (pc, post_prologue_pc); | |
1345 | ||
1346 | /* Can't determine prologue from the symbol table, need to examine | |
1347 | instructions. */ | |
bd5635a1 | 1348 | |
e157305c PS |
1349 | /* Skip the typical prologue instructions. These are the stack adjustment |
1350 | instruction and the instructions that save registers on the stack | |
1351 | or in the gcc frame. */ | |
96431497 | 1352 | for (offset = 0; offset < 100; offset += MIPS_INSTLEN) |
ee5fb959 | 1353 | { |
28444bf3 | 1354 | char buf[MIPS_INSTLEN]; |
ee5fb959 JK |
1355 | int status; |
1356 | ||
28444bf3 | 1357 | status = read_memory_nobpt (pc + offset, buf, MIPS_INSTLEN); |
ee5fb959 JK |
1358 | if (status) |
1359 | memory_error (status, pc + offset); | |
28444bf3 | 1360 | inst = (unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN); |
ee5fb959 | 1361 | |
002a422b | 1362 | #if 0 |
ee5fb959 JK |
1363 | if (lenient && is_delayed (inst)) |
1364 | continue; | |
002a422b | 1365 | #endif |
ee5fb959 | 1366 | |
97e091b2 MA |
1367 | if ((inst & 0xffff0000) == 0x27bd0000 /* addiu $sp,$sp,offset */ |
1368 | || (inst & 0xffff0000) == 0x67bd0000) /* daddiu $sp,$sp,offset */ | |
0b0d6c3f | 1369 | seen_sp_adjust = 1; |
ac57e5ad SS |
1370 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
1371 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
1372 | seen_sp_adjust = 1; | |
97e091b2 MA |
1373 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ |
1374 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
1375 | && (inst & 0x001F0000)) /* reg != $zero */ | |
1376 | continue; | |
1377 | ||
e157305c PS |
1378 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ |
1379 | continue; | |
1380 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
1381 | /* sx reg,n($s8) */ | |
1382 | continue; /* reg != $zero */ | |
1d9489c1 JK |
1383 | |
1384 | /* move $s8,$sp. With different versions of gas this will be either | |
1385 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero'. Accept either. */ | |
1386 | else if (inst == 0x03A0F021 || inst == 0x03a0f025) | |
0b0d6c3f | 1387 | continue; |
1d9489c1 | 1388 | |
1b71de8e PS |
1389 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
1390 | continue; | |
e03c0cc6 ILT |
1391 | else if ((inst & 0xffff0000) == 0x3c1c0000) /* lui $gp,n */ |
1392 | continue; | |
1393 | else if ((inst & 0xffff0000) == 0x279c0000) /* addiu $gp,$gp,n */ | |
1394 | continue; | |
1395 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1396 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
1397 | continue; | |
ac57e5ad SS |
1398 | /* The following instructions load $at or $t0 with an immediate |
1399 | value in preparation for a stack adjustment via | |
1400 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
1401 | a local variable, so we accept them only before a stack adjustment | |
1402 | instruction was seen. */ | |
1403 | else if (!seen_sp_adjust) | |
1404 | { | |
1405 | if ((inst & 0xffff0000) == 0x3c010000 || /* lui $at,n */ | |
1406 | (inst & 0xffff0000) == 0x3c080000) /* lui $t0,n */ | |
1407 | { | |
28444bf3 | 1408 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1409 | continue; |
1410 | } | |
1411 | else if ((inst & 0xffff0000) == 0x34210000 || /* ori $at,$at,n */ | |
1412 | (inst & 0xffff0000) == 0x35080000 || /* ori $t0,$t0,n */ | |
1413 | (inst & 0xffff0000) == 0x34010000 || /* ori $at,$zero,n */ | |
1414 | (inst & 0xffff0000) == 0x34080000) /* ori $t0,$zero,n */ | |
1415 | { | |
28444bf3 | 1416 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1417 | continue; |
1418 | } | |
1419 | else | |
1420 | break; | |
1421 | } | |
0b0d6c3f | 1422 | else |
ac57e5ad | 1423 | break; |
d747e0af | 1424 | } |
e157305c | 1425 | |
ac57e5ad SS |
1426 | /* In a frameless function, we might have incorrectly |
1427 | skipped some load immediate instructions. Undo the skipping | |
1428 | if the load immediate was not followed by a stack adjustment. */ | |
1429 | if (load_immediate_bytes && !seen_sp_adjust) | |
1430 | offset -= load_immediate_bytes; | |
1431 | return pc + offset; | |
bd5635a1 | 1432 | } |
c2a0f1cb | 1433 | |
002a422b JK |
1434 | #if 0 |
1435 | /* The lenient prologue stuff should be superceded by the code in | |
1436 | init_extra_frame_info which looks to see whether the stores mentioned | |
1437 | in the proc_desc have actually taken place. */ | |
1438 | ||
ee5fb959 JK |
1439 | /* Is address PC in the prologue (loosely defined) for function at |
1440 | STARTADDR? */ | |
1441 | ||
1442 | static int | |
1443 | mips_in_lenient_prologue (startaddr, pc) | |
1444 | CORE_ADDR startaddr; | |
1445 | CORE_ADDR pc; | |
1446 | { | |
1447 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
1448 | return pc >= startaddr && pc < end_prologue; | |
1449 | } | |
002a422b | 1450 | #endif |
ee5fb959 | 1451 | |
ac8cf67d PS |
1452 | /* Given a return value in `regbuf' with a type `valtype', |
1453 | extract and copy its value into `valbuf'. */ | |
1454 | void | |
1455 | mips_extract_return_value (valtype, regbuf, valbuf) | |
1456 | struct type *valtype; | |
1457 | char regbuf[REGISTER_BYTES]; | |
1458 | char *valbuf; | |
1459 | { | |
1460 | int regnum; | |
92a6d600 | 1461 | int offset = 0; |
ac8cf67d | 1462 | |
e4dbd248 PS |
1463 | regnum = 2; |
1464 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1465 | && (mips_fpu == MIPS_FPU_DOUBLE | |
28444bf3 | 1466 | || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) /* FIXME!! */ |
e4dbd248 | 1467 | regnum = FP0_REGNUM; |
ac8cf67d | 1468 | |
92a6d600 PS |
1469 | if (TARGET_BYTE_ORDER == BIG_ENDIAN |
1470 | && TYPE_CODE (valtype) != TYPE_CODE_FLT | |
1471 | && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (regnum)) | |
1472 | offset = REGISTER_RAW_SIZE (regnum) - TYPE_LENGTH (valtype); | |
1473 | ||
1474 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, | |
1475 | TYPE_LENGTH (valtype)); | |
ac8cf67d PS |
1476 | #ifdef REGISTER_CONVERT_TO_TYPE |
1477 | REGISTER_CONVERT_TO_TYPE(regnum, valtype, valbuf); | |
1478 | #endif | |
1479 | } | |
1480 | ||
1481 | /* Given a return value in `regbuf' with a type `valtype', | |
1482 | write it's value into the appropriate register. */ | |
1483 | void | |
1484 | mips_store_return_value (valtype, valbuf) | |
1485 | struct type *valtype; | |
1486 | char *valbuf; | |
1487 | { | |
1488 | int regnum; | |
1489 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
1490 | ||
e4dbd248 PS |
1491 | regnum = 2; |
1492 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1493 | && (mips_fpu == MIPS_FPU_DOUBLE | |
28444bf3 | 1494 | || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) /* FIXME!! */ |
e4dbd248 PS |
1495 | regnum = FP0_REGNUM; |
1496 | ||
ac8cf67d PS |
1497 | memcpy(raw_buffer, valbuf, TYPE_LENGTH (valtype)); |
1498 | ||
1499 | #ifdef REGISTER_CONVERT_FROM_TYPE | |
1500 | REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); | |
1501 | #endif | |
1502 | ||
1503 | write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, TYPE_LENGTH (valtype)); | |
1504 | } | |
1505 | ||
e03c0cc6 ILT |
1506 | /* Exported procedure: Is PC in the signal trampoline code */ |
1507 | ||
1508 | int | |
1509 | in_sigtramp (pc, ignore) | |
1510 | CORE_ADDR pc; | |
1511 | char *ignore; /* function name */ | |
1512 | { | |
1513 | if (sigtramp_address == 0) | |
1514 | fixup_sigtramp (); | |
1515 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
1516 | } | |
1517 | ||
e4dbd248 PS |
1518 | /* Command to set FPU type. mips_fpu_string will have been set to the |
1519 | user's argument. Set mips_fpu based on mips_fpu_string, and then | |
1520 | canonicalize mips_fpu_string. */ | |
1521 | ||
1522 | /*ARGSUSED*/ | |
1523 | static void | |
1524 | mips_set_fpu_command (args, from_tty, c) | |
1525 | char *args; | |
1526 | int from_tty; | |
1527 | struct cmd_list_element *c; | |
1528 | { | |
1529 | char *err = NULL; | |
1530 | ||
1531 | if (mips_fpu_string == NULL || *mips_fpu_string == '\0') | |
1532 | mips_fpu = MIPS_FPU_DOUBLE; | |
1533 | else if (strcasecmp (mips_fpu_string, "double") == 0 | |
1534 | || strcasecmp (mips_fpu_string, "on") == 0 | |
1535 | || strcasecmp (mips_fpu_string, "1") == 0 | |
1536 | || strcasecmp (mips_fpu_string, "yes") == 0) | |
1537 | mips_fpu = MIPS_FPU_DOUBLE; | |
1538 | else if (strcasecmp (mips_fpu_string, "none") == 0 | |
1539 | || strcasecmp (mips_fpu_string, "off") == 0 | |
1540 | || strcasecmp (mips_fpu_string, "0") == 0 | |
1541 | || strcasecmp (mips_fpu_string, "no") == 0) | |
1542 | mips_fpu = MIPS_FPU_NONE; | |
1543 | else if (strcasecmp (mips_fpu_string, "single") == 0) | |
1544 | mips_fpu = MIPS_FPU_SINGLE; | |
1545 | else | |
1546 | err = strsave (mips_fpu_string); | |
1547 | ||
1548 | if (mips_fpu_string != NULL) | |
1549 | free (mips_fpu_string); | |
1550 | ||
1551 | switch (mips_fpu) | |
1552 | { | |
1553 | case MIPS_FPU_DOUBLE: | |
1554 | mips_fpu_string = strsave ("double"); | |
1555 | break; | |
1556 | case MIPS_FPU_SINGLE: | |
1557 | mips_fpu_string = strsave ("single"); | |
1558 | break; | |
1559 | case MIPS_FPU_NONE: | |
1560 | mips_fpu_string = strsave ("none"); | |
1561 | break; | |
1562 | } | |
1563 | ||
1564 | if (err != NULL) | |
1565 | { | |
1566 | struct cleanup *cleanups = make_cleanup (free, err); | |
1567 | error ("Unknown FPU type `%s'. Use `double', `none', or `single'.", | |
1568 | err); | |
1569 | do_cleanups (cleanups); | |
1570 | } | |
1571 | } | |
1572 | ||
1573 | static void | |
1574 | mips_show_fpu_command (args, from_tty, c) | |
1575 | char *args; | |
1576 | int from_tty; | |
1577 | struct cmd_list_element *c; | |
1578 | { | |
1579 | } | |
1580 | ||
9f9f94aa SS |
1581 | /* Command to set the processor type. */ |
1582 | ||
1583 | void | |
1584 | mips_set_processor_type_command (args, from_tty) | |
1585 | char *args; | |
1586 | int from_tty; | |
1587 | { | |
1588 | int i; | |
1589 | ||
1590 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
1591 | { | |
1592 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
1593 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
1594 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
1595 | ||
1596 | /* Restore the value. */ | |
1597 | tmp_mips_processor_type = strsave (mips_processor_type); | |
1598 | ||
1599 | return; | |
1600 | } | |
1601 | ||
1602 | if (!mips_set_processor_type (tmp_mips_processor_type)) | |
1603 | { | |
1604 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
1605 | /* Restore its value. */ | |
1606 | tmp_mips_processor_type = strsave (mips_processor_type); | |
1607 | } | |
1608 | } | |
1609 | ||
1610 | static void | |
1611 | mips_show_processor_type_command (args, from_tty) | |
1612 | char *args; | |
1613 | int from_tty; | |
1614 | { | |
1615 | } | |
1616 | ||
1617 | /* Modify the actual processor type. */ | |
1618 | ||
1619 | int | |
1620 | mips_set_processor_type (str) | |
1621 | char *str; | |
1622 | { | |
1623 | int i, j; | |
1624 | ||
1625 | if (str == NULL) | |
1d9489c1 | 1626 | return 0; |
9f9f94aa SS |
1627 | |
1628 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
1629 | { | |
1630 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
1631 | { | |
1632 | mips_processor_type = str; | |
1633 | ||
1634 | for (j = 0; j < NUM_REGS; ++j) | |
1635 | reg_names[j] = mips_processor_type_table[i].regnames[j]; | |
1636 | ||
1637 | return 1; | |
1638 | ||
1639 | /* FIXME tweak fpu flag too */ | |
1640 | } | |
1641 | } | |
1642 | ||
1643 | return 0; | |
1644 | } | |
1645 | ||
1646 | /* Attempt to identify the particular processor model by reading the | |
1647 | processor id. */ | |
1648 | ||
1649 | char * | |
1650 | mips_read_processor_type () | |
1651 | { | |
28444bf3 | 1652 | CORE_ADDR prid; |
9f9f94aa SS |
1653 | |
1654 | prid = read_register (PRID_REGNUM); | |
1655 | ||
80e0e92a | 1656 | if ((prid & ~0xf) == 0x700) |
9f9f94aa SS |
1657 | return savestring ("r3041", strlen("r3041")); |
1658 | ||
1659 | return NULL; | |
1660 | } | |
427fec5d JK |
1661 | |
1662 | /* Just like reinit_frame_cache, but with the right arguments to be | |
1663 | callable as an sfunc. */ | |
9f9f94aa | 1664 | |
427fec5d JK |
1665 | static void |
1666 | reinit_frame_cache_sfunc (args, from_tty, c) | |
1667 | char *args; | |
1668 | int from_tty; | |
1669 | struct cmd_list_element *c; | |
1670 | { | |
1671 | reinit_frame_cache (); | |
1672 | } | |
c2a0f1cb | 1673 | |
28444bf3 | 1674 | static int |
18b46e7c SS |
1675 | gdb_print_insn_mips (memaddr, info) |
1676 | bfd_vma memaddr; | |
1677 | disassemble_info *info; | |
1678 | { | |
1679 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1680 | return print_insn_big_mips (memaddr, info); | |
1681 | else | |
1682 | return print_insn_little_mips (memaddr, info); | |
1683 | } | |
1684 | ||
c2a0f1cb ILT |
1685 | void |
1686 | _initialize_mips_tdep () | |
1687 | { | |
427fec5d JK |
1688 | struct cmd_list_element *c; |
1689 | ||
18b46e7c SS |
1690 | tm_print_insn = gdb_print_insn_mips; |
1691 | ||
427fec5d JK |
1692 | /* Let the user turn off floating point and set the fence post for |
1693 | heuristic_proc_start. */ | |
1694 | ||
e4dbd248 PS |
1695 | c = add_set_cmd ("mipsfpu", class_support, var_string_noescape, |
1696 | (char *) &mips_fpu_string, | |
1697 | "Set use of floating point coprocessor.\n\ | |
1698 | Set to `none' to avoid using floating point instructions when calling\n\ | |
1699 | functions or dealing with return values. Set to `single' to use only\n\ | |
1700 | single precision floating point as on the R4650. Set to `double' for\n\ | |
1701 | normal floating point support.", | |
1702 | &setlist); | |
1703 | c->function.sfunc = mips_set_fpu_command; | |
1704 | c = add_show_from_set (c, &showlist); | |
1705 | c->function.sfunc = mips_show_fpu_command; | |
1706 | ||
1707 | mips_fpu = MIPS_FPU_DOUBLE; | |
1708 | mips_fpu_string = strsave ("double"); | |
3127785a | 1709 | |
9f9f94aa SS |
1710 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
1711 | (char *) &tmp_mips_processor_type, | |
1712 | "Set the type of MIPS processor in use.\n\ | |
1713 | Set this to be able to access processor-type-specific registers.\n\ | |
1714 | ", | |
1715 | &setlist); | |
1716 | c->function.cfunc = mips_set_processor_type_command; | |
1717 | c = add_show_from_set (c, &showlist); | |
1718 | c->function.cfunc = mips_show_processor_type_command; | |
1719 | ||
1720 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
1721 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
1722 | ||
bdef72d2 JK |
1723 | /* We really would like to have both "0" and "unlimited" work, but |
1724 | command.c doesn't deal with that. So make it a var_zinteger | |
1725 | because the user can always use "999999" or some such for unlimited. */ | |
1726 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
427fec5d JK |
1727 | (char *) &heuristic_fence_post, |
1728 | "\ | |
23d35572 JK |
1729 | Set the distance searched for the start of a function.\n\ |
1730 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
1731 | program for the start of a function. This command sets the distance of the\n\ | |
1732 | search. The only need to set it is when debugging a stripped executable.", | |
427fec5d JK |
1733 | &setlist); |
1734 | /* We need to throw away the frame cache when we set this, since it | |
1735 | might change our ability to get backtraces. */ | |
1736 | c->function.sfunc = reinit_frame_cache_sfunc; | |
1737 | add_show_from_set (c, &showlist); | |
c2a0f1cb | 1738 | } |