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7d9884b9 | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
97e091b2 | 2 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996 |
0434c1a0 | 3 | Free Software Foundation, Inc. |
bd5635a1 RP |
4 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
5 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
361bf6ee | 9 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 10 | it under the terms of the GNU General Public License as published by |
361bf6ee JG |
11 | the Free Software Foundation; either version 2 of the License, or |
12 | (at your option) any later version. | |
bd5635a1 | 13 | |
361bf6ee | 14 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
361bf6ee | 20 | along with this program; if not, write to the Free Software |
09af5868 | 21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
bd5635a1 | 22 | |
bd5635a1 | 23 | #include "defs.h" |
09af5868 | 24 | #include "gdb_string.h" |
bd5635a1 RP |
25 | #include "frame.h" |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "value.h" | |
29 | #include "gdbcmd.h" | |
ef08856f | 30 | #include "language.h" |
bd5635a1 | 31 | #include "gdbcore.h" |
62a469e1 SG |
32 | #include "symfile.h" |
33 | #include "objfiles.h" | |
3fed1c4a | 34 | #include "gdbtypes.h" |
28444bf3 | 35 | #include "target.h" |
bd5635a1 | 36 | |
ee5fb959 JK |
37 | #include "opcode/mips.h" |
38 | ||
28444bf3 | 39 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
70126bf9 KH |
40 | |
41 | /* FIXME: Put this declaration in frame.h. */ | |
42 | extern struct obstack frame_cache_obstack; | |
28444bf3 | 43 | |
002a422b | 44 | #if 0 |
ee5fb959 | 45 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
002a422b | 46 | #endif |
ee5fb959 | 47 | |
28444bf3 DP |
48 | static int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *)); |
49 | ||
f2bf454e FF |
50 | static void mips_print_register PARAMS ((int, int)); |
51 | ||
52 | static mips_extra_func_info_t | |
53 | heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *)); | |
54 | ||
55 | static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR)); | |
56 | ||
28444bf3 | 57 | static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int)); |
f2bf454e | 58 | |
e4dbd248 PS |
59 | static void mips_set_fpu_command PARAMS ((char *, int, |
60 | struct cmd_list_element *)); | |
61 | ||
62 | static void mips_show_fpu_command PARAMS ((char *, int, | |
63 | struct cmd_list_element *)); | |
64 | ||
9f9f94aa SS |
65 | void mips_set_processor_type_command PARAMS ((char *, int)); |
66 | ||
1d9489c1 JK |
67 | int mips_set_processor_type PARAMS ((char *)); |
68 | ||
69 | static void mips_show_processor_type_command PARAMS ((char *, int)); | |
70 | ||
9f9f94aa SS |
71 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, |
72 | struct cmd_list_element *)); | |
73 | ||
f2bf454e FF |
74 | static mips_extra_func_info_t |
75 | find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info *next_frame)); | |
76 | ||
77 | static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc, | |
78 | mips_extra_func_info_t proc_desc)); | |
79 | ||
9f9f94aa SS |
80 | /* This value is the model of MIPS in use. It is derived from the value |
81 | of the PrID register. */ | |
82 | ||
83 | char *mips_processor_type; | |
84 | ||
85 | char *tmp_mips_processor_type; | |
86 | ||
c2a0f1cb ILT |
87 | /* Some MIPS boards don't support floating point, so we permit the |
88 | user to turn it off. */ | |
9f9f94aa | 89 | |
e4dbd248 PS |
90 | enum mips_fpu_type mips_fpu; |
91 | ||
92 | static char *mips_fpu_string; | |
c2a0f1cb | 93 | |
9f9f94aa SS |
94 | /* A set of original names, to be used when restoring back to generic |
95 | registers from a specific set. */ | |
96 | ||
97 | char *mips_generic_reg_names[] = REGISTER_NAMES; | |
98 | ||
99 | /* Names of IDT R3041 registers. */ | |
100 | ||
101 | char *mips_r3041_reg_names[] = { | |
102 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
103 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
104 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
105 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
106 | "sr", "lo", "hi", "bad", "cause","pc", | |
107 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
108 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
109 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
110 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
111 | "fsr", "fir", "fp", "", | |
112 | "", "", "bus", "ccfg", "", "", "", "", | |
113 | "", "", "port", "cmp", "", "", "epc", "prid", | |
114 | }; | |
115 | ||
116 | /* Names of IDT R3051 registers. */ | |
117 | ||
118 | char *mips_r3051_reg_names[] = { | |
119 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
120 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
121 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
122 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
123 | "sr", "lo", "hi", "bad", "cause","pc", | |
124 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
125 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
126 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
127 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
128 | "fsr", "fir", "fp", "", | |
129 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
130 | "", "", "ehi", "", "", "", "epc", "prid", | |
131 | }; | |
132 | ||
133 | /* Names of IDT R3081 registers. */ | |
134 | ||
135 | char *mips_r3081_reg_names[] = { | |
136 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
137 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
138 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
139 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
140 | "sr", "lo", "hi", "bad", "cause","pc", | |
141 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
142 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
143 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
144 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
145 | "fsr", "fir", "fp", "", | |
146 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
147 | "", "", "ehi", "", "", "", "epc", "prid", | |
148 | }; | |
149 | ||
e4dbd248 PS |
150 | /* Names of LSI 33k registers. */ |
151 | ||
152 | char *mips_lsi33k_reg_names[] = { | |
153 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
154 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
155 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
156 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
157 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
158 | "dcic", "bpc", "bda", "", "", "", "", "", | |
159 | "", "", "", "", "", "", "", "", | |
160 | "", "", "", "", "", "", "", "", | |
161 | "", "", "", "", "", "", "", "", | |
162 | "", "", "", "", | |
163 | "", "", "", "", "", "", "", "", | |
164 | "", "", "", "", "", "", "", "", | |
165 | }; | |
166 | ||
9f9f94aa SS |
167 | struct { |
168 | char *name; | |
169 | char **regnames; | |
170 | } mips_processor_type_table[] = { | |
171 | { "generic", mips_generic_reg_names }, | |
172 | { "r3041", mips_r3041_reg_names }, | |
173 | { "r3051", mips_r3051_reg_names }, | |
174 | { "r3071", mips_r3081_reg_names }, | |
175 | { "r3081", mips_r3081_reg_names }, | |
e4dbd248 | 176 | { "lsi33k", mips_lsi33k_reg_names }, |
9f9f94aa SS |
177 | { NULL, NULL } |
178 | }; | |
179 | ||
f9f8c14b MA |
180 | /* Table to translate MIPS16 register field to actual register number. */ |
181 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; | |
182 | ||
3127785a RP |
183 | /* Heuristic_proc_start may hunt through the text section for a long |
184 | time across a 2400 baud serial line. Allows the user to limit this | |
185 | search. */ | |
9f9f94aa | 186 | |
3127785a RP |
187 | static unsigned int heuristic_fence_post = 0; |
188 | ||
0f552c5f | 189 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
28444bf3 | 190 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ |
0f552c5f JG |
191 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
192 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
193 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
194 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
195 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
196 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
197 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
198 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
bd5635a1 | 199 | #define _PROC_MAGIC_ 0x0F0F0F0F |
0f552c5f JG |
200 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
201 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
bd5635a1 RP |
202 | |
203 | struct linked_proc_info | |
204 | { | |
205 | struct mips_extra_func_info info; | |
206 | struct linked_proc_info *next; | |
dac4929a | 207 | } *linked_proc_desc_table = NULL; |
bd5635a1 | 208 | |
f2bf454e FF |
209 | |
210 | /* This returns the PC of the first inst after the prologue. If we can't | |
211 | find the prologue, then return 0. */ | |
212 | ||
213 | static CORE_ADDR | |
214 | after_prologue (pc, proc_desc) | |
215 | CORE_ADDR pc; | |
216 | mips_extra_func_info_t proc_desc; | |
217 | { | |
218 | struct symtab_and_line sal; | |
219 | CORE_ADDR func_addr, func_end; | |
220 | ||
221 | if (!proc_desc) | |
222 | proc_desc = find_proc_desc (pc, NULL); | |
223 | ||
224 | if (proc_desc) | |
225 | { | |
226 | /* If function is frameless, then we need to do it the hard way. I | |
227 | strongly suspect that frameless always means prologueless... */ | |
228 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
229 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
230 | return 0; | |
231 | } | |
232 | ||
233 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
234 | return 0; /* Unknown */ | |
235 | ||
236 | sal = find_pc_line (func_addr, 0); | |
237 | ||
238 | if (sal.end < func_end) | |
239 | return sal.end; | |
240 | ||
241 | /* The line after the prologue is after the end of the function. In this | |
242 | case, tell the caller to find the prologue the hard way. */ | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
f9f8c14b MA |
247 | /* Decode a MIPS32 instruction that saves a register in the stack, and |
248 | set the appropriate bit in the general register mask or float register mask | |
249 | to indicate which register is saved. This is a helper function | |
250 | for mips_find_saved_regs. */ | |
251 | ||
252 | static void | |
253 | mips32_decode_reg_save (inst, gen_mask, float_mask) | |
254 | t_inst inst; | |
255 | unsigned long *gen_mask; | |
256 | unsigned long *float_mask; | |
257 | { | |
258 | int reg; | |
259 | ||
260 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
261 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
262 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
263 | { | |
264 | /* It might be possible to use the instruction to | |
265 | find the offset, rather than the code below which | |
266 | is based on things being in a certain order in the | |
267 | frame, but figuring out what the instruction's offset | |
268 | is relative to might be a little tricky. */ | |
269 | reg = (inst & 0x001f0000) >> 16; | |
270 | *gen_mask |= (1 << reg); | |
271 | } | |
272 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
273 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ | |
274 | || (inst & 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */ | |
275 | ||
276 | { | |
277 | reg = ((inst & 0x001f0000) >> 16); | |
278 | *float_mask |= (1 << reg); | |
279 | } | |
280 | } | |
281 | ||
282 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
283 | set the appropriate bit in the general register or float register mask | |
284 | to indicate which register is saved. This is a helper function | |
285 | for mips_find_saved_regs. */ | |
286 | ||
287 | static void | |
288 | mips16_decode_reg_save (inst, gen_mask) | |
289 | t_inst inst; | |
290 | unsigned long *gen_mask; | |
291 | { | |
b348b9fd | 292 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
f9f8c14b | 293 | { |
b348b9fd MA |
294 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; |
295 | *gen_mask |= (1 << reg); | |
296 | } | |
297 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
298 | { | |
299 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
f9f8c14b MA |
300 | *gen_mask |= (1 << reg); |
301 | } | |
302 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ | |
303 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
304 | *gen_mask |= (1 << 31); | |
305 | } | |
306 | ||
c81a76b3 MA |
307 | |
308 | /* Fetch and return instruction from the specified location. If the PC | |
309 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
310 | ||
311 | static t_inst | |
312 | mips_fetch_instruction (addr) | |
313 | CORE_ADDR addr; | |
314 | { | |
315 | char buf[MIPS_INSTLEN]; | |
316 | int instlen; | |
317 | int status; | |
318 | ||
319 | if (IS_MIPS16_ADDR (addr)) | |
320 | { | |
321 | instlen = MIPS16_INSTLEN; | |
322 | addr = UNMAKE_MIPS16_ADDR (addr); | |
323 | } | |
324 | else | |
325 | instlen = MIPS_INSTLEN; | |
326 | status = read_memory_nobpt (addr, buf, instlen); | |
327 | if (status) | |
328 | memory_error (status, addr); | |
329 | return extract_unsigned_integer (buf, instlen); | |
330 | } | |
331 | ||
332 | ||
70126bf9 KH |
333 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
334 | NULL). */ | |
335 | ||
336 | void | |
337 | mips_find_saved_regs (fci) | |
9f9f94aa | 338 | struct frame_info *fci; |
70126bf9 KH |
339 | { |
340 | int ireg; | |
341 | CORE_ADDR reg_position; | |
342 | /* r0 bit means kernel trap */ | |
343 | int kernel_trap; | |
344 | /* What registers have been saved? Bitmasks. */ | |
345 | unsigned long gen_mask, float_mask; | |
346 | mips_extra_func_info_t proc_desc; | |
c81a76b3 | 347 | t_inst inst; |
70126bf9 KH |
348 | |
349 | fci->saved_regs = (struct frame_saved_regs *) | |
350 | obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs)); | |
351 | memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs)); | |
352 | ||
e4dbd248 PS |
353 | /* If it is the frame for sigtramp, the saved registers are located |
354 | in a sigcontext structure somewhere on the stack. | |
355 | If the stack layout for sigtramp changes we might have to change these | |
356 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
357 | #ifndef SIGFRAME_BASE | |
358 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
359 | above the sigtramp frame. */ | |
28444bf3 DP |
360 | #define SIGFRAME_BASE MIPS_REGSIZE |
361 | /* FIXME! Are these correct?? */ | |
362 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
363 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
364 | #define SIGFRAME_FPREGSAVE_OFF \ | |
365 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
e4dbd248 PS |
366 | #endif |
367 | #ifndef SIGFRAME_REG_SIZE | |
28444bf3 DP |
368 | /* FIXME! Is this correct?? */ |
369 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
e4dbd248 PS |
370 | #endif |
371 | if (fci->signal_handler_caller) | |
372 | { | |
28444bf3 | 373 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
374 | { |
375 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF | |
376 | + ireg * SIGFRAME_REG_SIZE; | |
377 | fci->saved_regs->regs[ireg] = reg_position; | |
378 | } | |
28444bf3 | 379 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
380 | { |
381 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF | |
382 | + ireg * SIGFRAME_REG_SIZE; | |
383 | fci->saved_regs->regs[FP0_REGNUM + ireg] = reg_position; | |
384 | } | |
385 | fci->saved_regs->regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
386 | return; | |
387 | } | |
388 | ||
70126bf9 KH |
389 | proc_desc = fci->proc_desc; |
390 | if (proc_desc == NULL) | |
391 | /* I'm not sure how/whether this can happen. Normally when we can't | |
392 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
393 | and set the saved_regs right away. */ | |
394 | return; | |
395 | ||
396 | kernel_trap = PROC_REG_MASK(proc_desc) & 1; | |
397 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); | |
398 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); | |
399 | ||
f9f8c14b MA |
400 | if (/* In any frame other than the innermost or a frame interrupted by |
401 | a signal, we assume that all registers have been saved. | |
402 | This assumes that all register saves in a function happen before | |
403 | the first function call. */ | |
404 | (fci->next == NULL || fci->next->signal_handler_caller) | |
70126bf9 KH |
405 | |
406 | /* In a dummy frame we know exactly where things are saved. */ | |
407 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
408 | ||
f2bf454e FF |
409 | /* Don't bother unless we are inside a function prologue. Outside the |
410 | prologue, we know where everything is. */ | |
411 | ||
412 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) | |
413 | ||
70126bf9 KH |
414 | /* Not sure exactly what kernel_trap means, but if it means |
415 | the kernel saves the registers without a prologue doing it, | |
416 | we better not examine the prologue to see whether registers | |
417 | have been saved yet. */ | |
418 | && !kernel_trap) | |
419 | { | |
420 | /* We need to figure out whether the registers that the proc_desc | |
421 | claims are saved have been saved yet. */ | |
422 | ||
423 | CORE_ADDR addr; | |
70126bf9 KH |
424 | |
425 | /* Bitmasks; set if we have found a save for the register. */ | |
426 | unsigned long gen_save_found = 0; | |
427 | unsigned long float_save_found = 0; | |
c81a76b3 | 428 | int instlen; |
70126bf9 | 429 | |
c1fc0935 MA |
430 | /* If the address is odd, assume this is MIPS16 code. */ |
431 | addr = PROC_LOW_ADDR (proc_desc); | |
c81a76b3 | 432 | instlen = IS_MIPS16_ADDR (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
f9f8c14b | 433 | |
20fa0902 MA |
434 | /* Scan through this function's instructions preceding the current |
435 | PC, and look for those that save registers. */ | |
f9f8c14b MA |
436 | while (addr < fci->pc) |
437 | { | |
c81a76b3 MA |
438 | inst = mips_fetch_instruction (addr); |
439 | if (IS_MIPS16_ADDR (addr)) | |
f9f8c14b MA |
440 | mips16_decode_reg_save (inst, &gen_save_found); |
441 | else | |
442 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
443 | addr += instlen; | |
70126bf9 KH |
444 | } |
445 | gen_mask = gen_save_found; | |
446 | float_mask = float_save_found; | |
447 | } | |
448 | ||
449 | /* Fill in the offsets for the registers which gen_mask says | |
450 | were saved. */ | |
451 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
28444bf3 | 452 | for (ireg= MIPS_NUMREGS-1; gen_mask; --ireg, gen_mask <<= 1) |
70126bf9 KH |
453 | if (gen_mask & 0x80000000) |
454 | { | |
455 | fci->saved_regs->regs[ireg] = reg_position; | |
456 | reg_position -= MIPS_REGSIZE; | |
457 | } | |
c81a76b3 MA |
458 | |
459 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
460 | of that normally used by gcc. Therefore, we have to fetch the first | |
461 | instruction of the function, and if it's an entry instruction that | |
462 | saves $s0 or $s1, correct their saved addresses. */ | |
463 | if (IS_MIPS16_ADDR (PROC_LOW_ADDR (proc_desc))) | |
464 | { | |
465 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
466 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
467 | { | |
468 | int reg; | |
469 | int sreg_count = (inst >> 6) & 3; | |
470 | ||
471 | /* Check if the ra register was pushed on the stack. */ | |
472 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
473 | if (inst & 0x20) | |
474 | reg_position -= MIPS_REGSIZE; | |
475 | ||
476 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
477 | for (reg = 16; reg < sreg_count+16; reg++) | |
478 | { | |
479 | fci->saved_regs->regs[reg] = reg_position; | |
480 | reg_position -= MIPS_REGSIZE; | |
481 | } | |
482 | } | |
483 | } | |
484 | ||
70126bf9 KH |
485 | /* Fill in the offsets for the registers which float_mask says |
486 | were saved. */ | |
487 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
488 | ||
489 | /* The freg_offset points to where the first *double* register | |
490 | is saved. So skip to the high-order word. */ | |
28444bf3 | 491 | if (! GDB_TARGET_IS_MIPS64) |
c81a76b3 | 492 | reg_position += MIPS_REGSIZE; |
28444bf3 | 493 | |
20fa0902 MA |
494 | /* Fill in the offsets for the float registers which float_mask says |
495 | were saved. */ | |
28444bf3 | 496 | for (ireg = MIPS_NUMREGS-1; float_mask; --ireg, float_mask <<= 1) |
70126bf9 KH |
497 | if (float_mask & 0x80000000) |
498 | { | |
499 | fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position; | |
500 | reg_position -= MIPS_REGSIZE; | |
501 | } | |
502 | ||
503 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; | |
504 | } | |
bd5635a1 | 505 | |
28444bf3 | 506 | static CORE_ADDR |
bd5635a1 | 507 | read_next_frame_reg(fi, regno) |
9f9f94aa | 508 | struct frame_info *fi; |
bd5635a1 RP |
509 | int regno; |
510 | { | |
bd5635a1 | 511 | for (; fi; fi = fi->next) |
70126bf9 | 512 | { |
e4dbd248 PS |
513 | /* We have to get the saved sp from the sigcontext |
514 | if it is a signal handler frame. */ | |
515 | if (regno == SP_REGNUM && !fi->signal_handler_caller) | |
516 | return fi->frame; | |
70126bf9 KH |
517 | else |
518 | { | |
519 | if (fi->saved_regs == NULL) | |
520 | mips_find_saved_regs (fi); | |
521 | if (fi->saved_regs->regs[regno]) | |
522 | return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE); | |
523 | } | |
524 | } | |
525 | return read_register (regno); | |
bd5635a1 RP |
526 | } |
527 | ||
96431497 MA |
528 | /* mips_addr_bits_remove - remove useless address bits */ |
529 | ||
530 | CORE_ADDR | |
531 | mips_addr_bits_remove (addr) | |
532 | CORE_ADDR addr; | |
533 | { | |
97e091b2 MA |
534 | #if GDB_TARGET_IS_MIPS64 |
535 | if ((addr >> 32 == (CORE_ADDR)0xffffffff) | |
f781fe93 MA |
536 | && (strcmp (target_shortname,"pmon")==0 |
537 | || strcmp (target_shortname,"ddb")==0 | |
538 | || strcmp (target_shortname,"sim")==0)) | |
96431497 MA |
539 | { |
540 | /* This hack is a work-around for existing boards using PMON, | |
541 | the simulator, and any other 64-bit targets that doesn't have | |
542 | true 64-bit addressing. On these targets, the upper 32 bits | |
543 | of addresses are ignored by the hardware. Thus, the PC or SP | |
544 | are likely to have been sign extended to all 1s by instruction | |
545 | sequences that load 32-bit addresses. For example, a typical | |
546 | piece of code that loads an address is this: | |
547 | lui $r2, <upper 16 bits> | |
548 | ori $r2, <lower 16 bits> | |
549 | But the lui sign-extends the value such that the upper 32 bits | |
550 | may be all 1s. The workaround is simply to mask off these bits. | |
551 | In the future, gcc may be changed to support true 64-bit | |
552 | addressing, and this masking will have to be disabled. */ | |
553 | addr &= (CORE_ADDR)0xffffffff; | |
554 | } | |
f9f8c14b MA |
555 | #else |
556 | /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf), | |
557 | BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits. | |
558 | So we still have to mask off useless bits from addresses. */ | |
559 | addr &= (CORE_ADDR)0xffffffff; | |
97e091b2 | 560 | #endif |
96431497 MA |
561 | |
562 | return addr; | |
563 | } | |
564 | ||
f781fe93 MA |
565 | void |
566 | mips_init_frame_pc_first (fromleaf, prev) | |
567 | int fromleaf; | |
568 | struct frame_info *prev; | |
569 | { | |
570 | CORE_ADDR pc, tmp; | |
571 | ||
572 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
573 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); | |
574 | tmp = mips_skip_stub (pc); | |
575 | prev->pc = tmp ? tmp : pc; | |
576 | } | |
577 | ||
578 | ||
28444bf3 | 579 | CORE_ADDR |
bd5635a1 | 580 | mips_frame_saved_pc(frame) |
9f9f94aa | 581 | struct frame_info *frame; |
bd5635a1 | 582 | { |
28444bf3 | 583 | CORE_ADDR saved_pc; |
0f552c5f | 584 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
0434c1a0 PS |
585 | /* We have to get the saved pc from the sigcontext |
586 | if it is a signal handler frame. */ | |
587 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
588 | : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); | |
0f552c5f | 589 | |
bd5635a1 | 590 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
28444bf3 DP |
591 | saved_pc = read_memory_integer(frame->frame - MIPS_REGSIZE, MIPS_REGSIZE); |
592 | else | |
593 | saved_pc = read_next_frame_reg(frame, pcreg); | |
0f552c5f | 594 | |
96431497 | 595 | return ADDR_BITS_REMOVE (saved_pc); |
bd5635a1 RP |
596 | } |
597 | ||
598 | static struct mips_extra_func_info temp_proc_desc; | |
599 | static struct frame_saved_regs temp_saved_regs; | |
600 | ||
a8172eea RP |
601 | /* This fencepost looks highly suspicious to me. Removing it also |
602 | seems suspicious as it could affect remote debugging across serial | |
3127785a | 603 | lines. */ |
a8172eea | 604 | |
0f552c5f JG |
605 | static CORE_ADDR |
606 | heuristic_proc_start(pc) | |
bd5635a1 RP |
607 | CORE_ADDR pc; |
608 | { | |
32dab603 MA |
609 | CORE_ADDR start_pc; |
610 | CORE_ADDR fence; | |
20fa0902 | 611 | int instlen; |
b348b9fd | 612 | int seen_adjsp = 0; |
0f552c5f | 613 | |
32dab603 MA |
614 | pc = ADDR_BITS_REMOVE (pc); |
615 | start_pc = pc; | |
616 | fence = start_pc - heuristic_fence_post; | |
0f552c5f | 617 | if (start_pc == 0) return 0; |
3127785a RP |
618 | |
619 | if (heuristic_fence_post == UINT_MAX | |
620 | || fence < VM_MIN_ADDRESS) | |
621 | fence = VM_MIN_ADDRESS; | |
0f552c5f | 622 | |
c1fc0935 | 623 | instlen = IS_MIPS16_ADDR (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
20fa0902 | 624 | |
bd5635a1 | 625 | /* search back for previous return */ |
20fa0902 | 626 | for (start_pc -= instlen; ; start_pc -= instlen) |
a8172eea RP |
627 | if (start_pc < fence) |
628 | { | |
3127785a RP |
629 | /* It's not clear to me why we reach this point when |
630 | stop_soon_quietly, but with this test, at least we | |
631 | don't print out warnings for every child forked (eg, on | |
632 | decstation). 22apr93 rich@cygnus.com. */ | |
633 | if (!stop_soon_quietly) | |
634 | { | |
23d35572 JK |
635 | static int blurb_printed = 0; |
636 | ||
3127785a RP |
637 | if (fence == VM_MIN_ADDRESS) |
638 | warning("Hit beginning of text section without finding"); | |
639 | else | |
640 | warning("Hit heuristic-fence-post without finding"); | |
641 | ||
f781fe93 | 642 | warning("enclosing function for address 0x%s", paddr_nz (pc)); |
23d35572 JK |
643 | if (!blurb_printed) |
644 | { | |
645 | printf_filtered ("\ | |
646 | This warning occurs if you are debugging a function without any symbols\n\ | |
647 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
648 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
649 | \n\ | |
650 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
651 | (more likely) you have encountered a bug in GDB.\n"); | |
652 | blurb_printed = 1; | |
653 | } | |
3127785a RP |
654 | } |
655 | ||
a8172eea RP |
656 | return 0; |
657 | } | |
c1fc0935 | 658 | else if (IS_MIPS16_ADDR (start_pc)) |
20fa0902 | 659 | { |
c1fc0935 MA |
660 | unsigned short inst; |
661 | ||
b348b9fd MA |
662 | /* On MIPS16, any one of the following is likely to be the |
663 | start of a function: | |
664 | entry | |
665 | addiu sp,-n | |
666 | daddiu sp,-n | |
667 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
c81a76b3 | 668 | inst = mips_fetch_instruction (start_pc); |
b348b9fd MA |
669 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
670 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
671 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
672 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
673 | break; | |
674 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
675 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
676 | seen_adjsp = 1; | |
677 | else | |
678 | seen_adjsp = 0; | |
20fa0902 | 679 | } |
bd5635a1 | 680 | else if (ABOUT_TO_RETURN(start_pc)) |
20fa0902 MA |
681 | { |
682 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
bd5635a1 | 683 | break; |
20fa0902 | 684 | } |
bd5635a1 | 685 | |
bd5635a1 RP |
686 | #if 0 |
687 | /* skip nops (usually 1) 0 - is this */ | |
28444bf3 DP |
688 | while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) |
689 | start_pc += MIPS_INSTLEN; | |
bd5635a1 RP |
690 | #endif |
691 | return start_pc; | |
692 | } | |
693 | ||
c81a76b3 | 694 | /* Fetch the immediate value from a MIPS16 instruction. |
b348b9fd MA |
695 | If the previous instruction was an EXTEND, use it to extend |
696 | the upper bits of the immediate value. This is a helper function | |
697 | for mips16_heuristic_proc_desc. */ | |
698 | ||
699 | static int | |
700 | mips16_get_imm (prev_inst, inst, nbits, scale, is_signed) | |
701 | unsigned short prev_inst; /* previous instruction */ | |
702 | unsigned short inst; /* current current instruction */ | |
703 | int nbits; /* number of bits in imm field */ | |
704 | int scale; /* scale factor to be applied to imm */ | |
705 | int is_signed; /* is the imm field signed? */ | |
706 | { | |
707 | int offset; | |
708 | ||
709 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
710 | { | |
7d9e8fac | 711 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); |
b348b9fd MA |
712 | if (offset & 0x8000) /* check for negative extend */ |
713 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
714 | return offset | (inst & 0x1f); | |
715 | } | |
716 | else | |
717 | { | |
718 | int max_imm = 1 << nbits; | |
719 | int mask = max_imm - 1; | |
720 | int sign_bit = max_imm >> 1; | |
721 | ||
722 | offset = inst & mask; | |
723 | if (is_signed && (offset & sign_bit)) | |
724 | offset = 0 - (max_imm - offset); | |
725 | return offset * scale; | |
726 | } | |
727 | } | |
728 | ||
729 | ||
730 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
731 | stream from start_pc to limit_pc. */ | |
732 | ||
733 | static void | |
734 | mips16_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp) | |
bd5635a1 | 735 | CORE_ADDR start_pc, limit_pc; |
9f9f94aa | 736 | struct frame_info *next_frame; |
b348b9fd | 737 | CORE_ADDR sp; |
bd5635a1 | 738 | { |
b348b9fd MA |
739 | CORE_ADDR cur_pc; |
740 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
741 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
742 | unsigned inst = 0; /* current instruction */ | |
bd5635a1 | 743 | |
b348b9fd | 744 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; |
34df79fc | 745 | |
b348b9fd MA |
746 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) |
747 | { | |
c81a76b3 | 748 | int reg, offset; |
b348b9fd MA |
749 | |
750 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
751 | the immediate offset extension from it in mips16_get_imm. */ | |
752 | prev_inst = inst; | |
753 | ||
c81a76b3 MA |
754 | /* Fetch and decode the instruction. */ |
755 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
b348b9fd MA |
756 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
757 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
758 | { | |
759 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
760 | if (offset < 0) /* negative stack adjustment? */ | |
761 | PROC_FRAME_OFFSET(&temp_proc_desc) -= offset; | |
762 | else | |
763 | /* Exit loop if a positive stack adjustment is found, which | |
764 | usually means that the stack cleanup code in the function | |
765 | epilogue is reached. */ | |
766 | break; | |
767 | } | |
768 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
769 | { | |
770 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
771 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
772 | PROC_REG_MASK(&temp_proc_desc) |= (1 << reg); | |
773 | temp_saved_regs.regs[reg] = sp + offset; | |
774 | } | |
775 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
776 | { | |
777 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
778 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
779 | PROC_REG_MASK(&temp_proc_desc) |= (1 << reg); | |
780 | temp_saved_regs.regs[reg] = sp + offset; | |
781 | } | |
782 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
783 | { | |
784 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
785 | PROC_REG_MASK(&temp_proc_desc) |= (1 << 31); | |
786 | temp_saved_regs.regs[31] = sp + offset; | |
97e091b2 | 787 | } |
b348b9fd MA |
788 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
789 | { | |
790 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
791 | PROC_REG_MASK(&temp_proc_desc) |= (1 << 31); | |
792 | temp_saved_regs.regs[31] = sp + offset; | |
bd5635a1 | 793 | } |
b348b9fd MA |
794 | else if (inst == 0x673d) /* move $s1, $sp */ |
795 | { | |
796 | frame_addr = read_next_frame_reg(next_frame, 30); | |
797 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
97e091b2 | 798 | } |
32dab603 MA |
799 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ |
800 | { | |
801 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
802 | frame_addr = sp + offset; | |
803 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
804 | } | |
b348b9fd MA |
805 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ |
806 | { | |
807 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
808 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
809 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
810 | temp_saved_regs.regs[reg] = frame_addr + offset; | |
811 | } | |
812 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
813 | { | |
814 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
815 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
816 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
817 | temp_saved_regs.regs[reg] = frame_addr + offset; | |
818 | } | |
819 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
820 | { | |
821 | int areg_count = (inst >> 8) & 7; | |
822 | int sreg_count = (inst >> 6) & 3; | |
823 | ||
824 | /* The entry instruction always subtracts 32 from the SP. */ | |
825 | PROC_FRAME_OFFSET(&temp_proc_desc) += 32; | |
826 | ||
827 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
c81a76b3 | 828 | for (reg = 4, offset = 32; reg < areg_count+4; reg++) |
b348b9fd MA |
829 | { |
830 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
831 | temp_saved_regs.regs[reg] = sp + offset; | |
c81a76b3 | 832 | offset -= MIPS_REGSIZE; |
b348b9fd MA |
833 | } |
834 | ||
835 | /* Check if the ra register was pushed on the stack. */ | |
836 | offset = 28; | |
837 | if (inst & 0x20) | |
838 | { | |
839 | PROC_REG_MASK(&temp_proc_desc) |= 1 << 31; | |
840 | temp_saved_regs.regs[31] = sp + offset; | |
c81a76b3 | 841 | offset -= MIPS_REGSIZE; |
b348b9fd MA |
842 | } |
843 | ||
844 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c81a76b3 | 845 | for (reg = 16; reg < sreg_count+16; reg++) |
b348b9fd MA |
846 | { |
847 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
848 | temp_saved_regs.regs[reg] = sp + offset; | |
c81a76b3 | 849 | offset -= MIPS_REGSIZE; |
b348b9fd MA |
850 | } |
851 | } | |
7d9e8fac MA |
852 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
853 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ | |
b348b9fd MA |
854 | } |
855 | } | |
856 | ||
857 | static void | |
858 | mips32_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp) | |
859 | CORE_ADDR start_pc, limit_pc; | |
860 | struct frame_info *next_frame; | |
861 | CORE_ADDR sp; | |
862 | { | |
863 | CORE_ADDR cur_pc; | |
864 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
865 | restart: | |
866 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; | |
867 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
868 | { | |
b348b9fd | 869 | unsigned long inst, high_word, low_word; |
c81a76b3 | 870 | int reg; |
b348b9fd MA |
871 | |
872 | /* Fetch the instruction. */ | |
c81a76b3 | 873 | inst = (unsigned long) mips_fetch_instruction (cur_pc); |
b348b9fd MA |
874 | |
875 | /* Save some code by pre-extracting some useful fields. */ | |
876 | high_word = (inst >> 16) & 0xffff; | |
877 | low_word = inst & 0xffff; | |
878 | reg = high_word & 0x1f; | |
879 | ||
880 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ | |
881 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
882 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
883 | { | |
884 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
885 | PROC_FRAME_OFFSET(&temp_proc_desc) += 0x10000 - low_word; | |
886 | else | |
887 | /* Exit loop if a positive stack adjustment is found, which | |
888 | usually means that the stack cleanup code in the function | |
889 | epilogue is reached. */ | |
890 | break; | |
891 | } | |
892 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
893 | { | |
894 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
895 | temp_saved_regs.regs[reg] = sp + low_word; | |
896 | } | |
897 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
898 | { | |
899 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
900 | but the register size used is only 32 bits. Make the address | |
901 | for the saved register point to the lower 32 bits. */ | |
902 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
903 | temp_saved_regs.regs[reg] = sp + low_word + 8 - MIPS_REGSIZE; | |
904 | } | |
905 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
906 | { | |
907 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
32dab603 | 908 | if ((long)low_word != PROC_FRAME_OFFSET(&temp_proc_desc)) |
b348b9fd MA |
909 | frame_addr = sp + low_word; |
910 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
911 | { | |
912 | unsigned alloca_adjust; | |
913 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
914 | frame_addr = read_next_frame_reg(next_frame, 30); | |
915 | alloca_adjust = (unsigned)(frame_addr - (sp + low_word)); | |
916 | if (alloca_adjust > 0) | |
917 | { | |
918 | /* FP > SP + frame_size. This may be because | |
919 | * of an alloca or somethings similar. | |
920 | * Fix sp to "pre-alloca" value, and try again. | |
921 | */ | |
922 | sp += alloca_adjust; | |
923 | goto restart; | |
bd5635a1 RP |
924 | } |
925 | } | |
926 | } | |
b348b9fd MA |
927 | /* move $30,$sp. With different versions of gas this will be either |
928 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
929 | Accept any one of these. */ | |
930 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
931 | { | |
932 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
933 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
934 | { | |
935 | unsigned alloca_adjust; | |
936 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
937 | frame_addr = read_next_frame_reg(next_frame, 30); | |
938 | alloca_adjust = (unsigned)(frame_addr - sp); | |
939 | if (alloca_adjust > 0) | |
940 | { | |
941 | /* FP > SP + frame_size. This may be because | |
942 | * of an alloca or somethings similar. | |
943 | * Fix sp to "pre-alloca" value, and try again. | |
944 | */ | |
945 | sp += alloca_adjust; | |
946 | goto restart; | |
97e091b2 MA |
947 | } |
948 | } | |
949 | } | |
b348b9fd MA |
950 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
951 | { | |
952 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
953 | temp_saved_regs.regs[reg] = frame_addr + low_word; | |
bd5635a1 RP |
954 | } |
955 | } | |
b348b9fd MA |
956 | } |
957 | ||
958 | static mips_extra_func_info_t | |
959 | heuristic_proc_desc(start_pc, limit_pc, next_frame) | |
960 | CORE_ADDR start_pc, limit_pc; | |
961 | struct frame_info *next_frame; | |
962 | { | |
963 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
964 | ||
965 | if (start_pc == 0) return NULL; | |
966 | memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); | |
967 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); | |
968 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; | |
969 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
970 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
971 | ||
972 | if (start_pc + 200 < limit_pc) | |
973 | limit_pc = start_pc + 200; | |
c1fc0935 | 974 | if (IS_MIPS16_ADDR (start_pc)) |
b348b9fd MA |
975 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); |
976 | else | |
977 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
978 | return &temp_proc_desc; | |
bd5635a1 RP |
979 | } |
980 | ||
0f552c5f | 981 | static mips_extra_func_info_t |
c1fc0935 | 982 | non_heuristic_proc_desc (pc, addrptr) |
9f9f94aa | 983 | CORE_ADDR pc; |
c1fc0935 | 984 | CORE_ADDR *addrptr; |
bd5635a1 | 985 | { |
c1fc0935 | 986 | CORE_ADDR startaddr; |
bd5635a1 | 987 | mips_extra_func_info_t proc_desc; |
0f552c5f | 988 | struct block *b = block_for_pc(pc); |
48be4c35 | 989 | struct symbol *sym; |
48be4c35 JK |
990 | |
991 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
c1fc0935 MA |
992 | if (addrptr) |
993 | *addrptr = startaddr; | |
97e091b2 | 994 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) |
48be4c35 JK |
995 | sym = NULL; |
996 | else | |
997 | { | |
998 | if (startaddr > BLOCK_START (b)) | |
999 | /* This is the "pathological" case referred to in a comment in | |
1000 | print_frame_info. It might be better to move this check into | |
1001 | symbol reading. */ | |
1002 | sym = NULL; | |
1003 | else | |
c1fc0935 | 1004 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); |
48be4c35 | 1005 | } |
0f552c5f | 1006 | |
e4dbd248 PS |
1007 | /* If we never found a PDR for this function in symbol reading, then |
1008 | examine prologues to find the information. */ | |
0f552c5f | 1009 | if (sym) |
bd5635a1 | 1010 | { |
c1fc0935 MA |
1011 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
1012 | if (PROC_FRAME_REG (proc_desc) == -1) | |
1013 | return NULL; | |
1014 | else | |
1015 | return proc_desc; | |
1016 | } | |
1017 | else | |
1018 | return NULL; | |
1019 | } | |
1020 | ||
1021 | ||
1022 | static mips_extra_func_info_t | |
1023 | find_proc_desc (pc, next_frame) | |
1024 | CORE_ADDR pc; | |
1025 | struct frame_info *next_frame; | |
1026 | { | |
1027 | mips_extra_func_info_t proc_desc; | |
1028 | CORE_ADDR startaddr; | |
1029 | ||
1030 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1031 | ||
1032 | if (proc_desc) | |
1033 | { | |
1034 | /* IF this is the topmost frame AND | |
1035 | * (this proc does not have debugging information OR | |
1036 | * the PC is in the procedure prologue) | |
1037 | * THEN create a "heuristic" proc_desc (by analyzing | |
1038 | * the actual code) to replace the "official" proc_desc. | |
1039 | */ | |
1040 | if (next_frame == NULL) | |
1041 | { | |
1042 | struct symtab_and_line val; | |
1043 | struct symbol *proc_symbol = | |
1044 | PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); | |
1045 | ||
1046 | if (proc_symbol) | |
1047 | { | |
1048 | val = find_pc_line (BLOCK_START | |
1049 | (SYMBOL_BLOCK_VALUE(proc_symbol)), | |
1050 | 0); | |
1051 | val.pc = val.end ? val.end : pc; | |
bd5635a1 | 1052 | } |
c1fc0935 MA |
1053 | if (!proc_symbol || pc < val.pc) |
1054 | { | |
1055 | mips_extra_func_info_t found_heuristic = | |
1056 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), | |
1057 | pc, next_frame); | |
1058 | if (found_heuristic) | |
1059 | proc_desc = found_heuristic; | |
bd5635a1 RP |
1060 | } |
1061 | } | |
1062 | } | |
1063 | else | |
1064 | { | |
0f552c5f JG |
1065 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
1066 | by procedure call dummys. However, the procedures being called ought | |
1067 | to have their own proc_descs, and even if they don't, | |
1068 | heuristic_proc_desc knows how to create them! */ | |
1069 | ||
bd5635a1 | 1070 | register struct linked_proc_info *link; |
9f9f94aa | 1071 | |
bd5635a1 | 1072 | for (link = linked_proc_desc_table; link; link = link->next) |
9f9f94aa SS |
1073 | if (PROC_LOW_ADDR(&link->info) <= pc |
1074 | && PROC_HIGH_ADDR(&link->info) > pc) | |
1075 | return &link->info; | |
23d35572 | 1076 | |
48be4c35 JK |
1077 | if (startaddr == 0) |
1078 | startaddr = heuristic_proc_start (pc); | |
1079 | ||
bd5635a1 | 1080 | proc_desc = |
48be4c35 | 1081 | heuristic_proc_desc (startaddr, pc, next_frame); |
bd5635a1 RP |
1082 | } |
1083 | return proc_desc; | |
1084 | } | |
1085 | ||
96431497 MA |
1086 | static CORE_ADDR |
1087 | get_frame_pointer(frame, proc_desc) | |
1088 | struct frame_info *frame; | |
1089 | mips_extra_func_info_t proc_desc; | |
1090 | { | |
1091 | return ADDR_BITS_REMOVE (read_next_frame_reg (frame, | |
1092 | PROC_FRAME_REG(proc_desc)) + PROC_FRAME_OFFSET(proc_desc)); | |
1093 | } | |
1094 | ||
bd5635a1 RP |
1095 | mips_extra_func_info_t cached_proc_desc; |
1096 | ||
9f9f94aa | 1097 | CORE_ADDR |
0f552c5f | 1098 | mips_frame_chain(frame) |
9f9f94aa | 1099 | struct frame_info *frame; |
bd5635a1 | 1100 | { |
f781fe93 MA |
1101 | mips_extra_func_info_t proc_desc; |
1102 | CORE_ADDR tmp; | |
1103 | CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); | |
1104 | ||
1105 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
1106 | return 0; | |
1107 | ||
1108 | /* Check if the PC is inside a call stub. If it is, fetch the | |
1109 | PC of the caller of that stub. */ | |
1110 | if ((tmp = mips_skip_stub (saved_pc)) != 0) | |
1111 | saved_pc = tmp; | |
1112 | ||
1113 | /* Look up the procedure descriptor for this PC. */ | |
1114 | proc_desc = find_proc_desc(saved_pc, frame); | |
1115 | if (!proc_desc) | |
1116 | return 0; | |
1117 | ||
1118 | cached_proc_desc = proc_desc; | |
1119 | ||
1120 | /* If no frame pointer and frame size is zero, we must be at end | |
1121 | of stack (or otherwise hosed). If we don't check frame size, | |
1122 | we loop forever if we see a zero size frame. */ | |
1123 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
1124 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
1125 | /* The previous frame from a sigtramp frame might be frameless | |
1126 | and have frame size zero. */ | |
1127 | && !frame->signal_handler_caller) | |
1128 | return 0; | |
1129 | else | |
1130 | return get_frame_pointer (frame, proc_desc); | |
bd5635a1 RP |
1131 | } |
1132 | ||
1133 | void | |
1134 | init_extra_frame_info(fci) | |
1135 | struct frame_info *fci; | |
1136 | { | |
96431497 MA |
1137 | int regnum; |
1138 | ||
bd5635a1 | 1139 | /* Use proc_desc calculated in frame_chain */ |
ee5fb959 JK |
1140 | mips_extra_func_info_t proc_desc = |
1141 | fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); | |
0f552c5f | 1142 | |
70126bf9 | 1143 | fci->saved_regs = NULL; |
bd5635a1 | 1144 | fci->proc_desc = |
ee5fb959 | 1145 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
bd5635a1 RP |
1146 | if (proc_desc) |
1147 | { | |
c2a0f1cb | 1148 | /* Fixup frame-pointer - only needed for top frame */ |
5efd597b PS |
1149 | /* This may not be quite right, if proc has a real frame register. |
1150 | Get the value of the frame relative sp, procedure might have been | |
1151 | interrupted by a signal at it's very start. */ | |
70126bf9 KH |
1152 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
1153 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
1154 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
c2a0f1cb | 1155 | else |
96431497 | 1156 | fci->frame = get_frame_pointer (fci->next, proc_desc); |
bd5635a1 | 1157 | |
48be4c35 | 1158 | if (proc_desc == &temp_proc_desc) |
ee5fb959 | 1159 | { |
09af5868 PS |
1160 | char *name; |
1161 | ||
1162 | /* Do not set the saved registers for a sigtramp frame, | |
1163 | mips_find_saved_registers will do that for us. | |
1164 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
1165 | find_pc_partial_function (fci->pc, &name, | |
1166 | (CORE_ADDR *)NULL,(CORE_ADDR *)NULL); | |
1167 | if (!IN_SIGTRAMP (fci->pc, name)) | |
1168 | { | |
1169 | fci->saved_regs = (struct frame_saved_regs*) | |
1170 | obstack_alloc (&frame_cache_obstack, | |
1171 | sizeof (struct frame_saved_regs)); | |
1172 | *fci->saved_regs = temp_saved_regs; | |
1173 | fci->saved_regs->regs[PC_REGNUM] | |
1174 | = fci->saved_regs->regs[RA_REGNUM]; | |
1175 | } | |
ee5fb959 | 1176 | } |
bd5635a1 RP |
1177 | |
1178 | /* hack: if argument regs are saved, guess these contain args */ | |
96431497 MA |
1179 | fci->num_args = -1; /* assume we can't tell how many args for now */ |
1180 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) | |
1181 | { | |
1182 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) | |
1183 | { | |
1184 | fci->num_args = regnum - A0_REGNUM + 1; | |
1185 | break; | |
1186 | } | |
1187 | } | |
bd5635a1 | 1188 | } |
bd5635a1 RP |
1189 | } |
1190 | ||
a70dc898 RP |
1191 | /* MIPS stack frames are almost impenetrable. When execution stops, |
1192 | we basically have to look at symbol information for the function | |
1193 | that we stopped in, which tells us *which* register (if any) is | |
1194 | the base of the frame pointer, and what offset from that register | |
1195 | the frame itself is at. | |
1196 | ||
1197 | This presents a problem when trying to examine a stack in memory | |
1198 | (that isn't executing at the moment), using the "frame" command. We | |
1199 | don't have a PC, nor do we have any registers except SP. | |
1200 | ||
1201 | This routine takes two arguments, SP and PC, and tries to make the | |
1202 | cached frames look as if these two arguments defined a frame on the | |
1203 | cache. This allows the rest of info frame to extract the important | |
1204 | arguments without difficulty. */ | |
1205 | ||
9f9f94aa | 1206 | struct frame_info * |
c2a0f1cb ILT |
1207 | setup_arbitrary_frame (argc, argv) |
1208 | int argc; | |
9f9f94aa | 1209 | CORE_ADDR *argv; |
a70dc898 | 1210 | { |
c2a0f1cb ILT |
1211 | if (argc != 2) |
1212 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
1213 | ||
1214 | return create_new_frame (argv[0], argv[1]); | |
a70dc898 RP |
1215 | } |
1216 | ||
0f552c5f JG |
1217 | CORE_ADDR |
1218 | mips_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
97e091b2 MA |
1219 | int nargs; |
1220 | value_ptr *args; | |
1221 | CORE_ADDR sp; | |
1222 | int struct_return; | |
1223 | CORE_ADDR struct_addr; | |
bd5635a1 | 1224 | { |
97e091b2 MA |
1225 | int argreg; |
1226 | int float_argreg; | |
1227 | int argnum; | |
1228 | int len = 0; | |
781a59b2 | 1229 | int stack_offset = 0; |
97e091b2 MA |
1230 | |
1231 | /* Macros to round N up or down to the next A boundary; A must be | |
1232 | a power of two. */ | |
1233 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
1234 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
28444bf3 DP |
1235 | |
1236 | /* First ensure that the stack and structure return address (if any) | |
97e091b2 MA |
1237 | are properly aligned. The stack has to be 64-bit aligned even |
1238 | on 32-bit machines, because doubles must be 64-bit aligned. */ | |
1239 | sp = ROUND_DOWN (sp, 8); | |
1240 | struct_addr = ROUND_DOWN (struct_addr, MIPS_REGSIZE); | |
28444bf3 | 1241 | |
97e091b2 MA |
1242 | /* Now make space on the stack for the args. We allocate more |
1243 | than necessary for EABI, because the first few arguments are | |
1244 | passed in registers, but that's OK. */ | |
1245 | for (argnum = 0; argnum < nargs; argnum++) | |
1246 | len += ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args[argnum])), MIPS_REGSIZE); | |
61d2d19a | 1247 | sp -= ROUND_UP (len, 8); |
97e091b2 MA |
1248 | |
1249 | /* Initialize the integer and float register pointers. */ | |
1250 | argreg = A0_REGNUM; | |
1251 | float_argreg = FPA0_REGNUM; | |
1252 | ||
1253 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
5efd597b | 1254 | if (struct_return) |
97e091b2 MA |
1255 | write_register (argreg++, struct_addr); |
1256 | ||
97e091b2 MA |
1257 | /* Now load as many as possible of the first arguments into |
1258 | registers, and push the rest onto the stack. Loop thru args | |
1259 | from first to last. */ | |
1260 | for (argnum = 0; argnum < nargs; argnum++) | |
5efd597b | 1261 | { |
97e091b2 MA |
1262 | char *val; |
1263 | char valbuf[REGISTER_RAW_SIZE(A0_REGNUM)]; | |
1264 | value_ptr arg = args[argnum]; | |
1265 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
1266 | int len = TYPE_LENGTH (arg_type); | |
1267 | enum type_code typecode = TYPE_CODE (arg_type); | |
1268 | ||
61d2d19a PS |
1269 | /* The EABI passes structures that do not fit in a register by |
1270 | reference. In all other cases, pass the structure by value. */ | |
781a59b2 MS |
1271 | if (MIPS_EABI && len > MIPS_REGSIZE && |
1272 | (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
97e091b2 MA |
1273 | { |
1274 | store_address (valbuf, MIPS_REGSIZE, VALUE_ADDRESS (arg)); | |
08d8f995 | 1275 | typecode = TYPE_CODE_PTR; |
97e091b2 MA |
1276 | len = MIPS_REGSIZE; |
1277 | val = valbuf; | |
1278 | } | |
1279 | else | |
1280 | val = (char *)VALUE_CONTENTS (arg); | |
1281 | ||
1282 | /* 32-bit ABIs always start floating point arguments in an | |
1283 | even-numbered floating point register. */ | |
1284 | if (!GDB_TARGET_IS_MIPS64 && typecode == TYPE_CODE_FLT | |
1285 | && (float_argreg & 1)) | |
1286 | float_argreg++; | |
1287 | ||
1288 | /* Floating point arguments passed in registers have to be | |
1289 | treated specially. On 32-bit architectures, doubles | |
1290 | are passed in register pairs; the even register gets | |
c81a76b3 MA |
1291 | the low word, and the odd register gets the high word. |
1292 | On non-EABI processors, the first two floating point arguments are | |
1293 | also copied to general registers, because MIPS16 functions | |
1294 | don't use float registers for arguments. This duplication of | |
1295 | arguments in general registers can't hurt non-MIPS16 functions | |
1296 | because those registers are normally skipped. */ | |
97e091b2 MA |
1297 | if (typecode == TYPE_CODE_FLT |
1298 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM | |
1299 | && mips_fpu != MIPS_FPU_NONE) | |
1300 | { | |
1301 | if (!GDB_TARGET_IS_MIPS64 && len == 8) | |
1302 | { | |
1303 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; | |
1304 | unsigned long regval; | |
1305 | ||
c81a76b3 | 1306 | /* Write the low word of the double to the even register(s). */ |
97e091b2 | 1307 | regval = extract_unsigned_integer (val+low_offset, 4); |
c81a76b3 MA |
1308 | write_register (float_argreg++, regval); |
1309 | if (!MIPS_EABI) | |
1310 | write_register (argreg+1, regval); | |
1311 | ||
1312 | /* Write the high word of the double to the odd register(s). */ | |
97e091b2 | 1313 | regval = extract_unsigned_integer (val+4-low_offset, 4); |
c81a76b3 MA |
1314 | write_register (float_argreg++, regval); |
1315 | if (!MIPS_EABI) | |
1316 | { | |
1317 | write_register (argreg, regval); | |
1318 | argreg += 2; | |
1319 | } | |
97e091b2 MA |
1320 | |
1321 | } | |
1322 | else | |
1323 | { | |
c81a76b3 MA |
1324 | /* This is a floating point value that fits entirely |
1325 | in a single register. */ | |
97e091b2 MA |
1326 | CORE_ADDR regval = extract_address (val, len); |
1327 | write_register (float_argreg++, regval); | |
c81a76b3 MA |
1328 | if (!MIPS_EABI) |
1329 | { | |
1330 | write_register (argreg, regval); | |
1331 | argreg += GDB_TARGET_IS_MIPS64 ? 1 : 2; | |
1332 | } | |
97e091b2 | 1333 | } |
97e091b2 MA |
1334 | } |
1335 | else | |
1336 | { | |
1337 | /* Copy the argument to general registers or the stack in | |
1338 | register-sized pieces. Large arguments are split between | |
1339 | registers and stack. */ | |
781a59b2 MS |
1340 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE |
1341 | are treated specially: Irix cc passes them in registers | |
1342 | where gcc sometimes puts them on the stack. For maximum | |
1343 | compatibility, we will put them in both places. */ | |
1344 | ||
1345 | int odd_sized_struct = ((len > MIPS_REGSIZE) && | |
1346 | (len % MIPS_REGSIZE != 0)); | |
97e091b2 MA |
1347 | while (len > 0) |
1348 | { | |
1349 | int partial_len = len < MIPS_REGSIZE ? len : MIPS_REGSIZE; | |
61d2d19a | 1350 | |
781a59b2 MS |
1351 | if (argreg > MIPS_LAST_ARG_REGNUM || odd_sized_struct) |
1352 | { | |
1353 | /* Write this portion of the argument to the stack. */ | |
1354 | int longword_offset; | |
1355 | ||
1356 | longword_offset = 0; | |
1357 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1358 | if (MIPS_REGSIZE == 8 && | |
1359 | (typecode == TYPE_CODE_INT || | |
1360 | typecode == TYPE_CODE_PTR || | |
1361 | typecode == TYPE_CODE_FLT) && len <= 4) | |
1362 | longword_offset = 4; | |
1363 | else if ((typecode == TYPE_CODE_STRUCT || | |
1364 | typecode == TYPE_CODE_UNION) && | |
1365 | TYPE_LENGTH (arg_type) < MIPS_REGSIZE) | |
1366 | longword_offset = MIPS_REGSIZE - len; | |
1367 | ||
1368 | write_memory (sp + stack_offset + longword_offset, | |
1369 | val, partial_len); | |
1370 | } | |
1371 | ||
1372 | /* Note!!! This is NOT an else clause. | |
1373 | Odd sized structs may go thru BOTH paths. */ | |
97e091b2 MA |
1374 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
1375 | { | |
61d2d19a PS |
1376 | CORE_ADDR regval = extract_address (val, partial_len); |
1377 | ||
c430260c MS |
1378 | /* A non-floating-point argument being passed in a |
1379 | general register. If a struct or union, and if | |
1380 | small enough for a single register, we have to | |
1381 | adjust the alignment. | |
158bda58 | 1382 | |
c430260c MS |
1383 | It does not seem to be necessary to do the |
1384 | same for integral types. | |
158bda58 | 1385 | |
c430260c | 1386 | Also don't do this adjustment on EABI targets. */ |
158bda58 MS |
1387 | |
1388 | if (!MIPS_EABI && | |
1389 | TYPE_LENGTH (arg_type) < MIPS_REGSIZE && | |
c430260c | 1390 | (typecode == TYPE_CODE_STRUCT || |
158bda58 MS |
1391 | typecode == TYPE_CODE_UNION)) |
1392 | regval <<= ((MIPS_REGSIZE - partial_len) * | |
1393 | TARGET_CHAR_BIT); | |
1394 | ||
97e091b2 MA |
1395 | write_register (argreg, regval); |
1396 | argreg++; | |
1397 | ||
1398 | /* If this is the old ABI, prevent subsequent floating | |
1399 | point arguments from being passed in floating point | |
1400 | registers. */ | |
1401 | if (!MIPS_EABI) | |
1402 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
1403 | } | |
97e091b2 MA |
1404 | |
1405 | len -= partial_len; | |
1406 | val += partial_len; | |
781a59b2 MS |
1407 | |
1408 | /* The offset onto the stack at which we will start | |
1409 | copying parameters (after the registers are used up) | |
1410 | begins at (4 * MIPS_REGSIZE) in the old ABI. This | |
1411 | leaves room for the "home" area for register parameters. | |
1412 | ||
1413 | In the new EABI, the 8 register parameters do not | |
1414 | have "home" stack space reserved for them, so the | |
1415 | stack offset does not get incremented until after | |
1416 | we have used up the 8 parameter registers. */ | |
1417 | if (!(MIPS_EABI && argnum < 8)) | |
1418 | stack_offset += ROUND_UP (partial_len, MIPS_REGSIZE); | |
97e091b2 MA |
1419 | } |
1420 | } | |
5efd597b | 1421 | } |
97e091b2 MA |
1422 | |
1423 | /* Set the return address register to point to the entry | |
1424 | point of the program, where a breakpoint lies in wait. */ | |
1425 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS()); | |
1426 | ||
1427 | /* Return adjusted stack pointer. */ | |
bd5635a1 RP |
1428 | return sp; |
1429 | } | |
1430 | ||
c81a76b3 | 1431 | static void |
28444bf3 DP |
1432 | mips_push_register(CORE_ADDR *sp, int regno) |
1433 | { | |
1434 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
1435 | int regsize = REGISTER_RAW_SIZE (regno); | |
1436 | ||
1437 | *sp -= regsize; | |
1438 | read_register_gen (regno, buffer); | |
1439 | write_memory (*sp, buffer, regsize); | |
1440 | } | |
1441 | ||
1442 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
e03c0cc6 | 1443 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
bd5635a1 RP |
1444 | |
1445 | void | |
1446 | mips_push_dummy_frame() | |
1447 | { | |
1448 | int ireg; | |
1449 | struct linked_proc_info *link = (struct linked_proc_info*) | |
1450 | xmalloc(sizeof(struct linked_proc_info)); | |
1451 | mips_extra_func_info_t proc_desc = &link->info; | |
96431497 | 1452 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM)); |
28444bf3 | 1453 | CORE_ADDR old_sp = sp; |
bd5635a1 RP |
1454 | link->next = linked_proc_desc_table; |
1455 | linked_proc_desc_table = link; | |
28444bf3 DP |
1456 | |
1457 | /* FIXME! are these correct ? */ | |
bd5635a1 | 1458 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
28444bf3 | 1459 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
bd5635a1 | 1460 | #define FLOAT_REG_SAVE_MASK MASK(0,19) |
e4dbd248 PS |
1461 | #define FLOAT_SINGLE_REG_SAVE_MASK \ |
1462 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
bd5635a1 RP |
1463 | /* |
1464 | * The registers we must save are all those not preserved across | |
1465 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
28444bf3 DP |
1466 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI |
1467 | * and FP Control/Status registers. | |
1468 | * | |
bd5635a1 RP |
1469 | * |
1470 | * Dummy frame layout: | |
1471 | * (high memory) | |
1472 | * Saved PC | |
1473 | * Saved MMHI, MMLO, FPC_CSR | |
1474 | * Saved R31 | |
1475 | * Saved R28 | |
1476 | * ... | |
1477 | * Saved R1 | |
1478 | * Saved D18 (i.e. F19, F18) | |
1479 | * ... | |
1480 | * Saved D0 (i.e. F1, F0) | |
f9f8c14b | 1481 | * Argument build area and stack arguments written via mips_push_arguments |
bd5635a1 RP |
1482 | * (low memory) |
1483 | */ | |
28444bf3 DP |
1484 | |
1485 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
28444bf3 DP |
1486 | PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; |
1487 | PROC_FRAME_OFFSET(proc_desc) = 0; | |
1488 | mips_push_register (&sp, PC_REGNUM); | |
1489 | mips_push_register (&sp, HI_REGNUM); | |
1490 | mips_push_register (&sp, LO_REGNUM); | |
1491 | mips_push_register (&sp, mips_fpu == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
1492 | ||
1493 | /* Save general CPU registers */ | |
bd5635a1 | 1494 | PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; |
28444bf3 | 1495 | PROC_REG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved R31) from FP */ |
bd5635a1 RP |
1496 | for (ireg = 32; --ireg >= 0; ) |
1497 | if (PROC_REG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1498 | mips_push_register (&sp, ireg); |
3fed1c4a | 1499 | |
28444bf3 DP |
1500 | /* Save floating point registers starting with high order word */ |
1501 | PROC_FREG_MASK(proc_desc) = | |
1502 | mips_fpu == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK | |
1503 | : mips_fpu == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
1504 | PROC_FREG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved D18) from FP */ | |
bd5635a1 RP |
1505 | for (ireg = 32; --ireg >= 0; ) |
1506 | if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1507 | mips_push_register (&sp, ireg + FP0_REGNUM); |
3fed1c4a | 1508 | |
f9f8c14b MA |
1509 | /* Update the frame pointer for the call dummy and the stack pointer. |
1510 | Set the procedure's starting and ending addresses to point to the | |
1511 | call dummy address at the entry point. */ | |
1512 | write_register (PUSH_FP_REGNUM, old_sp); | |
bd5635a1 | 1513 | write_register (SP_REGNUM, sp); |
97e091b2 MA |
1514 | PROC_LOW_ADDR(proc_desc) = CALL_DUMMY_ADDRESS(); |
1515 | PROC_HIGH_ADDR(proc_desc) = CALL_DUMMY_ADDRESS() + 4; | |
bd5635a1 RP |
1516 | SET_PROC_DESC_IS_DUMMY(proc_desc); |
1517 | PROC_PC_REG(proc_desc) = RA_REGNUM; | |
1518 | } | |
1519 | ||
1520 | void | |
1521 | mips_pop_frame() | |
dac4929a SG |
1522 | { |
1523 | register int regnum; | |
9f9f94aa SS |
1524 | struct frame_info *frame = get_current_frame (); |
1525 | CORE_ADDR new_sp = FRAME_FP (frame); | |
dac4929a | 1526 | |
a70dc898 | 1527 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
dac4929a SG |
1528 | |
1529 | write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); | |
70126bf9 KH |
1530 | if (frame->saved_regs == NULL) |
1531 | mips_find_saved_regs (frame); | |
61d2d19a | 1532 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
dac4929a | 1533 | { |
61d2d19a PS |
1534 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1535 | && frame->saved_regs->regs[regnum]) | |
1536 | write_register (regnum, | |
1537 | read_memory_integer (frame->saved_regs->regs[regnum], | |
1538 | MIPS_REGSIZE)); | |
dac4929a SG |
1539 | } |
1540 | write_register (SP_REGNUM, new_sp); | |
1541 | flush_cached_frames (); | |
dac4929a | 1542 | |
199b2450 | 1543 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
bd5635a1 | 1544 | { |
dac4929a SG |
1545 | struct linked_proc_info *pi_ptr, *prev_ptr; |
1546 | ||
1547 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
1548 | pi_ptr != NULL; | |
1549 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
1550 | { | |
1551 | if (&pi_ptr->info == proc_desc) | |
1552 | break; | |
1553 | } | |
1554 | ||
1555 | if (pi_ptr == NULL) | |
1556 | error ("Can't locate dummy extra frame info\n"); | |
1557 | ||
1558 | if (prev_ptr != NULL) | |
1559 | prev_ptr->next = pi_ptr->next; | |
1560 | else | |
1561 | linked_proc_desc_table = pi_ptr->next; | |
1562 | ||
1563 | free (pi_ptr); | |
1564 | ||
28444bf3 DP |
1565 | write_register (HI_REGNUM, |
1566 | read_memory_integer (new_sp - 2*MIPS_REGSIZE, MIPS_REGSIZE)); | |
1567 | write_register (LO_REGNUM, | |
1568 | read_memory_integer (new_sp - 3*MIPS_REGSIZE, MIPS_REGSIZE)); | |
e4dbd248 | 1569 | if (mips_fpu != MIPS_FPU_NONE) |
28444bf3 DP |
1570 | write_register (FCRCS_REGNUM, |
1571 | read_memory_integer (new_sp - 4*MIPS_REGSIZE, MIPS_REGSIZE)); | |
bd5635a1 | 1572 | } |
bd5635a1 RP |
1573 | } |
1574 | ||
0f552c5f | 1575 | static void |
a70dc898 | 1576 | mips_print_register (regnum, all) |
bd5635a1 RP |
1577 | int regnum, all; |
1578 | { | |
e4dbd248 | 1579 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
bd5635a1 | 1580 | |
48be4c35 JK |
1581 | /* Get the data in raw format. */ |
1582 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
1583 | { | |
1584 | printf_filtered ("%s: [Invalid]", reg_names[regnum]); | |
1585 | return; | |
1586 | } | |
1587 | ||
781a59b2 | 1588 | /* If an even floating point register, also print as double. */ |
28444bf3 | 1589 | if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+MIPS_NUMREGS |
e4dbd248 PS |
1590 | && !((regnum-FP0_REGNUM) & 1)) |
1591 | { | |
f781fe93 | 1592 | char dbuffer[2 * MAX_REGISTER_RAW_SIZE]; |
48be4c35 | 1593 | |
f781fe93 MA |
1594 | read_relative_register_raw_bytes (regnum, dbuffer); |
1595 | read_relative_register_raw_bytes (regnum+1, dbuffer+MIPS_REGSIZE); | |
1596 | REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer); | |
c81a76b3 | 1597 | |
e4dbd248 PS |
1598 | printf_filtered ("(d%d: ", regnum-FP0_REGNUM); |
1599 | val_print (builtin_type_double, dbuffer, 0, | |
1600 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
1601 | printf_filtered ("); "); | |
1602 | } | |
199b2450 | 1603 | fputs_filtered (reg_names[regnum], gdb_stdout); |
48be4c35 JK |
1604 | |
1605 | /* The problem with printing numeric register names (r26, etc.) is that | |
1606 | the user can't use them on input. Probably the best solution is to | |
1607 | fix it so that either the numeric or the funky (a2, etc.) names | |
1608 | are accepted on input. */ | |
28444bf3 | 1609 | if (regnum < MIPS_NUMREGS) |
48be4c35 JK |
1610 | printf_filtered ("(r%d): ", regnum); |
1611 | else | |
1612 | printf_filtered (": "); | |
bd5635a1 | 1613 | |
48be4c35 | 1614 | /* If virtual format is floating, print it that way. */ |
ac57e5ad | 1615 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
48be4c35 | 1616 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, |
199b2450 | 1617 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
48be4c35 JK |
1618 | /* Else print as integer in hex. */ |
1619 | else | |
ac57e5ad SS |
1620 | print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), |
1621 | 'x', 0, gdb_stdout); | |
bd5635a1 RP |
1622 | } |
1623 | ||
d8b3b00e | 1624 | /* Replacement for generic do_registers_info. */ |
9f9f94aa | 1625 | |
0f552c5f | 1626 | void |
361bf6ee | 1627 | mips_do_registers_info (regnum, fpregs) |
bd5635a1 | 1628 | int regnum; |
361bf6ee | 1629 | int fpregs; |
bd5635a1 | 1630 | { |
9f9f94aa SS |
1631 | if (regnum != -1) |
1632 | { | |
1633 | if (*(reg_names[regnum]) == '\0') | |
1634 | error ("Not a valid register for the current processor type"); | |
1635 | ||
bd5635a1 RP |
1636 | mips_print_register (regnum, 0); |
1637 | printf_filtered ("\n"); | |
9f9f94aa SS |
1638 | } |
1639 | else | |
1640 | { | |
09af5868 | 1641 | int did_newline = 0; |
9f9f94aa SS |
1642 | |
1643 | for (regnum = 0; regnum < NUM_REGS; ) | |
1644 | { | |
1645 | if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM) | |
1646 | || *(reg_names[regnum]) == '\0') | |
1647 | { | |
1648 | regnum++; | |
1649 | continue; | |
1650 | } | |
bd5635a1 RP |
1651 | mips_print_register (regnum, 1); |
1652 | regnum++; | |
9f9f94aa SS |
1653 | printf_filtered ("; "); |
1654 | did_newline = 0; | |
1655 | if ((regnum & 3) == 0) | |
1656 | { | |
1657 | printf_filtered ("\n"); | |
1658 | did_newline = 1; | |
1659 | } | |
1660 | } | |
1661 | if (!did_newline) | |
1662 | printf_filtered ("\n"); | |
1663 | } | |
bd5635a1 | 1664 | } |
9f9f94aa | 1665 | |
bd5635a1 RP |
1666 | /* Return number of args passed to a frame. described by FIP. |
1667 | Can return -1, meaning no way to tell. */ | |
1668 | ||
0f552c5f | 1669 | int |
9f9f94aa SS |
1670 | mips_frame_num_args (frame) |
1671 | struct frame_info *frame; | |
bd5635a1 | 1672 | { |
9f9f94aa SS |
1673 | #if 0 /* FIXME Use or lose this! */ |
1674 | struct chain_info_t *p; | |
bd5635a1 | 1675 | |
9f9f94aa SS |
1676 | p = mips_find_cached_frame (FRAME_FP (frame)); |
1677 | if (p->valid) | |
1678 | return p->the_info.numargs; | |
bd5635a1 | 1679 | #endif |
9f9f94aa | 1680 | return -1; |
bd5635a1 | 1681 | } |
96431497 | 1682 | |
427fec5d | 1683 | /* Is this a branch with a delay slot? */ |
9f9f94aa | 1684 | |
b5aff268 JK |
1685 | static int is_delayed PARAMS ((unsigned long)); |
1686 | ||
ee5fb959 JK |
1687 | static int |
1688 | is_delayed (insn) | |
1689 | unsigned long insn; | |
1690 | { | |
1691 | int i; | |
1692 | for (i = 0; i < NUMOPCODES; ++i) | |
1693 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
1694 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
1695 | break; | |
427fec5d JK |
1696 | return (i < NUMOPCODES |
1697 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
1698 | | INSN_COND_BRANCH_DELAY | |
1699 | | INSN_COND_BRANCH_LIKELY))); | |
ee5fb959 | 1700 | } |
b5aff268 JK |
1701 | |
1702 | int | |
1703 | mips_step_skips_delay (pc) | |
1704 | CORE_ADDR pc; | |
1705 | { | |
96431497 | 1706 | char buf[MIPS_INSTLEN]; |
b5aff268 | 1707 | |
f9f8c14b | 1708 | /* There is no branch delay slot on MIPS16. */ |
c1fc0935 | 1709 | if (IS_MIPS16_ADDR (pc)) |
f9f8c14b MA |
1710 | return 0; |
1711 | ||
96431497 | 1712 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) |
b5aff268 JK |
1713 | /* If error reading memory, guess that it is not a delayed branch. */ |
1714 | return 0; | |
96431497 | 1715 | return is_delayed ((unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN)); |
b5aff268 | 1716 | } |
ee5fb959 | 1717 | |
bd5635a1 | 1718 | |
20fa0902 MA |
1719 | /* Skip the PC past function prologue instructions (32-bit version). |
1720 | This is a helper function for mips_skip_prologue. */ | |
1721 | ||
1722 | static CORE_ADDR | |
1723 | mips32_skip_prologue (pc, lenient) | |
1724 | CORE_ADDR pc; /* starting PC to search from */ | |
ee5fb959 | 1725 | int lenient; |
bd5635a1 | 1726 | { |
28444bf3 | 1727 | t_inst inst; |
20fa0902 | 1728 | CORE_ADDR end_pc; |
0b0d6c3f | 1729 | int seen_sp_adjust = 0; |
ac57e5ad | 1730 | int load_immediate_bytes = 0; |
bd5635a1 | 1731 | |
e157305c PS |
1732 | /* Skip the typical prologue instructions. These are the stack adjustment |
1733 | instruction and the instructions that save registers on the stack | |
1734 | or in the gcc frame. */ | |
20fa0902 | 1735 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) |
ee5fb959 | 1736 | { |
b348b9fd | 1737 | unsigned long high_word; |
ee5fb959 | 1738 | |
c81a76b3 | 1739 | inst = mips_fetch_instruction (pc); |
b348b9fd | 1740 | high_word = (inst >> 16) & 0xffff; |
ee5fb959 | 1741 | |
002a422b | 1742 | #if 0 |
ee5fb959 JK |
1743 | if (lenient && is_delayed (inst)) |
1744 | continue; | |
002a422b | 1745 | #endif |
ee5fb959 | 1746 | |
b348b9fd MA |
1747 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
1748 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
0b0d6c3f | 1749 | seen_sp_adjust = 1; |
ac57e5ad SS |
1750 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
1751 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
1752 | seen_sp_adjust = 1; | |
97e091b2 MA |
1753 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ |
1754 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
1755 | && (inst & 0x001F0000)) /* reg != $zero */ | |
1756 | continue; | |
1757 | ||
e157305c PS |
1758 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ |
1759 | continue; | |
1760 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
1761 | /* sx reg,n($s8) */ | |
1762 | continue; /* reg != $zero */ | |
1d9489c1 JK |
1763 | |
1764 | /* move $s8,$sp. With different versions of gas this will be either | |
20fa0902 MA |
1765 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. |
1766 | Accept any one of these. */ | |
1767 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
0b0d6c3f | 1768 | continue; |
1d9489c1 | 1769 | |
1b71de8e PS |
1770 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
1771 | continue; | |
b348b9fd | 1772 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
e03c0cc6 | 1773 | continue; |
b348b9fd | 1774 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ |
e03c0cc6 ILT |
1775 | continue; |
1776 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1777 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
1778 | continue; | |
ac57e5ad SS |
1779 | /* The following instructions load $at or $t0 with an immediate |
1780 | value in preparation for a stack adjustment via | |
1781 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
1782 | a local variable, so we accept them only before a stack adjustment | |
1783 | instruction was seen. */ | |
1784 | else if (!seen_sp_adjust) | |
1785 | { | |
b348b9fd MA |
1786 | if (high_word == 0x3c01 || /* lui $at,n */ |
1787 | high_word == 0x3c08) /* lui $t0,n */ | |
ac57e5ad | 1788 | { |
28444bf3 | 1789 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1790 | continue; |
1791 | } | |
b348b9fd MA |
1792 | else if (high_word == 0x3421 || /* ori $at,$at,n */ |
1793 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
1794 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
1795 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
ac57e5ad | 1796 | { |
28444bf3 | 1797 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1798 | continue; |
1799 | } | |
1800 | else | |
1801 | break; | |
1802 | } | |
0b0d6c3f | 1803 | else |
ac57e5ad | 1804 | break; |
d747e0af | 1805 | } |
e157305c | 1806 | |
ac57e5ad SS |
1807 | /* In a frameless function, we might have incorrectly |
1808 | skipped some load immediate instructions. Undo the skipping | |
1809 | if the load immediate was not followed by a stack adjustment. */ | |
1810 | if (load_immediate_bytes && !seen_sp_adjust) | |
20fa0902 MA |
1811 | pc -= load_immediate_bytes; |
1812 | return pc; | |
1813 | } | |
1814 | ||
1815 | /* Skip the PC past function prologue instructions (16-bit version). | |
1816 | This is a helper function for mips_skip_prologue. */ | |
1817 | ||
1818 | static CORE_ADDR | |
1819 | mips16_skip_prologue (pc, lenient) | |
1820 | CORE_ADDR pc; /* starting PC to search from */ | |
1821 | int lenient; | |
1822 | { | |
1823 | CORE_ADDR end_pc; | |
c81a76b3 MA |
1824 | int extend_bytes = 0; |
1825 | int prev_extend_bytes; | |
20fa0902 MA |
1826 | |
1827 | /* Table of instructions likely to be found in a function prologue. */ | |
1828 | static struct | |
1829 | { | |
1830 | unsigned short inst; | |
1831 | unsigned short mask; | |
1832 | } table[] = | |
1833 | { | |
1834 | { 0x6300, 0xff00 }, /* addiu $sp,offset */ | |
1835 | { 0xfb00, 0xff00 }, /* daddiu $sp,offset */ | |
1836 | { 0xd000, 0xf800 }, /* sw reg,n($sp) */ | |
1837 | { 0xf900, 0xff00 }, /* sd reg,n($sp) */ | |
1838 | { 0x6200, 0xff00 }, /* sw $ra,n($sp) */ | |
1839 | { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */ | |
1840 | { 0x673d, 0xffff }, /* move $s1,sp */ | |
1841 | { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */ | |
1842 | { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */ | |
1843 | { 0xe809, 0xf81f }, /* entry pseudo-op */ | |
32dab603 | 1844 | { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */ |
20fa0902 MA |
1845 | { 0, 0 } /* end of table marker */ |
1846 | }; | |
1847 | ||
1848 | /* Skip the typical prologue instructions. These are the stack adjustment | |
1849 | instruction and the instructions that save registers on the stack | |
1850 | or in the gcc frame. */ | |
1851 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
1852 | { | |
20fa0902 | 1853 | unsigned short inst; |
20fa0902 MA |
1854 | int i; |
1855 | ||
c81a76b3 | 1856 | inst = mips_fetch_instruction (pc); |
20fa0902 MA |
1857 | |
1858 | /* Normally we ignore an extend instruction. However, if it is | |
1859 | not followed by a valid prologue instruction, we must adjust | |
1860 | the pc back over the extend so that it won't be considered | |
1861 | part of the prologue. */ | |
1862 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1863 | { | |
1864 | extend_bytes = MIPS16_INSTLEN; | |
1865 | continue; | |
1866 | } | |
1867 | prev_extend_bytes = extend_bytes; | |
1868 | extend_bytes = 0; | |
1869 | ||
1870 | /* Check for other valid prologue instructions besides extend. */ | |
1871 | for (i = 0; table[i].mask != 0; i++) | |
1872 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
1873 | break; | |
1874 | if (table[i].mask != 0) /* it was in table? */ | |
32dab603 | 1875 | continue; /* ignore it */ |
20fa0902 MA |
1876 | else /* non-prologue */ |
1877 | { | |
1878 | /* Return the current pc, adjusted backwards by 2 if | |
1879 | the previous instruction was an extend. */ | |
1880 | return pc - prev_extend_bytes; | |
1881 | } | |
1882 | } | |
32dab603 | 1883 | return pc; |
20fa0902 MA |
1884 | } |
1885 | ||
1886 | /* To skip prologues, I use this predicate. Returns either PC itself | |
1887 | if the code at PC does not look like a function prologue; otherwise | |
1888 | returns an address that (if we're lucky) follows the prologue. If | |
1889 | LENIENT, then we must skip everything which is involved in setting | |
1890 | up the frame (it's OK to skip more, just so long as we don't skip | |
1891 | anything which might clobber the registers which are being saved. | |
1892 | We must skip more in the case where part of the prologue is in the | |
1893 | delay slot of a non-prologue instruction). */ | |
1894 | ||
1895 | CORE_ADDR | |
1896 | mips_skip_prologue (pc, lenient) | |
1897 | CORE_ADDR pc; | |
1898 | int lenient; | |
1899 | { | |
1900 | /* See if we can determine the end of the prologue via the symbol table. | |
1901 | If so, then return either PC, or the PC after the prologue, whichever | |
1902 | is greater. */ | |
1903 | ||
1904 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
1905 | ||
1906 | if (post_prologue_pc != 0) | |
1907 | return max (pc, post_prologue_pc); | |
1908 | ||
1909 | /* Can't determine prologue from the symbol table, need to examine | |
1910 | instructions. */ | |
1911 | ||
c1fc0935 | 1912 | if (IS_MIPS16_ADDR (pc)) |
20fa0902 MA |
1913 | return mips16_skip_prologue (pc, lenient); |
1914 | else | |
1915 | return mips32_skip_prologue (pc, lenient); | |
bd5635a1 | 1916 | } |
c2a0f1cb | 1917 | |
002a422b | 1918 | #if 0 |
20fa0902 | 1919 | /* The lenient prologue stuff should be superseded by the code in |
002a422b JK |
1920 | init_extra_frame_info which looks to see whether the stores mentioned |
1921 | in the proc_desc have actually taken place. */ | |
1922 | ||
ee5fb959 JK |
1923 | /* Is address PC in the prologue (loosely defined) for function at |
1924 | STARTADDR? */ | |
1925 | ||
1926 | static int | |
1927 | mips_in_lenient_prologue (startaddr, pc) | |
1928 | CORE_ADDR startaddr; | |
1929 | CORE_ADDR pc; | |
1930 | { | |
1931 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
1932 | return pc >= startaddr && pc < end_prologue; | |
1933 | } | |
002a422b | 1934 | #endif |
ee5fb959 | 1935 | |
ac8cf67d PS |
1936 | /* Given a return value in `regbuf' with a type `valtype', |
1937 | extract and copy its value into `valbuf'. */ | |
1938 | void | |
1939 | mips_extract_return_value (valtype, regbuf, valbuf) | |
1940 | struct type *valtype; | |
1941 | char regbuf[REGISTER_BYTES]; | |
1942 | char *valbuf; | |
1943 | { | |
1944 | int regnum; | |
92a6d600 | 1945 | int offset = 0; |
c81a76b3 | 1946 | int len = TYPE_LENGTH (valtype); |
ac8cf67d | 1947 | |
e4dbd248 PS |
1948 | regnum = 2; |
1949 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
0af60e03 MS |
1950 | && (mips_fpu == MIPS_FPU_DOUBLE |
1951 | || (mips_fpu == MIPS_FPU_SINGLE && len <= MIPS_REGSIZE))) | |
f781fe93 | 1952 | regnum = FP0_REGNUM; |
ac8cf67d | 1953 | |
0af60e03 MS |
1954 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
1955 | { /* "un-left-justify" the value from the register */ | |
1956 | if (len < REGISTER_RAW_SIZE (regnum) && | |
1957 | TYPE_CODE (valtype) != TYPE_CODE_FLT) | |
1958 | offset = REGISTER_RAW_SIZE (regnum) - len; | |
1959 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ | |
1960 | len < REGISTER_RAW_SIZE (regnum) * 2 && | |
1961 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
1962 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
1963 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
1964 | } | |
c81a76b3 | 1965 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, len); |
f781fe93 | 1966 | REGISTER_CONVERT_TO_TYPE (regnum, valtype, valbuf); |
ac8cf67d PS |
1967 | } |
1968 | ||
1969 | /* Given a return value in `regbuf' with a type `valtype', | |
1970 | write it's value into the appropriate register. */ | |
1971 | void | |
1972 | mips_store_return_value (valtype, valbuf) | |
1973 | struct type *valtype; | |
1974 | char *valbuf; | |
1975 | { | |
1976 | int regnum; | |
0af60e03 MS |
1977 | int offset = 0; |
1978 | int len = TYPE_LENGTH (valtype); | |
ac8cf67d PS |
1979 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
1980 | ||
e4dbd248 PS |
1981 | regnum = 2; |
1982 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
0af60e03 MS |
1983 | && (mips_fpu == MIPS_FPU_DOUBLE |
1984 | || (mips_fpu == MIPS_FPU_SINGLE && len <= MIPS_REGSIZE))) | |
e4dbd248 PS |
1985 | regnum = FP0_REGNUM; |
1986 | ||
0af60e03 MS |
1987 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
1988 | { /* "left-justify" the value in the register */ | |
1989 | if (len < REGISTER_RAW_SIZE (regnum)) | |
1990 | offset = REGISTER_RAW_SIZE (regnum) - len; | |
1991 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ | |
1992 | len < REGISTER_RAW_SIZE (regnum) * 2 && | |
1993 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
1994 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
1995 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
1996 | } | |
1997 | memcpy(raw_buffer + offset, valbuf, len); | |
ac8cf67d | 1998 | REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); |
0af60e03 MS |
1999 | write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, |
2000 | len > REGISTER_RAW_SIZE (regnum) ? | |
2001 | len : REGISTER_RAW_SIZE (regnum)); | |
ac8cf67d PS |
2002 | } |
2003 | ||
e03c0cc6 ILT |
2004 | /* Exported procedure: Is PC in the signal trampoline code */ |
2005 | ||
2006 | int | |
2007 | in_sigtramp (pc, ignore) | |
2008 | CORE_ADDR pc; | |
2009 | char *ignore; /* function name */ | |
2010 | { | |
2011 | if (sigtramp_address == 0) | |
2012 | fixup_sigtramp (); | |
2013 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
2014 | } | |
2015 | ||
e4dbd248 PS |
2016 | /* Command to set FPU type. mips_fpu_string will have been set to the |
2017 | user's argument. Set mips_fpu based on mips_fpu_string, and then | |
2018 | canonicalize mips_fpu_string. */ | |
2019 | ||
2020 | /*ARGSUSED*/ | |
2021 | static void | |
2022 | mips_set_fpu_command (args, from_tty, c) | |
2023 | char *args; | |
2024 | int from_tty; | |
2025 | struct cmd_list_element *c; | |
2026 | { | |
2027 | char *err = NULL; | |
2028 | ||
2029 | if (mips_fpu_string == NULL || *mips_fpu_string == '\0') | |
2030 | mips_fpu = MIPS_FPU_DOUBLE; | |
2031 | else if (strcasecmp (mips_fpu_string, "double") == 0 | |
2032 | || strcasecmp (mips_fpu_string, "on") == 0 | |
2033 | || strcasecmp (mips_fpu_string, "1") == 0 | |
2034 | || strcasecmp (mips_fpu_string, "yes") == 0) | |
2035 | mips_fpu = MIPS_FPU_DOUBLE; | |
2036 | else if (strcasecmp (mips_fpu_string, "none") == 0 | |
2037 | || strcasecmp (mips_fpu_string, "off") == 0 | |
2038 | || strcasecmp (mips_fpu_string, "0") == 0 | |
2039 | || strcasecmp (mips_fpu_string, "no") == 0) | |
2040 | mips_fpu = MIPS_FPU_NONE; | |
2041 | else if (strcasecmp (mips_fpu_string, "single") == 0) | |
2042 | mips_fpu = MIPS_FPU_SINGLE; | |
2043 | else | |
2044 | err = strsave (mips_fpu_string); | |
2045 | ||
2046 | if (mips_fpu_string != NULL) | |
2047 | free (mips_fpu_string); | |
2048 | ||
2049 | switch (mips_fpu) | |
2050 | { | |
2051 | case MIPS_FPU_DOUBLE: | |
2052 | mips_fpu_string = strsave ("double"); | |
2053 | break; | |
2054 | case MIPS_FPU_SINGLE: | |
2055 | mips_fpu_string = strsave ("single"); | |
2056 | break; | |
2057 | case MIPS_FPU_NONE: | |
2058 | mips_fpu_string = strsave ("none"); | |
2059 | break; | |
2060 | } | |
2061 | ||
2062 | if (err != NULL) | |
2063 | { | |
2064 | struct cleanup *cleanups = make_cleanup (free, err); | |
2065 | error ("Unknown FPU type `%s'. Use `double', `none', or `single'.", | |
2066 | err); | |
2067 | do_cleanups (cleanups); | |
2068 | } | |
2069 | } | |
2070 | ||
2071 | static void | |
2072 | mips_show_fpu_command (args, from_tty, c) | |
2073 | char *args; | |
2074 | int from_tty; | |
2075 | struct cmd_list_element *c; | |
2076 | { | |
2077 | } | |
2078 | ||
9f9f94aa SS |
2079 | /* Command to set the processor type. */ |
2080 | ||
2081 | void | |
2082 | mips_set_processor_type_command (args, from_tty) | |
2083 | char *args; | |
2084 | int from_tty; | |
2085 | { | |
2086 | int i; | |
2087 | ||
2088 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
2089 | { | |
2090 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
2091 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
2092 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
2093 | ||
2094 | /* Restore the value. */ | |
2095 | tmp_mips_processor_type = strsave (mips_processor_type); | |
2096 | ||
2097 | return; | |
2098 | } | |
2099 | ||
2100 | if (!mips_set_processor_type (tmp_mips_processor_type)) | |
2101 | { | |
2102 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
2103 | /* Restore its value. */ | |
2104 | tmp_mips_processor_type = strsave (mips_processor_type); | |
2105 | } | |
2106 | } | |
2107 | ||
2108 | static void | |
2109 | mips_show_processor_type_command (args, from_tty) | |
2110 | char *args; | |
2111 | int from_tty; | |
2112 | { | |
2113 | } | |
2114 | ||
2115 | /* Modify the actual processor type. */ | |
2116 | ||
2117 | int | |
2118 | mips_set_processor_type (str) | |
2119 | char *str; | |
2120 | { | |
2121 | int i, j; | |
2122 | ||
2123 | if (str == NULL) | |
1d9489c1 | 2124 | return 0; |
9f9f94aa SS |
2125 | |
2126 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
2127 | { | |
2128 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
2129 | { | |
2130 | mips_processor_type = str; | |
2131 | ||
2132 | for (j = 0; j < NUM_REGS; ++j) | |
2133 | reg_names[j] = mips_processor_type_table[i].regnames[j]; | |
2134 | ||
2135 | return 1; | |
2136 | ||
2137 | /* FIXME tweak fpu flag too */ | |
2138 | } | |
2139 | } | |
2140 | ||
2141 | return 0; | |
2142 | } | |
2143 | ||
2144 | /* Attempt to identify the particular processor model by reading the | |
2145 | processor id. */ | |
2146 | ||
2147 | char * | |
2148 | mips_read_processor_type () | |
2149 | { | |
28444bf3 | 2150 | CORE_ADDR prid; |
9f9f94aa SS |
2151 | |
2152 | prid = read_register (PRID_REGNUM); | |
2153 | ||
80e0e92a | 2154 | if ((prid & ~0xf) == 0x700) |
9f9f94aa SS |
2155 | return savestring ("r3041", strlen("r3041")); |
2156 | ||
2157 | return NULL; | |
2158 | } | |
427fec5d JK |
2159 | |
2160 | /* Just like reinit_frame_cache, but with the right arguments to be | |
2161 | callable as an sfunc. */ | |
9f9f94aa | 2162 | |
427fec5d JK |
2163 | static void |
2164 | reinit_frame_cache_sfunc (args, from_tty, c) | |
2165 | char *args; | |
2166 | int from_tty; | |
2167 | struct cmd_list_element *c; | |
2168 | { | |
2169 | reinit_frame_cache (); | |
2170 | } | |
c2a0f1cb | 2171 | |
28444bf3 | 2172 | static int |
18b46e7c SS |
2173 | gdb_print_insn_mips (memaddr, info) |
2174 | bfd_vma memaddr; | |
2175 | disassemble_info *info; | |
2176 | { | |
f9f8c14b MA |
2177 | mips_extra_func_info_t proc_desc; |
2178 | ||
2179 | /* Search for the function containing this address. Set the low bit | |
2180 | of the address when searching, in case we were given an even address | |
2181 | that is the start of a 16-bit function. If we didn't do this, | |
2182 | the search would fail because the symbol table says the function | |
2183 | starts at an odd address, i.e. 1 byte past the given address. */ | |
c1fc0935 MA |
2184 | memaddr = ADDR_BITS_REMOVE (memaddr); |
2185 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
f9f8c14b MA |
2186 | |
2187 | /* Make an attempt to determine if this is a 16-bit function. If | |
2188 | the procedure descriptor exists and the address therein is odd, | |
2189 | it's definitely a 16-bit function. Otherwise, we have to just | |
2190 | guess that if the address passed in is odd, it's 16-bits. */ | |
2191 | if (proc_desc) | |
c1fc0935 | 2192 | info->mach = IS_MIPS16_ADDR (PROC_LOW_ADDR (proc_desc)) ? 16 : 0; |
f9f8c14b | 2193 | else |
c1fc0935 | 2194 | info->mach = IS_MIPS16_ADDR (memaddr) ? 16 : 0; |
f9f8c14b | 2195 | |
c1fc0935 | 2196 | /* Round down the instruction address to the appropriate boundary. */ |
f9f8c14b MA |
2197 | memaddr &= (info->mach == 16 ? ~1 : ~3); |
2198 | ||
2199 | /* Call the appropriate disassembler based on the target endian-ness. */ | |
18b46e7c SS |
2200 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
2201 | return print_insn_big_mips (memaddr, info); | |
2202 | else | |
2203 | return print_insn_little_mips (memaddr, info); | |
2204 | } | |
2205 | ||
f9f8c14b MA |
2206 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
2207 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
2208 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
2209 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
2210 | (if necessary) to point to the actual memory location where the | |
2211 | breakpoint should be inserted. */ | |
2212 | ||
2213 | unsigned char *mips_breakpoint_from_pc (pcptr, lenptr) | |
2214 | CORE_ADDR *pcptr; | |
2215 | int *lenptr; | |
2216 | { | |
2217 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2218 | { | |
c1fc0935 | 2219 | if (IS_MIPS16_ADDR (*pcptr)) |
f9f8c14b MA |
2220 | { |
2221 | static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT; | |
c1fc0935 | 2222 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
f9f8c14b MA |
2223 | *lenptr = sizeof(mips16_big_breakpoint); |
2224 | return mips16_big_breakpoint; | |
2225 | } | |
2226 | else | |
2227 | { | |
2228 | static char big_breakpoint[] = BIG_BREAKPOINT; | |
f781fe93 MA |
2229 | static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; |
2230 | static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
2231 | ||
f9f8c14b | 2232 | *lenptr = sizeof(big_breakpoint); |
f781fe93 MA |
2233 | |
2234 | if (strcmp (target_shortname, "mips") == 0) | |
2235 | return idt_big_breakpoint; | |
2236 | else if (strcmp (target_shortname, "ddb") == 0 | |
2237 | || strcmp (target_shortname, "pmon") == 0 | |
2238 | || strcmp (target_shortname, "lsi") == 0) | |
2239 | return pmon_big_breakpoint; | |
2240 | else | |
2241 | return big_breakpoint; | |
f9f8c14b MA |
2242 | } |
2243 | } | |
2244 | else | |
2245 | { | |
c1fc0935 | 2246 | if (IS_MIPS16_ADDR (*pcptr)) |
f9f8c14b MA |
2247 | { |
2248 | static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT; | |
c1fc0935 | 2249 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
f9f8c14b MA |
2250 | *lenptr = sizeof(mips16_little_breakpoint); |
2251 | return mips16_little_breakpoint; | |
2252 | } | |
2253 | else | |
2254 | { | |
2255 | static char little_breakpoint[] = LITTLE_BREAKPOINT; | |
f781fe93 MA |
2256 | static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT; |
2257 | static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT; | |
2258 | ||
f9f8c14b | 2259 | *lenptr = sizeof(little_breakpoint); |
f781fe93 MA |
2260 | |
2261 | if (strcmp (target_shortname, "mips") == 0) | |
2262 | return idt_little_breakpoint; | |
2263 | else if (strcmp (target_shortname, "ddb") == 0 | |
2264 | || strcmp (target_shortname, "pmon") == 0 | |
2265 | || strcmp (target_shortname, "lsi") == 0) | |
2266 | return pmon_little_breakpoint; | |
2267 | else | |
2268 | return little_breakpoint; | |
f9f8c14b MA |
2269 | } |
2270 | } | |
2271 | } | |
2272 | ||
2273 | /* Test whether the PC points to the return instruction at the | |
2274 | end of a function. This implements the ABOUT_TO_RETURN macro. */ | |
2275 | ||
2276 | int | |
2277 | mips_about_to_return (pc) | |
2278 | CORE_ADDR pc; | |
2279 | { | |
c1fc0935 | 2280 | if (IS_MIPS16_ADDR (pc)) |
f9f8c14b MA |
2281 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2282 | generates a "jr $ra"; other times it generates code to load | |
2283 | the return address from the stack to an accessible register (such | |
2284 | as $a3), then a "jr" using that register. This second case | |
2285 | is almost impossible to distinguish from an indirect jump | |
2286 | used for switch statements, so we don't even try. */ | |
c81a76b3 | 2287 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ |
f9f8c14b | 2288 | else |
c81a76b3 | 2289 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ |
f9f8c14b MA |
2290 | } |
2291 | ||
2292 | ||
f781fe93 MA |
2293 | /* If PC is in a mips16 call or return stub, return the address of the target |
2294 | PC, which is either the callee or the caller. There are several | |
2295 | cases which must be handled: | |
2296 | ||
2297 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
2298 | target PC is in $31 ($ra). | |
2299 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
2300 | and the target PC is in $2. | |
2301 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
2302 | before the jal instruction, this is effectively a call stub | |
2303 | and the the target PC is in $2. Otherwise this is effectively | |
2304 | a return stub and the target PC is in $18. | |
2305 | ||
2306 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
2307 | gory details. | |
2308 | ||
2309 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
2310 | */ | |
2311 | ||
2312 | CORE_ADDR | |
2313 | mips_skip_stub (pc) | |
2314 | CORE_ADDR pc; | |
2315 | { | |
2316 | char *name; | |
2317 | CORE_ADDR start_addr; | |
2318 | ||
2319 | /* Find the starting address and name of the function containing the PC. */ | |
2320 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2321 | return 0; | |
2322 | ||
2323 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
2324 | target PC is in $31 ($ra). */ | |
2325 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
2326 | || strcmp (name, "__mips16_ret_df") == 0) | |
2327 | return read_register (RA_REGNUM); | |
2328 | ||
2329 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
2330 | { | |
2331 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
2332 | and the target PC is in $2. */ | |
2333 | if (name[19] >= '0' && name[19] <= '9') | |
2334 | return read_register (2); | |
2335 | ||
2336 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
2337 | before the jal instruction, this is effectively a call stub | |
2338 | and the the target PC is in $2. Otherwise this is effectively | |
2339 | a return stub and the target PC is in $18. */ | |
2340 | else if (name[19] == 's' || name[19] == 'd') | |
2341 | { | |
2342 | if (pc == start_addr) | |
2343 | { | |
2344 | /* Check if the target of the stub is a compiler-generated | |
2345 | stub. Such a stub for a function bar might have a name | |
2346 | like __fn_stub_bar, and might look like this: | |
2347 | mfc1 $4,$f13 | |
2348 | mfc1 $5,$f12 | |
2349 | mfc1 $6,$f15 | |
2350 | mfc1 $7,$f14 | |
2351 | la $1,bar (becomes a lui/addiu pair) | |
2352 | jr $1 | |
2353 | So scan down to the lui/addi and extract the target | |
2354 | address from those two instructions. */ | |
2355 | ||
2356 | CORE_ADDR target_pc = read_register (2); | |
2357 | t_inst inst; | |
2358 | int i; | |
2359 | ||
2360 | /* See if the name of the target function is __fn_stub_*. */ | |
2361 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
2362 | return target_pc; | |
2363 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
2364 | && strcmp (name, "etext") != 0 | |
2365 | && strcmp (name, "_etext") != 0) | |
2366 | return target_pc; | |
2367 | ||
2368 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
2369 | The limit on the search is arbitrarily set to 20 | |
2370 | instructions. FIXME. */ | |
2371 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) | |
2372 | { | |
2373 | inst = mips_fetch_instruction (target_pc); | |
2374 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
2375 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
2376 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
2377 | return pc | (inst & 0xffff); /* low word */ | |
2378 | } | |
2379 | ||
2380 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
2381 | return target_pc; | |
2382 | } | |
2383 | else | |
2384 | /* This is the 'return' part of a call stub. The return | |
2385 | address is in $r18. */ | |
2386 | return read_register (18); | |
2387 | } | |
2388 | } | |
2389 | return 0; /* not a stub */ | |
2390 | } | |
2391 | ||
2392 | ||
2393 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
2394 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
2395 | ||
2396 | int | |
2397 | mips_in_call_stub (pc, name) | |
2398 | CORE_ADDR pc; | |
2399 | char *name; | |
2400 | { | |
2401 | CORE_ADDR start_addr; | |
2402 | ||
2403 | /* Find the starting address of the function containing the PC. If the | |
2404 | caller didn't give us a name, look it up at the same time. */ | |
2405 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
2406 | return 0; | |
2407 | ||
2408 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
2409 | { | |
2410 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
2411 | if (name[19] >= '0' && name[19] <= '9') | |
2412 | return 1; | |
2413 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
2414 | before the jal instruction, this is effectively a call stub. */ | |
2415 | else if (name[19] == 's' || name[19] == 'd') | |
2416 | return pc == start_addr; | |
2417 | } | |
2418 | ||
2419 | return 0; /* not a stub */ | |
2420 | } | |
2421 | ||
2422 | ||
2423 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
2424 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
2425 | ||
2426 | int | |
2427 | mips_in_return_stub (pc, name) | |
2428 | CORE_ADDR pc; | |
2429 | char *name; | |
2430 | { | |
2431 | CORE_ADDR start_addr; | |
2432 | ||
2433 | /* Find the starting address of the function containing the PC. */ | |
2434 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
2435 | return 0; | |
2436 | ||
2437 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
2438 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
2439 | || strcmp (name, "__mips16_ret_df") == 0) | |
2440 | return 1; | |
2441 | ||
2442 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
2443 | i.e. after the jal instruction, this is effectively a return stub. */ | |
2444 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 | |
2445 | && (name[19] == 's' || name[19] == 'd') | |
2446 | && pc != start_addr) | |
2447 | return 1; | |
2448 | ||
2449 | return 0; /* not a stub */ | |
2450 | } | |
2451 | ||
2452 | ||
2453 | /* Return non-zero if the PC is in a library helper function that should | |
2454 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
2455 | ||
2456 | int | |
2457 | mips_ignore_helper (pc) | |
2458 | CORE_ADDR pc; | |
2459 | { | |
2460 | char *name; | |
2461 | ||
2462 | /* Find the starting address and name of the function containing the PC. */ | |
2463 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
2464 | return 0; | |
2465 | ||
2466 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
2467 | that we want to ignore. */ | |
2468 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
2469 | || strcmp (name, "__mips16_ret_df") == 0); | |
2470 | } | |
2471 | ||
2472 | ||
c2a0f1cb ILT |
2473 | void |
2474 | _initialize_mips_tdep () | |
2475 | { | |
427fec5d JK |
2476 | struct cmd_list_element *c; |
2477 | ||
18b46e7c SS |
2478 | tm_print_insn = gdb_print_insn_mips; |
2479 | ||
427fec5d JK |
2480 | /* Let the user turn off floating point and set the fence post for |
2481 | heuristic_proc_start. */ | |
2482 | ||
e4dbd248 PS |
2483 | c = add_set_cmd ("mipsfpu", class_support, var_string_noescape, |
2484 | (char *) &mips_fpu_string, | |
2485 | "Set use of floating point coprocessor.\n\ | |
2486 | Set to `none' to avoid using floating point instructions when calling\n\ | |
2487 | functions or dealing with return values. Set to `single' to use only\n\ | |
2488 | single precision floating point as on the R4650. Set to `double' for\n\ | |
2489 | normal floating point support.", | |
2490 | &setlist); | |
2491 | c->function.sfunc = mips_set_fpu_command; | |
2492 | c = add_show_from_set (c, &showlist); | |
2493 | c->function.sfunc = mips_show_fpu_command; | |
2494 | ||
2495 | mips_fpu = MIPS_FPU_DOUBLE; | |
2496 | mips_fpu_string = strsave ("double"); | |
3127785a | 2497 | |
9f9f94aa SS |
2498 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
2499 | (char *) &tmp_mips_processor_type, | |
2500 | "Set the type of MIPS processor in use.\n\ | |
2501 | Set this to be able to access processor-type-specific registers.\n\ | |
2502 | ", | |
2503 | &setlist); | |
2504 | c->function.cfunc = mips_set_processor_type_command; | |
2505 | c = add_show_from_set (c, &showlist); | |
2506 | c->function.cfunc = mips_show_processor_type_command; | |
2507 | ||
2508 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
2509 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
2510 | ||
bdef72d2 JK |
2511 | /* We really would like to have both "0" and "unlimited" work, but |
2512 | command.c doesn't deal with that. So make it a var_zinteger | |
2513 | because the user can always use "999999" or some such for unlimited. */ | |
2514 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
427fec5d JK |
2515 | (char *) &heuristic_fence_post, |
2516 | "\ | |
23d35572 JK |
2517 | Set the distance searched for the start of a function.\n\ |
2518 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
2519 | program for the start of a function. This command sets the distance of the\n\ | |
2520 | search. The only need to set it is when debugging a stripped executable.", | |
427fec5d JK |
2521 | &setlist); |
2522 | /* We need to throw away the frame cache when we set this, since it | |
2523 | might change our ability to get backtraces. */ | |
2524 | c->function.sfunc = reinit_frame_cache_sfunc; | |
2525 | add_show_from_set (c, &showlist); | |
c2a0f1cb | 2526 | } |