Commit | Line | Data |
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7d9884b9 | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
18b46e7c | 2 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995 |
0434c1a0 | 3 | Free Software Foundation, Inc. |
bd5635a1 RP |
4 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
5 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
361bf6ee | 9 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 10 | it under the terms of the GNU General Public License as published by |
361bf6ee JG |
11 | the Free Software Foundation; either version 2 of the License, or |
12 | (at your option) any later version. | |
bd5635a1 | 13 | |
361bf6ee | 14 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
361bf6ee | 20 | along with this program; if not, write to the Free Software |
09af5868 | 21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
bd5635a1 | 22 | |
bd5635a1 | 23 | #include "defs.h" |
09af5868 | 24 | #include "gdb_string.h" |
bd5635a1 RP |
25 | #include "frame.h" |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "value.h" | |
29 | #include "gdbcmd.h" | |
ef08856f | 30 | #include "language.h" |
bd5635a1 | 31 | #include "gdbcore.h" |
62a469e1 SG |
32 | #include "symfile.h" |
33 | #include "objfiles.h" | |
3fed1c4a | 34 | #include "gdbtypes.h" |
28444bf3 | 35 | #include "target.h" |
bd5635a1 | 36 | |
ee5fb959 JK |
37 | #include "opcode/mips.h" |
38 | ||
28444bf3 | 39 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
70126bf9 KH |
40 | |
41 | /* FIXME: Put this declaration in frame.h. */ | |
42 | extern struct obstack frame_cache_obstack; | |
28444bf3 DP |
43 | |
44 | /* FIXME! this code assumes 4-byte instructions. */ | |
96431497 MA |
45 | #define MIPS_INSTLEN 4 /* Length of an instruction */ |
46 | #define MIPS_NUMREGS 32 /* Number of integer or float registers */ | |
47 | typedef unsigned long t_inst; /* Integer big enough to hold an instruction */ | |
28444bf3 | 48 | |
002a422b | 49 | #if 0 |
ee5fb959 | 50 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
002a422b | 51 | #endif |
ee5fb959 | 52 | |
28444bf3 DP |
53 | static int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *)); |
54 | ||
f2bf454e FF |
55 | static void mips_print_register PARAMS ((int, int)); |
56 | ||
57 | static mips_extra_func_info_t | |
58 | heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *)); | |
59 | ||
60 | static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR)); | |
61 | ||
28444bf3 | 62 | static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int)); |
f2bf454e | 63 | |
e4dbd248 PS |
64 | static void mips_set_fpu_command PARAMS ((char *, int, |
65 | struct cmd_list_element *)); | |
66 | ||
67 | static void mips_show_fpu_command PARAMS ((char *, int, | |
68 | struct cmd_list_element *)); | |
69 | ||
9f9f94aa SS |
70 | void mips_set_processor_type_command PARAMS ((char *, int)); |
71 | ||
1d9489c1 JK |
72 | int mips_set_processor_type PARAMS ((char *)); |
73 | ||
74 | static void mips_show_processor_type_command PARAMS ((char *, int)); | |
75 | ||
9f9f94aa SS |
76 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, |
77 | struct cmd_list_element *)); | |
78 | ||
f2bf454e FF |
79 | static mips_extra_func_info_t |
80 | find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info *next_frame)); | |
81 | ||
82 | static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc, | |
83 | mips_extra_func_info_t proc_desc)); | |
84 | ||
9f9f94aa SS |
85 | /* This value is the model of MIPS in use. It is derived from the value |
86 | of the PrID register. */ | |
87 | ||
88 | char *mips_processor_type; | |
89 | ||
90 | char *tmp_mips_processor_type; | |
91 | ||
c2a0f1cb ILT |
92 | /* Some MIPS boards don't support floating point, so we permit the |
93 | user to turn it off. */ | |
9f9f94aa | 94 | |
e4dbd248 PS |
95 | enum mips_fpu_type mips_fpu; |
96 | ||
97 | static char *mips_fpu_string; | |
c2a0f1cb | 98 | |
9f9f94aa SS |
99 | /* A set of original names, to be used when restoring back to generic |
100 | registers from a specific set. */ | |
101 | ||
102 | char *mips_generic_reg_names[] = REGISTER_NAMES; | |
103 | ||
104 | /* Names of IDT R3041 registers. */ | |
105 | ||
106 | char *mips_r3041_reg_names[] = { | |
107 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
108 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
109 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
110 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
111 | "sr", "lo", "hi", "bad", "cause","pc", | |
112 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
113 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
114 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
115 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
116 | "fsr", "fir", "fp", "", | |
117 | "", "", "bus", "ccfg", "", "", "", "", | |
118 | "", "", "port", "cmp", "", "", "epc", "prid", | |
119 | }; | |
120 | ||
121 | /* Names of IDT R3051 registers. */ | |
122 | ||
123 | char *mips_r3051_reg_names[] = { | |
124 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
125 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
126 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
127 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
128 | "sr", "lo", "hi", "bad", "cause","pc", | |
129 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
130 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
131 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
132 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
133 | "fsr", "fir", "fp", "", | |
134 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
135 | "", "", "ehi", "", "", "", "epc", "prid", | |
136 | }; | |
137 | ||
138 | /* Names of IDT R3081 registers. */ | |
139 | ||
140 | char *mips_r3081_reg_names[] = { | |
141 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
142 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
143 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
144 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
145 | "sr", "lo", "hi", "bad", "cause","pc", | |
146 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
147 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
148 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
149 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
150 | "fsr", "fir", "fp", "", | |
151 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
152 | "", "", "ehi", "", "", "", "epc", "prid", | |
153 | }; | |
154 | ||
e4dbd248 PS |
155 | /* Names of LSI 33k registers. */ |
156 | ||
157 | char *mips_lsi33k_reg_names[] = { | |
158 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
159 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
160 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
161 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
162 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
163 | "dcic", "bpc", "bda", "", "", "", "", "", | |
164 | "", "", "", "", "", "", "", "", | |
165 | "", "", "", "", "", "", "", "", | |
166 | "", "", "", "", "", "", "", "", | |
167 | "", "", "", "", | |
168 | "", "", "", "", "", "", "", "", | |
169 | "", "", "", "", "", "", "", "", | |
170 | }; | |
171 | ||
9f9f94aa SS |
172 | struct { |
173 | char *name; | |
174 | char **regnames; | |
175 | } mips_processor_type_table[] = { | |
176 | { "generic", mips_generic_reg_names }, | |
177 | { "r3041", mips_r3041_reg_names }, | |
178 | { "r3051", mips_r3051_reg_names }, | |
179 | { "r3071", mips_r3081_reg_names }, | |
180 | { "r3081", mips_r3081_reg_names }, | |
e4dbd248 | 181 | { "lsi33k", mips_lsi33k_reg_names }, |
9f9f94aa SS |
182 | { NULL, NULL } |
183 | }; | |
184 | ||
3127785a RP |
185 | /* Heuristic_proc_start may hunt through the text section for a long |
186 | time across a 2400 baud serial line. Allows the user to limit this | |
187 | search. */ | |
9f9f94aa | 188 | |
3127785a RP |
189 | static unsigned int heuristic_fence_post = 0; |
190 | ||
0f552c5f | 191 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
28444bf3 | 192 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ |
0f552c5f JG |
193 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
194 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
195 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
196 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
197 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
198 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
199 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
200 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
bd5635a1 | 201 | #define _PROC_MAGIC_ 0x0F0F0F0F |
0f552c5f JG |
202 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
203 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
bd5635a1 RP |
204 | |
205 | struct linked_proc_info | |
206 | { | |
207 | struct mips_extra_func_info info; | |
208 | struct linked_proc_info *next; | |
dac4929a | 209 | } *linked_proc_desc_table = NULL; |
bd5635a1 | 210 | |
f2bf454e FF |
211 | |
212 | /* This returns the PC of the first inst after the prologue. If we can't | |
213 | find the prologue, then return 0. */ | |
214 | ||
215 | static CORE_ADDR | |
216 | after_prologue (pc, proc_desc) | |
217 | CORE_ADDR pc; | |
218 | mips_extra_func_info_t proc_desc; | |
219 | { | |
220 | struct symtab_and_line sal; | |
221 | CORE_ADDR func_addr, func_end; | |
222 | ||
223 | if (!proc_desc) | |
224 | proc_desc = find_proc_desc (pc, NULL); | |
225 | ||
226 | if (proc_desc) | |
227 | { | |
228 | /* If function is frameless, then we need to do it the hard way. I | |
229 | strongly suspect that frameless always means prologueless... */ | |
230 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
231 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
232 | return 0; | |
233 | } | |
234 | ||
235 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
236 | return 0; /* Unknown */ | |
237 | ||
238 | sal = find_pc_line (func_addr, 0); | |
239 | ||
240 | if (sal.end < func_end) | |
241 | return sal.end; | |
242 | ||
243 | /* The line after the prologue is after the end of the function. In this | |
244 | case, tell the caller to find the prologue the hard way. */ | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
70126bf9 KH |
249 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
250 | NULL). */ | |
251 | ||
252 | void | |
253 | mips_find_saved_regs (fci) | |
9f9f94aa | 254 | struct frame_info *fci; |
70126bf9 KH |
255 | { |
256 | int ireg; | |
257 | CORE_ADDR reg_position; | |
258 | /* r0 bit means kernel trap */ | |
259 | int kernel_trap; | |
260 | /* What registers have been saved? Bitmasks. */ | |
261 | unsigned long gen_mask, float_mask; | |
262 | mips_extra_func_info_t proc_desc; | |
263 | ||
264 | fci->saved_regs = (struct frame_saved_regs *) | |
265 | obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs)); | |
266 | memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs)); | |
267 | ||
e4dbd248 PS |
268 | /* If it is the frame for sigtramp, the saved registers are located |
269 | in a sigcontext structure somewhere on the stack. | |
270 | If the stack layout for sigtramp changes we might have to change these | |
271 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
272 | #ifndef SIGFRAME_BASE | |
273 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
274 | above the sigtramp frame. */ | |
28444bf3 DP |
275 | #define SIGFRAME_BASE MIPS_REGSIZE |
276 | /* FIXME! Are these correct?? */ | |
277 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
278 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
279 | #define SIGFRAME_FPREGSAVE_OFF \ | |
280 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
e4dbd248 PS |
281 | #endif |
282 | #ifndef SIGFRAME_REG_SIZE | |
28444bf3 DP |
283 | /* FIXME! Is this correct?? */ |
284 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
e4dbd248 PS |
285 | #endif |
286 | if (fci->signal_handler_caller) | |
287 | { | |
28444bf3 | 288 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
289 | { |
290 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF | |
291 | + ireg * SIGFRAME_REG_SIZE; | |
292 | fci->saved_regs->regs[ireg] = reg_position; | |
293 | } | |
28444bf3 | 294 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
295 | { |
296 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF | |
297 | + ireg * SIGFRAME_REG_SIZE; | |
298 | fci->saved_regs->regs[FP0_REGNUM + ireg] = reg_position; | |
299 | } | |
300 | fci->saved_regs->regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
301 | return; | |
302 | } | |
303 | ||
70126bf9 KH |
304 | proc_desc = fci->proc_desc; |
305 | if (proc_desc == NULL) | |
306 | /* I'm not sure how/whether this can happen. Normally when we can't | |
307 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
308 | and set the saved_regs right away. */ | |
309 | return; | |
310 | ||
311 | kernel_trap = PROC_REG_MASK(proc_desc) & 1; | |
312 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); | |
313 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); | |
314 | ||
315 | if (/* In any frame other than the innermost, we assume that all | |
316 | registers have been saved. This assumes that all register | |
317 | saves in a function happen before the first function | |
318 | call. */ | |
319 | fci->next == NULL | |
320 | ||
321 | /* In a dummy frame we know exactly where things are saved. */ | |
322 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
323 | ||
f2bf454e FF |
324 | /* Don't bother unless we are inside a function prologue. Outside the |
325 | prologue, we know where everything is. */ | |
326 | ||
327 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) | |
328 | ||
70126bf9 KH |
329 | /* Not sure exactly what kernel_trap means, but if it means |
330 | the kernel saves the registers without a prologue doing it, | |
331 | we better not examine the prologue to see whether registers | |
332 | have been saved yet. */ | |
333 | && !kernel_trap) | |
334 | { | |
335 | /* We need to figure out whether the registers that the proc_desc | |
336 | claims are saved have been saved yet. */ | |
337 | ||
338 | CORE_ADDR addr; | |
339 | int status; | |
28444bf3 DP |
340 | char buf[MIPS_INSTLEN]; |
341 | t_inst inst; | |
70126bf9 KH |
342 | |
343 | /* Bitmasks; set if we have found a save for the register. */ | |
344 | unsigned long gen_save_found = 0; | |
345 | unsigned long float_save_found = 0; | |
346 | ||
347 | for (addr = PROC_LOW_ADDR (proc_desc); | |
348 | addr < fci->pc /*&& (gen_mask != gen_save_found | |
349 | || float_mask != float_save_found)*/; | |
28444bf3 | 350 | addr += MIPS_INSTLEN) |
70126bf9 | 351 | { |
28444bf3 | 352 | status = read_memory_nobpt (addr, buf, MIPS_INSTLEN); |
70126bf9 KH |
353 | if (status) |
354 | memory_error (status, addr); | |
28444bf3 | 355 | inst = extract_unsigned_integer (buf, MIPS_INSTLEN); |
70126bf9 KH |
356 | if (/* sw reg,n($sp) */ |
357 | (inst & 0xffe00000) == 0xafa00000 | |
358 | ||
359 | /* sw reg,n($r30) */ | |
360 | || (inst & 0xffe00000) == 0xafc00000 | |
361 | ||
362 | /* sd reg,n($sp) */ | |
363 | || (inst & 0xffe00000) == 0xffa00000) | |
364 | { | |
365 | /* It might be possible to use the instruction to | |
366 | find the offset, rather than the code below which | |
367 | is based on things being in a certain order in the | |
368 | frame, but figuring out what the instruction's offset | |
369 | is relative to might be a little tricky. */ | |
370 | int reg = (inst & 0x001f0000) >> 16; | |
371 | gen_save_found |= (1 << reg); | |
372 | } | |
373 | else if (/* swc1 freg,n($sp) */ | |
374 | (inst & 0xffe00000) == 0xe7a00000 | |
375 | ||
376 | /* swc1 freg,n($r30) */ | |
377 | || (inst & 0xffe00000) == 0xe7c00000 | |
378 | ||
379 | /* sdc1 freg,n($sp) */ | |
380 | || (inst & 0xffe00000) == 0xf7a00000) | |
381 | ||
382 | { | |
383 | int reg = ((inst & 0x001f0000) >> 16); | |
384 | float_save_found |= (1 << reg); | |
385 | } | |
386 | } | |
387 | gen_mask = gen_save_found; | |
388 | float_mask = float_save_found; | |
389 | } | |
390 | ||
391 | /* Fill in the offsets for the registers which gen_mask says | |
392 | were saved. */ | |
393 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
28444bf3 | 394 | for (ireg= MIPS_NUMREGS-1; gen_mask; --ireg, gen_mask <<= 1) |
70126bf9 KH |
395 | if (gen_mask & 0x80000000) |
396 | { | |
397 | fci->saved_regs->regs[ireg] = reg_position; | |
398 | reg_position -= MIPS_REGSIZE; | |
399 | } | |
400 | /* Fill in the offsets for the registers which float_mask says | |
401 | were saved. */ | |
402 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
403 | ||
404 | /* The freg_offset points to where the first *double* register | |
405 | is saved. So skip to the high-order word. */ | |
28444bf3 DP |
406 | if (! GDB_TARGET_IS_MIPS64) |
407 | reg_position += 4; | |
408 | ||
409 | /* FIXME! this code looks scary... | |
410 | * Looks like it's trying to do stuff with a register, | |
411 | * but .... ??? | |
412 | */ | |
413 | for (ireg = MIPS_NUMREGS-1; float_mask; --ireg, float_mask <<= 1) | |
70126bf9 KH |
414 | if (float_mask & 0x80000000) |
415 | { | |
416 | fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position; | |
417 | reg_position -= MIPS_REGSIZE; | |
418 | } | |
419 | ||
420 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; | |
421 | } | |
bd5635a1 | 422 | |
28444bf3 | 423 | static CORE_ADDR |
bd5635a1 | 424 | read_next_frame_reg(fi, regno) |
9f9f94aa | 425 | struct frame_info *fi; |
bd5635a1 RP |
426 | int regno; |
427 | { | |
bd5635a1 | 428 | for (; fi; fi = fi->next) |
70126bf9 | 429 | { |
e4dbd248 PS |
430 | /* We have to get the saved sp from the sigcontext |
431 | if it is a signal handler frame. */ | |
432 | if (regno == SP_REGNUM && !fi->signal_handler_caller) | |
433 | return fi->frame; | |
70126bf9 KH |
434 | else |
435 | { | |
436 | if (fi->saved_regs == NULL) | |
437 | mips_find_saved_regs (fi); | |
438 | if (fi->saved_regs->regs[regno]) | |
439 | return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE); | |
440 | } | |
441 | } | |
442 | return read_register (regno); | |
bd5635a1 RP |
443 | } |
444 | ||
96431497 MA |
445 | /* mips_addr_bits_remove - remove useless address bits */ |
446 | ||
447 | CORE_ADDR | |
448 | mips_addr_bits_remove (addr) | |
449 | CORE_ADDR addr; | |
450 | { | |
451 | if (GDB_TARGET_IS_MIPS64 | |
452 | && (addr >> 32 == (CORE_ADDR)0xffffffff) | |
453 | && (strcmp(target_shortname,"pmon")==0 | |
454 | || strcmp(target_shortname,"ddb")==0 | |
455 | || strcmp(target_shortname,"sim")==0)) | |
456 | { | |
457 | /* This hack is a work-around for existing boards using PMON, | |
458 | the simulator, and any other 64-bit targets that doesn't have | |
459 | true 64-bit addressing. On these targets, the upper 32 bits | |
460 | of addresses are ignored by the hardware. Thus, the PC or SP | |
461 | are likely to have been sign extended to all 1s by instruction | |
462 | sequences that load 32-bit addresses. For example, a typical | |
463 | piece of code that loads an address is this: | |
464 | lui $r2, <upper 16 bits> | |
465 | ori $r2, <lower 16 bits> | |
466 | But the lui sign-extends the value such that the upper 32 bits | |
467 | may be all 1s. The workaround is simply to mask off these bits. | |
468 | In the future, gcc may be changed to support true 64-bit | |
469 | addressing, and this masking will have to be disabled. */ | |
470 | addr &= (CORE_ADDR)0xffffffff; | |
471 | } | |
472 | ||
473 | return addr; | |
474 | } | |
475 | ||
28444bf3 | 476 | CORE_ADDR |
bd5635a1 | 477 | mips_frame_saved_pc(frame) |
9f9f94aa | 478 | struct frame_info *frame; |
bd5635a1 | 479 | { |
28444bf3 | 480 | CORE_ADDR saved_pc; |
0f552c5f | 481 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
0434c1a0 PS |
482 | /* We have to get the saved pc from the sigcontext |
483 | if it is a signal handler frame. */ | |
484 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
485 | : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); | |
0f552c5f | 486 | |
bd5635a1 | 487 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
28444bf3 DP |
488 | saved_pc = read_memory_integer(frame->frame - MIPS_REGSIZE, MIPS_REGSIZE); |
489 | else | |
490 | saved_pc = read_next_frame_reg(frame, pcreg); | |
0f552c5f | 491 | |
96431497 | 492 | return ADDR_BITS_REMOVE (saved_pc); |
bd5635a1 RP |
493 | } |
494 | ||
495 | static struct mips_extra_func_info temp_proc_desc; | |
496 | static struct frame_saved_regs temp_saved_regs; | |
497 | ||
a8172eea RP |
498 | /* This fencepost looks highly suspicious to me. Removing it also |
499 | seems suspicious as it could affect remote debugging across serial | |
3127785a | 500 | lines. */ |
a8172eea | 501 | |
0f552c5f JG |
502 | static CORE_ADDR |
503 | heuristic_proc_start(pc) | |
bd5635a1 RP |
504 | CORE_ADDR pc; |
505 | { | |
bd5635a1 | 506 | CORE_ADDR start_pc = pc; |
3127785a | 507 | CORE_ADDR fence = start_pc - heuristic_fence_post; |
0f552c5f JG |
508 | |
509 | if (start_pc == 0) return 0; | |
3127785a RP |
510 | |
511 | if (heuristic_fence_post == UINT_MAX | |
512 | || fence < VM_MIN_ADDRESS) | |
513 | fence = VM_MIN_ADDRESS; | |
0f552c5f | 514 | |
bd5635a1 | 515 | /* search back for previous return */ |
28444bf3 | 516 | for (start_pc -= MIPS_INSTLEN; ; start_pc -= MIPS_INSTLEN) /* FIXME!! */ |
a8172eea RP |
517 | if (start_pc < fence) |
518 | { | |
3127785a RP |
519 | /* It's not clear to me why we reach this point when |
520 | stop_soon_quietly, but with this test, at least we | |
521 | don't print out warnings for every child forked (eg, on | |
522 | decstation). 22apr93 rich@cygnus.com. */ | |
523 | if (!stop_soon_quietly) | |
524 | { | |
23d35572 JK |
525 | static int blurb_printed = 0; |
526 | ||
3127785a RP |
527 | if (fence == VM_MIN_ADDRESS) |
528 | warning("Hit beginning of text section without finding"); | |
529 | else | |
530 | warning("Hit heuristic-fence-post without finding"); | |
531 | ||
96431497 | 532 | warning("enclosing function for address 0x%s", paddr (pc)); |
23d35572 JK |
533 | if (!blurb_printed) |
534 | { | |
535 | printf_filtered ("\ | |
536 | This warning occurs if you are debugging a function without any symbols\n\ | |
537 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
538 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
539 | \n\ | |
540 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
541 | (more likely) you have encountered a bug in GDB.\n"); | |
542 | blurb_printed = 1; | |
543 | } | |
3127785a RP |
544 | } |
545 | ||
a8172eea RP |
546 | return 0; |
547 | } | |
bd5635a1 RP |
548 | else if (ABOUT_TO_RETURN(start_pc)) |
549 | break; | |
550 | ||
96431497 | 551 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ |
bd5635a1 RP |
552 | #if 0 |
553 | /* skip nops (usually 1) 0 - is this */ | |
28444bf3 DP |
554 | while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) |
555 | start_pc += MIPS_INSTLEN; | |
bd5635a1 RP |
556 | #endif |
557 | return start_pc; | |
558 | } | |
559 | ||
0f552c5f | 560 | static mips_extra_func_info_t |
bd5635a1 RP |
561 | heuristic_proc_desc(start_pc, limit_pc, next_frame) |
562 | CORE_ADDR start_pc, limit_pc; | |
9f9f94aa | 563 | struct frame_info *next_frame; |
bd5635a1 | 564 | { |
ac57e5ad | 565 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); |
bd5635a1 | 566 | CORE_ADDR cur_pc; |
28444bf3 | 567 | unsigned long frame_size; |
bd5635a1 | 568 | int has_frame_reg = 0; |
28444bf3 | 569 | CORE_ADDR reg30 = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
bd5635a1 RP |
570 | unsigned long reg_mask = 0; |
571 | ||
572 | if (start_pc == 0) return NULL; | |
9f9f94aa SS |
573 | memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); |
574 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); | |
575 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; | |
a70dc898 | 576 | |
9f9f94aa SS |
577 | if (start_pc + 200 < limit_pc) |
578 | limit_pc = start_pc + 200; | |
bd5635a1 RP |
579 | restart: |
580 | frame_size = 0; | |
28444bf3 DP |
581 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) { |
582 | char buf[MIPS_INSTLEN]; | |
bd5635a1 RP |
583 | unsigned long word; |
584 | int status; | |
585 | ||
28444bf3 | 586 | status = (unsigned long) read_memory_nobpt (cur_pc, buf, MIPS_INSTLEN); /* FIXME!! */ |
34df79fc | 587 | if (status) memory_error (status, cur_pc); |
28444bf3 | 588 | word = (unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN); /* FIXME!! */ |
34df79fc | 589 | |
96431497 MA |
590 | if ((word & 0xFFFF0000) == 0x27bd0000 /* addiu $sp,$sp,-i */ |
591 | || (word & 0xFFFF0000) == 0x23bd0000 /* addi $sp,$sp,-i */ | |
592 | || (word & 0xFFFF0000) == 0x67bd0000) /* daddiu $sp,$sp,-i */ | |
bd5635a1 | 593 | frame_size += (-word) & 0xFFFF; |
96431497 MA |
594 | else if ((word & 0xFFE00000) == 0xafa00000 /* sw reg,offset($sp) */ |
595 | || (word & 0xFFE00000) == 0xffa00000) { /* sd reg,offset($sp) */ | |
bd5635a1 RP |
596 | int reg = (word & 0x001F0000) >> 16; |
597 | reg_mask |= 1 << reg; | |
002a422b | 598 | temp_saved_regs.regs[reg] = sp + (word & 0xffff); |
bd5635a1 RP |
599 | } |
600 | else if ((word & 0xFFFF0000) == 0x27be0000) { /* addiu $30,$sp,size */ | |
002a422b JK |
601 | if ((word & 0xffff) != frame_size) |
602 | reg30 = sp + (word & 0xffff); | |
bd5635a1 | 603 | else if (!has_frame_reg) { |
28444bf3 | 604 | unsigned alloca_adjust; |
bd5635a1 RP |
605 | has_frame_reg = 1; |
606 | reg30 = read_next_frame_reg(next_frame, 30); | |
28444bf3 | 607 | alloca_adjust = (unsigned)(reg30 - (sp + (word & 0xffff))); |
bd5635a1 RP |
608 | if (alloca_adjust > 0) { |
609 | /* FP > SP + frame_size. This may be because | |
e03c0cc6 | 610 | * of an alloca or somethings similar. |
bd5635a1 RP |
611 | * Fix sp to "pre-alloca" value, and try again. |
612 | */ | |
613 | sp += alloca_adjust; | |
614 | goto restart; | |
615 | } | |
616 | } | |
617 | } | |
618 | else if ((word & 0xFFE00000) == 0xafc00000) { /* sw reg,offset($30) */ | |
619 | int reg = (word & 0x001F0000) >> 16; | |
620 | reg_mask |= 1 << reg; | |
002a422b | 621 | temp_saved_regs.regs[reg] = reg30 + (word & 0xffff); |
bd5635a1 RP |
622 | } |
623 | } | |
624 | if (has_frame_reg) { | |
625 | PROC_FRAME_REG(&temp_proc_desc) = 30; | |
626 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; | |
627 | } | |
628 | else { | |
629 | PROC_FRAME_REG(&temp_proc_desc) = SP_REGNUM; | |
630 | PROC_FRAME_OFFSET(&temp_proc_desc) = frame_size; | |
631 | } | |
632 | PROC_REG_MASK(&temp_proc_desc) = reg_mask; | |
633 | PROC_PC_REG(&temp_proc_desc) = RA_REGNUM; | |
634 | return &temp_proc_desc; | |
635 | } | |
636 | ||
0f552c5f | 637 | static mips_extra_func_info_t |
9f9f94aa SS |
638 | find_proc_desc (pc, next_frame) |
639 | CORE_ADDR pc; | |
640 | struct frame_info *next_frame; | |
bd5635a1 RP |
641 | { |
642 | mips_extra_func_info_t proc_desc; | |
0f552c5f | 643 | struct block *b = block_for_pc(pc); |
48be4c35 JK |
644 | struct symbol *sym; |
645 | CORE_ADDR startaddr; | |
646 | ||
647 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
648 | if (b == NULL) | |
649 | sym = NULL; | |
650 | else | |
651 | { | |
652 | if (startaddr > BLOCK_START (b)) | |
653 | /* This is the "pathological" case referred to in a comment in | |
654 | print_frame_info. It might be better to move this check into | |
655 | symbol reading. */ | |
656 | sym = NULL; | |
657 | else | |
658 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, | |
659 | 0, NULL); | |
660 | } | |
0f552c5f | 661 | |
e4dbd248 PS |
662 | /* If we never found a PDR for this function in symbol reading, then |
663 | examine prologues to find the information. */ | |
664 | if (sym && ((mips_extra_func_info_t) SYMBOL_VALUE (sym))->pdr.framereg == -1) | |
665 | sym = NULL; | |
666 | ||
0f552c5f | 667 | if (sym) |
bd5635a1 RP |
668 | { |
669 | /* IF this is the topmost frame AND | |
670 | * (this proc does not have debugging information OR | |
671 | * the PC is in the procedure prologue) | |
be772100 | 672 | * THEN create a "heuristic" proc_desc (by analyzing |
bd5635a1 RP |
673 | * the actual code) to replace the "official" proc_desc. |
674 | */ | |
9f9f94aa | 675 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
bd5635a1 RP |
676 | if (next_frame == NULL) { |
677 | struct symtab_and_line val; | |
678 | struct symbol *proc_symbol = | |
679 | PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); | |
0f552c5f | 680 | |
bd5635a1 RP |
681 | if (proc_symbol) { |
682 | val = find_pc_line (BLOCK_START | |
683 | (SYMBOL_BLOCK_VALUE(proc_symbol)), | |
684 | 0); | |
685 | val.pc = val.end ? val.end : pc; | |
686 | } | |
687 | if (!proc_symbol || pc < val.pc) { | |
688 | mips_extra_func_info_t found_heuristic = | |
9f9f94aa SS |
689 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
690 | pc, next_frame); | |
691 | if (found_heuristic) | |
692 | proc_desc = found_heuristic; | |
bd5635a1 RP |
693 | } |
694 | } | |
695 | } | |
696 | else | |
697 | { | |
0f552c5f JG |
698 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
699 | by procedure call dummys. However, the procedures being called ought | |
700 | to have their own proc_descs, and even if they don't, | |
701 | heuristic_proc_desc knows how to create them! */ | |
702 | ||
bd5635a1 | 703 | register struct linked_proc_info *link; |
9f9f94aa | 704 | |
bd5635a1 | 705 | for (link = linked_proc_desc_table; link; link = link->next) |
9f9f94aa SS |
706 | if (PROC_LOW_ADDR(&link->info) <= pc |
707 | && PROC_HIGH_ADDR(&link->info) > pc) | |
708 | return &link->info; | |
23d35572 | 709 | |
48be4c35 JK |
710 | if (startaddr == 0) |
711 | startaddr = heuristic_proc_start (pc); | |
712 | ||
bd5635a1 | 713 | proc_desc = |
48be4c35 | 714 | heuristic_proc_desc (startaddr, pc, next_frame); |
bd5635a1 RP |
715 | } |
716 | return proc_desc; | |
717 | } | |
718 | ||
96431497 MA |
719 | static CORE_ADDR |
720 | get_frame_pointer(frame, proc_desc) | |
721 | struct frame_info *frame; | |
722 | mips_extra_func_info_t proc_desc; | |
723 | { | |
724 | return ADDR_BITS_REMOVE (read_next_frame_reg (frame, | |
725 | PROC_FRAME_REG(proc_desc)) + PROC_FRAME_OFFSET(proc_desc)); | |
726 | } | |
727 | ||
bd5635a1 RP |
728 | mips_extra_func_info_t cached_proc_desc; |
729 | ||
9f9f94aa | 730 | CORE_ADDR |
0f552c5f | 731 | mips_frame_chain(frame) |
9f9f94aa | 732 | struct frame_info *frame; |
bd5635a1 | 733 | { |
bd5635a1 RP |
734 | mips_extra_func_info_t proc_desc; |
735 | CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); | |
be772100 | 736 | |
0f552c5f JG |
737 | if (saved_pc == 0 || inside_entry_file (saved_pc)) |
738 | return 0; | |
739 | ||
bd5635a1 | 740 | proc_desc = find_proc_desc(saved_pc, frame); |
0f552c5f JG |
741 | if (!proc_desc) |
742 | return 0; | |
743 | ||
bd5635a1 | 744 | cached_proc_desc = proc_desc; |
e797b4bc JK |
745 | |
746 | /* If no frame pointer and frame size is zero, we must be at end | |
747 | of stack (or otherwise hosed). If we don't check frame size, | |
748 | we loop forever if we see a zero size frame. */ | |
749 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
3f528883 | 750 | && PROC_FRAME_OFFSET (proc_desc) == 0 |
199b2450 TL |
751 | /* The previous frame from a sigtramp frame might be frameless |
752 | and have frame size zero. */ | |
753 | && !frame->signal_handler_caller) | |
bdef72d2 JK |
754 | return 0; |
755 | else | |
96431497 | 756 | return get_frame_pointer (frame, proc_desc); |
bd5635a1 RP |
757 | } |
758 | ||
759 | void | |
760 | init_extra_frame_info(fci) | |
761 | struct frame_info *fci; | |
762 | { | |
96431497 MA |
763 | int regnum; |
764 | ||
bd5635a1 | 765 | /* Use proc_desc calculated in frame_chain */ |
ee5fb959 JK |
766 | mips_extra_func_info_t proc_desc = |
767 | fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); | |
0f552c5f | 768 | |
70126bf9 | 769 | fci->saved_regs = NULL; |
bd5635a1 | 770 | fci->proc_desc = |
ee5fb959 | 771 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
bd5635a1 RP |
772 | if (proc_desc) |
773 | { | |
c2a0f1cb | 774 | /* Fixup frame-pointer - only needed for top frame */ |
5efd597b PS |
775 | /* This may not be quite right, if proc has a real frame register. |
776 | Get the value of the frame relative sp, procedure might have been | |
777 | interrupted by a signal at it's very start. */ | |
70126bf9 KH |
778 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
779 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
780 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
c2a0f1cb | 781 | else |
96431497 | 782 | fci->frame = get_frame_pointer (fci->next, proc_desc); |
bd5635a1 | 783 | |
48be4c35 | 784 | if (proc_desc == &temp_proc_desc) |
ee5fb959 | 785 | { |
09af5868 PS |
786 | char *name; |
787 | ||
788 | /* Do not set the saved registers for a sigtramp frame, | |
789 | mips_find_saved_registers will do that for us. | |
790 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
791 | find_pc_partial_function (fci->pc, &name, | |
792 | (CORE_ADDR *)NULL,(CORE_ADDR *)NULL); | |
793 | if (!IN_SIGTRAMP (fci->pc, name)) | |
794 | { | |
795 | fci->saved_regs = (struct frame_saved_regs*) | |
796 | obstack_alloc (&frame_cache_obstack, | |
797 | sizeof (struct frame_saved_regs)); | |
798 | *fci->saved_regs = temp_saved_regs; | |
799 | fci->saved_regs->regs[PC_REGNUM] | |
800 | = fci->saved_regs->regs[RA_REGNUM]; | |
801 | } | |
ee5fb959 | 802 | } |
bd5635a1 RP |
803 | |
804 | /* hack: if argument regs are saved, guess these contain args */ | |
96431497 MA |
805 | fci->num_args = -1; /* assume we can't tell how many args for now */ |
806 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) | |
807 | { | |
808 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) | |
809 | { | |
810 | fci->num_args = regnum - A0_REGNUM + 1; | |
811 | break; | |
812 | } | |
813 | } | |
bd5635a1 | 814 | } |
bd5635a1 RP |
815 | } |
816 | ||
a70dc898 RP |
817 | /* MIPS stack frames are almost impenetrable. When execution stops, |
818 | we basically have to look at symbol information for the function | |
819 | that we stopped in, which tells us *which* register (if any) is | |
820 | the base of the frame pointer, and what offset from that register | |
821 | the frame itself is at. | |
822 | ||
823 | This presents a problem when trying to examine a stack in memory | |
824 | (that isn't executing at the moment), using the "frame" command. We | |
825 | don't have a PC, nor do we have any registers except SP. | |
826 | ||
827 | This routine takes two arguments, SP and PC, and tries to make the | |
828 | cached frames look as if these two arguments defined a frame on the | |
829 | cache. This allows the rest of info frame to extract the important | |
830 | arguments without difficulty. */ | |
831 | ||
9f9f94aa | 832 | struct frame_info * |
c2a0f1cb ILT |
833 | setup_arbitrary_frame (argc, argv) |
834 | int argc; | |
9f9f94aa | 835 | CORE_ADDR *argv; |
a70dc898 | 836 | { |
c2a0f1cb ILT |
837 | if (argc != 2) |
838 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
839 | ||
840 | return create_new_frame (argv[0], argv[1]); | |
a70dc898 RP |
841 | } |
842 | ||
bd5635a1 | 843 | |
0f552c5f JG |
844 | CORE_ADDR |
845 | mips_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
bd5635a1 | 846 | int nargs; |
ac57e5ad | 847 | value_ptr *args; |
bd5635a1 RP |
848 | CORE_ADDR sp; |
849 | int struct_return; | |
850 | CORE_ADDR struct_addr; | |
851 | { | |
bd5635a1 | 852 | register i; |
28444bf3 | 853 | int accumulate_size; |
bd5635a1 | 854 | struct mips_arg { char *contents; int len; int offset; }; |
28444bf3 | 855 | struct mips_arg *mips_args; |
bd5635a1 | 856 | register struct mips_arg *m_arg; |
70126bf9 | 857 | int fake_args = 0; |
28444bf3 DP |
858 | int len; |
859 | ||
860 | /* Macro to round n up to the next a boundary (a must be a power of two) */ | |
861 | #define ALIGN(n,a) (((n)+(a)-1) & ~((a)-1)) | |
862 | ||
863 | /* First ensure that the stack and structure return address (if any) | |
864 | are properly aligned. */ | |
865 | ||
866 | sp = ALIGN (sp, MIPS_REGSIZE); | |
867 | struct_addr = ALIGN (struct_addr, MIPS_REGSIZE); | |
868 | ||
869 | accumulate_size = struct_return ? MIPS_REGSIZE : 0; | |
870 | ||
871 | /* Allocate descriptors for each argument, plus some extras for the | |
872 | dummies we will create to zero-fill the holes left when we align | |
873 | arguments passed in registers that are smaller than a register. */ | |
96431497 MA |
874 | mips_args = |
875 | (struct mips_arg*) alloca ((nargs + MIPS_NUM_ARG_REGS) * sizeof (struct mips_arg)); | |
70126bf9 | 876 | |
28444bf3 | 877 | /* Build up the list of argument descriptors. */ |
bd5635a1 | 878 | for (i = 0, m_arg = mips_args; i < nargs; i++, m_arg++) { |
e4dbd248 | 879 | value_ptr arg = args[i]; |
28444bf3 | 880 | len = m_arg->len = TYPE_LENGTH (VALUE_TYPE (arg)); |
bd5635a1 RP |
881 | /* This entire mips-specific routine is because doubles must be aligned |
882 | * on 8-byte boundaries. It still isn't quite right, because MIPS decided | |
883 | * to align 'struct {int a, b}' on 4-byte boundaries (even though this | |
884 | * breaks their varargs implementation...). A correct solution | |
96431497 | 885 | * requires a simulation of gcc's 'alignof' (and use of 'alignof' |
bd5635a1 | 886 | * in stdarg.h/varargs.h). |
70126bf9 KH |
887 | * On the 64 bit r4000 we always pass the first four arguments |
888 | * using eight bytes each, so that we can load them up correctly | |
889 | * in CALL_DUMMY. | |
bd5635a1 | 890 | */ |
28444bf3 DP |
891 | if (len > 4) /* FIXME? */ |
892 | accumulate_size = ALIGN (accumulate_size, 8); | |
bd5635a1 | 893 | m_arg->offset = accumulate_size; |
bd5635a1 | 894 | m_arg->contents = VALUE_CONTENTS(arg); |
9f9f94aa | 895 | if (! GDB_TARGET_IS_MIPS64) |
28444bf3 DP |
896 | /* For 32-bit targets, align the next argument on a 32-bit boundary. */ |
897 | accumulate_size = ALIGN (accumulate_size + len, 4); | |
70126bf9 KH |
898 | else |
899 | { | |
96431497 MA |
900 | /* The following test attempts to determine if the argument |
901 | is being passed on the stack. But it fails account for | |
902 | floating point arguments in the EABI, which should have their | |
903 | own accumulated size separate from that for integer arguments. | |
904 | FIXME!! */ | |
905 | if (accumulate_size >= MIPS_NUM_ARG_REGS * MIPS_REGSIZE) | |
906 | /* The argument is being passed on the stack, not a register, | |
907 | so adjust the size of the argument upward to account for stack | |
908 | alignment. But shouldn't we be right-aligning small arguments | |
909 | as we do below for the args-in-registers case? FIXME!! */ | |
28444bf3 | 910 | accumulate_size = ALIGN (accumulate_size + len, 8); |
9f9f94aa | 911 | else |
70126bf9 | 912 | { |
28444bf3 | 913 | if (len < MIPS_REGSIZE) |
9f9f94aa | 914 | { |
28444bf3 DP |
915 | /* The argument is being passed in a register, but is smaller |
916 | than a register. So it it must be right-aligned in the | |
917 | register image being placed in the stack, and the rest | |
918 | of the register image must be zero-filled. */ | |
919 | static char zeroes[MIPS_REGSIZE] = { 0 }; | |
920 | ||
921 | /* Align the arg in the rightmost part of the 64-bit word. */ | |
9f9f94aa | 922 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
28444bf3 DP |
923 | m_arg->offset += MIPS_REGSIZE - len; |
924 | ||
925 | /* Create a fake argument to zero-fill the unsused part | |
926 | of the 64-bit word. */ | |
9f9f94aa | 927 | ++m_arg; |
28444bf3 | 928 | m_arg->len = MIPS_REGSIZE - len; |
9f9f94aa SS |
929 | m_arg->contents = zeroes; |
930 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
931 | m_arg->offset = accumulate_size; | |
932 | else | |
933 | m_arg->offset = accumulate_size + len; | |
934 | ++fake_args; | |
935 | } | |
28444bf3 | 936 | accumulate_size = ALIGN (accumulate_size + len, MIPS_REGSIZE); |
70126bf9 | 937 | } |
70126bf9 | 938 | } |
bd5635a1 | 939 | } |
28444bf3 | 940 | accumulate_size = ALIGN (accumulate_size, 8); |
70126bf9 KH |
941 | if (accumulate_size < 4 * MIPS_REGSIZE) |
942 | accumulate_size = 4 * MIPS_REGSIZE; | |
bd5635a1 | 943 | sp -= accumulate_size; |
70126bf9 | 944 | for (i = nargs + fake_args; m_arg--, --i >= 0; ) |
bd5635a1 | 945 | write_memory(sp + m_arg->offset, m_arg->contents, m_arg->len); |
5efd597b PS |
946 | if (struct_return) |
947 | { | |
948 | char buf[TARGET_PTR_BIT / HOST_CHAR_BIT]; | |
949 | ||
950 | store_address (buf, sizeof buf, struct_addr); | |
951 | write_memory (sp, buf, sizeof buf); | |
952 | } | |
bd5635a1 RP |
953 | return sp; |
954 | } | |
955 | ||
28444bf3 DP |
956 | void |
957 | mips_push_register(CORE_ADDR *sp, int regno) | |
958 | { | |
959 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
960 | int regsize = REGISTER_RAW_SIZE (regno); | |
961 | ||
962 | *sp -= regsize; | |
963 | read_register_gen (regno, buffer); | |
964 | write_memory (*sp, buffer, regsize); | |
965 | } | |
966 | ||
967 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
e03c0cc6 | 968 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
bd5635a1 RP |
969 | |
970 | void | |
971 | mips_push_dummy_frame() | |
972 | { | |
973 | int ireg; | |
974 | struct linked_proc_info *link = (struct linked_proc_info*) | |
975 | xmalloc(sizeof(struct linked_proc_info)); | |
976 | mips_extra_func_info_t proc_desc = &link->info; | |
96431497 | 977 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM)); |
28444bf3 | 978 | CORE_ADDR old_sp = sp; |
bd5635a1 RP |
979 | link->next = linked_proc_desc_table; |
980 | linked_proc_desc_table = link; | |
28444bf3 DP |
981 | |
982 | /* FIXME! are these correct ? */ | |
bd5635a1 | 983 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
28444bf3 | 984 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
bd5635a1 | 985 | #define FLOAT_REG_SAVE_MASK MASK(0,19) |
e4dbd248 PS |
986 | #define FLOAT_SINGLE_REG_SAVE_MASK \ |
987 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
bd5635a1 RP |
988 | /* |
989 | * The registers we must save are all those not preserved across | |
990 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
28444bf3 DP |
991 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI |
992 | * and FP Control/Status registers. | |
993 | * | |
bd5635a1 RP |
994 | * |
995 | * Dummy frame layout: | |
996 | * (high memory) | |
997 | * Saved PC | |
998 | * Saved MMHI, MMLO, FPC_CSR | |
999 | * Saved R31 | |
1000 | * Saved R28 | |
1001 | * ... | |
1002 | * Saved R1 | |
1003 | * Saved D18 (i.e. F19, F18) | |
1004 | * ... | |
1005 | * Saved D0 (i.e. F1, F0) | |
c2a0f1cb | 1006 | * CALL_DUMMY (subroutine stub; see tm-mips.h) |
bd5635a1 RP |
1007 | * Parameter build area (not yet implemented) |
1008 | * (low memory) | |
1009 | */ | |
28444bf3 DP |
1010 | |
1011 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
1012 | write_register (PUSH_FP_REGNUM, sp); | |
1013 | PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; | |
1014 | PROC_FRAME_OFFSET(proc_desc) = 0; | |
1015 | mips_push_register (&sp, PC_REGNUM); | |
1016 | mips_push_register (&sp, HI_REGNUM); | |
1017 | mips_push_register (&sp, LO_REGNUM); | |
1018 | mips_push_register (&sp, mips_fpu == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
1019 | ||
1020 | /* Save general CPU registers */ | |
bd5635a1 | 1021 | PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; |
28444bf3 | 1022 | PROC_REG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved R31) from FP */ |
bd5635a1 RP |
1023 | for (ireg = 32; --ireg >= 0; ) |
1024 | if (PROC_REG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1025 | mips_push_register (&sp, ireg); |
3fed1c4a | 1026 | |
28444bf3 DP |
1027 | /* Save floating point registers starting with high order word */ |
1028 | PROC_FREG_MASK(proc_desc) = | |
1029 | mips_fpu == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK | |
1030 | : mips_fpu == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
1031 | PROC_FREG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved D18) from FP */ | |
bd5635a1 RP |
1032 | for (ireg = 32; --ireg >= 0; ) |
1033 | if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1034 | mips_push_register (&sp, ireg + FP0_REGNUM); |
3fed1c4a | 1035 | |
28444bf3 DP |
1036 | /* Update the stack pointer. Set the procedure's starting and ending |
1037 | addresses to point to the place on the stack where we'll be writing the | |
1038 | dummy code (in mips_push_arguments). */ | |
bd5635a1 RP |
1039 | write_register (SP_REGNUM, sp); |
1040 | PROC_LOW_ADDR(proc_desc) = sp - CALL_DUMMY_SIZE + CALL_DUMMY_START_OFFSET; | |
1041 | PROC_HIGH_ADDR(proc_desc) = sp; | |
1042 | SET_PROC_DESC_IS_DUMMY(proc_desc); | |
1043 | PROC_PC_REG(proc_desc) = RA_REGNUM; | |
1044 | } | |
1045 | ||
1046 | void | |
1047 | mips_pop_frame() | |
dac4929a SG |
1048 | { |
1049 | register int regnum; | |
9f9f94aa SS |
1050 | struct frame_info *frame = get_current_frame (); |
1051 | CORE_ADDR new_sp = FRAME_FP (frame); | |
dac4929a | 1052 | |
a70dc898 | 1053 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
dac4929a SG |
1054 | |
1055 | write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); | |
70126bf9 KH |
1056 | if (frame->saved_regs == NULL) |
1057 | mips_find_saved_regs (frame); | |
dac4929a SG |
1058 | if (proc_desc) |
1059 | { | |
28444bf3 | 1060 | for (regnum = MIPS_NUMREGS; --regnum >= 0; ) |
dac4929a SG |
1061 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) |
1062 | write_register (regnum, | |
1063 | read_memory_integer (frame->saved_regs->regs[regnum], | |
28444bf3 DP |
1064 | MIPS_REGSIZE)); |
1065 | for (regnum = MIPS_NUMREGS; --regnum >= 0; ) | |
dac4929a SG |
1066 | if (PROC_FREG_MASK(proc_desc) & (1 << regnum)) |
1067 | write_register (regnum + FP0_REGNUM, | |
28444bf3 | 1068 | read_memory_integer (frame->saved_regs->regs[regnum + FP0_REGNUM], MIPS_REGSIZE)); |
dac4929a SG |
1069 | } |
1070 | write_register (SP_REGNUM, new_sp); | |
1071 | flush_cached_frames (); | |
dac4929a | 1072 | |
199b2450 | 1073 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
bd5635a1 | 1074 | { |
dac4929a SG |
1075 | struct linked_proc_info *pi_ptr, *prev_ptr; |
1076 | ||
1077 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
1078 | pi_ptr != NULL; | |
1079 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
1080 | { | |
1081 | if (&pi_ptr->info == proc_desc) | |
1082 | break; | |
1083 | } | |
1084 | ||
1085 | if (pi_ptr == NULL) | |
1086 | error ("Can't locate dummy extra frame info\n"); | |
1087 | ||
1088 | if (prev_ptr != NULL) | |
1089 | prev_ptr->next = pi_ptr->next; | |
1090 | else | |
1091 | linked_proc_desc_table = pi_ptr->next; | |
1092 | ||
1093 | free (pi_ptr); | |
1094 | ||
28444bf3 DP |
1095 | write_register (HI_REGNUM, |
1096 | read_memory_integer (new_sp - 2*MIPS_REGSIZE, MIPS_REGSIZE)); | |
1097 | write_register (LO_REGNUM, | |
1098 | read_memory_integer (new_sp - 3*MIPS_REGSIZE, MIPS_REGSIZE)); | |
e4dbd248 | 1099 | if (mips_fpu != MIPS_FPU_NONE) |
28444bf3 DP |
1100 | write_register (FCRCS_REGNUM, |
1101 | read_memory_integer (new_sp - 4*MIPS_REGSIZE, MIPS_REGSIZE)); | |
bd5635a1 | 1102 | } |
bd5635a1 RP |
1103 | } |
1104 | ||
0f552c5f | 1105 | static void |
a70dc898 | 1106 | mips_print_register (regnum, all) |
bd5635a1 RP |
1107 | int regnum, all; |
1108 | { | |
e4dbd248 | 1109 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
bd5635a1 | 1110 | |
48be4c35 JK |
1111 | /* Get the data in raw format. */ |
1112 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
1113 | { | |
1114 | printf_filtered ("%s: [Invalid]", reg_names[regnum]); | |
1115 | return; | |
1116 | } | |
1117 | ||
1118 | /* If an even floating pointer register, also print as double. */ | |
28444bf3 | 1119 | if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+MIPS_NUMREGS |
e4dbd248 PS |
1120 | && !((regnum-FP0_REGNUM) & 1)) |
1121 | { | |
1122 | char dbuffer[MAX_REGISTER_RAW_SIZE]; | |
48be4c35 | 1123 | |
e4dbd248 | 1124 | read_relative_register_raw_bytes (regnum, dbuffer); |
28444bf3 | 1125 | read_relative_register_raw_bytes (regnum+1, dbuffer+4); /* FIXME!! */ |
ac8cf67d | 1126 | #ifdef REGISTER_CONVERT_TO_TYPE |
e4dbd248 | 1127 | REGISTER_CONVERT_TO_TYPE(regnum, builtin_type_double, dbuffer); |
ac8cf67d | 1128 | #endif |
e4dbd248 PS |
1129 | printf_filtered ("(d%d: ", regnum-FP0_REGNUM); |
1130 | val_print (builtin_type_double, dbuffer, 0, | |
1131 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
1132 | printf_filtered ("); "); | |
1133 | } | |
199b2450 | 1134 | fputs_filtered (reg_names[regnum], gdb_stdout); |
48be4c35 JK |
1135 | |
1136 | /* The problem with printing numeric register names (r26, etc.) is that | |
1137 | the user can't use them on input. Probably the best solution is to | |
1138 | fix it so that either the numeric or the funky (a2, etc.) names | |
1139 | are accepted on input. */ | |
28444bf3 | 1140 | if (regnum < MIPS_NUMREGS) |
48be4c35 JK |
1141 | printf_filtered ("(r%d): ", regnum); |
1142 | else | |
1143 | printf_filtered (": "); | |
bd5635a1 | 1144 | |
48be4c35 | 1145 | /* If virtual format is floating, print it that way. */ |
ac57e5ad | 1146 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
48be4c35 | 1147 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, |
199b2450 | 1148 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
48be4c35 JK |
1149 | /* Else print as integer in hex. */ |
1150 | else | |
ac57e5ad SS |
1151 | print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), |
1152 | 'x', 0, gdb_stdout); | |
bd5635a1 RP |
1153 | } |
1154 | ||
d8b3b00e | 1155 | /* Replacement for generic do_registers_info. */ |
9f9f94aa | 1156 | |
0f552c5f | 1157 | void |
361bf6ee | 1158 | mips_do_registers_info (regnum, fpregs) |
bd5635a1 | 1159 | int regnum; |
361bf6ee | 1160 | int fpregs; |
bd5635a1 | 1161 | { |
9f9f94aa SS |
1162 | if (regnum != -1) |
1163 | { | |
1164 | if (*(reg_names[regnum]) == '\0') | |
1165 | error ("Not a valid register for the current processor type"); | |
1166 | ||
bd5635a1 RP |
1167 | mips_print_register (regnum, 0); |
1168 | printf_filtered ("\n"); | |
9f9f94aa SS |
1169 | } |
1170 | else | |
1171 | { | |
09af5868 | 1172 | int did_newline = 0; |
9f9f94aa SS |
1173 | |
1174 | for (regnum = 0; regnum < NUM_REGS; ) | |
1175 | { | |
1176 | if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM) | |
1177 | || *(reg_names[regnum]) == '\0') | |
1178 | { | |
1179 | regnum++; | |
1180 | continue; | |
1181 | } | |
bd5635a1 RP |
1182 | mips_print_register (regnum, 1); |
1183 | regnum++; | |
9f9f94aa SS |
1184 | printf_filtered ("; "); |
1185 | did_newline = 0; | |
1186 | if ((regnum & 3) == 0) | |
1187 | { | |
1188 | printf_filtered ("\n"); | |
1189 | did_newline = 1; | |
1190 | } | |
1191 | } | |
1192 | if (!did_newline) | |
1193 | printf_filtered ("\n"); | |
1194 | } | |
bd5635a1 | 1195 | } |
9f9f94aa | 1196 | |
bd5635a1 RP |
1197 | /* Return number of args passed to a frame. described by FIP. |
1198 | Can return -1, meaning no way to tell. */ | |
1199 | ||
0f552c5f | 1200 | int |
9f9f94aa SS |
1201 | mips_frame_num_args (frame) |
1202 | struct frame_info *frame; | |
bd5635a1 | 1203 | { |
9f9f94aa SS |
1204 | #if 0 /* FIXME Use or lose this! */ |
1205 | struct chain_info_t *p; | |
bd5635a1 | 1206 | |
9f9f94aa SS |
1207 | p = mips_find_cached_frame (FRAME_FP (frame)); |
1208 | if (p->valid) | |
1209 | return p->the_info.numargs; | |
bd5635a1 | 1210 | #endif |
9f9f94aa | 1211 | return -1; |
bd5635a1 | 1212 | } |
96431497 | 1213 | |
427fec5d | 1214 | /* Is this a branch with a delay slot? */ |
9f9f94aa | 1215 | |
b5aff268 JK |
1216 | static int is_delayed PARAMS ((unsigned long)); |
1217 | ||
ee5fb959 JK |
1218 | static int |
1219 | is_delayed (insn) | |
1220 | unsigned long insn; | |
1221 | { | |
1222 | int i; | |
1223 | for (i = 0; i < NUMOPCODES; ++i) | |
1224 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
1225 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
1226 | break; | |
427fec5d JK |
1227 | return (i < NUMOPCODES |
1228 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
1229 | | INSN_COND_BRANCH_DELAY | |
1230 | | INSN_COND_BRANCH_LIKELY))); | |
ee5fb959 | 1231 | } |
b5aff268 JK |
1232 | |
1233 | int | |
1234 | mips_step_skips_delay (pc) | |
1235 | CORE_ADDR pc; | |
1236 | { | |
96431497 | 1237 | char buf[MIPS_INSTLEN]; |
b5aff268 | 1238 | |
96431497 | 1239 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) |
b5aff268 JK |
1240 | /* If error reading memory, guess that it is not a delayed branch. */ |
1241 | return 0; | |
96431497 | 1242 | return is_delayed ((unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN)); |
b5aff268 | 1243 | } |
ee5fb959 JK |
1244 | |
1245 | /* To skip prologues, I use this predicate. Returns either PC itself | |
1246 | if the code at PC does not look like a function prologue; otherwise | |
1247 | returns an address that (if we're lucky) follows the prologue. If | |
1248 | LENIENT, then we must skip everything which is involved in setting | |
1249 | up the frame (it's OK to skip more, just so long as we don't skip | |
1250 | anything which might clobber the registers which are being saved. | |
1251 | We must skip more in the case where part of the prologue is in the | |
1252 | delay slot of a non-prologue instruction). */ | |
bd5635a1 | 1253 | |
be772100 | 1254 | CORE_ADDR |
ee5fb959 | 1255 | mips_skip_prologue (pc, lenient) |
bd5635a1 | 1256 | CORE_ADDR pc; |
ee5fb959 | 1257 | int lenient; |
bd5635a1 | 1258 | { |
28444bf3 DP |
1259 | t_inst inst; |
1260 | unsigned offset; | |
0b0d6c3f | 1261 | int seen_sp_adjust = 0; |
ac57e5ad | 1262 | int load_immediate_bytes = 0; |
f2bf454e FF |
1263 | CORE_ADDR post_prologue_pc; |
1264 | ||
1265 | /* See if we can determine the end of the prologue via the symbol table. | |
1266 | If so, then return either PC, or the PC after the prologue, whichever | |
1267 | is greater. */ | |
1268 | ||
1269 | post_prologue_pc = after_prologue (pc, NULL); | |
1270 | ||
1271 | if (post_prologue_pc != 0) | |
1272 | return max (pc, post_prologue_pc); | |
1273 | ||
1274 | /* Can't determine prologue from the symbol table, need to examine | |
1275 | instructions. */ | |
bd5635a1 | 1276 | |
e157305c PS |
1277 | /* Skip the typical prologue instructions. These are the stack adjustment |
1278 | instruction and the instructions that save registers on the stack | |
1279 | or in the gcc frame. */ | |
96431497 | 1280 | for (offset = 0; offset < 100; offset += MIPS_INSTLEN) |
ee5fb959 | 1281 | { |
28444bf3 | 1282 | char buf[MIPS_INSTLEN]; |
ee5fb959 JK |
1283 | int status; |
1284 | ||
28444bf3 | 1285 | status = read_memory_nobpt (pc + offset, buf, MIPS_INSTLEN); |
ee5fb959 JK |
1286 | if (status) |
1287 | memory_error (status, pc + offset); | |
28444bf3 | 1288 | inst = (unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN); |
ee5fb959 | 1289 | |
002a422b | 1290 | #if 0 |
ee5fb959 JK |
1291 | if (lenient && is_delayed (inst)) |
1292 | continue; | |
002a422b | 1293 | #endif |
ee5fb959 | 1294 | |
96431497 | 1295 | /* Must add cases for 64-bit operations. FIXME!! */ |
e157305c | 1296 | if ((inst & 0xffff0000) == 0x27bd0000) /* addiu $sp,$sp,offset */ |
0b0d6c3f | 1297 | seen_sp_adjust = 1; |
ac57e5ad SS |
1298 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
1299 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
1300 | seen_sp_adjust = 1; | |
e157305c PS |
1301 | else if ((inst & 0xFFE00000) == 0xAFA00000 && (inst & 0x001F0000)) |
1302 | continue; /* sw reg,n($sp) */ | |
1303 | /* reg != $zero */ | |
1304 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
1305 | continue; | |
1306 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
1307 | /* sx reg,n($s8) */ | |
1308 | continue; /* reg != $zero */ | |
1d9489c1 JK |
1309 | |
1310 | /* move $s8,$sp. With different versions of gas this will be either | |
1311 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero'. Accept either. */ | |
1312 | else if (inst == 0x03A0F021 || inst == 0x03a0f025) | |
0b0d6c3f | 1313 | continue; |
1d9489c1 | 1314 | |
1b71de8e PS |
1315 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
1316 | continue; | |
e03c0cc6 ILT |
1317 | else if ((inst & 0xffff0000) == 0x3c1c0000) /* lui $gp,n */ |
1318 | continue; | |
1319 | else if ((inst & 0xffff0000) == 0x279c0000) /* addiu $gp,$gp,n */ | |
1320 | continue; | |
1321 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1322 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
1323 | continue; | |
ac57e5ad SS |
1324 | /* The following instructions load $at or $t0 with an immediate |
1325 | value in preparation for a stack adjustment via | |
1326 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
1327 | a local variable, so we accept them only before a stack adjustment | |
1328 | instruction was seen. */ | |
1329 | else if (!seen_sp_adjust) | |
1330 | { | |
1331 | if ((inst & 0xffff0000) == 0x3c010000 || /* lui $at,n */ | |
1332 | (inst & 0xffff0000) == 0x3c080000) /* lui $t0,n */ | |
1333 | { | |
28444bf3 | 1334 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1335 | continue; |
1336 | } | |
1337 | else if ((inst & 0xffff0000) == 0x34210000 || /* ori $at,$at,n */ | |
1338 | (inst & 0xffff0000) == 0x35080000 || /* ori $t0,$t0,n */ | |
1339 | (inst & 0xffff0000) == 0x34010000 || /* ori $at,$zero,n */ | |
1340 | (inst & 0xffff0000) == 0x34080000) /* ori $t0,$zero,n */ | |
1341 | { | |
28444bf3 | 1342 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1343 | continue; |
1344 | } | |
1345 | else | |
1346 | break; | |
1347 | } | |
0b0d6c3f | 1348 | else |
ac57e5ad | 1349 | break; |
d747e0af | 1350 | } |
e157305c | 1351 | |
ac57e5ad SS |
1352 | /* In a frameless function, we might have incorrectly |
1353 | skipped some load immediate instructions. Undo the skipping | |
1354 | if the load immediate was not followed by a stack adjustment. */ | |
1355 | if (load_immediate_bytes && !seen_sp_adjust) | |
1356 | offset -= load_immediate_bytes; | |
1357 | return pc + offset; | |
bd5635a1 | 1358 | } |
c2a0f1cb | 1359 | |
002a422b JK |
1360 | #if 0 |
1361 | /* The lenient prologue stuff should be superceded by the code in | |
1362 | init_extra_frame_info which looks to see whether the stores mentioned | |
1363 | in the proc_desc have actually taken place. */ | |
1364 | ||
ee5fb959 JK |
1365 | /* Is address PC in the prologue (loosely defined) for function at |
1366 | STARTADDR? */ | |
1367 | ||
1368 | static int | |
1369 | mips_in_lenient_prologue (startaddr, pc) | |
1370 | CORE_ADDR startaddr; | |
1371 | CORE_ADDR pc; | |
1372 | { | |
1373 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
1374 | return pc >= startaddr && pc < end_prologue; | |
1375 | } | |
002a422b | 1376 | #endif |
ee5fb959 | 1377 | |
ac8cf67d PS |
1378 | /* Given a return value in `regbuf' with a type `valtype', |
1379 | extract and copy its value into `valbuf'. */ | |
1380 | void | |
1381 | mips_extract_return_value (valtype, regbuf, valbuf) | |
1382 | struct type *valtype; | |
1383 | char regbuf[REGISTER_BYTES]; | |
1384 | char *valbuf; | |
1385 | { | |
1386 | int regnum; | |
92a6d600 | 1387 | int offset = 0; |
ac8cf67d | 1388 | |
e4dbd248 PS |
1389 | regnum = 2; |
1390 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1391 | && (mips_fpu == MIPS_FPU_DOUBLE | |
28444bf3 | 1392 | || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) /* FIXME!! */ |
e4dbd248 | 1393 | regnum = FP0_REGNUM; |
ac8cf67d | 1394 | |
92a6d600 PS |
1395 | if (TARGET_BYTE_ORDER == BIG_ENDIAN |
1396 | && TYPE_CODE (valtype) != TYPE_CODE_FLT | |
1397 | && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (regnum)) | |
1398 | offset = REGISTER_RAW_SIZE (regnum) - TYPE_LENGTH (valtype); | |
1399 | ||
1400 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, | |
1401 | TYPE_LENGTH (valtype)); | |
ac8cf67d PS |
1402 | #ifdef REGISTER_CONVERT_TO_TYPE |
1403 | REGISTER_CONVERT_TO_TYPE(regnum, valtype, valbuf); | |
1404 | #endif | |
1405 | } | |
1406 | ||
1407 | /* Given a return value in `regbuf' with a type `valtype', | |
1408 | write it's value into the appropriate register. */ | |
1409 | void | |
1410 | mips_store_return_value (valtype, valbuf) | |
1411 | struct type *valtype; | |
1412 | char *valbuf; | |
1413 | { | |
1414 | int regnum; | |
1415 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
1416 | ||
e4dbd248 PS |
1417 | regnum = 2; |
1418 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1419 | && (mips_fpu == MIPS_FPU_DOUBLE | |
28444bf3 | 1420 | || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) /* FIXME!! */ |
e4dbd248 PS |
1421 | regnum = FP0_REGNUM; |
1422 | ||
ac8cf67d PS |
1423 | memcpy(raw_buffer, valbuf, TYPE_LENGTH (valtype)); |
1424 | ||
1425 | #ifdef REGISTER_CONVERT_FROM_TYPE | |
1426 | REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); | |
1427 | #endif | |
1428 | ||
1429 | write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, TYPE_LENGTH (valtype)); | |
1430 | } | |
1431 | ||
e03c0cc6 ILT |
1432 | /* Exported procedure: Is PC in the signal trampoline code */ |
1433 | ||
1434 | int | |
1435 | in_sigtramp (pc, ignore) | |
1436 | CORE_ADDR pc; | |
1437 | char *ignore; /* function name */ | |
1438 | { | |
1439 | if (sigtramp_address == 0) | |
1440 | fixup_sigtramp (); | |
1441 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
1442 | } | |
1443 | ||
e4dbd248 PS |
1444 | /* Command to set FPU type. mips_fpu_string will have been set to the |
1445 | user's argument. Set mips_fpu based on mips_fpu_string, and then | |
1446 | canonicalize mips_fpu_string. */ | |
1447 | ||
1448 | /*ARGSUSED*/ | |
1449 | static void | |
1450 | mips_set_fpu_command (args, from_tty, c) | |
1451 | char *args; | |
1452 | int from_tty; | |
1453 | struct cmd_list_element *c; | |
1454 | { | |
1455 | char *err = NULL; | |
1456 | ||
1457 | if (mips_fpu_string == NULL || *mips_fpu_string == '\0') | |
1458 | mips_fpu = MIPS_FPU_DOUBLE; | |
1459 | else if (strcasecmp (mips_fpu_string, "double") == 0 | |
1460 | || strcasecmp (mips_fpu_string, "on") == 0 | |
1461 | || strcasecmp (mips_fpu_string, "1") == 0 | |
1462 | || strcasecmp (mips_fpu_string, "yes") == 0) | |
1463 | mips_fpu = MIPS_FPU_DOUBLE; | |
1464 | else if (strcasecmp (mips_fpu_string, "none") == 0 | |
1465 | || strcasecmp (mips_fpu_string, "off") == 0 | |
1466 | || strcasecmp (mips_fpu_string, "0") == 0 | |
1467 | || strcasecmp (mips_fpu_string, "no") == 0) | |
1468 | mips_fpu = MIPS_FPU_NONE; | |
1469 | else if (strcasecmp (mips_fpu_string, "single") == 0) | |
1470 | mips_fpu = MIPS_FPU_SINGLE; | |
1471 | else | |
1472 | err = strsave (mips_fpu_string); | |
1473 | ||
1474 | if (mips_fpu_string != NULL) | |
1475 | free (mips_fpu_string); | |
1476 | ||
1477 | switch (mips_fpu) | |
1478 | { | |
1479 | case MIPS_FPU_DOUBLE: | |
1480 | mips_fpu_string = strsave ("double"); | |
1481 | break; | |
1482 | case MIPS_FPU_SINGLE: | |
1483 | mips_fpu_string = strsave ("single"); | |
1484 | break; | |
1485 | case MIPS_FPU_NONE: | |
1486 | mips_fpu_string = strsave ("none"); | |
1487 | break; | |
1488 | } | |
1489 | ||
1490 | if (err != NULL) | |
1491 | { | |
1492 | struct cleanup *cleanups = make_cleanup (free, err); | |
1493 | error ("Unknown FPU type `%s'. Use `double', `none', or `single'.", | |
1494 | err); | |
1495 | do_cleanups (cleanups); | |
1496 | } | |
1497 | } | |
1498 | ||
1499 | static void | |
1500 | mips_show_fpu_command (args, from_tty, c) | |
1501 | char *args; | |
1502 | int from_tty; | |
1503 | struct cmd_list_element *c; | |
1504 | { | |
1505 | } | |
1506 | ||
9f9f94aa SS |
1507 | /* Command to set the processor type. */ |
1508 | ||
1509 | void | |
1510 | mips_set_processor_type_command (args, from_tty) | |
1511 | char *args; | |
1512 | int from_tty; | |
1513 | { | |
1514 | int i; | |
1515 | ||
1516 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
1517 | { | |
1518 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
1519 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
1520 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
1521 | ||
1522 | /* Restore the value. */ | |
1523 | tmp_mips_processor_type = strsave (mips_processor_type); | |
1524 | ||
1525 | return; | |
1526 | } | |
1527 | ||
1528 | if (!mips_set_processor_type (tmp_mips_processor_type)) | |
1529 | { | |
1530 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
1531 | /* Restore its value. */ | |
1532 | tmp_mips_processor_type = strsave (mips_processor_type); | |
1533 | } | |
1534 | } | |
1535 | ||
1536 | static void | |
1537 | mips_show_processor_type_command (args, from_tty) | |
1538 | char *args; | |
1539 | int from_tty; | |
1540 | { | |
1541 | } | |
1542 | ||
1543 | /* Modify the actual processor type. */ | |
1544 | ||
1545 | int | |
1546 | mips_set_processor_type (str) | |
1547 | char *str; | |
1548 | { | |
1549 | int i, j; | |
1550 | ||
1551 | if (str == NULL) | |
1d9489c1 | 1552 | return 0; |
9f9f94aa SS |
1553 | |
1554 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
1555 | { | |
1556 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
1557 | { | |
1558 | mips_processor_type = str; | |
1559 | ||
1560 | for (j = 0; j < NUM_REGS; ++j) | |
1561 | reg_names[j] = mips_processor_type_table[i].regnames[j]; | |
1562 | ||
1563 | return 1; | |
1564 | ||
1565 | /* FIXME tweak fpu flag too */ | |
1566 | } | |
1567 | } | |
1568 | ||
1569 | return 0; | |
1570 | } | |
1571 | ||
1572 | /* Attempt to identify the particular processor model by reading the | |
1573 | processor id. */ | |
1574 | ||
1575 | char * | |
1576 | mips_read_processor_type () | |
1577 | { | |
28444bf3 | 1578 | CORE_ADDR prid; |
9f9f94aa SS |
1579 | |
1580 | prid = read_register (PRID_REGNUM); | |
1581 | ||
80e0e92a | 1582 | if ((prid & ~0xf) == 0x700) |
9f9f94aa SS |
1583 | return savestring ("r3041", strlen("r3041")); |
1584 | ||
1585 | return NULL; | |
1586 | } | |
427fec5d JK |
1587 | |
1588 | /* Just like reinit_frame_cache, but with the right arguments to be | |
1589 | callable as an sfunc. */ | |
9f9f94aa | 1590 | |
427fec5d JK |
1591 | static void |
1592 | reinit_frame_cache_sfunc (args, from_tty, c) | |
1593 | char *args; | |
1594 | int from_tty; | |
1595 | struct cmd_list_element *c; | |
1596 | { | |
1597 | reinit_frame_cache (); | |
1598 | } | |
c2a0f1cb | 1599 | |
28444bf3 | 1600 | static int |
18b46e7c SS |
1601 | gdb_print_insn_mips (memaddr, info) |
1602 | bfd_vma memaddr; | |
1603 | disassemble_info *info; | |
1604 | { | |
1605 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1606 | return print_insn_big_mips (memaddr, info); | |
1607 | else | |
1608 | return print_insn_little_mips (memaddr, info); | |
1609 | } | |
1610 | ||
c2a0f1cb ILT |
1611 | void |
1612 | _initialize_mips_tdep () | |
1613 | { | |
427fec5d JK |
1614 | struct cmd_list_element *c; |
1615 | ||
18b46e7c SS |
1616 | tm_print_insn = gdb_print_insn_mips; |
1617 | ||
427fec5d JK |
1618 | /* Let the user turn off floating point and set the fence post for |
1619 | heuristic_proc_start. */ | |
1620 | ||
e4dbd248 PS |
1621 | c = add_set_cmd ("mipsfpu", class_support, var_string_noescape, |
1622 | (char *) &mips_fpu_string, | |
1623 | "Set use of floating point coprocessor.\n\ | |
1624 | Set to `none' to avoid using floating point instructions when calling\n\ | |
1625 | functions or dealing with return values. Set to `single' to use only\n\ | |
1626 | single precision floating point as on the R4650. Set to `double' for\n\ | |
1627 | normal floating point support.", | |
1628 | &setlist); | |
1629 | c->function.sfunc = mips_set_fpu_command; | |
1630 | c = add_show_from_set (c, &showlist); | |
1631 | c->function.sfunc = mips_show_fpu_command; | |
1632 | ||
1633 | mips_fpu = MIPS_FPU_DOUBLE; | |
1634 | mips_fpu_string = strsave ("double"); | |
3127785a | 1635 | |
9f9f94aa SS |
1636 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
1637 | (char *) &tmp_mips_processor_type, | |
1638 | "Set the type of MIPS processor in use.\n\ | |
1639 | Set this to be able to access processor-type-specific registers.\n\ | |
1640 | ", | |
1641 | &setlist); | |
1642 | c->function.cfunc = mips_set_processor_type_command; | |
1643 | c = add_show_from_set (c, &showlist); | |
1644 | c->function.cfunc = mips_show_processor_type_command; | |
1645 | ||
1646 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
1647 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
1648 | ||
bdef72d2 JK |
1649 | /* We really would like to have both "0" and "unlimited" work, but |
1650 | command.c doesn't deal with that. So make it a var_zinteger | |
1651 | because the user can always use "999999" or some such for unlimited. */ | |
1652 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
427fec5d JK |
1653 | (char *) &heuristic_fence_post, |
1654 | "\ | |
23d35572 JK |
1655 | Set the distance searched for the start of a function.\n\ |
1656 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
1657 | program for the start of a function. This command sets the distance of the\n\ | |
1658 | search. The only need to set it is when debugging a stripped executable.", | |
427fec5d JK |
1659 | &setlist); |
1660 | /* We need to throw away the frame cache when we set this, since it | |
1661 | might change our ability to get backtraces. */ | |
1662 | c->function.sfunc = reinit_frame_cache_sfunc; | |
1663 | add_show_from_set (c, &showlist); | |
c2a0f1cb | 1664 | } |