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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "gdb_string.h" | |
5e2e9765 | 25 | #include "gdb_assert.h" |
c906108c SS |
26 | #include "frame.h" |
27 | #include "inferior.h" | |
28 | #include "symtab.h" | |
29 | #include "value.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "language.h" | |
32 | #include "gdbcore.h" | |
33 | #include "symfile.h" | |
34 | #include "objfiles.h" | |
35 | #include "gdbtypes.h" | |
36 | #include "target.h" | |
28d069e6 | 37 | #include "arch-utils.h" |
4e052eda | 38 | #include "regcache.h" |
70f80edf | 39 | #include "osabi.h" |
d1973055 | 40 | #include "mips-tdep.h" |
fe898f56 | 41 | #include "block.h" |
a4b8ebc8 | 42 | #include "reggroups.h" |
c906108c | 43 | #include "opcode/mips.h" |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
a4b8ebc8 | 47 | #include "sim-regno.h" |
a89aa300 | 48 | #include "dis-asm.h" |
edfae063 AC |
49 | #include "frame-unwind.h" |
50 | #include "frame-base.h" | |
51 | #include "trad-frame.h" | |
7d9b040b | 52 | #include "infcall.h" |
fed7ba43 | 53 | #include "floatformat.h" |
29709017 DJ |
54 | #include "remote.h" |
55 | #include "target-descriptions.h" | |
2bd0c3d7 | 56 | #include "dwarf2-frame.h" |
f8b73d13 | 57 | #include "user-regs.h" |
79a45b7d | 58 | #include "valprint.h" |
175ff332 | 59 | #include "ax.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
24e05951 | 65 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
66 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 | #define ST0_FR (1 << 26) | |
68 | ||
b0069a17 AC |
69 | /* The sizes of floating point registers. */ |
70 | ||
71 | enum | |
72 | { | |
73 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
74 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
75 | }; | |
76 | ||
1a69e1e4 DJ |
77 | enum |
78 | { | |
79 | MIPS32_REGSIZE = 4, | |
80 | MIPS64_REGSIZE = 8 | |
81 | }; | |
0dadbba0 | 82 | |
2e4ebe70 DJ |
83 | static const char *mips_abi_string; |
84 | ||
40478521 | 85 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
86 | "auto", |
87 | "n32", | |
88 | "o32", | |
28d169de | 89 | "n64", |
2e4ebe70 DJ |
90 | "o64", |
91 | "eabi32", | |
92 | "eabi64", | |
93 | NULL | |
94 | }; | |
95 | ||
f8b73d13 DJ |
96 | /* The standard register names, and all the valid aliases for them. */ |
97 | struct register_alias | |
98 | { | |
99 | const char *name; | |
100 | int regnum; | |
101 | }; | |
102 | ||
103 | /* Aliases for o32 and most other ABIs. */ | |
104 | const struct register_alias mips_o32_aliases[] = { | |
105 | { "ta0", 12 }, | |
106 | { "ta1", 13 }, | |
107 | { "ta2", 14 }, | |
108 | { "ta3", 15 } | |
109 | }; | |
110 | ||
111 | /* Aliases for n32 and n64. */ | |
112 | const struct register_alias mips_n32_n64_aliases[] = { | |
113 | { "ta0", 8 }, | |
114 | { "ta1", 9 }, | |
115 | { "ta2", 10 }, | |
116 | { "ta3", 11 } | |
117 | }; | |
118 | ||
119 | /* Aliases for ABI-independent registers. */ | |
120 | const struct register_alias mips_register_aliases[] = { | |
121 | /* The architecture manuals specify these ABI-independent names for | |
122 | the GPRs. */ | |
123 | #define R(n) { "r" #n, n } | |
124 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
125 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
126 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
127 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
128 | #undef R | |
129 | ||
130 | /* k0 and k1 are sometimes called these instead (for "kernel | |
131 | temp"). */ | |
132 | { "kt0", 26 }, | |
133 | { "kt1", 27 }, | |
134 | ||
135 | /* This is the traditional GDB name for the CP0 status register. */ | |
136 | { "sr", MIPS_PS_REGNUM }, | |
137 | ||
138 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
139 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
140 | ||
141 | /* This is the traditional GDB name for the FCSR. */ | |
142 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
143 | }; | |
144 | ||
865093a3 AR |
145 | const struct register_alias mips_numeric_register_aliases[] = { |
146 | #define R(n) { #n, n } | |
147 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
148 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
149 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
150 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
151 | #undef R | |
152 | }; | |
153 | ||
c906108c SS |
154 | #ifndef MIPS_DEFAULT_FPU_TYPE |
155 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
156 | #endif | |
157 | static int mips_fpu_type_auto = 1; | |
158 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 159 | |
9ace0497 | 160 | static int mips_debug = 0; |
7a292a7a | 161 | |
29709017 DJ |
162 | /* Properties (for struct target_desc) describing the g/G packet |
163 | layout. */ | |
164 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
165 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
166 | ||
4eb0ad19 DJ |
167 | struct target_desc *mips_tdesc_gp32; |
168 | struct target_desc *mips_tdesc_gp64; | |
169 | ||
56cea623 AC |
170 | const struct mips_regnum * |
171 | mips_regnum (struct gdbarch *gdbarch) | |
172 | { | |
173 | return gdbarch_tdep (gdbarch)->regnum; | |
174 | } | |
175 | ||
176 | static int | |
177 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
178 | { | |
179 | return mips_regnum (gdbarch)->fp0 + 12; | |
180 | } | |
181 | ||
74ed0bb4 MD |
182 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
183 | == MIPS_ABI_EABI32 \ | |
184 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 185 | |
025bb325 MS |
186 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
187 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 188 | |
025bb325 MS |
189 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
190 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 191 | |
74ed0bb4 | 192 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 193 | |
95404a3e AC |
194 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
195 | functions to test, set, or clear bit 0 of addresses. */ | |
196 | ||
197 | static CORE_ADDR | |
198 | is_mips16_addr (CORE_ADDR addr) | |
199 | { | |
200 | return ((addr) & 1); | |
201 | } | |
202 | ||
95404a3e AC |
203 | static CORE_ADDR |
204 | unmake_mips16_addr (CORE_ADDR addr) | |
205 | { | |
5b652102 | 206 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
207 | } |
208 | ||
930bd0e0 KB |
209 | static CORE_ADDR |
210 | make_mips16_addr (CORE_ADDR addr) | |
211 | { | |
212 | return ((addr) | (CORE_ADDR) 1); | |
213 | } | |
214 | ||
d1973055 KB |
215 | /* Return the MIPS ABI associated with GDBARCH. */ |
216 | enum mips_abi | |
217 | mips_abi (struct gdbarch *gdbarch) | |
218 | { | |
219 | return gdbarch_tdep (gdbarch)->mips_abi; | |
220 | } | |
221 | ||
4246e332 | 222 | int |
1b13c4f6 | 223 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 224 | { |
29709017 DJ |
225 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
226 | ||
227 | /* If we know how big the registers are, use that size. */ | |
228 | if (tdep->register_size_valid_p) | |
229 | return tdep->register_size; | |
230 | ||
231 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
232 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
233 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
234 | } | |
235 | ||
025bb325 | 236 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 237 | |
e6bc2e8a | 238 | unsigned int |
13326b4e | 239 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 240 | { |
1a69e1e4 DJ |
241 | switch (mips_abi (gdbarch)) |
242 | { | |
243 | case MIPS_ABI_EABI32: | |
244 | case MIPS_ABI_O32: | |
245 | return 4; | |
246 | case MIPS_ABI_N32: | |
247 | case MIPS_ABI_N64: | |
248 | case MIPS_ABI_O64: | |
249 | case MIPS_ABI_EABI64: | |
250 | return 8; | |
251 | case MIPS_ABI_UNKNOWN: | |
252 | case MIPS_ABI_LAST: | |
253 | default: | |
254 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
255 | } | |
d929b26f AC |
256 | } |
257 | ||
71b8ef93 | 258 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 259 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 260 | "info" field is used for this purpose. |
5a89d8aa | 261 | |
95f1da47 | 262 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
263 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
264 | minimal symbol to mark it as a 16-bit function | |
265 | ||
f594e5e9 | 266 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 267 | |
5a89d8aa | 268 | static void |
6d82d43b AC |
269 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
270 | { | |
271 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
272 | { | |
b887350f | 273 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b | 274 | } |
5a89d8aa MS |
275 | } |
276 | ||
71b8ef93 MS |
277 | static int |
278 | msymbol_is_special (struct minimal_symbol *msym) | |
279 | { | |
b887350f | 280 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
281 | } |
282 | ||
88658117 AC |
283 | /* XFER a value from the big/little/left end of the register. |
284 | Depending on the size of the value it might occupy the entire | |
285 | register or just part of it. Make an allowance for this, aligning | |
286 | things accordingly. */ | |
287 | ||
288 | static void | |
ba32f989 DJ |
289 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
290 | int reg_num, int length, | |
870cd05e MK |
291 | enum bfd_endian endian, gdb_byte *in, |
292 | const gdb_byte *out, int buf_offset) | |
88658117 | 293 | { |
88658117 | 294 | int reg_offset = 0; |
72a155b4 UW |
295 | |
296 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
297 | /* Need to transfer the left or right part of the register, based on |
298 | the targets byte order. */ | |
88658117 AC |
299 | switch (endian) |
300 | { | |
301 | case BFD_ENDIAN_BIG: | |
72a155b4 | 302 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
303 | break; |
304 | case BFD_ENDIAN_LITTLE: | |
305 | reg_offset = 0; | |
306 | break; | |
6d82d43b | 307 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
308 | reg_offset = 0; |
309 | break; | |
310 | default: | |
e2e0b3e5 | 311 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
312 | } |
313 | if (mips_debug) | |
cb1d2653 AC |
314 | fprintf_unfiltered (gdb_stderr, |
315 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
316 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
317 | if (mips_debug && out != NULL) |
318 | { | |
319 | int i; | |
cb1d2653 | 320 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 321 | for (i = 0; i < length; i++) |
cb1d2653 | 322 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
323 | } |
324 | if (in != NULL) | |
6d82d43b AC |
325 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
326 | in + buf_offset); | |
88658117 | 327 | if (out != NULL) |
6d82d43b AC |
328 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
329 | out + buf_offset); | |
88658117 AC |
330 | if (mips_debug && in != NULL) |
331 | { | |
332 | int i; | |
cb1d2653 | 333 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 334 | for (i = 0; i < length; i++) |
cb1d2653 | 335 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
336 | } |
337 | if (mips_debug) | |
338 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
339 | } | |
340 | ||
dd824b04 DJ |
341 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
342 | compatiblity mode. A return value of 1 means that we have | |
343 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
344 | ||
345 | static int | |
9c9acae0 | 346 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 347 | { |
72a155b4 | 348 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
349 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
350 | meaningful. */ | |
72a155b4 | 351 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
352 | return 0; |
353 | ||
354 | #if 0 | |
355 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
356 | in all the places we deal with FP registers. PR gdb/413. */ | |
357 | /* Otherwise check the FR bit in the status register - it controls | |
358 | the FP compatiblity mode. If it is clear we are in compatibility | |
359 | mode. */ | |
9c9acae0 | 360 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
361 | return 1; |
362 | #endif | |
361d1df0 | 363 | |
dd824b04 DJ |
364 | return 0; |
365 | } | |
366 | ||
7a292a7a | 367 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 368 | |
74ed0bb4 | 369 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 370 | |
a14ed312 | 371 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 372 | |
025bb325 | 373 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
374 | |
375 | static struct cmd_list_element *setmipscmdlist = NULL; | |
376 | static struct cmd_list_element *showmipscmdlist = NULL; | |
377 | ||
5e2e9765 KB |
378 | /* Integer registers 0 thru 31 are handled explicitly by |
379 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 380 | are listed in the following tables. */ |
691c0433 | 381 | |
6d82d43b AC |
382 | enum |
383 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
384 | |
385 | /* Generic MIPS. */ | |
386 | ||
387 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
388 | "sr", "lo", "hi", "bad", "cause", "pc", |
389 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
390 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
391 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
392 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 393 | "fsr", "fir", |
691c0433 AC |
394 | }; |
395 | ||
396 | /* Names of IDT R3041 registers. */ | |
397 | ||
398 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
399 | "sr", "lo", "hi", "bad", "cause", "pc", |
400 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
401 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
402 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
403 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
404 | "fsr", "fir", "", /*"fp" */ "", | |
405 | "", "", "bus", "ccfg", "", "", "", "", | |
406 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
407 | }; |
408 | ||
409 | /* Names of tx39 registers. */ | |
410 | ||
411 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
412 | "sr", "lo", "hi", "bad", "cause", "pc", |
413 | "", "", "", "", "", "", "", "", | |
414 | "", "", "", "", "", "", "", "", | |
415 | "", "", "", "", "", "", "", "", | |
416 | "", "", "", "", "", "", "", "", | |
417 | "", "", "", "", | |
418 | "", "", "", "", "", "", "", "", | |
1faeff08 | 419 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
420 | }; |
421 | ||
422 | /* Names of IRIX registers. */ | |
423 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
424 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
425 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
426 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
427 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
428 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
429 | }; |
430 | ||
44099a67 | 431 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
432 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
433 | "sr", "lo", "hi", "bad", "cause", "pc", | |
434 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
435 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
436 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
437 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
438 | "fsr", "fir" | |
439 | }; | |
440 | ||
cce74817 | 441 | |
5e2e9765 | 442 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 443 | static const char * |
d93859e2 | 444 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 445 | { |
d93859e2 | 446 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
447 | /* GPR names for all ABIs other than n32/n64. */ |
448 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
449 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
450 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
451 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
452 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
453 | }; |
454 | ||
455 | /* GPR names for n32 and n64 ABIs. */ | |
456 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
457 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
458 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
459 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
460 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
461 | }; |
462 | ||
d93859e2 | 463 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 464 | |
f57d151a | 465 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
466 | but then don't make the raw register names visible. This (upper) |
467 | range of user visible register numbers are the pseudo-registers. | |
468 | ||
469 | This approach was adopted accommodate the following scenario: | |
470 | It is possible to debug a 64-bit device using a 32-bit | |
471 | programming model. In such instances, the raw registers are | |
472 | configured to be 64-bits wide, while the pseudo registers are | |
473 | configured to be 32-bits wide. The registers that the user | |
474 | sees - the pseudo registers - match the users expectations | |
475 | given the programming model being used. */ | |
d93859e2 UW |
476 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
477 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
478 | return ""; |
479 | ||
5e2e9765 KB |
480 | /* The MIPS integer registers are always mapped from 0 to 31. The |
481 | names of the registers (which reflects the conventions regarding | |
482 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 483 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
484 | { |
485 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 486 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 487 | else |
a4b8ebc8 | 488 | return mips_gpr_names[rawnum]; |
5e2e9765 | 489 | } |
d93859e2 UW |
490 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
491 | return tdesc_register_name (gdbarch, rawnum); | |
492 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
493 | { |
494 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
495 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
496 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
497 | return ""; | |
691c0433 | 498 | } |
5e2e9765 KB |
499 | else |
500 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 501 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 502 | } |
5e2e9765 | 503 | |
a4b8ebc8 | 504 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 505 | |
a4b8ebc8 AC |
506 | static int |
507 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
508 | struct reggroup *reggroup) | |
509 | { | |
510 | int vector_p; | |
511 | int float_p; | |
512 | int raw_p; | |
72a155b4 UW |
513 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
514 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
515 | if (reggroup == all_reggroup) |
516 | return pseudo; | |
517 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
518 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
519 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
520 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
521 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
522 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
523 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
524 | return 0; |
525 | if (reggroup == float_reggroup) | |
526 | return float_p && pseudo; | |
527 | if (reggroup == vector_reggroup) | |
528 | return vector_p && pseudo; | |
529 | if (reggroup == general_reggroup) | |
530 | return (!vector_p && !float_p) && pseudo; | |
531 | /* Save the pseudo registers. Need to make certain that any code | |
532 | extracting register values from a saved register cache also uses | |
533 | pseudo registers. */ | |
534 | if (reggroup == save_reggroup) | |
535 | return raw_p && pseudo; | |
536 | /* Restore the same pseudo register. */ | |
537 | if (reggroup == restore_reggroup) | |
538 | return raw_p && pseudo; | |
6d82d43b | 539 | return 0; |
a4b8ebc8 AC |
540 | } |
541 | ||
f8b73d13 DJ |
542 | /* Return the groups that a MIPS register can be categorised into. |
543 | This version is only used if we have a target description which | |
544 | describes real registers (and their groups). */ | |
545 | ||
546 | static int | |
547 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
548 | struct reggroup *reggroup) | |
549 | { | |
550 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
551 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
552 | int ret; | |
553 | ||
554 | /* Only save, restore, and display the pseudo registers. Need to | |
555 | make certain that any code extracting register values from a | |
556 | saved register cache also uses pseudo registers. | |
557 | ||
558 | Note: saving and restoring the pseudo registers is slightly | |
559 | strange; if we have 64 bits, we should save and restore all | |
560 | 64 bits. But this is hard and has little benefit. */ | |
561 | if (!pseudo) | |
562 | return 0; | |
563 | ||
564 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
565 | if (ret != -1) | |
566 | return ret; | |
567 | ||
568 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
569 | } | |
570 | ||
a4b8ebc8 | 571 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 572 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 573 | registers. Take care of alignment and size problems. */ |
c5aa993b | 574 | |
05d1431c | 575 | static enum register_status |
a4b8ebc8 | 576 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 577 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 578 | { |
72a155b4 UW |
579 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
580 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
581 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 582 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 583 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
584 | else if (register_size (gdbarch, rawnum) > |
585 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 586 | { |
8bdf35dc | 587 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 588 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 589 | else |
8bdf35dc KB |
590 | { |
591 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
592 | LONGEST regval; | |
05d1431c PA |
593 | enum register_status status; |
594 | ||
595 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
596 | if (status == REG_VALID) | |
597 | store_signed_integer (buf, 4, byte_order, regval); | |
598 | return status; | |
8bdf35dc | 599 | } |
47ebcfbe AC |
600 | } |
601 | else | |
e2e0b3e5 | 602 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
603 | } |
604 | ||
605 | static void | |
6d82d43b AC |
606 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
607 | struct regcache *regcache, int cookednum, | |
47a35522 | 608 | const gdb_byte *buf) |
a4b8ebc8 | 609 | { |
72a155b4 UW |
610 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
611 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
612 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 613 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 614 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
615 | else if (register_size (gdbarch, rawnum) > |
616 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 617 | { |
8bdf35dc | 618 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
619 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
620 | else | |
8bdf35dc KB |
621 | { |
622 | /* Sign extend the shortened version of the register prior | |
623 | to placing it in the raw register. This is required for | |
624 | some mips64 parts in order to avoid unpredictable behavior. */ | |
625 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
626 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
627 | regcache_raw_write_signed (regcache, rawnum, regval); | |
628 | } | |
47ebcfbe AC |
629 | } |
630 | else | |
e2e0b3e5 | 631 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 632 | } |
c5aa993b | 633 | |
175ff332 HZ |
634 | static int |
635 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
636 | struct agent_expr *ax, int reg) | |
637 | { | |
638 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
639 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
640 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
641 | ||
642 | ax_reg_mask (ax, rawnum); | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
647 | static int | |
648 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
649 | struct agent_expr *ax, int reg) | |
650 | { | |
651 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
652 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
653 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
654 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
655 | { | |
656 | ax_reg (ax, rawnum); | |
657 | ||
658 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
659 | { | |
660 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
661 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
662 | { | |
663 | ax_const_l (ax, 32); | |
664 | ax_simple (ax, aop_lsh); | |
665 | } | |
666 | ax_const_l (ax, 32); | |
667 | ax_simple (ax, aop_rsh_signed); | |
668 | } | |
669 | } | |
670 | else | |
671 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
c906108c | 676 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 677 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
678 | |
679 | /* Heuristic_proc_start may hunt through the text section for a long | |
680 | time across a 2400 baud serial line. Allows the user to limit this | |
681 | search. */ | |
682 | ||
683 | static unsigned int heuristic_fence_post = 0; | |
684 | ||
46cd78fb | 685 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
686 | register N. NOTE: This defines the pseudo register type so need to |
687 | rebuild the architecture vector. */ | |
43e526b9 JM |
688 | |
689 | static int mips64_transfers_32bit_regs_p = 0; | |
690 | ||
719ec221 AC |
691 | static void |
692 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
693 | struct cmd_list_element *c) | |
43e526b9 | 694 | { |
719ec221 AC |
695 | struct gdbarch_info info; |
696 | gdbarch_info_init (&info); | |
697 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
698 | instead of relying on globals. Doing that would let generic code | |
699 | handle the search for this specific architecture. */ | |
700 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 701 | { |
719ec221 | 702 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 703 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 704 | } |
a4b8ebc8 AC |
705 | } |
706 | ||
47ebcfbe | 707 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 708 | |
ee51a8c7 KB |
709 | /* This predicate tests for the case of an 8 byte floating point |
710 | value that is being transferred to or from a pair of floating point | |
711 | registers each of which are (or are considered to be) only 4 bytes | |
712 | wide. */ | |
ff2e87ac | 713 | static int |
ee51a8c7 KB |
714 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
715 | struct type *type) | |
ff2e87ac | 716 | { |
0abe36f5 MD |
717 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
718 | && register_size (gdbarch, regnum) == 4 | |
719 | && (regnum % gdbarch_num_regs (gdbarch)) | |
720 | >= mips_regnum (gdbarch)->fp0 | |
721 | && (regnum % gdbarch_num_regs (gdbarch)) | |
722 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 723 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
724 | } |
725 | ||
ee51a8c7 KB |
726 | /* This predicate tests for the case of a value of less than 8 |
727 | bytes in width that is being transfered to or from an 8 byte | |
728 | general purpose register. */ | |
729 | static int | |
730 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
731 | struct type *type) | |
732 | { | |
733 | int num_regs = gdbarch_num_regs (gdbarch); | |
734 | ||
735 | return (register_size (gdbarch, regnum) == 8 | |
736 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
737 | && TYPE_LENGTH (type) < 8); | |
738 | } | |
739 | ||
740 | static int | |
025bb325 MS |
741 | mips_convert_register_p (struct gdbarch *gdbarch, |
742 | int regnum, struct type *type) | |
ee51a8c7 KB |
743 | { |
744 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
745 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
746 | } | |
747 | ||
8dccd430 | 748 | static int |
ff2e87ac | 749 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
750 | struct type *type, gdb_byte *to, |
751 | int *optimizedp, int *unavailablep) | |
102182a9 | 752 | { |
ee51a8c7 KB |
753 | struct gdbarch *gdbarch = get_frame_arch (frame); |
754 | ||
755 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
756 | { | |
757 | get_frame_register (frame, regnum + 0, to + 4); | |
758 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
759 | |
760 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
761 | optimizedp, unavailablep)) | |
762 | return 0; | |
763 | ||
764 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
765 | optimizedp, unavailablep)) | |
766 | return 0; | |
767 | *optimizedp = *unavailablep = 0; | |
768 | return 1; | |
ee51a8c7 KB |
769 | } |
770 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
771 | { | |
772 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
773 | CORE_ADDR offset; |
774 | ||
775 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
776 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
777 | optimizedp, unavailablep)) | |
778 | return 0; | |
779 | ||
780 | *optimizedp = *unavailablep = 0; | |
781 | return 1; | |
ee51a8c7 KB |
782 | } |
783 | else | |
784 | { | |
785 | internal_error (__FILE__, __LINE__, | |
786 | _("mips_register_to_value: unrecognized case")); | |
787 | } | |
102182a9 MS |
788 | } |
789 | ||
42c466d7 | 790 | static void |
ff2e87ac | 791 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 792 | struct type *type, const gdb_byte *from) |
102182a9 | 793 | { |
ee51a8c7 KB |
794 | struct gdbarch *gdbarch = get_frame_arch (frame); |
795 | ||
796 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
797 | { | |
798 | put_frame_register (frame, regnum + 0, from + 4); | |
799 | put_frame_register (frame, regnum + 1, from + 0); | |
800 | } | |
801 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
802 | { | |
803 | gdb_byte fill[8]; | |
804 | int len = TYPE_LENGTH (type); | |
805 | ||
806 | /* Sign extend values, irrespective of type, that are stored to | |
807 | a 64-bit general purpose register. (32-bit unsigned values | |
808 | are stored as signed quantities within a 64-bit register. | |
809 | When performing an operation, in compiled code, that combines | |
810 | a 32-bit unsigned value with a signed 64-bit value, a type | |
811 | conversion is first performed that zeroes out the high 32 bits.) */ | |
812 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
813 | { | |
814 | if (from[0] & 0x80) | |
815 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
816 | else | |
817 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
818 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
819 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
820 | } | |
821 | else | |
822 | { | |
823 | if (from[len-1] & 0x80) | |
824 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
825 | else | |
826 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
827 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
828 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
829 | } | |
830 | } | |
831 | else | |
832 | { | |
833 | internal_error (__FILE__, __LINE__, | |
834 | _("mips_value_to_register: unrecognized case")); | |
835 | } | |
102182a9 MS |
836 | } |
837 | ||
a4b8ebc8 AC |
838 | /* Return the GDB type object for the "standard" data type of data in |
839 | register REG. */ | |
78fde5f8 KB |
840 | |
841 | static struct type * | |
a4b8ebc8 AC |
842 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
843 | { | |
72a155b4 UW |
844 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
845 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
846 | && (regnum % gdbarch_num_regs (gdbarch)) | |
847 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 848 | { |
5ef80fb0 | 849 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 850 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 851 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 852 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 853 | else |
27067745 | 854 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 855 | } |
72a155b4 | 856 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
857 | { |
858 | /* The raw or ISA registers. These are all sized according to | |
859 | the ISA regsize. */ | |
860 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 861 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 862 | else |
df4df182 | 863 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 864 | } |
78fde5f8 | 865 | else |
d5ac5a39 | 866 | { |
1faeff08 MR |
867 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
868 | ||
d5ac5a39 AC |
869 | /* The cooked or ABI registers. These are sized according to |
870 | the ABI (with a few complications). */ | |
1faeff08 MR |
871 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
872 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
873 | return builtin_type (gdbarch)->builtin_int32; | |
874 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX | |
875 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
876 | && rawnum >= MIPS_FIRST_EMBED_REGNUM | |
877 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
878 | /* The pseudo/cooked view of the embedded registers is always |
879 | 32-bit. The raw view is handled below. */ | |
df4df182 | 880 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
881 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
882 | /* The target, while possibly using a 64-bit register buffer, | |
883 | is only transfering 32-bits of each integer register. | |
884 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 885 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
886 | else if (mips_abi_regsize (gdbarch) == 4) |
887 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
888 | 32- or 64-bit). */ | |
df4df182 | 889 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
890 | else |
891 | /* 64-bit ABI. */ | |
df4df182 | 892 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 893 | } |
78fde5f8 KB |
894 | } |
895 | ||
f8b73d13 DJ |
896 | /* Return the GDB type for the pseudo register REGNUM, which is the |
897 | ABI-level view. This function is only called if there is a target | |
898 | description which includes registers, so we know precisely the | |
899 | types of hardware registers. */ | |
900 | ||
901 | static struct type * | |
902 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
903 | { | |
904 | const int num_regs = gdbarch_num_regs (gdbarch); | |
905 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
906 | int rawnum = regnum % num_regs; | |
907 | struct type *rawtype; | |
908 | ||
909 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
910 | ||
911 | /* Absent registers are still absent. */ | |
912 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
913 | if (TYPE_LENGTH (rawtype) == 0) | |
914 | return rawtype; | |
915 | ||
1faeff08 MR |
916 | if (rawnum >= mips_regnum (gdbarch)->fp0 |
917 | && rawnum < mips_regnum (gdbarch)->fp0 + 32) | |
f8b73d13 DJ |
918 | /* Present the floating point registers however the hardware did; |
919 | do not try to convert between FPU layouts. */ | |
920 | return rawtype; | |
921 | ||
f8b73d13 DJ |
922 | /* Use pointer types for registers if we can. For n32 we can not, |
923 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
924 | if (mips_abi_regsize (gdbarch) |
925 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 926 | { |
1faeff08 MR |
927 | if (rawnum == MIPS_SP_REGNUM |
928 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 929 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 930 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 931 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
932 | } |
933 | ||
934 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
935 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
936 | || rawnum == mips_regnum (gdbarch)->lo | |
937 | || rawnum == mips_regnum (gdbarch)->hi | |
938 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
939 | || rawnum == mips_regnum (gdbarch)->cause | |
940 | || rawnum == mips_regnum (gdbarch)->pc | |
941 | || (mips_regnum (gdbarch)->dspacc != -1 | |
942 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
943 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 944 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 945 | |
1faeff08 MR |
946 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
947 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
948 | && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 | |
949 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
950 | { | |
951 | /* The pseudo/cooked view of embedded registers is always | |
952 | 32-bit, even if the target transfers 64-bit values for them. | |
953 | New targets relying on XML descriptions should only transfer | |
954 | the necessary 32 bits, but older versions of GDB expected 64, | |
955 | so allow the target to provide 64 bits without interfering | |
956 | with the displayed type. */ | |
957 | return builtin_type (gdbarch)->builtin_int32; | |
958 | } | |
959 | ||
f8b73d13 DJ |
960 | /* For all other registers, pass through the hardware type. */ |
961 | return rawtype; | |
962 | } | |
bcb0cc15 | 963 | |
025bb325 | 964 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 965 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
966 | |
967 | static int | |
480d3dd2 | 968 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
969 | { |
970 | switch (mask_address_var) | |
971 | { | |
7f19b9a2 | 972 | case AUTO_BOOLEAN_TRUE: |
4014092b | 973 | return 1; |
7f19b9a2 | 974 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
975 | return 0; |
976 | break; | |
7f19b9a2 | 977 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 978 | return tdep->default_mask_address_p; |
4014092b | 979 | default: |
025bb325 MS |
980 | internal_error (__FILE__, __LINE__, |
981 | _("mips_mask_address_p: bad switch")); | |
4014092b | 982 | return -1; |
361d1df0 | 983 | } |
4014092b AC |
984 | } |
985 | ||
986 | static void | |
08546159 AC |
987 | show_mask_address (struct ui_file *file, int from_tty, |
988 | struct cmd_list_element *c, const char *value) | |
4014092b | 989 | { |
1cf3db46 | 990 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
991 | |
992 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
993 | switch (mask_address_var) |
994 | { | |
7f19b9a2 | 995 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
996 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
997 | break; | |
7f19b9a2 | 998 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
999 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1000 | break; | |
7f19b9a2 | 1001 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1002 | printf_filtered |
1003 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1004 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1005 | break; |
1006 | default: | |
e2e0b3e5 | 1007 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1008 | break; |
361d1df0 | 1009 | } |
4014092b | 1010 | } |
c906108c | 1011 | |
c906108c SS |
1012 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1013 | ||
0fe7e7c8 AC |
1014 | int |
1015 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
1016 | { |
1017 | struct minimal_symbol *sym; | |
1018 | ||
91912e4d MR |
1019 | /* A flag indicating that this is a MIPS16 function is stored by |
1020 | elfread.c in the high bit of the info field. Use this to decide | |
1021 | if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of | |
1022 | the address is set, assume this is a MIPS16 address. */ | |
c906108c SS |
1023 | sym = lookup_minimal_symbol_by_pc (memaddr); |
1024 | if (sym) | |
71b8ef93 | 1025 | return msymbol_is_special (sym); |
c906108c | 1026 | else |
91912e4d | 1027 | return is_mips16_addr (memaddr); |
c906108c SS |
1028 | } |
1029 | ||
b2fa5097 | 1030 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1031 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1032 | |
1033 | static CORE_ADDR | |
61a1198a | 1034 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1035 | { |
61a1198a UW |
1036 | ULONGEST pc; |
1037 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
1038 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
930bd0e0 KB |
1039 | if (is_mips16_addr (pc)) |
1040 | pc = unmake_mips16_addr (pc); | |
61a1198a | 1041 | return pc; |
b6cb9035 AC |
1042 | } |
1043 | ||
58dfe9ff AC |
1044 | static CORE_ADDR |
1045 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1046 | { | |
930bd0e0 KB |
1047 | ULONGEST pc; |
1048 | ||
1049 | pc = frame_unwind_register_signed | |
1050 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
1051 | if (is_mips16_addr (pc)) | |
1052 | pc = unmake_mips16_addr (pc); | |
1053 | return pc; | |
edfae063 AC |
1054 | } |
1055 | ||
30244cd8 UW |
1056 | static CORE_ADDR |
1057 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1058 | { | |
72a155b4 UW |
1059 | return frame_unwind_register_signed |
1060 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1061 | } |
1062 | ||
b8a22b94 | 1063 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1064 | dummy frame. The frame ID's base needs to match the TOS value |
1065 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1066 | breakpoint. */ | |
1067 | ||
1068 | static struct frame_id | |
b8a22b94 | 1069 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1070 | { |
f57d151a | 1071 | return frame_id_build |
b8a22b94 DJ |
1072 | (get_frame_register_signed (this_frame, |
1073 | gdbarch_num_regs (gdbarch) | |
1074 | + MIPS_SP_REGNUM), | |
1075 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1076 | } |
1077 | ||
b6cb9035 | 1078 | static void |
61a1198a | 1079 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1080 | { |
61a1198a | 1081 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
930bd0e0 KB |
1082 | if (mips_pc_is_mips16 (pc)) |
1083 | regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc)); | |
1084 | else | |
1085 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 1086 | } |
c906108c | 1087 | |
c906108c SS |
1088 | /* Fetch and return instruction from the specified location. If the PC |
1089 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
1090 | ||
d37cca3d | 1091 | static ULONGEST |
e17a4113 | 1092 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 1093 | { |
e17a4113 | 1094 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1095 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1096 | int instlen; |
1097 | int status; | |
1098 | ||
0fe7e7c8 | 1099 | if (mips_pc_is_mips16 (addr)) |
c906108c | 1100 | { |
95ac2dcf | 1101 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 1102 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1103 | } |
1104 | else | |
95ac2dcf | 1105 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 1106 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
1107 | if (status) |
1108 | memory_error (status, addr); | |
e17a4113 | 1109 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1110 | } |
1111 | ||
025bb325 | 1112 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1113 | #define mips32_op(x) (x >> 26) |
1114 | #define itype_op(x) (x >> 26) | |
1115 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1116 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1117 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1118 | |
e135b889 DJ |
1119 | #define jtype_op(x) (x >> 26) |
1120 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1121 | |
e135b889 DJ |
1122 | #define rtype_op(x) (x >> 26) |
1123 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1124 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1125 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1126 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1127 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1128 | |
06987e64 MK |
1129 | static LONGEST |
1130 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1131 | { |
06987e64 | 1132 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1133 | } |
1134 | ||
a385295e MR |
1135 | /* Determine the address of the next instruction executed after the INST |
1136 | floating condition branch instruction at PC. COUNT specifies the | |
1137 | number of the floating condition bits tested by the branch. */ | |
1138 | ||
1139 | static CORE_ADDR | |
1140 | mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1141 | ULONGEST inst, CORE_ADDR pc, int count) | |
1142 | { | |
1143 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1144 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1145 | int tf = itype_rt (inst) & 1; | |
1146 | int mask = (1 << count) - 1; | |
1147 | ULONGEST fcs; | |
1148 | int cond; | |
1149 | ||
1150 | if (fcsr == -1) | |
1151 | /* No way to handle; it'll most likely trap anyway. */ | |
1152 | return pc; | |
1153 | ||
1154 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1155 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1156 | ||
1157 | if (((cond >> cnum) & mask) != mask * !tf) | |
1158 | pc += mips32_relative_offset (inst); | |
1159 | else | |
1160 | pc += 4; | |
1161 | ||
1162 | return pc; | |
1163 | } | |
1164 | ||
f49e4e6d MS |
1165 | /* Determine where to set a single step breakpoint while considering |
1166 | branch prediction. */ | |
5a89d8aa | 1167 | static CORE_ADDR |
0b1b3e42 | 1168 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1169 | { |
e17a4113 | 1170 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1171 | unsigned long inst; |
1172 | int op; | |
e17a4113 | 1173 | inst = mips_fetch_instruction (gdbarch, pc); |
025bb325 MS |
1174 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1175 | instruction. */ | |
c5aa993b | 1176 | { |
e135b889 | 1177 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1178 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1179 | { |
e135b889 | 1180 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1181 | switch (op) |
1182 | { | |
e135b889 DJ |
1183 | case 0: /* BEQL */ |
1184 | goto equal_branch; | |
1185 | case 1: /* BNEL */ | |
1186 | goto neq_branch; | |
1187 | case 2: /* BLEZL */ | |
1188 | goto less_branch; | |
313628cc | 1189 | case 3: /* BGTZL */ |
e135b889 | 1190 | goto greater_branch; |
c5aa993b JM |
1191 | default: |
1192 | pc += 4; | |
c906108c SS |
1193 | } |
1194 | } | |
e135b889 | 1195 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1196 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
1197 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
1198 | else if (itype_op (inst) == 17 && itype_rs (inst) == 9 | |
1199 | && (itype_rt (inst) & 2) == 0) | |
1200 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
1201 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); | |
1202 | else if (itype_op (inst) == 17 && itype_rs (inst) == 10 | |
1203 | && (itype_rt (inst) & 2) == 0) | |
1204 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
1205 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); | |
9e8da49c MR |
1206 | else if (itype_op (inst) == 29) |
1207 | /* JALX: 011101 */ | |
1208 | /* The new PC will be alternate mode. */ | |
1209 | { | |
1210 | unsigned long reg; | |
1211 | ||
1212 | reg = jtype_target (inst) << 2; | |
1213 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1214 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1215 | } | |
c5aa993b | 1216 | else |
025bb325 | 1217 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1218 | } |
1219 | else | |
025bb325 | 1220 | { /* This gets way messy. */ |
c5aa993b | 1221 | |
025bb325 MS |
1222 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
1223 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | |
c906108c | 1224 | { |
c5aa993b JM |
1225 | case 0: /* SPECIAL */ |
1226 | op = rtype_funct (inst); | |
1227 | switch (op) | |
1228 | { | |
1229 | case 8: /* JR */ | |
1230 | case 9: /* JALR */ | |
025bb325 | 1231 | /* Set PC to that address. */ |
0b1b3e42 | 1232 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1233 | break; |
e38d4e1a DJ |
1234 | case 12: /* SYSCALL */ |
1235 | { | |
1236 | struct gdbarch_tdep *tdep; | |
1237 | ||
1238 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1239 | if (tdep->syscall_next_pc != NULL) | |
1240 | pc = tdep->syscall_next_pc (frame); | |
1241 | else | |
1242 | pc += 4; | |
1243 | } | |
1244 | break; | |
c5aa993b JM |
1245 | default: |
1246 | pc += 4; | |
1247 | } | |
1248 | ||
6d82d43b | 1249 | break; /* end SPECIAL */ |
025bb325 | 1250 | case 1: /* REGIMM */ |
c906108c | 1251 | { |
e135b889 DJ |
1252 | op = itype_rt (inst); /* branch condition */ |
1253 | switch (op) | |
c906108c | 1254 | { |
c5aa993b | 1255 | case 0: /* BLTZ */ |
e135b889 DJ |
1256 | case 2: /* BLTZL */ |
1257 | case 16: /* BLTZAL */ | |
c5aa993b | 1258 | case 18: /* BLTZALL */ |
c906108c | 1259 | less_branch: |
0b1b3e42 | 1260 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1261 | pc += mips32_relative_offset (inst) + 4; |
1262 | else | |
1263 | pc += 8; /* after the delay slot */ | |
1264 | break; | |
e135b889 | 1265 | case 1: /* BGEZ */ |
c5aa993b JM |
1266 | case 3: /* BGEZL */ |
1267 | case 17: /* BGEZAL */ | |
1268 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1269 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1270 | pc += mips32_relative_offset (inst) + 4; |
1271 | else | |
1272 | pc += 8; /* after the delay slot */ | |
1273 | break; | |
a385295e MR |
1274 | case 0x1c: /* BPOSGE32 */ |
1275 | case 0x1e: /* BPOSGE64 */ | |
1276 | pc += 4; | |
1277 | if (itype_rs (inst) == 0) | |
1278 | { | |
1279 | unsigned int pos = (op & 2) ? 64 : 32; | |
1280 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1281 | ||
1282 | if (dspctl == -1) | |
1283 | /* No way to handle; it'll most likely trap anyway. */ | |
1284 | break; | |
1285 | ||
1286 | if ((get_frame_register_unsigned (frame, | |
1287 | dspctl) & 0x7f) >= pos) | |
1288 | pc += mips32_relative_offset (inst); | |
1289 | else | |
1290 | pc += 4; | |
1291 | } | |
1292 | break; | |
e135b889 | 1293 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1294 | default: |
1295 | pc += 4; | |
c906108c SS |
1296 | } |
1297 | } | |
6d82d43b | 1298 | break; /* end REGIMM */ |
c5aa993b JM |
1299 | case 2: /* J */ |
1300 | case 3: /* JAL */ | |
1301 | { | |
1302 | unsigned long reg; | |
1303 | reg = jtype_target (inst) << 2; | |
025bb325 | 1304 | /* Upper four bits get never changed... */ |
5b652102 | 1305 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1306 | } |
c5aa993b | 1307 | break; |
e135b889 | 1308 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1309 | equal_branch: |
0b1b3e42 UW |
1310 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1311 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1312 | pc += mips32_relative_offset (inst) + 4; |
1313 | else | |
1314 | pc += 8; | |
1315 | break; | |
e135b889 | 1316 | case 5: /* BNE, BNEL */ |
c5aa993b | 1317 | neq_branch: |
0b1b3e42 UW |
1318 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1319 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1320 | pc += mips32_relative_offset (inst) + 4; |
1321 | else | |
1322 | pc += 8; | |
1323 | break; | |
e135b889 | 1324 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1325 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1326 | pc += mips32_relative_offset (inst) + 4; |
1327 | else | |
1328 | pc += 8; | |
1329 | break; | |
1330 | case 7: | |
e135b889 DJ |
1331 | default: |
1332 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1333 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1334 | pc += mips32_relative_offset (inst) + 4; |
1335 | else | |
1336 | pc += 8; | |
1337 | break; | |
c5aa993b JM |
1338 | } /* switch */ |
1339 | } /* else */ | |
1340 | return pc; | |
1341 | } /* mips32_next_pc */ | |
c906108c SS |
1342 | |
1343 | /* Decoding the next place to set a breakpoint is irregular for the | |
025bb325 MS |
1344 | mips 16 variant, but fortunately, there fewer instructions. We have |
1345 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1346 | 32 bit instructions. We dont want to set a single step instruction | |
1347 | on the extend instruction either. */ | |
c906108c SS |
1348 | |
1349 | /* Lots of mips16 instruction formats */ | |
1350 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1351 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1352 | enum mips16_inst_fmts |
1353 | { | |
c5aa993b JM |
1354 | itype, /* 0 immediate 5,10 */ |
1355 | ritype, /* 1 5,3,8 */ | |
1356 | rrtype, /* 2 5,3,3,5 */ | |
1357 | rritype, /* 3 5,3,3,5 */ | |
1358 | rrrtype, /* 4 5,3,3,3,2 */ | |
1359 | rriatype, /* 5 5,3,3,1,4 */ | |
1360 | shifttype, /* 6 5,3,3,3,2 */ | |
1361 | i8type, /* 7 5,3,8 */ | |
1362 | i8movtype, /* 8 5,3,3,5 */ | |
1363 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1364 | i64type, /* 10 5,3,8 */ | |
1365 | ri64type, /* 11 5,3,3,5 */ | |
1366 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1367 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1368 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1369 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1370 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1371 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1372 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1373 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1374 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1375 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1376 | }; | |
12f02c2a | 1377 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 1378 | then, only the fields which are involved in instruction extension. */ |
c906108c | 1379 | struct upk_mips16 |
6d82d43b AC |
1380 | { |
1381 | CORE_ADDR offset; | |
025bb325 | 1382 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
1383 | unsigned int regy; |
1384 | }; | |
c906108c SS |
1385 | |
1386 | ||
12f02c2a | 1387 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1388 | for the bits which make up the immediate extension. */ |
c906108c | 1389 | |
12f02c2a AC |
1390 | static CORE_ADDR |
1391 | extended_offset (unsigned int extension) | |
c906108c | 1392 | { |
12f02c2a | 1393 | CORE_ADDR value; |
130854df | 1394 | |
4c2051c6 | 1395 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 1396 | value = value << 6; |
4c2051c6 | 1397 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 1398 | value = value << 5; |
130854df MR |
1399 | value |= extension & 0x1f; /* Extract 4:0. */ |
1400 | ||
c5aa993b | 1401 | return value; |
c906108c SS |
1402 | } |
1403 | ||
1404 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1405 | instruction. It won't malfunction, but why make excess remote memory |
1406 | references? If the immediate operands get sign extended or something, | |
1407 | do it after the extension is performed. */ | |
c906108c | 1408 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1409 | when the offset is to be used in relative addressing. */ |
c906108c | 1410 | |
12f02c2a | 1411 | static unsigned int |
e17a4113 | 1412 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1413 | { |
e17a4113 | 1414 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1415 | gdb_byte buf[8]; |
025bb325 | 1416 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
c5aa993b | 1417 | target_read_memory (pc, buf, 2); |
e17a4113 | 1418 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1419 | } |
1420 | ||
1421 | static void | |
e17a4113 | 1422 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1423 | unsigned int extension, |
1424 | unsigned int inst, | |
6d82d43b | 1425 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1426 | { |
12f02c2a AC |
1427 | CORE_ADDR offset; |
1428 | int regx; | |
1429 | int regy; | |
1430 | switch (insn_format) | |
c906108c | 1431 | { |
c5aa993b | 1432 | case itype: |
c906108c | 1433 | { |
12f02c2a AC |
1434 | CORE_ADDR value; |
1435 | if (extension) | |
c5aa993b | 1436 | { |
4c2051c6 MR |
1437 | value = extended_offset ((extension << 16) | inst); |
1438 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
1439 | } |
1440 | else | |
c5aa993b | 1441 | { |
12f02c2a | 1442 | value = inst & 0x7ff; |
4c2051c6 | 1443 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 1444 | } |
12f02c2a AC |
1445 | offset = value; |
1446 | regx = -1; | |
1447 | regy = -1; | |
c906108c | 1448 | } |
c5aa993b JM |
1449 | break; |
1450 | case ritype: | |
1451 | case i8type: | |
025bb325 | 1452 | { /* A register identifier and an offset. */ |
c906108c | 1453 | /* Most of the fields are the same as I type but the |
025bb325 | 1454 | immediate value is of a different length. */ |
12f02c2a AC |
1455 | CORE_ADDR value; |
1456 | if (extension) | |
c906108c | 1457 | { |
4c2051c6 MR |
1458 | value = extended_offset ((extension << 16) | inst); |
1459 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 1460 | } |
c5aa993b JM |
1461 | else |
1462 | { | |
4c2051c6 MR |
1463 | value = inst & 0xff; /* 8 bits */ |
1464 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 1465 | } |
12f02c2a | 1466 | offset = value; |
4c2051c6 | 1467 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 1468 | regy = -1; |
c5aa993b | 1469 | break; |
c906108c | 1470 | } |
c5aa993b | 1471 | case jalxtype: |
c906108c | 1472 | { |
c5aa993b | 1473 | unsigned long value; |
12f02c2a AC |
1474 | unsigned int nexthalf; |
1475 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1476 | value = value << 16; |
025bb325 MS |
1477 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit |
1478 | still set. */ | |
c5aa993b | 1479 | value |= nexthalf; |
12f02c2a AC |
1480 | offset = value; |
1481 | regx = -1; | |
1482 | regy = -1; | |
c5aa993b | 1483 | break; |
c906108c SS |
1484 | } |
1485 | default: | |
e2e0b3e5 | 1486 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1487 | } |
12f02c2a AC |
1488 | upk->offset = offset; |
1489 | upk->regx = regx; | |
1490 | upk->regy = regy; | |
c906108c SS |
1491 | } |
1492 | ||
1493 | ||
c5aa993b JM |
1494 | static CORE_ADDR |
1495 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1496 | { |
5b652102 | 1497 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1498 | } |
1499 | ||
12f02c2a | 1500 | static CORE_ADDR |
0b1b3e42 | 1501 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1502 | unsigned int extension, unsigned int insn) |
c906108c | 1503 | { |
e17a4113 | 1504 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1505 | int op = (insn >> 11); |
1506 | switch (op) | |
c906108c | 1507 | { |
6d82d43b | 1508 | case 2: /* Branch */ |
12f02c2a AC |
1509 | { |
1510 | CORE_ADDR offset; | |
1511 | struct upk_mips16 upk; | |
e17a4113 | 1512 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
4c2051c6 | 1513 | pc += (upk.offset << 1) + 2; |
12f02c2a AC |
1514 | break; |
1515 | } | |
025bb325 MS |
1516 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
1517 | instructions. */ | |
12f02c2a AC |
1518 | { |
1519 | struct upk_mips16 upk; | |
e17a4113 | 1520 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1521 | pc = add_offset_16 (pc, upk.offset); |
1522 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 1523 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
1524 | else |
1525 | pc |= 0x01; | |
1526 | break; | |
1527 | } | |
6d82d43b | 1528 | case 4: /* beqz */ |
12f02c2a AC |
1529 | { |
1530 | struct upk_mips16 upk; | |
1531 | int reg; | |
e17a4113 | 1532 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4c2051c6 | 1533 | reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); |
12f02c2a AC |
1534 | if (reg == 0) |
1535 | pc += (upk.offset << 1) + 2; | |
1536 | else | |
1537 | pc += 2; | |
1538 | break; | |
1539 | } | |
6d82d43b | 1540 | case 5: /* bnez */ |
12f02c2a AC |
1541 | { |
1542 | struct upk_mips16 upk; | |
1543 | int reg; | |
e17a4113 | 1544 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4c2051c6 | 1545 | reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); |
12f02c2a AC |
1546 | if (reg != 0) |
1547 | pc += (upk.offset << 1) + 2; | |
1548 | else | |
1549 | pc += 2; | |
1550 | break; | |
1551 | } | |
6d82d43b | 1552 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1553 | { |
1554 | struct upk_mips16 upk; | |
1555 | int reg; | |
e17a4113 | 1556 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1557 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1558 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1559 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1560 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1561 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1562 | pc += (upk.offset << 1) + 2; | |
1563 | else | |
1564 | pc += 2; | |
1565 | break; | |
1566 | } | |
6d82d43b | 1567 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1568 | { |
1569 | struct upk_mips16 upk; | |
1570 | /* upk.fmt = rrtype; */ | |
1571 | op = insn & 0x1f; | |
1572 | if (op == 0) | |
c5aa993b | 1573 | { |
12f02c2a AC |
1574 | int reg; |
1575 | upk.regx = (insn >> 8) & 0x07; | |
1576 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 MR |
1577 | if ((upk.regy & 1) == 0) |
1578 | reg = mips16_to_32_reg[upk.regx]; | |
1579 | else | |
1580 | reg = 31; /* Function return instruction. */ | |
0b1b3e42 | 1581 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1582 | } |
12f02c2a | 1583 | else |
c5aa993b | 1584 | pc += 2; |
12f02c2a AC |
1585 | break; |
1586 | } | |
1587 | case 30: | |
1588 | /* This is an instruction extension. Fetch the real instruction | |
1589 | (which follows the extension) and decode things based on | |
025bb325 | 1590 | that. */ |
12f02c2a AC |
1591 | { |
1592 | pc += 2; | |
e17a4113 UW |
1593 | pc = extended_mips16_next_pc (frame, pc, insn, |
1594 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1595 | break; |
1596 | } | |
1597 | default: | |
1598 | { | |
1599 | pc += 2; | |
1600 | break; | |
1601 | } | |
c906108c | 1602 | } |
c5aa993b | 1603 | return pc; |
12f02c2a | 1604 | } |
c906108c | 1605 | |
5a89d8aa | 1606 | static CORE_ADDR |
0b1b3e42 | 1607 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1608 | { |
e17a4113 UW |
1609 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1610 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1611 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1612 | } |
1613 | ||
1614 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1615 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 1616 | It works by decoding the current instruction and predicting where a |
025bb325 | 1617 | branch will go. This isnt hard because all the data is available. |
ce1f96de | 1618 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1619 | static CORE_ADDR |
0b1b3e42 | 1620 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1621 | { |
91912e4d | 1622 | if (mips_pc_is_mips16 (pc)) |
0b1b3e42 | 1623 | return mips16_next_pc (frame, pc); |
c5aa993b | 1624 | else |
0b1b3e42 | 1625 | return mips32_next_pc (frame, pc); |
12f02c2a | 1626 | } |
c906108c | 1627 | |
edfae063 AC |
1628 | struct mips_frame_cache |
1629 | { | |
1630 | CORE_ADDR base; | |
1631 | struct trad_frame_saved_reg *saved_regs; | |
1632 | }; | |
1633 | ||
29639122 JB |
1634 | /* Set a register's saved stack address in temp_saved_regs. If an |
1635 | address has already been set for this register, do nothing; this | |
1636 | way we will only recognize the first save of a given register in a | |
1637 | function prologue. | |
eec63939 | 1638 | |
f57d151a UW |
1639 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1640 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1641 | Strictly speaking, only the second range is used as it is only second | |
1642 | range (the ABI instead of ISA registers) that comes into play when finding | |
1643 | saved registers in a frame. */ | |
eec63939 AC |
1644 | |
1645 | static void | |
74ed0bb4 MD |
1646 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1647 | int regnum, CORE_ADDR offset) | |
eec63939 | 1648 | { |
29639122 JB |
1649 | if (this_cache != NULL |
1650 | && this_cache->saved_regs[regnum].addr == -1) | |
1651 | { | |
74ed0bb4 MD |
1652 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1653 | = offset; | |
1654 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1655 | = offset; | |
29639122 | 1656 | } |
eec63939 AC |
1657 | } |
1658 | ||
eec63939 | 1659 | |
29639122 JB |
1660 | /* Fetch the immediate value from a MIPS16 instruction. |
1661 | If the previous instruction was an EXTEND, use it to extend | |
1662 | the upper bits of the immediate value. This is a helper function | |
1663 | for mips16_scan_prologue. */ | |
eec63939 | 1664 | |
29639122 JB |
1665 | static int |
1666 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1667 | unsigned short inst, /* current instruction */ | |
1668 | int nbits, /* number of bits in imm field */ | |
1669 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 1670 | int is_signed) /* is the imm field signed? */ |
eec63939 | 1671 | { |
29639122 | 1672 | int offset; |
eec63939 | 1673 | |
29639122 JB |
1674 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1675 | { | |
1676 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1677 | if (offset & 0x8000) /* check for negative extend */ | |
1678 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1679 | return offset | (inst & 0x1f); | |
1680 | } | |
eec63939 | 1681 | else |
29639122 JB |
1682 | { |
1683 | int max_imm = 1 << nbits; | |
1684 | int mask = max_imm - 1; | |
1685 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1686 | |
29639122 JB |
1687 | offset = inst & mask; |
1688 | if (is_signed && (offset & sign_bit)) | |
1689 | offset = 0 - (max_imm - offset); | |
1690 | return offset * scale; | |
1691 | } | |
1692 | } | |
eec63939 | 1693 | |
65596487 | 1694 | |
29639122 JB |
1695 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1696 | the associated FRAME_CACHE if not null. | |
1697 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1698 | |
29639122 | 1699 | static CORE_ADDR |
e17a4113 UW |
1700 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1701 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1702 | struct frame_info *this_frame, |
29639122 JB |
1703 | struct mips_frame_cache *this_cache) |
1704 | { | |
1705 | CORE_ADDR cur_pc; | |
025bb325 | 1706 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
1707 | CORE_ADDR sp; |
1708 | long frame_offset = 0; /* Size of stack frame. */ | |
1709 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1710 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 1711 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
1712 | unsigned inst = 0; /* current instruction */ |
1713 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1714 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1715 | int reg, offset; |
a343eb3c | 1716 | |
29639122 JB |
1717 | int extend_bytes = 0; |
1718 | int prev_extend_bytes; | |
1719 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1720 | |
29639122 | 1721 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1722 | THIS_FRAME. */ |
1723 | if (this_frame != NULL) | |
1724 | sp = get_frame_register_signed (this_frame, | |
1725 | gdbarch_num_regs (gdbarch) | |
1726 | + MIPS_SP_REGNUM); | |
29639122 JB |
1727 | else |
1728 | sp = 0; | |
eec63939 | 1729 | |
29639122 JB |
1730 | if (limit_pc > start_pc + 200) |
1731 | limit_pc = start_pc + 200; | |
eec63939 | 1732 | |
95ac2dcf | 1733 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1734 | { |
1735 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1736 | the immediate offset extension from it in mips16_get_imm. */ | |
1737 | prev_inst = inst; | |
eec63939 | 1738 | |
025bb325 | 1739 | /* Fetch and decode the instruction. */ |
e17a4113 | 1740 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1741 | |
29639122 JB |
1742 | /* Normally we ignore extend instructions. However, if it is |
1743 | not followed by a valid prologue instruction, then this | |
1744 | instruction is not part of the prologue either. We must | |
1745 | remember in this case to adjust the end_prologue_addr back | |
1746 | over the extend. */ | |
1747 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1748 | { | |
95ac2dcf | 1749 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1750 | continue; |
1751 | } | |
eec63939 | 1752 | |
29639122 JB |
1753 | prev_extend_bytes = extend_bytes; |
1754 | extend_bytes = 0; | |
eec63939 | 1755 | |
29639122 JB |
1756 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1757 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1758 | { | |
1759 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 1760 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
1761 | frame_offset -= offset; |
1762 | else | |
1763 | /* Exit loop if a positive stack adjustment is found, which | |
1764 | usually means that the stack cleanup code in the function | |
1765 | epilogue is reached. */ | |
1766 | break; | |
1767 | } | |
1768 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1769 | { | |
1770 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1771 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1772 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1773 | } |
1774 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1775 | { | |
1776 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1777 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1778 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1779 | } |
1780 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1781 | { | |
1782 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1783 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1784 | } |
1785 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1786 | { | |
1787 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1788 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1789 | } |
1790 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1791 | { | |
1792 | frame_addr = sp; | |
1793 | frame_reg = 17; | |
1794 | } | |
1795 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1796 | { | |
1797 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1798 | frame_addr = sp + offset; | |
1799 | frame_reg = 17; | |
1800 | frame_adjust = offset; | |
1801 | } | |
1802 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1803 | { | |
1804 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1805 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1806 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1807 | } |
1808 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1809 | { | |
1810 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1811 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1812 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1813 | } |
1814 | else if ((inst & 0xf81f) == 0xe809 | |
1815 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 1816 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
1817 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1818 | { | |
025bb325 | 1819 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
1820 | if (prev_extend_bytes) /* extend */ |
1821 | save_inst |= prev_inst << 16; | |
1822 | } | |
29639122 | 1823 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1824 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1825 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1826 | { | |
1827 | /* This instruction is part of the prologue, but we don't | |
1828 | need to do anything special to handle it. */ | |
1829 | } | |
1830 | else | |
1831 | { | |
1832 | /* This instruction is not an instruction typically found | |
1833 | in a prologue, so we must have reached the end of the | |
1834 | prologue. */ | |
1835 | if (end_prologue_addr == 0) | |
1836 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1837 | } | |
1838 | } | |
eec63939 | 1839 | |
29639122 JB |
1840 | /* The entry instruction is typically the first instruction in a function, |
1841 | and it stores registers at offsets relative to the value of the old SP | |
1842 | (before the prologue). But the value of the sp parameter to this | |
1843 | function is the new SP (after the prologue has been executed). So we | |
1844 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 1845 | and can calculate what the old SP must have been. */ |
29639122 JB |
1846 | if (entry_inst != 0) |
1847 | { | |
1848 | int areg_count = (entry_inst >> 8) & 7; | |
1849 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1850 | |
29639122 JB |
1851 | /* The entry instruction always subtracts 32 from the SP. */ |
1852 | frame_offset += 32; | |
1853 | ||
1854 | /* Now we can calculate what the SP must have been at the | |
1855 | start of the function prologue. */ | |
1856 | sp += frame_offset; | |
1857 | ||
1858 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1859 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1860 | { | |
74ed0bb4 | 1861 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1862 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1863 | } |
1864 | ||
1865 | /* Check if the ra register was pushed on the stack. */ | |
1866 | offset = -4; | |
1867 | if (entry_inst & 0x20) | |
1868 | { | |
74ed0bb4 | 1869 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1870 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1871 | } |
1872 | ||
1873 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1874 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1875 | { | |
74ed0bb4 | 1876 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1877 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1878 | } |
1879 | } | |
1880 | ||
2207132d MR |
1881 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1882 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1883 | size of the frame is specified as an immediate field of instruction | |
1884 | and an extended variation exists which lets additional registers and | |
1885 | frame space to be specified. The instruction always treats registers | |
1886 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1887 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1888 | { | |
1889 | static int args_table[16] = { | |
1890 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1891 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1892 | }; | |
1893 | static int astatic_table[16] = { | |
1894 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1895 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1896 | }; | |
1897 | int aregs = (save_inst >> 16) & 0xf; | |
1898 | int xsregs = (save_inst >> 24) & 0x7; | |
1899 | int args = args_table[aregs]; | |
1900 | int astatic = astatic_table[aregs]; | |
1901 | long frame_size; | |
1902 | ||
1903 | if (args < 0) | |
1904 | { | |
1905 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1906 | args = 0; | |
1907 | } | |
1908 | if (astatic < 0) | |
1909 | { | |
1910 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1911 | astatic = 0; | |
1912 | } | |
1913 | ||
1914 | /* For standard SAVE the frame size of 0 means 128. */ | |
1915 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1916 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1917 | frame_size = 16; | |
1918 | frame_size *= 8; | |
1919 | frame_offset += frame_size; | |
1920 | ||
1921 | /* Now we can calculate what the SP must have been at the | |
1922 | start of the function prologue. */ | |
1923 | sp += frame_offset; | |
1924 | ||
1925 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1926 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1927 | { | |
74ed0bb4 | 1928 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1929 | offset += mips_abi_regsize (gdbarch); |
1930 | } | |
1931 | ||
1932 | offset = -4; | |
1933 | ||
1934 | /* Check if the RA register was pushed on the stack. */ | |
1935 | if (save_inst & 0x40) | |
1936 | { | |
74ed0bb4 | 1937 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1938 | offset -= mips_abi_regsize (gdbarch); |
1939 | } | |
1940 | ||
1941 | /* Check if the S8 register was pushed on the stack. */ | |
1942 | if (xsregs > 6) | |
1943 | { | |
74ed0bb4 | 1944 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1945 | offset -= mips_abi_regsize (gdbarch); |
1946 | xsregs--; | |
1947 | } | |
1948 | /* Check if S2-S7 were pushed on the stack. */ | |
1949 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1950 | { | |
74ed0bb4 | 1951 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1952 | offset -= mips_abi_regsize (gdbarch); |
1953 | } | |
1954 | ||
1955 | /* Check if the S1 register was pushed on the stack. */ | |
1956 | if (save_inst & 0x10) | |
1957 | { | |
74ed0bb4 | 1958 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1959 | offset -= mips_abi_regsize (gdbarch); |
1960 | } | |
1961 | /* Check if the S0 register was pushed on the stack. */ | |
1962 | if (save_inst & 0x20) | |
1963 | { | |
74ed0bb4 | 1964 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1965 | offset -= mips_abi_regsize (gdbarch); |
1966 | } | |
1967 | ||
1968 | /* Check if A0-A3 were pushed on the stack. */ | |
1969 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1970 | { | |
74ed0bb4 | 1971 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1972 | offset -= mips_abi_regsize (gdbarch); |
1973 | } | |
1974 | } | |
1975 | ||
29639122 JB |
1976 | if (this_cache != NULL) |
1977 | { | |
1978 | this_cache->base = | |
b8a22b94 DJ |
1979 | (get_frame_register_signed (this_frame, |
1980 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1981 | + frame_offset - frame_adjust); |
1982 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
025bb325 | 1983 | be able to get rid of the assignment below, evetually. But it's |
29639122 | 1984 | still needed for now. */ |
72a155b4 UW |
1985 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1986 | + mips_regnum (gdbarch)->pc] | |
1987 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1988 | } |
1989 | ||
1990 | /* If we didn't reach the end of the prologue when scanning the function | |
1991 | instructions, then set end_prologue_addr to the address of the | |
1992 | instruction immediately after the last one we scanned. */ | |
1993 | if (end_prologue_addr == 0) | |
1994 | end_prologue_addr = cur_pc; | |
1995 | ||
1996 | return end_prologue_addr; | |
eec63939 AC |
1997 | } |
1998 | ||
29639122 JB |
1999 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
2000 | Procedures that use the 32-bit instruction set are handled by the | |
2001 | mips_insn32 unwinder. */ | |
2002 | ||
2003 | static struct mips_frame_cache * | |
b8a22b94 | 2004 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 2005 | { |
e17a4113 | 2006 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2007 | struct mips_frame_cache *cache; |
eec63939 AC |
2008 | |
2009 | if ((*this_cache) != NULL) | |
2010 | return (*this_cache); | |
29639122 JB |
2011 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2012 | (*this_cache) = cache; | |
b8a22b94 | 2013 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 2014 | |
29639122 JB |
2015 | /* Analyze the function prologue. */ |
2016 | { | |
b8a22b94 | 2017 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2018 | CORE_ADDR start_addr; |
eec63939 | 2019 | |
29639122 JB |
2020 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2021 | if (start_addr == 0) | |
e17a4113 | 2022 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2023 | /* We can't analyze the prologue if we couldn't find the begining |
2024 | of the function. */ | |
2025 | if (start_addr == 0) | |
2026 | return cache; | |
eec63939 | 2027 | |
e17a4113 | 2028 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2029 | } |
2030 | ||
3e8c568d | 2031 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 2032 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2033 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 2034 | cache->base); |
eec63939 | 2035 | |
29639122 | 2036 | return (*this_cache); |
eec63939 AC |
2037 | } |
2038 | ||
2039 | static void | |
b8a22b94 | 2040 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2041 | struct frame_id *this_id) |
eec63939 | 2042 | { |
b8a22b94 | 2043 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2044 | this_cache); |
21327321 DJ |
2045 | /* This marks the outermost frame. */ |
2046 | if (info->base == 0) | |
2047 | return; | |
b8a22b94 | 2048 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
2049 | } |
2050 | ||
b8a22b94 DJ |
2051 | static struct value * |
2052 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2053 | void **this_cache, int regnum) | |
eec63939 | 2054 | { |
b8a22b94 | 2055 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2056 | this_cache); |
b8a22b94 DJ |
2057 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2058 | } | |
2059 | ||
2060 | static int | |
2061 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2062 | struct frame_info *this_frame, void **this_cache) | |
2063 | { | |
2064 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2065 | if (mips_pc_is_mips16 (pc)) | |
2066 | return 1; | |
2067 | return 0; | |
eec63939 AC |
2068 | } |
2069 | ||
29639122 | 2070 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
2071 | { |
2072 | NORMAL_FRAME, | |
8fbca658 | 2073 | default_frame_unwind_stop_reason, |
29639122 | 2074 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
2075 | mips_insn16_frame_prev_register, |
2076 | NULL, | |
2077 | mips_insn16_frame_sniffer | |
eec63939 AC |
2078 | }; |
2079 | ||
eec63939 | 2080 | static CORE_ADDR |
b8a22b94 | 2081 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 2082 | void **this_cache) |
eec63939 | 2083 | { |
b8a22b94 | 2084 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
2085 | this_cache); |
2086 | return info->base; | |
eec63939 AC |
2087 | } |
2088 | ||
29639122 | 2089 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2090 | { |
29639122 JB |
2091 | &mips_insn16_frame_unwind, |
2092 | mips_insn16_frame_base_address, | |
2093 | mips_insn16_frame_base_address, | |
2094 | mips_insn16_frame_base_address | |
eec63939 AC |
2095 | }; |
2096 | ||
2097 | static const struct frame_base * | |
b8a22b94 | 2098 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 2099 | { |
b8a22b94 DJ |
2100 | CORE_ADDR pc = get_frame_pc (this_frame); |
2101 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 2102 | return &mips_insn16_frame_base; |
eec63939 AC |
2103 | else |
2104 | return NULL; | |
edfae063 AC |
2105 | } |
2106 | ||
29639122 JB |
2107 | /* Mark all the registers as unset in the saved_regs array |
2108 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
2109 | ||
74ed0bb4 MD |
2110 | static void |
2111 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 2112 | { |
29639122 JB |
2113 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
2114 | return; | |
2115 | ||
2116 | { | |
74ed0bb4 | 2117 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 2118 | int i; |
64159455 | 2119 | |
29639122 JB |
2120 | for (i = 0; i < num_regs; i++) |
2121 | { | |
2122 | this_cache->saved_regs[i].addr = -1; | |
2123 | } | |
2124 | } | |
c906108c SS |
2125 | } |
2126 | ||
025bb325 | 2127 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
2128 | the associated FRAME_CACHE if not null. |
2129 | Return the address of the first instruction past the prologue. */ | |
c906108c | 2130 | |
875e1767 | 2131 | static CORE_ADDR |
e17a4113 UW |
2132 | mips32_scan_prologue (struct gdbarch *gdbarch, |
2133 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2134 | struct frame_info *this_frame, |
29639122 | 2135 | struct mips_frame_cache *this_cache) |
c906108c | 2136 | { |
29639122 | 2137 | CORE_ADDR cur_pc; |
025bb325 MS |
2138 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
2139 | frame-pointer. */ | |
29639122 JB |
2140 | CORE_ADDR sp; |
2141 | long frame_offset; | |
2142 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2143 | |
29639122 JB |
2144 | CORE_ADDR end_prologue_addr = 0; |
2145 | int seen_sp_adjust = 0; | |
2146 | int load_immediate_bytes = 0; | |
db5f024e | 2147 | int in_delay_slot = 0; |
7d1e6fb8 | 2148 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 2149 | |
29639122 | 2150 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2151 | THIS_FRAME. */ |
2152 | if (this_frame != NULL) | |
2153 | sp = get_frame_register_signed (this_frame, | |
2154 | gdbarch_num_regs (gdbarch) | |
2155 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2156 | else |
29639122 | 2157 | sp = 0; |
9022177c | 2158 | |
29639122 JB |
2159 | if (limit_pc > start_pc + 200) |
2160 | limit_pc = start_pc + 200; | |
9022177c | 2161 | |
29639122 | 2162 | restart: |
9022177c | 2163 | |
29639122 | 2164 | frame_offset = 0; |
95ac2dcf | 2165 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 2166 | { |
29639122 JB |
2167 | unsigned long inst, high_word, low_word; |
2168 | int reg; | |
9022177c | 2169 | |
025bb325 | 2170 | /* Fetch the instruction. */ |
e17a4113 | 2171 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 2172 | |
29639122 JB |
2173 | /* Save some code by pre-extracting some useful fields. */ |
2174 | high_word = (inst >> 16) & 0xffff; | |
2175 | low_word = inst & 0xffff; | |
2176 | reg = high_word & 0x1f; | |
fe29b929 | 2177 | |
025bb325 | 2178 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
2179 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2180 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2181 | { | |
025bb325 | 2182 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
2183 | frame_offset += 0x10000 - low_word; |
2184 | else | |
2185 | /* Exit loop if a positive stack adjustment is found, which | |
2186 | usually means that the stack cleanup code in the function | |
2187 | epilogue is reached. */ | |
2188 | break; | |
2189 | seen_sp_adjust = 1; | |
2190 | } | |
7d1e6fb8 KB |
2191 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
2192 | && !regsize_is_64_bits) | |
29639122 | 2193 | { |
74ed0bb4 | 2194 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 2195 | } |
7d1e6fb8 KB |
2196 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
2197 | && regsize_is_64_bits) | |
29639122 JB |
2198 | { |
2199 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 2200 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
2201 | } |
2202 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2203 | { | |
2204 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2205 | if ((long) low_word != frame_offset) | |
2206 | frame_addr = sp + low_word; | |
b8a22b94 | 2207 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2208 | { |
2209 | unsigned alloca_adjust; | |
a4b8ebc8 | 2210 | |
29639122 | 2211 | frame_reg = 30; |
b8a22b94 DJ |
2212 | frame_addr = get_frame_register_signed |
2213 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2214 | |
29639122 JB |
2215 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
2216 | if (alloca_adjust > 0) | |
2217 | { | |
025bb325 | 2218 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2219 | an alloca or somethings similar. Fix sp to |
2220 | "pre-alloca" value, and try again. */ | |
2221 | sp += alloca_adjust; | |
2222 | /* Need to reset the status of all registers. Otherwise, | |
2223 | we will hit a guard that prevents the new address | |
2224 | for each register to be recomputed during the second | |
2225 | pass. */ | |
74ed0bb4 | 2226 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2227 | goto restart; |
2228 | } | |
2229 | } | |
2230 | } | |
2231 | /* move $30,$sp. With different versions of gas this will be either | |
2232 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2233 | Accept any one of these. */ | |
2234 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2235 | { | |
2236 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2237 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2238 | { |
2239 | unsigned alloca_adjust; | |
c906108c | 2240 | |
29639122 | 2241 | frame_reg = 30; |
b8a22b94 DJ |
2242 | frame_addr = get_frame_register_signed |
2243 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2244 | |
29639122 JB |
2245 | alloca_adjust = (unsigned) (frame_addr - sp); |
2246 | if (alloca_adjust > 0) | |
2247 | { | |
025bb325 | 2248 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2249 | an alloca or somethings similar. Fix sp to |
2250 | "pre-alloca" value, and try again. */ | |
2251 | sp = frame_addr; | |
2252 | /* Need to reset the status of all registers. Otherwise, | |
2253 | we will hit a guard that prevents the new address | |
2254 | for each register to be recomputed during the second | |
2255 | pass. */ | |
74ed0bb4 | 2256 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2257 | goto restart; |
2258 | } | |
2259 | } | |
2260 | } | |
7d1e6fb8 KB |
2261 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2262 | && !regsize_is_64_bits) | |
29639122 | 2263 | { |
74ed0bb4 | 2264 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2265 | } |
2266 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2267 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2268 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2269 | || high_word == 0x3c1c /* lui $gp,n */ | |
2270 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2271 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2272 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2273 | ) | |
19080931 MR |
2274 | { |
2275 | /* These instructions are part of the prologue, but we don't | |
2276 | need to do anything special to handle them. */ | |
2277 | } | |
29639122 JB |
2278 | /* The instructions below load $at or $t0 with an immediate |
2279 | value in preparation for a stack adjustment via | |
025bb325 | 2280 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
2281 | initialize a local variable, so we accept them only before |
2282 | a stack adjustment instruction was seen. */ | |
2283 | else if (!seen_sp_adjust | |
19080931 MR |
2284 | && (high_word == 0x3c01 /* lui $at,n */ |
2285 | || high_word == 0x3c08 /* lui $t0,n */ | |
2286 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2287 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2288 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2289 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2290 | )) | |
2291 | { | |
2292 | if (end_prologue_addr == 0) | |
2293 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ | |
2294 | } | |
29639122 | 2295 | else |
19080931 MR |
2296 | { |
2297 | /* This instruction is not an instruction typically found | |
2298 | in a prologue, so we must have reached the end of the | |
2299 | prologue. */ | |
2300 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2301 | loop now? Why would we need to continue scanning the function | |
2302 | instructions? */ | |
2303 | if (end_prologue_addr == 0) | |
2304 | end_prologue_addr = cur_pc; | |
2305 | ||
2306 | /* Check for branches and jumps. For now, only jump to | |
2307 | register are caught (i.e. returns). */ | |
2308 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2309 | in_delay_slot = 1; | |
2310 | } | |
db5f024e DJ |
2311 | |
2312 | /* If the previous instruction was a jump, we must have reached | |
2313 | the end of the prologue by now. Stop scanning so that we do | |
2314 | not go past the function return. */ | |
2315 | if (in_delay_slot) | |
2316 | break; | |
a4b8ebc8 | 2317 | } |
c906108c | 2318 | |
29639122 JB |
2319 | if (this_cache != NULL) |
2320 | { | |
2321 | this_cache->base = | |
b8a22b94 DJ |
2322 | (get_frame_register_signed (this_frame, |
2323 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2324 | + frame_offset); |
2325 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2326 | this assignment below, eventually. But it's still needed | |
2327 | for now. */ | |
72a155b4 UW |
2328 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2329 | + mips_regnum (gdbarch)->pc] | |
2330 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2331 | + MIPS_RA_REGNUM]; |
29639122 | 2332 | } |
c906108c | 2333 | |
29639122 JB |
2334 | /* If we didn't reach the end of the prologue when scanning the function |
2335 | instructions, then set end_prologue_addr to the address of the | |
2336 | instruction immediately after the last one we scanned. */ | |
2337 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2338 | we may as well be careful and do our best if we have a null | |
2339 | end_prologue_addr. */ | |
2340 | if (end_prologue_addr == 0) | |
2341 | end_prologue_addr = cur_pc; | |
2342 | ||
2343 | /* In a frameless function, we might have incorrectly | |
025bb325 | 2344 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
2345 | if the load immediate was not followed by a stack adjustment. */ |
2346 | if (load_immediate_bytes && !seen_sp_adjust) | |
2347 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2348 | |
29639122 | 2349 | return end_prologue_addr; |
c906108c SS |
2350 | } |
2351 | ||
29639122 JB |
2352 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2353 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2354 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2355 | unwinder. */ | |
c906108c | 2356 | |
29639122 | 2357 | static struct mips_frame_cache * |
b8a22b94 | 2358 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2359 | { |
e17a4113 | 2360 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2361 | struct mips_frame_cache *cache; |
c906108c | 2362 | |
29639122 JB |
2363 | if ((*this_cache) != NULL) |
2364 | return (*this_cache); | |
c5aa993b | 2365 | |
29639122 JB |
2366 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2367 | (*this_cache) = cache; | |
b8a22b94 | 2368 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2369 | |
29639122 JB |
2370 | /* Analyze the function prologue. */ |
2371 | { | |
b8a22b94 | 2372 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2373 | CORE_ADDR start_addr; |
c906108c | 2374 | |
29639122 JB |
2375 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2376 | if (start_addr == 0) | |
e17a4113 | 2377 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2378 | /* We can't analyze the prologue if we couldn't find the begining |
2379 | of the function. */ | |
2380 | if (start_addr == 0) | |
2381 | return cache; | |
c5aa993b | 2382 | |
e17a4113 | 2383 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2384 | } |
2385 | ||
3e8c568d | 2386 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2387 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2388 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2389 | cache->base); |
c5aa993b | 2390 | |
29639122 | 2391 | return (*this_cache); |
c906108c SS |
2392 | } |
2393 | ||
29639122 | 2394 | static void |
b8a22b94 | 2395 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2396 | struct frame_id *this_id) |
c906108c | 2397 | { |
b8a22b94 | 2398 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2399 | this_cache); |
21327321 DJ |
2400 | /* This marks the outermost frame. */ |
2401 | if (info->base == 0) | |
2402 | return; | |
b8a22b94 | 2403 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2404 | } |
c906108c | 2405 | |
b8a22b94 DJ |
2406 | static struct value * |
2407 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2408 | void **this_cache, int regnum) | |
29639122 | 2409 | { |
b8a22b94 | 2410 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2411 | this_cache); |
b8a22b94 DJ |
2412 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2413 | } | |
2414 | ||
2415 | static int | |
2416 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2417 | struct frame_info *this_frame, void **this_cache) | |
2418 | { | |
2419 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2420 | if (! mips_pc_is_mips16 (pc)) | |
2421 | return 1; | |
2422 | return 0; | |
c906108c SS |
2423 | } |
2424 | ||
29639122 JB |
2425 | static const struct frame_unwind mips_insn32_frame_unwind = |
2426 | { | |
2427 | NORMAL_FRAME, | |
8fbca658 | 2428 | default_frame_unwind_stop_reason, |
29639122 | 2429 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
2430 | mips_insn32_frame_prev_register, |
2431 | NULL, | |
2432 | mips_insn32_frame_sniffer | |
29639122 | 2433 | }; |
c906108c | 2434 | |
1c645fec | 2435 | static CORE_ADDR |
b8a22b94 | 2436 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2437 | void **this_cache) |
c906108c | 2438 | { |
b8a22b94 | 2439 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2440 | this_cache); |
2441 | return info->base; | |
2442 | } | |
c906108c | 2443 | |
29639122 JB |
2444 | static const struct frame_base mips_insn32_frame_base = |
2445 | { | |
2446 | &mips_insn32_frame_unwind, | |
2447 | mips_insn32_frame_base_address, | |
2448 | mips_insn32_frame_base_address, | |
2449 | mips_insn32_frame_base_address | |
2450 | }; | |
1c645fec | 2451 | |
29639122 | 2452 | static const struct frame_base * |
b8a22b94 | 2453 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2454 | { |
b8a22b94 DJ |
2455 | CORE_ADDR pc = get_frame_pc (this_frame); |
2456 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2457 | return &mips_insn32_frame_base; |
a65bbe44 | 2458 | else |
29639122 JB |
2459 | return NULL; |
2460 | } | |
a65bbe44 | 2461 | |
29639122 | 2462 | static struct trad_frame_cache * |
b8a22b94 | 2463 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2464 | { |
2465 | CORE_ADDR pc; | |
2466 | CORE_ADDR start_addr; | |
2467 | CORE_ADDR stack_addr; | |
2468 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2469 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2470 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2471 | |
29639122 JB |
2472 | if ((*this_cache) != NULL) |
2473 | return (*this_cache); | |
b8a22b94 | 2474 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2475 | (*this_cache) = this_trad_cache; |
1c645fec | 2476 | |
29639122 | 2477 | /* The return address is in the link register. */ |
3e8c568d | 2478 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2479 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2480 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2481 | |
29639122 JB |
2482 | /* Frame ID, since it's a frameless / stackless function, no stack |
2483 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2484 | pc = get_frame_pc (this_frame); |
29639122 | 2485 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2486 | stack_addr = get_frame_register_signed (this_frame, |
2487 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2488 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2489 | |
29639122 JB |
2490 | /* Assume that the frame's base is the same as the |
2491 | stack-pointer. */ | |
2492 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2493 | |
29639122 JB |
2494 | return this_trad_cache; |
2495 | } | |
c906108c | 2496 | |
29639122 | 2497 | static void |
b8a22b94 | 2498 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2499 | struct frame_id *this_id) |
2500 | { | |
2501 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2502 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2503 | trad_frame_get_id (this_trad_cache, this_id); |
2504 | } | |
c906108c | 2505 | |
b8a22b94 DJ |
2506 | static struct value * |
2507 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2508 | void **this_cache, int regnum) | |
29639122 JB |
2509 | { |
2510 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2511 | = mips_stub_frame_cache (this_frame, this_cache); |
2512 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2513 | } |
c906108c | 2514 | |
b8a22b94 DJ |
2515 | static int |
2516 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2517 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2518 | { |
aa6c981f | 2519 | gdb_byte dummy[4]; |
979b38e0 | 2520 | struct obj_section *s; |
b8a22b94 | 2521 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2522 | struct minimal_symbol *msym; |
979b38e0 | 2523 | |
aa6c981f | 2524 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2525 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2526 | return 1; | |
aa6c981f | 2527 | |
29639122 | 2528 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2529 | return 1; |
979b38e0 DJ |
2530 | |
2531 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2532 | s = find_pc_section (pc); | |
2533 | ||
2534 | if (s != NULL | |
2535 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2536 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2537 | return 1; |
979b38e0 | 2538 | |
db5f024e DJ |
2539 | /* Calling a PIC function from a non-PIC function passes through a |
2540 | stub. The stub for foo is named ".pic.foo". */ | |
2541 | msym = lookup_minimal_symbol_by_pc (pc); | |
2542 | if (msym != NULL | |
2543 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2544 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2545 | return 1; | |
2546 | ||
b8a22b94 | 2547 | return 0; |
29639122 | 2548 | } |
c906108c | 2549 | |
b8a22b94 DJ |
2550 | static const struct frame_unwind mips_stub_frame_unwind = |
2551 | { | |
2552 | NORMAL_FRAME, | |
8fbca658 | 2553 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
2554 | mips_stub_frame_this_id, |
2555 | mips_stub_frame_prev_register, | |
2556 | NULL, | |
2557 | mips_stub_frame_sniffer | |
2558 | }; | |
2559 | ||
29639122 | 2560 | static CORE_ADDR |
b8a22b94 | 2561 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2562 | void **this_cache) |
2563 | { | |
2564 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2565 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2566 | return trad_frame_get_this_base (this_trad_cache); |
2567 | } | |
0fce0821 | 2568 | |
29639122 JB |
2569 | static const struct frame_base mips_stub_frame_base = |
2570 | { | |
2571 | &mips_stub_frame_unwind, | |
2572 | mips_stub_frame_base_address, | |
2573 | mips_stub_frame_base_address, | |
2574 | mips_stub_frame_base_address | |
2575 | }; | |
2576 | ||
2577 | static const struct frame_base * | |
b8a22b94 | 2578 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2579 | { |
b8a22b94 | 2580 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2581 | return &mips_stub_frame_base; |
2582 | else | |
2583 | return NULL; | |
2584 | } | |
2585 | ||
29639122 | 2586 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2587 | |
29639122 | 2588 | static CORE_ADDR |
24568a2c | 2589 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2590 | { |
24568a2c | 2591 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 KB |
2592 | |
2593 | if (is_mips16_addr (addr)) | |
2594 | addr = unmake_mips16_addr (addr); | |
2595 | ||
29639122 JB |
2596 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2597 | /* This hack is a work-around for existing boards using PMON, the | |
2598 | simulator, and any other 64-bit targets that doesn't have true | |
2599 | 64-bit addressing. On these targets, the upper 32 bits of | |
2600 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2601 | likely to have been sign extended to all 1s by instruction | |
2602 | sequences that load 32-bit addresses. For example, a typical | |
2603 | piece of code that loads an address is this: | |
65596487 | 2604 | |
29639122 JB |
2605 | lui $r2, <upper 16 bits> |
2606 | ori $r2, <lower 16 bits> | |
65596487 | 2607 | |
29639122 JB |
2608 | But the lui sign-extends the value such that the upper 32 bits |
2609 | may be all 1s. The workaround is simply to mask off these | |
2610 | bits. In the future, gcc may be changed to support true 64-bit | |
2611 | addressing, and this masking will have to be disabled. */ | |
2612 | return addr &= 0xffffffffUL; | |
2613 | else | |
2614 | return addr; | |
65596487 JB |
2615 | } |
2616 | ||
3d5f6d12 DJ |
2617 | /* Instructions used during single-stepping of atomic sequences. */ |
2618 | #define LL_OPCODE 0x30 | |
2619 | #define LLD_OPCODE 0x34 | |
2620 | #define SC_OPCODE 0x38 | |
2621 | #define SCD_OPCODE 0x3c | |
2622 | ||
2623 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2624 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2625 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2626 | the sequence. */ | |
2627 | ||
2628 | static int | |
6c95b8df PA |
2629 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2630 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
2631 | { |
2632 | CORE_ADDR breaks[2] = {-1, -1}; | |
2633 | CORE_ADDR loc = pc; | |
2634 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2635 | unsigned long insn; | |
2636 | int insn_count; | |
2637 | int index; | |
2638 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2639 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2640 | ||
2641 | if (pc & 0x01) | |
2642 | return 0; | |
2643 | ||
e17a4113 | 2644 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2645 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2646 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2647 | return 0; | |
2648 | ||
2649 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2650 | instructions. */ | |
2651 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2652 | { | |
2653 | int is_branch = 0; | |
2654 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2655 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2656 | |
2657 | /* Assume that there is at most one branch in the atomic | |
2658 | sequence. If a branch is found, put a breakpoint in its | |
2659 | destination address. */ | |
2660 | switch (itype_op (insn)) | |
2661 | { | |
2662 | case 0: /* SPECIAL */ | |
2663 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 2664 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2665 | break; |
2666 | case 1: /* REGIMM */ | |
a385295e MR |
2667 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
2668 | || ((itype_rt (insn) & 0x1e) == 0 | |
2669 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
2670 | break; |
2671 | case 2: /* J */ | |
2672 | case 3: /* JAL */ | |
025bb325 | 2673 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2674 | case 4: /* BEQ */ |
2675 | case 5: /* BNE */ | |
2676 | case 6: /* BLEZ */ | |
2677 | case 7: /* BGTZ */ | |
2678 | case 20: /* BEQL */ | |
2679 | case 21: /* BNEL */ | |
2680 | case 22: /* BLEZL */ | |
2681 | case 23: /* BGTTL */ | |
2682 | is_branch = 1; | |
2683 | break; | |
2684 | case 17: /* COP1 */ | |
a385295e MR |
2685 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
2686 | && (itype_rt (insn) & 0x2) == 0); | |
2687 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
2688 | break; | |
2689 | /* Fall through. */ | |
3d5f6d12 DJ |
2690 | case 18: /* COP2 */ |
2691 | case 19: /* COP3 */ | |
2692 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2693 | break; | |
2694 | } | |
2695 | if (is_branch) | |
2696 | { | |
2697 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2698 | if (last_breakpoint >= 1) | |
2699 | return 0; /* More than one branch found, fallback to the | |
2700 | standard single-step code. */ | |
2701 | breaks[1] = branch_bp; | |
2702 | last_breakpoint++; | |
2703 | } | |
2704 | ||
2705 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2706 | break; | |
2707 | } | |
2708 | ||
2709 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2710 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2711 | return 0; | |
2712 | ||
2713 | loc += MIPS_INSN32_SIZE; | |
2714 | ||
2715 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2716 | breaks[0] = loc; | |
2717 | ||
2718 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 2719 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
2720 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
2721 | last_breakpoint = 0; | |
2722 | ||
2723 | /* Effectively inserts the breakpoints. */ | |
2724 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 2725 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
2726 | |
2727 | return 1; | |
2728 | } | |
2729 | ||
29639122 JB |
2730 | /* mips_software_single_step() is called just before we want to resume |
2731 | the inferior, if we want to single-step it but there is no hardware | |
2732 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2733 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2734 | |
e6590a1b | 2735 | int |
0b1b3e42 | 2736 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2737 | { |
a6d9a66e | 2738 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2739 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 2740 | CORE_ADDR pc, next_pc; |
65596487 | 2741 | |
0b1b3e42 | 2742 | pc = get_frame_pc (frame); |
6c95b8df | 2743 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
2744 | return 1; |
2745 | ||
0b1b3e42 | 2746 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2747 | |
6c95b8df | 2748 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 2749 | return 1; |
29639122 | 2750 | } |
a65bbe44 | 2751 | |
29639122 | 2752 | /* Test whether the PC points to the return instruction at the |
025bb325 | 2753 | end of a function. */ |
65596487 | 2754 | |
29639122 | 2755 | static int |
e17a4113 | 2756 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2757 | { |
0fe7e7c8 | 2758 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2759 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2760 | generates a "jr $ra"; other times it generates code to load | |
2761 | the return address from the stack to an accessible register (such | |
2762 | as $a3), then a "jr" using that register. This second case | |
2763 | is almost impossible to distinguish from an indirect jump | |
2764 | used for switch statements, so we don't even try. */ | |
e17a4113 | 2765 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
29639122 | 2766 | else |
e17a4113 | 2767 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
29639122 | 2768 | } |
c906108c | 2769 | |
c906108c | 2770 | |
29639122 JB |
2771 | /* This fencepost looks highly suspicious to me. Removing it also |
2772 | seems suspicious as it could affect remote debugging across serial | |
2773 | lines. */ | |
c906108c | 2774 | |
29639122 | 2775 | static CORE_ADDR |
74ed0bb4 | 2776 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2777 | { |
2778 | CORE_ADDR start_pc; | |
2779 | CORE_ADDR fence; | |
2780 | int instlen; | |
2781 | int seen_adjsp = 0; | |
d6b48e9c | 2782 | struct inferior *inf; |
65596487 | 2783 | |
74ed0bb4 | 2784 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2785 | start_pc = pc; |
2786 | fence = start_pc - heuristic_fence_post; | |
2787 | if (start_pc == 0) | |
2788 | return 0; | |
65596487 | 2789 | |
29639122 JB |
2790 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2791 | fence = VM_MIN_ADDRESS; | |
65596487 | 2792 | |
95ac2dcf | 2793 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2794 | |
d6b48e9c PA |
2795 | inf = current_inferior (); |
2796 | ||
025bb325 | 2797 | /* Search back for previous return. */ |
29639122 JB |
2798 | for (start_pc -= instlen;; start_pc -= instlen) |
2799 | if (start_pc < fence) | |
2800 | { | |
2801 | /* It's not clear to me why we reach this point when | |
2802 | stop_soon, but with this test, at least we | |
2803 | don't print out warnings for every child forked (eg, on | |
2804 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 2805 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2806 | { |
2807 | static int blurb_printed = 0; | |
98b4dd94 | 2808 | |
5af949e3 UW |
2809 | warning (_("GDB can't find the start of the function at %s."), |
2810 | paddress (gdbarch, pc)); | |
29639122 JB |
2811 | |
2812 | if (!blurb_printed) | |
2813 | { | |
2814 | /* This actually happens frequently in embedded | |
2815 | development, when you first connect to a board | |
2816 | and your stack pointer and pc are nowhere in | |
2817 | particular. This message needs to give people | |
2818 | in that situation enough information to | |
2819 | determine that it's no big deal. */ | |
2820 | printf_filtered ("\n\ | |
5af949e3 | 2821 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2822 | and thus can't determine the size of that function's stack frame.\n\ |
2823 | This means that GDB may be unable to access that stack frame, or\n\ | |
2824 | the frames below it.\n\ | |
2825 | This problem is most likely caused by an invalid program counter or\n\ | |
2826 | stack pointer.\n\ | |
2827 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2828 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2829 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2830 | heuristic-fence-post' command.\n", |
2831 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2832 | blurb_printed = 1; |
2833 | } | |
2834 | } | |
2835 | ||
2836 | return 0; | |
2837 | } | |
0fe7e7c8 | 2838 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2839 | { |
2840 | unsigned short inst; | |
2841 | ||
2842 | /* On MIPS16, any one of the following is likely to be the | |
2843 | start of a function: | |
193774b3 MR |
2844 | extend save |
2845 | save | |
29639122 JB |
2846 | entry |
2847 | addiu sp,-n | |
2848 | daddiu sp,-n | |
025bb325 | 2849 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
e17a4113 | 2850 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2851 | if ((inst & 0xff80) == 0x6480) /* save */ |
2852 | { | |
2853 | if (start_pc - instlen >= fence) | |
2854 | { | |
e17a4113 | 2855 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2856 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2857 | start_pc -= instlen; | |
2858 | } | |
2859 | break; | |
2860 | } | |
2861 | else if (((inst & 0xf81f) == 0xe809 | |
2862 | && (inst & 0x700) != 0x700) /* entry */ | |
2863 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2864 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2865 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2866 | break; |
2867 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2868 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2869 | seen_adjsp = 1; | |
2870 | else | |
2871 | seen_adjsp = 0; | |
2872 | } | |
e17a4113 | 2873 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2874 | { |
4c7d22cb | 2875 | /* Skip return and its delay slot. */ |
95ac2dcf | 2876 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2877 | break; |
2878 | } | |
2879 | ||
2880 | return start_pc; | |
c906108c SS |
2881 | } |
2882 | ||
6c0d6680 DJ |
2883 | struct mips_objfile_private |
2884 | { | |
2885 | bfd_size_type size; | |
2886 | char *contents; | |
2887 | }; | |
2888 | ||
f09ded24 AC |
2889 | /* According to the current ABI, should the type be passed in a |
2890 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2891 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 2892 | FP registers and, consequently this returns false - forces FP |
025bb325 | 2893 | arguments into integer registers. */ |
f09ded24 AC |
2894 | |
2895 | static int | |
74ed0bb4 MD |
2896 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2897 | struct type *arg_type) | |
f09ded24 AC |
2898 | { |
2899 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2900 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2901 | && (typecode == TYPE_CODE_STRUCT |
2902 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2903 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2904 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2905 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2906 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2907 | } |
2908 | ||
49e790b0 | 2909 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 2910 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
2911 | |
2912 | static int | |
2913 | mips_type_needs_double_align (struct type *type) | |
2914 | { | |
2915 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2916 | |
49e790b0 DJ |
2917 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2918 | return 1; | |
2919 | else if (typecode == TYPE_CODE_STRUCT) | |
2920 | { | |
2921 | if (TYPE_NFIELDS (type) < 1) | |
2922 | return 0; | |
2923 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2924 | } | |
2925 | else if (typecode == TYPE_CODE_UNION) | |
2926 | { | |
361d1df0 | 2927 | int i, n; |
49e790b0 DJ |
2928 | |
2929 | n = TYPE_NFIELDS (type); | |
2930 | for (i = 0; i < n; i++) | |
2931 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2932 | return 1; | |
2933 | return 0; | |
2934 | } | |
2935 | return 0; | |
2936 | } | |
2937 | ||
dc604539 AC |
2938 | /* Adjust the address downward (direction of stack growth) so that it |
2939 | is correctly aligned for a new stack frame. */ | |
2940 | static CORE_ADDR | |
2941 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2942 | { | |
5b03f266 | 2943 | return align_down (addr, 16); |
dc604539 AC |
2944 | } |
2945 | ||
f7ab6ec6 | 2946 | static CORE_ADDR |
7d9b040b | 2947 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2948 | struct regcache *regcache, CORE_ADDR bp_addr, |
2949 | int nargs, struct value **args, CORE_ADDR sp, | |
2950 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2951 | { |
2952 | int argreg; | |
2953 | int float_argreg; | |
2954 | int argnum; | |
2955 | int len = 0; | |
2956 | int stack_offset = 0; | |
480d3dd2 | 2957 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 2958 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 2959 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2960 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2961 | |
25ab4790 AC |
2962 | /* For shared libraries, "t9" needs to point at the function |
2963 | address. */ | |
4c7d22cb | 2964 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2965 | |
2966 | /* Set the return address register to point to the entry point of | |
2967 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2968 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2969 | |
c906108c | 2970 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2971 | are properly aligned. The stack has to be at least 64-bit |
2972 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2973 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2974 | aligned, so we round to this widest known alignment. */ | |
2975 | ||
5b03f266 AC |
2976 | sp = align_down (sp, 16); |
2977 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2978 | |
46e0f506 | 2979 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2980 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2981 | passed in registers, but that's OK. */ |
c906108c | 2982 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2983 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2984 | sp -= align_up (len, 16); |
c906108c | 2985 | |
9ace0497 | 2986 | if (mips_debug) |
6d82d43b | 2987 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2988 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2989 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2990 | |
c906108c | 2991 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2992 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2993 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2994 | |
46e0f506 | 2995 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2996 | if (struct_return) |
9ace0497 AC |
2997 | { |
2998 | if (mips_debug) | |
2999 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3000 | "mips_eabi_push_dummy_call: " |
3001 | "struct_return reg=%d %s\n", | |
5af949e3 | 3002 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3003 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 3004 | } |
c906108c SS |
3005 | |
3006 | /* Now load as many as possible of the first arguments into | |
3007 | registers, and push the rest onto the stack. Loop thru args | |
3008 | from first to last. */ | |
3009 | for (argnum = 0; argnum < nargs; argnum++) | |
3010 | { | |
47a35522 MK |
3011 | const gdb_byte *val; |
3012 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 3013 | struct value *arg = args[argnum]; |
4991999e | 3014 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
3015 | int len = TYPE_LENGTH (arg_type); |
3016 | enum type_code typecode = TYPE_CODE (arg_type); | |
3017 | ||
9ace0497 AC |
3018 | if (mips_debug) |
3019 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3020 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 3021 | argnum + 1, len, (int) typecode); |
9ace0497 | 3022 | |
930bd0e0 KB |
3023 | /* Function pointer arguments to mips16 code need to be made into |
3024 | mips16 pointers. */ | |
3025 | if (typecode == TYPE_CODE_PTR | |
3026 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
3027 | { | |
3028 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
3029 | len, byte_order); | |
3030 | if (mips_pc_is_mips16 (addr)) | |
3031 | { | |
3032 | store_signed_integer (valbuf, len, byte_order, | |
3033 | make_mips16_addr (addr)); | |
3034 | val = valbuf; | |
3035 | } | |
3036 | else | |
3037 | val = value_contents (arg); | |
3038 | } | |
c906108c | 3039 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 3040 | reference. */ |
930bd0e0 | 3041 | else if (len > regsize |
9ace0497 | 3042 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 3043 | { |
e17a4113 UW |
3044 | store_unsigned_integer (valbuf, regsize, byte_order, |
3045 | value_address (arg)); | |
c906108c | 3046 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 3047 | len = regsize; |
c906108c | 3048 | val = valbuf; |
9ace0497 AC |
3049 | if (mips_debug) |
3050 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3051 | } |
3052 | else | |
47a35522 | 3053 | val = value_contents (arg); |
c906108c SS |
3054 | |
3055 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3056 | even-numbered floating point register. Round the FP register |
3057 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3058 | left. Non MIPS_EABI targets also pass the FP in the integer |
3059 | registers so also round up normal registers. */ | |
74ed0bb4 | 3060 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
3061 | { |
3062 | if ((float_argreg & 1)) | |
3063 | float_argreg++; | |
3064 | } | |
c906108c SS |
3065 | |
3066 | /* Floating point arguments passed in registers have to be | |
3067 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3068 | are passed in register pairs; the even register gets |
3069 | the low word, and the odd register gets the high word. | |
3070 | On non-EABI processors, the first two floating point arguments are | |
3071 | also copied to general registers, because MIPS16 functions | |
3072 | don't use float registers for arguments. This duplication of | |
3073 | arguments in general registers can't hurt non-MIPS16 functions | |
3074 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3075 | /* MIPS_EABI squeezes a struct that contains a single floating |
3076 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3077 | stack. */ |
74ed0bb4 MD |
3078 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3079 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 3080 | { |
6da397e0 KB |
3081 | /* EABI32 will pass doubles in consecutive registers, even on |
3082 | 64-bit cores. At one time, we used to check the size of | |
3083 | `float_argreg' to determine whether or not to pass doubles | |
3084 | in consecutive registers, but this is not sufficient for | |
3085 | making the ABI determination. */ | |
3086 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 3087 | { |
72a155b4 | 3088 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3089 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 3090 | long regval; |
c906108c SS |
3091 | |
3092 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
3093 | regval = extract_signed_integer (val + low_offset, |
3094 | 4, byte_order); | |
9ace0497 | 3095 | if (mips_debug) |
acdb74a0 | 3096 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3097 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3098 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3099 | |
3100 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
3101 | regval = extract_signed_integer (val + 4 - low_offset, |
3102 | 4, byte_order); | |
9ace0497 | 3103 | if (mips_debug) |
acdb74a0 | 3104 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3105 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3106 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3107 | } |
3108 | else | |
3109 | { | |
3110 | /* This is a floating point value that fits entirely | |
3111 | in a single register. */ | |
53a5351d | 3112 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3113 | above to ensure that it is even register aligned. */ |
a8852dc5 | 3114 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 3115 | if (mips_debug) |
acdb74a0 | 3116 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3117 | float_argreg, phex (regval, len)); |
a8852dc5 | 3118 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3119 | } |
3120 | } | |
3121 | else | |
3122 | { | |
3123 | /* Copy the argument to general registers or the stack in | |
3124 | register-sized pieces. Large arguments are split between | |
3125 | registers and stack. */ | |
1a69e1e4 DJ |
3126 | /* Note: structs whose size is not a multiple of regsize |
3127 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3128 | them in registers where gcc sometimes puts them on the |
3129 | stack. For maximum compatibility, we will put them in | |
3130 | both places. */ | |
1a69e1e4 | 3131 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 3132 | |
f09ded24 | 3133 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3134 | register are only written to memory. */ |
c906108c SS |
3135 | while (len > 0) |
3136 | { | |
ebafbe83 | 3137 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3138 | int stack_used_p = 0; |
1a69e1e4 | 3139 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 3140 | |
acdb74a0 AC |
3141 | if (mips_debug) |
3142 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3143 | partial_len); | |
3144 | ||
566f0f7a | 3145 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3146 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 3147 | || odd_sized_struct |
74ed0bb4 | 3148 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 3149 | { |
c906108c | 3150 | /* Should shorter than int integer values be |
025bb325 | 3151 | promoted to int before being stored? */ |
c906108c | 3152 | int longword_offset = 0; |
9ace0497 | 3153 | CORE_ADDR addr; |
566f0f7a | 3154 | stack_used_p = 1; |
72a155b4 | 3155 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 3156 | { |
1a69e1e4 | 3157 | if (regsize == 8 |
480d3dd2 AC |
3158 | && (typecode == TYPE_CODE_INT |
3159 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3160 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 3161 | longword_offset = regsize - len; |
480d3dd2 AC |
3162 | else if ((typecode == TYPE_CODE_STRUCT |
3163 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
3164 | && TYPE_LENGTH (arg_type) < regsize) |
3165 | longword_offset = regsize - len; | |
7a292a7a | 3166 | } |
c5aa993b | 3167 | |
9ace0497 AC |
3168 | if (mips_debug) |
3169 | { | |
5af949e3 UW |
3170 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3171 | paddress (gdbarch, stack_offset)); | |
3172 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3173 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 3174 | } |
361d1df0 | 3175 | |
9ace0497 AC |
3176 | addr = sp + stack_offset + longword_offset; |
3177 | ||
3178 | if (mips_debug) | |
3179 | { | |
3180 | int i; | |
5af949e3 UW |
3181 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3182 | paddress (gdbarch, addr)); | |
9ace0497 AC |
3183 | for (i = 0; i < partial_len; i++) |
3184 | { | |
6d82d43b | 3185 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3186 | val[i] & 0xff); |
9ace0497 AC |
3187 | } |
3188 | } | |
3189 | write_memory (addr, val, partial_len); | |
c906108c SS |
3190 | } |
3191 | ||
f09ded24 AC |
3192 | /* Note!!! This is NOT an else clause. Odd sized |
3193 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3194 | arguments will not. */ |
566f0f7a | 3195 | /* Write this portion of the argument to a general |
6d82d43b | 3196 | purpose register. */ |
74ed0bb4 MD |
3197 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
3198 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 3199 | { |
6d82d43b | 3200 | LONGEST regval = |
a8852dc5 | 3201 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 3202 | |
9ace0497 | 3203 | if (mips_debug) |
acdb74a0 | 3204 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3205 | argreg, |
1a69e1e4 | 3206 | phex (regval, regsize)); |
a8852dc5 | 3207 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 3208 | argreg++; |
c906108c | 3209 | } |
c5aa993b | 3210 | |
c906108c SS |
3211 | len -= partial_len; |
3212 | val += partial_len; | |
3213 | ||
b021a221 MS |
3214 | /* Compute the offset into the stack at which we will |
3215 | copy the next parameter. | |
566f0f7a | 3216 | |
566f0f7a | 3217 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3218 | only needs to be adjusted when it has been used. */ |
c906108c | 3219 | |
46e0f506 | 3220 | if (stack_used_p) |
1a69e1e4 | 3221 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
3222 | } |
3223 | } | |
9ace0497 AC |
3224 | if (mips_debug) |
3225 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3226 | } |
3227 | ||
f10683bb | 3228 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3229 | |
0f71a2f6 JM |
3230 | /* Return adjusted stack pointer. */ |
3231 | return sp; | |
3232 | } | |
3233 | ||
a1f5b845 | 3234 | /* Determine the return value convention being used. */ |
6d82d43b | 3235 | |
9c8fdbfa | 3236 | static enum return_value_convention |
c055b101 | 3237 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 3238 | struct type *type, struct regcache *regcache, |
47a35522 | 3239 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3240 | { |
609ba780 JM |
3241 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3242 | int fp_return_type = 0; | |
3243 | int offset, regnum, xfer; | |
3244 | ||
9c8fdbfa AC |
3245 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3246 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
3247 | |
3248 | /* Floating point type? */ | |
3249 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3250 | { | |
3251 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
3252 | fp_return_type = 1; | |
3253 | /* Structs with a single field of float type | |
3254 | are returned in a floating point register. */ | |
3255 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3256 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3257 | && TYPE_NFIELDS (type) == 1) | |
3258 | { | |
3259 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
3260 | ||
3261 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
3262 | fp_return_type = 1; | |
3263 | } | |
3264 | } | |
3265 | ||
3266 | if (fp_return_type) | |
3267 | { | |
3268 | /* A floating-point value belongs in the least significant part | |
3269 | of FP0/FP1. */ | |
3270 | if (mips_debug) | |
3271 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3272 | regnum = mips_regnum (gdbarch)->fp0; | |
3273 | } | |
3274 | else | |
3275 | { | |
3276 | /* An integer value goes in V0/V1. */ | |
3277 | if (mips_debug) | |
3278 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3279 | regnum = MIPS_V0_REGNUM; | |
3280 | } | |
3281 | for (offset = 0; | |
3282 | offset < TYPE_LENGTH (type); | |
3283 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3284 | { | |
3285 | xfer = mips_abi_regsize (gdbarch); | |
3286 | if (offset + xfer > TYPE_LENGTH (type)) | |
3287 | xfer = TYPE_LENGTH (type) - offset; | |
3288 | mips_xfer_register (gdbarch, regcache, | |
3289 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3290 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3291 | offset); | |
3292 | } | |
3293 | ||
9c8fdbfa | 3294 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3295 | } |
3296 | ||
6d82d43b AC |
3297 | |
3298 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3299 | |
8d26208a DJ |
3300 | /* Search for a naturally aligned double at OFFSET inside a struct |
3301 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3302 | registers. */ | |
3303 | ||
3304 | static int | |
74ed0bb4 MD |
3305 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3306 | int offset) | |
8d26208a DJ |
3307 | { |
3308 | int i; | |
3309 | ||
3310 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3311 | return 0; | |
3312 | ||
74ed0bb4 | 3313 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3314 | return 0; |
3315 | ||
3316 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3317 | return 0; | |
3318 | ||
3319 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3320 | { | |
3321 | int pos; | |
3322 | struct type *field_type; | |
3323 | ||
3324 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3325 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3326 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3327 | continue; | |
3328 | ||
3329 | /* If we have gone past the offset, there is no double to pass. */ | |
3330 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3331 | if (pos > offset) | |
3332 | return 0; | |
3333 | ||
3334 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3335 | ||
3336 | /* If this field is entirely before the requested offset, go | |
3337 | on to the next one. */ | |
3338 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3339 | continue; | |
3340 | ||
3341 | /* If this is our special aligned double, we can stop. */ | |
3342 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3343 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3344 | return 1; | |
3345 | ||
3346 | /* This field starts at or before the requested offset, and | |
3347 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3348 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3349 | } |
3350 | ||
3351 | return 0; | |
3352 | } | |
3353 | ||
f7ab6ec6 | 3354 | static CORE_ADDR |
7d9b040b | 3355 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3356 | struct regcache *regcache, CORE_ADDR bp_addr, |
3357 | int nargs, struct value **args, CORE_ADDR sp, | |
3358 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3359 | { |
3360 | int argreg; | |
3361 | int float_argreg; | |
3362 | int argnum; | |
3363 | int len = 0; | |
3364 | int stack_offset = 0; | |
480d3dd2 | 3365 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3366 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3367 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3368 | |
25ab4790 AC |
3369 | /* For shared libraries, "t9" needs to point at the function |
3370 | address. */ | |
4c7d22cb | 3371 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3372 | |
3373 | /* Set the return address register to point to the entry point of | |
3374 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3375 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3376 | |
cb3d25d1 MS |
3377 | /* First ensure that the stack and structure return address (if any) |
3378 | are properly aligned. The stack has to be at least 64-bit | |
3379 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3380 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3381 | aligned, so we round to this widest known alignment. */ | |
3382 | ||
5b03f266 AC |
3383 | sp = align_down (sp, 16); |
3384 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3385 | |
3386 | /* Now make space on the stack for the args. */ | |
3387 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3388 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3389 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3390 | |
3391 | if (mips_debug) | |
6d82d43b | 3392 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3393 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3394 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3395 | |
3396 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3397 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3398 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3399 | |
46e0f506 | 3400 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3401 | if (struct_return) |
3402 | { | |
3403 | if (mips_debug) | |
3404 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3405 | "mips_n32n64_push_dummy_call: " |
3406 | "struct_return reg=%d %s\n", | |
5af949e3 | 3407 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3408 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3409 | } |
3410 | ||
3411 | /* Now load as many as possible of the first arguments into | |
3412 | registers, and push the rest onto the stack. Loop thru args | |
3413 | from first to last. */ | |
3414 | for (argnum = 0; argnum < nargs; argnum++) | |
3415 | { | |
47a35522 | 3416 | const gdb_byte *val; |
cb3d25d1 | 3417 | struct value *arg = args[argnum]; |
4991999e | 3418 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3419 | int len = TYPE_LENGTH (arg_type); |
3420 | enum type_code typecode = TYPE_CODE (arg_type); | |
3421 | ||
3422 | if (mips_debug) | |
3423 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3424 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3425 | argnum + 1, len, (int) typecode); |
3426 | ||
47a35522 | 3427 | val = value_contents (arg); |
cb3d25d1 | 3428 | |
5b68030f JM |
3429 | /* A 128-bit long double value requires an even-odd pair of |
3430 | floating-point registers. */ | |
3431 | if (len == 16 | |
3432 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3433 | && (float_argreg & 1)) | |
3434 | { | |
3435 | float_argreg++; | |
3436 | argreg++; | |
3437 | } | |
3438 | ||
74ed0bb4 MD |
3439 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3440 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3441 | { |
3442 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3443 | in a single register or a pair of registers. */ |
3444 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3445 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3446 | if (mips_debug) |
3447 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3448 | float_argreg, phex (regval, reglen)); |
8d26208a | 3449 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3450 | |
3451 | if (mips_debug) | |
3452 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3453 | argreg, phex (regval, reglen)); |
9c9acae0 | 3454 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3455 | float_argreg++; |
3456 | argreg++; | |
5b68030f JM |
3457 | if (len == 16) |
3458 | { | |
e17a4113 UW |
3459 | regval = extract_unsigned_integer (val + reglen, |
3460 | reglen, byte_order); | |
5b68030f JM |
3461 | if (mips_debug) |
3462 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3463 | float_argreg, phex (regval, reglen)); | |
3464 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3465 | ||
3466 | if (mips_debug) | |
3467 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3468 | argreg, phex (regval, reglen)); | |
3469 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3470 | float_argreg++; | |
3471 | argreg++; | |
3472 | } | |
cb3d25d1 MS |
3473 | } |
3474 | else | |
3475 | { | |
3476 | /* Copy the argument to general registers or the stack in | |
3477 | register-sized pieces. Large arguments are split between | |
3478 | registers and stack. */ | |
ab2e1992 MR |
3479 | /* For N32/N64, structs, unions, or other composite types are |
3480 | treated as a sequence of doublewords, and are passed in integer | |
3481 | or floating point registers as though they were simple scalar | |
3482 | parameters to the extent that they fit, with any excess on the | |
3483 | stack packed according to the normal memory layout of the | |
3484 | object. | |
3485 | The caller does not reserve space for the register arguments; | |
3486 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3487 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3488 | register are only written to memory. */ |
cb3d25d1 MS |
3489 | while (len > 0) |
3490 | { | |
ad018eee | 3491 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3492 | int stack_used_p = 0; |
1a69e1e4 | 3493 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3494 | |
3495 | if (mips_debug) | |
3496 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3497 | partial_len); | |
3498 | ||
74ed0bb4 MD |
3499 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3500 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3501 | |
cb3d25d1 | 3502 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3503 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3504 | { |
3505 | /* Should shorter than int integer values be | |
025bb325 | 3506 | promoted to int before being stored? */ |
cb3d25d1 MS |
3507 | int longword_offset = 0; |
3508 | CORE_ADDR addr; | |
3509 | stack_used_p = 1; | |
72a155b4 | 3510 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3511 | { |
1a69e1e4 | 3512 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3513 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3514 | && len <= 4) |
3515 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3516 | } |
3517 | ||
3518 | if (mips_debug) | |
3519 | { | |
5af949e3 UW |
3520 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3521 | paddress (gdbarch, stack_offset)); | |
3522 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3523 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3524 | } |
3525 | ||
3526 | addr = sp + stack_offset + longword_offset; | |
3527 | ||
3528 | if (mips_debug) | |
3529 | { | |
3530 | int i; | |
5af949e3 UW |
3531 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3532 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3533 | for (i = 0; i < partial_len; i++) |
3534 | { | |
6d82d43b | 3535 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3536 | val[i] & 0xff); |
3537 | } | |
3538 | } | |
3539 | write_memory (addr, val, partial_len); | |
3540 | } | |
3541 | ||
3542 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3543 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3544 | /* Write this portion of the argument to a general |
6d82d43b | 3545 | purpose register. */ |
74ed0bb4 | 3546 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3547 | { |
5863b5d5 MR |
3548 | LONGEST regval; |
3549 | ||
3550 | /* Sign extend pointers, 32-bit integers and signed | |
3551 | 16-bit and 8-bit integers; everything else is taken | |
3552 | as is. */ | |
3553 | ||
3554 | if ((partial_len == 4 | |
3555 | && (typecode == TYPE_CODE_PTR | |
3556 | || typecode == TYPE_CODE_INT)) | |
3557 | || (partial_len < 4 | |
3558 | && typecode == TYPE_CODE_INT | |
3559 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3560 | regval = extract_signed_integer (val, partial_len, |
3561 | byte_order); | |
5863b5d5 | 3562 | else |
e17a4113 UW |
3563 | regval = extract_unsigned_integer (val, partial_len, |
3564 | byte_order); | |
cb3d25d1 MS |
3565 | |
3566 | /* A non-floating-point argument being passed in a | |
3567 | general register. If a struct or union, and if | |
3568 | the remaining length is smaller than the register | |
3569 | size, we have to adjust the register value on | |
3570 | big endian targets. | |
3571 | ||
3572 | It does not seem to be necessary to do the | |
1a69e1e4 | 3573 | same for integral types. */ |
cb3d25d1 | 3574 | |
72a155b4 | 3575 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3576 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3577 | && (typecode == TYPE_CODE_STRUCT |
3578 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3579 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3580 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3581 | |
3582 | if (mips_debug) | |
3583 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3584 | argreg, | |
1a69e1e4 | 3585 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3586 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3587 | |
74ed0bb4 | 3588 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3589 | TYPE_LENGTH (arg_type) - len)) |
3590 | { | |
3591 | if (mips_debug) | |
3592 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3593 | float_argreg, | |
3594 | phex (regval, MIPS64_REGSIZE)); | |
3595 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3596 | regval); | |
3597 | } | |
3598 | ||
3599 | float_argreg++; | |
cb3d25d1 MS |
3600 | argreg++; |
3601 | } | |
3602 | ||
3603 | len -= partial_len; | |
3604 | val += partial_len; | |
3605 | ||
b021a221 MS |
3606 | /* Compute the offset into the stack at which we will |
3607 | copy the next parameter. | |
cb3d25d1 MS |
3608 | |
3609 | In N32 (N64?), the stack_offset only needs to be | |
3610 | adjusted when it has been used. */ | |
3611 | ||
3612 | if (stack_used_p) | |
1a69e1e4 | 3613 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3614 | } |
3615 | } | |
3616 | if (mips_debug) | |
3617 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3618 | } | |
3619 | ||
f10683bb | 3620 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3621 | |
cb3d25d1 MS |
3622 | /* Return adjusted stack pointer. */ |
3623 | return sp; | |
3624 | } | |
3625 | ||
6d82d43b | 3626 | static enum return_value_convention |
c055b101 | 3627 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3628 | struct type *type, struct regcache *regcache, |
47a35522 | 3629 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3630 | { |
72a155b4 | 3631 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3632 | |
3633 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3634 | ||
3635 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3636 | if needed), as appropriate for the type. Composite results (struct, | |
3637 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3638 | following rules: | |
3639 | ||
3640 | * A struct with only one or two floating point fields is returned in $f0 | |
3641 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3642 | case. | |
3643 | ||
f08877ba | 3644 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
3645 | $2 (first 64 bits) and $3 (remainder, if necessary). |
3646 | ||
3647 | * Larger composite results are handled by converting the function to a | |
3648 | procedure with an implicit first parameter, which is a pointer to an area | |
3649 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3650 | that all composite results be handled by conversion to implicit first | |
3651 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3652 | specific exception to return COMPLEX results in the floating point | |
3653 | registers.] */ | |
3654 | ||
f08877ba | 3655 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3656 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3657 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3658 | && TYPE_LENGTH (type) == 16 | |
3659 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3660 | { | |
3661 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3662 | two registers are used in the same as memory order, so the | |
3663 | eight bytes with the lower memory address are in $f0. */ | |
3664 | if (mips_debug) | |
3665 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3666 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3667 | gdbarch_num_regs (gdbarch) |
3668 | + mips_regnum (gdbarch)->fp0, | |
3669 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3670 | readbuf, writebuf, 0); |
ba32f989 | 3671 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3672 | gdbarch_num_regs (gdbarch) |
3673 | + mips_regnum (gdbarch)->fp0 + 2, | |
3674 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3675 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3676 | writebuf ? writebuf + 8 : writebuf, 0); |
3677 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3678 | } | |
6d82d43b AC |
3679 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3680 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3681 | { | |
59aa1faa | 3682 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3683 | if (mips_debug) |
3684 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3685 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3686 | gdbarch_num_regs (gdbarch) |
3687 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3688 | TYPE_LENGTH (type), |
72a155b4 | 3689 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3690 | readbuf, writebuf, 0); |
6d82d43b AC |
3691 | return RETURN_VALUE_REGISTER_CONVENTION; |
3692 | } | |
3693 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3694 | && TYPE_NFIELDS (type) <= 2 | |
3695 | && TYPE_NFIELDS (type) >= 1 | |
3696 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3697 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3698 | == TYPE_CODE_FLT)) |
3699 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3700 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3701 | == TYPE_CODE_FLT) |
b18bb924 | 3702 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3703 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3704 | { |
3705 | /* A struct that contains one or two floats. Each value is part | |
3706 | in the least significant part of their floating point | |
5b68030f | 3707 | register (or GPR, for soft float). */ |
6d82d43b AC |
3708 | int regnum; |
3709 | int field; | |
5b68030f JM |
3710 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3711 | ? mips_regnum (gdbarch)->fp0 | |
3712 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3713 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3714 | { | |
3715 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3716 | / TARGET_CHAR_BIT); | |
3717 | if (mips_debug) | |
3718 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3719 | offset); | |
5b68030f JM |
3720 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3721 | { | |
3722 | /* A 16-byte long double field goes in two consecutive | |
3723 | registers. */ | |
3724 | mips_xfer_register (gdbarch, regcache, | |
3725 | gdbarch_num_regs (gdbarch) + regnum, | |
3726 | 8, | |
3727 | gdbarch_byte_order (gdbarch), | |
3728 | readbuf, writebuf, offset); | |
3729 | mips_xfer_register (gdbarch, regcache, | |
3730 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3731 | 8, | |
3732 | gdbarch_byte_order (gdbarch), | |
3733 | readbuf, writebuf, offset + 8); | |
3734 | } | |
3735 | else | |
3736 | mips_xfer_register (gdbarch, regcache, | |
3737 | gdbarch_num_regs (gdbarch) + regnum, | |
3738 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3739 | gdbarch_byte_order (gdbarch), | |
3740 | readbuf, writebuf, offset); | |
6d82d43b AC |
3741 | } |
3742 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3743 | } | |
3744 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
3745 | || TYPE_CODE (type) == TYPE_CODE_UNION |
3746 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 3747 | { |
f08877ba | 3748 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
3749 | regardless of the byte order. I.e. DO NOT USE |
3750 | mips_xfer_lower. */ | |
3751 | int offset; | |
3752 | int regnum; | |
4c7d22cb | 3753 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3754 | offset < TYPE_LENGTH (type); |
72a155b4 | 3755 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3756 | { |
72a155b4 | 3757 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3758 | if (offset + xfer > TYPE_LENGTH (type)) |
3759 | xfer = TYPE_LENGTH (type) - offset; | |
3760 | if (mips_debug) | |
3761 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3762 | offset, xfer, regnum); | |
ba32f989 DJ |
3763 | mips_xfer_register (gdbarch, regcache, |
3764 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3765 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3766 | offset); | |
6d82d43b AC |
3767 | } |
3768 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3769 | } | |
3770 | else | |
3771 | { | |
3772 | /* A scalar extract each part but least-significant-byte | |
3773 | justified. */ | |
3774 | int offset; | |
3775 | int regnum; | |
4c7d22cb | 3776 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3777 | offset < TYPE_LENGTH (type); |
72a155b4 | 3778 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3779 | { |
72a155b4 | 3780 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3781 | if (offset + xfer > TYPE_LENGTH (type)) |
3782 | xfer = TYPE_LENGTH (type) - offset; | |
3783 | if (mips_debug) | |
3784 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3785 | offset, xfer, regnum); | |
ba32f989 DJ |
3786 | mips_xfer_register (gdbarch, regcache, |
3787 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3788 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3789 | readbuf, writebuf, offset); |
6d82d43b AC |
3790 | } |
3791 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3792 | } | |
3793 | } | |
3794 | ||
3795 | /* O32 ABI stuff. */ | |
3796 | ||
3797 | static CORE_ADDR | |
7d9b040b | 3798 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3799 | struct regcache *regcache, CORE_ADDR bp_addr, |
3800 | int nargs, struct value **args, CORE_ADDR sp, | |
3801 | int struct_return, CORE_ADDR struct_addr) | |
3802 | { | |
3803 | int argreg; | |
3804 | int float_argreg; | |
3805 | int argnum; | |
3806 | int len = 0; | |
3807 | int stack_offset = 0; | |
3808 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3809 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3810 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3811 | |
3812 | /* For shared libraries, "t9" needs to point at the function | |
3813 | address. */ | |
4c7d22cb | 3814 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3815 | |
3816 | /* Set the return address register to point to the entry point of | |
3817 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3818 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3819 | |
3820 | /* First ensure that the stack and structure return address (if any) | |
3821 | are properly aligned. The stack has to be at least 64-bit | |
3822 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3823 | aligned. For n32 and n64, stack frames need to be 128-bit |
3824 | aligned, so we round to this widest known alignment. */ | |
3825 | ||
5b03f266 AC |
3826 | sp = align_down (sp, 16); |
3827 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3828 | |
3829 | /* Now make space on the stack for the args. */ | |
3830 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3831 | { |
3832 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3833 | int arglen = TYPE_LENGTH (arg_type); | |
3834 | ||
3835 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3836 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3837 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3838 | /* Allocate space on the stack. */ |
1a69e1e4 | 3839 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3840 | } |
5b03f266 | 3841 | sp -= align_up (len, 16); |
ebafbe83 MS |
3842 | |
3843 | if (mips_debug) | |
6d82d43b | 3844 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3845 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3846 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3847 | |
3848 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3849 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3850 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3851 | |
bcb0cc15 | 3852 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3853 | if (struct_return) |
3854 | { | |
3855 | if (mips_debug) | |
3856 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3857 | "mips_o32_push_dummy_call: " |
3858 | "struct_return reg=%d %s\n", | |
5af949e3 | 3859 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3860 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3861 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3862 | } |
3863 | ||
3864 | /* Now load as many as possible of the first arguments into | |
3865 | registers, and push the rest onto the stack. Loop thru args | |
3866 | from first to last. */ | |
3867 | for (argnum = 0; argnum < nargs; argnum++) | |
3868 | { | |
47a35522 | 3869 | const gdb_byte *val; |
ebafbe83 | 3870 | struct value *arg = args[argnum]; |
4991999e | 3871 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3872 | int len = TYPE_LENGTH (arg_type); |
3873 | enum type_code typecode = TYPE_CODE (arg_type); | |
3874 | ||
3875 | if (mips_debug) | |
3876 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3877 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3878 | argnum + 1, len, (int) typecode); |
3879 | ||
47a35522 | 3880 | val = value_contents (arg); |
46cac009 AC |
3881 | |
3882 | /* 32-bit ABIs always start floating point arguments in an | |
3883 | even-numbered floating point register. Round the FP register | |
3884 | up before the check to see if there are any FP registers | |
3885 | left. O32/O64 targets also pass the FP in the integer | |
3886 | registers so also round up normal registers. */ | |
74ed0bb4 | 3887 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3888 | { |
3889 | if ((float_argreg & 1)) | |
3890 | float_argreg++; | |
3891 | } | |
3892 | ||
3893 | /* Floating point arguments passed in registers have to be | |
3894 | treated specially. On 32-bit architectures, doubles | |
3895 | are passed in register pairs; the even register gets | |
3896 | the low word, and the odd register gets the high word. | |
3897 | On O32/O64, the first two floating point arguments are | |
3898 | also copied to general registers, because MIPS16 functions | |
3899 | don't use float registers for arguments. This duplication of | |
3900 | arguments in general registers can't hurt non-MIPS16 functions | |
3901 | because those registers are normally skipped. */ | |
3902 | ||
74ed0bb4 MD |
3903 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3904 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3905 | { |
8b07f6d8 | 3906 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3907 | { |
72a155b4 | 3908 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3909 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3910 | unsigned long regval; |
3911 | ||
3912 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
3913 | regval = extract_unsigned_integer (val + low_offset, |
3914 | 4, byte_order); | |
46cac009 AC |
3915 | if (mips_debug) |
3916 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3917 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3918 | regcache_cooked_write_unsigned (regcache, |
3919 | float_argreg++, regval); | |
46cac009 AC |
3920 | if (mips_debug) |
3921 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3922 | argreg, phex (regval, 4)); | |
9c9acae0 | 3923 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3924 | |
3925 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
3926 | regval = extract_unsigned_integer (val + 4 - low_offset, |
3927 | 4, byte_order); | |
46cac009 AC |
3928 | if (mips_debug) |
3929 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3930 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3931 | regcache_cooked_write_unsigned (regcache, |
3932 | float_argreg++, regval); | |
46cac009 AC |
3933 | |
3934 | if (mips_debug) | |
3935 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3936 | argreg, phex (regval, 4)); | |
9c9acae0 | 3937 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3938 | } |
3939 | else | |
3940 | { | |
3941 | /* This is a floating point value that fits entirely | |
3942 | in a single register. */ | |
3943 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3944 | above to ensure that it is even register aligned. */ |
e17a4113 | 3945 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
3946 | if (mips_debug) |
3947 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3948 | float_argreg, phex (regval, len)); | |
025bb325 MS |
3949 | regcache_cooked_write_unsigned (regcache, |
3950 | float_argreg++, regval); | |
5b68030f JM |
3951 | /* Although two FP registers are reserved for each |
3952 | argument, only one corresponding integer register is | |
3953 | reserved. */ | |
46cac009 AC |
3954 | if (mips_debug) |
3955 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3956 | argreg, phex (regval, len)); | |
5b68030f | 3957 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3958 | } |
3959 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3960 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3961 | } |
3962 | else | |
3963 | { | |
3964 | /* Copy the argument to general registers or the stack in | |
3965 | register-sized pieces. Large arguments are split between | |
3966 | registers and stack. */ | |
1a69e1e4 DJ |
3967 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3968 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3969 | them in registers where gcc sometimes puts them on the |
3970 | stack. For maximum compatibility, we will put them in | |
3971 | both places. */ | |
1a69e1e4 DJ |
3972 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3973 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3974 | /* Structures should be aligned to eight bytes (even arg registers) |
3975 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3976 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3977 | { |
3978 | if ((argreg & 1)) | |
968b5391 MR |
3979 | { |
3980 | argreg++; | |
1a69e1e4 | 3981 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3982 | } |
46cac009 | 3983 | } |
46cac009 AC |
3984 | while (len > 0) |
3985 | { | |
3986 | /* Remember if the argument was written to the stack. */ | |
3987 | int stack_used_p = 0; | |
1a69e1e4 | 3988 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3989 | |
3990 | if (mips_debug) | |
3991 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3992 | partial_len); | |
3993 | ||
3994 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3995 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3996 | || odd_sized_struct) |
46cac009 AC |
3997 | { |
3998 | /* Should shorter than int integer values be | |
025bb325 | 3999 | promoted to int before being stored? */ |
46cac009 AC |
4000 | int longword_offset = 0; |
4001 | CORE_ADDR addr; | |
4002 | stack_used_p = 1; | |
46cac009 AC |
4003 | |
4004 | if (mips_debug) | |
4005 | { | |
5af949e3 UW |
4006 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4007 | paddress (gdbarch, stack_offset)); | |
4008 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4009 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
4010 | } |
4011 | ||
4012 | addr = sp + stack_offset + longword_offset; | |
4013 | ||
4014 | if (mips_debug) | |
4015 | { | |
4016 | int i; | |
5af949e3 UW |
4017 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4018 | paddress (gdbarch, addr)); | |
46cac009 AC |
4019 | for (i = 0; i < partial_len; i++) |
4020 | { | |
6d82d43b | 4021 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
4022 | val[i] & 0xff); |
4023 | } | |
4024 | } | |
4025 | write_memory (addr, val, partial_len); | |
4026 | } | |
4027 | ||
4028 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4029 | structs may go thru BOTH paths. */ |
46cac009 | 4030 | /* Write this portion of the argument to a general |
6d82d43b | 4031 | purpose register. */ |
74ed0bb4 | 4032 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 4033 | { |
e17a4113 UW |
4034 | LONGEST regval = extract_signed_integer (val, partial_len, |
4035 | byte_order); | |
4246e332 | 4036 | /* Value may need to be sign extended, because |
1b13c4f6 | 4037 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
4038 | |
4039 | /* A non-floating-point argument being passed in a | |
4040 | general register. If a struct or union, and if | |
4041 | the remaining length is smaller than the register | |
4042 | size, we have to adjust the register value on | |
4043 | big endian targets. | |
4044 | ||
4045 | It does not seem to be necessary to do the | |
4046 | same for integral types. | |
4047 | ||
4048 | Also don't do this adjustment on O64 binaries. | |
4049 | ||
4050 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4051 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
4052 | mips_abi_regsize(), generates a left shift |
4053 | as part of storing the argument in a register | |
4054 | (the left shift isn't generated when | |
1b13c4f6 | 4055 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4056 | it is quite possible that this is GCC |
4057 | contradicting the LE/O32 ABI, GDB has not been | |
4058 | adjusted to accommodate this. Either someone | |
4059 | needs to demonstrate that the LE/O32 ABI | |
4060 | specifies such a left shift OR this new ABI gets | |
4061 | identified as such and GDB gets tweaked | |
4062 | accordingly. */ | |
4063 | ||
72a155b4 | 4064 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4065 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
4066 | && (typecode == TYPE_CODE_STRUCT |
4067 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4068 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 4069 | * TARGET_CHAR_BIT); |
46cac009 AC |
4070 | |
4071 | if (mips_debug) | |
4072 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4073 | argreg, | |
1a69e1e4 | 4074 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 4075 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
4076 | argreg++; |
4077 | ||
4078 | /* Prevent subsequent floating point arguments from | |
4079 | being passed in floating point registers. */ | |
74ed0bb4 | 4080 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
4081 | } |
4082 | ||
4083 | len -= partial_len; | |
4084 | val += partial_len; | |
4085 | ||
b021a221 MS |
4086 | /* Compute the offset into the stack at which we will |
4087 | copy the next parameter. | |
46cac009 | 4088 | |
6d82d43b AC |
4089 | In older ABIs, the caller reserved space for |
4090 | registers that contained arguments. This was loosely | |
4091 | refered to as their "home". Consequently, space is | |
4092 | always allocated. */ | |
46cac009 | 4093 | |
1a69e1e4 | 4094 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
4095 | } |
4096 | } | |
4097 | if (mips_debug) | |
4098 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4099 | } | |
4100 | ||
f10683bb | 4101 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4102 | |
46cac009 AC |
4103 | /* Return adjusted stack pointer. */ |
4104 | return sp; | |
4105 | } | |
4106 | ||
6d82d43b | 4107 | static enum return_value_convention |
c055b101 CV |
4108 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
4109 | struct type *type, struct regcache *regcache, | |
47a35522 | 4110 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4111 | { |
72a155b4 | 4112 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
4113 | |
4114 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4115 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4116 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4117 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4118 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4119 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4120 | { | |
4121 | /* A single-precision floating-point value. It fits in the | |
4122 | least significant part of FP0. */ | |
4123 | if (mips_debug) | |
4124 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4125 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4126 | gdbarch_num_regs (gdbarch) |
4127 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 4128 | TYPE_LENGTH (type), |
72a155b4 | 4129 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4130 | readbuf, writebuf, 0); |
6d82d43b AC |
4131 | return RETURN_VALUE_REGISTER_CONVENTION; |
4132 | } | |
4133 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4134 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4135 | { | |
4136 | /* A double-precision floating-point value. The most | |
4137 | significant part goes in FP1, and the least significant in | |
4138 | FP0. */ | |
4139 | if (mips_debug) | |
4140 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 4141 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
4142 | { |
4143 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 4144 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4145 | gdbarch_num_regs (gdbarch) |
4146 | + mips_regnum (gdbarch)->fp0 + | |
4147 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4148 | readbuf, writebuf, 0); |
ba32f989 | 4149 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4150 | gdbarch_num_regs (gdbarch) |
4151 | + mips_regnum (gdbarch)->fp0 + 1, | |
4152 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4153 | readbuf, writebuf, 4); |
6d82d43b AC |
4154 | break; |
4155 | case BFD_ENDIAN_BIG: | |
ba32f989 | 4156 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4157 | gdbarch_num_regs (gdbarch) |
4158 | + mips_regnum (gdbarch)->fp0 + 1, | |
4159 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4160 | readbuf, writebuf, 0); |
ba32f989 | 4161 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4162 | gdbarch_num_regs (gdbarch) |
4163 | + mips_regnum (gdbarch)->fp0 + 0, | |
4164 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4165 | readbuf, writebuf, 4); |
6d82d43b AC |
4166 | break; |
4167 | default: | |
e2e0b3e5 | 4168 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
4169 | } |
4170 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4171 | } | |
4172 | #if 0 | |
4173 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4174 | && TYPE_NFIELDS (type) <= 2 | |
4175 | && TYPE_NFIELDS (type) >= 1 | |
4176 | && ((TYPE_NFIELDS (type) == 1 | |
4177 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4178 | == TYPE_CODE_FLT)) | |
4179 | || (TYPE_NFIELDS (type) == 2 | |
4180 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4181 | == TYPE_CODE_FLT) | |
4182 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4183 | == TYPE_CODE_FLT))) | |
4184 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4185 | { | |
4186 | /* A struct that contains one or two floats. Each value is part | |
4187 | in the least significant part of their floating point | |
4188 | register.. */ | |
870cd05e | 4189 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
4190 | int regnum; |
4191 | int field; | |
72a155b4 | 4192 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
4193 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4194 | { | |
4195 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4196 | / TARGET_CHAR_BIT); | |
4197 | if (mips_debug) | |
4198 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4199 | offset); | |
ba32f989 DJ |
4200 | mips_xfer_register (gdbarch, regcache, |
4201 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 4202 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 4203 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4204 | readbuf, writebuf, offset); |
6d82d43b AC |
4205 | } |
4206 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4207 | } | |
4208 | #endif | |
4209 | #if 0 | |
4210 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4211 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4212 | { | |
4213 | /* A structure or union. Extract the left justified value, | |
4214 | regardless of the byte order. I.e. DO NOT USE | |
4215 | mips_xfer_lower. */ | |
4216 | int offset; | |
4217 | int regnum; | |
4c7d22cb | 4218 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4219 | offset < TYPE_LENGTH (type); |
72a155b4 | 4220 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 4221 | { |
72a155b4 | 4222 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
4223 | if (offset + xfer > TYPE_LENGTH (type)) |
4224 | xfer = TYPE_LENGTH (type) - offset; | |
4225 | if (mips_debug) | |
4226 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4227 | offset, xfer, regnum); | |
ba32f989 DJ |
4228 | mips_xfer_register (gdbarch, regcache, |
4229 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
4230 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
4231 | } | |
4232 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4233 | } | |
4234 | #endif | |
4235 | else | |
4236 | { | |
4237 | /* A scalar extract each part but least-significant-byte | |
4238 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 4239 | the ISA. */ |
6d82d43b AC |
4240 | int offset; |
4241 | int regnum; | |
4c7d22cb | 4242 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4243 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 4244 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 4245 | { |
1a69e1e4 | 4246 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
4247 | if (offset + xfer > TYPE_LENGTH (type)) |
4248 | xfer = TYPE_LENGTH (type) - offset; | |
4249 | if (mips_debug) | |
4250 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4251 | offset, xfer, regnum); | |
ba32f989 DJ |
4252 | mips_xfer_register (gdbarch, regcache, |
4253 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 4254 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4255 | readbuf, writebuf, offset); |
6d82d43b AC |
4256 | } |
4257 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4258 | } | |
4259 | } | |
4260 | ||
4261 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4262 | ABI. */ | |
46cac009 AC |
4263 | |
4264 | static CORE_ADDR | |
7d9b040b | 4265 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4266 | struct regcache *regcache, CORE_ADDR bp_addr, |
4267 | int nargs, | |
4268 | struct value **args, CORE_ADDR sp, | |
4269 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4270 | { |
4271 | int argreg; | |
4272 | int float_argreg; | |
4273 | int argnum; | |
4274 | int len = 0; | |
4275 | int stack_offset = 0; | |
480d3dd2 | 4276 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4277 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4278 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4279 | |
25ab4790 AC |
4280 | /* For shared libraries, "t9" needs to point at the function |
4281 | address. */ | |
4c7d22cb | 4282 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4283 | |
4284 | /* Set the return address register to point to the entry point of | |
4285 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4286 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4287 | |
46cac009 AC |
4288 | /* First ensure that the stack and structure return address (if any) |
4289 | are properly aligned. The stack has to be at least 64-bit | |
4290 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4291 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4292 | aligned, so we round to this widest known alignment. */ | |
4293 | ||
5b03f266 AC |
4294 | sp = align_down (sp, 16); |
4295 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4296 | |
4297 | /* Now make space on the stack for the args. */ | |
4298 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4299 | { |
4300 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4301 | int arglen = TYPE_LENGTH (arg_type); | |
4302 | ||
968b5391 | 4303 | /* Allocate space on the stack. */ |
1a69e1e4 | 4304 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4305 | } |
5b03f266 | 4306 | sp -= align_up (len, 16); |
46cac009 AC |
4307 | |
4308 | if (mips_debug) | |
6d82d43b | 4309 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4310 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4311 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4312 | |
4313 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4314 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4315 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4316 | |
4317 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4318 | if (struct_return) | |
4319 | { | |
4320 | if (mips_debug) | |
4321 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4322 | "mips_o64_push_dummy_call: " |
4323 | "struct_return reg=%d %s\n", | |
5af949e3 | 4324 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4325 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4326 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4327 | } |
4328 | ||
4329 | /* Now load as many as possible of the first arguments into | |
4330 | registers, and push the rest onto the stack. Loop thru args | |
4331 | from first to last. */ | |
4332 | for (argnum = 0; argnum < nargs; argnum++) | |
4333 | { | |
47a35522 | 4334 | const gdb_byte *val; |
930bd0e0 | 4335 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 4336 | struct value *arg = args[argnum]; |
4991999e | 4337 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4338 | int len = TYPE_LENGTH (arg_type); |
4339 | enum type_code typecode = TYPE_CODE (arg_type); | |
4340 | ||
4341 | if (mips_debug) | |
4342 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4343 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4344 | argnum + 1, len, (int) typecode); |
4345 | ||
47a35522 | 4346 | val = value_contents (arg); |
ebafbe83 | 4347 | |
930bd0e0 KB |
4348 | /* Function pointer arguments to mips16 code need to be made into |
4349 | mips16 pointers. */ | |
4350 | if (typecode == TYPE_CODE_PTR | |
4351 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4352 | { | |
4353 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4354 | len, byte_order); | |
4355 | if (mips_pc_is_mips16 (addr)) | |
4356 | { | |
4357 | store_signed_integer (valbuf, len, byte_order, | |
4358 | make_mips16_addr (addr)); | |
4359 | val = valbuf; | |
4360 | } | |
4361 | } | |
4362 | ||
ebafbe83 MS |
4363 | /* Floating point arguments passed in registers have to be |
4364 | treated specially. On 32-bit architectures, doubles | |
4365 | are passed in register pairs; the even register gets | |
4366 | the low word, and the odd register gets the high word. | |
4367 | On O32/O64, the first two floating point arguments are | |
4368 | also copied to general registers, because MIPS16 functions | |
4369 | don't use float registers for arguments. This duplication of | |
4370 | arguments in general registers can't hurt non-MIPS16 functions | |
4371 | because those registers are normally skipped. */ | |
4372 | ||
74ed0bb4 MD |
4373 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4374 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4375 | { |
e17a4113 | 4376 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4377 | if (mips_debug) |
4378 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4379 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4380 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4381 | if (mips_debug) |
4382 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4383 | argreg, phex (regval, len)); | |
9c9acae0 | 4384 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4385 | argreg++; |
ebafbe83 | 4386 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4387 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4388 | } |
4389 | else | |
4390 | { | |
4391 | /* Copy the argument to general registers or the stack in | |
4392 | register-sized pieces. Large arguments are split between | |
4393 | registers and stack. */ | |
1a69e1e4 | 4394 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4395 | are treated specially: Irix cc passes them in registers |
4396 | where gcc sometimes puts them on the stack. For maximum | |
4397 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4398 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4399 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4400 | while (len > 0) |
4401 | { | |
4402 | /* Remember if the argument was written to the stack. */ | |
4403 | int stack_used_p = 0; | |
1a69e1e4 | 4404 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4405 | |
4406 | if (mips_debug) | |
4407 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4408 | partial_len); | |
4409 | ||
4410 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4411 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4412 | || odd_sized_struct) |
ebafbe83 MS |
4413 | { |
4414 | /* Should shorter than int integer values be | |
025bb325 | 4415 | promoted to int before being stored? */ |
ebafbe83 MS |
4416 | int longword_offset = 0; |
4417 | CORE_ADDR addr; | |
4418 | stack_used_p = 1; | |
72a155b4 | 4419 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4420 | { |
1a69e1e4 DJ |
4421 | if ((typecode == TYPE_CODE_INT |
4422 | || typecode == TYPE_CODE_PTR | |
4423 | || typecode == TYPE_CODE_FLT) | |
4424 | && len <= 4) | |
4425 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4426 | } |
4427 | ||
4428 | if (mips_debug) | |
4429 | { | |
5af949e3 UW |
4430 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4431 | paddress (gdbarch, stack_offset)); | |
4432 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4433 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4434 | } |
4435 | ||
4436 | addr = sp + stack_offset + longword_offset; | |
4437 | ||
4438 | if (mips_debug) | |
4439 | { | |
4440 | int i; | |
5af949e3 UW |
4441 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4442 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4443 | for (i = 0; i < partial_len; i++) |
4444 | { | |
6d82d43b | 4445 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4446 | val[i] & 0xff); |
4447 | } | |
4448 | } | |
4449 | write_memory (addr, val, partial_len); | |
4450 | } | |
4451 | ||
4452 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4453 | structs may go thru BOTH paths. */ |
ebafbe83 | 4454 | /* Write this portion of the argument to a general |
6d82d43b | 4455 | purpose register. */ |
74ed0bb4 | 4456 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4457 | { |
e17a4113 UW |
4458 | LONGEST regval = extract_signed_integer (val, partial_len, |
4459 | byte_order); | |
4246e332 | 4460 | /* Value may need to be sign extended, because |
1b13c4f6 | 4461 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4462 | |
4463 | /* A non-floating-point argument being passed in a | |
4464 | general register. If a struct or union, and if | |
4465 | the remaining length is smaller than the register | |
4466 | size, we have to adjust the register value on | |
4467 | big endian targets. | |
4468 | ||
4469 | It does not seem to be necessary to do the | |
025bb325 | 4470 | same for integral types. */ |
480d3dd2 | 4471 | |
72a155b4 | 4472 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4473 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4474 | && (typecode == TYPE_CODE_STRUCT |
4475 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4476 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4477 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4478 | |
4479 | if (mips_debug) | |
4480 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4481 | argreg, | |
1a69e1e4 | 4482 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4483 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4484 | argreg++; |
4485 | ||
4486 | /* Prevent subsequent floating point arguments from | |
4487 | being passed in floating point registers. */ | |
74ed0bb4 | 4488 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4489 | } |
4490 | ||
4491 | len -= partial_len; | |
4492 | val += partial_len; | |
4493 | ||
b021a221 MS |
4494 | /* Compute the offset into the stack at which we will |
4495 | copy the next parameter. | |
ebafbe83 | 4496 | |
6d82d43b AC |
4497 | In older ABIs, the caller reserved space for |
4498 | registers that contained arguments. This was loosely | |
4499 | refered to as their "home". Consequently, space is | |
4500 | always allocated. */ | |
ebafbe83 | 4501 | |
1a69e1e4 | 4502 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4503 | } |
4504 | } | |
4505 | if (mips_debug) | |
4506 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4507 | } | |
4508 | ||
f10683bb | 4509 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4510 | |
ebafbe83 MS |
4511 | /* Return adjusted stack pointer. */ |
4512 | return sp; | |
4513 | } | |
4514 | ||
9c8fdbfa | 4515 | static enum return_value_convention |
c055b101 | 4516 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4517 | struct type *type, struct regcache *regcache, |
47a35522 | 4518 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4519 | { |
72a155b4 | 4520 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4521 | |
4522 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4523 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4524 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4525 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4526 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4527 | { |
4528 | /* A floating-point value. It fits in the least significant | |
4529 | part of FP0. */ | |
4530 | if (mips_debug) | |
4531 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4532 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4533 | gdbarch_num_regs (gdbarch) |
4534 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4535 | TYPE_LENGTH (type), |
72a155b4 | 4536 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4537 | readbuf, writebuf, 0); |
7a076fd2 FF |
4538 | return RETURN_VALUE_REGISTER_CONVENTION; |
4539 | } | |
4540 | else | |
4541 | { | |
4542 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 4543 | justified. */ |
7a076fd2 FF |
4544 | int offset; |
4545 | int regnum; | |
4546 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4547 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4548 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4549 | { |
1a69e1e4 | 4550 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4551 | if (offset + xfer > TYPE_LENGTH (type)) |
4552 | xfer = TYPE_LENGTH (type) - offset; | |
4553 | if (mips_debug) | |
4554 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4555 | offset, xfer, regnum); | |
ba32f989 DJ |
4556 | mips_xfer_register (gdbarch, regcache, |
4557 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4558 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4559 | readbuf, writebuf, offset); |
7a076fd2 FF |
4560 | } |
4561 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4562 | } | |
6d82d43b AC |
4563 | } |
4564 | ||
dd824b04 DJ |
4565 | /* Floating point register management. |
4566 | ||
4567 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4568 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4569 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4570 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4571 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4572 | double precision floats into two 32-bit chunks and store them in | |
4573 | consecutive fp regs. To display 64-bit floats stored in this | |
4574 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4575 | Throw in user-configurable endianness and you have a real mess. | |
4576 | ||
4577 | The way this works is: | |
4578 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4579 | double-precision value will be split across two logical registers. | |
4580 | The lower-numbered logical register will hold the low-order bits, | |
4581 | regardless of the processor's endianness. | |
4582 | - If we are on a 64-bit processor, and we are looking for a | |
4583 | single-precision value, it will be in the low ordered bits | |
4584 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4585 | save slot in memory. | |
4586 | - If we are in 64-bit mode, everything is straightforward. | |
4587 | ||
4588 | Note that this code only deals with "live" registers at the top of the | |
4589 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 4590 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
4591 | interface that can deal with dynamic saved register sizes -- fp |
4592 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4593 | and below). */ | |
4594 | ||
4595 | /* Copy a 32-bit single-precision value from the current frame | |
4596 | into rare_buffer. */ | |
4597 | ||
4598 | static void | |
e11c53d2 | 4599 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4600 | gdb_byte *rare_buffer) |
dd824b04 | 4601 | { |
72a155b4 UW |
4602 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4603 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4604 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4605 | |
e11c53d2 | 4606 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4607 | error (_("can't read register %d (%s)"), |
72a155b4 | 4608 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4609 | if (raw_size == 8) |
4610 | { | |
4611 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4612 | 32 bits. */ |
dd824b04 DJ |
4613 | int offset; |
4614 | ||
72a155b4 | 4615 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4616 | offset = 4; |
4617 | else | |
4618 | offset = 0; | |
4619 | ||
4620 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4621 | } | |
4622 | else | |
4623 | { | |
4624 | memcpy (rare_buffer, raw_buffer, 4); | |
4625 | } | |
4626 | } | |
4627 | ||
4628 | /* Copy a 64-bit double-precision value from the current frame into | |
4629 | rare_buffer. This may include getting half of it from the next | |
4630 | register. */ | |
4631 | ||
4632 | static void | |
e11c53d2 | 4633 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4634 | gdb_byte *rare_buffer) |
dd824b04 | 4635 | { |
72a155b4 UW |
4636 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4637 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4638 | |
9c9acae0 | 4639 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4640 | { |
4641 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4642 | all 64 bits. */ |
e11c53d2 | 4643 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4644 | error (_("can't read register %d (%s)"), |
72a155b4 | 4645 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4646 | } |
4647 | else | |
4648 | { | |
72a155b4 | 4649 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4650 | |
72a155b4 | 4651 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4652 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4653 | _("mips_read_fp_register_double: bad access to " |
4654 | "odd-numbered FP register")); | |
dd824b04 DJ |
4655 | |
4656 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4657 | each register. */ |
72a155b4 | 4658 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4659 | { |
e11c53d2 AC |
4660 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4661 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4662 | } |
361d1df0 | 4663 | else |
dd824b04 | 4664 | { |
e11c53d2 AC |
4665 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4666 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4667 | } |
4668 | } | |
4669 | } | |
4670 | ||
c906108c | 4671 | static void |
e11c53d2 AC |
4672 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4673 | int regnum) | |
025bb325 | 4674 | { /* Do values for FP (float) regs. */ |
72a155b4 | 4675 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4676 | gdb_byte *raw_buffer; |
025bb325 | 4677 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 4678 | int inv1, inv2; |
c5aa993b | 4679 | |
025bb325 MS |
4680 | raw_buffer = alloca (2 * register_size (gdbarch, |
4681 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 4682 | |
72a155b4 | 4683 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4684 | fprintf_filtered (file, "%*s", |
72a155b4 | 4685 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4686 | ""); |
f0ef6b29 | 4687 | |
72a155b4 | 4688 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4689 | { |
79a45b7d TT |
4690 | struct value_print_options opts; |
4691 | ||
f0ef6b29 KB |
4692 | /* 4-byte registers: Print hex and floating. Also print even |
4693 | numbered registers as doubles. */ | |
e11c53d2 | 4694 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
4695 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4696 | raw_buffer, &inv1); | |
c5aa993b | 4697 | |
79a45b7d | 4698 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4699 | print_scalar_formatted (raw_buffer, |
4700 | builtin_type (gdbarch)->builtin_uint32, | |
4701 | &opts, 'w', file); | |
dd824b04 | 4702 | |
e11c53d2 | 4703 | fprintf_filtered (file, " flt: "); |
1adad886 | 4704 | if (inv1) |
e11c53d2 | 4705 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4706 | else |
e11c53d2 | 4707 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4708 | |
72a155b4 | 4709 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4710 | { |
e11c53d2 | 4711 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4712 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4713 | raw_buffer, &inv2); | |
1adad886 | 4714 | |
e11c53d2 | 4715 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4716 | if (inv2) |
e11c53d2 | 4717 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4718 | else |
e11c53d2 | 4719 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4720 | } |
c906108c SS |
4721 | } |
4722 | else | |
dd824b04 | 4723 | { |
79a45b7d TT |
4724 | struct value_print_options opts; |
4725 | ||
f0ef6b29 | 4726 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4727 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4728 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4729 | raw_buffer, &inv1); | |
c906108c | 4730 | |
e11c53d2 | 4731 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4732 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4733 | raw_buffer, &inv2); | |
f0ef6b29 | 4734 | |
79a45b7d | 4735 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4736 | print_scalar_formatted (raw_buffer, |
4737 | builtin_type (gdbarch)->builtin_uint64, | |
4738 | &opts, 'g', file); | |
f0ef6b29 | 4739 | |
e11c53d2 | 4740 | fprintf_filtered (file, " flt: "); |
1adad886 | 4741 | if (inv1) |
e11c53d2 | 4742 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4743 | else |
e11c53d2 | 4744 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4745 | |
e11c53d2 | 4746 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4747 | if (inv2) |
e11c53d2 | 4748 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4749 | else |
e11c53d2 | 4750 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4751 | } |
4752 | } | |
4753 | ||
4754 | static void | |
e11c53d2 | 4755 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4756 | int regnum) |
f0ef6b29 | 4757 | { |
a4b8ebc8 | 4758 | struct gdbarch *gdbarch = get_frame_arch (frame); |
f0ef6b29 | 4759 | int offset; |
79a45b7d | 4760 | struct value_print_options opts; |
de15c4ab | 4761 | struct value *val; |
1adad886 | 4762 | |
7b9ee6a8 | 4763 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4764 | { |
e11c53d2 | 4765 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4766 | return; |
4767 | } | |
4768 | ||
de15c4ab PA |
4769 | val = get_frame_register_value (frame, regnum); |
4770 | if (value_optimized_out (val)) | |
f0ef6b29 | 4771 | { |
c9f4d572 | 4772 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4773 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4774 | return; |
c906108c | 4775 | } |
f0ef6b29 | 4776 | |
72a155b4 | 4777 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4778 | |
4779 | /* The problem with printing numeric register names (r26, etc.) is that | |
4780 | the user can't use them on input. Probably the best solution is to | |
4781 | fix it so that either the numeric or the funky (a2, etc.) names | |
4782 | are accepted on input. */ | |
4783 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4784 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4785 | else |
e11c53d2 | 4786 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4787 | |
79a45b7d | 4788 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
4789 | val_print_scalar_formatted (value_type (val), |
4790 | value_contents_for_printing (val), | |
4791 | value_embedded_offset (val), | |
4792 | val, | |
4793 | &opts, 0, file); | |
c906108c SS |
4794 | } |
4795 | ||
f0ef6b29 KB |
4796 | /* Replacement for generic do_registers_info. |
4797 | Print regs in pretty columns. */ | |
4798 | ||
4799 | static int | |
e11c53d2 AC |
4800 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4801 | int regnum) | |
f0ef6b29 | 4802 | { |
e11c53d2 AC |
4803 | fprintf_filtered (file, " "); |
4804 | mips_print_fp_register (file, frame, regnum); | |
4805 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4806 | return regnum + 1; |
4807 | } | |
4808 | ||
4809 | ||
025bb325 | 4810 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
4811 | |
4812 | static int | |
e11c53d2 | 4813 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4814 | int start_regnum) |
c906108c | 4815 | { |
a4b8ebc8 | 4816 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 4817 | /* Do values for GP (int) regs. */ |
47a35522 | 4818 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
4819 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
4820 | per row. */ | |
c906108c | 4821 | int col, byte; |
a4b8ebc8 | 4822 | int regnum; |
c906108c | 4823 | |
025bb325 | 4824 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 4825 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4826 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4827 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4828 | regnum++) |
c906108c | 4829 | { |
72a155b4 | 4830 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4831 | continue; /* unused register */ |
7b9ee6a8 | 4832 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4833 | TYPE_CODE_FLT) |
025bb325 | 4834 | break; /* End the row: reached FP register. */ |
0cc93a06 | 4835 | /* Large registers are handled separately. */ |
72a155b4 | 4836 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4837 | { |
4838 | if (col > 0) | |
4839 | break; /* End the row before this register. */ | |
4840 | ||
4841 | /* Print this register on a row by itself. */ | |
4842 | mips_print_register (file, frame, regnum); | |
4843 | fprintf_filtered (file, "\n"); | |
4844 | return regnum + 1; | |
4845 | } | |
d05f6826 DJ |
4846 | if (col == 0) |
4847 | fprintf_filtered (file, " "); | |
6d82d43b | 4848 | fprintf_filtered (file, |
72a155b4 UW |
4849 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4850 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4851 | col++; |
4852 | } | |
d05f6826 DJ |
4853 | |
4854 | if (col == 0) | |
4855 | return regnum; | |
4856 | ||
025bb325 | 4857 | /* Print the R0 to R31 names. */ |
72a155b4 | 4858 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4859 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4860 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4861 | else |
4862 | fprintf_filtered (file, "\n "); | |
c906108c | 4863 | |
025bb325 | 4864 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 4865 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4866 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4867 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4868 | regnum++) |
c906108c | 4869 | { |
72a155b4 | 4870 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4871 | continue; /* unused register */ |
7b9ee6a8 | 4872 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4873 | TYPE_CODE_FLT) |
025bb325 | 4874 | break; /* End row: reached FP register. */ |
72a155b4 | 4875 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4876 | break; /* End row: large register. */ |
4877 | ||
c906108c | 4878 | /* OK: get the data in raw format. */ |
e11c53d2 | 4879 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4880 | error (_("can't read register %d (%s)"), |
72a155b4 | 4881 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4882 | /* pad small registers */ |
4246e332 | 4883 | for (byte = 0; |
72a155b4 UW |
4884 | byte < (mips_abi_regsize (gdbarch) |
4885 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 4886 | printf_filtered (" "); |
025bb325 | 4887 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 4888 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4889 | for (byte = |
72a155b4 UW |
4890 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4891 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4892 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4893 | else |
72a155b4 | 4894 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4895 | byte >= 0; byte--) |
47a35522 | 4896 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4897 | fprintf_filtered (file, " "); |
c906108c SS |
4898 | col++; |
4899 | } | |
025bb325 | 4900 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4901 | fprintf_filtered (file, "\n"); |
c906108c SS |
4902 | |
4903 | return regnum; | |
4904 | } | |
4905 | ||
025bb325 | 4906 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 4907 | |
bf1f5b4c | 4908 | static void |
e11c53d2 AC |
4909 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4910 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4911 | { |
025bb325 | 4912 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 4913 | { |
72a155b4 UW |
4914 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4915 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4916 | error (_("Not a valid register for the current processor type")); |
c906108c | 4917 | |
0cc93a06 | 4918 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4919 | fprintf_filtered (file, "\n"); |
c906108c | 4920 | } |
c5aa993b | 4921 | else |
025bb325 | 4922 | /* Do all (or most) registers. */ |
c906108c | 4923 | { |
72a155b4 UW |
4924 | regnum = gdbarch_num_regs (gdbarch); |
4925 | while (regnum < gdbarch_num_regs (gdbarch) | |
4926 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4927 | { |
7b9ee6a8 | 4928 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4929 | TYPE_CODE_FLT) |
e11c53d2 | 4930 | { |
025bb325 | 4931 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
4932 | regnum = print_fp_register_row (file, frame, regnum); |
4933 | else | |
025bb325 | 4934 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 4935 | } |
c906108c | 4936 | else |
e11c53d2 | 4937 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4938 | } |
4939 | } | |
4940 | } | |
4941 | ||
c906108c SS |
4942 | /* Is this a branch with a delay slot? */ |
4943 | ||
c906108c | 4944 | static int |
acdb74a0 | 4945 | is_delayed (unsigned long insn) |
c906108c SS |
4946 | { |
4947 | int i; | |
4948 | for (i = 0; i < NUMOPCODES; ++i) | |
4949 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4950 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4951 | break; | |
4952 | return (i < NUMOPCODES | |
4953 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4954 | | INSN_COND_BRANCH_DELAY | |
4955 | | INSN_COND_BRANCH_LIKELY))); | |
4956 | } | |
4957 | ||
63807e1d | 4958 | static int |
3352ef37 AC |
4959 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4960 | struct frame_info *frame) | |
c906108c | 4961 | { |
e17a4113 | 4962 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 4963 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4964 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4965 | |
4966 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4967 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4968 | return 0; |
4969 | ||
6c95b8df | 4970 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
06648491 MK |
4971 | return 0; |
4972 | ||
3352ef37 AC |
4973 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4974 | /* If error reading memory, guess that it is not a delayed | |
4975 | branch. */ | |
c906108c | 4976 | return 0; |
e17a4113 | 4977 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
4978 | } |
4979 | ||
6d82d43b AC |
4980 | /* To skip prologues, I use this predicate. Returns either PC itself |
4981 | if the code at PC does not look like a function prologue; otherwise | |
4982 | returns an address that (if we're lucky) follows the prologue. If | |
4983 | LENIENT, then we must skip everything which is involved in setting | |
4984 | up the frame (it's OK to skip more, just so long as we don't skip | |
4985 | anything which might clobber the registers which are being saved. | |
4986 | We must skip more in the case where part of the prologue is in the | |
4987 | delay slot of a non-prologue instruction). */ | |
4988 | ||
4989 | static CORE_ADDR | |
6093d2eb | 4990 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4991 | { |
8b622e6a AC |
4992 | CORE_ADDR limit_pc; |
4993 | CORE_ADDR func_addr; | |
4994 | ||
6d82d43b AC |
4995 | /* See if we can determine the end of the prologue via the symbol table. |
4996 | If so, then return either PC, or the PC after the prologue, whichever | |
4997 | is greater. */ | |
8b622e6a AC |
4998 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4999 | { | |
d80b854b UW |
5000 | CORE_ADDR post_prologue_pc |
5001 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
5002 | if (post_prologue_pc != 0) |
5003 | return max (pc, post_prologue_pc); | |
5004 | } | |
6d82d43b AC |
5005 | |
5006 | /* Can't determine prologue from the symbol table, need to examine | |
5007 | instructions. */ | |
5008 | ||
98b4dd94 JB |
5009 | /* Find an upper limit on the function prologue using the debug |
5010 | information. If the debug information could not be used to provide | |
5011 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 5012 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
5013 | if (limit_pc == 0) |
5014 | limit_pc = pc + 100; /* Magic. */ | |
5015 | ||
0fe7e7c8 | 5016 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 5017 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 5018 | else |
e17a4113 | 5019 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
5020 | } |
5021 | ||
97ab0fdd MR |
5022 | /* Check whether the PC is in a function epilogue (32-bit version). |
5023 | This is a helper function for mips_in_function_epilogue_p. */ | |
5024 | static int | |
e17a4113 | 5025 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
5026 | { |
5027 | CORE_ADDR func_addr = 0, func_end = 0; | |
5028 | ||
5029 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
5030 | { | |
5031 | /* The MIPS epilogue is max. 12 bytes long. */ | |
5032 | CORE_ADDR addr = func_end - 12; | |
5033 | ||
5034 | if (addr < func_addr + 4) | |
5035 | addr = func_addr + 4; | |
5036 | if (pc < addr) | |
5037 | return 0; | |
5038 | ||
5039 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
5040 | { | |
5041 | unsigned long high_word; | |
5042 | unsigned long inst; | |
5043 | ||
e17a4113 | 5044 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
5045 | high_word = (inst >> 16) & 0xffff; |
5046 | ||
5047 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
5048 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
5049 | && inst != 0x03e00008 /* jr $ra */ | |
5050 | && inst != 0x00000000) /* nop */ | |
5051 | return 0; | |
5052 | } | |
5053 | ||
5054 | return 1; | |
5055 | } | |
5056 | ||
5057 | return 0; | |
5058 | } | |
5059 | ||
5060 | /* Check whether the PC is in a function epilogue (16-bit version). | |
5061 | This is a helper function for mips_in_function_epilogue_p. */ | |
5062 | static int | |
e17a4113 | 5063 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
5064 | { |
5065 | CORE_ADDR func_addr = 0, func_end = 0; | |
5066 | ||
5067 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
5068 | { | |
5069 | /* The MIPS epilogue is max. 12 bytes long. */ | |
5070 | CORE_ADDR addr = func_end - 12; | |
5071 | ||
5072 | if (addr < func_addr + 4) | |
5073 | addr = func_addr + 4; | |
5074 | if (pc < addr) | |
5075 | return 0; | |
5076 | ||
5077 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
5078 | { | |
5079 | unsigned short inst; | |
5080 | ||
e17a4113 | 5081 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
5082 | |
5083 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
5084 | continue; | |
5085 | ||
5086 | if (inst != 0x6300 /* addiu $sp,offset */ | |
5087 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
5088 | && inst != 0xe820 /* jr $ra */ | |
5089 | && inst != 0xe8a0 /* jrc $ra */ | |
5090 | && inst != 0x6500) /* nop */ | |
5091 | return 0; | |
5092 | } | |
5093 | ||
5094 | return 1; | |
5095 | } | |
5096 | ||
5097 | return 0; | |
5098 | } | |
5099 | ||
5100 | /* The epilogue is defined here as the area at the end of a function, | |
5101 | after an instruction which destroys the function's stack frame. */ | |
5102 | static int | |
5103 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
5104 | { | |
5105 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 5106 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 5107 | else |
e17a4113 | 5108 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
5109 | } |
5110 | ||
025bb325 | 5111 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
5112 | used for all MIPS-specific commands. */ |
5113 | ||
a5ea2558 | 5114 | static void |
acdb74a0 | 5115 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5116 | { |
5117 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5118 | } | |
5119 | ||
a5ea2558 | 5120 | static void |
acdb74a0 | 5121 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5122 | { |
6d82d43b AC |
5123 | printf_unfiltered |
5124 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5125 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5126 | } | |
5127 | ||
c906108c SS |
5128 | /* Commands to show/set the MIPS FPU type. */ |
5129 | ||
c906108c | 5130 | static void |
acdb74a0 | 5131 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5132 | { |
c906108c | 5133 | char *fpu; |
6ca0852e | 5134 | |
1cf3db46 | 5135 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
5136 | { |
5137 | printf_unfiltered | |
5138 | ("The MIPS floating-point coprocessor is unknown " | |
5139 | "because the current architecture is not MIPS.\n"); | |
5140 | return; | |
5141 | } | |
5142 | ||
1cf3db46 | 5143 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
5144 | { |
5145 | case MIPS_FPU_SINGLE: | |
5146 | fpu = "single-precision"; | |
5147 | break; | |
5148 | case MIPS_FPU_DOUBLE: | |
5149 | fpu = "double-precision"; | |
5150 | break; | |
5151 | case MIPS_FPU_NONE: | |
5152 | fpu = "absent (none)"; | |
5153 | break; | |
93d56215 | 5154 | default: |
e2e0b3e5 | 5155 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
5156 | } |
5157 | if (mips_fpu_type_auto) | |
025bb325 MS |
5158 | printf_unfiltered ("The MIPS floating-point coprocessor " |
5159 | "is set automatically (currently %s)\n", | |
5160 | fpu); | |
c906108c | 5161 | else |
6d82d43b AC |
5162 | printf_unfiltered |
5163 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5164 | } |
5165 | ||
5166 | ||
c906108c | 5167 | static void |
acdb74a0 | 5168 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5169 | { |
025bb325 MS |
5170 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
5171 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5172 | show_mipsfpu_command (args, from_tty); |
5173 | } | |
5174 | ||
c906108c | 5175 | static void |
acdb74a0 | 5176 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5177 | { |
8d5838b5 AC |
5178 | struct gdbarch_info info; |
5179 | gdbarch_info_init (&info); | |
c906108c SS |
5180 | mips_fpu_type = MIPS_FPU_SINGLE; |
5181 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5182 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5183 | instead of relying on globals. Doing that would let generic code | |
5184 | handle the search for this specific architecture. */ | |
5185 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5186 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5187 | } |
5188 | ||
c906108c | 5189 | static void |
acdb74a0 | 5190 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5191 | { |
8d5838b5 AC |
5192 | struct gdbarch_info info; |
5193 | gdbarch_info_init (&info); | |
c906108c SS |
5194 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5195 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5196 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5197 | instead of relying on globals. Doing that would let generic code | |
5198 | handle the search for this specific architecture. */ | |
5199 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5200 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5201 | } |
5202 | ||
c906108c | 5203 | static void |
acdb74a0 | 5204 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5205 | { |
8d5838b5 AC |
5206 | struct gdbarch_info info; |
5207 | gdbarch_info_init (&info); | |
c906108c SS |
5208 | mips_fpu_type = MIPS_FPU_NONE; |
5209 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5210 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5211 | instead of relying on globals. Doing that would let generic code | |
5212 | handle the search for this specific architecture. */ | |
5213 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5214 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5215 | } |
5216 | ||
c906108c | 5217 | static void |
acdb74a0 | 5218 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5219 | { |
5220 | mips_fpu_type_auto = 1; | |
5221 | } | |
5222 | ||
c906108c | 5223 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5224 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5225 | the relevant processor still exists (it dates back to '94) and | |
5226 | secondly this is not the way to do this. The processor type should | |
5227 | be set by forcing an architecture change. */ | |
c906108c | 5228 | |
691c0433 AC |
5229 | void |
5230 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5231 | { |
bb486190 UW |
5232 | struct regcache *regcache = get_current_regcache (); |
5233 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
5234 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 5235 | ULONGEST prid; |
c906108c | 5236 | |
bb486190 | 5237 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 5238 | if ((prid & ~0xf) == 0x700) |
691c0433 | 5239 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5240 | } |
5241 | ||
5242 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5243 | callable as an sfunc. */ | |
5244 | ||
5245 | static void | |
acdb74a0 AC |
5246 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5247 | struct cmd_list_element *c) | |
c906108c SS |
5248 | { |
5249 | reinit_frame_cache (); | |
5250 | } | |
5251 | ||
a89aa300 AC |
5252 | static int |
5253 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5254 | { |
d31431ed AC |
5255 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5256 | disassembler needs to be able to locally determine the ISA, and | |
5257 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5258 | work. */ | |
ec4045ea AC |
5259 | if (mips_pc_is_mips16 (memaddr)) |
5260 | info->mach = bfd_mach_mips16; | |
c906108c SS |
5261 | |
5262 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5263 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5264 | |
e5ab0dce | 5265 | /* Set the disassembler options. */ |
9dae60cc | 5266 | if (!info->disassembler_options) |
e5ab0dce AC |
5267 | /* This string is not recognized explicitly by the disassembler, |
5268 | but it tells the disassembler to not try to guess the ABI from | |
5269 | the bfd elf headers, such that, if the user overrides the ABI | |
5270 | of a program linked as NewABI, the disassembly will follow the | |
5271 | register naming conventions specified by the user. */ | |
5272 | info->disassembler_options = "gpr-names=32"; | |
5273 | ||
c906108c | 5274 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 5275 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
5276 | return print_insn_big_mips (memaddr, info); |
5277 | else | |
5278 | return print_insn_little_mips (memaddr, info); | |
5279 | } | |
5280 | ||
9dae60cc UW |
5281 | static int |
5282 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
5283 | { | |
5284 | /* Set up the disassembler info, so that we get the right | |
5285 | register names from libopcodes. */ | |
5286 | info->disassembler_options = "gpr-names=n32"; | |
5287 | info->flavour = bfd_target_elf_flavour; | |
5288 | ||
5289 | return gdb_print_insn_mips (memaddr, info); | |
5290 | } | |
5291 | ||
5292 | static int | |
5293 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5294 | { | |
5295 | /* Set up the disassembler info, so that we get the right | |
5296 | register names from libopcodes. */ | |
5297 | info->disassembler_options = "gpr-names=64"; | |
5298 | info->flavour = bfd_target_elf_flavour; | |
5299 | ||
5300 | return gdb_print_insn_mips (memaddr, info); | |
5301 | } | |
5302 | ||
025bb325 MS |
5303 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
5304 | program counter value to determine whether a 16- or 32-bit breakpoint | |
5305 | should be used. It returns a pointer to a string of bytes that encode a | |
5306 | breakpoint instruction, stores the length of the string to *lenptr, and | |
5307 | adjusts pc (if necessary) to point to the actual memory location where | |
5308 | the breakpoint should be inserted. */ | |
c906108c | 5309 | |
47a35522 | 5310 | static const gdb_byte * |
025bb325 MS |
5311 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
5312 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 5313 | { |
67d57894 | 5314 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5315 | { |
0fe7e7c8 | 5316 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5317 | { |
47a35522 | 5318 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5319 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5320 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5321 | return mips16_big_breakpoint; |
5322 | } | |
5323 | else | |
5324 | { | |
aaab4dba AC |
5325 | /* The IDT board uses an unusual breakpoint value, and |
5326 | sometimes gets confused when it sees the usual MIPS | |
5327 | breakpoint instruction. */ | |
47a35522 MK |
5328 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5329 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5330 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 5331 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 5332 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 5333 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 5334 | |
c5aa993b | 5335 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5336 | |
5337 | if (strcmp (target_shortname, "mips") == 0) | |
5338 | return idt_big_breakpoint; | |
5339 | else if (strcmp (target_shortname, "ddb") == 0 | |
5340 | || strcmp (target_shortname, "pmon") == 0 | |
5341 | || strcmp (target_shortname, "lsi") == 0) | |
5342 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
5343 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5344 | return irix_big_breakpoint; | |
c906108c SS |
5345 | else |
5346 | return big_breakpoint; | |
5347 | } | |
5348 | } | |
5349 | else | |
5350 | { | |
0fe7e7c8 | 5351 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5352 | { |
47a35522 | 5353 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5354 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5355 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5356 | return mips16_little_breakpoint; |
5357 | } | |
5358 | else | |
5359 | { | |
47a35522 MK |
5360 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5361 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5362 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5363 | |
c5aa993b | 5364 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5365 | |
5366 | if (strcmp (target_shortname, "mips") == 0) | |
5367 | return idt_little_breakpoint; | |
5368 | else if (strcmp (target_shortname, "ddb") == 0 | |
5369 | || strcmp (target_shortname, "pmon") == 0 | |
5370 | || strcmp (target_shortname, "lsi") == 0) | |
5371 | return pmon_little_breakpoint; | |
5372 | else | |
5373 | return little_breakpoint; | |
5374 | } | |
5375 | } | |
5376 | } | |
5377 | ||
c8cef75f MR |
5378 | /* Return non-zero if the ADDR instruction has a branch delay slot |
5379 | (i.e. it is a jump or branch instruction). This function is based | |
5380 | on mips32_next_pc. */ | |
5381 | ||
5382 | static int | |
5383 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) | |
5384 | { | |
5385 | gdb_byte buf[MIPS_INSN32_SIZE]; | |
5386 | unsigned long inst; | |
5387 | int status; | |
5388 | int op; | |
a385295e MR |
5389 | int rs; |
5390 | int rt; | |
c8cef75f MR |
5391 | |
5392 | status = target_read_memory (addr, buf, MIPS_INSN32_SIZE); | |
5393 | if (status) | |
5394 | return 0; | |
5395 | ||
5396 | inst = mips_fetch_instruction (gdbarch, addr); | |
5397 | op = itype_op (inst); | |
5398 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
5399 | { |
5400 | rs = itype_rs (inst); | |
5401 | rt = itype_rt (inst); | |
5402 | return (op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
5403 | || op == 29 /* JALX: bits 011101 */ | |
5404 | || (op == 17 | |
5405 | && (rs == 8 | |
c8cef75f | 5406 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
5407 | || (rs == 9 && (rt & 0x2) == 0) |
5408 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
5409 | || (rs == 10 && (rt & 0x2) == 0)))); | |
5410 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
5411 | } | |
c8cef75f MR |
5412 | else |
5413 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
5414 | { | |
5415 | case 0: /* SPECIAL */ | |
5416 | op = rtype_funct (inst); | |
5417 | return (op == 8 /* JR */ | |
5418 | || op == 9); /* JALR */ | |
5419 | break; /* end SPECIAL */ | |
5420 | case 1: /* REGIMM */ | |
a385295e MR |
5421 | rs = itype_rs (inst); |
5422 | rt = itype_rt (inst); /* branch condition */ | |
5423 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
5424 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
5425 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
5426 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
5427 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
5428 | break; /* end REGIMM */ |
5429 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
5430 | return 1; | |
5431 | break; | |
5432 | } | |
5433 | } | |
5434 | ||
5435 | /* Return non-zero if the ADDR instruction, which must be a 32-bit | |
5436 | instruction if MUSTBE32 is set or can be any instruction otherwise, | |
5437 | has a branch delay slot (i.e. it is a non-compact jump instruction). */ | |
5438 | ||
5439 | static int | |
5440 | mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, | |
5441 | int mustbe32) | |
5442 | { | |
5443 | gdb_byte buf[MIPS_INSN16_SIZE]; | |
5444 | unsigned short inst; | |
5445 | int status; | |
5446 | ||
5447 | status = target_read_memory (addr, buf, MIPS_INSN16_SIZE); | |
5448 | if (status) | |
5449 | return 0; | |
5450 | ||
5451 | inst = mips_fetch_instruction (gdbarch, addr); | |
5452 | if (!mustbe32) | |
5453 | return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */ | |
5454 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ | |
5455 | } | |
5456 | ||
5457 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. | |
5458 | This assumes KSSEG exists. */ | |
5459 | ||
5460 | static CORE_ADDR | |
5461 | mips_segment_boundary (CORE_ADDR bpaddr) | |
5462 | { | |
5463 | CORE_ADDR mask = CORE_ADDR_MAX; | |
5464 | int segsize; | |
5465 | ||
5466 | if (sizeof (CORE_ADDR) == 8) | |
5467 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
5468 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
5469 | though in that case this is dead code). */ | |
5470 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
5471 | { | |
5472 | case 3: | |
5473 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
5474 | segsize = 29; /* 32-bit compatibility segment */ | |
5475 | else | |
5476 | segsize = 62; /* xkseg */ | |
5477 | break; | |
5478 | case 2: /* xkphys */ | |
5479 | segsize = 59; | |
5480 | break; | |
5481 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
5482 | segsize = 62; | |
5483 | break; | |
5484 | } | |
5485 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
5486 | segsize = 29; | |
5487 | else | |
5488 | segsize = 31; /* user segment */ | |
5489 | mask <<= segsize; | |
5490 | return bpaddr & mask; | |
5491 | } | |
5492 | ||
5493 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
5494 | it backwards if necessary. Return the address of the new location. */ | |
5495 | ||
5496 | static CORE_ADDR | |
5497 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
5498 | { | |
5499 | CORE_ADDR prev_addr, next_addr; | |
5500 | CORE_ADDR boundary; | |
5501 | CORE_ADDR func_addr; | |
5502 | ||
5503 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
5504 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
5505 | the instruction in the branch delay slot, the PC will point to | |
5506 | the branch instruction. Since the PC doesn't match any known | |
5507 | breakpoints, GDB reports a trap exception. | |
5508 | ||
5509 | There are two possible fixes for this problem. | |
5510 | ||
5511 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
5512 | Cause register (which indicates the last exception occurred in a | |
5513 | branch delay slot). If the BD bit is set, fix the PC to point to | |
5514 | the instruction in the branch delay slot. | |
5515 | ||
5516 | 2) When the user sets the breakpoint, don't allow him to set the | |
5517 | breakpoint on the instruction in the branch delay slot. Instead | |
5518 | move the breakpoint to the branch instruction (which will have | |
5519 | the same result). | |
5520 | ||
5521 | The problem with the first solution is that if the user then | |
5522 | single-steps the processor, the branch instruction will get | |
5523 | skipped (since GDB thinks the PC is on the instruction in the | |
5524 | branch delay slot). | |
5525 | ||
5526 | So, we'll use the second solution. To do this we need to know if | |
5527 | the instruction we're trying to set the breakpoint on is in the | |
5528 | branch delay slot. */ | |
5529 | ||
5530 | boundary = mips_segment_boundary (bpaddr); | |
5531 | ||
5532 | /* Make sure we don't scan back before the beginning of the current | |
5533 | function, since we may fetch constant data or insns that look like | |
5534 | a jump. Of course we might do that anyway if the compiler has | |
5535 | moved constants inline. :-( */ | |
5536 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
5537 | && func_addr > boundary && func_addr <= bpaddr) | |
5538 | boundary = func_addr; | |
5539 | ||
5540 | if (!mips_pc_is_mips16 (bpaddr)) | |
5541 | { | |
5542 | if (bpaddr == boundary) | |
5543 | return bpaddr; | |
5544 | ||
5545 | /* If the previous instruction has a branch delay slot, we have | |
5546 | to move the breakpoint to the branch instruction. */ | |
5547 | prev_addr = bpaddr - 4; | |
5548 | if (mips32_instruction_has_delay_slot (gdbarch, prev_addr)) | |
5549 | bpaddr = prev_addr; | |
5550 | } | |
5551 | else | |
5552 | { | |
5553 | struct minimal_symbol *sym; | |
5554 | CORE_ADDR addr, jmpaddr; | |
5555 | int i; | |
5556 | ||
5557 | boundary = unmake_mips16_addr (boundary); | |
5558 | ||
5559 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
5560 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
5561 | so try for that first, then try the 2 byte JALR/JR. | |
5562 | FIXME: We have to assume that bpaddr is not the second half | |
5563 | of an extended instruction. */ | |
5564 | ||
5565 | jmpaddr = 0; | |
5566 | addr = bpaddr; | |
5567 | for (i = 1; i < 4; i++) | |
5568 | { | |
5569 | if (unmake_mips16_addr (addr) == boundary) | |
5570 | break; | |
5571 | addr -= 2; | |
5572 | if (i == 1 && mips16_instruction_has_delay_slot (gdbarch, addr, 0)) | |
5573 | /* Looks like a JR/JALR at [target-1], but it could be | |
5574 | the second word of a previous JAL/JALX, so record it | |
5575 | and check back one more. */ | |
5576 | jmpaddr = addr; | |
5577 | else if (i > 1 | |
5578 | && mips16_instruction_has_delay_slot (gdbarch, addr, 1)) | |
5579 | { | |
5580 | if (i == 2) | |
5581 | /* Looks like a JAL/JALX at [target-2], but it could also | |
5582 | be the second word of a previous JAL/JALX, record it, | |
5583 | and check back one more. */ | |
5584 | jmpaddr = addr; | |
5585 | else | |
5586 | /* Looks like a JAL/JALX at [target-3], so any previously | |
5587 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
5588 | ||
5589 | >-3: JAL | |
5590 | -2: JAL-ext (can't be JAL/JALX) | |
5591 | -1: bdslot (can't be JR/JALR) | |
5592 | 0: target insn | |
5593 | ||
5594 | Of course it could be another JAL-ext which looks | |
5595 | like a JAL, but in that case we'd have broken out | |
5596 | of this loop at [target-2]: | |
5597 | ||
5598 | -4: JAL | |
5599 | >-3: JAL-ext | |
5600 | -2: bdslot (can't be jmp) | |
5601 | -1: JR/JALR | |
5602 | 0: target insn */ | |
5603 | jmpaddr = 0; | |
5604 | } | |
5605 | else | |
5606 | { | |
5607 | /* Not a jump instruction: if we're at [target-1] this | |
5608 | could be the second word of a JAL/JALX, so continue; | |
5609 | otherwise we're done. */ | |
5610 | if (i > 1) | |
5611 | break; | |
5612 | } | |
5613 | } | |
5614 | ||
5615 | if (jmpaddr) | |
5616 | bpaddr = jmpaddr; | |
5617 | } | |
5618 | ||
5619 | return bpaddr; | |
5620 | } | |
5621 | ||
c906108c SS |
5622 | /* If PC is in a mips16 call or return stub, return the address of the target |
5623 | PC, which is either the callee or the caller. There are several | |
5624 | cases which must be handled: | |
5625 | ||
5626 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5627 | target PC is in $31 ($ra). |
c906108c | 5628 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5629 | and the target PC is in $2. |
c906108c | 5630 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b | 5631 | before the jal instruction, this is effectively a call stub |
b021a221 | 5632 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5633 | a return stub and the target PC is in $18. |
c906108c SS |
5634 | |
5635 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5636 | gory details. */ |
c906108c | 5637 | |
757a7cc6 | 5638 | static CORE_ADDR |
db5f024e | 5639 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5640 | { |
e17a4113 | 5641 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2c02bd72 | 5642 | const char *name; |
c906108c SS |
5643 | CORE_ADDR start_addr; |
5644 | ||
5645 | /* Find the starting address and name of the function containing the PC. */ | |
5646 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5647 | return 0; | |
5648 | ||
5649 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5650 | target PC is in $31 ($ra). */ | |
5651 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5652 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5653 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5654 | |
5655 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5656 | { | |
5657 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5658 | and the target PC is in $2. */ | |
5659 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5660 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5661 | |
5662 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5663 | before the jal instruction, this is effectively a call stub |
b021a221 | 5664 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5665 | a return stub and the target PC is in $18. */ |
c906108c SS |
5666 | else if (name[19] == 's' || name[19] == 'd') |
5667 | { | |
5668 | if (pc == start_addr) | |
5669 | { | |
5670 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5671 | stub. Such a stub for a function bar might have a name |
5672 | like __fn_stub_bar, and might look like this: | |
5673 | mfc1 $4,$f13 | |
5674 | mfc1 $5,$f12 | |
5675 | mfc1 $6,$f15 | |
5676 | mfc1 $7,$f14 | |
5677 | la $1,bar (becomes a lui/addiu pair) | |
5678 | jr $1 | |
5679 | So scan down to the lui/addi and extract the target | |
5680 | address from those two instructions. */ | |
c906108c | 5681 | |
52f729a7 | 5682 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
c906108c SS |
5683 | int i; |
5684 | ||
5685 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5686 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5687 | 0) | |
c906108c SS |
5688 | return target_pc; |
5689 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5690 | && strcmp (name, "etext") != 0 | |
5691 | && strcmp (name, "_etext") != 0) | |
5692 | return target_pc; | |
5693 | ||
5694 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5695 | The limit on the search is arbitrarily set to 20 |
5696 | instructions. FIXME. */ | |
95ac2dcf | 5697 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5698 | { |
280711e7 MR |
5699 | ULONGEST inst = mips_fetch_instruction (gdbarch, target_pc); |
5700 | CORE_ADDR addr = inst; | |
5701 | ||
c5aa993b | 5702 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
280711e7 MR |
5703 | pc = (((addr & 0xffff) ^ 0x8000) - 0x8000) << 16; |
5704 | /* high word */ | |
c5aa993b | 5705 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ |
280711e7 MR |
5706 | return pc + ((addr & 0xffff) ^ 0x8000) - 0x8000; |
5707 | /* low word */ | |
c906108c SS |
5708 | } |
5709 | ||
5710 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5711 | return target_pc; | |
5712 | } | |
5713 | else | |
5714 | /* This is the 'return' part of a call stub. The return | |
5715 | address is in $r18. */ | |
52f729a7 | 5716 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5717 | } |
5718 | } | |
c5aa993b | 5719 | return 0; /* not a stub */ |
c906108c SS |
5720 | } |
5721 | ||
db5f024e DJ |
5722 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5723 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5724 | so that $t9 has the correct value at function entry. */ | |
5725 | ||
5726 | static CORE_ADDR | |
5727 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5728 | { | |
e17a4113 UW |
5729 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5730 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
5731 | struct minimal_symbol *msym; |
5732 | int i; | |
5733 | gdb_byte stub_code[16]; | |
5734 | int32_t stub_words[4]; | |
5735 | ||
5736 | /* The stub for foo is named ".pic.foo", and is either two | |
5737 | instructions inserted before foo or a three instruction sequence | |
5738 | which jumps to foo. */ | |
5739 | msym = lookup_minimal_symbol_by_pc (pc); | |
5740 | if (msym == NULL | |
5741 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5742 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5743 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5744 | return 0; | |
5745 | ||
5746 | /* A two-instruction header. */ | |
5747 | if (MSYMBOL_SIZE (msym) == 8) | |
5748 | return pc + 8; | |
5749 | ||
5750 | /* A three-instruction (plus delay slot) trampoline. */ | |
5751 | if (MSYMBOL_SIZE (msym) == 16) | |
5752 | { | |
5753 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5754 | return 0; | |
5755 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
5756 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
5757 | 4, byte_order); | |
db5f024e DJ |
5758 | |
5759 | /* A stub contains these instructions: | |
5760 | lui t9, %hi(target) | |
5761 | j target | |
5762 | addiu t9, t9, %lo(target) | |
5763 | nop | |
5764 | ||
5765 | This works even for N64, since stubs are only generated with | |
5766 | -msym32. */ | |
5767 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5768 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5769 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5770 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
5771 | return ((((stub_words[0] & 0x0000ffff) << 16) |
5772 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
5773 | } |
5774 | ||
5775 | /* Not a recognized stub. */ | |
5776 | return 0; | |
5777 | } | |
5778 | ||
5779 | static CORE_ADDR | |
5780 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5781 | { | |
5782 | CORE_ADDR target_pc; | |
5783 | ||
5784 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5785 | if (target_pc) | |
5786 | return target_pc; | |
5787 | ||
5788 | target_pc = find_solib_trampoline_target (frame, pc); | |
5789 | if (target_pc) | |
5790 | return target_pc; | |
5791 | ||
5792 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5793 | if (target_pc) | |
5794 | return target_pc; | |
5795 | ||
5796 | return 0; | |
5797 | } | |
5798 | ||
a4b8ebc8 | 5799 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5800 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5801 | |
5802 | static int | |
d3f73121 | 5803 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5804 | { |
a4b8ebc8 | 5805 | int regnum; |
2f38ef89 | 5806 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5807 | regnum = num; |
2f38ef89 | 5808 | else if (num >= 38 && num < 70) |
d3f73121 | 5809 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5810 | else if (num == 70) |
d3f73121 | 5811 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5812 | else if (num == 71) |
d3f73121 | 5813 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
5814 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
5815 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 5816 | else |
a4b8ebc8 AC |
5817 | /* This will hopefully (eventually) provoke a warning. Should |
5818 | we be calling complaint() here? */ | |
d3f73121 MD |
5819 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5820 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5821 | } |
5822 | ||
2f38ef89 | 5823 | |
a4b8ebc8 | 5824 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5825 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5826 | |
5827 | static int | |
d3f73121 | 5828 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5829 | { |
a4b8ebc8 | 5830 | int regnum; |
2f38ef89 | 5831 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5832 | regnum = num; |
2f38ef89 | 5833 | else if (num >= 32 && num < 64) |
d3f73121 | 5834 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5835 | else if (num == 64) |
d3f73121 | 5836 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5837 | else if (num == 65) |
d3f73121 | 5838 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
5839 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
5840 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 5841 | else |
a4b8ebc8 AC |
5842 | /* This will hopefully (eventually) provoke a warning. Should we |
5843 | be calling complaint() here? */ | |
d3f73121 MD |
5844 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5845 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5846 | } |
5847 | ||
5848 | static int | |
e7faf938 | 5849 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5850 | { |
5851 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5852 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5853 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5854 | decide if it is valid. Should instead define a standard sim/gdb | |
5855 | register numbering scheme. */ | |
e7faf938 MD |
5856 | if (gdbarch_register_name (gdbarch, |
5857 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5858 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
5859 | gdbarch_num_regs (gdbarch) |
5860 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5861 | return regnum; |
5862 | else | |
6d82d43b | 5863 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5864 | } |
5865 | ||
2f38ef89 | 5866 | |
4844f454 CV |
5867 | /* Convert an integer into an address. Extracting the value signed |
5868 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5869 | |
5870 | static CORE_ADDR | |
79dd2d24 | 5871 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5872 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5873 | { |
e17a4113 UW |
5874 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
5875 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
5876 | } |
5877 | ||
82e91389 DJ |
5878 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5879 | than most other architectures; we just need to be explicit about it, | |
5880 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5881 | an assertion failure. */ | |
5882 | ||
5883 | static void | |
a54fba4c MD |
5884 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5885 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5886 | { |
5887 | *reg = MIPS_SP_REGNUM; | |
5888 | *offset = 0; | |
5889 | } | |
5890 | ||
caaa3122 DJ |
5891 | static void |
5892 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5893 | { | |
5894 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5895 | const char *name = bfd_get_section_name (abfd, sect); | |
5896 | ||
5897 | if (*abip != MIPS_ABI_UNKNOWN) | |
5898 | return; | |
5899 | ||
5900 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5901 | return; | |
5902 | ||
5903 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5904 | *abip = MIPS_ABI_O32; | |
5905 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5906 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5907 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5908 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5909 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5910 | *abip = MIPS_ABI_O64; | |
5911 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5912 | *abip = MIPS_ABI_EABI32; | |
5913 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5914 | *abip = MIPS_ABI_EABI64; | |
5915 | else | |
8a3fe4f8 | 5916 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5917 | } |
5918 | ||
22e47e37 FF |
5919 | static void |
5920 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5921 | { | |
5922 | int *lbp = (int *) obj; | |
5923 | const char *name = bfd_get_section_name (abfd, sect); | |
5924 | ||
5925 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5926 | *lbp = 32; | |
5927 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5928 | *lbp = 64; | |
5929 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5930 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5931 | } | |
5932 | ||
2e4ebe70 DJ |
5933 | static enum mips_abi |
5934 | global_mips_abi (void) | |
5935 | { | |
5936 | int i; | |
5937 | ||
5938 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5939 | if (mips_abi_strings[i] == mips_abi_string) | |
5940 | return (enum mips_abi) i; | |
5941 | ||
e2e0b3e5 | 5942 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5943 | } |
5944 | ||
29709017 DJ |
5945 | static void |
5946 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5947 | { | |
29709017 DJ |
5948 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5949 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5950 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5951 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5952 | |
5953 | /* If the size matches the full set of registers GDB traditionally | |
5954 | knows about, including floating point, for either 32-bit or | |
5955 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5956 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5957 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5958 | |
5959 | /* Otherwise we don't have a useful guess. */ | |
5960 | } | |
5961 | ||
f8b73d13 DJ |
5962 | static struct value * |
5963 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5964 | { | |
5965 | const int *reg_p = baton; | |
5966 | return value_of_register (*reg_p, frame); | |
5967 | } | |
5968 | ||
c2d11a7d | 5969 | static struct gdbarch * |
6d82d43b | 5970 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5971 | { |
c2d11a7d JM |
5972 | struct gdbarch *gdbarch; |
5973 | struct gdbarch_tdep *tdep; | |
5974 | int elf_flags; | |
2e4ebe70 | 5975 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5976 | int i, num_regs; |
8d5838b5 | 5977 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5978 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5979 | int elf_fpu_type = 0; |
1faeff08 MR |
5980 | const char **reg_names; |
5981 | struct mips_regnum mips_regnum, *regnum; | |
5982 | int dspacc; | |
5983 | int dspctl; | |
5984 | ||
5985 | /* Fill in the OS dependent register numbers and names. */ | |
5986 | if (info.osabi == GDB_OSABI_IRIX) | |
5987 | { | |
5988 | mips_regnum.fp0 = 32; | |
5989 | mips_regnum.pc = 64; | |
5990 | mips_regnum.cause = 65; | |
5991 | mips_regnum.badvaddr = 66; | |
5992 | mips_regnum.hi = 67; | |
5993 | mips_regnum.lo = 68; | |
5994 | mips_regnum.fp_control_status = 69; | |
5995 | mips_regnum.fp_implementation_revision = 70; | |
5996 | mips_regnum.dspacc = dspacc = -1; | |
5997 | mips_regnum.dspctl = dspctl = -1; | |
5998 | num_regs = 71; | |
5999 | reg_names = mips_irix_reg_names; | |
6000 | } | |
6001 | else if (info.osabi == GDB_OSABI_LINUX) | |
6002 | { | |
6003 | mips_regnum.fp0 = 38; | |
6004 | mips_regnum.pc = 37; | |
6005 | mips_regnum.cause = 36; | |
6006 | mips_regnum.badvaddr = 35; | |
6007 | mips_regnum.hi = 34; | |
6008 | mips_regnum.lo = 33; | |
6009 | mips_regnum.fp_control_status = 70; | |
6010 | mips_regnum.fp_implementation_revision = 71; | |
6011 | mips_regnum.dspacc = -1; | |
6012 | mips_regnum.dspctl = -1; | |
6013 | dspacc = 72; | |
6014 | dspctl = 78; | |
6015 | num_regs = 79; | |
6016 | reg_names = mips_linux_reg_names; | |
6017 | } | |
6018 | else | |
6019 | { | |
6020 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
6021 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
6022 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6023 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
6024 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
6025 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
6026 | mips_regnum.fp_control_status = 70; | |
6027 | mips_regnum.fp_implementation_revision = 71; | |
6028 | mips_regnum.dspacc = dspacc = -1; | |
6029 | mips_regnum.dspctl = dspctl = -1; | |
6030 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
6031 | if (info.bfd_arch_info != NULL | |
6032 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6033 | reg_names = mips_tx39_reg_names; | |
6034 | else | |
6035 | reg_names = mips_generic_reg_names; | |
6036 | } | |
f8b73d13 DJ |
6037 | |
6038 | /* Check any target description for validity. */ | |
6039 | if (tdesc_has_registers (info.target_desc)) | |
6040 | { | |
6041 | static const char *const mips_gprs[] = { | |
6042 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
6043 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
6044 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
6045 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
6046 | }; | |
6047 | static const char *const mips_fprs[] = { | |
6048 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
6049 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
6050 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
6051 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
6052 | }; | |
6053 | ||
6054 | const struct tdesc_feature *feature; | |
6055 | int valid_p; | |
6056 | ||
6057 | feature = tdesc_find_feature (info.target_desc, | |
6058 | "org.gnu.gdb.mips.cpu"); | |
6059 | if (feature == NULL) | |
6060 | return NULL; | |
6061 | ||
6062 | tdesc_data = tdesc_data_alloc (); | |
6063 | ||
6064 | valid_p = 1; | |
6065 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
6066 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
6067 | mips_gprs[i]); | |
6068 | ||
6069 | ||
6070 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6071 | mips_regnum.lo, "lo"); |
f8b73d13 | 6072 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 6073 | mips_regnum.hi, "hi"); |
f8b73d13 | 6074 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 6075 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
6076 | |
6077 | if (!valid_p) | |
6078 | { | |
6079 | tdesc_data_cleanup (tdesc_data); | |
6080 | return NULL; | |
6081 | } | |
6082 | ||
6083 | feature = tdesc_find_feature (info.target_desc, | |
6084 | "org.gnu.gdb.mips.cp0"); | |
6085 | if (feature == NULL) | |
6086 | { | |
6087 | tdesc_data_cleanup (tdesc_data); | |
6088 | return NULL; | |
6089 | } | |
6090 | ||
6091 | valid_p = 1; | |
6092 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6093 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
6094 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
6095 | MIPS_PS_REGNUM, "status"); | |
6096 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6097 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
6098 | |
6099 | if (!valid_p) | |
6100 | { | |
6101 | tdesc_data_cleanup (tdesc_data); | |
6102 | return NULL; | |
6103 | } | |
6104 | ||
6105 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
6106 | backend is not prepared for that, though. */ | |
6107 | feature = tdesc_find_feature (info.target_desc, | |
6108 | "org.gnu.gdb.mips.fpu"); | |
6109 | if (feature == NULL) | |
6110 | { | |
6111 | tdesc_data_cleanup (tdesc_data); | |
6112 | return NULL; | |
6113 | } | |
6114 | ||
6115 | valid_p = 1; | |
6116 | for (i = 0; i < 32; i++) | |
6117 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6118 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
6119 | |
6120 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
6121 | mips_regnum.fp_control_status, |
6122 | "fcsr"); | |
6123 | valid_p | |
6124 | &= tdesc_numbered_register (feature, tdesc_data, | |
6125 | mips_regnum.fp_implementation_revision, | |
6126 | "fir"); | |
f8b73d13 DJ |
6127 | |
6128 | if (!valid_p) | |
6129 | { | |
6130 | tdesc_data_cleanup (tdesc_data); | |
6131 | return NULL; | |
6132 | } | |
6133 | ||
1faeff08 MR |
6134 | if (dspacc >= 0) |
6135 | { | |
6136 | feature = tdesc_find_feature (info.target_desc, | |
6137 | "org.gnu.gdb.mips.dsp"); | |
6138 | /* The DSP registers are optional; it's OK if they are absent. */ | |
6139 | if (feature != NULL) | |
6140 | { | |
6141 | i = 0; | |
6142 | valid_p = 1; | |
6143 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6144 | dspacc + i++, "hi1"); | |
6145 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6146 | dspacc + i++, "lo1"); | |
6147 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6148 | dspacc + i++, "hi2"); | |
6149 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6150 | dspacc + i++, "lo2"); | |
6151 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6152 | dspacc + i++, "hi3"); | |
6153 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6154 | dspacc + i++, "lo3"); | |
6155 | ||
6156 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6157 | dspctl, "dspctl"); | |
6158 | ||
6159 | if (!valid_p) | |
6160 | { | |
6161 | tdesc_data_cleanup (tdesc_data); | |
6162 | return NULL; | |
6163 | } | |
6164 | ||
6165 | mips_regnum.dspacc = dspacc; | |
6166 | mips_regnum.dspctl = dspctl; | |
6167 | } | |
6168 | } | |
6169 | ||
f8b73d13 DJ |
6170 | /* It would be nice to detect an attempt to use a 64-bit ABI |
6171 | when only 32-bit registers are provided. */ | |
1faeff08 | 6172 | reg_names = NULL; |
f8b73d13 | 6173 | } |
c2d11a7d | 6174 | |
ec03c1ac AC |
6175 | /* First of all, extract the elf_flags, if available. */ |
6176 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
6177 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
6178 | else if (arches != NULL) |
6179 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
6180 | else |
6181 | elf_flags = 0; | |
6182 | if (gdbarch_debug) | |
6183 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6184 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 6185 | |
102182a9 | 6186 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
6187 | switch ((elf_flags & EF_MIPS_ABI)) |
6188 | { | |
6189 | case E_MIPS_ABI_O32: | |
ec03c1ac | 6190 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
6191 | break; |
6192 | case E_MIPS_ABI_O64: | |
ec03c1ac | 6193 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
6194 | break; |
6195 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 6196 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
6197 | break; |
6198 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 6199 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
6200 | break; |
6201 | default: | |
acdb74a0 | 6202 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 6203 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 6204 | else |
ec03c1ac | 6205 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
6206 | break; |
6207 | } | |
acdb74a0 | 6208 | |
caaa3122 | 6209 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
6210 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
6211 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 6212 | |
dc305454 | 6213 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
6214 | MIPS architecture (if there is one). */ |
6215 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
6216 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 6217 | |
32a6503c | 6218 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 6219 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
6220 | && info.bfd_arch_info != NULL |
6221 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6222 | { | |
6223 | switch (info.bfd_arch_info->mach) | |
6224 | { | |
6225 | case bfd_mach_mips3900: | |
ec03c1ac | 6226 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
6227 | break; |
6228 | case bfd_mach_mips4100: | |
6229 | case bfd_mach_mips5000: | |
ec03c1ac | 6230 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 6231 | break; |
1d06468c EZ |
6232 | case bfd_mach_mips8000: |
6233 | case bfd_mach_mips10000: | |
32a6503c KB |
6234 | /* On Irix, ELF64 executables use the N64 ABI. The |
6235 | pseudo-sections which describe the ABI aren't present | |
6236 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
6237 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
6238 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 6239 | found_abi = MIPS_ABI_N64; |
28d169de | 6240 | else |
ec03c1ac | 6241 | found_abi = MIPS_ABI_N32; |
1d06468c | 6242 | break; |
bf64bfd6 AC |
6243 | } |
6244 | } | |
2e4ebe70 | 6245 | |
26c53e50 DJ |
6246 | /* Default 64-bit objects to N64 instead of O32. */ |
6247 | if (found_abi == MIPS_ABI_UNKNOWN | |
6248 | && info.abfd != NULL | |
6249 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
6250 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
6251 | found_abi = MIPS_ABI_N64; | |
6252 | ||
ec03c1ac AC |
6253 | if (gdbarch_debug) |
6254 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
6255 | found_abi); | |
6256 | ||
6257 | /* What has the user specified from the command line? */ | |
6258 | wanted_abi = global_mips_abi (); | |
6259 | if (gdbarch_debug) | |
6260 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
6261 | wanted_abi); | |
2e4ebe70 DJ |
6262 | |
6263 | /* Now that we have found what the ABI for this binary would be, | |
6264 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
6265 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
6266 | mips_abi = wanted_abi; | |
ec03c1ac AC |
6267 | else if (found_abi != MIPS_ABI_UNKNOWN) |
6268 | mips_abi = found_abi; | |
6269 | else | |
6270 | mips_abi = MIPS_ABI_O32; | |
6271 | if (gdbarch_debug) | |
6272 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
6273 | mips_abi); | |
2e4ebe70 | 6274 | |
ec03c1ac | 6275 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 6276 | if (gdbarch_debug) |
ec03c1ac | 6277 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
6278 | "mips_gdbarch_init: " |
6279 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 6280 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 6281 | |
8d5838b5 | 6282 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
6283 | #ifdef HAVE_ELF |
6284 | if (info.abfd | |
6285 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
6286 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
6287 | Tag_GNU_MIPS_ABI_FP); | |
6288 | #endif /* HAVE_ELF */ | |
6289 | ||
8d5838b5 AC |
6290 | if (!mips_fpu_type_auto) |
6291 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
6292 | else if (elf_fpu_type != 0) |
6293 | { | |
6294 | switch (elf_fpu_type) | |
6295 | { | |
6296 | case 1: | |
6297 | fpu_type = MIPS_FPU_DOUBLE; | |
6298 | break; | |
6299 | case 2: | |
6300 | fpu_type = MIPS_FPU_SINGLE; | |
6301 | break; | |
6302 | case 3: | |
6303 | default: | |
6304 | /* Soft float or unknown. */ | |
6305 | fpu_type = MIPS_FPU_NONE; | |
6306 | break; | |
6307 | } | |
6308 | } | |
8d5838b5 AC |
6309 | else if (info.bfd_arch_info != NULL |
6310 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6311 | switch (info.bfd_arch_info->mach) | |
6312 | { | |
6313 | case bfd_mach_mips3900: | |
6314 | case bfd_mach_mips4100: | |
6315 | case bfd_mach_mips4111: | |
a9d61c86 | 6316 | case bfd_mach_mips4120: |
8d5838b5 AC |
6317 | fpu_type = MIPS_FPU_NONE; |
6318 | break; | |
6319 | case bfd_mach_mips4650: | |
6320 | fpu_type = MIPS_FPU_SINGLE; | |
6321 | break; | |
6322 | default: | |
6323 | fpu_type = MIPS_FPU_DOUBLE; | |
6324 | break; | |
6325 | } | |
6326 | else if (arches != NULL) | |
6327 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
6328 | else | |
6329 | fpu_type = MIPS_FPU_DOUBLE; | |
6330 | if (gdbarch_debug) | |
6331 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6332 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 6333 | |
29709017 DJ |
6334 | /* Check for blatant incompatibilities. */ |
6335 | ||
6336 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
6337 | ABI. */ | |
6338 | if (info.target_desc | |
6339 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
6340 | && mips_abi != MIPS_ABI_EABI32 | |
6341 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
6342 | { |
6343 | if (tdesc_data != NULL) | |
6344 | tdesc_data_cleanup (tdesc_data); | |
6345 | return NULL; | |
6346 | } | |
29709017 | 6347 | |
025bb325 | 6348 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
6349 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
6350 | arches != NULL; | |
6351 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
6352 | { | |
6353 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 6354 | using. */ |
9103eae0 | 6355 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 6356 | continue; |
9103eae0 | 6357 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 6358 | continue; |
719ec221 AC |
6359 | /* Need to be pedantic about which register virtual size is |
6360 | used. */ | |
6361 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
6362 | != mips64_transfers_32bit_regs_p) | |
6363 | continue; | |
8d5838b5 AC |
6364 | /* Be pedantic about which FPU is selected. */ |
6365 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
6366 | continue; | |
f8b73d13 DJ |
6367 | |
6368 | if (tdesc_data != NULL) | |
6369 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 6370 | return arches->gdbarch; |
c2d11a7d JM |
6371 | } |
6372 | ||
102182a9 | 6373 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
6374 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
6375 | gdbarch = gdbarch_alloc (&info, tdep); | |
6376 | tdep->elf_flags = elf_flags; | |
719ec221 | 6377 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
6378 | tdep->found_abi = found_abi; |
6379 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 6380 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
6381 | tdep->register_size_valid_p = 0; |
6382 | tdep->register_size = 0; | |
50e8a0d5 HZ |
6383 | tdep->gregset = NULL; |
6384 | tdep->gregset64 = NULL; | |
6385 | tdep->fpregset = NULL; | |
6386 | tdep->fpregset64 = NULL; | |
29709017 DJ |
6387 | |
6388 | if (info.target_desc) | |
6389 | { | |
6390 | /* Some useful properties can be inferred from the target. */ | |
6391 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
6392 | { | |
6393 | tdep->register_size_valid_p = 1; | |
6394 | tdep->register_size = 4; | |
6395 | } | |
6396 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
6397 | { | |
6398 | tdep->register_size_valid_p = 1; | |
6399 | tdep->register_size = 8; | |
6400 | } | |
6401 | } | |
c2d11a7d | 6402 | |
102182a9 | 6403 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
6404 | set_gdbarch_short_bit (gdbarch, 16); |
6405 | set_gdbarch_int_bit (gdbarch, 32); | |
6406 | set_gdbarch_float_bit (gdbarch, 32); | |
6407 | set_gdbarch_double_bit (gdbarch, 64); | |
6408 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
6409 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
6410 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
6411 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 6412 | |
175ff332 HZ |
6413 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
6414 | mips_ax_pseudo_register_collect); | |
6415 | set_gdbarch_ax_pseudo_register_push_stack | |
6416 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
6417 | ||
6d82d43b | 6418 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
6419 | mips_elf_make_msymbol_special); |
6420 | ||
1faeff08 MR |
6421 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
6422 | *regnum = mips_regnum; | |
1faeff08 MR |
6423 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
6424 | set_gdbarch_num_regs (gdbarch, num_regs); | |
6425 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6426 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6427 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
6428 | tdep->mips_processor_reg_names = reg_names; | |
6429 | tdep->regnum = regnum; | |
fe29b929 | 6430 | |
0dadbba0 | 6431 | switch (mips_abi) |
c2d11a7d | 6432 | { |
0dadbba0 | 6433 | case MIPS_ABI_O32: |
25ab4790 | 6434 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6435 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 6436 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6437 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6438 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6439 | set_gdbarch_long_bit (gdbarch, 32); |
6440 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6441 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6442 | break; | |
0dadbba0 | 6443 | case MIPS_ABI_O64: |
25ab4790 | 6444 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 6445 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 6446 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6447 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6448 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6449 | set_gdbarch_long_bit (gdbarch, 32); |
6450 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6451 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6452 | break; | |
0dadbba0 | 6453 | case MIPS_ABI_EABI32: |
25ab4790 | 6454 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6455 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6456 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6457 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6458 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6459 | set_gdbarch_long_bit (gdbarch, 32); |
6460 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6461 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6462 | break; | |
0dadbba0 | 6463 | case MIPS_ABI_EABI64: |
25ab4790 | 6464 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6465 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6466 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6467 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6468 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6469 | set_gdbarch_long_bit (gdbarch, 64); |
6470 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6471 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6472 | break; | |
0dadbba0 | 6473 | case MIPS_ABI_N32: |
25ab4790 | 6474 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6475 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6476 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6477 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6478 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6479 | set_gdbarch_long_bit (gdbarch, 32); |
6480 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6481 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6482 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6483 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
6484 | break; |
6485 | case MIPS_ABI_N64: | |
25ab4790 | 6486 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6487 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6488 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6489 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6490 | tdep->default_mask_address_p = 0; |
6491 | set_gdbarch_long_bit (gdbarch, 64); | |
6492 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6493 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6494 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6495 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 6496 | break; |
c2d11a7d | 6497 | default: |
e2e0b3e5 | 6498 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
6499 | } |
6500 | ||
22e47e37 FF |
6501 | /* GCC creates a pseudo-section whose name specifies the size of |
6502 | longs, since -mlong32 or -mlong64 may be used independent of | |
6503 | other options. How those options affect pointer sizes is ABI and | |
6504 | architecture dependent, so use them to override the default sizes | |
6505 | set by the ABI. This table shows the relationship between ABI, | |
6506 | -mlongXX, and size of pointers: | |
6507 | ||
6508 | ABI -mlongXX ptr bits | |
6509 | --- -------- -------- | |
6510 | o32 32 32 | |
6511 | o32 64 32 | |
6512 | n32 32 32 | |
6513 | n32 64 64 | |
6514 | o64 32 32 | |
6515 | o64 64 64 | |
6516 | n64 32 32 | |
6517 | n64 64 64 | |
6518 | eabi32 32 32 | |
6519 | eabi32 64 32 | |
6520 | eabi64 32 32 | |
6521 | eabi64 64 64 | |
6522 | ||
6523 | Note that for o32 and eabi32, pointers are always 32 bits | |
6524 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 6525 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
6526 | |
6527 | if (info.abfd != NULL) | |
6528 | { | |
6529 | int long_bit = 0; | |
6530 | ||
6531 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
6532 | if (long_bit) | |
6533 | { | |
6534 | set_gdbarch_long_bit (gdbarch, long_bit); | |
6535 | switch (mips_abi) | |
6536 | { | |
6537 | case MIPS_ABI_O32: | |
6538 | case MIPS_ABI_EABI32: | |
6539 | break; | |
6540 | case MIPS_ABI_N32: | |
6541 | case MIPS_ABI_O64: | |
6542 | case MIPS_ABI_N64: | |
6543 | case MIPS_ABI_EABI64: | |
6544 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
6545 | break; | |
6546 | default: | |
6547 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
6548 | } | |
6549 | } | |
6550 | } | |
6551 | ||
a5ea2558 AC |
6552 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6553 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6554 | comment: | |
6555 | ||
6556 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6557 | flag in object files because to do so would make it impossible to | |
102182a9 | 6558 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6559 | unnecessarily restrictive. |
361d1df0 | 6560 | |
a5ea2558 AC |
6561 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6562 | but to set this flag before gcc is built with such multilibs will | |
6563 | break too many systems.'' | |
6564 | ||
6565 | But even more unhelpfully, the default linker output target for | |
6566 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6567 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6568 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6569 | this flag to detect 32-bit mode would do the wrong thing given |
6570 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6571 | as 32-bit programs by default. */ |
a5ea2558 | 6572 | |
6c997a34 | 6573 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6574 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 6575 | |
102182a9 MS |
6576 | /* Add/remove bits from an address. The MIPS needs be careful to |
6577 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6578 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6579 | ||
58dfe9ff AC |
6580 | /* Unwind the frame. */ |
6581 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 6582 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 6583 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 6584 | |
102182a9 | 6585 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6586 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6587 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6588 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
6589 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
6590 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6591 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6592 | |
025bb325 | 6593 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 6594 | |
9710e734 AC |
6595 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6596 | replaced by a command, and all targets will default to on stack | |
6597 | (regardless of the stack's execute status). */ | |
6598 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6599 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6600 | |
87783b8b AC |
6601 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6602 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6603 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6604 | ||
f7b9e9fc AC |
6605 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6606 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
c8cef75f MR |
6607 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
6608 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
6609 | |
6610 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6611 | |
97ab0fdd MR |
6612 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6613 | ||
fc0c74b1 AC |
6614 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6615 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6616 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6617 | |
a4b8ebc8 | 6618 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6619 | |
e11c53d2 | 6620 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6621 | |
9dae60cc UW |
6622 | if (mips_abi == MIPS_ABI_N32) |
6623 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
6624 | else if (mips_abi == MIPS_ABI_N64) | |
6625 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
6626 | else | |
6627 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 6628 | |
d92524f1 PM |
6629 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6630 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6631 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6632 | being used as guards for target_stopped_by_watchpoint, why not have |
6633 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6634 | is sitting on? */ |
6635 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6636 | ||
e7d6a6d2 | 6637 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6638 | |
025bb325 MS |
6639 | set_gdbarch_single_step_through_delay (gdbarch, |
6640 | mips_single_step_through_delay); | |
3352ef37 | 6641 | |
0d5de010 DJ |
6642 | /* Virtual tables. */ |
6643 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6644 | ||
29709017 DJ |
6645 | mips_register_g_packet_guesses (gdbarch); |
6646 | ||
6de918a6 | 6647 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6648 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6649 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6650 | |
9aac7884 MR |
6651 | /* The hook may have adjusted num_regs, fetch the final value and |
6652 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
6653 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been | |
6654 | replaced by gdbarch_read_pc? */ | |
6655 | num_regs = gdbarch_num_regs (gdbarch); | |
6656 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
6657 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6658 | ||
5792a79b | 6659 | /* Unwind the frame. */ |
b8a22b94 DJ |
6660 | dwarf2_append_unwinders (gdbarch); |
6661 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6662 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6663 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6664 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6665 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6666 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6667 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6668 | |
f8b73d13 DJ |
6669 | if (tdesc_data) |
6670 | { | |
6671 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6672 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6673 | |
6674 | /* Override the normal target description methods to handle our | |
6675 | dual real and pseudo registers. */ | |
6676 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
6677 | set_gdbarch_register_reggroup_p (gdbarch, |
6678 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
6679 | |
6680 | num_regs = gdbarch_num_regs (gdbarch); | |
6681 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6682 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6683 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6684 | } | |
6685 | ||
6686 | /* Add ABI-specific aliases for the registers. */ | |
6687 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6688 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6689 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6690 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6691 | else | |
6692 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6693 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6694 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6695 | ||
6696 | /* Add some other standard aliases. */ | |
6697 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6698 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6699 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6700 | ||
865093a3 AR |
6701 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6702 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6703 | value_of_mips_user_reg, | |
6704 | &mips_numeric_register_aliases[i].regnum); | |
6705 | ||
4b9b3959 AC |
6706 | return gdbarch; |
6707 | } | |
6708 | ||
2e4ebe70 | 6709 | static void |
6d82d43b | 6710 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6711 | { |
6712 | struct gdbarch_info info; | |
6713 | ||
6714 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6715 | mips_gdbarch_init will take care of the rest. */ | |
6716 | gdbarch_info_init (&info); | |
6717 | gdbarch_update_p (info); | |
6718 | } | |
6719 | ||
ad188201 KB |
6720 | /* Print out which MIPS ABI is in use. */ |
6721 | ||
6722 | static void | |
1f8ca57c JB |
6723 | show_mips_abi (struct ui_file *file, |
6724 | int from_tty, | |
6725 | struct cmd_list_element *ignored_cmd, | |
6726 | const char *ignored_value) | |
ad188201 | 6727 | { |
1cf3db46 | 6728 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6729 | fprintf_filtered |
6730 | (file, | |
6731 | "The MIPS ABI is unknown because the current architecture " | |
6732 | "is not MIPS.\n"); | |
ad188201 KB |
6733 | else |
6734 | { | |
6735 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6736 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6737 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6738 | ||
6739 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6740 | fprintf_filtered |
6741 | (file, | |
6742 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6743 | actual_abi_str); |
ad188201 | 6744 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6745 | fprintf_filtered |
6746 | (file, | |
6747 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6748 | actual_abi_str); |
ad188201 KB |
6749 | else |
6750 | { | |
6751 | /* Probably shouldn't happen... */ | |
025bb325 MS |
6752 | fprintf_filtered (file, |
6753 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
6754 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 6755 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6756 | } |
6757 | } | |
6758 | } | |
6759 | ||
4b9b3959 | 6760 | static void |
72a155b4 | 6761 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6762 | { |
72a155b4 | 6763 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6764 | if (tdep != NULL) |
c2d11a7d | 6765 | { |
acdb74a0 AC |
6766 | int ef_mips_arch; |
6767 | int ef_mips_32bitmode; | |
f49e4e6d | 6768 | /* Determine the ISA. */ |
acdb74a0 AC |
6769 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6770 | { | |
6771 | case E_MIPS_ARCH_1: | |
6772 | ef_mips_arch = 1; | |
6773 | break; | |
6774 | case E_MIPS_ARCH_2: | |
6775 | ef_mips_arch = 2; | |
6776 | break; | |
6777 | case E_MIPS_ARCH_3: | |
6778 | ef_mips_arch = 3; | |
6779 | break; | |
6780 | case E_MIPS_ARCH_4: | |
93d56215 | 6781 | ef_mips_arch = 4; |
acdb74a0 AC |
6782 | break; |
6783 | default: | |
93d56215 | 6784 | ef_mips_arch = 0; |
acdb74a0 AC |
6785 | break; |
6786 | } | |
f49e4e6d | 6787 | /* Determine the size of a pointer. */ |
acdb74a0 | 6788 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6789 | fprintf_unfiltered (file, |
6790 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6791 | tdep->elf_flags); |
4b9b3959 | 6792 | fprintf_unfiltered (file, |
acdb74a0 AC |
6793 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6794 | ef_mips_32bitmode); | |
6795 | fprintf_unfiltered (file, | |
6796 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6797 | ef_mips_arch); | |
6798 | fprintf_unfiltered (file, | |
6799 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6800 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 6801 | fprintf_unfiltered (file, |
025bb325 MS |
6802 | "mips_dump_tdep: " |
6803 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6804 | mips_mask_address_p (tdep), |
4014092b | 6805 | tdep->default_mask_address_p); |
c2d11a7d | 6806 | } |
4b9b3959 AC |
6807 | fprintf_unfiltered (file, |
6808 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6809 | MIPS_DEFAULT_FPU_TYPE, | |
6810 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6811 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6812 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6813 | : "???")); | |
74ed0bb4 MD |
6814 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6815 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6816 | fprintf_unfiltered (file, |
6817 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6818 | MIPS_FPU_TYPE (gdbarch), |
6819 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6820 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6821 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6822 | : "???")); |
c2d11a7d JM |
6823 | } |
6824 | ||
025bb325 | 6825 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6826 | |
c906108c | 6827 | void |
acdb74a0 | 6828 | _initialize_mips_tdep (void) |
c906108c SS |
6829 | { |
6830 | static struct cmd_list_element *mipsfpulist = NULL; | |
6831 | struct cmd_list_element *c; | |
6832 | ||
6d82d43b | 6833 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6834 | if (MIPS_ABI_LAST + 1 |
6835 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6836 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6837 | |
4b9b3959 | 6838 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6839 | |
8d5f9dcb DJ |
6840 | mips_pdr_data = register_objfile_data (); |
6841 | ||
4eb0ad19 DJ |
6842 | /* Create feature sets with the appropriate properties. The values |
6843 | are not important. */ | |
6844 | mips_tdesc_gp32 = allocate_target_description (); | |
6845 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6846 | ||
6847 | mips_tdesc_gp64 = allocate_target_description (); | |
6848 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6849 | ||
025bb325 | 6850 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 6851 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 6852 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6853 | &setmipscmdlist, "set mips ", 0, &setlist); |
6854 | ||
6855 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6856 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6857 | &showmipscmdlist, "show mips ", 0, &showlist); |
6858 | ||
025bb325 | 6859 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6860 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6861 | &mips_abi_string, _("\ | |
6862 | Set the MIPS ABI used by this program."), _("\ | |
6863 | Show the MIPS ABI used by this program."), _("\ | |
6864 | This option can be set to one of:\n\ | |
6865 | auto - the default ABI associated with the current binary\n\ | |
6866 | o32\n\ | |
6867 | o64\n\ | |
6868 | n32\n\ | |
6869 | n64\n\ | |
6870 | eabi32\n\ | |
6871 | eabi64"), | |
6872 | mips_abi_update, | |
6873 | show_mips_abi, | |
6874 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6875 | |
c906108c SS |
6876 | /* Let the user turn off floating point and set the fence post for |
6877 | heuristic_proc_start. */ | |
6878 | ||
6879 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6880 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6881 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6882 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6883 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6884 | &mipsfpulist); |
6885 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6886 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6887 | &mipsfpulist); |
6888 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6889 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6890 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6891 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6892 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6893 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6894 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6895 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6896 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6897 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6898 | &mipsfpulist); |
6899 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6900 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6901 | &showlist); |
6902 | ||
c906108c SS |
6903 | /* We really would like to have both "0" and "unlimited" work, but |
6904 | command.c doesn't deal with that. So make it a var_zinteger | |
6905 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6906 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6907 | &heuristic_fence_post, _("\ |
6908 | Set the distance searched for the start of a function."), _("\ | |
6909 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6910 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6911 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6912 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6913 | reinit_frame_cache_sfunc, |
025bb325 MS |
6914 | NULL, /* FIXME: i18n: The distance searched for |
6915 | the start of a function is %s. */ | |
6bcadd06 | 6916 | &setlist, &showlist); |
c906108c SS |
6917 | |
6918 | /* Allow the user to control whether the upper bits of 64-bit | |
6919 | addresses should be zeroed. */ | |
7915a72c AC |
6920 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6921 | &mask_address_var, _("\ | |
6922 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6923 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 6924 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 6925 | allow GDB to determine the correct value."), |
08546159 AC |
6926 | NULL, show_mask_address, |
6927 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6928 | |
6929 | /* Allow the user to control the size of 32 bit registers within the | |
6930 | raw remote packet. */ | |
b3f42336 | 6931 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6932 | &mips64_transfers_32bit_regs_p, _("\ |
6933 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6934 | _("\ | |
6935 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6936 | _("\ | |
719ec221 AC |
6937 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6938 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6939 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6940 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
6941 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
6942 | MIPS target that transfers 32-bit | |
6943 | quantities is %s. */ | |
7915a72c | 6944 | &setlist, &showlist); |
9ace0497 | 6945 | |
025bb325 | 6946 | /* Debug this files internals. */ |
6bcadd06 | 6947 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6948 | &mips_debug, _("\ |
6949 | Set mips debugging."), _("\ | |
6950 | Show mips debugging."), _("\ | |
6951 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6952 | NULL, |
025bb325 MS |
6953 | NULL, /* FIXME: i18n: Mips debugging is |
6954 | currently %s. */ | |
6bcadd06 | 6955 | &setdebuglist, &showdebuglist); |
c906108c | 6956 | } |