Commit | Line | Data |
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7d9884b9 | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
0434c1a0 PS |
2 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994 |
3 | Free Software Foundation, Inc. | |
bd5635a1 RP |
4 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
5 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
361bf6ee | 9 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 10 | it under the terms of the GNU General Public License as published by |
361bf6ee JG |
11 | the Free Software Foundation; either version 2 of the License, or |
12 | (at your option) any later version. | |
bd5635a1 | 13 | |
361bf6ee | 14 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
361bf6ee JG |
20 | along with this program; if not, write to the Free Software |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
bd5635a1 | 22 | |
bd5635a1 | 23 | #include "defs.h" |
bd5635a1 RP |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
ef08856f | 29 | #include "language.h" |
bd5635a1 | 30 | #include "gdbcore.h" |
62a469e1 SG |
31 | #include "symfile.h" |
32 | #include "objfiles.h" | |
3fed1c4a | 33 | #include "gdbtypes.h" |
bd5635a1 | 34 | |
ee5fb959 JK |
35 | #include "opcode/mips.h" |
36 | ||
bd5635a1 | 37 | #define VM_MIN_ADDRESS (unsigned)0x400000 |
70126bf9 KH |
38 | |
39 | /* FIXME: Put this declaration in frame.h. */ | |
40 | extern struct obstack frame_cache_obstack; | |
bd5635a1 | 41 | \f |
002a422b | 42 | #if 0 |
ee5fb959 | 43 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
002a422b | 44 | #endif |
ee5fb959 | 45 | |
9f9f94aa SS |
46 | void mips_set_processor_type_command PARAMS ((char *, int)); |
47 | ||
48 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, | |
49 | struct cmd_list_element *)); | |
50 | ||
51 | /* This value is the model of MIPS in use. It is derived from the value | |
52 | of the PrID register. */ | |
53 | ||
54 | char *mips_processor_type; | |
55 | ||
56 | char *tmp_mips_processor_type; | |
57 | ||
c2a0f1cb ILT |
58 | /* Some MIPS boards don't support floating point, so we permit the |
59 | user to turn it off. */ | |
9f9f94aa | 60 | |
c2a0f1cb ILT |
61 | int mips_fpu = 1; |
62 | ||
9f9f94aa SS |
63 | /* A set of original names, to be used when restoring back to generic |
64 | registers from a specific set. */ | |
65 | ||
66 | char *mips_generic_reg_names[] = REGISTER_NAMES; | |
67 | ||
68 | /* Names of IDT R3041 registers. */ | |
69 | ||
70 | char *mips_r3041_reg_names[] = { | |
71 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
72 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
73 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
74 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
75 | "sr", "lo", "hi", "bad", "cause","pc", | |
76 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
77 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
78 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
79 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
80 | "fsr", "fir", "fp", "", | |
81 | "", "", "bus", "ccfg", "", "", "", "", | |
82 | "", "", "port", "cmp", "", "", "epc", "prid", | |
83 | }; | |
84 | ||
85 | /* Names of IDT R3051 registers. */ | |
86 | ||
87 | char *mips_r3051_reg_names[] = { | |
88 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
89 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
90 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
91 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
92 | "sr", "lo", "hi", "bad", "cause","pc", | |
93 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
94 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
95 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
96 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
97 | "fsr", "fir", "fp", "", | |
98 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
99 | "", "", "ehi", "", "", "", "epc", "prid", | |
100 | }; | |
101 | ||
102 | /* Names of IDT R3081 registers. */ | |
103 | ||
104 | char *mips_r3081_reg_names[] = { | |
105 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
106 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
107 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
108 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
109 | "sr", "lo", "hi", "bad", "cause","pc", | |
110 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
111 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
112 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
113 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
114 | "fsr", "fir", "fp", "", | |
115 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
116 | "", "", "ehi", "", "", "", "epc", "prid", | |
117 | }; | |
118 | ||
119 | struct { | |
120 | char *name; | |
121 | char **regnames; | |
122 | } mips_processor_type_table[] = { | |
123 | { "generic", mips_generic_reg_names }, | |
124 | { "r3041", mips_r3041_reg_names }, | |
125 | { "r3051", mips_r3051_reg_names }, | |
126 | { "r3071", mips_r3081_reg_names }, | |
127 | { "r3081", mips_r3081_reg_names }, | |
128 | { NULL, NULL } | |
129 | }; | |
130 | ||
3127785a RP |
131 | /* Heuristic_proc_start may hunt through the text section for a long |
132 | time across a 2400 baud serial line. Allows the user to limit this | |
133 | search. */ | |
9f9f94aa | 134 | |
3127785a RP |
135 | static unsigned int heuristic_fence_post = 0; |
136 | ||
0f552c5f JG |
137 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
138 | #define PROC_HIGH_ADDR(proc) ((proc)->pdr.iline) /* upper address bound */ | |
139 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) | |
140 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
141 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
142 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
143 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
144 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
145 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
146 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
bd5635a1 | 147 | #define _PROC_MAGIC_ 0x0F0F0F0F |
0f552c5f JG |
148 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
149 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
bd5635a1 RP |
150 | |
151 | struct linked_proc_info | |
152 | { | |
153 | struct mips_extra_func_info info; | |
154 | struct linked_proc_info *next; | |
dac4929a | 155 | } *linked_proc_desc_table = NULL; |
bd5635a1 RP |
156 | |
157 | \f | |
70126bf9 KH |
158 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
159 | NULL). */ | |
160 | ||
161 | void | |
162 | mips_find_saved_regs (fci) | |
9f9f94aa | 163 | struct frame_info *fci; |
70126bf9 KH |
164 | { |
165 | int ireg; | |
166 | CORE_ADDR reg_position; | |
167 | /* r0 bit means kernel trap */ | |
168 | int kernel_trap; | |
169 | /* What registers have been saved? Bitmasks. */ | |
170 | unsigned long gen_mask, float_mask; | |
171 | mips_extra_func_info_t proc_desc; | |
172 | ||
173 | fci->saved_regs = (struct frame_saved_regs *) | |
174 | obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs)); | |
175 | memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs)); | |
176 | ||
177 | proc_desc = fci->proc_desc; | |
178 | if (proc_desc == NULL) | |
179 | /* I'm not sure how/whether this can happen. Normally when we can't | |
180 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
181 | and set the saved_regs right away. */ | |
182 | return; | |
183 | ||
184 | kernel_trap = PROC_REG_MASK(proc_desc) & 1; | |
185 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); | |
186 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); | |
187 | ||
188 | if (/* In any frame other than the innermost, we assume that all | |
189 | registers have been saved. This assumes that all register | |
190 | saves in a function happen before the first function | |
191 | call. */ | |
192 | fci->next == NULL | |
193 | ||
194 | /* In a dummy frame we know exactly where things are saved. */ | |
195 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
196 | ||
197 | /* Not sure exactly what kernel_trap means, but if it means | |
198 | the kernel saves the registers without a prologue doing it, | |
199 | we better not examine the prologue to see whether registers | |
200 | have been saved yet. */ | |
201 | && !kernel_trap) | |
202 | { | |
203 | /* We need to figure out whether the registers that the proc_desc | |
204 | claims are saved have been saved yet. */ | |
205 | ||
206 | CORE_ADDR addr; | |
207 | int status; | |
208 | char buf[4]; | |
209 | unsigned long inst; | |
210 | ||
211 | /* Bitmasks; set if we have found a save for the register. */ | |
212 | unsigned long gen_save_found = 0; | |
213 | unsigned long float_save_found = 0; | |
214 | ||
215 | for (addr = PROC_LOW_ADDR (proc_desc); | |
216 | addr < fci->pc /*&& (gen_mask != gen_save_found | |
217 | || float_mask != float_save_found)*/; | |
218 | addr += 4) | |
219 | { | |
220 | status = read_memory_nobpt (addr, buf, 4); | |
221 | if (status) | |
222 | memory_error (status, addr); | |
223 | inst = extract_unsigned_integer (buf, 4); | |
224 | if (/* sw reg,n($sp) */ | |
225 | (inst & 0xffe00000) == 0xafa00000 | |
226 | ||
227 | /* sw reg,n($r30) */ | |
228 | || (inst & 0xffe00000) == 0xafc00000 | |
229 | ||
230 | /* sd reg,n($sp) */ | |
231 | || (inst & 0xffe00000) == 0xffa00000) | |
232 | { | |
233 | /* It might be possible to use the instruction to | |
234 | find the offset, rather than the code below which | |
235 | is based on things being in a certain order in the | |
236 | frame, but figuring out what the instruction's offset | |
237 | is relative to might be a little tricky. */ | |
238 | int reg = (inst & 0x001f0000) >> 16; | |
239 | gen_save_found |= (1 << reg); | |
240 | } | |
241 | else if (/* swc1 freg,n($sp) */ | |
242 | (inst & 0xffe00000) == 0xe7a00000 | |
243 | ||
244 | /* swc1 freg,n($r30) */ | |
245 | || (inst & 0xffe00000) == 0xe7c00000 | |
246 | ||
247 | /* sdc1 freg,n($sp) */ | |
248 | || (inst & 0xffe00000) == 0xf7a00000) | |
249 | ||
250 | { | |
251 | int reg = ((inst & 0x001f0000) >> 16); | |
252 | float_save_found |= (1 << reg); | |
253 | } | |
254 | } | |
255 | gen_mask = gen_save_found; | |
256 | float_mask = float_save_found; | |
257 | } | |
258 | ||
259 | /* Fill in the offsets for the registers which gen_mask says | |
260 | were saved. */ | |
261 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
262 | for (ireg= 31; gen_mask; --ireg, gen_mask <<= 1) | |
263 | if (gen_mask & 0x80000000) | |
264 | { | |
265 | fci->saved_regs->regs[ireg] = reg_position; | |
266 | reg_position -= MIPS_REGSIZE; | |
267 | } | |
268 | /* Fill in the offsets for the registers which float_mask says | |
269 | were saved. */ | |
270 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
271 | ||
272 | /* The freg_offset points to where the first *double* register | |
273 | is saved. So skip to the high-order word. */ | |
274 | reg_position += 4; | |
275 | for (ireg = 31; float_mask; --ireg, float_mask <<= 1) | |
276 | if (float_mask & 0x80000000) | |
277 | { | |
278 | fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position; | |
279 | reg_position -= MIPS_REGSIZE; | |
280 | } | |
281 | ||
282 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; | |
283 | } | |
bd5635a1 | 284 | |
0f552c5f | 285 | static int |
bd5635a1 | 286 | read_next_frame_reg(fi, regno) |
9f9f94aa | 287 | struct frame_info *fi; |
bd5635a1 RP |
288 | int regno; |
289 | { | |
e157305c | 290 | /* If it is the frame for sigtramp we have a complete sigcontext |
0434c1a0 | 291 | somewhere above the frame and we get the saved registers from there. |
e157305c | 292 | If the stack layout for sigtramp changes we might have to change these |
e03c0cc6 | 293 | constants and the companion fixup_sigtramp in mdebugread.c */ |
1b71de8e | 294 | #ifndef SIGFRAME_BASE |
0434c1a0 PS |
295 | /* To satisfy alignment restrictions the sigcontext is located 4 bytes |
296 | above the sigtramp frame. */ | |
297 | #define SIGFRAME_BASE 4 | |
298 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * 4) | |
299 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * 4) | |
5efd597b PS |
300 | #endif |
301 | #ifndef SIGFRAME_REG_SIZE | |
e03c0cc6 | 302 | #define SIGFRAME_REG_SIZE 4 |
1b71de8e | 303 | #endif |
bd5635a1 | 304 | for (; fi; fi = fi->next) |
70126bf9 KH |
305 | { |
306 | if (fi->signal_handler_caller) | |
307 | { | |
bd5635a1 RP |
308 | int offset; |
309 | if (regno == PC_REGNUM) offset = SIGFRAME_PC_OFF; | |
e03c0cc6 ILT |
310 | else if (regno < 32) offset = (SIGFRAME_REGSAVE_OFF |
311 | + regno * SIGFRAME_REG_SIZE); | |
bd5635a1 | 312 | else return 0; |
70126bf9 KH |
313 | return read_memory_integer(fi->frame + offset, MIPS_REGSIZE); |
314 | } | |
bd5635a1 | 315 | else if (regno == SP_REGNUM) return fi->frame; |
70126bf9 KH |
316 | else |
317 | { | |
318 | if (fi->saved_regs == NULL) | |
319 | mips_find_saved_regs (fi); | |
320 | if (fi->saved_regs->regs[regno]) | |
321 | return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE); | |
322 | } | |
323 | } | |
324 | return read_register (regno); | |
bd5635a1 RP |
325 | } |
326 | ||
327 | int | |
328 | mips_frame_saved_pc(frame) | |
9f9f94aa | 329 | struct frame_info *frame; |
bd5635a1 | 330 | { |
0f552c5f | 331 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
0434c1a0 PS |
332 | /* We have to get the saved pc from the sigcontext |
333 | if it is a signal handler frame. */ | |
334 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
335 | : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); | |
0f552c5f | 336 | |
bd5635a1 RP |
337 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
338 | return read_memory_integer(frame->frame - 4, 4); | |
0f552c5f | 339 | |
bd5635a1 RP |
340 | return read_next_frame_reg(frame, pcreg); |
341 | } | |
342 | ||
343 | static struct mips_extra_func_info temp_proc_desc; | |
344 | static struct frame_saved_regs temp_saved_regs; | |
345 | ||
a8172eea RP |
346 | /* This fencepost looks highly suspicious to me. Removing it also |
347 | seems suspicious as it could affect remote debugging across serial | |
3127785a | 348 | lines. */ |
a8172eea | 349 | |
0f552c5f JG |
350 | static CORE_ADDR |
351 | heuristic_proc_start(pc) | |
bd5635a1 RP |
352 | CORE_ADDR pc; |
353 | { | |
bd5635a1 | 354 | CORE_ADDR start_pc = pc; |
3127785a | 355 | CORE_ADDR fence = start_pc - heuristic_fence_post; |
0f552c5f JG |
356 | |
357 | if (start_pc == 0) return 0; | |
3127785a RP |
358 | |
359 | if (heuristic_fence_post == UINT_MAX | |
360 | || fence < VM_MIN_ADDRESS) | |
361 | fence = VM_MIN_ADDRESS; | |
0f552c5f | 362 | |
bd5635a1 RP |
363 | /* search back for previous return */ |
364 | for (start_pc -= 4; ; start_pc -= 4) | |
a8172eea RP |
365 | if (start_pc < fence) |
366 | { | |
3127785a RP |
367 | /* It's not clear to me why we reach this point when |
368 | stop_soon_quietly, but with this test, at least we | |
369 | don't print out warnings for every child forked (eg, on | |
370 | decstation). 22apr93 rich@cygnus.com. */ | |
371 | if (!stop_soon_quietly) | |
372 | { | |
23d35572 JK |
373 | static int blurb_printed = 0; |
374 | ||
3127785a RP |
375 | if (fence == VM_MIN_ADDRESS) |
376 | warning("Hit beginning of text section without finding"); | |
377 | else | |
378 | warning("Hit heuristic-fence-post without finding"); | |
379 | ||
23d35572 JK |
380 | warning("enclosing function for address 0x%x", pc); |
381 | if (!blurb_printed) | |
382 | { | |
383 | printf_filtered ("\ | |
384 | This warning occurs if you are debugging a function without any symbols\n\ | |
385 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
386 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
387 | \n\ | |
388 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
389 | (more likely) you have encountered a bug in GDB.\n"); | |
390 | blurb_printed = 1; | |
391 | } | |
3127785a RP |
392 | } |
393 | ||
a8172eea RP |
394 | return 0; |
395 | } | |
bd5635a1 RP |
396 | else if (ABOUT_TO_RETURN(start_pc)) |
397 | break; | |
398 | ||
399 | start_pc += 8; /* skip return, and its delay slot */ | |
400 | #if 0 | |
401 | /* skip nops (usually 1) 0 - is this */ | |
402 | while (start_pc < pc && read_memory_integer (start_pc, 4) == 0) | |
403 | start_pc += 4; | |
404 | #endif | |
405 | return start_pc; | |
406 | } | |
407 | ||
0f552c5f | 408 | static mips_extra_func_info_t |
bd5635a1 RP |
409 | heuristic_proc_desc(start_pc, limit_pc, next_frame) |
410 | CORE_ADDR start_pc, limit_pc; | |
9f9f94aa | 411 | struct frame_info *next_frame; |
bd5635a1 | 412 | { |
ac57e5ad | 413 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); |
bd5635a1 RP |
414 | CORE_ADDR cur_pc; |
415 | int frame_size; | |
416 | int has_frame_reg = 0; | |
e03c0cc6 | 417 | int reg30 = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
bd5635a1 RP |
418 | unsigned long reg_mask = 0; |
419 | ||
420 | if (start_pc == 0) return NULL; | |
9f9f94aa SS |
421 | memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); |
422 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); | |
423 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; | |
a70dc898 | 424 | |
9f9f94aa SS |
425 | if (start_pc + 200 < limit_pc) |
426 | limit_pc = start_pc + 200; | |
bd5635a1 RP |
427 | restart: |
428 | frame_size = 0; | |
429 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += 4) { | |
34df79fc | 430 | char buf[4]; |
bd5635a1 RP |
431 | unsigned long word; |
432 | int status; | |
433 | ||
34df79fc JK |
434 | status = read_memory_nobpt (cur_pc, buf, 4); |
435 | if (status) memory_error (status, cur_pc); | |
436 | word = extract_unsigned_integer (buf, 4); | |
437 | ||
bd5635a1 RP |
438 | if ((word & 0xFFFF0000) == 0x27bd0000) /* addiu $sp,$sp,-i */ |
439 | frame_size += (-word) & 0xFFFF; | |
440 | else if ((word & 0xFFFF0000) == 0x23bd0000) /* addu $sp,$sp,-i */ | |
441 | frame_size += (-word) & 0xFFFF; | |
442 | else if ((word & 0xFFE00000) == 0xafa00000) { /* sw reg,offset($sp) */ | |
443 | int reg = (word & 0x001F0000) >> 16; | |
444 | reg_mask |= 1 << reg; | |
002a422b | 445 | temp_saved_regs.regs[reg] = sp + (word & 0xffff); |
bd5635a1 RP |
446 | } |
447 | else if ((word & 0xFFFF0000) == 0x27be0000) { /* addiu $30,$sp,size */ | |
002a422b JK |
448 | if ((word & 0xffff) != frame_size) |
449 | reg30 = sp + (word & 0xffff); | |
bd5635a1 RP |
450 | else if (!has_frame_reg) { |
451 | int alloca_adjust; | |
452 | has_frame_reg = 1; | |
453 | reg30 = read_next_frame_reg(next_frame, 30); | |
002a422b | 454 | alloca_adjust = reg30 - (sp + (word & 0xffff)); |
bd5635a1 RP |
455 | if (alloca_adjust > 0) { |
456 | /* FP > SP + frame_size. This may be because | |
e03c0cc6 | 457 | * of an alloca or somethings similar. |
bd5635a1 RP |
458 | * Fix sp to "pre-alloca" value, and try again. |
459 | */ | |
460 | sp += alloca_adjust; | |
461 | goto restart; | |
462 | } | |
463 | } | |
464 | } | |
465 | else if ((word & 0xFFE00000) == 0xafc00000) { /* sw reg,offset($30) */ | |
466 | int reg = (word & 0x001F0000) >> 16; | |
467 | reg_mask |= 1 << reg; | |
002a422b | 468 | temp_saved_regs.regs[reg] = reg30 + (word & 0xffff); |
bd5635a1 RP |
469 | } |
470 | } | |
471 | if (has_frame_reg) { | |
472 | PROC_FRAME_REG(&temp_proc_desc) = 30; | |
473 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; | |
474 | } | |
475 | else { | |
476 | PROC_FRAME_REG(&temp_proc_desc) = SP_REGNUM; | |
477 | PROC_FRAME_OFFSET(&temp_proc_desc) = frame_size; | |
478 | } | |
479 | PROC_REG_MASK(&temp_proc_desc) = reg_mask; | |
480 | PROC_PC_REG(&temp_proc_desc) = RA_REGNUM; | |
481 | return &temp_proc_desc; | |
482 | } | |
483 | ||
0f552c5f | 484 | static mips_extra_func_info_t |
9f9f94aa SS |
485 | find_proc_desc (pc, next_frame) |
486 | CORE_ADDR pc; | |
487 | struct frame_info *next_frame; | |
bd5635a1 RP |
488 | { |
489 | mips_extra_func_info_t proc_desc; | |
0f552c5f | 490 | struct block *b = block_for_pc(pc); |
48be4c35 JK |
491 | struct symbol *sym; |
492 | CORE_ADDR startaddr; | |
493 | ||
494 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
495 | if (b == NULL) | |
496 | sym = NULL; | |
497 | else | |
498 | { | |
499 | if (startaddr > BLOCK_START (b)) | |
500 | /* This is the "pathological" case referred to in a comment in | |
501 | print_frame_info. It might be better to move this check into | |
502 | symbol reading. */ | |
503 | sym = NULL; | |
504 | else | |
505 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, | |
506 | 0, NULL); | |
507 | } | |
0f552c5f JG |
508 | |
509 | if (sym) | |
bd5635a1 RP |
510 | { |
511 | /* IF this is the topmost frame AND | |
512 | * (this proc does not have debugging information OR | |
513 | * the PC is in the procedure prologue) | |
be772100 | 514 | * THEN create a "heuristic" proc_desc (by analyzing |
bd5635a1 RP |
515 | * the actual code) to replace the "official" proc_desc. |
516 | */ | |
9f9f94aa | 517 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
bd5635a1 RP |
518 | if (next_frame == NULL) { |
519 | struct symtab_and_line val; | |
520 | struct symbol *proc_symbol = | |
521 | PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); | |
0f552c5f | 522 | |
bd5635a1 RP |
523 | if (proc_symbol) { |
524 | val = find_pc_line (BLOCK_START | |
525 | (SYMBOL_BLOCK_VALUE(proc_symbol)), | |
526 | 0); | |
527 | val.pc = val.end ? val.end : pc; | |
528 | } | |
529 | if (!proc_symbol || pc < val.pc) { | |
530 | mips_extra_func_info_t found_heuristic = | |
9f9f94aa SS |
531 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
532 | pc, next_frame); | |
533 | if (found_heuristic) | |
534 | proc_desc = found_heuristic; | |
bd5635a1 RP |
535 | } |
536 | } | |
537 | } | |
538 | else | |
539 | { | |
0f552c5f JG |
540 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
541 | by procedure call dummys. However, the procedures being called ought | |
542 | to have their own proc_descs, and even if they don't, | |
543 | heuristic_proc_desc knows how to create them! */ | |
544 | ||
bd5635a1 | 545 | register struct linked_proc_info *link; |
9f9f94aa | 546 | |
bd5635a1 | 547 | for (link = linked_proc_desc_table; link; link = link->next) |
9f9f94aa SS |
548 | if (PROC_LOW_ADDR(&link->info) <= pc |
549 | && PROC_HIGH_ADDR(&link->info) > pc) | |
550 | return &link->info; | |
23d35572 | 551 | |
48be4c35 JK |
552 | if (startaddr == 0) |
553 | startaddr = heuristic_proc_start (pc); | |
554 | ||
bd5635a1 | 555 | proc_desc = |
48be4c35 | 556 | heuristic_proc_desc (startaddr, pc, next_frame); |
bd5635a1 RP |
557 | } |
558 | return proc_desc; | |
559 | } | |
560 | ||
561 | mips_extra_func_info_t cached_proc_desc; | |
562 | ||
9f9f94aa | 563 | CORE_ADDR |
0f552c5f | 564 | mips_frame_chain(frame) |
9f9f94aa | 565 | struct frame_info *frame; |
bd5635a1 | 566 | { |
bd5635a1 RP |
567 | mips_extra_func_info_t proc_desc; |
568 | CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); | |
be772100 | 569 | |
0f552c5f JG |
570 | if (saved_pc == 0 || inside_entry_file (saved_pc)) |
571 | return 0; | |
572 | ||
bd5635a1 | 573 | proc_desc = find_proc_desc(saved_pc, frame); |
0f552c5f JG |
574 | if (!proc_desc) |
575 | return 0; | |
576 | ||
bd5635a1 | 577 | cached_proc_desc = proc_desc; |
e797b4bc JK |
578 | |
579 | /* If no frame pointer and frame size is zero, we must be at end | |
580 | of stack (or otherwise hosed). If we don't check frame size, | |
581 | we loop forever if we see a zero size frame. */ | |
582 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
3f528883 | 583 | && PROC_FRAME_OFFSET (proc_desc) == 0 |
199b2450 TL |
584 | /* The previous frame from a sigtramp frame might be frameless |
585 | and have frame size zero. */ | |
586 | && !frame->signal_handler_caller) | |
bdef72d2 JK |
587 | return 0; |
588 | else | |
589 | return read_next_frame_reg(frame, PROC_FRAME_REG(proc_desc)) | |
590 | + PROC_FRAME_OFFSET(proc_desc); | |
bd5635a1 RP |
591 | } |
592 | ||
593 | void | |
594 | init_extra_frame_info(fci) | |
595 | struct frame_info *fci; | |
596 | { | |
bd5635a1 | 597 | /* Use proc_desc calculated in frame_chain */ |
ee5fb959 JK |
598 | mips_extra_func_info_t proc_desc = |
599 | fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); | |
0f552c5f | 600 | |
70126bf9 | 601 | fci->saved_regs = NULL; |
bd5635a1 | 602 | fci->proc_desc = |
ee5fb959 | 603 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
bd5635a1 RP |
604 | if (proc_desc) |
605 | { | |
c2a0f1cb | 606 | /* Fixup frame-pointer - only needed for top frame */ |
5efd597b PS |
607 | /* This may not be quite right, if proc has a real frame register. |
608 | Get the value of the frame relative sp, procedure might have been | |
609 | interrupted by a signal at it's very start. */ | |
70126bf9 KH |
610 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
611 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
612 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
c2a0f1cb | 613 | else |
70126bf9 KH |
614 | fci->frame = |
615 | read_next_frame_reg (fci->next, PROC_FRAME_REG (proc_desc)) | |
616 | + PROC_FRAME_OFFSET (proc_desc); | |
bd5635a1 | 617 | |
48be4c35 | 618 | if (proc_desc == &temp_proc_desc) |
ee5fb959 | 619 | { |
70126bf9 KH |
620 | fci->saved_regs = (struct frame_saved_regs*) |
621 | obstack_alloc (&frame_cache_obstack, | |
622 | sizeof (struct frame_saved_regs)); | |
623 | *fci->saved_regs = temp_saved_regs; | |
624 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; | |
ee5fb959 | 625 | } |
bd5635a1 RP |
626 | |
627 | /* hack: if argument regs are saved, guess these contain args */ | |
628 | if ((PROC_REG_MASK(proc_desc) & 0xF0) == 0) fci->num_args = -1; | |
629 | else if ((PROC_REG_MASK(proc_desc) & 0x80) == 0) fci->num_args = 4; | |
630 | else if ((PROC_REG_MASK(proc_desc) & 0x40) == 0) fci->num_args = 3; | |
631 | else if ((PROC_REG_MASK(proc_desc) & 0x20) == 0) fci->num_args = 2; | |
632 | else if ((PROC_REG_MASK(proc_desc) & 0x10) == 0) fci->num_args = 1; | |
bd5635a1 | 633 | } |
bd5635a1 RP |
634 | } |
635 | ||
a70dc898 RP |
636 | /* MIPS stack frames are almost impenetrable. When execution stops, |
637 | we basically have to look at symbol information for the function | |
638 | that we stopped in, which tells us *which* register (if any) is | |
639 | the base of the frame pointer, and what offset from that register | |
640 | the frame itself is at. | |
641 | ||
642 | This presents a problem when trying to examine a stack in memory | |
643 | (that isn't executing at the moment), using the "frame" command. We | |
644 | don't have a PC, nor do we have any registers except SP. | |
645 | ||
646 | This routine takes two arguments, SP and PC, and tries to make the | |
647 | cached frames look as if these two arguments defined a frame on the | |
648 | cache. This allows the rest of info frame to extract the important | |
649 | arguments without difficulty. */ | |
650 | ||
9f9f94aa | 651 | struct frame_info * |
c2a0f1cb ILT |
652 | setup_arbitrary_frame (argc, argv) |
653 | int argc; | |
9f9f94aa | 654 | CORE_ADDR *argv; |
a70dc898 | 655 | { |
c2a0f1cb ILT |
656 | if (argc != 2) |
657 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
658 | ||
659 | return create_new_frame (argv[0], argv[1]); | |
a70dc898 RP |
660 | } |
661 | ||
bd5635a1 | 662 | |
0f552c5f JG |
663 | CORE_ADDR |
664 | mips_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
bd5635a1 | 665 | int nargs; |
ac57e5ad | 666 | value_ptr *args; |
bd5635a1 RP |
667 | CORE_ADDR sp; |
668 | int struct_return; | |
669 | CORE_ADDR struct_addr; | |
670 | { | |
bd5635a1 | 671 | register i; |
70126bf9 | 672 | int accumulate_size = struct_return ? MIPS_REGSIZE : 0; |
bd5635a1 RP |
673 | struct mips_arg { char *contents; int len; int offset; }; |
674 | struct mips_arg *mips_args = | |
70126bf9 | 675 | (struct mips_arg*)alloca((nargs + 4) * sizeof(struct mips_arg)); |
bd5635a1 | 676 | register struct mips_arg *m_arg; |
70126bf9 KH |
677 | int fake_args = 0; |
678 | ||
bd5635a1 | 679 | for (i = 0, m_arg = mips_args; i < nargs; i++, m_arg++) { |
ac57e5ad | 680 | value_ptr arg = value_arg_coerce (args[i]); |
bd5635a1 RP |
681 | m_arg->len = TYPE_LENGTH (VALUE_TYPE (arg)); |
682 | /* This entire mips-specific routine is because doubles must be aligned | |
683 | * on 8-byte boundaries. It still isn't quite right, because MIPS decided | |
684 | * to align 'struct {int a, b}' on 4-byte boundaries (even though this | |
685 | * breaks their varargs implementation...). A correct solution | |
686 | * requires an simulation of gcc's 'alignof' (and use of 'alignof' | |
687 | * in stdarg.h/varargs.h). | |
70126bf9 KH |
688 | * On the 64 bit r4000 we always pass the first four arguments |
689 | * using eight bytes each, so that we can load them up correctly | |
690 | * in CALL_DUMMY. | |
bd5635a1 | 691 | */ |
70126bf9 KH |
692 | if (m_arg->len > 4) |
693 | accumulate_size = (accumulate_size + 7) & -8; | |
bd5635a1 | 694 | m_arg->offset = accumulate_size; |
bd5635a1 | 695 | m_arg->contents = VALUE_CONTENTS(arg); |
9f9f94aa SS |
696 | if (! GDB_TARGET_IS_MIPS64) |
697 | accumulate_size = (accumulate_size + m_arg->len + 3) & -4; | |
70126bf9 KH |
698 | else |
699 | { | |
9f9f94aa SS |
700 | if (accumulate_size >= 4 * MIPS_REGSIZE) |
701 | accumulate_size = (accumulate_size + m_arg->len + 3) &~ 4; | |
702 | else | |
70126bf9 | 703 | { |
9f9f94aa SS |
704 | static char zeroes[8] = { 0 }; |
705 | int len = m_arg->len; | |
706 | ||
707 | if (len < 8) | |
708 | { | |
709 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
710 | m_arg->offset += 8 - len; | |
711 | ++m_arg; | |
712 | m_arg->len = 8 - len; | |
713 | m_arg->contents = zeroes; | |
714 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
715 | m_arg->offset = accumulate_size; | |
716 | else | |
717 | m_arg->offset = accumulate_size + len; | |
718 | ++fake_args; | |
719 | } | |
720 | accumulate_size = (accumulate_size + len + 7) & ~8; | |
70126bf9 | 721 | } |
70126bf9 | 722 | } |
bd5635a1 RP |
723 | } |
724 | accumulate_size = (accumulate_size + 7) & (-8); | |
70126bf9 KH |
725 | if (accumulate_size < 4 * MIPS_REGSIZE) |
726 | accumulate_size = 4 * MIPS_REGSIZE; | |
bd5635a1 | 727 | sp -= accumulate_size; |
70126bf9 | 728 | for (i = nargs + fake_args; m_arg--, --i >= 0; ) |
bd5635a1 | 729 | write_memory(sp + m_arg->offset, m_arg->contents, m_arg->len); |
5efd597b PS |
730 | if (struct_return) |
731 | { | |
732 | char buf[TARGET_PTR_BIT / HOST_CHAR_BIT]; | |
733 | ||
734 | store_address (buf, sizeof buf, struct_addr); | |
735 | write_memory (sp, buf, sizeof buf); | |
736 | } | |
bd5635a1 RP |
737 | return sp; |
738 | } | |
739 | ||
740 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<31. */ | |
e03c0cc6 | 741 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
bd5635a1 RP |
742 | |
743 | void | |
744 | mips_push_dummy_frame() | |
745 | { | |
5efd597b | 746 | char buffer[MAX_REGISTER_RAW_SIZE]; |
bd5635a1 RP |
747 | int ireg; |
748 | struct linked_proc_info *link = (struct linked_proc_info*) | |
749 | xmalloc(sizeof(struct linked_proc_info)); | |
750 | mips_extra_func_info_t proc_desc = &link->info; | |
751 | CORE_ADDR sp = read_register (SP_REGNUM); | |
752 | CORE_ADDR save_address; | |
bd5635a1 RP |
753 | link->next = linked_proc_desc_table; |
754 | linked_proc_desc_table = link; | |
755 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ | |
756 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<31) | |
757 | #define GEN_REG_SAVE_COUNT 22 | |
758 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
759 | #define FLOAT_REG_SAVE_COUNT 20 | |
760 | #define SPECIAL_REG_SAVE_COUNT 4 | |
761 | /* | |
762 | * The registers we must save are all those not preserved across | |
763 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
764 | * In addition, we must save the PC, and PUSH_FP_REGNUM. | |
765 | * (Ideally, we should also save MDLO/-HI and FP Control/Status reg.) | |
766 | * | |
767 | * Dummy frame layout: | |
768 | * (high memory) | |
769 | * Saved PC | |
770 | * Saved MMHI, MMLO, FPC_CSR | |
771 | * Saved R31 | |
772 | * Saved R28 | |
773 | * ... | |
774 | * Saved R1 | |
775 | * Saved D18 (i.e. F19, F18) | |
776 | * ... | |
777 | * Saved D0 (i.e. F1, F0) | |
c2a0f1cb | 778 | * CALL_DUMMY (subroutine stub; see tm-mips.h) |
bd5635a1 RP |
779 | * Parameter build area (not yet implemented) |
780 | * (low memory) | |
781 | */ | |
782 | PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; | |
c2a0f1cb | 783 | PROC_FREG_MASK(proc_desc) = mips_fpu ? FLOAT_REG_SAVE_MASK : 0; |
bd5635a1 RP |
784 | PROC_REG_OFFSET(proc_desc) = /* offset of (Saved R31) from FP */ |
785 | -sizeof(long) - 4 * SPECIAL_REG_SAVE_COUNT; | |
786 | PROC_FREG_OFFSET(proc_desc) = /* offset of (Saved D18) from FP */ | |
787 | -sizeof(double) - 4 * (SPECIAL_REG_SAVE_COUNT + GEN_REG_SAVE_COUNT); | |
788 | /* save general registers */ | |
789 | save_address = sp + PROC_REG_OFFSET(proc_desc); | |
790 | for (ireg = 32; --ireg >= 0; ) | |
791 | if (PROC_REG_MASK(proc_desc) & (1 << ireg)) | |
792 | { | |
3fed1c4a JK |
793 | read_register_gen (ireg, buffer); |
794 | ||
795 | /* Need to fix the save_address decrement below, and also make sure | |
796 | that we don't run into problems with the size of the dummy frame | |
797 | or any of the offsets within it. */ | |
798 | if (REGISTER_RAW_SIZE (ireg) > 4) | |
799 | error ("Cannot call functions on mips64"); | |
800 | ||
5efd597b | 801 | write_memory (save_address, buffer, REGISTER_RAW_SIZE (ireg)); |
bd5635a1 RP |
802 | save_address -= 4; |
803 | } | |
0b0d6c3f PS |
804 | /* save floating-points registers starting with high order word */ |
805 | save_address = sp + PROC_FREG_OFFSET(proc_desc) + 4; | |
bd5635a1 RP |
806 | for (ireg = 32; --ireg >= 0; ) |
807 | if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) | |
808 | { | |
3fed1c4a JK |
809 | read_register_gen (ireg + FP0_REGNUM, buffer); |
810 | ||
811 | if (REGISTER_RAW_SIZE (ireg + FP0_REGNUM) > 4) | |
812 | error ("Cannot call functions on mips64"); | |
813 | ||
814 | write_memory (save_address, buffer, | |
815 | REGISTER_RAW_SIZE (ireg + FP0_REGNUM)); | |
bd5635a1 RP |
816 | save_address -= 4; |
817 | } | |
818 | write_register (PUSH_FP_REGNUM, sp); | |
819 | PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; | |
820 | PROC_FRAME_OFFSET(proc_desc) = 0; | |
3fed1c4a | 821 | read_register_gen (PC_REGNUM, buffer); |
5efd597b | 822 | write_memory (sp - 4, buffer, REGISTER_RAW_SIZE (PC_REGNUM)); |
3fed1c4a | 823 | read_register_gen (HI_REGNUM, buffer); |
5efd597b | 824 | write_memory (sp - 8, buffer, REGISTER_RAW_SIZE (HI_REGNUM)); |
3fed1c4a | 825 | read_register_gen (LO_REGNUM, buffer); |
5efd597b | 826 | write_memory (sp - 12, buffer, REGISTER_RAW_SIZE (LO_REGNUM)); |
3fed1c4a JK |
827 | if (mips_fpu) |
828 | read_register_gen (FCRCS_REGNUM, buffer); | |
829 | else | |
830 | memset (buffer, 0, REGISTER_RAW_SIZE (FCRCS_REGNUM)); | |
5efd597b | 831 | write_memory (sp - 16, buffer, REGISTER_RAW_SIZE (FCRCS_REGNUM)); |
c2a0f1cb ILT |
832 | sp -= 4 * (GEN_REG_SAVE_COUNT |
833 | + (mips_fpu ? FLOAT_REG_SAVE_COUNT : 0) | |
834 | + SPECIAL_REG_SAVE_COUNT); | |
bd5635a1 RP |
835 | write_register (SP_REGNUM, sp); |
836 | PROC_LOW_ADDR(proc_desc) = sp - CALL_DUMMY_SIZE + CALL_DUMMY_START_OFFSET; | |
837 | PROC_HIGH_ADDR(proc_desc) = sp; | |
838 | SET_PROC_DESC_IS_DUMMY(proc_desc); | |
839 | PROC_PC_REG(proc_desc) = RA_REGNUM; | |
840 | } | |
841 | ||
842 | void | |
843 | mips_pop_frame() | |
dac4929a SG |
844 | { |
845 | register int regnum; | |
9f9f94aa SS |
846 | struct frame_info *frame = get_current_frame (); |
847 | CORE_ADDR new_sp = FRAME_FP (frame); | |
dac4929a | 848 | |
a70dc898 | 849 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
dac4929a SG |
850 | |
851 | write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); | |
70126bf9 KH |
852 | if (frame->saved_regs == NULL) |
853 | mips_find_saved_regs (frame); | |
dac4929a SG |
854 | if (proc_desc) |
855 | { | |
856 | for (regnum = 32; --regnum >= 0; ) | |
857 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) | |
858 | write_register (regnum, | |
859 | read_memory_integer (frame->saved_regs->regs[regnum], | |
860 | 4)); | |
861 | for (regnum = 32; --regnum >= 0; ) | |
862 | if (PROC_FREG_MASK(proc_desc) & (1 << regnum)) | |
863 | write_register (regnum + FP0_REGNUM, | |
864 | read_memory_integer (frame->saved_regs->regs[regnum + FP0_REGNUM], 4)); | |
865 | } | |
866 | write_register (SP_REGNUM, new_sp); | |
867 | flush_cached_frames (); | |
dac4929a | 868 | |
199b2450 | 869 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
bd5635a1 | 870 | { |
dac4929a SG |
871 | struct linked_proc_info *pi_ptr, *prev_ptr; |
872 | ||
873 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
874 | pi_ptr != NULL; | |
875 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
876 | { | |
877 | if (&pi_ptr->info == proc_desc) | |
878 | break; | |
879 | } | |
880 | ||
881 | if (pi_ptr == NULL) | |
882 | error ("Can't locate dummy extra frame info\n"); | |
883 | ||
884 | if (prev_ptr != NULL) | |
885 | prev_ptr->next = pi_ptr->next; | |
886 | else | |
887 | linked_proc_desc_table = pi_ptr->next; | |
888 | ||
889 | free (pi_ptr); | |
890 | ||
bd5635a1 RP |
891 | write_register (HI_REGNUM, read_memory_integer(new_sp - 8, 4)); |
892 | write_register (LO_REGNUM, read_memory_integer(new_sp - 12, 4)); | |
c2a0f1cb ILT |
893 | if (mips_fpu) |
894 | write_register (FCRCS_REGNUM, read_memory_integer(new_sp - 16, 4)); | |
bd5635a1 | 895 | } |
bd5635a1 RP |
896 | } |
897 | ||
0f552c5f | 898 | static void |
a70dc898 | 899 | mips_print_register (regnum, all) |
bd5635a1 RP |
900 | int regnum, all; |
901 | { | |
48be4c35 | 902 | unsigned char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
3fed1c4a JK |
903 | struct type *our_type = |
904 | init_type (TYPE_CODE_INT, | |
905 | /* We will fill in the length for each register. */ | |
906 | 0, | |
907 | TYPE_FLAG_UNSIGNED, | |
908 | NULL, | |
909 | NULL); | |
bd5635a1 | 910 | |
48be4c35 JK |
911 | /* Get the data in raw format. */ |
912 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
913 | { | |
914 | printf_filtered ("%s: [Invalid]", reg_names[regnum]); | |
915 | return; | |
916 | } | |
917 | ||
918 | /* If an even floating pointer register, also print as double. */ | |
919 | if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+32 | |
920 | && !((regnum-FP0_REGNUM) & 1)) { | |
921 | char dbuffer[MAX_REGISTER_RAW_SIZE]; | |
922 | ||
923 | read_relative_register_raw_bytes (regnum, dbuffer); | |
924 | read_relative_register_raw_bytes (regnum+1, dbuffer+4); | |
ac8cf67d | 925 | #ifdef REGISTER_CONVERT_TO_TYPE |
48be4c35 | 926 | REGISTER_CONVERT_TO_TYPE(regnum, builtin_type_double, dbuffer); |
ac8cf67d | 927 | #endif |
48be4c35 JK |
928 | printf_filtered ("(d%d: ", regnum-FP0_REGNUM); |
929 | val_print (builtin_type_double, dbuffer, 0, | |
199b2450 | 930 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
48be4c35 JK |
931 | printf_filtered ("); "); |
932 | } | |
199b2450 | 933 | fputs_filtered (reg_names[regnum], gdb_stdout); |
48be4c35 JK |
934 | |
935 | /* The problem with printing numeric register names (r26, etc.) is that | |
936 | the user can't use them on input. Probably the best solution is to | |
937 | fix it so that either the numeric or the funky (a2, etc.) names | |
938 | are accepted on input. */ | |
939 | if (regnum < 32) | |
940 | printf_filtered ("(r%d): ", regnum); | |
941 | else | |
942 | printf_filtered (": "); | |
bd5635a1 | 943 | |
48be4c35 | 944 | /* If virtual format is floating, print it that way. */ |
ac57e5ad | 945 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
48be4c35 | 946 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, |
199b2450 | 947 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
48be4c35 JK |
948 | /* Else print as integer in hex. */ |
949 | else | |
ac57e5ad SS |
950 | print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), |
951 | 'x', 0, gdb_stdout); | |
bd5635a1 RP |
952 | } |
953 | ||
d8b3b00e | 954 | /* Replacement for generic do_registers_info. */ |
9f9f94aa | 955 | |
0f552c5f | 956 | void |
361bf6ee | 957 | mips_do_registers_info (regnum, fpregs) |
bd5635a1 | 958 | int regnum; |
361bf6ee | 959 | int fpregs; |
bd5635a1 | 960 | { |
9f9f94aa SS |
961 | if (regnum != -1) |
962 | { | |
963 | if (*(reg_names[regnum]) == '\0') | |
964 | error ("Not a valid register for the current processor type"); | |
965 | ||
bd5635a1 RP |
966 | mips_print_register (regnum, 0); |
967 | printf_filtered ("\n"); | |
9f9f94aa SS |
968 | } |
969 | else | |
970 | { | |
971 | int did_newline; | |
972 | ||
973 | for (regnum = 0; regnum < NUM_REGS; ) | |
974 | { | |
975 | if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM) | |
976 | || *(reg_names[regnum]) == '\0') | |
977 | { | |
978 | regnum++; | |
979 | continue; | |
980 | } | |
bd5635a1 RP |
981 | mips_print_register (regnum, 1); |
982 | regnum++; | |
9f9f94aa SS |
983 | printf_filtered ("; "); |
984 | did_newline = 0; | |
985 | if ((regnum & 3) == 0) | |
986 | { | |
987 | printf_filtered ("\n"); | |
988 | did_newline = 1; | |
989 | } | |
990 | } | |
991 | if (!did_newline) | |
992 | printf_filtered ("\n"); | |
993 | } | |
bd5635a1 | 994 | } |
9f9f94aa | 995 | |
bd5635a1 RP |
996 | /* Return number of args passed to a frame. described by FIP. |
997 | Can return -1, meaning no way to tell. */ | |
998 | ||
0f552c5f | 999 | int |
9f9f94aa SS |
1000 | mips_frame_num_args (frame) |
1001 | struct frame_info *frame; | |
bd5635a1 | 1002 | { |
9f9f94aa SS |
1003 | #if 0 /* FIXME Use or lose this! */ |
1004 | struct chain_info_t *p; | |
bd5635a1 | 1005 | |
9f9f94aa SS |
1006 | p = mips_find_cached_frame (FRAME_FP (frame)); |
1007 | if (p->valid) | |
1008 | return p->the_info.numargs; | |
bd5635a1 | 1009 | #endif |
9f9f94aa | 1010 | return -1; |
bd5635a1 | 1011 | } |
407a8389 | 1012 | \f |
427fec5d | 1013 | /* Is this a branch with a delay slot? */ |
9f9f94aa | 1014 | |
b5aff268 JK |
1015 | static int is_delayed PARAMS ((unsigned long)); |
1016 | ||
ee5fb959 JK |
1017 | static int |
1018 | is_delayed (insn) | |
1019 | unsigned long insn; | |
1020 | { | |
1021 | int i; | |
1022 | for (i = 0; i < NUMOPCODES; ++i) | |
1023 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
1024 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
1025 | break; | |
427fec5d JK |
1026 | return (i < NUMOPCODES |
1027 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
1028 | | INSN_COND_BRANCH_DELAY | |
1029 | | INSN_COND_BRANCH_LIKELY))); | |
ee5fb959 | 1030 | } |
b5aff268 JK |
1031 | |
1032 | int | |
1033 | mips_step_skips_delay (pc) | |
1034 | CORE_ADDR pc; | |
1035 | { | |
1036 | char buf[4]; | |
1037 | ||
1038 | if (target_read_memory (pc, buf, 4) != 0) | |
1039 | /* If error reading memory, guess that it is not a delayed branch. */ | |
1040 | return 0; | |
1041 | return is_delayed (extract_unsigned_integer (buf, 4)); | |
1042 | } | |
ee5fb959 JK |
1043 | |
1044 | /* To skip prologues, I use this predicate. Returns either PC itself | |
1045 | if the code at PC does not look like a function prologue; otherwise | |
1046 | returns an address that (if we're lucky) follows the prologue. If | |
1047 | LENIENT, then we must skip everything which is involved in setting | |
1048 | up the frame (it's OK to skip more, just so long as we don't skip | |
1049 | anything which might clobber the registers which are being saved. | |
1050 | We must skip more in the case where part of the prologue is in the | |
1051 | delay slot of a non-prologue instruction). */ | |
bd5635a1 | 1052 | |
be772100 | 1053 | CORE_ADDR |
ee5fb959 | 1054 | mips_skip_prologue (pc, lenient) |
bd5635a1 | 1055 | CORE_ADDR pc; |
ee5fb959 | 1056 | int lenient; |
bd5635a1 | 1057 | { |
bd5635a1 | 1058 | unsigned long inst; |
d747e0af | 1059 | int offset; |
0b0d6c3f | 1060 | int seen_sp_adjust = 0; |
ac57e5ad | 1061 | int load_immediate_bytes = 0; |
bd5635a1 | 1062 | |
e157305c PS |
1063 | /* Skip the typical prologue instructions. These are the stack adjustment |
1064 | instruction and the instructions that save registers on the stack | |
1065 | or in the gcc frame. */ | |
ee5fb959 JK |
1066 | for (offset = 0; offset < 100; offset += 4) |
1067 | { | |
1068 | char buf[4]; | |
1069 | int status; | |
1070 | ||
1071 | status = read_memory_nobpt (pc + offset, buf, 4); | |
1072 | if (status) | |
1073 | memory_error (status, pc + offset); | |
1074 | inst = extract_unsigned_integer (buf, 4); | |
1075 | ||
002a422b | 1076 | #if 0 |
ee5fb959 JK |
1077 | if (lenient && is_delayed (inst)) |
1078 | continue; | |
002a422b | 1079 | #endif |
ee5fb959 | 1080 | |
e157305c | 1081 | if ((inst & 0xffff0000) == 0x27bd0000) /* addiu $sp,$sp,offset */ |
0b0d6c3f | 1082 | seen_sp_adjust = 1; |
ac57e5ad SS |
1083 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
1084 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
1085 | seen_sp_adjust = 1; | |
e157305c PS |
1086 | else if ((inst & 0xFFE00000) == 0xAFA00000 && (inst & 0x001F0000)) |
1087 | continue; /* sw reg,n($sp) */ | |
1088 | /* reg != $zero */ | |
1089 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
1090 | continue; | |
1091 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
1092 | /* sx reg,n($s8) */ | |
1093 | continue; /* reg != $zero */ | |
1094 | else if (inst == 0x03A0F021) /* move $s8,$sp */ | |
0b0d6c3f | 1095 | continue; |
1b71de8e PS |
1096 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
1097 | continue; | |
e03c0cc6 ILT |
1098 | else if ((inst & 0xffff0000) == 0x3c1c0000) /* lui $gp,n */ |
1099 | continue; | |
1100 | else if ((inst & 0xffff0000) == 0x279c0000) /* addiu $gp,$gp,n */ | |
1101 | continue; | |
1102 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1103 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
1104 | continue; | |
ac57e5ad SS |
1105 | /* The following instructions load $at or $t0 with an immediate |
1106 | value in preparation for a stack adjustment via | |
1107 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
1108 | a local variable, so we accept them only before a stack adjustment | |
1109 | instruction was seen. */ | |
1110 | else if (!seen_sp_adjust) | |
1111 | { | |
1112 | if ((inst & 0xffff0000) == 0x3c010000 || /* lui $at,n */ | |
1113 | (inst & 0xffff0000) == 0x3c080000) /* lui $t0,n */ | |
1114 | { | |
1115 | load_immediate_bytes += 4; | |
1116 | continue; | |
1117 | } | |
1118 | else if ((inst & 0xffff0000) == 0x34210000 || /* ori $at,$at,n */ | |
1119 | (inst & 0xffff0000) == 0x35080000 || /* ori $t0,$t0,n */ | |
1120 | (inst & 0xffff0000) == 0x34010000 || /* ori $at,$zero,n */ | |
1121 | (inst & 0xffff0000) == 0x34080000) /* ori $t0,$zero,n */ | |
1122 | { | |
1123 | load_immediate_bytes += 4; | |
1124 | continue; | |
1125 | } | |
1126 | else | |
1127 | break; | |
1128 | } | |
0b0d6c3f | 1129 | else |
ac57e5ad | 1130 | break; |
d747e0af | 1131 | } |
e157305c | 1132 | |
ac57e5ad SS |
1133 | /* In a frameless function, we might have incorrectly |
1134 | skipped some load immediate instructions. Undo the skipping | |
1135 | if the load immediate was not followed by a stack adjustment. */ | |
1136 | if (load_immediate_bytes && !seen_sp_adjust) | |
1137 | offset -= load_immediate_bytes; | |
1138 | return pc + offset; | |
bd5635a1 | 1139 | } |
c2a0f1cb | 1140 | |
002a422b JK |
1141 | #if 0 |
1142 | /* The lenient prologue stuff should be superceded by the code in | |
1143 | init_extra_frame_info which looks to see whether the stores mentioned | |
1144 | in the proc_desc have actually taken place. */ | |
1145 | ||
ee5fb959 JK |
1146 | /* Is address PC in the prologue (loosely defined) for function at |
1147 | STARTADDR? */ | |
1148 | ||
1149 | static int | |
1150 | mips_in_lenient_prologue (startaddr, pc) | |
1151 | CORE_ADDR startaddr; | |
1152 | CORE_ADDR pc; | |
1153 | { | |
1154 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
1155 | return pc >= startaddr && pc < end_prologue; | |
1156 | } | |
002a422b | 1157 | #endif |
ee5fb959 | 1158 | |
ac8cf67d PS |
1159 | /* Given a return value in `regbuf' with a type `valtype', |
1160 | extract and copy its value into `valbuf'. */ | |
1161 | void | |
1162 | mips_extract_return_value (valtype, regbuf, valbuf) | |
1163 | struct type *valtype; | |
1164 | char regbuf[REGISTER_BYTES]; | |
1165 | char *valbuf; | |
1166 | { | |
1167 | int regnum; | |
1168 | ||
1169 | regnum = TYPE_CODE (valtype) == TYPE_CODE_FLT && mips_fpu ? FP0_REGNUM : 2; | |
1170 | ||
1171 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum), TYPE_LENGTH (valtype)); | |
1172 | #ifdef REGISTER_CONVERT_TO_TYPE | |
1173 | REGISTER_CONVERT_TO_TYPE(regnum, valtype, valbuf); | |
1174 | #endif | |
1175 | } | |
1176 | ||
1177 | /* Given a return value in `regbuf' with a type `valtype', | |
1178 | write it's value into the appropriate register. */ | |
1179 | void | |
1180 | mips_store_return_value (valtype, valbuf) | |
1181 | struct type *valtype; | |
1182 | char *valbuf; | |
1183 | { | |
1184 | int regnum; | |
1185 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
1186 | ||
1187 | regnum = TYPE_CODE (valtype) == TYPE_CODE_FLT && mips_fpu ? FP0_REGNUM : 2; | |
1188 | memcpy(raw_buffer, valbuf, TYPE_LENGTH (valtype)); | |
1189 | ||
1190 | #ifdef REGISTER_CONVERT_FROM_TYPE | |
1191 | REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); | |
1192 | #endif | |
1193 | ||
1194 | write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, TYPE_LENGTH (valtype)); | |
1195 | } | |
1196 | ||
e03c0cc6 ILT |
1197 | /* These exist in mdebugread.c. */ |
1198 | extern CORE_ADDR sigtramp_address, sigtramp_end; | |
1199 | extern void fixup_sigtramp PARAMS ((void)); | |
1200 | ||
1201 | /* Exported procedure: Is PC in the signal trampoline code */ | |
1202 | ||
1203 | int | |
1204 | in_sigtramp (pc, ignore) | |
1205 | CORE_ADDR pc; | |
1206 | char *ignore; /* function name */ | |
1207 | { | |
1208 | if (sigtramp_address == 0) | |
1209 | fixup_sigtramp (); | |
1210 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
1211 | } | |
1212 | ||
9f9f94aa SS |
1213 | /* Command to set the processor type. */ |
1214 | ||
1215 | void | |
1216 | mips_set_processor_type_command (args, from_tty) | |
1217 | char *args; | |
1218 | int from_tty; | |
1219 | { | |
1220 | int i; | |
1221 | ||
1222 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
1223 | { | |
1224 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
1225 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
1226 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
1227 | ||
1228 | /* Restore the value. */ | |
1229 | tmp_mips_processor_type = strsave (mips_processor_type); | |
1230 | ||
1231 | return; | |
1232 | } | |
1233 | ||
1234 | if (!mips_set_processor_type (tmp_mips_processor_type)) | |
1235 | { | |
1236 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
1237 | /* Restore its value. */ | |
1238 | tmp_mips_processor_type = strsave (mips_processor_type); | |
1239 | } | |
1240 | } | |
1241 | ||
1242 | static void | |
1243 | mips_show_processor_type_command (args, from_tty) | |
1244 | char *args; | |
1245 | int from_tty; | |
1246 | { | |
1247 | } | |
1248 | ||
1249 | /* Modify the actual processor type. */ | |
1250 | ||
1251 | int | |
1252 | mips_set_processor_type (str) | |
1253 | char *str; | |
1254 | { | |
1255 | int i, j; | |
1256 | ||
1257 | if (str == NULL) | |
1258 | return; | |
1259 | ||
1260 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
1261 | { | |
1262 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
1263 | { | |
1264 | mips_processor_type = str; | |
1265 | ||
1266 | for (j = 0; j < NUM_REGS; ++j) | |
1267 | reg_names[j] = mips_processor_type_table[i].regnames[j]; | |
1268 | ||
1269 | return 1; | |
1270 | ||
1271 | /* FIXME tweak fpu flag too */ | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | /* Attempt to identify the particular processor model by reading the | |
1279 | processor id. */ | |
1280 | ||
1281 | char * | |
1282 | mips_read_processor_type () | |
1283 | { | |
1284 | int prid; | |
1285 | ||
1286 | prid = read_register (PRID_REGNUM); | |
1287 | ||
1288 | if (prid & ~0xf == 0x700) | |
1289 | return savestring ("r3041", strlen("r3041")); | |
1290 | ||
1291 | return NULL; | |
1292 | } | |
427fec5d JK |
1293 | |
1294 | /* Just like reinit_frame_cache, but with the right arguments to be | |
1295 | callable as an sfunc. */ | |
9f9f94aa | 1296 | |
427fec5d JK |
1297 | static void |
1298 | reinit_frame_cache_sfunc (args, from_tty, c) | |
1299 | char *args; | |
1300 | int from_tty; | |
1301 | struct cmd_list_element *c; | |
1302 | { | |
1303 | reinit_frame_cache (); | |
1304 | } | |
c2a0f1cb ILT |
1305 | |
1306 | void | |
1307 | _initialize_mips_tdep () | |
1308 | { | |
427fec5d JK |
1309 | struct cmd_list_element *c; |
1310 | ||
1311 | /* Let the user turn off floating point and set the fence post for | |
1312 | heuristic_proc_start. */ | |
1313 | ||
c2a0f1cb | 1314 | add_show_from_set |
a8172eea | 1315 | (add_set_cmd ("mipsfpu", class_support, var_boolean, |
c2a0f1cb ILT |
1316 | (char *) &mips_fpu, |
1317 | "Set use of floating point coprocessor.\n\ | |
1318 | Turn off to avoid using floating point instructions when calling functions\n\ | |
1319 | or dealing with return values.", &setlist), | |
1320 | &showlist); | |
3127785a | 1321 | |
9f9f94aa SS |
1322 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
1323 | (char *) &tmp_mips_processor_type, | |
1324 | "Set the type of MIPS processor in use.\n\ | |
1325 | Set this to be able to access processor-type-specific registers.\n\ | |
1326 | ", | |
1327 | &setlist); | |
1328 | c->function.cfunc = mips_set_processor_type_command; | |
1329 | c = add_show_from_set (c, &showlist); | |
1330 | c->function.cfunc = mips_show_processor_type_command; | |
1331 | ||
1332 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
1333 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
1334 | ||
bdef72d2 JK |
1335 | /* We really would like to have both "0" and "unlimited" work, but |
1336 | command.c doesn't deal with that. So make it a var_zinteger | |
1337 | because the user can always use "999999" or some such for unlimited. */ | |
1338 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
427fec5d JK |
1339 | (char *) &heuristic_fence_post, |
1340 | "\ | |
23d35572 JK |
1341 | Set the distance searched for the start of a function.\n\ |
1342 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
1343 | program for the start of a function. This command sets the distance of the\n\ | |
1344 | search. The only need to set it is when debugging a stripped executable.", | |
427fec5d JK |
1345 | &setlist); |
1346 | /* We need to throw away the frame cache when we set this, since it | |
1347 | might change our ability to get backtraces. */ | |
1348 | c->function.sfunc = reinit_frame_cache_sfunc; | |
1349 | add_show_from_set (c, &showlist); | |
c2a0f1cb | 1350 | } |