Commit | Line | Data |
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342ee437 MS |
1 | /* Target-dependent code for the Matsushita MN10300 for GDB, the GNU debugger. |
2 | ||
61baf725 | 3 | Copyright (C) 1996-2017 Free Software Foundation, Inc. |
342ee437 MS |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
342ee437 MS |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
342ee437 | 19 | |
342ee437 MS |
20 | #include "defs.h" |
21 | #include "arch-utils.h" | |
22 | #include "dis-asm.h" | |
23 | #include "gdbtypes.h" | |
24 | #include "regcache.h" | |
025bb325 | 25 | #include "gdbcore.h" /* For write_memory_unsigned_integer. */ |
342ee437 | 26 | #include "value.h" |
342ee437 MS |
27 | #include "frame.h" |
28 | #include "frame-unwind.h" | |
29 | #include "frame-base.h" | |
342ee437 MS |
30 | #include "symtab.h" |
31 | #include "dwarf2-frame.h" | |
697e3bc9 | 32 | #include "osabi.h" |
ee3a2f01 | 33 | #include "infcall.h" |
6c02c64c | 34 | #include "prologue-value.h" |
effa26a9 | 35 | #include "target.h" |
342ee437 MS |
36 | |
37 | #include "mn10300-tdep.h" | |
38 | ||
6c02c64c KB |
39 | |
40 | /* The am33-2 has 64 registers. */ | |
41 | #define MN10300_MAX_NUM_REGS 64 | |
42 | ||
b8b6e72f AH |
43 | /* Big enough to hold the size of the largest register in bytes. */ |
44 | #define MN10300_MAX_REGISTER_SIZE 64 | |
45 | ||
6c02c64c KB |
46 | /* This structure holds the results of a prologue analysis. */ |
47 | struct mn10300_prologue | |
48 | { | |
d80b854b UW |
49 | /* The architecture for which we generated this prologue info. */ |
50 | struct gdbarch *gdbarch; | |
51 | ||
6c02c64c KB |
52 | /* The offset from the frame base to the stack pointer --- always |
53 | zero or negative. | |
54 | ||
55 | Calling this a "size" is a bit misleading, but given that the | |
56 | stack grows downwards, using offsets for everything keeps one | |
57 | from going completely sign-crazy: you never change anything's | |
58 | sign for an ADD instruction; always change the second operand's | |
59 | sign for a SUB instruction; and everything takes care of | |
60 | itself. */ | |
61 | int frame_size; | |
62 | ||
63 | /* Non-zero if this function has initialized the frame pointer from | |
64 | the stack pointer, zero otherwise. */ | |
65 | int has_frame_ptr; | |
66 | ||
67 | /* If has_frame_ptr is non-zero, this is the offset from the frame | |
68 | base to where the frame pointer points. This is always zero or | |
69 | negative. */ | |
70 | int frame_ptr_offset; | |
71 | ||
72 | /* The address of the first instruction at which the frame has been | |
73 | set up and the arguments are where the debug info says they are | |
74 | --- as best as we can tell. */ | |
75 | CORE_ADDR prologue_end; | |
76 | ||
77 | /* reg_offset[R] is the offset from the CFA at which register R is | |
78 | saved, or 1 if register R has not been saved. (Real values are | |
79 | always zero or negative.) */ | |
80 | int reg_offset[MN10300_MAX_NUM_REGS]; | |
81 | }; | |
82 | ||
342ee437 MS |
83 | |
84 | /* Compute the alignment required by a type. */ | |
85 | ||
86 | static int | |
87 | mn10300_type_align (struct type *type) | |
88 | { | |
89 | int i, align = 1; | |
90 | ||
91 | switch (TYPE_CODE (type)) | |
92 | { | |
93 | case TYPE_CODE_INT: | |
94 | case TYPE_CODE_ENUM: | |
95 | case TYPE_CODE_SET: | |
96 | case TYPE_CODE_RANGE: | |
97 | case TYPE_CODE_CHAR: | |
98 | case TYPE_CODE_BOOL: | |
99 | case TYPE_CODE_FLT: | |
100 | case TYPE_CODE_PTR: | |
101 | case TYPE_CODE_REF: | |
aa006118 | 102 | case TYPE_CODE_RVALUE_REF: |
342ee437 MS |
103 | return TYPE_LENGTH (type); |
104 | ||
105 | case TYPE_CODE_COMPLEX: | |
106 | return TYPE_LENGTH (type) / 2; | |
107 | ||
108 | case TYPE_CODE_STRUCT: | |
109 | case TYPE_CODE_UNION: | |
110 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
111 | { | |
112 | int falign = mn10300_type_align (TYPE_FIELD_TYPE (type, i)); | |
113 | while (align < falign) | |
114 | align <<= 1; | |
115 | } | |
116 | return align; | |
117 | ||
118 | case TYPE_CODE_ARRAY: | |
119 | /* HACK! Structures containing arrays, even small ones, are not | |
120 | elligible for returning in registers. */ | |
121 | return 256; | |
122 | ||
123 | case TYPE_CODE_TYPEDEF: | |
124 | return mn10300_type_align (check_typedef (type)); | |
125 | ||
126 | default: | |
127 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
128 | } | |
129 | } | |
130 | ||
342ee437 | 131 | /* Should call_function allocate stack space for a struct return? */ |
342ee437 | 132 | static int |
99fe5f9d | 133 | mn10300_use_struct_convention (struct type *type) |
342ee437 MS |
134 | { |
135 | /* Structures bigger than a pair of words can't be returned in | |
136 | registers. */ | |
137 | if (TYPE_LENGTH (type) > 8) | |
138 | return 1; | |
139 | ||
140 | switch (TYPE_CODE (type)) | |
141 | { | |
142 | case TYPE_CODE_STRUCT: | |
143 | case TYPE_CODE_UNION: | |
144 | /* Structures with a single field are handled as the field | |
145 | itself. */ | |
146 | if (TYPE_NFIELDS (type) == 1) | |
99fe5f9d | 147 | return mn10300_use_struct_convention (TYPE_FIELD_TYPE (type, 0)); |
342ee437 MS |
148 | |
149 | /* Structures with word or double-word size are passed in memory, as | |
150 | long as they require at least word alignment. */ | |
151 | if (mn10300_type_align (type) >= 4) | |
152 | return 0; | |
153 | ||
154 | return 1; | |
155 | ||
156 | /* Arrays are addressable, so they're never returned in | |
157 | registers. This condition can only hold when the array is | |
158 | the only field of a struct or union. */ | |
159 | case TYPE_CODE_ARRAY: | |
160 | return 1; | |
161 | ||
162 | case TYPE_CODE_TYPEDEF: | |
99fe5f9d | 163 | return mn10300_use_struct_convention (check_typedef (type)); |
342ee437 MS |
164 | |
165 | default: | |
166 | return 0; | |
167 | } | |
168 | } | |
169 | ||
342ee437 | 170 | static void |
99fe5f9d | 171 | mn10300_store_return_value (struct gdbarch *gdbarch, struct type *type, |
948f8e3d | 172 | struct regcache *regcache, const gdb_byte *valbuf) |
342ee437 | 173 | { |
342ee437 MS |
174 | int len = TYPE_LENGTH (type); |
175 | int reg, regsz; | |
176 | ||
177 | if (TYPE_CODE (type) == TYPE_CODE_PTR) | |
178 | reg = 4; | |
179 | else | |
180 | reg = 0; | |
181 | ||
182 | regsz = register_size (gdbarch, reg); | |
183 | ||
184 | if (len <= regsz) | |
185 | regcache_raw_write_part (regcache, reg, 0, len, valbuf); | |
186 | else if (len <= 2 * regsz) | |
187 | { | |
188 | regcache_raw_write (regcache, reg, valbuf); | |
189 | gdb_assert (regsz == register_size (gdbarch, reg + 1)); | |
190 | regcache_raw_write_part (regcache, reg+1, 0, | |
948f8e3d | 191 | len - regsz, valbuf + regsz); |
342ee437 MS |
192 | } |
193 | else | |
194 | internal_error (__FILE__, __LINE__, | |
195 | _("Cannot store return value %d bytes long."), len); | |
196 | } | |
197 | ||
342ee437 | 198 | static void |
99fe5f9d | 199 | mn10300_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
342ee437 MS |
200 | struct regcache *regcache, void *valbuf) |
201 | { | |
b8b6e72f | 202 | gdb_byte buf[MN10300_MAX_REGISTER_SIZE]; |
342ee437 MS |
203 | int len = TYPE_LENGTH (type); |
204 | int reg, regsz; | |
205 | ||
206 | if (TYPE_CODE (type) == TYPE_CODE_PTR) | |
207 | reg = 4; | |
208 | else | |
209 | reg = 0; | |
210 | ||
211 | regsz = register_size (gdbarch, reg); | |
b8b6e72f | 212 | gdb_assert (regsz <= MN10300_MAX_REGISTER_SIZE); |
342ee437 MS |
213 | if (len <= regsz) |
214 | { | |
215 | regcache_raw_read (regcache, reg, buf); | |
216 | memcpy (valbuf, buf, len); | |
217 | } | |
218 | else if (len <= 2 * regsz) | |
219 | { | |
220 | regcache_raw_read (regcache, reg, buf); | |
221 | memcpy (valbuf, buf, regsz); | |
222 | gdb_assert (regsz == register_size (gdbarch, reg + 1)); | |
223 | regcache_raw_read (regcache, reg + 1, buf); | |
224 | memcpy ((char *) valbuf + regsz, buf, len - regsz); | |
225 | } | |
226 | else | |
227 | internal_error (__FILE__, __LINE__, | |
228 | _("Cannot extract return value %d bytes long."), len); | |
229 | } | |
230 | ||
99fe5f9d KB |
231 | /* Determine, for architecture GDBARCH, how a return value of TYPE |
232 | should be returned. If it is supposed to be returned in registers, | |
233 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
234 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
235 | from WRITEBUF into REGCACHE. */ | |
236 | ||
237 | static enum return_value_convention | |
6a3a010b | 238 | mn10300_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
239 | struct type *type, struct regcache *regcache, |
240 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
99fe5f9d KB |
241 | { |
242 | if (mn10300_use_struct_convention (type)) | |
243 | return RETURN_VALUE_STRUCT_CONVENTION; | |
244 | ||
245 | if (readbuf) | |
246 | mn10300_extract_return_value (gdbarch, type, regcache, readbuf); | |
247 | if (writebuf) | |
248 | mn10300_store_return_value (gdbarch, type, regcache, writebuf); | |
249 | ||
250 | return RETURN_VALUE_REGISTER_CONVENTION; | |
251 | } | |
252 | ||
a121b7c1 PA |
253 | static const char * |
254 | register_name (int reg, const char **regs, long sizeof_regs) | |
342ee437 MS |
255 | { |
256 | if (reg < 0 || reg >= sizeof_regs / sizeof (regs[0])) | |
257 | return NULL; | |
258 | else | |
259 | return regs[reg]; | |
260 | } | |
261 | ||
262 | static const char * | |
d93859e2 | 263 | mn10300_generic_register_name (struct gdbarch *gdbarch, int reg) |
342ee437 | 264 | { |
a121b7c1 | 265 | static const char *regs[] = |
342ee437 MS |
266 | { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", |
267 | "sp", "pc", "mdr", "psw", "lir", "lar", "", "", | |
268 | "", "", "", "", "", "", "", "", | |
269 | "", "", "", "", "", "", "", "fp" | |
270 | }; | |
271 | return register_name (reg, regs, sizeof regs); | |
272 | } | |
273 | ||
274 | ||
275 | static const char * | |
d93859e2 | 276 | am33_register_name (struct gdbarch *gdbarch, int reg) |
342ee437 | 277 | { |
a121b7c1 | 278 | static const char *regs[] = |
342ee437 MS |
279 | { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", |
280 | "sp", "pc", "mdr", "psw", "lir", "lar", "", | |
281 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
282 | "ssp", "msp", "usp", "mcrh", "mcrl", "mcvf", "", "", "" | |
283 | }; | |
284 | return register_name (reg, regs, sizeof regs); | |
285 | } | |
286 | ||
4640dd91 | 287 | static const char * |
d93859e2 | 288 | am33_2_register_name (struct gdbarch *gdbarch, int reg) |
4640dd91 | 289 | { |
a121b7c1 | 290 | static const char *regs[] = |
4640dd91 KB |
291 | { |
292 | "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", | |
293 | "sp", "pc", "mdr", "psw", "lir", "lar", "mdrq", "r0", | |
294 | "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ssp", | |
295 | "msp", "usp", "mcrh", "mcrl", "mcvf", "fpcr", "", "", | |
296 | "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", | |
297 | "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15", | |
298 | "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23", | |
299 | "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" | |
300 | }; | |
301 | return register_name (reg, regs, sizeof regs); | |
302 | } | |
342ee437 MS |
303 | |
304 | static struct type * | |
305 | mn10300_register_type (struct gdbarch *gdbarch, int reg) | |
306 | { | |
0dfff4cb | 307 | return builtin_type (gdbarch)->builtin_int; |
342ee437 MS |
308 | } |
309 | ||
310 | static CORE_ADDR | |
61a1198a | 311 | mn10300_read_pc (struct regcache *regcache) |
342ee437 | 312 | { |
61a1198a UW |
313 | ULONGEST val; |
314 | regcache_cooked_read_unsigned (regcache, E_PC_REGNUM, &val); | |
315 | return val; | |
342ee437 MS |
316 | } |
317 | ||
318 | static void | |
61a1198a | 319 | mn10300_write_pc (struct regcache *regcache, CORE_ADDR val) |
342ee437 | 320 | { |
61a1198a | 321 | regcache_cooked_write_unsigned (regcache, E_PC_REGNUM, val); |
342ee437 MS |
322 | } |
323 | ||
324 | /* The breakpoint instruction must be the same size as the smallest | |
325 | instruction in the instruction set. | |
326 | ||
327 | The Matsushita mn10x00 processors have single byte instructions | |
328 | so we need a single byte breakpoint. Matsushita hasn't defined | |
329 | one, so we defined it ourselves. */ | |
04180708 | 330 | constexpr gdb_byte mn10300_break_insn[] = {0xff}; |
342ee437 | 331 | |
04180708 | 332 | typedef BP_MANIPULATION (mn10300_break_insn) mn10300_breakpoint; |
342ee437 | 333 | |
6c02c64c KB |
334 | /* Model the semantics of pushing a register onto the stack. This |
335 | is a helper function for mn10300_analyze_prologue, below. */ | |
336 | static void | |
337 | push_reg (pv_t *regs, struct pv_area *stack, int regnum) | |
338 | { | |
339 | regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4); | |
340 | pv_area_store (stack, regs[E_SP_REGNUM], 4, regs[regnum]); | |
341 | } | |
342 | ||
343 | /* Translate an "r" register number extracted from an instruction encoding | |
344 | into a GDB register number. Adapted from a simulator function | |
345 | of the same name; see am33.igen. */ | |
346 | static int | |
347 | translate_rreg (int rreg) | |
348 | { | |
349 | /* The higher register numbers actually correspond to the | |
350 | basic machine's address and data registers. */ | |
351 | if (rreg > 7 && rreg < 12) | |
352 | return E_A0_REGNUM + rreg - 8; | |
353 | else if (rreg > 11 && rreg < 16) | |
354 | return E_D0_REGNUM + rreg - 12; | |
355 | else | |
356 | return E_E0_REGNUM + rreg; | |
357 | } | |
358 | ||
359 | /* Find saved registers in a 'struct pv_area'; we pass this to pv_area_scan. | |
9cacebf5 | 360 | |
6c02c64c KB |
361 | If VALUE is a saved register, ADDR says it was saved at a constant |
362 | offset from the frame base, and SIZE indicates that the whole | |
363 | register was saved, record its offset in RESULT_UNTYPED. */ | |
9cacebf5 | 364 | static void |
6c02c64c | 365 | check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value) |
9cacebf5 | 366 | { |
6c02c64c | 367 | struct mn10300_prologue *result = (struct mn10300_prologue *) result_untyped; |
9cacebf5 | 368 | |
6c02c64c KB |
369 | if (value.kind == pvk_register |
370 | && value.k == 0 | |
371 | && pv_is_register (addr, E_SP_REGNUM) | |
d80b854b | 372 | && size == register_size (result->gdbarch, value.reg)) |
6c02c64c KB |
373 | result->reg_offset[value.reg] = addr.k; |
374 | } | |
9cacebf5 | 375 | |
6c02c64c KB |
376 | /* Analyze the prologue to determine where registers are saved, |
377 | the end of the prologue, etc. The result of this analysis is | |
378 | returned in RESULT. See struct mn10300_prologue above for more | |
379 | information. */ | |
380 | static void | |
381 | mn10300_analyze_prologue (struct gdbarch *gdbarch, | |
382 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
383 | struct mn10300_prologue *result) | |
384 | { | |
e17a4113 | 385 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
22e048c9 | 386 | CORE_ADDR pc; |
6c02c64c KB |
387 | int rn; |
388 | pv_t regs[MN10300_MAX_NUM_REGS]; | |
389 | struct pv_area *stack; | |
390 | struct cleanup *back_to; | |
391 | CORE_ADDR after_last_frame_setup_insn = start_pc; | |
392 | int am33_mode = AM33_MODE (gdbarch); | |
393 | ||
394 | memset (result, 0, sizeof (*result)); | |
d80b854b | 395 | result->gdbarch = gdbarch; |
9cacebf5 | 396 | |
6c02c64c | 397 | for (rn = 0; rn < MN10300_MAX_NUM_REGS; rn++) |
4640dd91 | 398 | { |
6c02c64c KB |
399 | regs[rn] = pv_register (rn, 0); |
400 | result->reg_offset[rn] = 1; | |
4640dd91 | 401 | } |
55f960e1 | 402 | stack = make_pv_area (E_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
6c02c64c KB |
403 | back_to = make_cleanup_free_pv_area (stack); |
404 | ||
405 | /* The typical call instruction will have saved the return address on the | |
406 | stack. Space for the return address has already been preallocated in | |
407 | the caller's frame. It's possible, such as when using -mrelax with gcc | |
408 | that other registers were saved as well. If this happens, we really | |
409 | have no chance of deciphering the frame. DWARF info can save the day | |
410 | when this happens. */ | |
411 | pv_area_store (stack, regs[E_SP_REGNUM], 4, regs[E_PC_REGNUM]); | |
412 | ||
413 | pc = start_pc; | |
414 | while (pc < limit_pc) | |
4640dd91 | 415 | { |
6c02c64c KB |
416 | int status; |
417 | gdb_byte instr[2]; | |
4640dd91 | 418 | |
6c02c64c KB |
419 | /* Instructions can be as small as one byte; however, we usually |
420 | need at least two bytes to do the decoding, so fetch that many | |
421 | to begin with. */ | |
422 | status = target_read_memory (pc, instr, 2); | |
423 | if (status != 0) | |
424 | break; | |
4640dd91 | 425 | |
6c02c64c KB |
426 | /* movm [regs], sp */ |
427 | if (instr[0] == 0xcf) | |
4640dd91 | 428 | { |
6c02c64c KB |
429 | gdb_byte save_mask; |
430 | ||
431 | save_mask = instr[1]; | |
432 | ||
433 | if ((save_mask & movm_exreg0_bit) && am33_mode) | |
434 | { | |
435 | push_reg (regs, stack, E_E2_REGNUM); | |
436 | push_reg (regs, stack, E_E3_REGNUM); | |
437 | } | |
438 | if ((save_mask & movm_exreg1_bit) && am33_mode) | |
4640dd91 | 439 | { |
6c02c64c KB |
440 | push_reg (regs, stack, E_E4_REGNUM); |
441 | push_reg (regs, stack, E_E5_REGNUM); | |
442 | push_reg (regs, stack, E_E6_REGNUM); | |
443 | push_reg (regs, stack, E_E7_REGNUM); | |
4640dd91 | 444 | } |
6c02c64c KB |
445 | if ((save_mask & movm_exother_bit) && am33_mode) |
446 | { | |
447 | push_reg (regs, stack, E_E0_REGNUM); | |
448 | push_reg (regs, stack, E_E1_REGNUM); | |
449 | push_reg (regs, stack, E_MDRQ_REGNUM); | |
450 | push_reg (regs, stack, E_MCRH_REGNUM); | |
451 | push_reg (regs, stack, E_MCRL_REGNUM); | |
452 | push_reg (regs, stack, E_MCVF_REGNUM); | |
453 | } | |
454 | if (save_mask & movm_d2_bit) | |
455 | push_reg (regs, stack, E_D2_REGNUM); | |
456 | if (save_mask & movm_d3_bit) | |
457 | push_reg (regs, stack, E_D3_REGNUM); | |
458 | if (save_mask & movm_a2_bit) | |
459 | push_reg (regs, stack, E_A2_REGNUM); | |
460 | if (save_mask & movm_a3_bit) | |
461 | push_reg (regs, stack, E_A3_REGNUM); | |
462 | if (save_mask & movm_other_bit) | |
463 | { | |
464 | push_reg (regs, stack, E_D0_REGNUM); | |
465 | push_reg (regs, stack, E_D1_REGNUM); | |
466 | push_reg (regs, stack, E_A0_REGNUM); | |
467 | push_reg (regs, stack, E_A1_REGNUM); | |
468 | push_reg (regs, stack, E_MDR_REGNUM); | |
469 | push_reg (regs, stack, E_LIR_REGNUM); | |
470 | push_reg (regs, stack, E_LAR_REGNUM); | |
471 | /* The `other' bit leaves a blank area of four bytes at | |
472 | the beginning of its block of saved registers, making | |
473 | it 32 bytes long in total. */ | |
474 | regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4); | |
475 | } | |
476 | ||
477 | pc += 2; | |
478 | after_last_frame_setup_insn = pc; | |
4640dd91 | 479 | } |
6c02c64c KB |
480 | /* mov sp, aN */ |
481 | else if ((instr[0] & 0xfc) == 0x3c) | |
482 | { | |
483 | int aN = instr[0] & 0x03; | |
4640dd91 | 484 | |
6c02c64c | 485 | regs[E_A0_REGNUM + aN] = regs[E_SP_REGNUM]; |
4640dd91 | 486 | |
6c02c64c KB |
487 | pc += 1; |
488 | if (aN == 3) | |
489 | after_last_frame_setup_insn = pc; | |
490 | } | |
491 | /* mov aM, aN */ | |
492 | else if ((instr[0] & 0xf0) == 0x90 | |
493 | && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2)) | |
494 | { | |
495 | int aN = instr[0] & 0x03; | |
496 | int aM = (instr[0] & 0x0c) >> 2; | |
9cacebf5 | 497 | |
6c02c64c | 498 | regs[E_A0_REGNUM + aN] = regs[E_A0_REGNUM + aM]; |
9cacebf5 | 499 | |
6c02c64c KB |
500 | pc += 1; |
501 | } | |
502 | /* mov dM, dN */ | |
503 | else if ((instr[0] & 0xf0) == 0x80 | |
504 | && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2)) | |
505 | { | |
506 | int dN = instr[0] & 0x03; | |
507 | int dM = (instr[0] & 0x0c) >> 2; | |
9cacebf5 | 508 | |
6c02c64c | 509 | regs[E_D0_REGNUM + dN] = regs[E_D0_REGNUM + dM]; |
9cacebf5 | 510 | |
6c02c64c KB |
511 | pc += 1; |
512 | } | |
513 | /* mov aM, dN */ | |
514 | else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xd0) | |
515 | { | |
516 | int dN = instr[1] & 0x03; | |
517 | int aM = (instr[1] & 0x0c) >> 2; | |
9cacebf5 | 518 | |
6c02c64c | 519 | regs[E_D0_REGNUM + dN] = regs[E_A0_REGNUM + aM]; |
9cacebf5 | 520 | |
6c02c64c KB |
521 | pc += 2; |
522 | } | |
523 | /* mov dM, aN */ | |
524 | else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xe0) | |
525 | { | |
526 | int aN = instr[1] & 0x03; | |
527 | int dM = (instr[1] & 0x0c) >> 2; | |
9cacebf5 | 528 | |
6c02c64c | 529 | regs[E_A0_REGNUM + aN] = regs[E_D0_REGNUM + dM]; |
9cacebf5 | 530 | |
6c02c64c KB |
531 | pc += 2; |
532 | } | |
533 | /* add imm8, SP */ | |
534 | else if (instr[0] == 0xf8 && instr[1] == 0xfe) | |
535 | { | |
536 | gdb_byte buf[1]; | |
537 | LONGEST imm8; | |
9cacebf5 | 538 | |
9cacebf5 | 539 | |
6c02c64c KB |
540 | status = target_read_memory (pc + 2, buf, 1); |
541 | if (status != 0) | |
542 | break; | |
9cacebf5 | 543 | |
e17a4113 | 544 | imm8 = extract_signed_integer (buf, 1, byte_order); |
6c02c64c | 545 | regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm8); |
9cacebf5 | 546 | |
6c02c64c KB |
547 | pc += 3; |
548 | /* Stack pointer adjustments are frame related. */ | |
549 | after_last_frame_setup_insn = pc; | |
550 | } | |
551 | /* add imm16, SP */ | |
552 | else if (instr[0] == 0xfa && instr[1] == 0xfe) | |
553 | { | |
554 | gdb_byte buf[2]; | |
555 | LONGEST imm16; | |
9cacebf5 | 556 | |
6c02c64c KB |
557 | status = target_read_memory (pc + 2, buf, 2); |
558 | if (status != 0) | |
559 | break; | |
9cacebf5 | 560 | |
e17a4113 | 561 | imm16 = extract_signed_integer (buf, 2, byte_order); |
6c02c64c | 562 | regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm16); |
9cacebf5 | 563 | |
6c02c64c KB |
564 | pc += 4; |
565 | /* Stack pointer adjustments are frame related. */ | |
566 | after_last_frame_setup_insn = pc; | |
567 | } | |
568 | /* add imm32, SP */ | |
569 | else if (instr[0] == 0xfc && instr[1] == 0xfe) | |
570 | { | |
571 | gdb_byte buf[4]; | |
572 | LONGEST imm32; | |
9cacebf5 | 573 | |
6c02c64c KB |
574 | status = target_read_memory (pc + 2, buf, 4); |
575 | if (status != 0) | |
576 | break; | |
9cacebf5 | 577 | |
9cacebf5 | 578 | |
e17a4113 | 579 | imm32 = extract_signed_integer (buf, 4, byte_order); |
6c02c64c | 580 | regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm32); |
9cacebf5 | 581 | |
6c02c64c KB |
582 | pc += 6; |
583 | /* Stack pointer adjustments are frame related. */ | |
584 | after_last_frame_setup_insn = pc; | |
585 | } | |
586 | /* add imm8, aN */ | |
587 | else if ((instr[0] & 0xfc) == 0x20) | |
588 | { | |
589 | int aN; | |
590 | LONGEST imm8; | |
9cacebf5 | 591 | |
6c02c64c | 592 | aN = instr[0] & 0x03; |
e17a4113 | 593 | imm8 = extract_signed_integer (&instr[1], 1, byte_order); |
9cacebf5 | 594 | |
6c02c64c KB |
595 | regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN], |
596 | imm8); | |
9cacebf5 | 597 | |
6c02c64c KB |
598 | pc += 2; |
599 | } | |
600 | /* add imm16, aN */ | |
601 | else if (instr[0] == 0xfa && (instr[1] & 0xfc) == 0xd0) | |
602 | { | |
603 | int aN; | |
604 | LONGEST imm16; | |
605 | gdb_byte buf[2]; | |
9cacebf5 | 606 | |
6c02c64c | 607 | aN = instr[1] & 0x03; |
9cacebf5 | 608 | |
6c02c64c KB |
609 | status = target_read_memory (pc + 2, buf, 2); |
610 | if (status != 0) | |
611 | break; | |
9cacebf5 | 612 | |
9cacebf5 | 613 | |
e17a4113 | 614 | imm16 = extract_signed_integer (buf, 2, byte_order); |
9cacebf5 | 615 | |
6c02c64c KB |
616 | regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN], |
617 | imm16); | |
9cacebf5 | 618 | |
6c02c64c KB |
619 | pc += 4; |
620 | } | |
621 | /* add imm32, aN */ | |
622 | else if (instr[0] == 0xfc && (instr[1] & 0xfc) == 0xd0) | |
623 | { | |
624 | int aN; | |
625 | LONGEST imm32; | |
626 | gdb_byte buf[4]; | |
9cacebf5 | 627 | |
6c02c64c | 628 | aN = instr[1] & 0x03; |
9cacebf5 | 629 | |
6c02c64c KB |
630 | status = target_read_memory (pc + 2, buf, 4); |
631 | if (status != 0) | |
632 | break; | |
9cacebf5 | 633 | |
e17a4113 | 634 | imm32 = extract_signed_integer (buf, 2, byte_order); |
9cacebf5 | 635 | |
6c02c64c KB |
636 | regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN], |
637 | imm32); | |
638 | pc += 6; | |
639 | } | |
640 | /* fmov fsM, (rN) */ | |
641 | else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x30) | |
642 | { | |
643 | int fsM, sM, Y, rN; | |
644 | gdb_byte buf[1]; | |
9cacebf5 | 645 | |
6c02c64c | 646 | Y = (instr[1] & 0x02) >> 1; |
9cacebf5 | 647 | |
6c02c64c KB |
648 | status = target_read_memory (pc + 2, buf, 1); |
649 | if (status != 0) | |
650 | break; | |
9cacebf5 | 651 | |
6c02c64c KB |
652 | sM = (buf[0] & 0xf0) >> 4; |
653 | rN = buf[0] & 0x0f; | |
654 | fsM = (Y << 4) | sM; | |
9cacebf5 | 655 | |
6c02c64c KB |
656 | pv_area_store (stack, regs[translate_rreg (rN)], 4, |
657 | regs[E_FS0_REGNUM + fsM]); | |
9cacebf5 | 658 | |
6c02c64c KB |
659 | pc += 3; |
660 | } | |
661 | /* fmov fsM, (sp) */ | |
662 | else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x34) | |
663 | { | |
664 | int fsM, sM, Y; | |
665 | gdb_byte buf[1]; | |
9cacebf5 | 666 | |
6c02c64c | 667 | Y = (instr[1] & 0x02) >> 1; |
9cacebf5 | 668 | |
6c02c64c KB |
669 | status = target_read_memory (pc + 2, buf, 1); |
670 | if (status != 0) | |
671 | break; | |
9cacebf5 | 672 | |
6c02c64c KB |
673 | sM = (buf[0] & 0xf0) >> 4; |
674 | fsM = (Y << 4) | sM; | |
9cacebf5 | 675 | |
6c02c64c KB |
676 | pv_area_store (stack, regs[E_SP_REGNUM], 4, |
677 | regs[E_FS0_REGNUM + fsM]); | |
9cacebf5 | 678 | |
6c02c64c KB |
679 | pc += 3; |
680 | } | |
681 | /* fmov fsM, (rN, rI) */ | |
682 | else if (instr[0] == 0xfb && instr[1] == 0x37) | |
683 | { | |
684 | int fsM, sM, Z, rN, rI; | |
685 | gdb_byte buf[2]; | |
9cacebf5 | 686 | |
9cacebf5 | 687 | |
6c02c64c KB |
688 | status = target_read_memory (pc + 2, buf, 2); |
689 | if (status != 0) | |
690 | break; | |
83845630 | 691 | |
6c02c64c KB |
692 | rI = (buf[0] & 0xf0) >> 4; |
693 | rN = buf[0] & 0x0f; | |
694 | sM = (buf[1] & 0xf0) >> 4; | |
695 | Z = (buf[1] & 0x02) >> 1; | |
696 | fsM = (Z << 4) | sM; | |
83845630 | 697 | |
6c02c64c KB |
698 | pv_area_store (stack, |
699 | pv_add (regs[translate_rreg (rN)], | |
700 | regs[translate_rreg (rI)]), | |
701 | 4, regs[E_FS0_REGNUM + fsM]); | |
83845630 | 702 | |
6c02c64c KB |
703 | pc += 4; |
704 | } | |
705 | /* fmov fsM, (d8, rN) */ | |
706 | else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x30) | |
4640dd91 | 707 | { |
6c02c64c KB |
708 | int fsM, sM, Y, rN; |
709 | LONGEST d8; | |
710 | gdb_byte buf[2]; | |
711 | ||
712 | Y = (instr[1] & 0x02) >> 1; | |
713 | ||
714 | status = target_read_memory (pc + 2, buf, 2); | |
715 | if (status != 0) | |
716 | break; | |
717 | ||
718 | sM = (buf[0] & 0xf0) >> 4; | |
719 | rN = buf[0] & 0x0f; | |
720 | fsM = (Y << 4) | sM; | |
e17a4113 | 721 | d8 = extract_signed_integer (&buf[1], 1, byte_order); |
6c02c64c KB |
722 | |
723 | pv_area_store (stack, | |
724 | pv_add_constant (regs[translate_rreg (rN)], d8), | |
725 | 4, regs[E_FS0_REGNUM + fsM]); | |
726 | ||
727 | pc += 4; | |
4640dd91 | 728 | } |
6c02c64c KB |
729 | /* fmov fsM, (d24, rN) */ |
730 | else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x30) | |
83845630 | 731 | { |
6c02c64c KB |
732 | int fsM, sM, Y, rN; |
733 | LONGEST d24; | |
734 | gdb_byte buf[4]; | |
735 | ||
736 | Y = (instr[1] & 0x02) >> 1; | |
737 | ||
738 | status = target_read_memory (pc + 2, buf, 4); | |
83845630 | 739 | if (status != 0) |
6c02c64c KB |
740 | break; |
741 | ||
742 | sM = (buf[0] & 0xf0) >> 4; | |
743 | rN = buf[0] & 0x0f; | |
744 | fsM = (Y << 4) | sM; | |
e17a4113 | 745 | d24 = extract_signed_integer (&buf[1], 3, byte_order); |
6c02c64c KB |
746 | |
747 | pv_area_store (stack, | |
748 | pv_add_constant (regs[translate_rreg (rN)], d24), | |
749 | 4, regs[E_FS0_REGNUM + fsM]); | |
750 | ||
751 | pc += 6; | |
83845630 | 752 | } |
6c02c64c KB |
753 | /* fmov fsM, (d32, rN) */ |
754 | else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x30) | |
755 | { | |
756 | int fsM, sM, Y, rN; | |
757 | LONGEST d32; | |
758 | gdb_byte buf[5]; | |
4640dd91 | 759 | |
6c02c64c KB |
760 | Y = (instr[1] & 0x02) >> 1; |
761 | ||
762 | status = target_read_memory (pc + 2, buf, 5); | |
763 | if (status != 0) | |
764 | break; | |
765 | ||
766 | sM = (buf[0] & 0xf0) >> 4; | |
767 | rN = buf[0] & 0x0f; | |
768 | fsM = (Y << 4) | sM; | |
e17a4113 | 769 | d32 = extract_signed_integer (&buf[1], 4, byte_order); |
9cacebf5 | 770 | |
6c02c64c KB |
771 | pv_area_store (stack, |
772 | pv_add_constant (regs[translate_rreg (rN)], d32), | |
773 | 4, regs[E_FS0_REGNUM + fsM]); | |
774 | ||
775 | pc += 7; | |
776 | } | |
777 | /* fmov fsM, (d8, SP) */ | |
778 | else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x34) | |
9cacebf5 | 779 | { |
6c02c64c KB |
780 | int fsM, sM, Y; |
781 | LONGEST d8; | |
782 | gdb_byte buf[2]; | |
783 | ||
784 | Y = (instr[1] & 0x02) >> 1; | |
785 | ||
786 | status = target_read_memory (pc + 2, buf, 2); | |
787 | if (status != 0) | |
788 | break; | |
789 | ||
790 | sM = (buf[0] & 0xf0) >> 4; | |
791 | fsM = (Y << 4) | sM; | |
e17a4113 | 792 | d8 = extract_signed_integer (&buf[1], 1, byte_order); |
6c02c64c KB |
793 | |
794 | pv_area_store (stack, | |
795 | pv_add_constant (regs[E_SP_REGNUM], d8), | |
796 | 4, regs[E_FS0_REGNUM + fsM]); | |
797 | ||
798 | pc += 4; | |
9cacebf5 | 799 | } |
6c02c64c KB |
800 | /* fmov fsM, (d24, SP) */ |
801 | else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x34) | |
802 | { | |
803 | int fsM, sM, Y; | |
804 | LONGEST d24; | |
805 | gdb_byte buf[4]; | |
9cacebf5 | 806 | |
6c02c64c | 807 | Y = (instr[1] & 0x02) >> 1; |
9cacebf5 | 808 | |
6c02c64c KB |
809 | status = target_read_memory (pc + 2, buf, 4); |
810 | if (status != 0) | |
811 | break; | |
9cacebf5 | 812 | |
6c02c64c KB |
813 | sM = (buf[0] & 0xf0) >> 4; |
814 | fsM = (Y << 4) | sM; | |
e17a4113 | 815 | d24 = extract_signed_integer (&buf[1], 3, byte_order); |
9cacebf5 | 816 | |
6c02c64c KB |
817 | pv_area_store (stack, |
818 | pv_add_constant (regs[E_SP_REGNUM], d24), | |
819 | 4, regs[E_FS0_REGNUM + fsM]); | |
9cacebf5 | 820 | |
6c02c64c KB |
821 | pc += 6; |
822 | } | |
823 | /* fmov fsM, (d32, SP) */ | |
824 | else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x34) | |
825 | { | |
826 | int fsM, sM, Y; | |
827 | LONGEST d32; | |
828 | gdb_byte buf[5]; | |
9cacebf5 | 829 | |
6c02c64c | 830 | Y = (instr[1] & 0x02) >> 1; |
9cacebf5 | 831 | |
6c02c64c KB |
832 | status = target_read_memory (pc + 2, buf, 5); |
833 | if (status != 0) | |
834 | break; | |
835 | ||
836 | sM = (buf[0] & 0xf0) >> 4; | |
837 | fsM = (Y << 4) | sM; | |
e17a4113 | 838 | d32 = extract_signed_integer (&buf[1], 4, byte_order); |
6c02c64c KB |
839 | |
840 | pv_area_store (stack, | |
841 | pv_add_constant (regs[E_SP_REGNUM], d32), | |
842 | 4, regs[E_FS0_REGNUM + fsM]); | |
843 | ||
844 | pc += 7; | |
845 | } | |
846 | /* fmov fsM, (rN+) */ | |
847 | else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x31) | |
848 | { | |
849 | int fsM, sM, Y, rN, rN_regnum; | |
850 | gdb_byte buf[1]; | |
851 | ||
852 | Y = (instr[1] & 0x02) >> 1; | |
853 | ||
854 | status = target_read_memory (pc + 2, buf, 1); | |
855 | if (status != 0) | |
856 | break; | |
857 | ||
858 | sM = (buf[0] & 0xf0) >> 4; | |
859 | rN = buf[0] & 0x0f; | |
860 | fsM = (Y << 4) | sM; | |
861 | ||
862 | rN_regnum = translate_rreg (rN); | |
863 | ||
864 | pv_area_store (stack, regs[rN_regnum], 4, | |
865 | regs[E_FS0_REGNUM + fsM]); | |
866 | regs[rN_regnum] = pv_add_constant (regs[rN_regnum], 4); | |
867 | ||
868 | pc += 3; | |
869 | } | |
870 | /* fmov fsM, (rN+, imm8) */ | |
871 | else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x31) | |
872 | { | |
873 | int fsM, sM, Y, rN, rN_regnum; | |
874 | LONGEST imm8; | |
875 | gdb_byte buf[2]; | |
876 | ||
877 | Y = (instr[1] & 0x02) >> 1; | |
878 | ||
879 | status = target_read_memory (pc + 2, buf, 2); | |
880 | if (status != 0) | |
881 | break; | |
882 | ||
883 | sM = (buf[0] & 0xf0) >> 4; | |
884 | rN = buf[0] & 0x0f; | |
885 | fsM = (Y << 4) | sM; | |
e17a4113 | 886 | imm8 = extract_signed_integer (&buf[1], 1, byte_order); |
6c02c64c KB |
887 | |
888 | rN_regnum = translate_rreg (rN); | |
889 | ||
890 | pv_area_store (stack, regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]); | |
891 | regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm8); | |
892 | ||
893 | pc += 4; | |
894 | } | |
895 | /* fmov fsM, (rN+, imm24) */ | |
896 | else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x31) | |
897 | { | |
898 | int fsM, sM, Y, rN, rN_regnum; | |
899 | LONGEST imm24; | |
900 | gdb_byte buf[4]; | |
901 | ||
902 | Y = (instr[1] & 0x02) >> 1; | |
903 | ||
904 | status = target_read_memory (pc + 2, buf, 4); | |
905 | if (status != 0) | |
906 | break; | |
907 | ||
908 | sM = (buf[0] & 0xf0) >> 4; | |
909 | rN = buf[0] & 0x0f; | |
910 | fsM = (Y << 4) | sM; | |
e17a4113 | 911 | imm24 = extract_signed_integer (&buf[1], 3, byte_order); |
6c02c64c KB |
912 | |
913 | rN_regnum = translate_rreg (rN); | |
914 | ||
915 | pv_area_store (stack, regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]); | |
916 | regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm24); | |
917 | ||
918 | pc += 6; | |
919 | } | |
920 | /* fmov fsM, (rN+, imm32) */ | |
921 | else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x31) | |
922 | { | |
923 | int fsM, sM, Y, rN, rN_regnum; | |
924 | LONGEST imm32; | |
925 | gdb_byte buf[5]; | |
926 | ||
927 | Y = (instr[1] & 0x02) >> 1; | |
928 | ||
929 | status = target_read_memory (pc + 2, buf, 5); | |
930 | if (status != 0) | |
931 | break; | |
932 | ||
933 | sM = (buf[0] & 0xf0) >> 4; | |
934 | rN = buf[0] & 0x0f; | |
935 | fsM = (Y << 4) | sM; | |
e17a4113 | 936 | imm32 = extract_signed_integer (&buf[1], 4, byte_order); |
6c02c64c KB |
937 | |
938 | rN_regnum = translate_rreg (rN); | |
939 | ||
940 | pv_area_store (stack, regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]); | |
941 | regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm32); | |
942 | ||
943 | pc += 7; | |
944 | } | |
945 | /* mov imm8, aN */ | |
946 | else if ((instr[0] & 0xf0) == 0x90) | |
947 | { | |
948 | int aN = instr[0] & 0x03; | |
949 | LONGEST imm8; | |
9cacebf5 | 950 | |
e17a4113 | 951 | imm8 = extract_signed_integer (&instr[1], 1, byte_order); |
9cacebf5 | 952 | |
6c02c64c KB |
953 | regs[E_A0_REGNUM + aN] = pv_constant (imm8); |
954 | pc += 2; | |
955 | } | |
956 | /* mov imm16, aN */ | |
957 | else if ((instr[0] & 0xfc) == 0x24) | |
958 | { | |
959 | int aN = instr[0] & 0x03; | |
960 | gdb_byte buf[2]; | |
961 | LONGEST imm16; | |
962 | ||
963 | status = target_read_memory (pc + 1, buf, 2); | |
964 | if (status != 0) | |
965 | break; | |
966 | ||
e17a4113 | 967 | imm16 = extract_signed_integer (buf, 2, byte_order); |
6c02c64c KB |
968 | regs[E_A0_REGNUM + aN] = pv_constant (imm16); |
969 | pc += 3; | |
970 | } | |
971 | /* mov imm32, aN */ | |
972 | else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xdc)) | |
973 | { | |
974 | int aN = instr[1] & 0x03; | |
975 | gdb_byte buf[4]; | |
976 | LONGEST imm32; | |
977 | ||
978 | status = target_read_memory (pc + 2, buf, 4); | |
979 | if (status != 0) | |
980 | break; | |
981 | ||
e17a4113 | 982 | imm32 = extract_signed_integer (buf, 4, byte_order); |
6c02c64c KB |
983 | regs[E_A0_REGNUM + aN] = pv_constant (imm32); |
984 | pc += 6; | |
985 | } | |
986 | /* mov imm8, dN */ | |
987 | else if ((instr[0] & 0xf0) == 0x80) | |
988 | { | |
989 | int dN = instr[0] & 0x03; | |
990 | LONGEST imm8; | |
991 | ||
e17a4113 | 992 | imm8 = extract_signed_integer (&instr[1], 1, byte_order); |
6c02c64c KB |
993 | |
994 | regs[E_D0_REGNUM + dN] = pv_constant (imm8); | |
995 | pc += 2; | |
996 | } | |
997 | /* mov imm16, dN */ | |
998 | else if ((instr[0] & 0xfc) == 0x2c) | |
999 | { | |
1000 | int dN = instr[0] & 0x03; | |
1001 | gdb_byte buf[2]; | |
1002 | LONGEST imm16; | |
1003 | ||
1004 | status = target_read_memory (pc + 1, buf, 2); | |
1005 | if (status != 0) | |
1006 | break; | |
1007 | ||
e17a4113 | 1008 | imm16 = extract_signed_integer (buf, 2, byte_order); |
6c02c64c KB |
1009 | regs[E_D0_REGNUM + dN] = pv_constant (imm16); |
1010 | pc += 3; | |
1011 | } | |
1012 | /* mov imm32, dN */ | |
1013 | else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xcc)) | |
1014 | { | |
1015 | int dN = instr[1] & 0x03; | |
1016 | gdb_byte buf[4]; | |
1017 | LONGEST imm32; | |
1018 | ||
1019 | status = target_read_memory (pc + 2, buf, 4); | |
1020 | if (status != 0) | |
1021 | break; | |
1022 | ||
e17a4113 | 1023 | imm32 = extract_signed_integer (buf, 4, byte_order); |
6c02c64c KB |
1024 | regs[E_D0_REGNUM + dN] = pv_constant (imm32); |
1025 | pc += 6; | |
1026 | } | |
1027 | else | |
1028 | { | |
1029 | /* We've hit some instruction that we don't recognize. Hopefully, | |
1030 | we have enough to do prologue analysis. */ | |
1031 | break; | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | /* Is the frame size (offset, really) a known constant? */ | |
1036 | if (pv_is_register (regs[E_SP_REGNUM], E_SP_REGNUM)) | |
1037 | result->frame_size = regs[E_SP_REGNUM].k; | |
9cacebf5 | 1038 | |
6c02c64c KB |
1039 | /* Was the frame pointer initialized? */ |
1040 | if (pv_is_register (regs[E_A3_REGNUM], E_SP_REGNUM)) | |
1041 | { | |
1042 | result->has_frame_ptr = 1; | |
1043 | result->frame_ptr_offset = regs[E_A3_REGNUM].k; | |
9cacebf5 | 1044 | } |
6c02c64c KB |
1045 | |
1046 | /* Record where all the registers were saved. */ | |
1047 | pv_area_scan (stack, check_for_saved, (void *) result); | |
1048 | ||
1049 | result->prologue_end = after_last_frame_setup_insn; | |
1050 | ||
1051 | do_cleanups (back_to); | |
9cacebf5 MS |
1052 | } |
1053 | ||
342ee437 MS |
1054 | /* Function: skip_prologue |
1055 | Return the address of the first inst past the prologue of the function. */ | |
1056 | ||
1057 | static CORE_ADDR | |
6093d2eb | 1058 | mn10300_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
342ee437 | 1059 | { |
2c02bd72 | 1060 | const char *name; |
6c02c64c KB |
1061 | CORE_ADDR func_addr, func_end; |
1062 | struct mn10300_prologue p; | |
1063 | ||
1064 | /* Try to find the extent of the function that contains PC. */ | |
1065 | if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) | |
1066 | return pc; | |
1067 | ||
1068 | mn10300_analyze_prologue (gdbarch, pc, func_end, &p); | |
1069 | return p.prologue_end; | |
342ee437 MS |
1070 | } |
1071 | ||
6c02c64c KB |
1072 | /* Wrapper for mn10300_analyze_prologue: find the function start; |
1073 | use the current frame PC as the limit, then | |
1074 | invoke mn10300_analyze_prologue and return its result. */ | |
1075 | static struct mn10300_prologue * | |
1076 | mn10300_analyze_frame_prologue (struct frame_info *this_frame, | |
1077 | void **this_prologue_cache) | |
342ee437 | 1078 | { |
6c02c64c | 1079 | if (!*this_prologue_cache) |
93d42b30 | 1080 | { |
6c02c64c KB |
1081 | CORE_ADDR func_start, stop_addr; |
1082 | ||
1083 | *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct mn10300_prologue); | |
1084 | ||
1085 | func_start = get_frame_func (this_frame); | |
1086 | stop_addr = get_frame_pc (this_frame); | |
1087 | ||
1088 | /* If we couldn't find any function containing the PC, then | |
1089 | just initialize the prologue cache, but don't do anything. */ | |
1090 | if (!func_start) | |
1091 | stop_addr = func_start; | |
1092 | ||
1093 | mn10300_analyze_prologue (get_frame_arch (this_frame), | |
19ba03f4 SM |
1094 | func_start, stop_addr, |
1095 | ((struct mn10300_prologue *) | |
1096 | *this_prologue_cache)); | |
93d42b30 | 1097 | } |
342ee437 | 1098 | |
19ba03f4 | 1099 | return (struct mn10300_prologue *) *this_prologue_cache; |
6c02c64c KB |
1100 | } |
1101 | ||
1102 | /* Given the next frame and a prologue cache, return this frame's | |
1103 | base. */ | |
1104 | static CORE_ADDR | |
1105 | mn10300_frame_base (struct frame_info *this_frame, void **this_prologue_cache) | |
1106 | { | |
1107 | struct mn10300_prologue *p | |
1108 | = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache); | |
1109 | ||
1110 | /* In functions that use alloca, the distance between the stack | |
1111 | pointer and the frame base varies dynamically, so we can't use | |
1112 | the SP plus static information like prologue analysis to find the | |
1113 | frame base. However, such functions must have a frame pointer, | |
1114 | to be able to restore the SP on exit. So whenever we do have a | |
1115 | frame pointer, use that to find the base. */ | |
1116 | if (p->has_frame_ptr) | |
1117 | { | |
1118 | CORE_ADDR fp = get_frame_register_unsigned (this_frame, E_A3_REGNUM); | |
1119 | return fp - p->frame_ptr_offset; | |
1120 | } | |
1121 | else | |
1122 | { | |
1123 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, E_SP_REGNUM); | |
1124 | return sp - p->frame_size; | |
1125 | } | |
342ee437 MS |
1126 | } |
1127 | ||
1128 | /* Here is a dummy implementation. */ | |
1129 | static struct frame_id | |
94afd7a6 | 1130 | mn10300_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
342ee437 | 1131 | { |
94afd7a6 UW |
1132 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, E_SP_REGNUM); |
1133 | CORE_ADDR pc = get_frame_register_unsigned (this_frame, E_PC_REGNUM); | |
1134 | return frame_id_build (sp, pc); | |
342ee437 MS |
1135 | } |
1136 | ||
342ee437 | 1137 | static void |
94afd7a6 | 1138 | mn10300_frame_this_id (struct frame_info *this_frame, |
342ee437 MS |
1139 | void **this_prologue_cache, |
1140 | struct frame_id *this_id) | |
1141 | { | |
025bb325 MS |
1142 | *this_id = frame_id_build (mn10300_frame_base (this_frame, |
1143 | this_prologue_cache), | |
6c02c64c | 1144 | get_frame_func (this_frame)); |
342ee437 | 1145 | |
342ee437 MS |
1146 | } |
1147 | ||
94afd7a6 UW |
1148 | static struct value * |
1149 | mn10300_frame_prev_register (struct frame_info *this_frame, | |
6c02c64c | 1150 | void **this_prologue_cache, int regnum) |
342ee437 | 1151 | { |
6c02c64c KB |
1152 | struct mn10300_prologue *p |
1153 | = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache); | |
1154 | CORE_ADDR frame_base = mn10300_frame_base (this_frame, this_prologue_cache); | |
6c02c64c KB |
1155 | |
1156 | if (regnum == E_SP_REGNUM) | |
1157 | return frame_unwind_got_constant (this_frame, regnum, frame_base); | |
1158 | ||
1159 | /* If prologue analysis says we saved this register somewhere, | |
1160 | return a description of the stack slot holding it. */ | |
1161 | if (p->reg_offset[regnum] != 1) | |
1162 | return frame_unwind_got_memory (this_frame, regnum, | |
1163 | frame_base + p->reg_offset[regnum]); | |
1164 | ||
1165 | /* Otherwise, presume we haven't changed the value of this | |
1166 | register, and get it from the next frame. */ | |
1167 | return frame_unwind_got_register (this_frame, regnum, regnum); | |
342ee437 MS |
1168 | } |
1169 | ||
1170 | static const struct frame_unwind mn10300_frame_unwind = { | |
1171 | NORMAL_FRAME, | |
8fbca658 | 1172 | default_frame_unwind_stop_reason, |
342ee437 | 1173 | mn10300_frame_this_id, |
94afd7a6 UW |
1174 | mn10300_frame_prev_register, |
1175 | NULL, | |
1176 | default_frame_sniffer | |
342ee437 MS |
1177 | }; |
1178 | ||
1179 | static CORE_ADDR | |
6c02c64c | 1180 | mn10300_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
342ee437 MS |
1181 | { |
1182 | ULONGEST pc; | |
1183 | ||
6c02c64c | 1184 | pc = frame_unwind_register_unsigned (this_frame, E_PC_REGNUM); |
342ee437 MS |
1185 | return pc; |
1186 | } | |
1187 | ||
1188 | static CORE_ADDR | |
6c02c64c | 1189 | mn10300_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) |
342ee437 MS |
1190 | { |
1191 | ULONGEST sp; | |
1192 | ||
6c02c64c | 1193 | sp = frame_unwind_register_unsigned (this_frame, E_SP_REGNUM); |
342ee437 MS |
1194 | return sp; |
1195 | } | |
1196 | ||
1197 | static void | |
1198 | mn10300_frame_unwind_init (struct gdbarch *gdbarch) | |
1199 | { | |
94afd7a6 UW |
1200 | dwarf2_append_unwinders (gdbarch); |
1201 | frame_unwind_append_unwinder (gdbarch, &mn10300_frame_unwind); | |
94afd7a6 | 1202 | set_gdbarch_dummy_id (gdbarch, mn10300_dummy_id); |
342ee437 MS |
1203 | set_gdbarch_unwind_pc (gdbarch, mn10300_unwind_pc); |
1204 | set_gdbarch_unwind_sp (gdbarch, mn10300_unwind_sp); | |
1205 | } | |
1206 | ||
1207 | /* Function: push_dummy_call | |
1208 | * | |
1209 | * Set up machine state for a target call, including | |
1210 | * function arguments, stack, return address, etc. | |
1211 | * | |
1212 | */ | |
1213 | ||
1214 | static CORE_ADDR | |
1215 | mn10300_push_dummy_call (struct gdbarch *gdbarch, | |
1216 | struct value *target_func, | |
1217 | struct regcache *regcache, | |
1218 | CORE_ADDR bp_addr, | |
1219 | int nargs, struct value **args, | |
1220 | CORE_ADDR sp, | |
1221 | int struct_return, | |
1222 | CORE_ADDR struct_addr) | |
1223 | { | |
e17a4113 | 1224 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
342ee437 | 1225 | const int push_size = register_size (gdbarch, E_PC_REGNUM); |
1fb1ca27 | 1226 | int regs_used; |
342ee437 MS |
1227 | int len, arg_len; |
1228 | int stack_offset = 0; | |
1229 | int argnum; | |
948f8e3d | 1230 | const gdb_byte *val; |
b8b6e72f | 1231 | gdb_byte valbuf[MN10300_MAX_REGISTER_SIZE]; |
342ee437 | 1232 | |
342ee437 MS |
1233 | /* This should be a nop, but align the stack just in case something |
1234 | went wrong. Stacks are four byte aligned on the mn10300. */ | |
1235 | sp &= ~3; | |
1236 | ||
1237 | /* Now make space on the stack for the args. | |
1238 | ||
1239 | XXX This doesn't appear to handle pass-by-invisible reference | |
1240 | arguments. */ | |
1fb1ca27 | 1241 | regs_used = struct_return ? 1 : 0; |
342ee437 MS |
1242 | for (len = 0, argnum = 0; argnum < nargs; argnum++) |
1243 | { | |
1244 | arg_len = (TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3; | |
342ee437 MS |
1245 | while (regs_used < 2 && arg_len > 0) |
1246 | { | |
1247 | regs_used++; | |
1248 | arg_len -= push_size; | |
1249 | } | |
1250 | len += arg_len; | |
1251 | } | |
1252 | ||
1253 | /* Allocate stack space. */ | |
1254 | sp -= len; | |
1255 | ||
1fb1ca27 MS |
1256 | if (struct_return) |
1257 | { | |
1258 | regs_used = 1; | |
9c9acae0 | 1259 | regcache_cooked_write_unsigned (regcache, E_D0_REGNUM, struct_addr); |
1fb1ca27 MS |
1260 | } |
1261 | else | |
1262 | regs_used = 0; | |
1263 | ||
025bb325 | 1264 | /* Push all arguments onto the stack. */ |
342ee437 MS |
1265 | for (argnum = 0; argnum < nargs; argnum++) |
1266 | { | |
1fb1ca27 MS |
1267 | /* FIXME what about structs? Unions? */ |
1268 | if (TYPE_CODE (value_type (*args)) == TYPE_CODE_STRUCT | |
1269 | && TYPE_LENGTH (value_type (*args)) > 8) | |
1270 | { | |
1271 | /* Change to pointer-to-type. */ | |
1272 | arg_len = push_size; | |
b8b6e72f | 1273 | gdb_assert (push_size <= MN10300_MAX_REGISTER_SIZE); |
e17a4113 | 1274 | store_unsigned_integer (valbuf, push_size, byte_order, |
42ae5230 | 1275 | value_address (*args)); |
1fb1ca27 MS |
1276 | val = &valbuf[0]; |
1277 | } | |
1278 | else | |
1279 | { | |
1280 | arg_len = TYPE_LENGTH (value_type (*args)); | |
948f8e3d | 1281 | val = value_contents (*args); |
1fb1ca27 | 1282 | } |
342ee437 MS |
1283 | |
1284 | while (regs_used < 2 && arg_len > 0) | |
1285 | { | |
9c9acae0 | 1286 | regcache_cooked_write_unsigned (regcache, regs_used, |
e17a4113 | 1287 | extract_unsigned_integer (val, push_size, byte_order)); |
342ee437 MS |
1288 | val += push_size; |
1289 | arg_len -= push_size; | |
1290 | regs_used++; | |
1291 | } | |
1292 | ||
1293 | while (arg_len > 0) | |
1294 | { | |
1295 | write_memory (sp + stack_offset, val, push_size); | |
1296 | arg_len -= push_size; | |
1297 | val += push_size; | |
1298 | stack_offset += push_size; | |
1299 | } | |
1300 | ||
1301 | args++; | |
1302 | } | |
1303 | ||
1304 | /* Make space for the flushback area. */ | |
1305 | sp -= 8; | |
1306 | ||
1307 | /* Push the return address that contains the magic breakpoint. */ | |
1308 | sp -= 4; | |
e17a4113 | 1309 | write_memory_unsigned_integer (sp, push_size, byte_order, bp_addr); |
a64ae7e0 CV |
1310 | |
1311 | /* The CPU also writes the return address always into the | |
1312 | MDR register on "call". */ | |
1313 | regcache_cooked_write_unsigned (regcache, E_MDR_REGNUM, bp_addr); | |
1314 | ||
342ee437 MS |
1315 | /* Update $sp. */ |
1316 | regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp); | |
ee3a2f01 KB |
1317 | |
1318 | /* On the mn10300, it's possible to move some of the stack adjustment | |
1319 | and saving of the caller-save registers out of the prologue and | |
1320 | into the call sites. (When using gcc, this optimization can | |
1321 | occur when using the -mrelax switch.) If this occurs, the dwarf2 | |
1322 | info will reflect this fact. We can test to see if this is the | |
1323 | case by creating a new frame using the current stack pointer and | |
1324 | the address of the function that we're about to call. We then | |
1325 | unwind SP and see if it's different than the SP of our newly | |
1326 | created frame. If the SP values are the same, the caller is not | |
1327 | expected to allocate any additional stack. On the other hand, if | |
1328 | the SP values are different, the difference determines the | |
1329 | additional stack that must be allocated. | |
1330 | ||
1331 | Note that we don't update the return value though because that's | |
1332 | the value of the stack just after pushing the arguments, but prior | |
1333 | to performing the call. This value is needed in order to | |
025bb325 | 1334 | construct the frame ID of the dummy call. */ |
ee3a2f01 KB |
1335 | { |
1336 | CORE_ADDR func_addr = find_function_addr (target_func, NULL); | |
1337 | CORE_ADDR unwound_sp | |
1338 | = mn10300_unwind_sp (gdbarch, create_new_frame (sp, func_addr)); | |
1339 | if (sp != unwound_sp) | |
1340 | regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, | |
1341 | sp - (unwound_sp - sp)); | |
1342 | } | |
1343 | ||
342ee437 MS |
1344 | return sp; |
1345 | } | |
1346 | ||
336c28c5 KB |
1347 | /* If DWARF2 is a register number appearing in Dwarf2 debug info, then |
1348 | mn10300_dwarf2_reg_to_regnum (DWARF2) is the corresponding GDB | |
1349 | register number. Why don't Dwarf2 and GDB use the same numbering? | |
1350 | Who knows? But since people have object files lying around with | |
1351 | the existing Dwarf2 numbering, and other people have written stubs | |
1352 | to work with the existing GDB, neither of them can change. So we | |
1353 | just have to cope. */ | |
1354 | static int | |
be8626e0 | 1355 | mn10300_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int dwarf2) |
336c28c5 | 1356 | { |
c9f4d572 | 1357 | /* This table is supposed to be shaped like the gdbarch_register_name |
336c28c5 KB |
1358 | initializer in gcc/config/mn10300/mn10300.h. Registers which |
1359 | appear in GCC's numbering, but have no counterpart in GDB's | |
1360 | world, are marked with a -1. */ | |
1361 | static int dwarf2_to_gdb[] = { | |
c5bb7362 KB |
1362 | E_D0_REGNUM, E_D1_REGNUM, E_D2_REGNUM, E_D3_REGNUM, |
1363 | E_A0_REGNUM, E_A1_REGNUM, E_A2_REGNUM, E_A3_REGNUM, | |
1364 | -1, E_SP_REGNUM, | |
1365 | ||
1366 | E_E0_REGNUM, E_E1_REGNUM, E_E2_REGNUM, E_E3_REGNUM, | |
1367 | E_E4_REGNUM, E_E5_REGNUM, E_E6_REGNUM, E_E7_REGNUM, | |
1368 | ||
1369 | E_FS0_REGNUM + 0, E_FS0_REGNUM + 1, E_FS0_REGNUM + 2, E_FS0_REGNUM + 3, | |
1370 | E_FS0_REGNUM + 4, E_FS0_REGNUM + 5, E_FS0_REGNUM + 6, E_FS0_REGNUM + 7, | |
1371 | ||
1372 | E_FS0_REGNUM + 8, E_FS0_REGNUM + 9, E_FS0_REGNUM + 10, E_FS0_REGNUM + 11, | |
1373 | E_FS0_REGNUM + 12, E_FS0_REGNUM + 13, E_FS0_REGNUM + 14, E_FS0_REGNUM + 15, | |
1374 | ||
1375 | E_FS0_REGNUM + 16, E_FS0_REGNUM + 17, E_FS0_REGNUM + 18, E_FS0_REGNUM + 19, | |
1376 | E_FS0_REGNUM + 20, E_FS0_REGNUM + 21, E_FS0_REGNUM + 22, E_FS0_REGNUM + 23, | |
1377 | ||
1378 | E_FS0_REGNUM + 24, E_FS0_REGNUM + 25, E_FS0_REGNUM + 26, E_FS0_REGNUM + 27, | |
1379 | E_FS0_REGNUM + 28, E_FS0_REGNUM + 29, E_FS0_REGNUM + 30, E_FS0_REGNUM + 31, | |
1380 | ||
1381 | E_MDR_REGNUM, E_PSW_REGNUM, E_PC_REGNUM | |
336c28c5 KB |
1382 | }; |
1383 | ||
1384 | if (dwarf2 < 0 | |
bbc1a784 | 1385 | || dwarf2 >= ARRAY_SIZE (dwarf2_to_gdb)) |
0fde2c53 | 1386 | return -1; |
336c28c5 KB |
1387 | |
1388 | return dwarf2_to_gdb[dwarf2]; | |
1389 | } | |
342ee437 MS |
1390 | |
1391 | static struct gdbarch * | |
1392 | mn10300_gdbarch_init (struct gdbarch_info info, | |
1393 | struct gdbarch_list *arches) | |
1394 | { | |
1395 | struct gdbarch *gdbarch; | |
1396 | struct gdbarch_tdep *tdep; | |
4640dd91 | 1397 | int num_regs; |
342ee437 MS |
1398 | |
1399 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1400 | if (arches != NULL) | |
1401 | return arches->gdbarch; | |
1402 | ||
cdd238da | 1403 | tdep = XCNEW (struct gdbarch_tdep); |
342ee437 MS |
1404 | gdbarch = gdbarch_alloc (&info, tdep); |
1405 | ||
1406 | switch (info.bfd_arch_info->mach) | |
1407 | { | |
1408 | case 0: | |
1409 | case bfd_mach_mn10300: | |
1410 | set_gdbarch_register_name (gdbarch, mn10300_generic_register_name); | |
1411 | tdep->am33_mode = 0; | |
4640dd91 | 1412 | num_regs = 32; |
342ee437 MS |
1413 | break; |
1414 | case bfd_mach_am33: | |
1415 | set_gdbarch_register_name (gdbarch, am33_register_name); | |
1416 | tdep->am33_mode = 1; | |
4640dd91 KB |
1417 | num_regs = 32; |
1418 | break; | |
1419 | case bfd_mach_am33_2: | |
1420 | set_gdbarch_register_name (gdbarch, am33_2_register_name); | |
1421 | tdep->am33_mode = 2; | |
1422 | num_regs = 64; | |
1423 | set_gdbarch_fp0_regnum (gdbarch, 32); | |
342ee437 MS |
1424 | break; |
1425 | default: | |
1426 | internal_error (__FILE__, __LINE__, | |
1427 | _("mn10300_gdbarch_init: Unknown mn10300 variant")); | |
1428 | break; | |
1429 | } | |
1430 | ||
1b31f75d KB |
1431 | /* By default, chars are unsigned. */ |
1432 | set_gdbarch_char_signed (gdbarch, 0); | |
1433 | ||
342ee437 | 1434 | /* Registers. */ |
4640dd91 | 1435 | set_gdbarch_num_regs (gdbarch, num_regs); |
342ee437 MS |
1436 | set_gdbarch_register_type (gdbarch, mn10300_register_type); |
1437 | set_gdbarch_skip_prologue (gdbarch, mn10300_skip_prologue); | |
1438 | set_gdbarch_read_pc (gdbarch, mn10300_read_pc); | |
1439 | set_gdbarch_write_pc (gdbarch, mn10300_write_pc); | |
1440 | set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM); | |
1441 | set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM); | |
336c28c5 | 1442 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mn10300_dwarf2_reg_to_regnum); |
342ee437 MS |
1443 | |
1444 | /* Stack unwinding. */ | |
1445 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1446 | /* Breakpoints. */ | |
04180708 YQ |
1447 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1448 | mn10300_breakpoint::kind_from_pc); | |
1449 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1450 | mn10300_breakpoint::bp_from_kind); | |
025bb325 | 1451 | /* decr_pc_after_break? */ |
342ee437 MS |
1452 | |
1453 | /* Stage 2 */ | |
99fe5f9d | 1454 | set_gdbarch_return_value (gdbarch, mn10300_return_value); |
342ee437 MS |
1455 | |
1456 | /* Stage 3 -- get target calls working. */ | |
1457 | set_gdbarch_push_dummy_call (gdbarch, mn10300_push_dummy_call); | |
1458 | /* set_gdbarch_return_value (store, extract) */ | |
1459 | ||
1460 | ||
1461 | mn10300_frame_unwind_init (gdbarch); | |
1462 | ||
697e3bc9 KB |
1463 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1464 | gdbarch_init_osabi (info, gdbarch); | |
1465 | ||
342ee437 MS |
1466 | return gdbarch; |
1467 | } | |
1468 | ||
025bb325 | 1469 | /* Dump out the mn10300 specific architecture information. */ |
342ee437 MS |
1470 | |
1471 | static void | |
d93859e2 | 1472 | mn10300_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
342ee437 | 1473 | { |
d93859e2 | 1474 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
342ee437 MS |
1475 | fprintf_unfiltered (file, "mn10300_dump_tdep: am33_mode = %d\n", |
1476 | tdep->am33_mode); | |
1477 | } | |
1478 | ||
1479 | void | |
1480 | _initialize_mn10300_tdep (void) | |
1481 | { | |
1482 | gdbarch_register (bfd_arch_mn10300, mn10300_gdbarch_init, mn10300_dump_tdep); | |
1483 | } | |
1484 |