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d7066cce AG |
1 | /* Target-dependent code for Moxie. |
2 | ||
e2882c85 | 3 | Copyright (C) 2009-2018 Free Software Foundation, Inc. |
d7066cce AG |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "frame-unwind.h" | |
23 | #include "frame-base.h" | |
24 | #include "symtab.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcmd.h" | |
27 | #include "gdbcore.h" | |
d7066cce AG |
28 | #include "value.h" |
29 | #include "inferior.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
32 | #include "osabi.h" | |
33 | #include "language.h" | |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
37 | #include "dis-asm.h" | |
451fa05e | 38 | #include "record.h" |
d02ed0bb | 39 | #include "record-full.h" |
d7066cce | 40 | |
d7066cce | 41 | #include "moxie-tdep.h" |
325fac50 | 42 | #include <algorithm> |
d7066cce | 43 | |
d7066cce AG |
44 | /* Use an invalid address value as 'not available' marker. */ |
45 | enum { REG_UNAVAIL = (CORE_ADDR) -1 }; | |
46 | ||
47 | struct moxie_frame_cache | |
48 | { | |
49 | /* Base address. */ | |
50 | CORE_ADDR base; | |
51 | CORE_ADDR pc; | |
52 | LONGEST framesize; | |
53 | CORE_ADDR saved_regs[MOXIE_NUM_REGS]; | |
54 | CORE_ADDR saved_sp; | |
55 | }; | |
56 | ||
57 | /* Implement the "frame_align" gdbarch method. */ | |
58 | ||
59 | static CORE_ADDR | |
60 | moxie_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
61 | { | |
62 | /* Align to the size of an instruction (so that they can safely be | |
63 | pushed onto the stack. */ | |
64 | return sp & ~1; | |
65 | } | |
66 | ||
04180708 | 67 | constexpr gdb_byte moxie_break_insn[] = { 0x35, 0x00 }; |
d7066cce | 68 | |
04180708 | 69 | typedef BP_MANIPULATION (moxie_break_insn) moxie_breakpoint; |
d7066cce AG |
70 | |
71 | /* Moxie register names. */ | |
72 | ||
a121b7c1 | 73 | static const char *moxie_register_names[] = { |
d7066cce AG |
74 | "$fp", "$sp", "$r0", "$r1", "$r2", |
75 | "$r3", "$r4", "$r5", "$r6", "$r7", | |
76 | "$r8", "$r9", "$r10", "$r11", "$r12", | |
77 | "$r13", "$pc", "$cc" }; | |
78 | ||
79 | /* Implement the "register_name" gdbarch method. */ | |
80 | ||
81 | static const char * | |
82 | moxie_register_name (struct gdbarch *gdbarch, int reg_nr) | |
83 | { | |
84 | if (reg_nr < 0) | |
85 | return NULL; | |
86 | if (reg_nr >= MOXIE_NUM_REGS) | |
87 | return NULL; | |
88 | return moxie_register_names[reg_nr]; | |
89 | } | |
90 | ||
91 | /* Implement the "register_type" gdbarch method. */ | |
92 | ||
93 | static struct type * | |
94 | moxie_register_type (struct gdbarch *gdbarch, int reg_nr) | |
95 | { | |
96 | if (reg_nr == MOXIE_PC_REGNUM) | |
97 | return builtin_type (gdbarch)->builtin_func_ptr; | |
98 | else if (reg_nr == MOXIE_SP_REGNUM || reg_nr == MOXIE_FP_REGNUM) | |
99 | return builtin_type (gdbarch)->builtin_data_ptr; | |
100 | else | |
df4df182 | 101 | return builtin_type (gdbarch)->builtin_int32; |
d7066cce AG |
102 | } |
103 | ||
104 | /* Write into appropriate registers a function return value | |
105 | of type TYPE, given in virtual format. */ | |
106 | ||
107 | static void | |
108 | moxie_store_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 109 | const gdb_byte *valbuf) |
d7066cce | 110 | { |
ac7936df | 111 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 112 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d7066cce AG |
113 | CORE_ADDR regval; |
114 | int len = TYPE_LENGTH (type); | |
115 | ||
116 | /* Things always get returned in RET1_REGNUM, RET2_REGNUM. */ | |
e17a4113 | 117 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d7066cce AG |
118 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
119 | if (len > 4) | |
120 | { | |
7c543f7b | 121 | regval = extract_unsigned_integer (valbuf + 4, len - 4, byte_order); |
d7066cce AG |
122 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
123 | } | |
124 | } | |
125 | ||
126 | /* Decode the instructions within the given address range. Decide | |
127 | when we must have reached the end of the function prologue. If a | |
128 | frame_info pointer is provided, fill in its saved_regs etc. | |
129 | ||
130 | Returns the address of the first instruction after the prologue. */ | |
131 | ||
132 | static CORE_ADDR | |
133 | moxie_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR end_addr, | |
99f75275 AG |
134 | struct moxie_frame_cache *cache, |
135 | struct gdbarch *gdbarch) | |
d7066cce | 136 | { |
e17a4113 | 137 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d7066cce AG |
138 | CORE_ADDR next_addr; |
139 | ULONGEST inst, inst2; | |
140 | LONGEST offset; | |
141 | int regnum; | |
142 | ||
143 | /* Record where the jsra instruction saves the PC and FP. */ | |
144 | cache->saved_regs[MOXIE_PC_REGNUM] = -4; | |
145 | cache->saved_regs[MOXIE_FP_REGNUM] = 0; | |
146 | cache->framesize = 0; | |
147 | ||
148 | if (start_addr >= end_addr) | |
149 | return end_addr; | |
150 | ||
151 | for (next_addr = start_addr; next_addr < end_addr; ) | |
152 | { | |
e17a4113 | 153 | inst = read_memory_unsigned_integer (next_addr, 2, byte_order); |
d7066cce | 154 | |
5152ff90 AG |
155 | /* Match "push $sp $rN" where N is between 0 and 13 inclusive. */ |
156 | if (inst >= 0x0612 && inst <= 0x061f) | |
d7066cce AG |
157 | { |
158 | regnum = inst & 0x000f; | |
159 | cache->framesize += 4; | |
160 | cache->saved_regs[regnum] = cache->framesize; | |
161 | next_addr += 2; | |
162 | } | |
4ee73e90 AG |
163 | else |
164 | break; | |
ce0bf488 | 165 | } |
d7066cce | 166 | |
ce0bf488 | 167 | inst = read_memory_unsigned_integer (next_addr, 2, byte_order); |
d7066cce | 168 | |
ce0bf488 AG |
169 | /* Optional stack allocation for args and local vars <= 4 |
170 | byte. */ | |
5152ff90 | 171 | if (inst == 0x01e0) /* ldi.l $r12, X */ |
ce0bf488 AG |
172 | { |
173 | offset = read_memory_integer (next_addr + 2, 4, byte_order); | |
174 | inst2 = read_memory_unsigned_integer (next_addr + 6, 2, byte_order); | |
175 | ||
5152ff90 | 176 | if (inst2 == 0x291e) /* sub.l $sp, $r12 */ |
ce0bf488 AG |
177 | { |
178 | cache->framesize += offset; | |
179 | } | |
180 | ||
181 | return (next_addr + 8); | |
182 | } | |
5152ff90 | 183 | else if ((inst & 0xff00) == 0x9100) /* dec $sp, X */ |
ce0bf488 AG |
184 | { |
185 | cache->framesize += (inst & 0x00ff); | |
186 | next_addr += 2; | |
d7066cce | 187 | |
ce0bf488 AG |
188 | while (next_addr < end_addr) |
189 | { | |
190 | inst = read_memory_unsigned_integer (next_addr, 2, byte_order); | |
5152ff90 | 191 | if ((inst & 0xff00) != 0x9100) /* no more dec $sp, X */ |
ce0bf488 AG |
192 | break; |
193 | cache->framesize += (inst & 0x00ff); | |
194 | next_addr += 2; | |
d7066cce | 195 | } |
d7066cce AG |
196 | } |
197 | ||
198 | return next_addr; | |
199 | } | |
200 | ||
201 | /* Find the end of function prologue. */ | |
202 | ||
203 | static CORE_ADDR | |
204 | moxie_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
205 | { | |
206 | CORE_ADDR func_addr = 0, func_end = 0; | |
2c02bd72 | 207 | const char *func_name; |
d7066cce AG |
208 | |
209 | /* See if we can determine the end of the prologue via the symbol table. | |
210 | If so, then return either PC, or the PC after the prologue, whichever | |
211 | is greater. */ | |
212 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) | |
213 | { | |
d80b854b UW |
214 | CORE_ADDR post_prologue_pc |
215 | = skip_prologue_using_sal (gdbarch, func_addr); | |
d7066cce | 216 | if (post_prologue_pc != 0) |
325fac50 | 217 | return std::max (pc, post_prologue_pc); |
d7066cce AG |
218 | else |
219 | { | |
220 | /* Can't determine prologue from the symbol table, need to examine | |
221 | instructions. */ | |
222 | struct symtab_and_line sal; | |
223 | struct symbol *sym; | |
224 | struct moxie_frame_cache cache; | |
225 | CORE_ADDR plg_end; | |
226 | ||
227 | memset (&cache, 0, sizeof cache); | |
228 | ||
229 | plg_end = moxie_analyze_prologue (func_addr, | |
99f75275 | 230 | func_end, &cache, gdbarch); |
d7066cce | 231 | /* Found a function. */ |
835a09d9 | 232 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL).symbol; |
d7066cce | 233 | /* Don't use line number debug info for assembly source |
025bb325 | 234 | files. */ |
d7066cce AG |
235 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
236 | { | |
237 | sal = find_pc_line (func_addr, 0); | |
238 | if (sal.end && sal.end < func_end) | |
239 | { | |
240 | /* Found a line number, use it as end of | |
241 | prologue. */ | |
242 | return sal.end; | |
243 | } | |
244 | } | |
245 | /* No useable line symbol. Use result of prologue parsing | |
246 | method. */ | |
247 | return plg_end; | |
248 | } | |
249 | } | |
250 | ||
251 | /* No function symbol -- just return the PC. */ | |
252 | return (CORE_ADDR) pc; | |
253 | } | |
254 | ||
255 | struct moxie_unwind_cache | |
256 | { | |
257 | /* The previous frame's inner most stack address. Used as this | |
258 | frame ID's stack_addr. */ | |
259 | CORE_ADDR prev_sp; | |
260 | /* The frame's base, optionally used by the high-level debug info. */ | |
261 | CORE_ADDR base; | |
262 | int size; | |
263 | /* How far the SP and r13 (FP) have been offset from the start of | |
264 | the stack frame (as defined by the previous frame's stack | |
265 | pointer). */ | |
266 | LONGEST sp_offset; | |
267 | LONGEST r13_offset; | |
268 | int uses_frame; | |
269 | /* Table indicating the location of each and every register. */ | |
270 | struct trad_frame_saved_reg *saved_regs; | |
271 | }; | |
272 | ||
6ed1ff02 AG |
273 | /* Read an unsigned integer from the inferior, and adjust |
274 | endianess. */ | |
275 | static ULONGEST | |
276 | moxie_process_readu (CORE_ADDR addr, gdb_byte *buf, | |
277 | int length, enum bfd_endian byte_order) | |
278 | { | |
279 | if (target_read_memory (addr, buf, length)) | |
280 | { | |
281 | if (record_debug) | |
282 | printf_unfiltered (_("Process record: error reading memory at " | |
283 | "addr 0x%s len = %d.\n"), | |
284 | paddress (target_gdbarch (), addr), length); | |
285 | return -1; | |
286 | } | |
287 | ||
288 | return extract_unsigned_integer (buf, length, byte_order); | |
289 | } | |
290 | ||
291 | ||
292 | /* Helper macro to extract the signed 10-bit offset from a 16-bit | |
293 | branch instruction. */ | |
294 | #define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1) | |
295 | ||
296 | /* Insert a single step breakpoint. */ | |
297 | ||
a0ff9e1a | 298 | static std::vector<CORE_ADDR> |
f5ea389a | 299 | moxie_software_single_step (struct regcache *regcache) |
6ed1ff02 | 300 | { |
ac7936df | 301 | struct gdbarch *gdbarch = regcache->arch (); |
6ed1ff02 AG |
302 | CORE_ADDR addr; |
303 | gdb_byte buf[4]; | |
304 | uint16_t inst; | |
305 | uint32_t tmpu32; | |
306 | ULONGEST fp; | |
307 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
a0ff9e1a | 308 | std::vector<CORE_ADDR> next_pcs; |
6ed1ff02 | 309 | |
a8f34182 | 310 | addr = regcache_read_pc (regcache); |
6ed1ff02 AG |
311 | |
312 | inst = (uint16_t) moxie_process_readu (addr, buf, 2, byte_order); | |
313 | ||
314 | /* Decode instruction. */ | |
315 | if (inst & (1 << 15)) | |
316 | { | |
317 | if (inst & (1 << 14)) | |
318 | { | |
319 | /* This is a Form 3 instruction. */ | |
320 | int opcode = (inst >> 10 & 0xf); | |
321 | ||
322 | switch (opcode) | |
323 | { | |
324 | case 0x00: /* beq */ | |
325 | case 0x01: /* bne */ | |
326 | case 0x02: /* blt */ | |
327 | case 0x03: /* bgt */ | |
328 | case 0x04: /* bltu */ | |
329 | case 0x05: /* bgtu */ | |
330 | case 0x06: /* bge */ | |
331 | case 0x07: /* ble */ | |
332 | case 0x08: /* bgeu */ | |
333 | case 0x09: /* bleu */ | |
334 | /* Insert breaks on both branches, because we can't currently tell | |
335 | which way things will go. */ | |
a0ff9e1a SM |
336 | next_pcs.push_back (addr + 2); |
337 | next_pcs.push_back (addr + 2 + INST2OFFSET(inst)); | |
6ed1ff02 AG |
338 | break; |
339 | default: | |
340 | { | |
341 | /* Do nothing. */ | |
342 | break; | |
343 | } | |
344 | } | |
345 | } | |
346 | else | |
347 | { | |
348 | /* This is a Form 2 instruction. They are all 16 bits. */ | |
a0ff9e1a | 349 | next_pcs.push_back (addr + 2); |
6ed1ff02 AG |
350 | } |
351 | } | |
352 | else | |
353 | { | |
354 | /* This is a Form 1 instruction. */ | |
355 | int opcode = inst >> 8; | |
356 | ||
357 | switch (opcode) | |
358 | { | |
359 | /* 16-bit instructions. */ | |
6441e6db | 360 | case 0x00: /* bad */ |
6ed1ff02 AG |
361 | case 0x02: /* mov (register-to-register) */ |
362 | case 0x05: /* add.l */ | |
363 | case 0x06: /* push */ | |
364 | case 0x07: /* pop */ | |
365 | case 0x0a: /* ld.l (register indirect) */ | |
366 | case 0x0b: /* st.l */ | |
367 | case 0x0e: /* cmp */ | |
6441e6db AG |
368 | case 0x0f: /* nop */ |
369 | case 0x10: /* sex.b */ | |
370 | case 0x11: /* sex.s */ | |
371 | case 0x12: /* zex.b */ | |
372 | case 0x13: /* zex.s */ | |
373 | case 0x14: /* umul.x */ | |
374 | case 0x15: /* mul.x */ | |
6ed1ff02 AG |
375 | case 0x16: |
376 | case 0x17: | |
377 | case 0x18: | |
378 | case 0x1c: /* ld.b (register indirect) */ | |
379 | case 0x1e: /* st.b */ | |
380 | case 0x21: /* ld.s (register indirect) */ | |
381 | case 0x23: /* st.s */ | |
382 | case 0x26: /* and */ | |
383 | case 0x27: /* lshr */ | |
384 | case 0x28: /* ashl */ | |
385 | case 0x29: /* sub.l */ | |
386 | case 0x2a: /* neg */ | |
387 | case 0x2b: /* or */ | |
388 | case 0x2c: /* not */ | |
389 | case 0x2d: /* ashr */ | |
390 | case 0x2e: /* xor */ | |
391 | case 0x2f: /* mul.l */ | |
392 | case 0x31: /* div.l */ | |
393 | case 0x32: /* udiv.l */ | |
394 | case 0x33: /* mod.l */ | |
395 | case 0x34: /* umod.l */ | |
a0ff9e1a | 396 | next_pcs.push_back (addr + 2); |
6ed1ff02 AG |
397 | break; |
398 | ||
6441e6db AG |
399 | /* 32-bit instructions. */ |
400 | case 0x0c: /* ldo.l */ | |
401 | case 0x0d: /* sto.l */ | |
402 | case 0x36: /* ldo.b */ | |
403 | case 0x37: /* sto.b */ | |
404 | case 0x38: /* ldo.s */ | |
405 | case 0x39: /* sto.s */ | |
a0ff9e1a | 406 | next_pcs.push_back (addr + 4); |
6441e6db AG |
407 | break; |
408 | ||
6ed1ff02 AG |
409 | /* 48-bit instructions. */ |
410 | case 0x01: /* ldi.l (immediate) */ | |
411 | case 0x08: /* lda.l */ | |
412 | case 0x09: /* sta.l */ | |
6ed1ff02 AG |
413 | case 0x1b: /* ldi.b (immediate) */ |
414 | case 0x1d: /* lda.b */ | |
415 | case 0x1f: /* sta.b */ | |
416 | case 0x20: /* ldi.s (immediate) */ | |
417 | case 0x22: /* lda.s */ | |
418 | case 0x24: /* sta.s */ | |
a0ff9e1a | 419 | next_pcs.push_back (addr + 6); |
6ed1ff02 AG |
420 | break; |
421 | ||
422 | /* Control flow instructions. */ | |
423 | case 0x03: /* jsra */ | |
424 | case 0x1a: /* jmpa */ | |
a0ff9e1a SM |
425 | next_pcs.push_back (moxie_process_readu (addr + 2, buf, 4, |
426 | byte_order)); | |
6ed1ff02 AG |
427 | break; |
428 | ||
429 | case 0x04: /* ret */ | |
430 | regcache_cooked_read_unsigned (regcache, MOXIE_FP_REGNUM, &fp); | |
a0ff9e1a | 431 | next_pcs.push_back (moxie_process_readu (fp + 4, buf, 4, byte_order)); |
6ed1ff02 AG |
432 | break; |
433 | ||
434 | case 0x19: /* jsr */ | |
435 | case 0x25: /* jmp */ | |
0b883586 | 436 | regcache->raw_read ((inst >> 4) & 0xf, (gdb_byte *) & tmpu32); |
a0ff9e1a | 437 | next_pcs.push_back (tmpu32); |
6ed1ff02 AG |
438 | break; |
439 | ||
440 | case 0x30: /* swi */ | |
441 | case 0x35: /* brk */ | |
442 | /* Unsupported, for now. */ | |
443 | break; | |
444 | } | |
445 | } | |
446 | ||
93f9a11f | 447 | return next_pcs; |
6ed1ff02 AG |
448 | } |
449 | ||
451fa05e | 450 | /* Implement the "unwind_sp" gdbarch method. */ |
d7066cce AG |
451 | |
452 | static CORE_ADDR | |
453 | moxie_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
454 | { | |
455 | return frame_unwind_register_unsigned (next_frame, MOXIE_SP_REGNUM); | |
456 | } | |
457 | ||
458 | /* Given a return value in `regbuf' with a type `valtype', | |
459 | extract and copy its value into `valbuf'. */ | |
460 | ||
461 | static void | |
462 | moxie_extract_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 463 | gdb_byte *dst) |
d7066cce | 464 | { |
ac7936df | 465 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 466 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d7066cce AG |
467 | int len = TYPE_LENGTH (type); |
468 | ULONGEST tmp; | |
469 | ||
470 | /* By using store_unsigned_integer we avoid having to do | |
471 | anything special for small big-endian values. */ | |
472 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
7c543f7b | 473 | store_unsigned_integer (dst, (len > 4 ? len - 4 : len), byte_order, tmp); |
d7066cce AG |
474 | |
475 | /* Ignore return values more than 8 bytes in size because the moxie | |
476 | returns anything more than 8 bytes in the stack. */ | |
477 | if (len > 4) | |
478 | { | |
479 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
7c543f7b | 480 | store_unsigned_integer (dst + len - 4, 4, byte_order, tmp); |
d7066cce AG |
481 | } |
482 | } | |
483 | ||
484 | /* Implement the "return_value" gdbarch method. */ | |
485 | ||
486 | static enum return_value_convention | |
6a3a010b | 487 | moxie_return_value (struct gdbarch *gdbarch, struct value *function, |
d7066cce AG |
488 | struct type *valtype, struct regcache *regcache, |
489 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
490 | { | |
491 | if (TYPE_LENGTH (valtype) > 8) | |
492 | return RETURN_VALUE_STRUCT_CONVENTION; | |
493 | else | |
494 | { | |
495 | if (readbuf != NULL) | |
496 | moxie_extract_return_value (valtype, regcache, readbuf); | |
497 | if (writebuf != NULL) | |
498 | moxie_store_return_value (valtype, regcache, writebuf); | |
499 | return RETURN_VALUE_REGISTER_CONVENTION; | |
500 | } | |
501 | } | |
502 | ||
503 | /* Allocate and initialize a moxie_frame_cache object. */ | |
504 | ||
505 | static struct moxie_frame_cache * | |
506 | moxie_alloc_frame_cache (void) | |
507 | { | |
508 | struct moxie_frame_cache *cache; | |
509 | int i; | |
510 | ||
511 | cache = FRAME_OBSTACK_ZALLOC (struct moxie_frame_cache); | |
512 | ||
513 | cache->base = 0; | |
514 | cache->saved_sp = 0; | |
515 | cache->pc = 0; | |
516 | cache->framesize = 0; | |
517 | for (i = 0; i < MOXIE_NUM_REGS; ++i) | |
518 | cache->saved_regs[i] = REG_UNAVAIL; | |
519 | ||
520 | return cache; | |
521 | } | |
522 | ||
523 | /* Populate a moxie_frame_cache object for this_frame. */ | |
524 | ||
525 | static struct moxie_frame_cache * | |
526 | moxie_frame_cache (struct frame_info *this_frame, void **this_cache) | |
527 | { | |
528 | struct moxie_frame_cache *cache; | |
529 | CORE_ADDR current_pc; | |
530 | int i; | |
531 | ||
532 | if (*this_cache) | |
19ba03f4 | 533 | return (struct moxie_frame_cache *) *this_cache; |
d7066cce AG |
534 | |
535 | cache = moxie_alloc_frame_cache (); | |
536 | *this_cache = cache; | |
537 | ||
538 | cache->base = get_frame_register_unsigned (this_frame, MOXIE_FP_REGNUM); | |
539 | if (cache->base == 0) | |
540 | return cache; | |
541 | ||
542 | cache->pc = get_frame_func (this_frame); | |
543 | current_pc = get_frame_pc (this_frame); | |
544 | if (cache->pc) | |
99f75275 AG |
545 | { |
546 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
547 | moxie_analyze_prologue (cache->pc, current_pc, cache, gdbarch); | |
548 | } | |
d7066cce AG |
549 | |
550 | cache->saved_sp = cache->base - cache->framesize; | |
551 | ||
552 | for (i = 0; i < MOXIE_NUM_REGS; ++i) | |
553 | if (cache->saved_regs[i] != REG_UNAVAIL) | |
554 | cache->saved_regs[i] = cache->base - cache->saved_regs[i]; | |
555 | ||
556 | return cache; | |
557 | } | |
558 | ||
559 | /* Implement the "unwind_pc" gdbarch method. */ | |
560 | ||
561 | static CORE_ADDR | |
562 | moxie_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
563 | { | |
564 | return frame_unwind_register_unsigned (next_frame, MOXIE_PC_REGNUM); | |
565 | } | |
566 | ||
567 | /* Given a GDB frame, determine the address of the calling function's | |
568 | frame. This will be used to create a new GDB frame struct. */ | |
569 | ||
570 | static void | |
571 | moxie_frame_this_id (struct frame_info *this_frame, | |
572 | void **this_prologue_cache, struct frame_id *this_id) | |
573 | { | |
574 | struct moxie_frame_cache *cache = moxie_frame_cache (this_frame, | |
575 | this_prologue_cache); | |
576 | ||
577 | /* This marks the outermost frame. */ | |
578 | if (cache->base == 0) | |
579 | return; | |
580 | ||
581 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
582 | } | |
583 | ||
584 | /* Get the value of register regnum in the previous stack frame. */ | |
585 | ||
586 | static struct value * | |
587 | moxie_frame_prev_register (struct frame_info *this_frame, | |
588 | void **this_prologue_cache, int regnum) | |
589 | { | |
590 | struct moxie_frame_cache *cache = moxie_frame_cache (this_frame, | |
591 | this_prologue_cache); | |
592 | ||
593 | gdb_assert (regnum >= 0); | |
594 | ||
595 | if (regnum == MOXIE_SP_REGNUM && cache->saved_sp) | |
596 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); | |
597 | ||
598 | if (regnum < MOXIE_NUM_REGS && cache->saved_regs[regnum] != REG_UNAVAIL) | |
599 | return frame_unwind_got_memory (this_frame, regnum, | |
600 | cache->saved_regs[regnum]); | |
601 | ||
602 | return frame_unwind_got_register (this_frame, regnum, regnum); | |
603 | } | |
604 | ||
605 | static const struct frame_unwind moxie_frame_unwind = { | |
606 | NORMAL_FRAME, | |
8fbca658 | 607 | default_frame_unwind_stop_reason, |
d7066cce AG |
608 | moxie_frame_this_id, |
609 | moxie_frame_prev_register, | |
610 | NULL, | |
611 | default_frame_sniffer | |
612 | }; | |
613 | ||
614 | /* Return the base address of this_frame. */ | |
615 | ||
616 | static CORE_ADDR | |
617 | moxie_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
618 | { | |
619 | struct moxie_frame_cache *cache = moxie_frame_cache (this_frame, | |
620 | this_cache); | |
621 | ||
622 | return cache->base; | |
623 | } | |
624 | ||
625 | static const struct frame_base moxie_frame_base = { | |
626 | &moxie_frame_unwind, | |
627 | moxie_frame_base_address, | |
628 | moxie_frame_base_address, | |
629 | moxie_frame_base_address | |
630 | }; | |
631 | ||
632 | static struct frame_id | |
633 | moxie_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
634 | { | |
635 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, MOXIE_SP_REGNUM); | |
636 | ||
637 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
638 | } | |
639 | ||
451fa05e AG |
640 | /* Parse the current instruction and record the values of the registers and |
641 | memory that will be changed in current instruction to "record_arch_list". | |
025bb325 | 642 | Return -1 if something wrong. */ |
451fa05e | 643 | |
693be288 | 644 | static int |
451fa05e AG |
645 | moxie_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
646 | CORE_ADDR addr) | |
647 | { | |
648 | gdb_byte buf[4]; | |
649 | uint16_t inst; | |
650 | uint32_t tmpu32; | |
651 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
652 | ||
653 | if (record_debug > 1) | |
654 | fprintf_unfiltered (gdb_stdlog, "Process record: moxie_process_record " | |
655 | "addr = 0x%s\n", | |
f5656ead | 656 | paddress (target_gdbarch (), addr)); |
451fa05e AG |
657 | |
658 | inst = (uint16_t) moxie_process_readu (addr, buf, 2, byte_order); | |
659 | ||
660 | /* Decode instruction. */ | |
661 | if (inst & (1 << 15)) | |
662 | { | |
663 | if (inst & (1 << 14)) | |
664 | { | |
665 | /* This is a Form 3 instruction. */ | |
666 | int opcode = (inst >> 10 & 0xf); | |
667 | ||
668 | switch (opcode) | |
669 | { | |
670 | case 0x00: /* beq */ | |
671 | case 0x01: /* bne */ | |
672 | case 0x02: /* blt */ | |
673 | case 0x03: /* bgt */ | |
674 | case 0x04: /* bltu */ | |
675 | case 0x05: /* bgtu */ | |
676 | case 0x06: /* bge */ | |
677 | case 0x07: /* ble */ | |
678 | case 0x08: /* bgeu */ | |
679 | case 0x09: /* bleu */ | |
680 | /* Do nothing. */ | |
681 | break; | |
682 | default: | |
683 | { | |
684 | /* Do nothing. */ | |
685 | break; | |
686 | } | |
687 | } | |
688 | } | |
689 | else | |
690 | { | |
691 | /* This is a Form 2 instruction. */ | |
692 | int opcode = (inst >> 12 & 0x3); | |
693 | switch (opcode) | |
694 | { | |
695 | case 0x00: /* inc */ | |
696 | case 0x01: /* dec */ | |
697 | case 0x02: /* gsr */ | |
698 | { | |
699 | int reg = (inst >> 8) & 0xf; | |
25ea693b | 700 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
701 | return -1; |
702 | } | |
703 | break; | |
704 | case 0x03: /* ssr */ | |
705 | { | |
706 | /* Do nothing until GDB learns about moxie's special | |
707 | registers. */ | |
708 | } | |
709 | break; | |
710 | default: | |
711 | /* Do nothing. */ | |
712 | break; | |
713 | } | |
714 | } | |
715 | } | |
716 | else | |
717 | { | |
718 | /* This is a Form 1 instruction. */ | |
719 | int opcode = inst >> 8; | |
720 | ||
721 | switch (opcode) | |
722 | { | |
723 | case 0x00: /* nop */ | |
724 | /* Do nothing. */ | |
725 | break; | |
726 | case 0x01: /* ldi.l (immediate) */ | |
727 | case 0x02: /* mov (register-to-register) */ | |
728 | { | |
729 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 730 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
731 | return -1; |
732 | } | |
733 | break; | |
734 | case 0x03: /* jsra */ | |
735 | { | |
0b883586 | 736 | regcache->raw_read ( |
451fa05e AG |
737 | MOXIE_SP_REGNUM, (gdb_byte *) & tmpu32); |
738 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
739 | 4, byte_order); | |
25ea693b MM |
740 | if (record_full_arch_list_add_reg (regcache, MOXIE_FP_REGNUM) |
741 | || (record_full_arch_list_add_reg (regcache, | |
742 | MOXIE_SP_REGNUM)) | |
743 | || record_full_arch_list_add_mem (tmpu32 - 12, 12)) | |
451fa05e AG |
744 | return -1; |
745 | } | |
746 | break; | |
747 | case 0x04: /* ret */ | |
748 | { | |
25ea693b MM |
749 | if (record_full_arch_list_add_reg (regcache, MOXIE_FP_REGNUM) |
750 | || (record_full_arch_list_add_reg (regcache, | |
751 | MOXIE_SP_REGNUM))) | |
451fa05e AG |
752 | return -1; |
753 | } | |
754 | break; | |
755 | case 0x05: /* add.l */ | |
756 | { | |
757 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 758 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
759 | return -1; |
760 | } | |
761 | break; | |
762 | case 0x06: /* push */ | |
763 | { | |
764 | int reg = (inst >> 4) & 0xf; | |
0b883586 | 765 | regcache->raw_read (reg, (gdb_byte *) & tmpu32); |
451fa05e AG |
766 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, |
767 | 4, byte_order); | |
25ea693b MM |
768 | if (record_full_arch_list_add_reg (regcache, reg) |
769 | || record_full_arch_list_add_mem (tmpu32 - 4, 4)) | |
451fa05e AG |
770 | return -1; |
771 | } | |
772 | break; | |
773 | case 0x07: /* pop */ | |
774 | { | |
775 | int a = (inst >> 4) & 0xf; | |
776 | int b = inst & 0xf; | |
25ea693b MM |
777 | if (record_full_arch_list_add_reg (regcache, a) |
778 | || record_full_arch_list_add_reg (regcache, b)) | |
451fa05e AG |
779 | return -1; |
780 | } | |
781 | break; | |
782 | case 0x08: /* lda.l */ | |
783 | { | |
784 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 785 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
786 | return -1; |
787 | } | |
788 | break; | |
789 | case 0x09: /* sta.l */ | |
790 | { | |
791 | tmpu32 = (uint32_t) moxie_process_readu (addr+2, buf, | |
792 | 4, byte_order); | |
25ea693b | 793 | if (record_full_arch_list_add_mem (tmpu32, 4)) |
451fa05e AG |
794 | return -1; |
795 | } | |
796 | break; | |
797 | case 0x0a: /* ld.l (register indirect) */ | |
798 | { | |
799 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 800 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
801 | return -1; |
802 | } | |
803 | break; | |
804 | case 0x0b: /* st.l */ | |
805 | { | |
806 | int reg = (inst >> 4) & 0xf; | |
0b883586 | 807 | regcache->raw_read (reg, (gdb_byte *) & tmpu32); |
451fa05e AG |
808 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, |
809 | 4, byte_order); | |
25ea693b | 810 | if (record_full_arch_list_add_mem (tmpu32, 4)) |
451fa05e AG |
811 | return -1; |
812 | } | |
813 | break; | |
814 | case 0x0c: /* ldo.l */ | |
815 | { | |
816 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 817 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
818 | return -1; |
819 | } | |
820 | break; | |
821 | case 0x0d: /* sto.l */ | |
822 | { | |
823 | int reg = (inst >> 4) & 0xf; | |
6441e6db AG |
824 | uint32_t offset = (((int16_t) moxie_process_readu (addr+2, buf, 2, |
825 | byte_order)) << 16 ) >> 16; | |
0b883586 | 826 | regcache->raw_read (reg, (gdb_byte *) & tmpu32); |
451fa05e AG |
827 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, |
828 | 4, byte_order); | |
829 | tmpu32 += offset; | |
25ea693b | 830 | if (record_full_arch_list_add_mem (tmpu32, 4)) |
451fa05e AG |
831 | return -1; |
832 | } | |
833 | break; | |
834 | case 0x0e: /* cmp */ | |
835 | { | |
25ea693b | 836 | if (record_full_arch_list_add_reg (regcache, MOXIE_CC_REGNUM)) |
451fa05e AG |
837 | return -1; |
838 | } | |
839 | break; | |
6441e6db AG |
840 | case 0x0f: /* nop */ |
841 | { | |
842 | /* Do nothing. */ | |
843 | break; | |
844 | } | |
845 | case 0x10: /* sex.b */ | |
846 | case 0x11: /* sex.s */ | |
847 | case 0x12: /* zex.b */ | |
848 | case 0x13: /* zex.s */ | |
849 | case 0x14: /* umul.x */ | |
850 | case 0x15: /* mul.x */ | |
851 | { | |
852 | int reg = (inst >> 4) & 0xf; | |
853 | if (record_full_arch_list_add_reg (regcache, reg)) | |
854 | return -1; | |
855 | } | |
856 | break; | |
451fa05e AG |
857 | case 0x16: |
858 | case 0x17: | |
859 | case 0x18: | |
860 | { | |
861 | /* Do nothing. */ | |
862 | break; | |
863 | } | |
864 | case 0x19: /* jsr */ | |
865 | { | |
0b883586 | 866 | regcache->raw_read ( |
451fa05e AG |
867 | MOXIE_SP_REGNUM, (gdb_byte *) & tmpu32); |
868 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
869 | 4, byte_order); | |
25ea693b MM |
870 | if (record_full_arch_list_add_reg (regcache, MOXIE_FP_REGNUM) |
871 | || (record_full_arch_list_add_reg (regcache, | |
872 | MOXIE_SP_REGNUM)) | |
873 | || record_full_arch_list_add_mem (tmpu32 - 12, 12)) | |
451fa05e AG |
874 | return -1; |
875 | } | |
876 | break; | |
877 | case 0x1a: /* jmpa */ | |
878 | { | |
879 | /* Do nothing. */ | |
880 | } | |
881 | break; | |
882 | case 0x1b: /* ldi.b (immediate) */ | |
883 | case 0x1c: /* ld.b (register indirect) */ | |
884 | case 0x1d: /* lda.b */ | |
885 | { | |
886 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 887 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
888 | return -1; |
889 | } | |
890 | break; | |
891 | case 0x1e: /* st.b */ | |
892 | { | |
893 | int reg = (inst >> 4) & 0xf; | |
0b883586 | 894 | regcache->raw_read (reg, (gdb_byte *) & tmpu32); |
451fa05e AG |
895 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, |
896 | 4, byte_order); | |
25ea693b | 897 | if (record_full_arch_list_add_mem (tmpu32, 1)) |
451fa05e AG |
898 | return -1; |
899 | } | |
900 | break; | |
901 | case 0x1f: /* sta.b */ | |
902 | { | |
948f8e3d | 903 | tmpu32 = moxie_process_readu (addr+2, buf, 4, byte_order); |
25ea693b | 904 | if (record_full_arch_list_add_mem (tmpu32, 1)) |
451fa05e AG |
905 | return -1; |
906 | } | |
907 | break; | |
908 | case 0x20: /* ldi.s (immediate) */ | |
909 | case 0x21: /* ld.s (register indirect) */ | |
910 | case 0x22: /* lda.s */ | |
911 | { | |
912 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 913 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
914 | return -1; |
915 | } | |
916 | break; | |
917 | case 0x23: /* st.s */ | |
918 | { | |
919 | int reg = (inst >> 4) & 0xf; | |
0b883586 | 920 | regcache->raw_read (reg, (gdb_byte *) & tmpu32); |
451fa05e AG |
921 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, |
922 | 4, byte_order); | |
25ea693b | 923 | if (record_full_arch_list_add_mem (tmpu32, 2)) |
451fa05e AG |
924 | return -1; |
925 | } | |
926 | break; | |
927 | case 0x24: /* sta.s */ | |
928 | { | |
948f8e3d | 929 | tmpu32 = moxie_process_readu (addr+2, buf, 4, byte_order); |
25ea693b | 930 | if (record_full_arch_list_add_mem (tmpu32, 2)) |
451fa05e AG |
931 | return -1; |
932 | } | |
933 | break; | |
934 | case 0x25: /* jmp */ | |
935 | { | |
936 | /* Do nothing. */ | |
937 | } | |
938 | break; | |
939 | case 0x26: /* and */ | |
940 | case 0x27: /* lshr */ | |
941 | case 0x28: /* ashl */ | |
6441e6db | 942 | case 0x29: /* sub */ |
451fa05e AG |
943 | case 0x2a: /* neg */ |
944 | case 0x2b: /* or */ | |
945 | case 0x2c: /* not */ | |
946 | case 0x2d: /* ashr */ | |
947 | case 0x2e: /* xor */ | |
6441e6db | 948 | case 0x2f: /* mul */ |
451fa05e AG |
949 | { |
950 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 951 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
952 | return -1; |
953 | } | |
954 | break; | |
955 | case 0x30: /* swi */ | |
956 | { | |
957 | /* We currently implement support for libgloss' | |
958 | system calls. */ | |
959 | ||
948f8e3d | 960 | int inum = moxie_process_readu (addr+2, buf, 4, byte_order); |
451fa05e AG |
961 | |
962 | switch (inum) | |
963 | { | |
964 | case 0x1: /* SYS_exit */ | |
965 | { | |
966 | /* Do nothing. */ | |
967 | } | |
968 | break; | |
969 | case 0x2: /* SYS_open */ | |
970 | { | |
25ea693b | 971 | if (record_full_arch_list_add_reg (regcache, RET1_REGNUM)) |
451fa05e AG |
972 | return -1; |
973 | } | |
974 | break; | |
975 | case 0x4: /* SYS_read */ | |
976 | { | |
977 | uint32_t length, ptr; | |
978 | ||
979 | /* Read buffer pointer is in $r1. */ | |
0b883586 | 980 | regcache->raw_read (3, (gdb_byte *) & ptr); |
451fa05e AG |
981 | ptr = extract_unsigned_integer ((gdb_byte *) & ptr, |
982 | 4, byte_order); | |
983 | ||
025bb325 | 984 | /* String length is at 0x12($fp). */ |
0b883586 | 985 | regcache->raw_read ( |
451fa05e AG |
986 | MOXIE_FP_REGNUM, (gdb_byte *) & tmpu32); |
987 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
988 | 4, byte_order); | |
948f8e3d | 989 | length = moxie_process_readu (tmpu32+20, buf, 4, byte_order); |
451fa05e | 990 | |
25ea693b | 991 | if (record_full_arch_list_add_mem (ptr, length)) |
451fa05e AG |
992 | return -1; |
993 | } | |
994 | break; | |
995 | case 0x5: /* SYS_write */ | |
996 | { | |
25ea693b | 997 | if (record_full_arch_list_add_reg (regcache, RET1_REGNUM)) |
451fa05e AG |
998 | return -1; |
999 | } | |
1000 | break; | |
1001 | default: | |
1002 | break; | |
1003 | } | |
1004 | } | |
1005 | break; | |
1006 | case 0x31: /* div.l */ | |
1007 | case 0x32: /* udiv.l */ | |
1008 | case 0x33: /* mod.l */ | |
1009 | case 0x34: /* umod.l */ | |
1010 | { | |
1011 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 1012 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
1013 | return -1; |
1014 | } | |
1015 | break; | |
1016 | case 0x35: /* brk */ | |
1017 | /* Do nothing. */ | |
1018 | break; | |
1019 | case 0x36: /* ldo.b */ | |
1020 | { | |
1021 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 1022 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
1023 | return -1; |
1024 | } | |
1025 | break; | |
1026 | case 0x37: /* sto.b */ | |
1027 | { | |
1028 | int reg = (inst >> 4) & 0xf; | |
6441e6db AG |
1029 | uint32_t offset = (((int16_t) moxie_process_readu (addr+2, buf, 2, |
1030 | byte_order)) << 16 ) >> 16; | |
0b883586 | 1031 | regcache->raw_read (reg, (gdb_byte *) & tmpu32); |
451fa05e AG |
1032 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, |
1033 | 4, byte_order); | |
1034 | tmpu32 += offset; | |
25ea693b | 1035 | if (record_full_arch_list_add_mem (tmpu32, 1)) |
451fa05e AG |
1036 | return -1; |
1037 | } | |
1038 | break; | |
1039 | case 0x38: /* ldo.s */ | |
1040 | { | |
1041 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 1042 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
1043 | return -1; |
1044 | } | |
1045 | break; | |
1046 | case 0x39: /* sto.s */ | |
1047 | { | |
1048 | int reg = (inst >> 4) & 0xf; | |
6441e6db AG |
1049 | uint32_t offset = (((int16_t) moxie_process_readu (addr+2, buf, 2, |
1050 | byte_order)) << 16 ) >> 16; | |
0b883586 | 1051 | regcache->raw_read (reg, (gdb_byte *) & tmpu32); |
451fa05e AG |
1052 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, |
1053 | 4, byte_order); | |
1054 | tmpu32 += offset; | |
25ea693b | 1055 | if (record_full_arch_list_add_mem (tmpu32, 2)) |
451fa05e AG |
1056 | return -1; |
1057 | } | |
1058 | break; | |
1059 | default: | |
1060 | /* Do nothing. */ | |
1061 | break; | |
1062 | } | |
1063 | } | |
1064 | ||
25ea693b | 1065 | if (record_full_arch_list_add_reg (regcache, MOXIE_PC_REGNUM)) |
451fa05e | 1066 | return -1; |
25ea693b | 1067 | if (record_full_arch_list_add_end ()) |
451fa05e AG |
1068 | return -1; |
1069 | return 0; | |
1070 | } | |
1071 | ||
d7066cce AG |
1072 | /* Allocate and initialize the moxie gdbarch object. */ |
1073 | ||
1074 | static struct gdbarch * | |
1075 | moxie_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1076 | { | |
1077 | struct gdbarch *gdbarch; | |
1078 | struct gdbarch_tdep *tdep; | |
1079 | ||
1080 | /* If there is already a candidate, use it. */ | |
1081 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1082 | if (arches != NULL) | |
1083 | return arches->gdbarch; | |
1084 | ||
1085 | /* Allocate space for the new architecture. */ | |
cdd238da | 1086 | tdep = XCNEW (struct gdbarch_tdep); |
d7066cce AG |
1087 | gdbarch = gdbarch_alloc (&info, tdep); |
1088 | ||
53375380 PA |
1089 | set_gdbarch_wchar_bit (gdbarch, 32); |
1090 | set_gdbarch_wchar_signed (gdbarch, 0); | |
1091 | ||
d7066cce AG |
1092 | set_gdbarch_unwind_sp (gdbarch, moxie_unwind_sp); |
1093 | ||
1094 | set_gdbarch_num_regs (gdbarch, MOXIE_NUM_REGS); | |
1095 | set_gdbarch_sp_regnum (gdbarch, MOXIE_SP_REGNUM); | |
451fa05e | 1096 | set_gdbarch_pc_regnum (gdbarch, MOXIE_PC_REGNUM); |
d7066cce AG |
1097 | set_gdbarch_register_name (gdbarch, moxie_register_name); |
1098 | set_gdbarch_register_type (gdbarch, moxie_register_type); | |
1099 | ||
1100 | set_gdbarch_return_value (gdbarch, moxie_return_value); | |
1101 | ||
1102 | set_gdbarch_skip_prologue (gdbarch, moxie_skip_prologue); | |
1103 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
04180708 YQ |
1104 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1105 | moxie_breakpoint::kind_from_pc); | |
1106 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1107 | moxie_breakpoint::bp_from_kind); | |
d7066cce AG |
1108 | set_gdbarch_frame_align (gdbarch, moxie_frame_align); |
1109 | ||
1110 | frame_base_set_default (gdbarch, &moxie_frame_base); | |
1111 | ||
1112 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
1113 | stack address must match the SP value returned by | |
1114 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
1115 | set_gdbarch_dummy_id (gdbarch, moxie_dummy_id); | |
1116 | ||
1117 | set_gdbarch_unwind_pc (gdbarch, moxie_unwind_pc); | |
1118 | ||
d7066cce AG |
1119 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1120 | gdbarch_init_osabi (info, gdbarch); | |
1121 | ||
1122 | /* Hook in the default unwinders. */ | |
1123 | frame_unwind_append_unwinder (gdbarch, &moxie_frame_unwind); | |
1124 | ||
6ed1ff02 AG |
1125 | /* Single stepping. */ |
1126 | set_gdbarch_software_single_step (gdbarch, moxie_software_single_step); | |
1127 | ||
d7066cce AG |
1128 | /* Support simple overlay manager. */ |
1129 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
1130 | ||
451fa05e AG |
1131 | /* Support reverse debugging. */ |
1132 | set_gdbarch_process_record (gdbarch, moxie_process_record); | |
1133 | ||
d7066cce AG |
1134 | return gdbarch; |
1135 | } | |
1136 | ||
1137 | /* Register this machine's init routine. */ | |
1138 | ||
1139 | void | |
1140 | _initialize_moxie_tdep (void) | |
1141 | { | |
1142 | register_gdbarch_init (bfd_arch_moxie, moxie_gdbarch_init); | |
1143 | } |