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d7066cce AG |
1 | /* Target-dependent code for Moxie. |
2 | ||
61baf725 | 3 | Copyright (C) 2009-2017 Free Software Foundation, Inc. |
d7066cce AG |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "frame-unwind.h" | |
23 | #include "frame-base.h" | |
24 | #include "symtab.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcmd.h" | |
27 | #include "gdbcore.h" | |
d7066cce AG |
28 | #include "value.h" |
29 | #include "inferior.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
32 | #include "osabi.h" | |
33 | #include "language.h" | |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
37 | #include "dis-asm.h" | |
451fa05e | 38 | #include "record.h" |
d02ed0bb | 39 | #include "record-full.h" |
d7066cce | 40 | |
d7066cce | 41 | #include "moxie-tdep.h" |
325fac50 | 42 | #include <algorithm> |
d7066cce AG |
43 | |
44 | /* Local functions. */ | |
45 | ||
46 | extern void _initialize_moxie_tdep (void); | |
47 | ||
48 | /* Use an invalid address value as 'not available' marker. */ | |
49 | enum { REG_UNAVAIL = (CORE_ADDR) -1 }; | |
50 | ||
51 | struct moxie_frame_cache | |
52 | { | |
53 | /* Base address. */ | |
54 | CORE_ADDR base; | |
55 | CORE_ADDR pc; | |
56 | LONGEST framesize; | |
57 | CORE_ADDR saved_regs[MOXIE_NUM_REGS]; | |
58 | CORE_ADDR saved_sp; | |
59 | }; | |
60 | ||
61 | /* Implement the "frame_align" gdbarch method. */ | |
62 | ||
63 | static CORE_ADDR | |
64 | moxie_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
65 | { | |
66 | /* Align to the size of an instruction (so that they can safely be | |
67 | pushed onto the stack. */ | |
68 | return sp & ~1; | |
69 | } | |
70 | ||
04180708 | 71 | constexpr gdb_byte moxie_break_insn[] = { 0x35, 0x00 }; |
d7066cce | 72 | |
04180708 | 73 | typedef BP_MANIPULATION (moxie_break_insn) moxie_breakpoint; |
d7066cce AG |
74 | |
75 | /* Moxie register names. */ | |
76 | ||
a121b7c1 | 77 | static const char *moxie_register_names[] = { |
d7066cce AG |
78 | "$fp", "$sp", "$r0", "$r1", "$r2", |
79 | "$r3", "$r4", "$r5", "$r6", "$r7", | |
80 | "$r8", "$r9", "$r10", "$r11", "$r12", | |
81 | "$r13", "$pc", "$cc" }; | |
82 | ||
83 | /* Implement the "register_name" gdbarch method. */ | |
84 | ||
85 | static const char * | |
86 | moxie_register_name (struct gdbarch *gdbarch, int reg_nr) | |
87 | { | |
88 | if (reg_nr < 0) | |
89 | return NULL; | |
90 | if (reg_nr >= MOXIE_NUM_REGS) | |
91 | return NULL; | |
92 | return moxie_register_names[reg_nr]; | |
93 | } | |
94 | ||
95 | /* Implement the "register_type" gdbarch method. */ | |
96 | ||
97 | static struct type * | |
98 | moxie_register_type (struct gdbarch *gdbarch, int reg_nr) | |
99 | { | |
100 | if (reg_nr == MOXIE_PC_REGNUM) | |
101 | return builtin_type (gdbarch)->builtin_func_ptr; | |
102 | else if (reg_nr == MOXIE_SP_REGNUM || reg_nr == MOXIE_FP_REGNUM) | |
103 | return builtin_type (gdbarch)->builtin_data_ptr; | |
104 | else | |
df4df182 | 105 | return builtin_type (gdbarch)->builtin_int32; |
d7066cce AG |
106 | } |
107 | ||
108 | /* Write into appropriate registers a function return value | |
109 | of type TYPE, given in virtual format. */ | |
110 | ||
111 | static void | |
112 | moxie_store_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 113 | const gdb_byte *valbuf) |
d7066cce | 114 | { |
e17a4113 UW |
115 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
116 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d7066cce AG |
117 | CORE_ADDR regval; |
118 | int len = TYPE_LENGTH (type); | |
119 | ||
120 | /* Things always get returned in RET1_REGNUM, RET2_REGNUM. */ | |
e17a4113 | 121 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d7066cce AG |
122 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
123 | if (len > 4) | |
124 | { | |
7c543f7b | 125 | regval = extract_unsigned_integer (valbuf + 4, len - 4, byte_order); |
d7066cce AG |
126 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
127 | } | |
128 | } | |
129 | ||
130 | /* Decode the instructions within the given address range. Decide | |
131 | when we must have reached the end of the function prologue. If a | |
132 | frame_info pointer is provided, fill in its saved_regs etc. | |
133 | ||
134 | Returns the address of the first instruction after the prologue. */ | |
135 | ||
136 | static CORE_ADDR | |
137 | moxie_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR end_addr, | |
99f75275 AG |
138 | struct moxie_frame_cache *cache, |
139 | struct gdbarch *gdbarch) | |
d7066cce | 140 | { |
e17a4113 | 141 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d7066cce AG |
142 | CORE_ADDR next_addr; |
143 | ULONGEST inst, inst2; | |
144 | LONGEST offset; | |
145 | int regnum; | |
146 | ||
147 | /* Record where the jsra instruction saves the PC and FP. */ | |
148 | cache->saved_regs[MOXIE_PC_REGNUM] = -4; | |
149 | cache->saved_regs[MOXIE_FP_REGNUM] = 0; | |
150 | cache->framesize = 0; | |
151 | ||
152 | if (start_addr >= end_addr) | |
153 | return end_addr; | |
154 | ||
155 | for (next_addr = start_addr; next_addr < end_addr; ) | |
156 | { | |
e17a4113 | 157 | inst = read_memory_unsigned_integer (next_addr, 2, byte_order); |
d7066cce | 158 | |
5152ff90 AG |
159 | /* Match "push $sp $rN" where N is between 0 and 13 inclusive. */ |
160 | if (inst >= 0x0612 && inst <= 0x061f) | |
d7066cce AG |
161 | { |
162 | regnum = inst & 0x000f; | |
163 | cache->framesize += 4; | |
164 | cache->saved_regs[regnum] = cache->framesize; | |
165 | next_addr += 2; | |
166 | } | |
4ee73e90 AG |
167 | else |
168 | break; | |
ce0bf488 | 169 | } |
d7066cce | 170 | |
ce0bf488 | 171 | inst = read_memory_unsigned_integer (next_addr, 2, byte_order); |
d7066cce | 172 | |
ce0bf488 AG |
173 | /* Optional stack allocation for args and local vars <= 4 |
174 | byte. */ | |
5152ff90 | 175 | if (inst == 0x01e0) /* ldi.l $r12, X */ |
ce0bf488 AG |
176 | { |
177 | offset = read_memory_integer (next_addr + 2, 4, byte_order); | |
178 | inst2 = read_memory_unsigned_integer (next_addr + 6, 2, byte_order); | |
179 | ||
5152ff90 | 180 | if (inst2 == 0x291e) /* sub.l $sp, $r12 */ |
ce0bf488 AG |
181 | { |
182 | cache->framesize += offset; | |
183 | } | |
184 | ||
185 | return (next_addr + 8); | |
186 | } | |
5152ff90 | 187 | else if ((inst & 0xff00) == 0x9100) /* dec $sp, X */ |
ce0bf488 AG |
188 | { |
189 | cache->framesize += (inst & 0x00ff); | |
190 | next_addr += 2; | |
d7066cce | 191 | |
ce0bf488 AG |
192 | while (next_addr < end_addr) |
193 | { | |
194 | inst = read_memory_unsigned_integer (next_addr, 2, byte_order); | |
5152ff90 | 195 | if ((inst & 0xff00) != 0x9100) /* no more dec $sp, X */ |
ce0bf488 AG |
196 | break; |
197 | cache->framesize += (inst & 0x00ff); | |
198 | next_addr += 2; | |
d7066cce | 199 | } |
d7066cce AG |
200 | } |
201 | ||
202 | return next_addr; | |
203 | } | |
204 | ||
205 | /* Find the end of function prologue. */ | |
206 | ||
207 | static CORE_ADDR | |
208 | moxie_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
209 | { | |
210 | CORE_ADDR func_addr = 0, func_end = 0; | |
2c02bd72 | 211 | const char *func_name; |
d7066cce AG |
212 | |
213 | /* See if we can determine the end of the prologue via the symbol table. | |
214 | If so, then return either PC, or the PC after the prologue, whichever | |
215 | is greater. */ | |
216 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) | |
217 | { | |
d80b854b UW |
218 | CORE_ADDR post_prologue_pc |
219 | = skip_prologue_using_sal (gdbarch, func_addr); | |
d7066cce | 220 | if (post_prologue_pc != 0) |
325fac50 | 221 | return std::max (pc, post_prologue_pc); |
d7066cce AG |
222 | else |
223 | { | |
224 | /* Can't determine prologue from the symbol table, need to examine | |
225 | instructions. */ | |
226 | struct symtab_and_line sal; | |
227 | struct symbol *sym; | |
228 | struct moxie_frame_cache cache; | |
229 | CORE_ADDR plg_end; | |
230 | ||
231 | memset (&cache, 0, sizeof cache); | |
232 | ||
233 | plg_end = moxie_analyze_prologue (func_addr, | |
99f75275 | 234 | func_end, &cache, gdbarch); |
d7066cce | 235 | /* Found a function. */ |
835a09d9 | 236 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL).symbol; |
d7066cce | 237 | /* Don't use line number debug info for assembly source |
025bb325 | 238 | files. */ |
d7066cce AG |
239 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
240 | { | |
241 | sal = find_pc_line (func_addr, 0); | |
242 | if (sal.end && sal.end < func_end) | |
243 | { | |
244 | /* Found a line number, use it as end of | |
245 | prologue. */ | |
246 | return sal.end; | |
247 | } | |
248 | } | |
249 | /* No useable line symbol. Use result of prologue parsing | |
250 | method. */ | |
251 | return plg_end; | |
252 | } | |
253 | } | |
254 | ||
255 | /* No function symbol -- just return the PC. */ | |
256 | return (CORE_ADDR) pc; | |
257 | } | |
258 | ||
259 | struct moxie_unwind_cache | |
260 | { | |
261 | /* The previous frame's inner most stack address. Used as this | |
262 | frame ID's stack_addr. */ | |
263 | CORE_ADDR prev_sp; | |
264 | /* The frame's base, optionally used by the high-level debug info. */ | |
265 | CORE_ADDR base; | |
266 | int size; | |
267 | /* How far the SP and r13 (FP) have been offset from the start of | |
268 | the stack frame (as defined by the previous frame's stack | |
269 | pointer). */ | |
270 | LONGEST sp_offset; | |
271 | LONGEST r13_offset; | |
272 | int uses_frame; | |
273 | /* Table indicating the location of each and every register. */ | |
274 | struct trad_frame_saved_reg *saved_regs; | |
275 | }; | |
276 | ||
6ed1ff02 AG |
277 | /* Read an unsigned integer from the inferior, and adjust |
278 | endianess. */ | |
279 | static ULONGEST | |
280 | moxie_process_readu (CORE_ADDR addr, gdb_byte *buf, | |
281 | int length, enum bfd_endian byte_order) | |
282 | { | |
283 | if (target_read_memory (addr, buf, length)) | |
284 | { | |
285 | if (record_debug) | |
286 | printf_unfiltered (_("Process record: error reading memory at " | |
287 | "addr 0x%s len = %d.\n"), | |
288 | paddress (target_gdbarch (), addr), length); | |
289 | return -1; | |
290 | } | |
291 | ||
292 | return extract_unsigned_integer (buf, length, byte_order); | |
293 | } | |
294 | ||
295 | ||
296 | /* Helper macro to extract the signed 10-bit offset from a 16-bit | |
297 | branch instruction. */ | |
298 | #define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1) | |
299 | ||
300 | /* Insert a single step breakpoint. */ | |
301 | ||
a0ff9e1a | 302 | static std::vector<CORE_ADDR> |
f5ea389a | 303 | moxie_software_single_step (struct regcache *regcache) |
6ed1ff02 | 304 | { |
a8f34182 | 305 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
6ed1ff02 AG |
306 | CORE_ADDR addr; |
307 | gdb_byte buf[4]; | |
308 | uint16_t inst; | |
309 | uint32_t tmpu32; | |
310 | ULONGEST fp; | |
311 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
a0ff9e1a | 312 | std::vector<CORE_ADDR> next_pcs; |
6ed1ff02 | 313 | |
a8f34182 | 314 | addr = regcache_read_pc (regcache); |
6ed1ff02 AG |
315 | |
316 | inst = (uint16_t) moxie_process_readu (addr, buf, 2, byte_order); | |
317 | ||
318 | /* Decode instruction. */ | |
319 | if (inst & (1 << 15)) | |
320 | { | |
321 | if (inst & (1 << 14)) | |
322 | { | |
323 | /* This is a Form 3 instruction. */ | |
324 | int opcode = (inst >> 10 & 0xf); | |
325 | ||
326 | switch (opcode) | |
327 | { | |
328 | case 0x00: /* beq */ | |
329 | case 0x01: /* bne */ | |
330 | case 0x02: /* blt */ | |
331 | case 0x03: /* bgt */ | |
332 | case 0x04: /* bltu */ | |
333 | case 0x05: /* bgtu */ | |
334 | case 0x06: /* bge */ | |
335 | case 0x07: /* ble */ | |
336 | case 0x08: /* bgeu */ | |
337 | case 0x09: /* bleu */ | |
338 | /* Insert breaks on both branches, because we can't currently tell | |
339 | which way things will go. */ | |
a0ff9e1a SM |
340 | next_pcs.push_back (addr + 2); |
341 | next_pcs.push_back (addr + 2 + INST2OFFSET(inst)); | |
6ed1ff02 AG |
342 | break; |
343 | default: | |
344 | { | |
345 | /* Do nothing. */ | |
346 | break; | |
347 | } | |
348 | } | |
349 | } | |
350 | else | |
351 | { | |
352 | /* This is a Form 2 instruction. They are all 16 bits. */ | |
a0ff9e1a | 353 | next_pcs.push_back (addr + 2); |
6ed1ff02 AG |
354 | } |
355 | } | |
356 | else | |
357 | { | |
358 | /* This is a Form 1 instruction. */ | |
359 | int opcode = inst >> 8; | |
360 | ||
361 | switch (opcode) | |
362 | { | |
363 | /* 16-bit instructions. */ | |
6441e6db | 364 | case 0x00: /* bad */ |
6ed1ff02 AG |
365 | case 0x02: /* mov (register-to-register) */ |
366 | case 0x05: /* add.l */ | |
367 | case 0x06: /* push */ | |
368 | case 0x07: /* pop */ | |
369 | case 0x0a: /* ld.l (register indirect) */ | |
370 | case 0x0b: /* st.l */ | |
371 | case 0x0e: /* cmp */ | |
6441e6db AG |
372 | case 0x0f: /* nop */ |
373 | case 0x10: /* sex.b */ | |
374 | case 0x11: /* sex.s */ | |
375 | case 0x12: /* zex.b */ | |
376 | case 0x13: /* zex.s */ | |
377 | case 0x14: /* umul.x */ | |
378 | case 0x15: /* mul.x */ | |
6ed1ff02 AG |
379 | case 0x16: |
380 | case 0x17: | |
381 | case 0x18: | |
382 | case 0x1c: /* ld.b (register indirect) */ | |
383 | case 0x1e: /* st.b */ | |
384 | case 0x21: /* ld.s (register indirect) */ | |
385 | case 0x23: /* st.s */ | |
386 | case 0x26: /* and */ | |
387 | case 0x27: /* lshr */ | |
388 | case 0x28: /* ashl */ | |
389 | case 0x29: /* sub.l */ | |
390 | case 0x2a: /* neg */ | |
391 | case 0x2b: /* or */ | |
392 | case 0x2c: /* not */ | |
393 | case 0x2d: /* ashr */ | |
394 | case 0x2e: /* xor */ | |
395 | case 0x2f: /* mul.l */ | |
396 | case 0x31: /* div.l */ | |
397 | case 0x32: /* udiv.l */ | |
398 | case 0x33: /* mod.l */ | |
399 | case 0x34: /* umod.l */ | |
a0ff9e1a | 400 | next_pcs.push_back (addr + 2); |
6ed1ff02 AG |
401 | break; |
402 | ||
6441e6db AG |
403 | /* 32-bit instructions. */ |
404 | case 0x0c: /* ldo.l */ | |
405 | case 0x0d: /* sto.l */ | |
406 | case 0x36: /* ldo.b */ | |
407 | case 0x37: /* sto.b */ | |
408 | case 0x38: /* ldo.s */ | |
409 | case 0x39: /* sto.s */ | |
a0ff9e1a | 410 | next_pcs.push_back (addr + 4); |
6441e6db AG |
411 | break; |
412 | ||
6ed1ff02 AG |
413 | /* 48-bit instructions. */ |
414 | case 0x01: /* ldi.l (immediate) */ | |
415 | case 0x08: /* lda.l */ | |
416 | case 0x09: /* sta.l */ | |
6ed1ff02 AG |
417 | case 0x1b: /* ldi.b (immediate) */ |
418 | case 0x1d: /* lda.b */ | |
419 | case 0x1f: /* sta.b */ | |
420 | case 0x20: /* ldi.s (immediate) */ | |
421 | case 0x22: /* lda.s */ | |
422 | case 0x24: /* sta.s */ | |
a0ff9e1a | 423 | next_pcs.push_back (addr + 6); |
6ed1ff02 AG |
424 | break; |
425 | ||
426 | /* Control flow instructions. */ | |
427 | case 0x03: /* jsra */ | |
428 | case 0x1a: /* jmpa */ | |
a0ff9e1a SM |
429 | next_pcs.push_back (moxie_process_readu (addr + 2, buf, 4, |
430 | byte_order)); | |
6ed1ff02 AG |
431 | break; |
432 | ||
433 | case 0x04: /* ret */ | |
434 | regcache_cooked_read_unsigned (regcache, MOXIE_FP_REGNUM, &fp); | |
a0ff9e1a | 435 | next_pcs.push_back (moxie_process_readu (fp + 4, buf, 4, byte_order)); |
6ed1ff02 AG |
436 | break; |
437 | ||
438 | case 0x19: /* jsr */ | |
439 | case 0x25: /* jmp */ | |
440 | regcache_raw_read (regcache, | |
441 | (inst >> 4) & 0xf, (gdb_byte *) & tmpu32); | |
a0ff9e1a | 442 | next_pcs.push_back (tmpu32); |
6ed1ff02 AG |
443 | break; |
444 | ||
445 | case 0x30: /* swi */ | |
446 | case 0x35: /* brk */ | |
447 | /* Unsupported, for now. */ | |
448 | break; | |
449 | } | |
450 | } | |
451 | ||
93f9a11f | 452 | return next_pcs; |
6ed1ff02 AG |
453 | } |
454 | ||
d7066cce AG |
455 | /* Implement the "read_pc" gdbarch method. */ |
456 | ||
457 | static CORE_ADDR | |
458 | moxie_read_pc (struct regcache *regcache) | |
459 | { | |
460 | ULONGEST pc; | |
461 | ||
462 | regcache_cooked_read_unsigned (regcache, MOXIE_PC_REGNUM, &pc); | |
463 | return pc; | |
464 | } | |
465 | ||
466 | /* Implement the "write_pc" gdbarch method. */ | |
467 | ||
468 | static void | |
469 | moxie_write_pc (struct regcache *regcache, CORE_ADDR val) | |
470 | { | |
471 | regcache_cooked_write_unsigned (regcache, MOXIE_PC_REGNUM, val); | |
472 | } | |
473 | ||
451fa05e | 474 | /* Implement the "unwind_sp" gdbarch method. */ |
d7066cce AG |
475 | |
476 | static CORE_ADDR | |
477 | moxie_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
478 | { | |
479 | return frame_unwind_register_unsigned (next_frame, MOXIE_SP_REGNUM); | |
480 | } | |
481 | ||
482 | /* Given a return value in `regbuf' with a type `valtype', | |
483 | extract and copy its value into `valbuf'. */ | |
484 | ||
485 | static void | |
486 | moxie_extract_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 487 | gdb_byte *dst) |
d7066cce | 488 | { |
e17a4113 UW |
489 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
490 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d7066cce AG |
491 | int len = TYPE_LENGTH (type); |
492 | ULONGEST tmp; | |
493 | ||
494 | /* By using store_unsigned_integer we avoid having to do | |
495 | anything special for small big-endian values. */ | |
496 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
7c543f7b | 497 | store_unsigned_integer (dst, (len > 4 ? len - 4 : len), byte_order, tmp); |
d7066cce AG |
498 | |
499 | /* Ignore return values more than 8 bytes in size because the moxie | |
500 | returns anything more than 8 bytes in the stack. */ | |
501 | if (len > 4) | |
502 | { | |
503 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
7c543f7b | 504 | store_unsigned_integer (dst + len - 4, 4, byte_order, tmp); |
d7066cce AG |
505 | } |
506 | } | |
507 | ||
508 | /* Implement the "return_value" gdbarch method. */ | |
509 | ||
510 | static enum return_value_convention | |
6a3a010b | 511 | moxie_return_value (struct gdbarch *gdbarch, struct value *function, |
d7066cce AG |
512 | struct type *valtype, struct regcache *regcache, |
513 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
514 | { | |
515 | if (TYPE_LENGTH (valtype) > 8) | |
516 | return RETURN_VALUE_STRUCT_CONVENTION; | |
517 | else | |
518 | { | |
519 | if (readbuf != NULL) | |
520 | moxie_extract_return_value (valtype, regcache, readbuf); | |
521 | if (writebuf != NULL) | |
522 | moxie_store_return_value (valtype, regcache, writebuf); | |
523 | return RETURN_VALUE_REGISTER_CONVENTION; | |
524 | } | |
525 | } | |
526 | ||
527 | /* Allocate and initialize a moxie_frame_cache object. */ | |
528 | ||
529 | static struct moxie_frame_cache * | |
530 | moxie_alloc_frame_cache (void) | |
531 | { | |
532 | struct moxie_frame_cache *cache; | |
533 | int i; | |
534 | ||
535 | cache = FRAME_OBSTACK_ZALLOC (struct moxie_frame_cache); | |
536 | ||
537 | cache->base = 0; | |
538 | cache->saved_sp = 0; | |
539 | cache->pc = 0; | |
540 | cache->framesize = 0; | |
541 | for (i = 0; i < MOXIE_NUM_REGS; ++i) | |
542 | cache->saved_regs[i] = REG_UNAVAIL; | |
543 | ||
544 | return cache; | |
545 | } | |
546 | ||
547 | /* Populate a moxie_frame_cache object for this_frame. */ | |
548 | ||
549 | static struct moxie_frame_cache * | |
550 | moxie_frame_cache (struct frame_info *this_frame, void **this_cache) | |
551 | { | |
552 | struct moxie_frame_cache *cache; | |
553 | CORE_ADDR current_pc; | |
554 | int i; | |
555 | ||
556 | if (*this_cache) | |
19ba03f4 | 557 | return (struct moxie_frame_cache *) *this_cache; |
d7066cce AG |
558 | |
559 | cache = moxie_alloc_frame_cache (); | |
560 | *this_cache = cache; | |
561 | ||
562 | cache->base = get_frame_register_unsigned (this_frame, MOXIE_FP_REGNUM); | |
563 | if (cache->base == 0) | |
564 | return cache; | |
565 | ||
566 | cache->pc = get_frame_func (this_frame); | |
567 | current_pc = get_frame_pc (this_frame); | |
568 | if (cache->pc) | |
99f75275 AG |
569 | { |
570 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
571 | moxie_analyze_prologue (cache->pc, current_pc, cache, gdbarch); | |
572 | } | |
d7066cce AG |
573 | |
574 | cache->saved_sp = cache->base - cache->framesize; | |
575 | ||
576 | for (i = 0; i < MOXIE_NUM_REGS; ++i) | |
577 | if (cache->saved_regs[i] != REG_UNAVAIL) | |
578 | cache->saved_regs[i] = cache->base - cache->saved_regs[i]; | |
579 | ||
580 | return cache; | |
581 | } | |
582 | ||
583 | /* Implement the "unwind_pc" gdbarch method. */ | |
584 | ||
585 | static CORE_ADDR | |
586 | moxie_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
587 | { | |
588 | return frame_unwind_register_unsigned (next_frame, MOXIE_PC_REGNUM); | |
589 | } | |
590 | ||
591 | /* Given a GDB frame, determine the address of the calling function's | |
592 | frame. This will be used to create a new GDB frame struct. */ | |
593 | ||
594 | static void | |
595 | moxie_frame_this_id (struct frame_info *this_frame, | |
596 | void **this_prologue_cache, struct frame_id *this_id) | |
597 | { | |
598 | struct moxie_frame_cache *cache = moxie_frame_cache (this_frame, | |
599 | this_prologue_cache); | |
600 | ||
601 | /* This marks the outermost frame. */ | |
602 | if (cache->base == 0) | |
603 | return; | |
604 | ||
605 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
606 | } | |
607 | ||
608 | /* Get the value of register regnum in the previous stack frame. */ | |
609 | ||
610 | static struct value * | |
611 | moxie_frame_prev_register (struct frame_info *this_frame, | |
612 | void **this_prologue_cache, int regnum) | |
613 | { | |
614 | struct moxie_frame_cache *cache = moxie_frame_cache (this_frame, | |
615 | this_prologue_cache); | |
616 | ||
617 | gdb_assert (regnum >= 0); | |
618 | ||
619 | if (regnum == MOXIE_SP_REGNUM && cache->saved_sp) | |
620 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); | |
621 | ||
622 | if (regnum < MOXIE_NUM_REGS && cache->saved_regs[regnum] != REG_UNAVAIL) | |
623 | return frame_unwind_got_memory (this_frame, regnum, | |
624 | cache->saved_regs[regnum]); | |
625 | ||
626 | return frame_unwind_got_register (this_frame, regnum, regnum); | |
627 | } | |
628 | ||
629 | static const struct frame_unwind moxie_frame_unwind = { | |
630 | NORMAL_FRAME, | |
8fbca658 | 631 | default_frame_unwind_stop_reason, |
d7066cce AG |
632 | moxie_frame_this_id, |
633 | moxie_frame_prev_register, | |
634 | NULL, | |
635 | default_frame_sniffer | |
636 | }; | |
637 | ||
638 | /* Return the base address of this_frame. */ | |
639 | ||
640 | static CORE_ADDR | |
641 | moxie_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
642 | { | |
643 | struct moxie_frame_cache *cache = moxie_frame_cache (this_frame, | |
644 | this_cache); | |
645 | ||
646 | return cache->base; | |
647 | } | |
648 | ||
649 | static const struct frame_base moxie_frame_base = { | |
650 | &moxie_frame_unwind, | |
651 | moxie_frame_base_address, | |
652 | moxie_frame_base_address, | |
653 | moxie_frame_base_address | |
654 | }; | |
655 | ||
656 | static struct frame_id | |
657 | moxie_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
658 | { | |
659 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, MOXIE_SP_REGNUM); | |
660 | ||
661 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
662 | } | |
663 | ||
451fa05e AG |
664 | /* Parse the current instruction and record the values of the registers and |
665 | memory that will be changed in current instruction to "record_arch_list". | |
025bb325 | 666 | Return -1 if something wrong. */ |
451fa05e | 667 | |
693be288 | 668 | static int |
451fa05e AG |
669 | moxie_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
670 | CORE_ADDR addr) | |
671 | { | |
672 | gdb_byte buf[4]; | |
673 | uint16_t inst; | |
674 | uint32_t tmpu32; | |
675 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
676 | ||
677 | if (record_debug > 1) | |
678 | fprintf_unfiltered (gdb_stdlog, "Process record: moxie_process_record " | |
679 | "addr = 0x%s\n", | |
f5656ead | 680 | paddress (target_gdbarch (), addr)); |
451fa05e AG |
681 | |
682 | inst = (uint16_t) moxie_process_readu (addr, buf, 2, byte_order); | |
683 | ||
684 | /* Decode instruction. */ | |
685 | if (inst & (1 << 15)) | |
686 | { | |
687 | if (inst & (1 << 14)) | |
688 | { | |
689 | /* This is a Form 3 instruction. */ | |
690 | int opcode = (inst >> 10 & 0xf); | |
691 | ||
692 | switch (opcode) | |
693 | { | |
694 | case 0x00: /* beq */ | |
695 | case 0x01: /* bne */ | |
696 | case 0x02: /* blt */ | |
697 | case 0x03: /* bgt */ | |
698 | case 0x04: /* bltu */ | |
699 | case 0x05: /* bgtu */ | |
700 | case 0x06: /* bge */ | |
701 | case 0x07: /* ble */ | |
702 | case 0x08: /* bgeu */ | |
703 | case 0x09: /* bleu */ | |
704 | /* Do nothing. */ | |
705 | break; | |
706 | default: | |
707 | { | |
708 | /* Do nothing. */ | |
709 | break; | |
710 | } | |
711 | } | |
712 | } | |
713 | else | |
714 | { | |
715 | /* This is a Form 2 instruction. */ | |
716 | int opcode = (inst >> 12 & 0x3); | |
717 | switch (opcode) | |
718 | { | |
719 | case 0x00: /* inc */ | |
720 | case 0x01: /* dec */ | |
721 | case 0x02: /* gsr */ | |
722 | { | |
723 | int reg = (inst >> 8) & 0xf; | |
25ea693b | 724 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
725 | return -1; |
726 | } | |
727 | break; | |
728 | case 0x03: /* ssr */ | |
729 | { | |
730 | /* Do nothing until GDB learns about moxie's special | |
731 | registers. */ | |
732 | } | |
733 | break; | |
734 | default: | |
735 | /* Do nothing. */ | |
736 | break; | |
737 | } | |
738 | } | |
739 | } | |
740 | else | |
741 | { | |
742 | /* This is a Form 1 instruction. */ | |
743 | int opcode = inst >> 8; | |
744 | ||
745 | switch (opcode) | |
746 | { | |
747 | case 0x00: /* nop */ | |
748 | /* Do nothing. */ | |
749 | break; | |
750 | case 0x01: /* ldi.l (immediate) */ | |
751 | case 0x02: /* mov (register-to-register) */ | |
752 | { | |
753 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 754 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
755 | return -1; |
756 | } | |
757 | break; | |
758 | case 0x03: /* jsra */ | |
759 | { | |
760 | regcache_raw_read (regcache, | |
761 | MOXIE_SP_REGNUM, (gdb_byte *) & tmpu32); | |
762 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
763 | 4, byte_order); | |
25ea693b MM |
764 | if (record_full_arch_list_add_reg (regcache, MOXIE_FP_REGNUM) |
765 | || (record_full_arch_list_add_reg (regcache, | |
766 | MOXIE_SP_REGNUM)) | |
767 | || record_full_arch_list_add_mem (tmpu32 - 12, 12)) | |
451fa05e AG |
768 | return -1; |
769 | } | |
770 | break; | |
771 | case 0x04: /* ret */ | |
772 | { | |
25ea693b MM |
773 | if (record_full_arch_list_add_reg (regcache, MOXIE_FP_REGNUM) |
774 | || (record_full_arch_list_add_reg (regcache, | |
775 | MOXIE_SP_REGNUM))) | |
451fa05e AG |
776 | return -1; |
777 | } | |
778 | break; | |
779 | case 0x05: /* add.l */ | |
780 | { | |
781 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 782 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
783 | return -1; |
784 | } | |
785 | break; | |
786 | case 0x06: /* push */ | |
787 | { | |
788 | int reg = (inst >> 4) & 0xf; | |
789 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); | |
790 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
791 | 4, byte_order); | |
25ea693b MM |
792 | if (record_full_arch_list_add_reg (regcache, reg) |
793 | || record_full_arch_list_add_mem (tmpu32 - 4, 4)) | |
451fa05e AG |
794 | return -1; |
795 | } | |
796 | break; | |
797 | case 0x07: /* pop */ | |
798 | { | |
799 | int a = (inst >> 4) & 0xf; | |
800 | int b = inst & 0xf; | |
25ea693b MM |
801 | if (record_full_arch_list_add_reg (regcache, a) |
802 | || record_full_arch_list_add_reg (regcache, b)) | |
451fa05e AG |
803 | return -1; |
804 | } | |
805 | break; | |
806 | case 0x08: /* lda.l */ | |
807 | { | |
808 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 809 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
810 | return -1; |
811 | } | |
812 | break; | |
813 | case 0x09: /* sta.l */ | |
814 | { | |
815 | tmpu32 = (uint32_t) moxie_process_readu (addr+2, buf, | |
816 | 4, byte_order); | |
25ea693b | 817 | if (record_full_arch_list_add_mem (tmpu32, 4)) |
451fa05e AG |
818 | return -1; |
819 | } | |
820 | break; | |
821 | case 0x0a: /* ld.l (register indirect) */ | |
822 | { | |
823 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 824 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
825 | return -1; |
826 | } | |
827 | break; | |
828 | case 0x0b: /* st.l */ | |
829 | { | |
830 | int reg = (inst >> 4) & 0xf; | |
831 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); | |
832 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
833 | 4, byte_order); | |
25ea693b | 834 | if (record_full_arch_list_add_mem (tmpu32, 4)) |
451fa05e AG |
835 | return -1; |
836 | } | |
837 | break; | |
838 | case 0x0c: /* ldo.l */ | |
839 | { | |
840 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 841 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
842 | return -1; |
843 | } | |
844 | break; | |
845 | case 0x0d: /* sto.l */ | |
846 | { | |
847 | int reg = (inst >> 4) & 0xf; | |
6441e6db AG |
848 | uint32_t offset = (((int16_t) moxie_process_readu (addr+2, buf, 2, |
849 | byte_order)) << 16 ) >> 16; | |
451fa05e AG |
850 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); |
851 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
852 | 4, byte_order); | |
853 | tmpu32 += offset; | |
25ea693b | 854 | if (record_full_arch_list_add_mem (tmpu32, 4)) |
451fa05e AG |
855 | return -1; |
856 | } | |
857 | break; | |
858 | case 0x0e: /* cmp */ | |
859 | { | |
25ea693b | 860 | if (record_full_arch_list_add_reg (regcache, MOXIE_CC_REGNUM)) |
451fa05e AG |
861 | return -1; |
862 | } | |
863 | break; | |
6441e6db AG |
864 | case 0x0f: /* nop */ |
865 | { | |
866 | /* Do nothing. */ | |
867 | break; | |
868 | } | |
869 | case 0x10: /* sex.b */ | |
870 | case 0x11: /* sex.s */ | |
871 | case 0x12: /* zex.b */ | |
872 | case 0x13: /* zex.s */ | |
873 | case 0x14: /* umul.x */ | |
874 | case 0x15: /* mul.x */ | |
875 | { | |
876 | int reg = (inst >> 4) & 0xf; | |
877 | if (record_full_arch_list_add_reg (regcache, reg)) | |
878 | return -1; | |
879 | } | |
880 | break; | |
451fa05e AG |
881 | case 0x16: |
882 | case 0x17: | |
883 | case 0x18: | |
884 | { | |
885 | /* Do nothing. */ | |
886 | break; | |
887 | } | |
888 | case 0x19: /* jsr */ | |
889 | { | |
890 | regcache_raw_read (regcache, | |
891 | MOXIE_SP_REGNUM, (gdb_byte *) & tmpu32); | |
892 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
893 | 4, byte_order); | |
25ea693b MM |
894 | if (record_full_arch_list_add_reg (regcache, MOXIE_FP_REGNUM) |
895 | || (record_full_arch_list_add_reg (regcache, | |
896 | MOXIE_SP_REGNUM)) | |
897 | || record_full_arch_list_add_mem (tmpu32 - 12, 12)) | |
451fa05e AG |
898 | return -1; |
899 | } | |
900 | break; | |
901 | case 0x1a: /* jmpa */ | |
902 | { | |
903 | /* Do nothing. */ | |
904 | } | |
905 | break; | |
906 | case 0x1b: /* ldi.b (immediate) */ | |
907 | case 0x1c: /* ld.b (register indirect) */ | |
908 | case 0x1d: /* lda.b */ | |
909 | { | |
910 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 911 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
912 | return -1; |
913 | } | |
914 | break; | |
915 | case 0x1e: /* st.b */ | |
916 | { | |
917 | int reg = (inst >> 4) & 0xf; | |
918 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); | |
919 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
920 | 4, byte_order); | |
25ea693b | 921 | if (record_full_arch_list_add_mem (tmpu32, 1)) |
451fa05e AG |
922 | return -1; |
923 | } | |
924 | break; | |
925 | case 0x1f: /* sta.b */ | |
926 | { | |
948f8e3d | 927 | tmpu32 = moxie_process_readu (addr+2, buf, 4, byte_order); |
25ea693b | 928 | if (record_full_arch_list_add_mem (tmpu32, 1)) |
451fa05e AG |
929 | return -1; |
930 | } | |
931 | break; | |
932 | case 0x20: /* ldi.s (immediate) */ | |
933 | case 0x21: /* ld.s (register indirect) */ | |
934 | case 0x22: /* lda.s */ | |
935 | { | |
936 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 937 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
938 | return -1; |
939 | } | |
940 | break; | |
941 | case 0x23: /* st.s */ | |
942 | { | |
943 | int reg = (inst >> 4) & 0xf; | |
944 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); | |
945 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
946 | 4, byte_order); | |
25ea693b | 947 | if (record_full_arch_list_add_mem (tmpu32, 2)) |
451fa05e AG |
948 | return -1; |
949 | } | |
950 | break; | |
951 | case 0x24: /* sta.s */ | |
952 | { | |
948f8e3d | 953 | tmpu32 = moxie_process_readu (addr+2, buf, 4, byte_order); |
25ea693b | 954 | if (record_full_arch_list_add_mem (tmpu32, 2)) |
451fa05e AG |
955 | return -1; |
956 | } | |
957 | break; | |
958 | case 0x25: /* jmp */ | |
959 | { | |
960 | /* Do nothing. */ | |
961 | } | |
962 | break; | |
963 | case 0x26: /* and */ | |
964 | case 0x27: /* lshr */ | |
965 | case 0x28: /* ashl */ | |
6441e6db | 966 | case 0x29: /* sub */ |
451fa05e AG |
967 | case 0x2a: /* neg */ |
968 | case 0x2b: /* or */ | |
969 | case 0x2c: /* not */ | |
970 | case 0x2d: /* ashr */ | |
971 | case 0x2e: /* xor */ | |
6441e6db | 972 | case 0x2f: /* mul */ |
451fa05e AG |
973 | { |
974 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 975 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
976 | return -1; |
977 | } | |
978 | break; | |
979 | case 0x30: /* swi */ | |
980 | { | |
981 | /* We currently implement support for libgloss' | |
982 | system calls. */ | |
983 | ||
948f8e3d | 984 | int inum = moxie_process_readu (addr+2, buf, 4, byte_order); |
451fa05e AG |
985 | |
986 | switch (inum) | |
987 | { | |
988 | case 0x1: /* SYS_exit */ | |
989 | { | |
990 | /* Do nothing. */ | |
991 | } | |
992 | break; | |
993 | case 0x2: /* SYS_open */ | |
994 | { | |
25ea693b | 995 | if (record_full_arch_list_add_reg (regcache, RET1_REGNUM)) |
451fa05e AG |
996 | return -1; |
997 | } | |
998 | break; | |
999 | case 0x4: /* SYS_read */ | |
1000 | { | |
1001 | uint32_t length, ptr; | |
1002 | ||
1003 | /* Read buffer pointer is in $r1. */ | |
1004 | regcache_raw_read (regcache, 3, (gdb_byte *) & ptr); | |
1005 | ptr = extract_unsigned_integer ((gdb_byte *) & ptr, | |
1006 | 4, byte_order); | |
1007 | ||
025bb325 | 1008 | /* String length is at 0x12($fp). */ |
451fa05e AG |
1009 | regcache_raw_read (regcache, |
1010 | MOXIE_FP_REGNUM, (gdb_byte *) & tmpu32); | |
1011 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
1012 | 4, byte_order); | |
948f8e3d | 1013 | length = moxie_process_readu (tmpu32+20, buf, 4, byte_order); |
451fa05e | 1014 | |
25ea693b | 1015 | if (record_full_arch_list_add_mem (ptr, length)) |
451fa05e AG |
1016 | return -1; |
1017 | } | |
1018 | break; | |
1019 | case 0x5: /* SYS_write */ | |
1020 | { | |
25ea693b | 1021 | if (record_full_arch_list_add_reg (regcache, RET1_REGNUM)) |
451fa05e AG |
1022 | return -1; |
1023 | } | |
1024 | break; | |
1025 | default: | |
1026 | break; | |
1027 | } | |
1028 | } | |
1029 | break; | |
1030 | case 0x31: /* div.l */ | |
1031 | case 0x32: /* udiv.l */ | |
1032 | case 0x33: /* mod.l */ | |
1033 | case 0x34: /* umod.l */ | |
1034 | { | |
1035 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 1036 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
1037 | return -1; |
1038 | } | |
1039 | break; | |
1040 | case 0x35: /* brk */ | |
1041 | /* Do nothing. */ | |
1042 | break; | |
1043 | case 0x36: /* ldo.b */ | |
1044 | { | |
1045 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 1046 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
1047 | return -1; |
1048 | } | |
1049 | break; | |
1050 | case 0x37: /* sto.b */ | |
1051 | { | |
1052 | int reg = (inst >> 4) & 0xf; | |
6441e6db AG |
1053 | uint32_t offset = (((int16_t) moxie_process_readu (addr+2, buf, 2, |
1054 | byte_order)) << 16 ) >> 16; | |
451fa05e AG |
1055 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); |
1056 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
1057 | 4, byte_order); | |
1058 | tmpu32 += offset; | |
25ea693b | 1059 | if (record_full_arch_list_add_mem (tmpu32, 1)) |
451fa05e AG |
1060 | return -1; |
1061 | } | |
1062 | break; | |
1063 | case 0x38: /* ldo.s */ | |
1064 | { | |
1065 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 1066 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
1067 | return -1; |
1068 | } | |
1069 | break; | |
1070 | case 0x39: /* sto.s */ | |
1071 | { | |
1072 | int reg = (inst >> 4) & 0xf; | |
6441e6db AG |
1073 | uint32_t offset = (((int16_t) moxie_process_readu (addr+2, buf, 2, |
1074 | byte_order)) << 16 ) >> 16; | |
451fa05e AG |
1075 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); |
1076 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
1077 | 4, byte_order); | |
1078 | tmpu32 += offset; | |
25ea693b | 1079 | if (record_full_arch_list_add_mem (tmpu32, 2)) |
451fa05e AG |
1080 | return -1; |
1081 | } | |
1082 | break; | |
1083 | default: | |
1084 | /* Do nothing. */ | |
1085 | break; | |
1086 | } | |
1087 | } | |
1088 | ||
25ea693b | 1089 | if (record_full_arch_list_add_reg (regcache, MOXIE_PC_REGNUM)) |
451fa05e | 1090 | return -1; |
25ea693b | 1091 | if (record_full_arch_list_add_end ()) |
451fa05e AG |
1092 | return -1; |
1093 | return 0; | |
1094 | } | |
1095 | ||
d7066cce AG |
1096 | /* Allocate and initialize the moxie gdbarch object. */ |
1097 | ||
1098 | static struct gdbarch * | |
1099 | moxie_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1100 | { | |
1101 | struct gdbarch *gdbarch; | |
1102 | struct gdbarch_tdep *tdep; | |
1103 | ||
1104 | /* If there is already a candidate, use it. */ | |
1105 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1106 | if (arches != NULL) | |
1107 | return arches->gdbarch; | |
1108 | ||
1109 | /* Allocate space for the new architecture. */ | |
cdd238da | 1110 | tdep = XCNEW (struct gdbarch_tdep); |
d7066cce AG |
1111 | gdbarch = gdbarch_alloc (&info, tdep); |
1112 | ||
53375380 PA |
1113 | set_gdbarch_wchar_bit (gdbarch, 32); |
1114 | set_gdbarch_wchar_signed (gdbarch, 0); | |
1115 | ||
d7066cce AG |
1116 | set_gdbarch_read_pc (gdbarch, moxie_read_pc); |
1117 | set_gdbarch_write_pc (gdbarch, moxie_write_pc); | |
1118 | set_gdbarch_unwind_sp (gdbarch, moxie_unwind_sp); | |
1119 | ||
1120 | set_gdbarch_num_regs (gdbarch, MOXIE_NUM_REGS); | |
1121 | set_gdbarch_sp_regnum (gdbarch, MOXIE_SP_REGNUM); | |
451fa05e | 1122 | set_gdbarch_pc_regnum (gdbarch, MOXIE_PC_REGNUM); |
d7066cce AG |
1123 | set_gdbarch_register_name (gdbarch, moxie_register_name); |
1124 | set_gdbarch_register_type (gdbarch, moxie_register_type); | |
1125 | ||
1126 | set_gdbarch_return_value (gdbarch, moxie_return_value); | |
1127 | ||
1128 | set_gdbarch_skip_prologue (gdbarch, moxie_skip_prologue); | |
1129 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
04180708 YQ |
1130 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1131 | moxie_breakpoint::kind_from_pc); | |
1132 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1133 | moxie_breakpoint::bp_from_kind); | |
d7066cce AG |
1134 | set_gdbarch_frame_align (gdbarch, moxie_frame_align); |
1135 | ||
1136 | frame_base_set_default (gdbarch, &moxie_frame_base); | |
1137 | ||
1138 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
1139 | stack address must match the SP value returned by | |
1140 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
1141 | set_gdbarch_dummy_id (gdbarch, moxie_dummy_id); | |
1142 | ||
1143 | set_gdbarch_unwind_pc (gdbarch, moxie_unwind_pc); | |
1144 | ||
d7066cce AG |
1145 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1146 | gdbarch_init_osabi (info, gdbarch); | |
1147 | ||
1148 | /* Hook in the default unwinders. */ | |
1149 | frame_unwind_append_unwinder (gdbarch, &moxie_frame_unwind); | |
1150 | ||
6ed1ff02 AG |
1151 | /* Single stepping. */ |
1152 | set_gdbarch_software_single_step (gdbarch, moxie_software_single_step); | |
1153 | ||
d7066cce AG |
1154 | /* Support simple overlay manager. */ |
1155 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
1156 | ||
451fa05e AG |
1157 | /* Support reverse debugging. */ |
1158 | set_gdbarch_process_record (gdbarch, moxie_process_record); | |
1159 | ||
d7066cce AG |
1160 | return gdbarch; |
1161 | } | |
1162 | ||
1163 | /* Register this machine's init routine. */ | |
1164 | ||
1165 | void | |
1166 | _initialize_moxie_tdep (void) | |
1167 | { | |
1168 | register_gdbarch_init (bfd_arch_moxie, moxie_gdbarch_init); | |
1169 | } |