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d7066cce AG |
1 | /* Target-dependent code for Moxie. |
2 | ||
e2882c85 | 3 | Copyright (C) 2009-2018 Free Software Foundation, Inc. |
d7066cce AG |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "frame-unwind.h" | |
23 | #include "frame-base.h" | |
24 | #include "symtab.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcmd.h" | |
27 | #include "gdbcore.h" | |
d7066cce AG |
28 | #include "value.h" |
29 | #include "inferior.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
32 | #include "osabi.h" | |
33 | #include "language.h" | |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
37 | #include "dis-asm.h" | |
451fa05e | 38 | #include "record.h" |
d02ed0bb | 39 | #include "record-full.h" |
d7066cce | 40 | |
d7066cce | 41 | #include "moxie-tdep.h" |
325fac50 | 42 | #include <algorithm> |
d7066cce | 43 | |
d7066cce AG |
44 | /* Use an invalid address value as 'not available' marker. */ |
45 | enum { REG_UNAVAIL = (CORE_ADDR) -1 }; | |
46 | ||
47 | struct moxie_frame_cache | |
48 | { | |
49 | /* Base address. */ | |
50 | CORE_ADDR base; | |
51 | CORE_ADDR pc; | |
52 | LONGEST framesize; | |
53 | CORE_ADDR saved_regs[MOXIE_NUM_REGS]; | |
54 | CORE_ADDR saved_sp; | |
55 | }; | |
56 | ||
57 | /* Implement the "frame_align" gdbarch method. */ | |
58 | ||
59 | static CORE_ADDR | |
60 | moxie_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
61 | { | |
62 | /* Align to the size of an instruction (so that they can safely be | |
63 | pushed onto the stack. */ | |
64 | return sp & ~1; | |
65 | } | |
66 | ||
04180708 | 67 | constexpr gdb_byte moxie_break_insn[] = { 0x35, 0x00 }; |
d7066cce | 68 | |
04180708 | 69 | typedef BP_MANIPULATION (moxie_break_insn) moxie_breakpoint; |
d7066cce AG |
70 | |
71 | /* Moxie register names. */ | |
72 | ||
a121b7c1 | 73 | static const char *moxie_register_names[] = { |
d7066cce AG |
74 | "$fp", "$sp", "$r0", "$r1", "$r2", |
75 | "$r3", "$r4", "$r5", "$r6", "$r7", | |
76 | "$r8", "$r9", "$r10", "$r11", "$r12", | |
77 | "$r13", "$pc", "$cc" }; | |
78 | ||
79 | /* Implement the "register_name" gdbarch method. */ | |
80 | ||
81 | static const char * | |
82 | moxie_register_name (struct gdbarch *gdbarch, int reg_nr) | |
83 | { | |
84 | if (reg_nr < 0) | |
85 | return NULL; | |
86 | if (reg_nr >= MOXIE_NUM_REGS) | |
87 | return NULL; | |
88 | return moxie_register_names[reg_nr]; | |
89 | } | |
90 | ||
91 | /* Implement the "register_type" gdbarch method. */ | |
92 | ||
93 | static struct type * | |
94 | moxie_register_type (struct gdbarch *gdbarch, int reg_nr) | |
95 | { | |
96 | if (reg_nr == MOXIE_PC_REGNUM) | |
97 | return builtin_type (gdbarch)->builtin_func_ptr; | |
98 | else if (reg_nr == MOXIE_SP_REGNUM || reg_nr == MOXIE_FP_REGNUM) | |
99 | return builtin_type (gdbarch)->builtin_data_ptr; | |
100 | else | |
df4df182 | 101 | return builtin_type (gdbarch)->builtin_int32; |
d7066cce AG |
102 | } |
103 | ||
104 | /* Write into appropriate registers a function return value | |
105 | of type TYPE, given in virtual format. */ | |
106 | ||
107 | static void | |
108 | moxie_store_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 109 | const gdb_byte *valbuf) |
d7066cce | 110 | { |
ac7936df | 111 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 112 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d7066cce AG |
113 | CORE_ADDR regval; |
114 | int len = TYPE_LENGTH (type); | |
115 | ||
116 | /* Things always get returned in RET1_REGNUM, RET2_REGNUM. */ | |
e17a4113 | 117 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d7066cce AG |
118 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
119 | if (len > 4) | |
120 | { | |
7c543f7b | 121 | regval = extract_unsigned_integer (valbuf + 4, len - 4, byte_order); |
d7066cce AG |
122 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
123 | } | |
124 | } | |
125 | ||
126 | /* Decode the instructions within the given address range. Decide | |
127 | when we must have reached the end of the function prologue. If a | |
128 | frame_info pointer is provided, fill in its saved_regs etc. | |
129 | ||
130 | Returns the address of the first instruction after the prologue. */ | |
131 | ||
132 | static CORE_ADDR | |
133 | moxie_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR end_addr, | |
99f75275 AG |
134 | struct moxie_frame_cache *cache, |
135 | struct gdbarch *gdbarch) | |
d7066cce | 136 | { |
e17a4113 | 137 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d7066cce AG |
138 | CORE_ADDR next_addr; |
139 | ULONGEST inst, inst2; | |
140 | LONGEST offset; | |
141 | int regnum; | |
142 | ||
143 | /* Record where the jsra instruction saves the PC and FP. */ | |
144 | cache->saved_regs[MOXIE_PC_REGNUM] = -4; | |
145 | cache->saved_regs[MOXIE_FP_REGNUM] = 0; | |
146 | cache->framesize = 0; | |
147 | ||
148 | if (start_addr >= end_addr) | |
149 | return end_addr; | |
150 | ||
151 | for (next_addr = start_addr; next_addr < end_addr; ) | |
152 | { | |
e17a4113 | 153 | inst = read_memory_unsigned_integer (next_addr, 2, byte_order); |
d7066cce | 154 | |
5152ff90 AG |
155 | /* Match "push $sp $rN" where N is between 0 and 13 inclusive. */ |
156 | if (inst >= 0x0612 && inst <= 0x061f) | |
d7066cce AG |
157 | { |
158 | regnum = inst & 0x000f; | |
159 | cache->framesize += 4; | |
160 | cache->saved_regs[regnum] = cache->framesize; | |
161 | next_addr += 2; | |
162 | } | |
4ee73e90 AG |
163 | else |
164 | break; | |
ce0bf488 | 165 | } |
d7066cce | 166 | |
ce0bf488 | 167 | inst = read_memory_unsigned_integer (next_addr, 2, byte_order); |
d7066cce | 168 | |
ce0bf488 AG |
169 | /* Optional stack allocation for args and local vars <= 4 |
170 | byte. */ | |
5152ff90 | 171 | if (inst == 0x01e0) /* ldi.l $r12, X */ |
ce0bf488 AG |
172 | { |
173 | offset = read_memory_integer (next_addr + 2, 4, byte_order); | |
174 | inst2 = read_memory_unsigned_integer (next_addr + 6, 2, byte_order); | |
175 | ||
5152ff90 | 176 | if (inst2 == 0x291e) /* sub.l $sp, $r12 */ |
ce0bf488 AG |
177 | { |
178 | cache->framesize += offset; | |
179 | } | |
180 | ||
181 | return (next_addr + 8); | |
182 | } | |
5152ff90 | 183 | else if ((inst & 0xff00) == 0x9100) /* dec $sp, X */ |
ce0bf488 AG |
184 | { |
185 | cache->framesize += (inst & 0x00ff); | |
186 | next_addr += 2; | |
d7066cce | 187 | |
ce0bf488 AG |
188 | while (next_addr < end_addr) |
189 | { | |
190 | inst = read_memory_unsigned_integer (next_addr, 2, byte_order); | |
5152ff90 | 191 | if ((inst & 0xff00) != 0x9100) /* no more dec $sp, X */ |
ce0bf488 AG |
192 | break; |
193 | cache->framesize += (inst & 0x00ff); | |
194 | next_addr += 2; | |
d7066cce | 195 | } |
d7066cce AG |
196 | } |
197 | ||
198 | return next_addr; | |
199 | } | |
200 | ||
201 | /* Find the end of function prologue. */ | |
202 | ||
203 | static CORE_ADDR | |
204 | moxie_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
205 | { | |
206 | CORE_ADDR func_addr = 0, func_end = 0; | |
2c02bd72 | 207 | const char *func_name; |
d7066cce AG |
208 | |
209 | /* See if we can determine the end of the prologue via the symbol table. | |
210 | If so, then return either PC, or the PC after the prologue, whichever | |
211 | is greater. */ | |
212 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) | |
213 | { | |
d80b854b UW |
214 | CORE_ADDR post_prologue_pc |
215 | = skip_prologue_using_sal (gdbarch, func_addr); | |
d7066cce | 216 | if (post_prologue_pc != 0) |
325fac50 | 217 | return std::max (pc, post_prologue_pc); |
d7066cce AG |
218 | else |
219 | { | |
220 | /* Can't determine prologue from the symbol table, need to examine | |
221 | instructions. */ | |
222 | struct symtab_and_line sal; | |
223 | struct symbol *sym; | |
224 | struct moxie_frame_cache cache; | |
225 | CORE_ADDR plg_end; | |
226 | ||
227 | memset (&cache, 0, sizeof cache); | |
228 | ||
229 | plg_end = moxie_analyze_prologue (func_addr, | |
99f75275 | 230 | func_end, &cache, gdbarch); |
d7066cce | 231 | /* Found a function. */ |
835a09d9 | 232 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL).symbol; |
d7066cce | 233 | /* Don't use line number debug info for assembly source |
025bb325 | 234 | files. */ |
d7066cce AG |
235 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
236 | { | |
237 | sal = find_pc_line (func_addr, 0); | |
238 | if (sal.end && sal.end < func_end) | |
239 | { | |
240 | /* Found a line number, use it as end of | |
241 | prologue. */ | |
242 | return sal.end; | |
243 | } | |
244 | } | |
245 | /* No useable line symbol. Use result of prologue parsing | |
246 | method. */ | |
247 | return plg_end; | |
248 | } | |
249 | } | |
250 | ||
251 | /* No function symbol -- just return the PC. */ | |
252 | return (CORE_ADDR) pc; | |
253 | } | |
254 | ||
255 | struct moxie_unwind_cache | |
256 | { | |
257 | /* The previous frame's inner most stack address. Used as this | |
258 | frame ID's stack_addr. */ | |
259 | CORE_ADDR prev_sp; | |
260 | /* The frame's base, optionally used by the high-level debug info. */ | |
261 | CORE_ADDR base; | |
262 | int size; | |
263 | /* How far the SP and r13 (FP) have been offset from the start of | |
264 | the stack frame (as defined by the previous frame's stack | |
265 | pointer). */ | |
266 | LONGEST sp_offset; | |
267 | LONGEST r13_offset; | |
268 | int uses_frame; | |
269 | /* Table indicating the location of each and every register. */ | |
270 | struct trad_frame_saved_reg *saved_regs; | |
271 | }; | |
272 | ||
6ed1ff02 AG |
273 | /* Read an unsigned integer from the inferior, and adjust |
274 | endianess. */ | |
275 | static ULONGEST | |
276 | moxie_process_readu (CORE_ADDR addr, gdb_byte *buf, | |
277 | int length, enum bfd_endian byte_order) | |
278 | { | |
279 | if (target_read_memory (addr, buf, length)) | |
280 | { | |
281 | if (record_debug) | |
282 | printf_unfiltered (_("Process record: error reading memory at " | |
283 | "addr 0x%s len = %d.\n"), | |
284 | paddress (target_gdbarch (), addr), length); | |
285 | return -1; | |
286 | } | |
287 | ||
288 | return extract_unsigned_integer (buf, length, byte_order); | |
289 | } | |
290 | ||
291 | ||
292 | /* Helper macro to extract the signed 10-bit offset from a 16-bit | |
293 | branch instruction. */ | |
294 | #define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1) | |
295 | ||
296 | /* Insert a single step breakpoint. */ | |
297 | ||
a0ff9e1a | 298 | static std::vector<CORE_ADDR> |
f5ea389a | 299 | moxie_software_single_step (struct regcache *regcache) |
6ed1ff02 | 300 | { |
ac7936df | 301 | struct gdbarch *gdbarch = regcache->arch (); |
6ed1ff02 AG |
302 | CORE_ADDR addr; |
303 | gdb_byte buf[4]; | |
304 | uint16_t inst; | |
305 | uint32_t tmpu32; | |
306 | ULONGEST fp; | |
307 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
a0ff9e1a | 308 | std::vector<CORE_ADDR> next_pcs; |
6ed1ff02 | 309 | |
a8f34182 | 310 | addr = regcache_read_pc (regcache); |
6ed1ff02 AG |
311 | |
312 | inst = (uint16_t) moxie_process_readu (addr, buf, 2, byte_order); | |
313 | ||
314 | /* Decode instruction. */ | |
315 | if (inst & (1 << 15)) | |
316 | { | |
317 | if (inst & (1 << 14)) | |
318 | { | |
319 | /* This is a Form 3 instruction. */ | |
320 | int opcode = (inst >> 10 & 0xf); | |
321 | ||
322 | switch (opcode) | |
323 | { | |
324 | case 0x00: /* beq */ | |
325 | case 0x01: /* bne */ | |
326 | case 0x02: /* blt */ | |
327 | case 0x03: /* bgt */ | |
328 | case 0x04: /* bltu */ | |
329 | case 0x05: /* bgtu */ | |
330 | case 0x06: /* bge */ | |
331 | case 0x07: /* ble */ | |
332 | case 0x08: /* bgeu */ | |
333 | case 0x09: /* bleu */ | |
334 | /* Insert breaks on both branches, because we can't currently tell | |
335 | which way things will go. */ | |
a0ff9e1a SM |
336 | next_pcs.push_back (addr + 2); |
337 | next_pcs.push_back (addr + 2 + INST2OFFSET(inst)); | |
6ed1ff02 AG |
338 | break; |
339 | default: | |
340 | { | |
341 | /* Do nothing. */ | |
342 | break; | |
343 | } | |
344 | } | |
345 | } | |
346 | else | |
347 | { | |
348 | /* This is a Form 2 instruction. They are all 16 bits. */ | |
a0ff9e1a | 349 | next_pcs.push_back (addr + 2); |
6ed1ff02 AG |
350 | } |
351 | } | |
352 | else | |
353 | { | |
354 | /* This is a Form 1 instruction. */ | |
355 | int opcode = inst >> 8; | |
356 | ||
357 | switch (opcode) | |
358 | { | |
359 | /* 16-bit instructions. */ | |
6441e6db | 360 | case 0x00: /* bad */ |
6ed1ff02 AG |
361 | case 0x02: /* mov (register-to-register) */ |
362 | case 0x05: /* add.l */ | |
363 | case 0x06: /* push */ | |
364 | case 0x07: /* pop */ | |
365 | case 0x0a: /* ld.l (register indirect) */ | |
366 | case 0x0b: /* st.l */ | |
367 | case 0x0e: /* cmp */ | |
6441e6db AG |
368 | case 0x0f: /* nop */ |
369 | case 0x10: /* sex.b */ | |
370 | case 0x11: /* sex.s */ | |
371 | case 0x12: /* zex.b */ | |
372 | case 0x13: /* zex.s */ | |
373 | case 0x14: /* umul.x */ | |
374 | case 0x15: /* mul.x */ | |
6ed1ff02 AG |
375 | case 0x16: |
376 | case 0x17: | |
377 | case 0x18: | |
378 | case 0x1c: /* ld.b (register indirect) */ | |
379 | case 0x1e: /* st.b */ | |
380 | case 0x21: /* ld.s (register indirect) */ | |
381 | case 0x23: /* st.s */ | |
382 | case 0x26: /* and */ | |
383 | case 0x27: /* lshr */ | |
384 | case 0x28: /* ashl */ | |
385 | case 0x29: /* sub.l */ | |
386 | case 0x2a: /* neg */ | |
387 | case 0x2b: /* or */ | |
388 | case 0x2c: /* not */ | |
389 | case 0x2d: /* ashr */ | |
390 | case 0x2e: /* xor */ | |
391 | case 0x2f: /* mul.l */ | |
392 | case 0x31: /* div.l */ | |
393 | case 0x32: /* udiv.l */ | |
394 | case 0x33: /* mod.l */ | |
395 | case 0x34: /* umod.l */ | |
a0ff9e1a | 396 | next_pcs.push_back (addr + 2); |
6ed1ff02 AG |
397 | break; |
398 | ||
6441e6db AG |
399 | /* 32-bit instructions. */ |
400 | case 0x0c: /* ldo.l */ | |
401 | case 0x0d: /* sto.l */ | |
402 | case 0x36: /* ldo.b */ | |
403 | case 0x37: /* sto.b */ | |
404 | case 0x38: /* ldo.s */ | |
405 | case 0x39: /* sto.s */ | |
a0ff9e1a | 406 | next_pcs.push_back (addr + 4); |
6441e6db AG |
407 | break; |
408 | ||
6ed1ff02 AG |
409 | /* 48-bit instructions. */ |
410 | case 0x01: /* ldi.l (immediate) */ | |
411 | case 0x08: /* lda.l */ | |
412 | case 0x09: /* sta.l */ | |
6ed1ff02 AG |
413 | case 0x1b: /* ldi.b (immediate) */ |
414 | case 0x1d: /* lda.b */ | |
415 | case 0x1f: /* sta.b */ | |
416 | case 0x20: /* ldi.s (immediate) */ | |
417 | case 0x22: /* lda.s */ | |
418 | case 0x24: /* sta.s */ | |
a0ff9e1a | 419 | next_pcs.push_back (addr + 6); |
6ed1ff02 AG |
420 | break; |
421 | ||
422 | /* Control flow instructions. */ | |
423 | case 0x03: /* jsra */ | |
424 | case 0x1a: /* jmpa */ | |
a0ff9e1a SM |
425 | next_pcs.push_back (moxie_process_readu (addr + 2, buf, 4, |
426 | byte_order)); | |
6ed1ff02 AG |
427 | break; |
428 | ||
429 | case 0x04: /* ret */ | |
430 | regcache_cooked_read_unsigned (regcache, MOXIE_FP_REGNUM, &fp); | |
a0ff9e1a | 431 | next_pcs.push_back (moxie_process_readu (fp + 4, buf, 4, byte_order)); |
6ed1ff02 AG |
432 | break; |
433 | ||
434 | case 0x19: /* jsr */ | |
435 | case 0x25: /* jmp */ | |
436 | regcache_raw_read (regcache, | |
437 | (inst >> 4) & 0xf, (gdb_byte *) & tmpu32); | |
a0ff9e1a | 438 | next_pcs.push_back (tmpu32); |
6ed1ff02 AG |
439 | break; |
440 | ||
441 | case 0x30: /* swi */ | |
442 | case 0x35: /* brk */ | |
443 | /* Unsupported, for now. */ | |
444 | break; | |
445 | } | |
446 | } | |
447 | ||
93f9a11f | 448 | return next_pcs; |
6ed1ff02 AG |
449 | } |
450 | ||
451fa05e | 451 | /* Implement the "unwind_sp" gdbarch method. */ |
d7066cce AG |
452 | |
453 | static CORE_ADDR | |
454 | moxie_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
455 | { | |
456 | return frame_unwind_register_unsigned (next_frame, MOXIE_SP_REGNUM); | |
457 | } | |
458 | ||
459 | /* Given a return value in `regbuf' with a type `valtype', | |
460 | extract and copy its value into `valbuf'. */ | |
461 | ||
462 | static void | |
463 | moxie_extract_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 464 | gdb_byte *dst) |
d7066cce | 465 | { |
ac7936df | 466 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 467 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d7066cce AG |
468 | int len = TYPE_LENGTH (type); |
469 | ULONGEST tmp; | |
470 | ||
471 | /* By using store_unsigned_integer we avoid having to do | |
472 | anything special for small big-endian values. */ | |
473 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
7c543f7b | 474 | store_unsigned_integer (dst, (len > 4 ? len - 4 : len), byte_order, tmp); |
d7066cce AG |
475 | |
476 | /* Ignore return values more than 8 bytes in size because the moxie | |
477 | returns anything more than 8 bytes in the stack. */ | |
478 | if (len > 4) | |
479 | { | |
480 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
7c543f7b | 481 | store_unsigned_integer (dst + len - 4, 4, byte_order, tmp); |
d7066cce AG |
482 | } |
483 | } | |
484 | ||
485 | /* Implement the "return_value" gdbarch method. */ | |
486 | ||
487 | static enum return_value_convention | |
6a3a010b | 488 | moxie_return_value (struct gdbarch *gdbarch, struct value *function, |
d7066cce AG |
489 | struct type *valtype, struct regcache *regcache, |
490 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
491 | { | |
492 | if (TYPE_LENGTH (valtype) > 8) | |
493 | return RETURN_VALUE_STRUCT_CONVENTION; | |
494 | else | |
495 | { | |
496 | if (readbuf != NULL) | |
497 | moxie_extract_return_value (valtype, regcache, readbuf); | |
498 | if (writebuf != NULL) | |
499 | moxie_store_return_value (valtype, regcache, writebuf); | |
500 | return RETURN_VALUE_REGISTER_CONVENTION; | |
501 | } | |
502 | } | |
503 | ||
504 | /* Allocate and initialize a moxie_frame_cache object. */ | |
505 | ||
506 | static struct moxie_frame_cache * | |
507 | moxie_alloc_frame_cache (void) | |
508 | { | |
509 | struct moxie_frame_cache *cache; | |
510 | int i; | |
511 | ||
512 | cache = FRAME_OBSTACK_ZALLOC (struct moxie_frame_cache); | |
513 | ||
514 | cache->base = 0; | |
515 | cache->saved_sp = 0; | |
516 | cache->pc = 0; | |
517 | cache->framesize = 0; | |
518 | for (i = 0; i < MOXIE_NUM_REGS; ++i) | |
519 | cache->saved_regs[i] = REG_UNAVAIL; | |
520 | ||
521 | return cache; | |
522 | } | |
523 | ||
524 | /* Populate a moxie_frame_cache object for this_frame. */ | |
525 | ||
526 | static struct moxie_frame_cache * | |
527 | moxie_frame_cache (struct frame_info *this_frame, void **this_cache) | |
528 | { | |
529 | struct moxie_frame_cache *cache; | |
530 | CORE_ADDR current_pc; | |
531 | int i; | |
532 | ||
533 | if (*this_cache) | |
19ba03f4 | 534 | return (struct moxie_frame_cache *) *this_cache; |
d7066cce AG |
535 | |
536 | cache = moxie_alloc_frame_cache (); | |
537 | *this_cache = cache; | |
538 | ||
539 | cache->base = get_frame_register_unsigned (this_frame, MOXIE_FP_REGNUM); | |
540 | if (cache->base == 0) | |
541 | return cache; | |
542 | ||
543 | cache->pc = get_frame_func (this_frame); | |
544 | current_pc = get_frame_pc (this_frame); | |
545 | if (cache->pc) | |
99f75275 AG |
546 | { |
547 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
548 | moxie_analyze_prologue (cache->pc, current_pc, cache, gdbarch); | |
549 | } | |
d7066cce AG |
550 | |
551 | cache->saved_sp = cache->base - cache->framesize; | |
552 | ||
553 | for (i = 0; i < MOXIE_NUM_REGS; ++i) | |
554 | if (cache->saved_regs[i] != REG_UNAVAIL) | |
555 | cache->saved_regs[i] = cache->base - cache->saved_regs[i]; | |
556 | ||
557 | return cache; | |
558 | } | |
559 | ||
560 | /* Implement the "unwind_pc" gdbarch method. */ | |
561 | ||
562 | static CORE_ADDR | |
563 | moxie_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
564 | { | |
565 | return frame_unwind_register_unsigned (next_frame, MOXIE_PC_REGNUM); | |
566 | } | |
567 | ||
568 | /* Given a GDB frame, determine the address of the calling function's | |
569 | frame. This will be used to create a new GDB frame struct. */ | |
570 | ||
571 | static void | |
572 | moxie_frame_this_id (struct frame_info *this_frame, | |
573 | void **this_prologue_cache, struct frame_id *this_id) | |
574 | { | |
575 | struct moxie_frame_cache *cache = moxie_frame_cache (this_frame, | |
576 | this_prologue_cache); | |
577 | ||
578 | /* This marks the outermost frame. */ | |
579 | if (cache->base == 0) | |
580 | return; | |
581 | ||
582 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
583 | } | |
584 | ||
585 | /* Get the value of register regnum in the previous stack frame. */ | |
586 | ||
587 | static struct value * | |
588 | moxie_frame_prev_register (struct frame_info *this_frame, | |
589 | void **this_prologue_cache, int regnum) | |
590 | { | |
591 | struct moxie_frame_cache *cache = moxie_frame_cache (this_frame, | |
592 | this_prologue_cache); | |
593 | ||
594 | gdb_assert (regnum >= 0); | |
595 | ||
596 | if (regnum == MOXIE_SP_REGNUM && cache->saved_sp) | |
597 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); | |
598 | ||
599 | if (regnum < MOXIE_NUM_REGS && cache->saved_regs[regnum] != REG_UNAVAIL) | |
600 | return frame_unwind_got_memory (this_frame, regnum, | |
601 | cache->saved_regs[regnum]); | |
602 | ||
603 | return frame_unwind_got_register (this_frame, regnum, regnum); | |
604 | } | |
605 | ||
606 | static const struct frame_unwind moxie_frame_unwind = { | |
607 | NORMAL_FRAME, | |
8fbca658 | 608 | default_frame_unwind_stop_reason, |
d7066cce AG |
609 | moxie_frame_this_id, |
610 | moxie_frame_prev_register, | |
611 | NULL, | |
612 | default_frame_sniffer | |
613 | }; | |
614 | ||
615 | /* Return the base address of this_frame. */ | |
616 | ||
617 | static CORE_ADDR | |
618 | moxie_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
619 | { | |
620 | struct moxie_frame_cache *cache = moxie_frame_cache (this_frame, | |
621 | this_cache); | |
622 | ||
623 | return cache->base; | |
624 | } | |
625 | ||
626 | static const struct frame_base moxie_frame_base = { | |
627 | &moxie_frame_unwind, | |
628 | moxie_frame_base_address, | |
629 | moxie_frame_base_address, | |
630 | moxie_frame_base_address | |
631 | }; | |
632 | ||
633 | static struct frame_id | |
634 | moxie_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
635 | { | |
636 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, MOXIE_SP_REGNUM); | |
637 | ||
638 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
639 | } | |
640 | ||
451fa05e AG |
641 | /* Parse the current instruction and record the values of the registers and |
642 | memory that will be changed in current instruction to "record_arch_list". | |
025bb325 | 643 | Return -1 if something wrong. */ |
451fa05e | 644 | |
693be288 | 645 | static int |
451fa05e AG |
646 | moxie_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
647 | CORE_ADDR addr) | |
648 | { | |
649 | gdb_byte buf[4]; | |
650 | uint16_t inst; | |
651 | uint32_t tmpu32; | |
652 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
653 | ||
654 | if (record_debug > 1) | |
655 | fprintf_unfiltered (gdb_stdlog, "Process record: moxie_process_record " | |
656 | "addr = 0x%s\n", | |
f5656ead | 657 | paddress (target_gdbarch (), addr)); |
451fa05e AG |
658 | |
659 | inst = (uint16_t) moxie_process_readu (addr, buf, 2, byte_order); | |
660 | ||
661 | /* Decode instruction. */ | |
662 | if (inst & (1 << 15)) | |
663 | { | |
664 | if (inst & (1 << 14)) | |
665 | { | |
666 | /* This is a Form 3 instruction. */ | |
667 | int opcode = (inst >> 10 & 0xf); | |
668 | ||
669 | switch (opcode) | |
670 | { | |
671 | case 0x00: /* beq */ | |
672 | case 0x01: /* bne */ | |
673 | case 0x02: /* blt */ | |
674 | case 0x03: /* bgt */ | |
675 | case 0x04: /* bltu */ | |
676 | case 0x05: /* bgtu */ | |
677 | case 0x06: /* bge */ | |
678 | case 0x07: /* ble */ | |
679 | case 0x08: /* bgeu */ | |
680 | case 0x09: /* bleu */ | |
681 | /* Do nothing. */ | |
682 | break; | |
683 | default: | |
684 | { | |
685 | /* Do nothing. */ | |
686 | break; | |
687 | } | |
688 | } | |
689 | } | |
690 | else | |
691 | { | |
692 | /* This is a Form 2 instruction. */ | |
693 | int opcode = (inst >> 12 & 0x3); | |
694 | switch (opcode) | |
695 | { | |
696 | case 0x00: /* inc */ | |
697 | case 0x01: /* dec */ | |
698 | case 0x02: /* gsr */ | |
699 | { | |
700 | int reg = (inst >> 8) & 0xf; | |
25ea693b | 701 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
702 | return -1; |
703 | } | |
704 | break; | |
705 | case 0x03: /* ssr */ | |
706 | { | |
707 | /* Do nothing until GDB learns about moxie's special | |
708 | registers. */ | |
709 | } | |
710 | break; | |
711 | default: | |
712 | /* Do nothing. */ | |
713 | break; | |
714 | } | |
715 | } | |
716 | } | |
717 | else | |
718 | { | |
719 | /* This is a Form 1 instruction. */ | |
720 | int opcode = inst >> 8; | |
721 | ||
722 | switch (opcode) | |
723 | { | |
724 | case 0x00: /* nop */ | |
725 | /* Do nothing. */ | |
726 | break; | |
727 | case 0x01: /* ldi.l (immediate) */ | |
728 | case 0x02: /* mov (register-to-register) */ | |
729 | { | |
730 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 731 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
732 | return -1; |
733 | } | |
734 | break; | |
735 | case 0x03: /* jsra */ | |
736 | { | |
737 | regcache_raw_read (regcache, | |
738 | MOXIE_SP_REGNUM, (gdb_byte *) & tmpu32); | |
739 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
740 | 4, byte_order); | |
25ea693b MM |
741 | if (record_full_arch_list_add_reg (regcache, MOXIE_FP_REGNUM) |
742 | || (record_full_arch_list_add_reg (regcache, | |
743 | MOXIE_SP_REGNUM)) | |
744 | || record_full_arch_list_add_mem (tmpu32 - 12, 12)) | |
451fa05e AG |
745 | return -1; |
746 | } | |
747 | break; | |
748 | case 0x04: /* ret */ | |
749 | { | |
25ea693b MM |
750 | if (record_full_arch_list_add_reg (regcache, MOXIE_FP_REGNUM) |
751 | || (record_full_arch_list_add_reg (regcache, | |
752 | MOXIE_SP_REGNUM))) | |
451fa05e AG |
753 | return -1; |
754 | } | |
755 | break; | |
756 | case 0x05: /* add.l */ | |
757 | { | |
758 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 759 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
760 | return -1; |
761 | } | |
762 | break; | |
763 | case 0x06: /* push */ | |
764 | { | |
765 | int reg = (inst >> 4) & 0xf; | |
766 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); | |
767 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
768 | 4, byte_order); | |
25ea693b MM |
769 | if (record_full_arch_list_add_reg (regcache, reg) |
770 | || record_full_arch_list_add_mem (tmpu32 - 4, 4)) | |
451fa05e AG |
771 | return -1; |
772 | } | |
773 | break; | |
774 | case 0x07: /* pop */ | |
775 | { | |
776 | int a = (inst >> 4) & 0xf; | |
777 | int b = inst & 0xf; | |
25ea693b MM |
778 | if (record_full_arch_list_add_reg (regcache, a) |
779 | || record_full_arch_list_add_reg (regcache, b)) | |
451fa05e AG |
780 | return -1; |
781 | } | |
782 | break; | |
783 | case 0x08: /* lda.l */ | |
784 | { | |
785 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 786 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
787 | return -1; |
788 | } | |
789 | break; | |
790 | case 0x09: /* sta.l */ | |
791 | { | |
792 | tmpu32 = (uint32_t) moxie_process_readu (addr+2, buf, | |
793 | 4, byte_order); | |
25ea693b | 794 | if (record_full_arch_list_add_mem (tmpu32, 4)) |
451fa05e AG |
795 | return -1; |
796 | } | |
797 | break; | |
798 | case 0x0a: /* ld.l (register indirect) */ | |
799 | { | |
800 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 801 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
802 | return -1; |
803 | } | |
804 | break; | |
805 | case 0x0b: /* st.l */ | |
806 | { | |
807 | int reg = (inst >> 4) & 0xf; | |
808 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); | |
809 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
810 | 4, byte_order); | |
25ea693b | 811 | if (record_full_arch_list_add_mem (tmpu32, 4)) |
451fa05e AG |
812 | return -1; |
813 | } | |
814 | break; | |
815 | case 0x0c: /* ldo.l */ | |
816 | { | |
817 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 818 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
819 | return -1; |
820 | } | |
821 | break; | |
822 | case 0x0d: /* sto.l */ | |
823 | { | |
824 | int reg = (inst >> 4) & 0xf; | |
6441e6db AG |
825 | uint32_t offset = (((int16_t) moxie_process_readu (addr+2, buf, 2, |
826 | byte_order)) << 16 ) >> 16; | |
451fa05e AG |
827 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); |
828 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
829 | 4, byte_order); | |
830 | tmpu32 += offset; | |
25ea693b | 831 | if (record_full_arch_list_add_mem (tmpu32, 4)) |
451fa05e AG |
832 | return -1; |
833 | } | |
834 | break; | |
835 | case 0x0e: /* cmp */ | |
836 | { | |
25ea693b | 837 | if (record_full_arch_list_add_reg (regcache, MOXIE_CC_REGNUM)) |
451fa05e AG |
838 | return -1; |
839 | } | |
840 | break; | |
6441e6db AG |
841 | case 0x0f: /* nop */ |
842 | { | |
843 | /* Do nothing. */ | |
844 | break; | |
845 | } | |
846 | case 0x10: /* sex.b */ | |
847 | case 0x11: /* sex.s */ | |
848 | case 0x12: /* zex.b */ | |
849 | case 0x13: /* zex.s */ | |
850 | case 0x14: /* umul.x */ | |
851 | case 0x15: /* mul.x */ | |
852 | { | |
853 | int reg = (inst >> 4) & 0xf; | |
854 | if (record_full_arch_list_add_reg (regcache, reg)) | |
855 | return -1; | |
856 | } | |
857 | break; | |
451fa05e AG |
858 | case 0x16: |
859 | case 0x17: | |
860 | case 0x18: | |
861 | { | |
862 | /* Do nothing. */ | |
863 | break; | |
864 | } | |
865 | case 0x19: /* jsr */ | |
866 | { | |
867 | regcache_raw_read (regcache, | |
868 | MOXIE_SP_REGNUM, (gdb_byte *) & tmpu32); | |
869 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
870 | 4, byte_order); | |
25ea693b MM |
871 | if (record_full_arch_list_add_reg (regcache, MOXIE_FP_REGNUM) |
872 | || (record_full_arch_list_add_reg (regcache, | |
873 | MOXIE_SP_REGNUM)) | |
874 | || record_full_arch_list_add_mem (tmpu32 - 12, 12)) | |
451fa05e AG |
875 | return -1; |
876 | } | |
877 | break; | |
878 | case 0x1a: /* jmpa */ | |
879 | { | |
880 | /* Do nothing. */ | |
881 | } | |
882 | break; | |
883 | case 0x1b: /* ldi.b (immediate) */ | |
884 | case 0x1c: /* ld.b (register indirect) */ | |
885 | case 0x1d: /* lda.b */ | |
886 | { | |
887 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 888 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
889 | return -1; |
890 | } | |
891 | break; | |
892 | case 0x1e: /* st.b */ | |
893 | { | |
894 | int reg = (inst >> 4) & 0xf; | |
895 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); | |
896 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
897 | 4, byte_order); | |
25ea693b | 898 | if (record_full_arch_list_add_mem (tmpu32, 1)) |
451fa05e AG |
899 | return -1; |
900 | } | |
901 | break; | |
902 | case 0x1f: /* sta.b */ | |
903 | { | |
948f8e3d | 904 | tmpu32 = moxie_process_readu (addr+2, buf, 4, byte_order); |
25ea693b | 905 | if (record_full_arch_list_add_mem (tmpu32, 1)) |
451fa05e AG |
906 | return -1; |
907 | } | |
908 | break; | |
909 | case 0x20: /* ldi.s (immediate) */ | |
910 | case 0x21: /* ld.s (register indirect) */ | |
911 | case 0x22: /* lda.s */ | |
912 | { | |
913 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 914 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
915 | return -1; |
916 | } | |
917 | break; | |
918 | case 0x23: /* st.s */ | |
919 | { | |
920 | int reg = (inst >> 4) & 0xf; | |
921 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); | |
922 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
923 | 4, byte_order); | |
25ea693b | 924 | if (record_full_arch_list_add_mem (tmpu32, 2)) |
451fa05e AG |
925 | return -1; |
926 | } | |
927 | break; | |
928 | case 0x24: /* sta.s */ | |
929 | { | |
948f8e3d | 930 | tmpu32 = moxie_process_readu (addr+2, buf, 4, byte_order); |
25ea693b | 931 | if (record_full_arch_list_add_mem (tmpu32, 2)) |
451fa05e AG |
932 | return -1; |
933 | } | |
934 | break; | |
935 | case 0x25: /* jmp */ | |
936 | { | |
937 | /* Do nothing. */ | |
938 | } | |
939 | break; | |
940 | case 0x26: /* and */ | |
941 | case 0x27: /* lshr */ | |
942 | case 0x28: /* ashl */ | |
6441e6db | 943 | case 0x29: /* sub */ |
451fa05e AG |
944 | case 0x2a: /* neg */ |
945 | case 0x2b: /* or */ | |
946 | case 0x2c: /* not */ | |
947 | case 0x2d: /* ashr */ | |
948 | case 0x2e: /* xor */ | |
6441e6db | 949 | case 0x2f: /* mul */ |
451fa05e AG |
950 | { |
951 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 952 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
953 | return -1; |
954 | } | |
955 | break; | |
956 | case 0x30: /* swi */ | |
957 | { | |
958 | /* We currently implement support for libgloss' | |
959 | system calls. */ | |
960 | ||
948f8e3d | 961 | int inum = moxie_process_readu (addr+2, buf, 4, byte_order); |
451fa05e AG |
962 | |
963 | switch (inum) | |
964 | { | |
965 | case 0x1: /* SYS_exit */ | |
966 | { | |
967 | /* Do nothing. */ | |
968 | } | |
969 | break; | |
970 | case 0x2: /* SYS_open */ | |
971 | { | |
25ea693b | 972 | if (record_full_arch_list_add_reg (regcache, RET1_REGNUM)) |
451fa05e AG |
973 | return -1; |
974 | } | |
975 | break; | |
976 | case 0x4: /* SYS_read */ | |
977 | { | |
978 | uint32_t length, ptr; | |
979 | ||
980 | /* Read buffer pointer is in $r1. */ | |
981 | regcache_raw_read (regcache, 3, (gdb_byte *) & ptr); | |
982 | ptr = extract_unsigned_integer ((gdb_byte *) & ptr, | |
983 | 4, byte_order); | |
984 | ||
025bb325 | 985 | /* String length is at 0x12($fp). */ |
451fa05e AG |
986 | regcache_raw_read (regcache, |
987 | MOXIE_FP_REGNUM, (gdb_byte *) & tmpu32); | |
988 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
989 | 4, byte_order); | |
948f8e3d | 990 | length = moxie_process_readu (tmpu32+20, buf, 4, byte_order); |
451fa05e | 991 | |
25ea693b | 992 | if (record_full_arch_list_add_mem (ptr, length)) |
451fa05e AG |
993 | return -1; |
994 | } | |
995 | break; | |
996 | case 0x5: /* SYS_write */ | |
997 | { | |
25ea693b | 998 | if (record_full_arch_list_add_reg (regcache, RET1_REGNUM)) |
451fa05e AG |
999 | return -1; |
1000 | } | |
1001 | break; | |
1002 | default: | |
1003 | break; | |
1004 | } | |
1005 | } | |
1006 | break; | |
1007 | case 0x31: /* div.l */ | |
1008 | case 0x32: /* udiv.l */ | |
1009 | case 0x33: /* mod.l */ | |
1010 | case 0x34: /* umod.l */ | |
1011 | { | |
1012 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 1013 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
1014 | return -1; |
1015 | } | |
1016 | break; | |
1017 | case 0x35: /* brk */ | |
1018 | /* Do nothing. */ | |
1019 | break; | |
1020 | case 0x36: /* ldo.b */ | |
1021 | { | |
1022 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 1023 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
1024 | return -1; |
1025 | } | |
1026 | break; | |
1027 | case 0x37: /* sto.b */ | |
1028 | { | |
1029 | int reg = (inst >> 4) & 0xf; | |
6441e6db AG |
1030 | uint32_t offset = (((int16_t) moxie_process_readu (addr+2, buf, 2, |
1031 | byte_order)) << 16 ) >> 16; | |
451fa05e AG |
1032 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); |
1033 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
1034 | 4, byte_order); | |
1035 | tmpu32 += offset; | |
25ea693b | 1036 | if (record_full_arch_list_add_mem (tmpu32, 1)) |
451fa05e AG |
1037 | return -1; |
1038 | } | |
1039 | break; | |
1040 | case 0x38: /* ldo.s */ | |
1041 | { | |
1042 | int reg = (inst >> 4) & 0xf; | |
25ea693b | 1043 | if (record_full_arch_list_add_reg (regcache, reg)) |
451fa05e AG |
1044 | return -1; |
1045 | } | |
1046 | break; | |
1047 | case 0x39: /* sto.s */ | |
1048 | { | |
1049 | int reg = (inst >> 4) & 0xf; | |
6441e6db AG |
1050 | uint32_t offset = (((int16_t) moxie_process_readu (addr+2, buf, 2, |
1051 | byte_order)) << 16 ) >> 16; | |
451fa05e AG |
1052 | regcache_raw_read (regcache, reg, (gdb_byte *) & tmpu32); |
1053 | tmpu32 = extract_unsigned_integer ((gdb_byte *) & tmpu32, | |
1054 | 4, byte_order); | |
1055 | tmpu32 += offset; | |
25ea693b | 1056 | if (record_full_arch_list_add_mem (tmpu32, 2)) |
451fa05e AG |
1057 | return -1; |
1058 | } | |
1059 | break; | |
1060 | default: | |
1061 | /* Do nothing. */ | |
1062 | break; | |
1063 | } | |
1064 | } | |
1065 | ||
25ea693b | 1066 | if (record_full_arch_list_add_reg (regcache, MOXIE_PC_REGNUM)) |
451fa05e | 1067 | return -1; |
25ea693b | 1068 | if (record_full_arch_list_add_end ()) |
451fa05e AG |
1069 | return -1; |
1070 | return 0; | |
1071 | } | |
1072 | ||
d7066cce AG |
1073 | /* Allocate and initialize the moxie gdbarch object. */ |
1074 | ||
1075 | static struct gdbarch * | |
1076 | moxie_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1077 | { | |
1078 | struct gdbarch *gdbarch; | |
1079 | struct gdbarch_tdep *tdep; | |
1080 | ||
1081 | /* If there is already a candidate, use it. */ | |
1082 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1083 | if (arches != NULL) | |
1084 | return arches->gdbarch; | |
1085 | ||
1086 | /* Allocate space for the new architecture. */ | |
cdd238da | 1087 | tdep = XCNEW (struct gdbarch_tdep); |
d7066cce AG |
1088 | gdbarch = gdbarch_alloc (&info, tdep); |
1089 | ||
53375380 PA |
1090 | set_gdbarch_wchar_bit (gdbarch, 32); |
1091 | set_gdbarch_wchar_signed (gdbarch, 0); | |
1092 | ||
d7066cce AG |
1093 | set_gdbarch_unwind_sp (gdbarch, moxie_unwind_sp); |
1094 | ||
1095 | set_gdbarch_num_regs (gdbarch, MOXIE_NUM_REGS); | |
1096 | set_gdbarch_sp_regnum (gdbarch, MOXIE_SP_REGNUM); | |
451fa05e | 1097 | set_gdbarch_pc_regnum (gdbarch, MOXIE_PC_REGNUM); |
d7066cce AG |
1098 | set_gdbarch_register_name (gdbarch, moxie_register_name); |
1099 | set_gdbarch_register_type (gdbarch, moxie_register_type); | |
1100 | ||
1101 | set_gdbarch_return_value (gdbarch, moxie_return_value); | |
1102 | ||
1103 | set_gdbarch_skip_prologue (gdbarch, moxie_skip_prologue); | |
1104 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
04180708 YQ |
1105 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1106 | moxie_breakpoint::kind_from_pc); | |
1107 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1108 | moxie_breakpoint::bp_from_kind); | |
d7066cce AG |
1109 | set_gdbarch_frame_align (gdbarch, moxie_frame_align); |
1110 | ||
1111 | frame_base_set_default (gdbarch, &moxie_frame_base); | |
1112 | ||
1113 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
1114 | stack address must match the SP value returned by | |
1115 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
1116 | set_gdbarch_dummy_id (gdbarch, moxie_dummy_id); | |
1117 | ||
1118 | set_gdbarch_unwind_pc (gdbarch, moxie_unwind_pc); | |
1119 | ||
d7066cce AG |
1120 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1121 | gdbarch_init_osabi (info, gdbarch); | |
1122 | ||
1123 | /* Hook in the default unwinders. */ | |
1124 | frame_unwind_append_unwinder (gdbarch, &moxie_frame_unwind); | |
1125 | ||
6ed1ff02 AG |
1126 | /* Single stepping. */ |
1127 | set_gdbarch_software_single_step (gdbarch, moxie_software_single_step); | |
1128 | ||
d7066cce AG |
1129 | /* Support simple overlay manager. */ |
1130 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
1131 | ||
451fa05e AG |
1132 | /* Support reverse debugging. */ |
1133 | set_gdbarch_process_record (gdbarch, moxie_process_record); | |
1134 | ||
d7066cce AG |
1135 | return gdbarch; |
1136 | } | |
1137 | ||
1138 | /* Register this machine's init routine. */ | |
1139 | ||
1140 | void | |
1141 | _initialize_moxie_tdep (void) | |
1142 | { | |
1143 | register_gdbarch_init (bfd_arch_moxie, moxie_gdbarch_init); | |
1144 | } |