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1 | /* Target-dependent code for Morpho ms1 processor, for GDB. |
2 | ||
3 | Copyright 2005 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | /* Contributed by Michael Snyder, msnyder@redhat.com. */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "frame-unwind.h" | |
27 | #include "frame-base.h" | |
28 | #include "symtab.h" | |
29 | #include "dis-asm.h" | |
30 | #include "arch-utils.h" | |
31 | #include "gdbtypes.h" | |
32 | #include "gdb_string.h" | |
33 | #include "regcache.h" | |
34 | #include "reggroups.h" | |
35 | #include "gdbcore.h" | |
36 | #include "trad-frame.h" | |
37 | #include "inferior.h" | |
38 | #include "dwarf2-frame.h" | |
39 | #include "infcall.h" | |
40 | #include "gdb_assert.h" | |
41 | ||
42 | enum ms1_arch_constants | |
43 | { | |
44 | MS1_MAX_STRUCT_SIZE = 16 | |
45 | }; | |
46 | ||
47 | enum ms1_gdb_regnums | |
48 | { | |
49 | MS1_R0_REGNUM, /* 32 bit regs. */ | |
50 | MS1_R1_REGNUM, | |
51 | MS1_1ST_ARGREG = MS1_R1_REGNUM, | |
52 | MS1_R2_REGNUM, | |
53 | MS1_R3_REGNUM, | |
54 | MS1_R4_REGNUM, | |
55 | MS1_LAST_ARGREG = MS1_R4_REGNUM, | |
56 | MS1_R5_REGNUM, | |
57 | MS1_R6_REGNUM, | |
58 | MS1_R7_REGNUM, | |
59 | MS1_R8_REGNUM, | |
60 | MS1_R9_REGNUM, | |
61 | MS1_R10_REGNUM, | |
62 | MS1_R11_REGNUM, | |
63 | MS1_R12_REGNUM, | |
64 | MS1_FP_REGNUM = MS1_R12_REGNUM, | |
65 | MS1_R13_REGNUM, | |
66 | MS1_SP_REGNUM = MS1_R13_REGNUM, | |
67 | MS1_R14_REGNUM, | |
68 | MS1_RA_REGNUM = MS1_R14_REGNUM, | |
69 | MS1_R15_REGNUM, | |
70 | MS1_IRA_REGNUM = MS1_R15_REGNUM, | |
71 | MS1_PC_REGNUM, | |
72 | ||
73 | /* Interrupt Enable pseudo-register, exported by SID. */ | |
74 | MS1_INT_ENABLE_REGNUM, | |
75 | /* End of CPU regs. */ | |
76 | ||
77 | MS1_NUM_CPU_REGS, | |
78 | ||
79 | /* Co-processor registers. */ | |
80 | MS1_COPRO_REGNUM = MS1_NUM_CPU_REGS, /* 16 bit regs. */ | |
81 | MS1_CPR0_REGNUM, | |
82 | MS1_CPR1_REGNUM, | |
83 | MS1_CPR2_REGNUM, | |
84 | MS1_CPR3_REGNUM, | |
85 | MS1_CPR4_REGNUM, | |
86 | MS1_CPR5_REGNUM, | |
87 | MS1_CPR6_REGNUM, | |
88 | MS1_CPR7_REGNUM, | |
89 | MS1_CPR8_REGNUM, | |
90 | MS1_CPR9_REGNUM, | |
91 | MS1_CPR10_REGNUM, | |
92 | MS1_CPR11_REGNUM, | |
93 | MS1_CPR12_REGNUM, | |
94 | MS1_CPR13_REGNUM, | |
95 | MS1_CPR14_REGNUM, | |
96 | MS1_CPR15_REGNUM, | |
97 | MS1_BYPA_REGNUM, /* 32 bit regs. */ | |
98 | MS1_BYPB_REGNUM, | |
99 | MS1_BYPC_REGNUM, | |
100 | MS1_FLAG_REGNUM, | |
101 | MS1_CONTEXT_REGNUM, /* 38 bits (treat as array of | |
102 | six bytes). */ | |
103 | MS1_MAC_REGNUM, /* 32 bits. */ | |
104 | MS1_Z1_REGNUM, /* 16 bits. */ | |
105 | MS1_Z2_REGNUM, /* 16 bits. */ | |
106 | MS1_ICHANNEL_REGNUM, /* 32 bits. */ | |
107 | MS1_ISCRAMB_REGNUM, /* 32 bits. */ | |
108 | MS1_QSCRAMB_REGNUM, /* 32 bits. */ | |
109 | MS1_OUT_REGNUM, /* 16 bits. */ | |
110 | MS1_EXMAC_REGNUM, /* 32 bits (8 used). */ | |
111 | MS1_QCHANNEL_REGNUM, /* 32 bits. */ | |
112 | ||
113 | /* Number of real registers. */ | |
114 | MS1_NUM_REGS, | |
115 | ||
116 | /* Pseudo-registers. */ | |
117 | MS1_COPRO_PSEUDOREG_REGNUM = MS1_NUM_REGS, | |
118 | MS1_MAC_PSEUDOREG_REGNUM, | |
119 | ||
120 | /* Two pseudo-regs ('coprocessor' and 'mac'). */ | |
121 | MS1_NUM_PSEUDO_REGS = 2 | |
122 | }; | |
123 | ||
124 | /* Return name of register number specified by REGNUM. */ | |
125 | ||
126 | static const char * | |
127 | ms1_register_name (int regnum) | |
128 | { | |
129 | static char *register_names[] = { | |
130 | /* CPU regs. */ | |
131 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
132 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
133 | "pc", "IE", | |
134 | /* Co-processor regs. */ | |
135 | "", /* copro register. */ | |
136 | "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", | |
137 | "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15", | |
138 | "bypa", "bypb", "bypc", "flag", "context", "" /* mac. */ , "z1", "z2", | |
139 | "Ichannel", "Iscramb", "Qscramb", "out", "" /* ex-mac. */ , "Qchannel", | |
140 | /* Pseudo-registers. */ | |
141 | "coprocessor", "MAC" | |
142 | }; | |
143 | ||
144 | gdb_assert (regnum >= 0 && regnum < ARRAY_SIZE (register_names)); | |
145 | return register_names[regnum]; | |
146 | } | |
147 | ||
148 | /* Given ARCH and a register number specified by REGNUM, return the | |
149 | type of that register. */ | |
150 | ||
151 | static struct type * | |
152 | ms1_register_type (struct gdbarch *arch, int regnum) | |
153 | { | |
154 | static struct type *void_func_ptr = NULL; | |
155 | static struct type *void_ptr = NULL; | |
156 | static struct type *copro_type; | |
157 | ||
158 | if (regnum >= 0 && regnum < MS1_NUM_REGS + MS1_NUM_PSEUDO_REGS) | |
159 | { | |
160 | if (void_func_ptr == NULL) | |
161 | { | |
162 | struct type *temp; | |
163 | ||
164 | void_ptr = lookup_pointer_type (builtin_type_void); | |
165 | void_func_ptr = | |
166 | lookup_pointer_type (lookup_function_type (builtin_type_void)); | |
167 | temp = create_range_type (NULL, builtin_type_unsigned_int, 0, 1); | |
168 | copro_type = create_array_type (NULL, builtin_type_int16, temp); | |
169 | } | |
170 | switch (regnum) | |
171 | { | |
172 | case MS1_PC_REGNUM: | |
173 | case MS1_RA_REGNUM: | |
174 | case MS1_IRA_REGNUM: | |
175 | return void_func_ptr; | |
176 | case MS1_SP_REGNUM: | |
177 | case MS1_FP_REGNUM: | |
178 | return void_ptr; | |
179 | case MS1_INT_ENABLE_REGNUM: | |
180 | case MS1_ICHANNEL_REGNUM: | |
181 | case MS1_QCHANNEL_REGNUM: | |
182 | case MS1_ISCRAMB_REGNUM: | |
183 | case MS1_QSCRAMB_REGNUM: | |
184 | return builtin_type_int32; | |
185 | case MS1_EXMAC_REGNUM: | |
186 | case MS1_MAC_REGNUM: | |
187 | return builtin_type_uint32; | |
188 | case MS1_BYPA_REGNUM: | |
189 | case MS1_BYPB_REGNUM: | |
190 | case MS1_BYPC_REGNUM: | |
191 | case MS1_Z1_REGNUM: | |
192 | case MS1_Z2_REGNUM: | |
193 | case MS1_OUT_REGNUM: | |
194 | return builtin_type_int16; | |
195 | case MS1_CONTEXT_REGNUM: | |
196 | return builtin_type_long_long; | |
197 | case MS1_COPRO_REGNUM: | |
198 | case MS1_COPRO_PSEUDOREG_REGNUM: | |
199 | return copro_type; | |
200 | case MS1_MAC_PSEUDOREG_REGNUM: | |
201 | if (gdbarch_bfd_arch_info (arch)->mach == bfd_mach_mrisc2) | |
202 | return builtin_type_uint64; | |
203 | else | |
204 | return builtin_type_uint32; | |
205 | case MS1_FLAG_REGNUM: | |
206 | return builtin_type_unsigned_char; | |
207 | default: | |
208 | if (regnum >= MS1_R0_REGNUM && regnum <= MS1_R15_REGNUM) | |
209 | return builtin_type_int32; | |
210 | else if (regnum >= MS1_CPR0_REGNUM && regnum <= MS1_CPR15_REGNUM) | |
211 | return builtin_type_int16; | |
212 | } | |
213 | } | |
214 | internal_error (__FILE__, __LINE__, | |
215 | _("ms1_register_type: illegal register number %d"), regnum); | |
216 | } | |
217 | ||
218 | /* Return true if register REGNUM is a member of the register group | |
219 | specified by GROUP. */ | |
220 | ||
221 | static int | |
222 | ms1_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
223 | struct reggroup *group) | |
224 | { | |
225 | /* Groups of registers that can be displayed via "info reg". */ | |
226 | if (group == all_reggroup) | |
227 | return (regnum >= 0 | |
228 | && regnum < MS1_NUM_REGS + MS1_NUM_PSEUDO_REGS | |
229 | && ms1_register_name (regnum)[0] != '\0'); | |
230 | ||
231 | if (group == general_reggroup) | |
232 | return (regnum >= MS1_R0_REGNUM && regnum <= MS1_R15_REGNUM); | |
233 | ||
234 | if (group == float_reggroup) | |
235 | return 0; /* No float regs. */ | |
236 | ||
237 | if (group == vector_reggroup) | |
238 | return 0; /* No vector regs. */ | |
239 | ||
240 | /* For any that are not handled above. */ | |
241 | return default_register_reggroup_p (gdbarch, regnum, group); | |
242 | } | |
243 | ||
244 | /* Return the return value convention used for a given type TYPE. | |
245 | Optionally, fetch or set the return value via READBUF or | |
246 | WRITEBUF respectively using REGCACHE for the register | |
247 | values. */ | |
248 | ||
249 | static enum return_value_convention | |
250 | ms1_return_value (struct gdbarch *gdbarch, struct type *type, | |
251 | struct regcache *regcache, gdb_byte *readbuf, | |
252 | const gdb_byte *writebuf) | |
253 | { | |
254 | if (TYPE_LENGTH (type) > 4) | |
255 | { | |
256 | /* Return values > 4 bytes are returned in memory, | |
257 | pointed to by R11. */ | |
258 | if (readbuf) | |
259 | { | |
260 | ULONGEST addr; | |
261 | ||
262 | regcache_cooked_read_unsigned (regcache, MS1_R11_REGNUM, &addr); | |
263 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
264 | } | |
265 | ||
266 | if (writebuf) | |
267 | { | |
268 | ULONGEST addr; | |
269 | ||
270 | regcache_cooked_read_unsigned (regcache, MS1_R11_REGNUM, &addr); | |
271 | write_memory (addr, writebuf, TYPE_LENGTH (type)); | |
272 | } | |
273 | ||
274 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
275 | } | |
276 | else | |
277 | { | |
278 | if (readbuf) | |
279 | { | |
280 | ULONGEST temp; | |
281 | ||
282 | /* Return values of <= 4 bytes are returned in R11. */ | |
283 | regcache_cooked_read_unsigned (regcache, MS1_R11_REGNUM, &temp); | |
284 | store_unsigned_integer (readbuf, TYPE_LENGTH (type), temp); | |
285 | } | |
286 | ||
287 | if (writebuf) | |
288 | { | |
289 | if (TYPE_LENGTH (type) < 4) | |
290 | { | |
291 | gdb_byte buf[4]; | |
292 | /* Add leading zeros to the value. */ | |
293 | memset (buf, 0, sizeof (buf)); | |
294 | memcpy (buf + sizeof (buf) - TYPE_LENGTH (type), | |
295 | writebuf, TYPE_LENGTH (type)); | |
296 | regcache_cooked_write (regcache, MS1_R11_REGNUM, buf); | |
297 | } | |
298 | else /* (TYPE_LENGTH (type) == 4 */ | |
299 | regcache_cooked_write (regcache, MS1_R11_REGNUM, writebuf); | |
300 | } | |
301 | ||
302 | return RETURN_VALUE_REGISTER_CONVENTION; | |
303 | } | |
304 | } | |
305 | ||
306 | /* If the input address, PC, is in a function prologue, return the | |
307 | address of the end of the prologue, otherwise return the input | |
308 | address. | |
309 | ||
310 | Note: PC is likely to be the function start, since this function | |
311 | is mainly used for advancing a breakpoint to the first line, or | |
312 | stepping to the first line when we have stepped into a function | |
313 | call. */ | |
314 | ||
315 | static CORE_ADDR | |
316 | ms1_skip_prologue (CORE_ADDR pc) | |
317 | { | |
318 | CORE_ADDR func_addr = 0, func_end = 0; | |
319 | char *func_name; | |
320 | unsigned long instr; | |
321 | ||
322 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) | |
323 | { | |
324 | struct symtab_and_line sal; | |
325 | struct symbol *sym; | |
326 | ||
327 | /* Found a function. */ | |
328 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); | |
329 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
330 | { | |
331 | /* Don't use this trick for assembly source files. */ | |
332 | sal = find_pc_line (func_addr, 0); | |
333 | ||
334 | if (sal.end && sal.end < func_end) | |
335 | { | |
336 | /* Found a line number, use it as end of prologue. */ | |
337 | return sal.end; | |
338 | } | |
339 | } | |
340 | } | |
341 | ||
342 | /* No function symbol, or no line symbol. Use prologue scanning method. */ | |
343 | for (;; pc += 4) | |
344 | { | |
345 | instr = read_memory_unsigned_integer (pc, 4); | |
346 | if (instr == 0x12000000) /* nop */ | |
347 | continue; | |
348 | if (instr == 0x12ddc000) /* copy sp into fp */ | |
349 | continue; | |
350 | instr >>= 16; | |
351 | if (instr == 0x05dd) /* subi sp, sp, imm */ | |
352 | continue; | |
353 | if (instr >= 0x43c0 && instr <= 0x43df) /* push */ | |
354 | continue; | |
355 | /* Not an obvious prologue instruction. */ | |
356 | break; | |
357 | } | |
358 | ||
359 | return pc; | |
360 | } | |
361 | ||
362 | /* The breakpoint instruction must be the same size as the smallest | |
363 | instruction in the instruction set. | |
364 | ||
365 | The BP for ms1 is defined as 0x68000000. */ | |
366 | ||
367 | static const gdb_byte * | |
368 | ms1_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) | |
369 | { | |
370 | static gdb_byte breakpoint[] = { 0x68, 0, 0, 0 }; | |
371 | ||
372 | *bp_size = 4; | |
373 | return breakpoint; | |
374 | } | |
375 | ||
376 | /* Fetch the pseudo registers: | |
377 | ||
378 | There are two pseudo-registers: | |
379 | 1) The 'coprocessor' pseudo-register (which mirrors the | |
380 | "real" coprocessor register sent by the target), and | |
381 | 2) The 'MAC' pseudo-register (which represents the union | |
382 | of the original 32 bit target MAC register and the new | |
383 | 8-bit extended-MAC register). */ | |
384 | ||
385 | static void | |
386 | ms1_pseudo_register_read (struct gdbarch *gdbarch, | |
387 | struct regcache *regcache, int regno, gdb_byte *buf) | |
388 | { | |
389 | switch (regno) | |
390 | { | |
391 | case MS1_COPRO_REGNUM: | |
392 | case MS1_COPRO_PSEUDOREG_REGNUM: | |
393 | regcache_raw_read (regcache, MS1_COPRO_REGNUM, buf); | |
394 | break; | |
395 | case MS1_MAC_REGNUM: | |
396 | case MS1_MAC_PSEUDOREG_REGNUM: | |
397 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2) | |
398 | { | |
399 | ULONGEST oldmac = 0, ext_mac = 0; | |
400 | ULONGEST newmac; | |
401 | ||
402 | regcache_cooked_read_unsigned (regcache, MS1_MAC_REGNUM, &oldmac); | |
403 | regcache_cooked_read_unsigned (regcache, MS1_EXMAC_REGNUM, &ext_mac); | |
404 | newmac = | |
405 | (oldmac & 0xffffffff) | ((long long) (ext_mac & 0xff) << 32); | |
406 | store_signed_integer (buf, 8, newmac); | |
407 | } | |
408 | else | |
409 | regcache_raw_read (regcache, MS1_MAC_REGNUM, buf); | |
410 | break; | |
411 | default: | |
412 | internal_error (__FILE__, __LINE__, | |
413 | _("ms1_pseudo_register_read: bad reg # (%d)"), regno); | |
414 | break; | |
415 | } | |
416 | } | |
417 | ||
418 | /* Write the pseudo registers: | |
419 | ||
420 | Ms1 pseudo-registers are stored directly to the target. The | |
421 | 'coprocessor' register is special, because when it is modified, all | |
422 | the other coprocessor regs must be flushed from the reg cache. */ | |
423 | ||
424 | static void | |
425 | ms1_pseudo_register_write (struct gdbarch *gdbarch, | |
426 | struct regcache *regcache, | |
427 | int regno, const gdb_byte *buf) | |
428 | { | |
429 | int i; | |
430 | ||
431 | switch (regno) | |
432 | { | |
433 | case MS1_COPRO_REGNUM: | |
434 | case MS1_COPRO_PSEUDOREG_REGNUM: | |
435 | regcache_raw_write (regcache, MS1_COPRO_REGNUM, buf); | |
436 | for (i = MS1_NUM_CPU_REGS; i < MS1_NUM_REGS; i++) | |
437 | set_register_cached (i, 0); | |
438 | break; | |
439 | case MS1_MAC_REGNUM: | |
440 | case MS1_MAC_PSEUDOREG_REGNUM: | |
441 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2) | |
442 | { | |
443 | /* The 8-byte MAC pseudo-register must be broken down into two | |
444 | 32-byte registers. */ | |
445 | unsigned int oldmac, ext_mac; | |
446 | ULONGEST newmac; | |
447 | ||
448 | newmac = extract_unsigned_integer (buf, 8); | |
449 | oldmac = newmac & 0xffffffff; | |
450 | ext_mac = (newmac >> 32) & 0xff; | |
451 | regcache_cooked_write_unsigned (regcache, MS1_MAC_REGNUM, oldmac); | |
452 | regcache_cooked_write_unsigned (regcache, MS1_EXMAC_REGNUM, ext_mac); | |
453 | } | |
454 | else | |
455 | regcache_raw_write (regcache, MS1_MAC_REGNUM, buf); | |
456 | break; | |
457 | default: | |
458 | internal_error (__FILE__, __LINE__, | |
459 | _("ms1_pseudo_register_write: bad reg # (%d)"), regno); | |
460 | break; | |
461 | } | |
462 | } | |
463 | ||
464 | static CORE_ADDR | |
465 | ms1_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
466 | { | |
467 | /* Register size is 4 bytes. */ | |
468 | return align_down (sp, 4); | |
469 | } | |
470 | ||
471 | /* Implements the "info registers" command. When ``all'' is non-zero, | |
472 | the coprocessor registers will be printed in addition to the rest | |
473 | of the registers. */ | |
474 | ||
475 | static void | |
476 | ms1_registers_info (struct gdbarch *gdbarch, | |
477 | struct ui_file *file, | |
478 | struct frame_info *frame, int regnum, int all) | |
479 | { | |
480 | if (regnum == -1) | |
481 | { | |
482 | int lim; | |
483 | ||
484 | lim = all ? MS1_NUM_REGS : MS1_NUM_CPU_REGS; | |
485 | ||
486 | for (regnum = 0; regnum < lim; regnum++) | |
487 | { | |
488 | /* Don't display the Qchannel register since it will be displayed | |
489 | along with Ichannel. (See below.) */ | |
490 | if (regnum == MS1_QCHANNEL_REGNUM) | |
491 | continue; | |
492 | ||
493 | ms1_registers_info (gdbarch, file, frame, regnum, all); | |
494 | ||
495 | /* Display the Qchannel register immediately after Ichannel. */ | |
496 | if (regnum == MS1_ICHANNEL_REGNUM) | |
497 | ms1_registers_info (gdbarch, file, frame, MS1_QCHANNEL_REGNUM, all); | |
498 | } | |
499 | } | |
500 | else | |
501 | { | |
502 | if (regnum == MS1_EXMAC_REGNUM) | |
503 | return; | |
504 | else if (regnum == MS1_CONTEXT_REGNUM) | |
505 | { | |
506 | /* Special output handling for 38-bit context register. */ | |
507 | unsigned char *buff; | |
508 | unsigned int *bytes, i, regsize; | |
509 | ||
510 | regsize = register_size (gdbarch, regnum); | |
511 | ||
512 | buff = alloca (regsize); | |
513 | bytes = alloca (regsize * sizeof (*bytes)); | |
514 | ||
515 | frame_register_read (frame, regnum, buff); | |
516 | ||
517 | fputs_filtered (REGISTER_NAME (regnum), file); | |
518 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
519 | fputs_filtered ("0x", file); | |
520 | ||
521 | for (i = 0; i < regsize; i++) | |
522 | fprintf_filtered (file, "%02x", (unsigned int) | |
523 | extract_unsigned_integer (buff + i, 1)); | |
524 | fputs_filtered ("\t", file); | |
525 | print_longest (file, 'd', 0, | |
526 | extract_unsigned_integer (buff, regsize)); | |
527 | fputs_filtered ("\n", file); | |
528 | } | |
529 | else if (regnum == MS1_COPRO_REGNUM | |
530 | || regnum == MS1_COPRO_PSEUDOREG_REGNUM) | |
531 | { | |
532 | /* Special output handling for the 'coprocessor' register. */ | |
533 | char *buf; | |
534 | ||
535 | buf = alloca (register_size (gdbarch, MS1_COPRO_REGNUM)); | |
536 | frame_register_read (frame, MS1_COPRO_REGNUM, buf); | |
537 | /* And print. */ | |
538 | regnum = MS1_COPRO_PSEUDOREG_REGNUM; | |
539 | fputs_filtered (REGISTER_NAME (regnum), file); | |
540 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
541 | val_print (register_type (gdbarch, regnum), buf, | |
542 | 0, 0, file, 0, 1, 0, Val_no_prettyprint); | |
543 | fputs_filtered ("\n", file); | |
544 | } | |
545 | else if (regnum == MS1_MAC_REGNUM || regnum == MS1_MAC_PSEUDOREG_REGNUM) | |
546 | { | |
547 | ULONGEST oldmac, ext_mac, newmac; | |
548 | char buf[3 * sizeof (LONGEST)]; | |
549 | ||
550 | /* Get the two "real" mac registers. */ | |
551 | frame_register_read (frame, MS1_MAC_REGNUM, buf); | |
552 | oldmac = extract_unsigned_integer (buf, | |
553 | register_size (gdbarch, | |
554 | MS1_MAC_REGNUM)); | |
555 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2) | |
556 | { | |
557 | frame_register_read (frame, MS1_EXMAC_REGNUM, buf); | |
558 | ext_mac = extract_unsigned_integer (buf, | |
559 | register_size (gdbarch, | |
560 | MS1_EXMAC_REGNUM)); | |
561 | } | |
562 | else | |
563 | ext_mac = 0; | |
564 | ||
565 | /* Add them together. */ | |
566 | newmac = (oldmac & 0xffffffff) + ((ext_mac & 0xff) << 32); | |
567 | ||
568 | /* And print. */ | |
569 | regnum = MS1_MAC_PSEUDOREG_REGNUM; | |
570 | fputs_filtered (REGISTER_NAME (regnum), file); | |
571 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
572 | fputs_filtered ("0x", file); | |
573 | print_longest (file, 'x', 0, newmac); | |
574 | fputs_filtered ("\t", file); | |
575 | print_longest (file, 'u', 0, newmac); | |
576 | fputs_filtered ("\n", file); | |
577 | } | |
578 | else | |
579 | default_print_registers_info (gdbarch, file, frame, regnum, all); | |
580 | } | |
581 | } | |
582 | ||
583 | /* Set up the callee's arguments for an inferior function call. The | |
584 | arguments are pushed on the stack or are placed in registers as | |
585 | appropriate. It also sets up the return address (which points to | |
586 | the call dummy breakpoint). | |
587 | ||
588 | Returns the updated (and aligned) stack pointer. */ | |
589 | ||
590 | static CORE_ADDR | |
591 | ms1_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
592 | struct regcache *regcache, CORE_ADDR bp_addr, | |
593 | int nargs, struct value **args, CORE_ADDR sp, | |
594 | int struct_return, CORE_ADDR struct_addr) | |
595 | { | |
596 | #define wordsize 4 | |
597 | char buf[MS1_MAX_STRUCT_SIZE]; | |
598 | int argreg = MS1_1ST_ARGREG; | |
599 | int split_param_len = 0; | |
600 | int stack_dest = sp; | |
601 | int slacklen; | |
602 | int typelen; | |
603 | int i, j; | |
604 | ||
605 | /* First handle however many args we can fit into MS1_1ST_ARGREG thru | |
606 | MS1_LAST_ARGREG. */ | |
607 | for (i = 0; i < nargs && argreg <= MS1_LAST_ARGREG; i++) | |
608 | { | |
609 | const char *val; | |
610 | typelen = TYPE_LENGTH (value_type (args[i])); | |
611 | switch (typelen) | |
612 | { | |
613 | case 1: | |
614 | case 2: | |
615 | case 3: | |
616 | case 4: | |
617 | regcache_cooked_write_unsigned (regcache, argreg++, | |
618 | extract_unsigned_integer | |
619 | (value_contents (args[i]), | |
620 | wordsize)); | |
621 | break; | |
622 | case 8: | |
623 | case 12: | |
624 | case 16: | |
625 | val = value_contents (args[i]); | |
626 | while (typelen > 0) | |
627 | { | |
628 | if (argreg <= MS1_LAST_ARGREG) | |
629 | { | |
630 | /* This word of the argument is passed in a register. */ | |
631 | regcache_cooked_write_unsigned (regcache, argreg++, | |
632 | extract_unsigned_integer | |
633 | (val, wordsize)); | |
634 | typelen -= wordsize; | |
635 | val += wordsize; | |
636 | } | |
637 | else | |
638 | { | |
639 | /* Remainder of this arg must be passed on the stack | |
640 | (deferred to do later). */ | |
641 | split_param_len = typelen; | |
642 | memcpy (buf, val, typelen); | |
643 | break; /* No more args can be handled in regs. */ | |
644 | } | |
645 | } | |
646 | break; | |
647 | default: | |
648 | /* By reverse engineering of gcc output, args bigger than | |
649 | 16 bytes go on the stack, and their address is passed | |
650 | in the argreg. */ | |
651 | stack_dest -= typelen; | |
652 | write_memory (stack_dest, value_contents (args[i]), typelen); | |
653 | regcache_cooked_write_unsigned (regcache, argreg++, stack_dest); | |
654 | break; | |
655 | } | |
656 | } | |
657 | ||
658 | /* Next, the rest of the arguments go onto the stack, in reverse order. */ | |
659 | for (j = nargs - 1; j >= i; j--) | |
660 | { | |
661 | char *val; | |
662 | /* Right-justify the value in an aligned-length buffer. */ | |
663 | typelen = TYPE_LENGTH (value_type (args[j])); | |
664 | slacklen = (wordsize - (typelen % wordsize)) % wordsize; | |
665 | val = alloca (typelen + slacklen); | |
666 | memcpy (val, value_contents (args[j]), typelen); | |
667 | memset (val + typelen, 0, slacklen); | |
668 | /* Now write this data to the stack. */ | |
669 | stack_dest -= typelen + slacklen; | |
670 | write_memory (stack_dest, val, typelen + slacklen); | |
671 | } | |
672 | ||
673 | /* Finally, if a param needs to be split between registers and stack, | |
674 | write the second half to the stack now. */ | |
675 | if (split_param_len != 0) | |
676 | { | |
677 | stack_dest -= split_param_len; | |
678 | write_memory (stack_dest, buf, split_param_len); | |
679 | } | |
680 | ||
681 | /* Set up return address (provided to us as bp_addr). */ | |
682 | regcache_cooked_write_unsigned (regcache, MS1_RA_REGNUM, bp_addr); | |
683 | ||
684 | /* Store struct return address, if given. */ | |
685 | if (struct_return && struct_addr != 0) | |
686 | regcache_cooked_write_unsigned (regcache, MS1_R11_REGNUM, struct_addr); | |
687 | ||
688 | /* Set aside 16 bytes for the callee to save regs 1-4. */ | |
689 | stack_dest -= 16; | |
690 | ||
691 | /* Update the stack pointer. */ | |
692 | regcache_cooked_write_unsigned (regcache, MS1_SP_REGNUM, stack_dest); | |
693 | ||
694 | /* And that should do it. Return the new stack pointer. */ | |
695 | return stack_dest; | |
696 | } | |
697 | ||
698 | ||
699 | /* The 'unwind_cache' data structure. */ | |
700 | ||
701 | struct ms1_unwind_cache | |
702 | { | |
703 | /* The previous frame's inner most stack address. | |
704 | Used as this frame ID's stack_addr. */ | |
705 | CORE_ADDR prev_sp; | |
706 | CORE_ADDR frame_base; | |
707 | int framesize; | |
708 | int frameless_p; | |
709 | ||
710 | /* Table indicating the location of each and every register. */ | |
711 | struct trad_frame_saved_reg *saved_regs; | |
712 | }; | |
713 | ||
714 | /* Initialize an unwind_cache. Build up the saved_regs table etc. for | |
715 | the frame. */ | |
716 | ||
717 | static struct ms1_unwind_cache * | |
718 | ms1_frame_unwind_cache (struct frame_info *next_frame, | |
719 | void **this_prologue_cache) | |
720 | { | |
721 | struct gdbarch *gdbarch; | |
722 | struct ms1_unwind_cache *info; | |
723 | CORE_ADDR next_addr, start_addr, end_addr, prologue_end_addr; | |
724 | unsigned long instr, upper_half, delayed_store = 0; | |
725 | int regnum, offset; | |
726 | ULONGEST sp, fp; | |
727 | ||
728 | if ((*this_prologue_cache)) | |
729 | return (*this_prologue_cache); | |
730 | ||
731 | gdbarch = get_frame_arch (next_frame); | |
732 | info = FRAME_OBSTACK_ZALLOC (struct ms1_unwind_cache); | |
733 | (*this_prologue_cache) = info; | |
734 | ||
735 | info->prev_sp = 0; | |
736 | info->framesize = 0; | |
737 | info->frame_base = 0; | |
738 | info->frameless_p = 1; | |
739 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
740 | ||
741 | /* Grab the frame-relative values of SP and FP, needed below. | |
742 | The frame_saved_register function will find them on the | |
743 | stack or in the registers as appropriate. */ | |
744 | frame_unwind_unsigned_register (next_frame, MS1_SP_REGNUM, &sp); | |
745 | frame_unwind_unsigned_register (next_frame, MS1_FP_REGNUM, &fp); | |
746 | ||
747 | start_addr = frame_func_unwind (next_frame); | |
748 | ||
749 | /* Return early if GDB couldn't find the function. */ | |
750 | if (start_addr == 0) | |
751 | return info; | |
752 | ||
753 | end_addr = frame_pc_unwind (next_frame); | |
754 | prologue_end_addr = skip_prologue_using_sal (start_addr); | |
755 | if (end_addr == 0) | |
756 | for (next_addr = start_addr; next_addr < end_addr; next_addr += 4) | |
757 | { | |
758 | instr = get_frame_memory_unsigned (next_frame, next_addr, 4); | |
759 | if (delayed_store) /* previous instr was a push */ | |
760 | { | |
761 | upper_half = delayed_store >> 16; | |
762 | regnum = upper_half & 0xf; | |
763 | offset = delayed_store & 0xffff; | |
764 | switch (upper_half & 0xfff0) | |
765 | { | |
766 | case 0x43c0: /* push using frame pointer */ | |
767 | info->saved_regs[regnum].addr = offset; | |
768 | break; | |
769 | case 0x43d0: /* push using stack pointer */ | |
770 | info->saved_regs[regnum].addr = offset; | |
771 | break; | |
772 | default: /* lint */ | |
773 | break; | |
774 | } | |
775 | delayed_store = 0; | |
776 | } | |
777 | ||
778 | switch (instr) | |
779 | { | |
780 | case 0x12000000: /* NO-OP */ | |
781 | continue; | |
782 | case 0x12ddc000: /* copy sp into fp */ | |
783 | info->frameless_p = 0; /* Record that the frame pointer is in use. */ | |
784 | continue; | |
785 | default: | |
786 | upper_half = instr >> 16; | |
787 | if (upper_half == 0x05dd || /* subi sp, sp, imm */ | |
788 | upper_half == 0x07dd) /* subui sp, sp, imm */ | |
789 | { | |
790 | /* Record the frame size. */ | |
791 | info->framesize = instr & 0xffff; | |
792 | continue; | |
793 | } | |
794 | if ((upper_half & 0xfff0) == 0x43c0 || /* frame push */ | |
795 | (upper_half & 0xfff0) == 0x43d0) /* stack push */ | |
796 | { | |
797 | /* Save this instruction, but don't record the | |
798 | pushed register as 'saved' until we see the | |
799 | next instruction. That's because of deferred stores | |
800 | on this target -- GDB won't be able to read the register | |
801 | from the stack until one instruction later. */ | |
802 | delayed_store = instr; | |
803 | continue; | |
804 | } | |
805 | /* Not a prologue instruction. Is this the end of the prologue? | |
806 | This is the most difficult decision; when to stop scanning. | |
807 | ||
808 | If we have no line symbol, then the best thing we can do | |
809 | is to stop scanning when we encounter an instruction that | |
810 | is not likely to be a part of the prologue. | |
811 | ||
812 | But if we do have a line symbol, then we should | |
813 | keep scanning until we reach it (or we reach end_addr). */ | |
814 | ||
815 | if (prologue_end_addr && (prologue_end_addr > (next_addr + 4))) | |
816 | continue; /* Keep scanning, recording saved_regs etc. */ | |
817 | else | |
818 | break; /* Quit scanning: breakpoint can be set here. */ | |
819 | } | |
820 | } | |
821 | ||
822 | /* Special handling for the "saved" address of the SP: | |
823 | The SP is of course never saved on the stack at all, so | |
824 | by convention what we put here is simply the previous | |
825 | _value_ of the SP (as opposed to an address where the | |
826 | previous value would have been pushed). This will also | |
827 | give us the frame base address. */ | |
828 | ||
829 | if (info->frameless_p) | |
830 | { | |
831 | info->frame_base = sp + info->framesize; | |
832 | info->prev_sp = sp + info->framesize; | |
833 | } | |
834 | else | |
835 | { | |
836 | info->frame_base = fp + info->framesize; | |
837 | info->prev_sp = fp + info->framesize; | |
838 | } | |
839 | /* Save prev_sp in saved_regs as a value, not as an address. */ | |
840 | trad_frame_set_value (info->saved_regs, MS1_SP_REGNUM, info->prev_sp); | |
841 | ||
842 | /* Now convert frame offsets to actual addresses (not offsets). */ | |
843 | for (regnum = 0; regnum < MS1_NUM_REGS; regnum++) | |
844 | if (trad_frame_addr_p (info->saved_regs, regnum)) | |
845 | info->saved_regs[regnum].addr += info->frame_base - info->framesize; | |
846 | ||
847 | /* The call instruction moves the caller's PC in the callee's RA reg. | |
848 | Since this is an unwind, do the reverse. Copy the location of RA | |
849 | into PC (the address / regnum) so that a request for PC will be | |
850 | converted into a request for the RA. */ | |
851 | info->saved_regs[MS1_PC_REGNUM] = info->saved_regs[MS1_RA_REGNUM]; | |
852 | ||
853 | return info; | |
854 | } | |
855 | ||
856 | static CORE_ADDR | |
857 | ms1_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
858 | { | |
859 | ULONGEST pc; | |
860 | ||
861 | frame_unwind_unsigned_register (next_frame, MS1_PC_REGNUM, &pc); | |
862 | return pc; | |
863 | } | |
864 | ||
865 | static CORE_ADDR | |
866 | ms1_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
867 | { | |
868 | ULONGEST sp; | |
869 | ||
870 | frame_unwind_unsigned_register (next_frame, MS1_SP_REGNUM, &sp); | |
871 | return sp; | |
872 | } | |
873 | ||
874 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
875 | dummy frame. The frame ID's base needs to match the TOS value | |
876 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
877 | breakpoint. */ | |
878 | ||
879 | static struct frame_id | |
880 | ms1_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
881 | { | |
882 | return frame_id_build (ms1_unwind_sp (gdbarch, next_frame), | |
883 | frame_pc_unwind (next_frame)); | |
884 | } | |
885 | ||
886 | /* Given a GDB frame, determine the address of the calling function's | |
887 | frame. This will be used to create a new GDB frame struct. */ | |
888 | ||
889 | static void | |
890 | ms1_frame_this_id (struct frame_info *next_frame, | |
891 | void **this_prologue_cache, struct frame_id *this_id) | |
892 | { | |
893 | struct ms1_unwind_cache *info = | |
894 | ms1_frame_unwind_cache (next_frame, this_prologue_cache); | |
895 | ||
896 | if (!(info == NULL || info->prev_sp == 0)) | |
897 | { | |
898 | (*this_id) = frame_id_build (info->prev_sp, | |
899 | frame_func_unwind (next_frame)); | |
900 | } | |
901 | return; | |
902 | } | |
903 | ||
904 | static void | |
905 | ms1_frame_prev_register (struct frame_info *next_frame, | |
906 | void **this_prologue_cache, | |
907 | int regnum, int *optimizedp, | |
908 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
909 | int *realnump, gdb_byte *bufferp) | |
910 | { | |
911 | struct ms1_unwind_cache *info = | |
912 | ms1_frame_unwind_cache (next_frame, this_prologue_cache); | |
913 | ||
914 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
915 | optimizedp, lvalp, addrp, realnump, bufferp); | |
916 | } | |
917 | ||
918 | static CORE_ADDR | |
919 | ms1_frame_base_address (struct frame_info *next_frame, | |
920 | void **this_prologue_cache) | |
921 | { | |
922 | struct ms1_unwind_cache *info = | |
923 | ms1_frame_unwind_cache (next_frame, this_prologue_cache); | |
924 | ||
925 | return info->frame_base; | |
926 | } | |
927 | ||
928 | /* This is a shared interface: the 'frame_unwind' object is what's | |
929 | returned by the 'sniffer' function, and in turn specifies how to | |
930 | get a frame's ID and prev_regs. | |
931 | ||
932 | This exports the 'prev_register' and 'this_id' methods. */ | |
933 | ||
934 | static const struct frame_unwind ms1_frame_unwind = { | |
935 | NORMAL_FRAME, | |
936 | ms1_frame_this_id, | |
937 | ms1_frame_prev_register | |
938 | }; | |
939 | ||
940 | /* The sniffer is a registered function that identifies our family of | |
941 | frame unwind functions (this_id and prev_register). */ | |
942 | ||
943 | static const struct frame_unwind * | |
944 | ms1_frame_sniffer (struct frame_info *next_frame) | |
945 | { | |
946 | return &ms1_frame_unwind; | |
947 | } | |
948 | ||
949 | /* Another shared interface: the 'frame_base' object specifies how to | |
950 | unwind a frame and secure the base addresses for frame objects | |
951 | (locals, args). */ | |
952 | ||
953 | static struct frame_base ms1_frame_base = { | |
954 | &ms1_frame_unwind, | |
955 | ms1_frame_base_address, | |
956 | ms1_frame_base_address, | |
957 | ms1_frame_base_address | |
958 | }; | |
959 | ||
960 | static struct gdbarch * | |
961 | ms1_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
962 | { | |
963 | struct gdbarch *gdbarch; | |
964 | static void ms1_frame_unwind_init (struct gdbarch *); | |
965 | ||
966 | /* Find a candidate among the list of pre-declared architectures. */ | |
967 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
968 | if (arches != NULL) | |
969 | return arches->gdbarch; | |
970 | ||
971 | /* None found, create a new architecture from the information | |
972 | provided. */ | |
973 | gdbarch = gdbarch_alloc (&info, NULL); | |
974 | ||
975 | switch (info.byte_order) | |
976 | { | |
977 | case BFD_ENDIAN_BIG: | |
978 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
979 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
980 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
981 | break; | |
982 | case BFD_ENDIAN_LITTLE: | |
983 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
984 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
985 | set_gdbarch_long_double_format (gdbarch, | |
986 | &floatformat_ieee_double_little); | |
987 | break; | |
988 | default: | |
989 | internal_error (__FILE__, __LINE__, | |
990 | _("ms1_gdbarch_init: bad byte order for float format")); | |
991 | } | |
992 | ||
993 | set_gdbarch_register_name (gdbarch, ms1_register_name); | |
994 | set_gdbarch_num_regs (gdbarch, MS1_NUM_REGS); | |
995 | set_gdbarch_num_pseudo_regs (gdbarch, MS1_NUM_PSEUDO_REGS); | |
996 | set_gdbarch_pc_regnum (gdbarch, MS1_PC_REGNUM); | |
997 | set_gdbarch_sp_regnum (gdbarch, MS1_SP_REGNUM); | |
998 | set_gdbarch_pseudo_register_read (gdbarch, ms1_pseudo_register_read); | |
999 | set_gdbarch_pseudo_register_write (gdbarch, ms1_pseudo_register_write); | |
1000 | set_gdbarch_skip_prologue (gdbarch, ms1_skip_prologue); | |
1001 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1002 | set_gdbarch_breakpoint_from_pc (gdbarch, ms1_breakpoint_from_pc); | |
1003 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
1004 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1005 | set_gdbarch_print_insn (gdbarch, print_insn_ms1); | |
1006 | set_gdbarch_register_type (gdbarch, ms1_register_type); | |
1007 | set_gdbarch_register_reggroup_p (gdbarch, ms1_register_reggroup_p); | |
1008 | ||
1009 | set_gdbarch_return_value (gdbarch, ms1_return_value); | |
1010 | set_gdbarch_sp_regnum (gdbarch, MS1_SP_REGNUM); | |
1011 | ||
1012 | set_gdbarch_frame_align (gdbarch, ms1_frame_align); | |
1013 | ||
1014 | set_gdbarch_print_registers_info (gdbarch, ms1_registers_info); | |
1015 | ||
1016 | set_gdbarch_push_dummy_call (gdbarch, ms1_push_dummy_call); | |
1017 | ||
1018 | /* Target builtin data types. */ | |
1019 | set_gdbarch_short_bit (gdbarch, 16); | |
1020 | set_gdbarch_int_bit (gdbarch, 32); | |
1021 | set_gdbarch_long_bit (gdbarch, 32); | |
1022 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1023 | set_gdbarch_float_bit (gdbarch, 32); | |
1024 | set_gdbarch_double_bit (gdbarch, 64); | |
1025 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1026 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1027 | ||
1028 | /* Register the DWARF 2 sniffer first, and then the traditional prologue | |
1029 | based sniffer. */ | |
1030 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
1031 | frame_unwind_append_sniffer (gdbarch, ms1_frame_sniffer); | |
1032 | frame_base_set_default (gdbarch, &ms1_frame_base); | |
1033 | ||
1034 | /* Register the 'unwind_pc' method. */ | |
1035 | set_gdbarch_unwind_pc (gdbarch, ms1_unwind_pc); | |
1036 | set_gdbarch_unwind_sp (gdbarch, ms1_unwind_sp); | |
1037 | ||
1038 | /* Methods for saving / extracting a dummy frame's ID. | |
1039 | The ID's stack address must match the SP value returned by | |
1040 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
1041 | set_gdbarch_unwind_dummy_id (gdbarch, ms1_unwind_dummy_id); | |
1042 | ||
1043 | return gdbarch; | |
1044 | } | |
1045 | ||
1046 | void | |
1047 | _initialize_ms1_tdep (void) | |
1048 | { | |
1049 | register_gdbarch_init (bfd_arch_ms1, ms1_gdbarch_init); | |
1050 | } |