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d031aafb | 1 | /* Target-dependent code for Morpho mt processor, for GDB. |
61def6bd | 2 | |
61baf725 | 3 | Copyright (C) 2005-2017 Free Software Foundation, Inc. |
61def6bd KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
61def6bd KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
61def6bd KB |
19 | |
20 | /* Contributed by Michael Snyder, msnyder@redhat.com. */ | |
21 | ||
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "frame-unwind.h" | |
25 | #include "frame-base.h" | |
26 | #include "symtab.h" | |
27 | #include "dis-asm.h" | |
28 | #include "arch-utils.h" | |
29 | #include "gdbtypes.h" | |
61def6bd KB |
30 | #include "regcache.h" |
31 | #include "reggroups.h" | |
32 | #include "gdbcore.h" | |
33 | #include "trad-frame.h" | |
34 | #include "inferior.h" | |
35 | #include "dwarf2-frame.h" | |
36 | #include "infcall.h" | |
d8ca156b | 37 | #include "language.h" |
79a45b7d | 38 | #include "valprint.h" |
42518ba7 | 39 | #include "common/byte-vector.h" |
61def6bd | 40 | |
d031aafb | 41 | enum mt_arch_constants |
61def6bd | 42 | { |
d031aafb | 43 | MT_MAX_STRUCT_SIZE = 16 |
61def6bd KB |
44 | }; |
45 | ||
d031aafb | 46 | enum mt_gdb_regnums |
61def6bd | 47 | { |
d031aafb NS |
48 | MT_R0_REGNUM, /* 32 bit regs. */ |
49 | MT_R1_REGNUM, | |
50 | MT_1ST_ARGREG = MT_R1_REGNUM, | |
51 | MT_R2_REGNUM, | |
52 | MT_R3_REGNUM, | |
53 | MT_R4_REGNUM, | |
54 | MT_LAST_ARGREG = MT_R4_REGNUM, | |
55 | MT_R5_REGNUM, | |
56 | MT_R6_REGNUM, | |
57 | MT_R7_REGNUM, | |
58 | MT_R8_REGNUM, | |
59 | MT_R9_REGNUM, | |
60 | MT_R10_REGNUM, | |
61 | MT_R11_REGNUM, | |
62 | MT_R12_REGNUM, | |
63 | MT_FP_REGNUM = MT_R12_REGNUM, | |
64 | MT_R13_REGNUM, | |
65 | MT_SP_REGNUM = MT_R13_REGNUM, | |
66 | MT_R14_REGNUM, | |
67 | MT_RA_REGNUM = MT_R14_REGNUM, | |
68 | MT_R15_REGNUM, | |
69 | MT_IRA_REGNUM = MT_R15_REGNUM, | |
70 | MT_PC_REGNUM, | |
61def6bd KB |
71 | |
72 | /* Interrupt Enable pseudo-register, exported by SID. */ | |
d031aafb | 73 | MT_INT_ENABLE_REGNUM, |
61def6bd KB |
74 | /* End of CPU regs. */ |
75 | ||
d031aafb | 76 | MT_NUM_CPU_REGS, |
61def6bd KB |
77 | |
78 | /* Co-processor registers. */ | |
d031aafb NS |
79 | MT_COPRO_REGNUM = MT_NUM_CPU_REGS, /* 16 bit regs. */ |
80 | MT_CPR0_REGNUM, | |
81 | MT_CPR1_REGNUM, | |
82 | MT_CPR2_REGNUM, | |
83 | MT_CPR3_REGNUM, | |
84 | MT_CPR4_REGNUM, | |
85 | MT_CPR5_REGNUM, | |
86 | MT_CPR6_REGNUM, | |
87 | MT_CPR7_REGNUM, | |
88 | MT_CPR8_REGNUM, | |
89 | MT_CPR9_REGNUM, | |
90 | MT_CPR10_REGNUM, | |
91 | MT_CPR11_REGNUM, | |
92 | MT_CPR12_REGNUM, | |
93 | MT_CPR13_REGNUM, | |
94 | MT_CPR14_REGNUM, | |
95 | MT_CPR15_REGNUM, | |
96 | MT_BYPA_REGNUM, /* 32 bit regs. */ | |
97 | MT_BYPB_REGNUM, | |
98 | MT_BYPC_REGNUM, | |
99 | MT_FLAG_REGNUM, | |
100 | MT_CONTEXT_REGNUM, /* 38 bits (treat as array of | |
61def6bd | 101 | six bytes). */ |
d031aafb NS |
102 | MT_MAC_REGNUM, /* 32 bits. */ |
103 | MT_Z1_REGNUM, /* 16 bits. */ | |
104 | MT_Z2_REGNUM, /* 16 bits. */ | |
105 | MT_ICHANNEL_REGNUM, /* 32 bits. */ | |
106 | MT_ISCRAMB_REGNUM, /* 32 bits. */ | |
107 | MT_QSCRAMB_REGNUM, /* 32 bits. */ | |
108 | MT_OUT_REGNUM, /* 16 bits. */ | |
109 | MT_EXMAC_REGNUM, /* 32 bits (8 used). */ | |
110 | MT_QCHANNEL_REGNUM, /* 32 bits. */ | |
03a73f77 MM |
111 | MT_ZI2_REGNUM, /* 16 bits. */ |
112 | MT_ZQ2_REGNUM, /* 16 bits. */ | |
113 | MT_CHANNEL2_REGNUM, /* 32 bits. */ | |
114 | MT_ISCRAMB2_REGNUM, /* 32 bits. */ | |
115 | MT_QSCRAMB2_REGNUM, /* 32 bits. */ | |
116 | MT_QCHANNEL2_REGNUM, /* 32 bits. */ | |
61def6bd KB |
117 | |
118 | /* Number of real registers. */ | |
d031aafb | 119 | MT_NUM_REGS, |
61def6bd KB |
120 | |
121 | /* Pseudo-registers. */ | |
d031aafb NS |
122 | MT_COPRO_PSEUDOREG_REGNUM = MT_NUM_REGS, |
123 | MT_MAC_PSEUDOREG_REGNUM, | |
60e81fcc NS |
124 | MT_COPRO_PSEUDOREG_ARRAY, |
125 | ||
126 | MT_COPRO_PSEUDOREG_DIM_1 = 2, | |
127 | MT_COPRO_PSEUDOREG_DIM_2 = 8, | |
03a73f77 MM |
128 | /* The number of pseudo-registers for each coprocessor. These |
129 | include the real coprocessor registers, the pseudo-registe for | |
130 | the coprocessor number, and the pseudo-register for the MAC. */ | |
131 | MT_COPRO_PSEUDOREG_REGS = MT_NUM_REGS - MT_NUM_CPU_REGS + 2, | |
132 | /* The register number of the MAC, relative to a given coprocessor. */ | |
133 | MT_COPRO_PSEUDOREG_MAC_REGNUM = MT_COPRO_PSEUDOREG_REGS - 1, | |
61def6bd KB |
134 | |
135 | /* Two pseudo-regs ('coprocessor' and 'mac'). */ | |
60e81fcc NS |
136 | MT_NUM_PSEUDO_REGS = 2 + (MT_COPRO_PSEUDOREG_REGS |
137 | * MT_COPRO_PSEUDOREG_DIM_1 | |
138 | * MT_COPRO_PSEUDOREG_DIM_2) | |
61def6bd KB |
139 | }; |
140 | ||
df4df182 UW |
141 | /* The tdep structure. */ |
142 | struct gdbarch_tdep | |
143 | { | |
144 | /* ISA-specific types. */ | |
145 | struct type *copro_type; | |
146 | }; | |
147 | ||
148 | ||
61def6bd KB |
149 | /* Return name of register number specified by REGNUM. */ |
150 | ||
151 | static const char * | |
d93859e2 | 152 | mt_register_name (struct gdbarch *gdbarch, int regnum) |
61def6bd | 153 | { |
58b78171 | 154 | static const char *const register_names[] = { |
61def6bd KB |
155 | /* CPU regs. */ |
156 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
157 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
158 | "pc", "IE", | |
159 | /* Co-processor regs. */ | |
160 | "", /* copro register. */ | |
161 | "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", | |
162 | "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15", | |
163 | "bypa", "bypb", "bypc", "flag", "context", "" /* mac. */ , "z1", "z2", | |
164 | "Ichannel", "Iscramb", "Qscramb", "out", "" /* ex-mac. */ , "Qchannel", | |
03a73f77 | 165 | "zi2", "zq2", "Ichannel2", "Iscramb2", "Qscramb2", "Qchannel2", |
61def6bd KB |
166 | /* Pseudo-registers. */ |
167 | "coprocessor", "MAC" | |
168 | }; | |
60e81fcc NS |
169 | static const char *array_names[MT_COPRO_PSEUDOREG_REGS |
170 | * MT_COPRO_PSEUDOREG_DIM_1 | |
171 | * MT_COPRO_PSEUDOREG_DIM_2]; | |
172 | ||
173 | if (regnum < 0) | |
174 | return ""; | |
175 | if (regnum < ARRAY_SIZE (register_names)) | |
176 | return register_names[regnum]; | |
177 | if (array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY]) | |
178 | return array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY]; | |
179 | ||
180 | { | |
181 | char *name; | |
182 | const char *stub; | |
183 | unsigned dim_1; | |
184 | unsigned dim_2; | |
185 | unsigned index; | |
186 | ||
187 | regnum -= MT_COPRO_PSEUDOREG_ARRAY; | |
188 | index = regnum % MT_COPRO_PSEUDOREG_REGS; | |
189 | dim_2 = (regnum / MT_COPRO_PSEUDOREG_REGS) % MT_COPRO_PSEUDOREG_DIM_2; | |
190 | dim_1 = ((regnum / MT_COPRO_PSEUDOREG_REGS / MT_COPRO_PSEUDOREG_DIM_2) | |
191 | % MT_COPRO_PSEUDOREG_DIM_1); | |
192 | ||
03a73f77 | 193 | if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM) |
60e81fcc | 194 | stub = register_names[MT_MAC_PSEUDOREG_REGNUM]; |
03a73f77 | 195 | else if (index >= MT_NUM_REGS - MT_CPR0_REGNUM) |
60e81fcc NS |
196 | stub = ""; |
197 | else | |
198 | stub = register_names[index + MT_CPR0_REGNUM]; | |
199 | if (!*stub) | |
200 | { | |
201 | array_names[regnum] = stub; | |
202 | return stub; | |
203 | } | |
224c3ddb | 204 | name = (char *) xmalloc (30); |
60e81fcc NS |
205 | sprintf (name, "copro_%d_%d_%s", dim_1, dim_2, stub); |
206 | array_names[regnum] = name; | |
207 | return name; | |
208 | } | |
209 | } | |
61def6bd | 210 | |
60e81fcc NS |
211 | /* Return the type of a coprocessor register. */ |
212 | ||
213 | static struct type * | |
214 | mt_copro_register_type (struct gdbarch *arch, int regnum) | |
215 | { | |
216 | switch (regnum) | |
217 | { | |
218 | case MT_INT_ENABLE_REGNUM: | |
219 | case MT_ICHANNEL_REGNUM: | |
220 | case MT_QCHANNEL_REGNUM: | |
221 | case MT_ISCRAMB_REGNUM: | |
222 | case MT_QSCRAMB_REGNUM: | |
df4df182 | 223 | return builtin_type (arch)->builtin_int32; |
60e81fcc NS |
224 | case MT_BYPA_REGNUM: |
225 | case MT_BYPB_REGNUM: | |
226 | case MT_BYPC_REGNUM: | |
227 | case MT_Z1_REGNUM: | |
228 | case MT_Z2_REGNUM: | |
229 | case MT_OUT_REGNUM: | |
03a73f77 MM |
230 | case MT_ZI2_REGNUM: |
231 | case MT_ZQ2_REGNUM: | |
df4df182 | 232 | return builtin_type (arch)->builtin_int16; |
60e81fcc NS |
233 | case MT_EXMAC_REGNUM: |
234 | case MT_MAC_REGNUM: | |
df4df182 | 235 | return builtin_type (arch)->builtin_uint32; |
60e81fcc | 236 | case MT_CONTEXT_REGNUM: |
0dfff4cb | 237 | return builtin_type (arch)->builtin_long_long; |
60e81fcc | 238 | case MT_FLAG_REGNUM: |
0dfff4cb | 239 | return builtin_type (arch)->builtin_unsigned_char; |
60e81fcc NS |
240 | default: |
241 | if (regnum >= MT_CPR0_REGNUM && regnum <= MT_CPR15_REGNUM) | |
df4df182 | 242 | return builtin_type (arch)->builtin_int16; |
03a73f77 | 243 | else if (regnum == MT_CPR0_REGNUM + MT_COPRO_PSEUDOREG_MAC_REGNUM) |
60e81fcc NS |
244 | { |
245 | if (gdbarch_bfd_arch_info (arch)->mach == bfd_mach_mrisc2 | |
246 | || gdbarch_bfd_arch_info (arch)->mach == bfd_mach_ms2) | |
df4df182 | 247 | return builtin_type (arch)->builtin_uint64; |
60e81fcc | 248 | else |
df4df182 | 249 | return builtin_type (arch)->builtin_uint32; |
60e81fcc NS |
250 | } |
251 | else | |
df4df182 | 252 | return builtin_type (arch)->builtin_uint32; |
60e81fcc | 253 | } |
61def6bd KB |
254 | } |
255 | ||
256 | /* Given ARCH and a register number specified by REGNUM, return the | |
257 | type of that register. */ | |
258 | ||
259 | static struct type * | |
d031aafb | 260 | mt_register_type (struct gdbarch *arch, int regnum) |
61def6bd | 261 | { |
df4df182 | 262 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
61def6bd | 263 | |
d031aafb | 264 | if (regnum >= 0 && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS) |
61def6bd | 265 | { |
61def6bd KB |
266 | switch (regnum) |
267 | { | |
d031aafb NS |
268 | case MT_PC_REGNUM: |
269 | case MT_RA_REGNUM: | |
270 | case MT_IRA_REGNUM: | |
fde6c819 | 271 | return builtin_type (arch)->builtin_func_ptr; |
d031aafb NS |
272 | case MT_SP_REGNUM: |
273 | case MT_FP_REGNUM: | |
fde6c819 | 274 | return builtin_type (arch)->builtin_data_ptr; |
d031aafb NS |
275 | case MT_COPRO_REGNUM: |
276 | case MT_COPRO_PSEUDOREG_REGNUM: | |
df4df182 UW |
277 | if (tdep->copro_type == NULL) |
278 | { | |
279 | struct type *elt = builtin_type (arch)->builtin_int16; | |
280 | tdep->copro_type = lookup_array_range_type (elt, 0, 1); | |
281 | } | |
282 | return tdep->copro_type; | |
d031aafb | 283 | case MT_MAC_PSEUDOREG_REGNUM: |
60e81fcc NS |
284 | return mt_copro_register_type (arch, |
285 | MT_CPR0_REGNUM | |
03a73f77 | 286 | + MT_COPRO_PSEUDOREG_MAC_REGNUM); |
61def6bd | 287 | default: |
d031aafb | 288 | if (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM) |
df4df182 | 289 | return builtin_type (arch)->builtin_int32; |
60e81fcc NS |
290 | else if (regnum < MT_COPRO_PSEUDOREG_ARRAY) |
291 | return mt_copro_register_type (arch, regnum); | |
292 | else | |
293 | { | |
294 | regnum -= MT_COPRO_PSEUDOREG_ARRAY; | |
295 | regnum %= MT_COPRO_PSEUDOREG_REGS; | |
296 | regnum += MT_CPR0_REGNUM; | |
297 | return mt_copro_register_type (arch, regnum); | |
298 | } | |
61def6bd KB |
299 | } |
300 | } | |
301 | internal_error (__FILE__, __LINE__, | |
d031aafb | 302 | _("mt_register_type: illegal register number %d"), regnum); |
61def6bd KB |
303 | } |
304 | ||
305 | /* Return true if register REGNUM is a member of the register group | |
306 | specified by GROUP. */ | |
307 | ||
308 | static int | |
d031aafb | 309 | mt_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
61def6bd KB |
310 | struct reggroup *group) |
311 | { | |
312 | /* Groups of registers that can be displayed via "info reg". */ | |
313 | if (group == all_reggroup) | |
314 | return (regnum >= 0 | |
d031aafb | 315 | && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS |
d93859e2 | 316 | && mt_register_name (gdbarch, regnum)[0] != '\0'); |
61def6bd KB |
317 | |
318 | if (group == general_reggroup) | |
d031aafb | 319 | return (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM); |
61def6bd KB |
320 | |
321 | if (group == float_reggroup) | |
322 | return 0; /* No float regs. */ | |
323 | ||
324 | if (group == vector_reggroup) | |
325 | return 0; /* No vector regs. */ | |
326 | ||
327 | /* For any that are not handled above. */ | |
328 | return default_register_reggroup_p (gdbarch, regnum, group); | |
329 | } | |
330 | ||
331 | /* Return the return value convention used for a given type TYPE. | |
332 | Optionally, fetch or set the return value via READBUF or | |
333 | WRITEBUF respectively using REGCACHE for the register | |
334 | values. */ | |
335 | ||
336 | static enum return_value_convention | |
6a3a010b | 337 | mt_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
338 | struct type *type, struct regcache *regcache, |
339 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
61def6bd | 340 | { |
e17a4113 UW |
341 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
342 | ||
61def6bd KB |
343 | if (TYPE_LENGTH (type) > 4) |
344 | { | |
345 | /* Return values > 4 bytes are returned in memory, | |
346 | pointed to by R11. */ | |
347 | if (readbuf) | |
348 | { | |
349 | ULONGEST addr; | |
350 | ||
d031aafb | 351 | regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr); |
61def6bd KB |
352 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
353 | } | |
354 | ||
355 | if (writebuf) | |
356 | { | |
357 | ULONGEST addr; | |
358 | ||
d031aafb | 359 | regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr); |
61def6bd KB |
360 | write_memory (addr, writebuf, TYPE_LENGTH (type)); |
361 | } | |
362 | ||
363 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
364 | } | |
365 | else | |
366 | { | |
367 | if (readbuf) | |
368 | { | |
369 | ULONGEST temp; | |
370 | ||
371 | /* Return values of <= 4 bytes are returned in R11. */ | |
d031aafb | 372 | regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &temp); |
e17a4113 UW |
373 | store_unsigned_integer (readbuf, TYPE_LENGTH (type), |
374 | byte_order, temp); | |
61def6bd KB |
375 | } |
376 | ||
377 | if (writebuf) | |
378 | { | |
379 | if (TYPE_LENGTH (type) < 4) | |
380 | { | |
381 | gdb_byte buf[4]; | |
382 | /* Add leading zeros to the value. */ | |
383 | memset (buf, 0, sizeof (buf)); | |
384 | memcpy (buf + sizeof (buf) - TYPE_LENGTH (type), | |
385 | writebuf, TYPE_LENGTH (type)); | |
d031aafb | 386 | regcache_cooked_write (regcache, MT_R11_REGNUM, buf); |
61def6bd KB |
387 | } |
388 | else /* (TYPE_LENGTH (type) == 4 */ | |
d031aafb | 389 | regcache_cooked_write (regcache, MT_R11_REGNUM, writebuf); |
61def6bd KB |
390 | } |
391 | ||
392 | return RETURN_VALUE_REGISTER_CONVENTION; | |
393 | } | |
394 | } | |
395 | ||
396 | /* If the input address, PC, is in a function prologue, return the | |
397 | address of the end of the prologue, otherwise return the input | |
398 | address. | |
399 | ||
400 | Note: PC is likely to be the function start, since this function | |
401 | is mainly used for advancing a breakpoint to the first line, or | |
402 | stepping to the first line when we have stepped into a function | |
403 | call. */ | |
404 | ||
405 | static CORE_ADDR | |
6093d2eb | 406 | mt_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
61def6bd | 407 | { |
e17a4113 | 408 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
61def6bd | 409 | CORE_ADDR func_addr = 0, func_end = 0; |
2c02bd72 | 410 | const char *func_name; |
61def6bd KB |
411 | unsigned long instr; |
412 | ||
413 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) | |
414 | { | |
415 | struct symtab_and_line sal; | |
416 | struct symbol *sym; | |
417 | ||
418 | /* Found a function. */ | |
835a09d9 | 419 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL).symbol; |
61def6bd KB |
420 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
421 | { | |
422 | /* Don't use this trick for assembly source files. */ | |
423 | sal = find_pc_line (func_addr, 0); | |
424 | ||
425 | if (sal.end && sal.end < func_end) | |
426 | { | |
427 | /* Found a line number, use it as end of prologue. */ | |
428 | return sal.end; | |
429 | } | |
430 | } | |
431 | } | |
432 | ||
433 | /* No function symbol, or no line symbol. Use prologue scanning method. */ | |
434 | for (;; pc += 4) | |
435 | { | |
e17a4113 | 436 | instr = read_memory_unsigned_integer (pc, 4, byte_order); |
61def6bd KB |
437 | if (instr == 0x12000000) /* nop */ |
438 | continue; | |
439 | if (instr == 0x12ddc000) /* copy sp into fp */ | |
440 | continue; | |
441 | instr >>= 16; | |
442 | if (instr == 0x05dd) /* subi sp, sp, imm */ | |
443 | continue; | |
444 | if (instr >= 0x43c0 && instr <= 0x43df) /* push */ | |
445 | continue; | |
446 | /* Not an obvious prologue instruction. */ | |
447 | break; | |
448 | } | |
449 | ||
450 | return pc; | |
451 | } | |
452 | ||
cd6c3b4f YQ |
453 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
454 | ||
d19280ad YQ |
455 | static int |
456 | mt_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
457 | { | |
458 | return 4; | |
459 | } | |
61def6bd | 460 | |
cd6c3b4f YQ |
461 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
462 | ||
61def6bd | 463 | static const gdb_byte * |
d19280ad | 464 | mt_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
61def6bd | 465 | { |
d19280ad YQ |
466 | /* The breakpoint instruction must be the same size as the smallest |
467 | instruction in the instruction set. | |
468 | ||
469 | The BP for ms1 is defined as 0x68000000 (BREAK). | |
470 | The BP for ms2 is defined as 0x69000000 (illegal). */ | |
3950dc3f NS |
471 | static gdb_byte ms1_breakpoint[] = { 0x68, 0, 0, 0 }; |
472 | static gdb_byte ms2_breakpoint[] = { 0x69, 0, 0, 0 }; | |
61def6bd | 473 | |
d19280ad YQ |
474 | *size = kind; |
475 | ||
67d57894 | 476 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) |
3950dc3f | 477 | return ms2_breakpoint; |
d19280ad | 478 | |
3950dc3f | 479 | return ms1_breakpoint; |
61def6bd KB |
480 | } |
481 | ||
60e81fcc NS |
482 | /* Select the correct coprocessor register bank. Return the pseudo |
483 | regnum we really want to read. */ | |
484 | ||
485 | static int | |
486 | mt_select_coprocessor (struct gdbarch *gdbarch, | |
487 | struct regcache *regcache, int regno) | |
488 | { | |
e17a4113 | 489 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
60e81fcc NS |
490 | unsigned index, base; |
491 | gdb_byte copro[4]; | |
492 | ||
025bb325 | 493 | /* Get the copro pseudo regnum. */ |
60e81fcc | 494 | regcache_raw_read (regcache, MT_COPRO_REGNUM, copro); |
e17a4113 UW |
495 | base = ((extract_signed_integer (&copro[0], 2, byte_order) |
496 | * MT_COPRO_PSEUDOREG_DIM_2) | |
497 | + extract_signed_integer (&copro[2], 2, byte_order)); | |
60e81fcc NS |
498 | |
499 | regno -= MT_COPRO_PSEUDOREG_ARRAY; | |
500 | index = regno % MT_COPRO_PSEUDOREG_REGS; | |
501 | regno /= MT_COPRO_PSEUDOREG_REGS; | |
502 | if (base != regno) | |
503 | { | |
504 | /* Select the correct coprocessor register bank. Invalidate the | |
505 | coprocessor register cache. */ | |
506 | unsigned ix; | |
507 | ||
e17a4113 UW |
508 | store_signed_integer (&copro[0], 2, byte_order, |
509 | regno / MT_COPRO_PSEUDOREG_DIM_2); | |
510 | store_signed_integer (&copro[2], 2, byte_order, | |
511 | regno % MT_COPRO_PSEUDOREG_DIM_2); | |
60e81fcc NS |
512 | regcache_raw_write (regcache, MT_COPRO_REGNUM, copro); |
513 | ||
514 | /* We must flush the cache, as it is now invalid. */ | |
515 | for (ix = MT_NUM_CPU_REGS; ix != MT_NUM_REGS; ix++) | |
9c5ea4d9 | 516 | regcache_invalidate (regcache, ix); |
60e81fcc NS |
517 | } |
518 | ||
519 | return index; | |
520 | } | |
521 | ||
61def6bd KB |
522 | /* Fetch the pseudo registers: |
523 | ||
60e81fcc | 524 | There are two regular pseudo-registers: |
61def6bd KB |
525 | 1) The 'coprocessor' pseudo-register (which mirrors the |
526 | "real" coprocessor register sent by the target), and | |
527 | 2) The 'MAC' pseudo-register (which represents the union | |
528 | of the original 32 bit target MAC register and the new | |
60e81fcc NS |
529 | 8-bit extended-MAC register). |
530 | ||
531 | Additionally there is an array of coprocessor registers which track | |
532 | the coprocessor registers for each coprocessor. */ | |
61def6bd | 533 | |
05d1431c | 534 | static enum register_status |
d031aafb | 535 | mt_pseudo_register_read (struct gdbarch *gdbarch, |
05d1431c | 536 | struct regcache *regcache, int regno, gdb_byte *buf) |
61def6bd | 537 | { |
e17a4113 UW |
538 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
539 | ||
61def6bd KB |
540 | switch (regno) |
541 | { | |
d031aafb NS |
542 | case MT_COPRO_REGNUM: |
543 | case MT_COPRO_PSEUDOREG_REGNUM: | |
05d1431c | 544 | return regcache_raw_read (regcache, MT_COPRO_REGNUM, buf); |
d031aafb NS |
545 | case MT_MAC_REGNUM: |
546 | case MT_MAC_PSEUDOREG_REGNUM: | |
3950dc3f NS |
547 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2 |
548 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) | |
61def6bd | 549 | { |
05d1431c | 550 | enum register_status status; |
61def6bd KB |
551 | ULONGEST oldmac = 0, ext_mac = 0; |
552 | ULONGEST newmac; | |
553 | ||
05d1431c PA |
554 | status = regcache_cooked_read_unsigned (regcache, MT_MAC_REGNUM, &oldmac); |
555 | if (status != REG_VALID) | |
556 | return status; | |
557 | ||
d031aafb | 558 | regcache_cooked_read_unsigned (regcache, MT_EXMAC_REGNUM, &ext_mac); |
05d1431c PA |
559 | if (status != REG_VALID) |
560 | return status; | |
561 | ||
61def6bd KB |
562 | newmac = |
563 | (oldmac & 0xffffffff) | ((long long) (ext_mac & 0xff) << 32); | |
e17a4113 | 564 | store_signed_integer (buf, 8, byte_order, newmac); |
05d1431c PA |
565 | |
566 | return REG_VALID; | |
61def6bd KB |
567 | } |
568 | else | |
05d1431c | 569 | return regcache_raw_read (regcache, MT_MAC_REGNUM, buf); |
61def6bd KB |
570 | break; |
571 | default: | |
60e81fcc NS |
572 | { |
573 | unsigned index = mt_select_coprocessor (gdbarch, regcache, regno); | |
574 | ||
03a73f77 | 575 | if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM) |
05d1431c PA |
576 | return mt_pseudo_register_read (gdbarch, regcache, |
577 | MT_MAC_PSEUDOREG_REGNUM, buf); | |
60e81fcc | 578 | else if (index < MT_NUM_REGS - MT_CPR0_REGNUM) |
05d1431c PA |
579 | return regcache_raw_read (regcache, index + MT_CPR0_REGNUM, buf); |
580 | else | |
581 | /* ??? */ | |
582 | return REG_VALID; | |
60e81fcc | 583 | } |
61def6bd KB |
584 | break; |
585 | } | |
586 | } | |
587 | ||
588 | /* Write the pseudo registers: | |
589 | ||
d031aafb | 590 | Mt pseudo-registers are stored directly to the target. The |
61def6bd KB |
591 | 'coprocessor' register is special, because when it is modified, all |
592 | the other coprocessor regs must be flushed from the reg cache. */ | |
593 | ||
594 | static void | |
d031aafb | 595 | mt_pseudo_register_write (struct gdbarch *gdbarch, |
61def6bd KB |
596 | struct regcache *regcache, |
597 | int regno, const gdb_byte *buf) | |
598 | { | |
e17a4113 | 599 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
61def6bd KB |
600 | int i; |
601 | ||
602 | switch (regno) | |
603 | { | |
d031aafb NS |
604 | case MT_COPRO_REGNUM: |
605 | case MT_COPRO_PSEUDOREG_REGNUM: | |
606 | regcache_raw_write (regcache, MT_COPRO_REGNUM, buf); | |
607 | for (i = MT_NUM_CPU_REGS; i < MT_NUM_REGS; i++) | |
9c5ea4d9 | 608 | regcache_invalidate (regcache, i); |
61def6bd | 609 | break; |
d031aafb NS |
610 | case MT_MAC_REGNUM: |
611 | case MT_MAC_PSEUDOREG_REGNUM: | |
3950dc3f NS |
612 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2 |
613 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) | |
61def6bd KB |
614 | { |
615 | /* The 8-byte MAC pseudo-register must be broken down into two | |
616 | 32-byte registers. */ | |
617 | unsigned int oldmac, ext_mac; | |
618 | ULONGEST newmac; | |
619 | ||
e17a4113 | 620 | newmac = extract_unsigned_integer (buf, 8, byte_order); |
61def6bd KB |
621 | oldmac = newmac & 0xffffffff; |
622 | ext_mac = (newmac >> 32) & 0xff; | |
d031aafb NS |
623 | regcache_cooked_write_unsigned (regcache, MT_MAC_REGNUM, oldmac); |
624 | regcache_cooked_write_unsigned (regcache, MT_EXMAC_REGNUM, ext_mac); | |
61def6bd KB |
625 | } |
626 | else | |
d031aafb | 627 | regcache_raw_write (regcache, MT_MAC_REGNUM, buf); |
61def6bd KB |
628 | break; |
629 | default: | |
60e81fcc NS |
630 | { |
631 | unsigned index = mt_select_coprocessor (gdbarch, regcache, regno); | |
632 | ||
03a73f77 | 633 | if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM) |
60e81fcc | 634 | mt_pseudo_register_write (gdbarch, regcache, |
03a73f77 | 635 | MT_MAC_PSEUDOREG_REGNUM, buf); |
60e81fcc NS |
636 | else if (index < MT_NUM_REGS - MT_CPR0_REGNUM) |
637 | regcache_raw_write (regcache, index + MT_CPR0_REGNUM, buf); | |
638 | } | |
61def6bd KB |
639 | break; |
640 | } | |
641 | } | |
642 | ||
643 | static CORE_ADDR | |
d031aafb | 644 | mt_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
61def6bd KB |
645 | { |
646 | /* Register size is 4 bytes. */ | |
647 | return align_down (sp, 4); | |
648 | } | |
649 | ||
650 | /* Implements the "info registers" command. When ``all'' is non-zero, | |
651 | the coprocessor registers will be printed in addition to the rest | |
652 | of the registers. */ | |
653 | ||
654 | static void | |
d031aafb | 655 | mt_registers_info (struct gdbarch *gdbarch, |
d93859e2 UW |
656 | struct ui_file *file, |
657 | struct frame_info *frame, int regnum, int all) | |
61def6bd | 658 | { |
e17a4113 UW |
659 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
660 | ||
61def6bd KB |
661 | if (regnum == -1) |
662 | { | |
663 | int lim; | |
664 | ||
d031aafb | 665 | lim = all ? MT_NUM_REGS : MT_NUM_CPU_REGS; |
61def6bd KB |
666 | |
667 | for (regnum = 0; regnum < lim; regnum++) | |
668 | { | |
669 | /* Don't display the Qchannel register since it will be displayed | |
670 | along with Ichannel. (See below.) */ | |
d031aafb | 671 | if (regnum == MT_QCHANNEL_REGNUM) |
61def6bd KB |
672 | continue; |
673 | ||
d031aafb | 674 | mt_registers_info (gdbarch, file, frame, regnum, all); |
61def6bd KB |
675 | |
676 | /* Display the Qchannel register immediately after Ichannel. */ | |
d031aafb NS |
677 | if (regnum == MT_ICHANNEL_REGNUM) |
678 | mt_registers_info (gdbarch, file, frame, MT_QCHANNEL_REGNUM, all); | |
61def6bd KB |
679 | } |
680 | } | |
681 | else | |
682 | { | |
d031aafb | 683 | if (regnum == MT_EXMAC_REGNUM) |
61def6bd | 684 | return; |
d031aafb | 685 | else if (regnum == MT_CONTEXT_REGNUM) |
61def6bd KB |
686 | { |
687 | /* Special output handling for 38-bit context register. */ | |
688 | unsigned char *buff; | |
870f88f7 | 689 | unsigned int i, regsize; |
61def6bd KB |
690 | |
691 | regsize = register_size (gdbarch, regnum); | |
692 | ||
224c3ddb | 693 | buff = (unsigned char *) alloca (regsize); |
61def6bd | 694 | |
ca9d61b9 | 695 | deprecated_frame_register_read (frame, regnum, buff); |
61def6bd | 696 | |
c9f4d572 | 697 | fputs_filtered (gdbarch_register_name |
d93859e2 | 698 | (gdbarch, regnum), file); |
c9f4d572 | 699 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
d93859e2 | 700 | (gdbarch, regnum)), |
c9f4d572 | 701 | file); |
61def6bd KB |
702 | fputs_filtered ("0x", file); |
703 | ||
704 | for (i = 0; i < regsize; i++) | |
705 | fprintf_filtered (file, "%02x", (unsigned int) | |
e17a4113 | 706 | extract_unsigned_integer (buff + i, 1, byte_order)); |
61def6bd KB |
707 | fputs_filtered ("\t", file); |
708 | print_longest (file, 'd', 0, | |
e17a4113 | 709 | extract_unsigned_integer (buff, regsize, byte_order)); |
61def6bd KB |
710 | fputs_filtered ("\n", file); |
711 | } | |
d031aafb NS |
712 | else if (regnum == MT_COPRO_REGNUM |
713 | || regnum == MT_COPRO_PSEUDOREG_REGNUM) | |
61def6bd KB |
714 | { |
715 | /* Special output handling for the 'coprocessor' register. */ | |
79a45b7d | 716 | struct value_print_options opts; |
cc977dc7 | 717 | struct value *val; |
61def6bd | 718 | |
cc977dc7 | 719 | val = get_frame_register_value (frame, MT_COPRO_REGNUM); |
61def6bd | 720 | /* And print. */ |
d031aafb | 721 | regnum = MT_COPRO_PSEUDOREG_REGNUM; |
d93859e2 | 722 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), |
c9f4d572 UW |
723 | file); |
724 | print_spaces_filtered (15 - strlen (gdbarch_register_name | |
d93859e2 | 725 | (gdbarch, regnum)), |
c9f4d572 | 726 | file); |
915dd369 | 727 | get_no_prettyformat_print_options (&opts); |
79a45b7d | 728 | opts.deref_ref = 1; |
cc977dc7 | 729 | val_print (register_type (gdbarch, regnum), |
cc977dc7 | 730 | 0, 0, file, 0, val, |
0e03807e | 731 | &opts, current_language); |
61def6bd KB |
732 | fputs_filtered ("\n", file); |
733 | } | |
d031aafb | 734 | else if (regnum == MT_MAC_REGNUM || regnum == MT_MAC_PSEUDOREG_REGNUM) |
61def6bd KB |
735 | { |
736 | ULONGEST oldmac, ext_mac, newmac; | |
58b78171 | 737 | gdb_byte buf[3 * sizeof (LONGEST)]; |
61def6bd KB |
738 | |
739 | /* Get the two "real" mac registers. */ | |
ca9d61b9 | 740 | deprecated_frame_register_read (frame, MT_MAC_REGNUM, buf); |
3950dc3f | 741 | oldmac = extract_unsigned_integer |
e17a4113 | 742 | (buf, register_size (gdbarch, MT_MAC_REGNUM), byte_order); |
58b78171 NS |
743 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2 |
744 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) | |
61def6bd | 745 | { |
ca9d61b9 | 746 | deprecated_frame_register_read (frame, MT_EXMAC_REGNUM, buf); |
3950dc3f | 747 | ext_mac = extract_unsigned_integer |
e17a4113 | 748 | (buf, register_size (gdbarch, MT_EXMAC_REGNUM), byte_order); |
61def6bd KB |
749 | } |
750 | else | |
751 | ext_mac = 0; | |
752 | ||
753 | /* Add them together. */ | |
754 | newmac = (oldmac & 0xffffffff) + ((ext_mac & 0xff) << 32); | |
755 | ||
756 | /* And print. */ | |
d031aafb | 757 | regnum = MT_MAC_PSEUDOREG_REGNUM; |
d93859e2 | 758 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), |
c9f4d572 UW |
759 | file); |
760 | print_spaces_filtered (15 - strlen (gdbarch_register_name | |
d93859e2 | 761 | (gdbarch, regnum)), |
c9f4d572 | 762 | file); |
61def6bd KB |
763 | fputs_filtered ("0x", file); |
764 | print_longest (file, 'x', 0, newmac); | |
765 | fputs_filtered ("\t", file); | |
766 | print_longest (file, 'u', 0, newmac); | |
767 | fputs_filtered ("\n", file); | |
768 | } | |
769 | else | |
770 | default_print_registers_info (gdbarch, file, frame, regnum, all); | |
771 | } | |
772 | } | |
773 | ||
774 | /* Set up the callee's arguments for an inferior function call. The | |
775 | arguments are pushed on the stack or are placed in registers as | |
776 | appropriate. It also sets up the return address (which points to | |
777 | the call dummy breakpoint). | |
778 | ||
779 | Returns the updated (and aligned) stack pointer. */ | |
780 | ||
781 | static CORE_ADDR | |
d031aafb | 782 | mt_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
61def6bd KB |
783 | struct regcache *regcache, CORE_ADDR bp_addr, |
784 | int nargs, struct value **args, CORE_ADDR sp, | |
785 | int struct_return, CORE_ADDR struct_addr) | |
786 | { | |
787 | #define wordsize 4 | |
e17a4113 | 788 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d031aafb NS |
789 | gdb_byte buf[MT_MAX_STRUCT_SIZE]; |
790 | int argreg = MT_1ST_ARGREG; | |
61def6bd KB |
791 | int split_param_len = 0; |
792 | int stack_dest = sp; | |
793 | int slacklen; | |
794 | int typelen; | |
795 | int i, j; | |
796 | ||
d031aafb NS |
797 | /* First handle however many args we can fit into MT_1ST_ARGREG thru |
798 | MT_LAST_ARGREG. */ | |
799 | for (i = 0; i < nargs && argreg <= MT_LAST_ARGREG; i++) | |
61def6bd | 800 | { |
58b78171 | 801 | const gdb_byte *val; |
61def6bd KB |
802 | typelen = TYPE_LENGTH (value_type (args[i])); |
803 | switch (typelen) | |
804 | { | |
805 | case 1: | |
806 | case 2: | |
807 | case 3: | |
808 | case 4: | |
809 | regcache_cooked_write_unsigned (regcache, argreg++, | |
810 | extract_unsigned_integer | |
811 | (value_contents (args[i]), | |
e17a4113 | 812 | wordsize, byte_order)); |
61def6bd KB |
813 | break; |
814 | case 8: | |
815 | case 12: | |
816 | case 16: | |
817 | val = value_contents (args[i]); | |
818 | while (typelen > 0) | |
819 | { | |
d031aafb | 820 | if (argreg <= MT_LAST_ARGREG) |
61def6bd KB |
821 | { |
822 | /* This word of the argument is passed in a register. */ | |
823 | regcache_cooked_write_unsigned (regcache, argreg++, | |
824 | extract_unsigned_integer | |
e17a4113 | 825 | (val, wordsize, byte_order)); |
61def6bd KB |
826 | typelen -= wordsize; |
827 | val += wordsize; | |
828 | } | |
829 | else | |
830 | { | |
831 | /* Remainder of this arg must be passed on the stack | |
832 | (deferred to do later). */ | |
833 | split_param_len = typelen; | |
834 | memcpy (buf, val, typelen); | |
835 | break; /* No more args can be handled in regs. */ | |
836 | } | |
837 | } | |
838 | break; | |
839 | default: | |
840 | /* By reverse engineering of gcc output, args bigger than | |
841 | 16 bytes go on the stack, and their address is passed | |
842 | in the argreg. */ | |
843 | stack_dest -= typelen; | |
844 | write_memory (stack_dest, value_contents (args[i]), typelen); | |
845 | regcache_cooked_write_unsigned (regcache, argreg++, stack_dest); | |
846 | break; | |
847 | } | |
848 | } | |
849 | ||
850 | /* Next, the rest of the arguments go onto the stack, in reverse order. */ | |
851 | for (j = nargs - 1; j >= i; j--) | |
852 | { | |
ecfb0d68 | 853 | const gdb_byte *contents = value_contents (args[j]); |
58b78171 | 854 | |
61def6bd KB |
855 | /* Right-justify the value in an aligned-length buffer. */ |
856 | typelen = TYPE_LENGTH (value_type (args[j])); | |
857 | slacklen = (wordsize - (typelen % wordsize)) % wordsize; | |
42518ba7 TT |
858 | gdb::byte_vector val (typelen + slacklen); |
859 | memcpy (val.data (), contents, typelen); | |
860 | memset (val.data () + typelen, 0, slacklen); | |
61def6bd KB |
861 | /* Now write this data to the stack. */ |
862 | stack_dest -= typelen + slacklen; | |
42518ba7 | 863 | write_memory (stack_dest, val.data (), typelen + slacklen); |
61def6bd KB |
864 | } |
865 | ||
866 | /* Finally, if a param needs to be split between registers and stack, | |
867 | write the second half to the stack now. */ | |
868 | if (split_param_len != 0) | |
869 | { | |
870 | stack_dest -= split_param_len; | |
871 | write_memory (stack_dest, buf, split_param_len); | |
872 | } | |
873 | ||
874 | /* Set up return address (provided to us as bp_addr). */ | |
d031aafb | 875 | regcache_cooked_write_unsigned (regcache, MT_RA_REGNUM, bp_addr); |
61def6bd KB |
876 | |
877 | /* Store struct return address, if given. */ | |
878 | if (struct_return && struct_addr != 0) | |
d031aafb | 879 | regcache_cooked_write_unsigned (regcache, MT_R11_REGNUM, struct_addr); |
61def6bd KB |
880 | |
881 | /* Set aside 16 bytes for the callee to save regs 1-4. */ | |
882 | stack_dest -= 16; | |
883 | ||
884 | /* Update the stack pointer. */ | |
d031aafb | 885 | regcache_cooked_write_unsigned (regcache, MT_SP_REGNUM, stack_dest); |
61def6bd KB |
886 | |
887 | /* And that should do it. Return the new stack pointer. */ | |
888 | return stack_dest; | |
889 | } | |
890 | ||
891 | ||
892 | /* The 'unwind_cache' data structure. */ | |
893 | ||
d031aafb | 894 | struct mt_unwind_cache |
61def6bd | 895 | { |
025bb325 | 896 | /* The previous frame's inner most stack address. |
61def6bd KB |
897 | Used as this frame ID's stack_addr. */ |
898 | CORE_ADDR prev_sp; | |
899 | CORE_ADDR frame_base; | |
900 | int framesize; | |
901 | int frameless_p; | |
902 | ||
903 | /* Table indicating the location of each and every register. */ | |
904 | struct trad_frame_saved_reg *saved_regs; | |
905 | }; | |
906 | ||
907 | /* Initialize an unwind_cache. Build up the saved_regs table etc. for | |
908 | the frame. */ | |
909 | ||
d031aafb | 910 | static struct mt_unwind_cache * |
94afd7a6 | 911 | mt_frame_unwind_cache (struct frame_info *this_frame, |
61def6bd KB |
912 | void **this_prologue_cache) |
913 | { | |
914 | struct gdbarch *gdbarch; | |
d031aafb | 915 | struct mt_unwind_cache *info; |
61def6bd KB |
916 | CORE_ADDR next_addr, start_addr, end_addr, prologue_end_addr; |
917 | unsigned long instr, upper_half, delayed_store = 0; | |
918 | int regnum, offset; | |
919 | ULONGEST sp, fp; | |
920 | ||
921 | if ((*this_prologue_cache)) | |
19ba03f4 | 922 | return (struct mt_unwind_cache *) (*this_prologue_cache); |
61def6bd | 923 | |
94afd7a6 | 924 | gdbarch = get_frame_arch (this_frame); |
d031aafb | 925 | info = FRAME_OBSTACK_ZALLOC (struct mt_unwind_cache); |
61def6bd KB |
926 | (*this_prologue_cache) = info; |
927 | ||
928 | info->prev_sp = 0; | |
929 | info->framesize = 0; | |
930 | info->frame_base = 0; | |
931 | info->frameless_p = 1; | |
94afd7a6 | 932 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
61def6bd | 933 | |
025bb325 | 934 | /* Grab the frame-relative values of SP and FP, needed below. |
61def6bd KB |
935 | The frame_saved_register function will find them on the |
936 | stack or in the registers as appropriate. */ | |
94afd7a6 UW |
937 | sp = get_frame_register_unsigned (this_frame, MT_SP_REGNUM); |
938 | fp = get_frame_register_unsigned (this_frame, MT_FP_REGNUM); | |
61def6bd | 939 | |
94afd7a6 | 940 | start_addr = get_frame_func (this_frame); |
61def6bd KB |
941 | |
942 | /* Return early if GDB couldn't find the function. */ | |
943 | if (start_addr == 0) | |
944 | return info; | |
945 | ||
94afd7a6 | 946 | end_addr = get_frame_pc (this_frame); |
d80b854b | 947 | prologue_end_addr = skip_prologue_using_sal (gdbarch, start_addr); |
61def6bd KB |
948 | if (end_addr == 0) |
949 | for (next_addr = start_addr; next_addr < end_addr; next_addr += 4) | |
950 | { | |
94afd7a6 | 951 | instr = get_frame_memory_unsigned (this_frame, next_addr, 4); |
025bb325 | 952 | if (delayed_store) /* Previous instr was a push. */ |
61def6bd KB |
953 | { |
954 | upper_half = delayed_store >> 16; | |
955 | regnum = upper_half & 0xf; | |
956 | offset = delayed_store & 0xffff; | |
957 | switch (upper_half & 0xfff0) | |
958 | { | |
025bb325 | 959 | case 0x43c0: /* push using frame pointer. */ |
61def6bd KB |
960 | info->saved_regs[regnum].addr = offset; |
961 | break; | |
025bb325 | 962 | case 0x43d0: /* push using stack pointer. */ |
61def6bd KB |
963 | info->saved_regs[regnum].addr = offset; |
964 | break; | |
965 | default: /* lint */ | |
966 | break; | |
967 | } | |
968 | delayed_store = 0; | |
969 | } | |
970 | ||
971 | switch (instr) | |
972 | { | |
973 | case 0x12000000: /* NO-OP */ | |
974 | continue; | |
975 | case 0x12ddc000: /* copy sp into fp */ | |
025bb325 MS |
976 | info->frameless_p = 0; /* Record that the frame |
977 | pointer is in use. */ | |
61def6bd KB |
978 | continue; |
979 | default: | |
980 | upper_half = instr >> 16; | |
981 | if (upper_half == 0x05dd || /* subi sp, sp, imm */ | |
982 | upper_half == 0x07dd) /* subui sp, sp, imm */ | |
983 | { | |
984 | /* Record the frame size. */ | |
985 | info->framesize = instr & 0xffff; | |
986 | continue; | |
987 | } | |
988 | if ((upper_half & 0xfff0) == 0x43c0 || /* frame push */ | |
989 | (upper_half & 0xfff0) == 0x43d0) /* stack push */ | |
990 | { | |
991 | /* Save this instruction, but don't record the | |
992 | pushed register as 'saved' until we see the | |
993 | next instruction. That's because of deferred stores | |
994 | on this target -- GDB won't be able to read the register | |
995 | from the stack until one instruction later. */ | |
996 | delayed_store = instr; | |
997 | continue; | |
998 | } | |
999 | /* Not a prologue instruction. Is this the end of the prologue? | |
1000 | This is the most difficult decision; when to stop scanning. | |
1001 | ||
1002 | If we have no line symbol, then the best thing we can do | |
1003 | is to stop scanning when we encounter an instruction that | |
1004 | is not likely to be a part of the prologue. | |
1005 | ||
1006 | But if we do have a line symbol, then we should | |
1007 | keep scanning until we reach it (or we reach end_addr). */ | |
1008 | ||
1009 | if (prologue_end_addr && (prologue_end_addr > (next_addr + 4))) | |
025bb325 | 1010 | continue; /* Keep scanning, recording saved_regs etc. */ |
61def6bd | 1011 | else |
025bb325 | 1012 | break; /* Quit scanning: breakpoint can be set here. */ |
61def6bd KB |
1013 | } |
1014 | } | |
1015 | ||
1016 | /* Special handling for the "saved" address of the SP: | |
1017 | The SP is of course never saved on the stack at all, so | |
1018 | by convention what we put here is simply the previous | |
1019 | _value_ of the SP (as opposed to an address where the | |
1020 | previous value would have been pushed). This will also | |
1021 | give us the frame base address. */ | |
1022 | ||
1023 | if (info->frameless_p) | |
1024 | { | |
1025 | info->frame_base = sp + info->framesize; | |
1026 | info->prev_sp = sp + info->framesize; | |
1027 | } | |
1028 | else | |
1029 | { | |
1030 | info->frame_base = fp + info->framesize; | |
1031 | info->prev_sp = fp + info->framesize; | |
1032 | } | |
1033 | /* Save prev_sp in saved_regs as a value, not as an address. */ | |
d031aafb | 1034 | trad_frame_set_value (info->saved_regs, MT_SP_REGNUM, info->prev_sp); |
61def6bd KB |
1035 | |
1036 | /* Now convert frame offsets to actual addresses (not offsets). */ | |
d031aafb | 1037 | for (regnum = 0; regnum < MT_NUM_REGS; regnum++) |
61def6bd KB |
1038 | if (trad_frame_addr_p (info->saved_regs, regnum)) |
1039 | info->saved_regs[regnum].addr += info->frame_base - info->framesize; | |
1040 | ||
1041 | /* The call instruction moves the caller's PC in the callee's RA reg. | |
1042 | Since this is an unwind, do the reverse. Copy the location of RA | |
1043 | into PC (the address / regnum) so that a request for PC will be | |
1044 | converted into a request for the RA. */ | |
d031aafb | 1045 | info->saved_regs[MT_PC_REGNUM] = info->saved_regs[MT_RA_REGNUM]; |
61def6bd KB |
1046 | |
1047 | return info; | |
1048 | } | |
1049 | ||
1050 | static CORE_ADDR | |
d031aafb | 1051 | mt_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
61def6bd KB |
1052 | { |
1053 | ULONGEST pc; | |
1054 | ||
11411de3 | 1055 | pc = frame_unwind_register_unsigned (next_frame, MT_PC_REGNUM); |
61def6bd KB |
1056 | return pc; |
1057 | } | |
1058 | ||
1059 | static CORE_ADDR | |
d031aafb | 1060 | mt_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
61def6bd KB |
1061 | { |
1062 | ULONGEST sp; | |
1063 | ||
11411de3 | 1064 | sp = frame_unwind_register_unsigned (next_frame, MT_SP_REGNUM); |
61def6bd KB |
1065 | return sp; |
1066 | } | |
1067 | ||
94afd7a6 UW |
1068 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
1069 | frame. The frame ID's base needs to match the TOS value saved by | |
1070 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
61def6bd KB |
1071 | |
1072 | static struct frame_id | |
94afd7a6 | 1073 | mt_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
61def6bd | 1074 | { |
94afd7a6 UW |
1075 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, MT_SP_REGNUM); |
1076 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
61def6bd KB |
1077 | } |
1078 | ||
1079 | /* Given a GDB frame, determine the address of the calling function's | |
1080 | frame. This will be used to create a new GDB frame struct. */ | |
1081 | ||
1082 | static void | |
94afd7a6 | 1083 | mt_frame_this_id (struct frame_info *this_frame, |
61def6bd KB |
1084 | void **this_prologue_cache, struct frame_id *this_id) |
1085 | { | |
d031aafb | 1086 | struct mt_unwind_cache *info = |
94afd7a6 | 1087 | mt_frame_unwind_cache (this_frame, this_prologue_cache); |
61def6bd KB |
1088 | |
1089 | if (!(info == NULL || info->prev_sp == 0)) | |
94afd7a6 | 1090 | (*this_id) = frame_id_build (info->prev_sp, get_frame_func (this_frame)); |
93d42b30 | 1091 | |
61def6bd KB |
1092 | return; |
1093 | } | |
1094 | ||
94afd7a6 UW |
1095 | static struct value * |
1096 | mt_frame_prev_register (struct frame_info *this_frame, | |
1097 | void **this_prologue_cache, int regnum) | |
61def6bd | 1098 | { |
d031aafb | 1099 | struct mt_unwind_cache *info = |
94afd7a6 | 1100 | mt_frame_unwind_cache (this_frame, this_prologue_cache); |
61def6bd | 1101 | |
94afd7a6 | 1102 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
61def6bd KB |
1103 | } |
1104 | ||
1105 | static CORE_ADDR | |
94afd7a6 | 1106 | mt_frame_base_address (struct frame_info *this_frame, |
61def6bd KB |
1107 | void **this_prologue_cache) |
1108 | { | |
d031aafb | 1109 | struct mt_unwind_cache *info = |
94afd7a6 | 1110 | mt_frame_unwind_cache (this_frame, this_prologue_cache); |
61def6bd KB |
1111 | |
1112 | return info->frame_base; | |
1113 | } | |
1114 | ||
1115 | /* This is a shared interface: the 'frame_unwind' object is what's | |
1116 | returned by the 'sniffer' function, and in turn specifies how to | |
1117 | get a frame's ID and prev_regs. | |
1118 | ||
1119 | This exports the 'prev_register' and 'this_id' methods. */ | |
1120 | ||
d031aafb | 1121 | static const struct frame_unwind mt_frame_unwind = { |
61def6bd | 1122 | NORMAL_FRAME, |
8fbca658 | 1123 | default_frame_unwind_stop_reason, |
d031aafb | 1124 | mt_frame_this_id, |
94afd7a6 UW |
1125 | mt_frame_prev_register, |
1126 | NULL, | |
1127 | default_frame_sniffer | |
61def6bd KB |
1128 | }; |
1129 | ||
61def6bd KB |
1130 | /* Another shared interface: the 'frame_base' object specifies how to |
1131 | unwind a frame and secure the base addresses for frame objects | |
1132 | (locals, args). */ | |
1133 | ||
d031aafb NS |
1134 | static struct frame_base mt_frame_base = { |
1135 | &mt_frame_unwind, | |
1136 | mt_frame_base_address, | |
1137 | mt_frame_base_address, | |
1138 | mt_frame_base_address | |
61def6bd KB |
1139 | }; |
1140 | ||
1141 | static struct gdbarch * | |
d031aafb | 1142 | mt_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
61def6bd KB |
1143 | { |
1144 | struct gdbarch *gdbarch; | |
df4df182 | 1145 | struct gdbarch_tdep *tdep; |
61def6bd KB |
1146 | |
1147 | /* Find a candidate among the list of pre-declared architectures. */ | |
1148 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1149 | if (arches != NULL) | |
1150 | return arches->gdbarch; | |
1151 | ||
1152 | /* None found, create a new architecture from the information | |
1153 | provided. */ | |
fc270c35 | 1154 | tdep = XCNEW (struct gdbarch_tdep); |
df4df182 | 1155 | gdbarch = gdbarch_alloc (&info, tdep); |
61def6bd | 1156 | |
cb5c8c39 DJ |
1157 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
1158 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1159 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
61def6bd | 1160 | |
d031aafb NS |
1161 | set_gdbarch_register_name (gdbarch, mt_register_name); |
1162 | set_gdbarch_num_regs (gdbarch, MT_NUM_REGS); | |
1163 | set_gdbarch_num_pseudo_regs (gdbarch, MT_NUM_PSEUDO_REGS); | |
1164 | set_gdbarch_pc_regnum (gdbarch, MT_PC_REGNUM); | |
1165 | set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM); | |
1166 | set_gdbarch_pseudo_register_read (gdbarch, mt_pseudo_register_read); | |
1167 | set_gdbarch_pseudo_register_write (gdbarch, mt_pseudo_register_write); | |
1168 | set_gdbarch_skip_prologue (gdbarch, mt_skip_prologue); | |
61def6bd | 1169 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
1170 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, mt_breakpoint_kind_from_pc); |
1171 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, mt_sw_breakpoint_from_kind); | |
61def6bd KB |
1172 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
1173 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
d031aafb NS |
1174 | set_gdbarch_register_type (gdbarch, mt_register_type); |
1175 | set_gdbarch_register_reggroup_p (gdbarch, mt_register_reggroup_p); | |
61def6bd | 1176 | |
d031aafb NS |
1177 | set_gdbarch_return_value (gdbarch, mt_return_value); |
1178 | set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM); | |
61def6bd | 1179 | |
d031aafb | 1180 | set_gdbarch_frame_align (gdbarch, mt_frame_align); |
61def6bd | 1181 | |
d031aafb | 1182 | set_gdbarch_print_registers_info (gdbarch, mt_registers_info); |
61def6bd | 1183 | |
d031aafb | 1184 | set_gdbarch_push_dummy_call (gdbarch, mt_push_dummy_call); |
61def6bd KB |
1185 | |
1186 | /* Target builtin data types. */ | |
1187 | set_gdbarch_short_bit (gdbarch, 16); | |
1188 | set_gdbarch_int_bit (gdbarch, 32); | |
1189 | set_gdbarch_long_bit (gdbarch, 32); | |
1190 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1191 | set_gdbarch_float_bit (gdbarch, 32); | |
1192 | set_gdbarch_double_bit (gdbarch, 64); | |
1193 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1194 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1195 | ||
1196 | /* Register the DWARF 2 sniffer first, and then the traditional prologue | |
1197 | based sniffer. */ | |
94afd7a6 UW |
1198 | dwarf2_append_unwinders (gdbarch); |
1199 | frame_unwind_append_unwinder (gdbarch, &mt_frame_unwind); | |
d031aafb | 1200 | frame_base_set_default (gdbarch, &mt_frame_base); |
61def6bd KB |
1201 | |
1202 | /* Register the 'unwind_pc' method. */ | |
d031aafb NS |
1203 | set_gdbarch_unwind_pc (gdbarch, mt_unwind_pc); |
1204 | set_gdbarch_unwind_sp (gdbarch, mt_unwind_sp); | |
61def6bd | 1205 | |
025bb325 | 1206 | /* Methods for saving / extracting a dummy frame's ID. |
61def6bd KB |
1207 | The ID's stack address must match the SP value returned by |
1208 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 1209 | set_gdbarch_dummy_id (gdbarch, mt_dummy_id); |
61def6bd KB |
1210 | |
1211 | return gdbarch; | |
1212 | } | |
1213 | ||
1214 | void | |
d031aafb | 1215 | _initialize_mt_tdep (void) |
61def6bd | 1216 | { |
d031aafb | 1217 | register_gdbarch_init (bfd_arch_mt, mt_gdbarch_init); |
61def6bd | 1218 | } |