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d031aafb | 1 | /* Target-dependent code for Morpho mt processor, for GDB. |
61def6bd | 2 | |
197e01b6 | 3 | Copyright (C) 2005 Free Software Foundation, Inc. |
61def6bd KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
19 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
61def6bd KB |
21 | |
22 | /* Contributed by Michael Snyder, msnyder@redhat.com. */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "frame-unwind.h" | |
27 | #include "frame-base.h" | |
28 | #include "symtab.h" | |
29 | #include "dis-asm.h" | |
30 | #include "arch-utils.h" | |
31 | #include "gdbtypes.h" | |
32 | #include "gdb_string.h" | |
33 | #include "regcache.h" | |
34 | #include "reggroups.h" | |
35 | #include "gdbcore.h" | |
36 | #include "trad-frame.h" | |
37 | #include "inferior.h" | |
38 | #include "dwarf2-frame.h" | |
39 | #include "infcall.h" | |
40 | #include "gdb_assert.h" | |
41 | ||
d031aafb | 42 | enum mt_arch_constants |
61def6bd | 43 | { |
d031aafb | 44 | MT_MAX_STRUCT_SIZE = 16 |
61def6bd KB |
45 | }; |
46 | ||
d031aafb | 47 | enum mt_gdb_regnums |
61def6bd | 48 | { |
d031aafb NS |
49 | MT_R0_REGNUM, /* 32 bit regs. */ |
50 | MT_R1_REGNUM, | |
51 | MT_1ST_ARGREG = MT_R1_REGNUM, | |
52 | MT_R2_REGNUM, | |
53 | MT_R3_REGNUM, | |
54 | MT_R4_REGNUM, | |
55 | MT_LAST_ARGREG = MT_R4_REGNUM, | |
56 | MT_R5_REGNUM, | |
57 | MT_R6_REGNUM, | |
58 | MT_R7_REGNUM, | |
59 | MT_R8_REGNUM, | |
60 | MT_R9_REGNUM, | |
61 | MT_R10_REGNUM, | |
62 | MT_R11_REGNUM, | |
63 | MT_R12_REGNUM, | |
64 | MT_FP_REGNUM = MT_R12_REGNUM, | |
65 | MT_R13_REGNUM, | |
66 | MT_SP_REGNUM = MT_R13_REGNUM, | |
67 | MT_R14_REGNUM, | |
68 | MT_RA_REGNUM = MT_R14_REGNUM, | |
69 | MT_R15_REGNUM, | |
70 | MT_IRA_REGNUM = MT_R15_REGNUM, | |
71 | MT_PC_REGNUM, | |
61def6bd KB |
72 | |
73 | /* Interrupt Enable pseudo-register, exported by SID. */ | |
d031aafb | 74 | MT_INT_ENABLE_REGNUM, |
61def6bd KB |
75 | /* End of CPU regs. */ |
76 | ||
d031aafb | 77 | MT_NUM_CPU_REGS, |
61def6bd KB |
78 | |
79 | /* Co-processor registers. */ | |
d031aafb NS |
80 | MT_COPRO_REGNUM = MT_NUM_CPU_REGS, /* 16 bit regs. */ |
81 | MT_CPR0_REGNUM, | |
82 | MT_CPR1_REGNUM, | |
83 | MT_CPR2_REGNUM, | |
84 | MT_CPR3_REGNUM, | |
85 | MT_CPR4_REGNUM, | |
86 | MT_CPR5_REGNUM, | |
87 | MT_CPR6_REGNUM, | |
88 | MT_CPR7_REGNUM, | |
89 | MT_CPR8_REGNUM, | |
90 | MT_CPR9_REGNUM, | |
91 | MT_CPR10_REGNUM, | |
92 | MT_CPR11_REGNUM, | |
93 | MT_CPR12_REGNUM, | |
94 | MT_CPR13_REGNUM, | |
95 | MT_CPR14_REGNUM, | |
96 | MT_CPR15_REGNUM, | |
97 | MT_BYPA_REGNUM, /* 32 bit regs. */ | |
98 | MT_BYPB_REGNUM, | |
99 | MT_BYPC_REGNUM, | |
100 | MT_FLAG_REGNUM, | |
101 | MT_CONTEXT_REGNUM, /* 38 bits (treat as array of | |
61def6bd | 102 | six bytes). */ |
d031aafb NS |
103 | MT_MAC_REGNUM, /* 32 bits. */ |
104 | MT_Z1_REGNUM, /* 16 bits. */ | |
105 | MT_Z2_REGNUM, /* 16 bits. */ | |
106 | MT_ICHANNEL_REGNUM, /* 32 bits. */ | |
107 | MT_ISCRAMB_REGNUM, /* 32 bits. */ | |
108 | MT_QSCRAMB_REGNUM, /* 32 bits. */ | |
109 | MT_OUT_REGNUM, /* 16 bits. */ | |
110 | MT_EXMAC_REGNUM, /* 32 bits (8 used). */ | |
111 | MT_QCHANNEL_REGNUM, /* 32 bits. */ | |
61def6bd KB |
112 | |
113 | /* Number of real registers. */ | |
d031aafb | 114 | MT_NUM_REGS, |
61def6bd KB |
115 | |
116 | /* Pseudo-registers. */ | |
d031aafb NS |
117 | MT_COPRO_PSEUDOREG_REGNUM = MT_NUM_REGS, |
118 | MT_MAC_PSEUDOREG_REGNUM, | |
60e81fcc NS |
119 | MT_COPRO_PSEUDOREG_ARRAY, |
120 | ||
121 | MT_COPRO_PSEUDOREG_DIM_1 = 2, | |
122 | MT_COPRO_PSEUDOREG_DIM_2 = 8, | |
123 | MT_COPRO_PSEUDOREG_REGS = 32, | |
61def6bd KB |
124 | |
125 | /* Two pseudo-regs ('coprocessor' and 'mac'). */ | |
60e81fcc NS |
126 | MT_NUM_PSEUDO_REGS = 2 + (MT_COPRO_PSEUDOREG_REGS |
127 | * MT_COPRO_PSEUDOREG_DIM_1 | |
128 | * MT_COPRO_PSEUDOREG_DIM_2) | |
61def6bd KB |
129 | }; |
130 | ||
131 | /* Return name of register number specified by REGNUM. */ | |
132 | ||
133 | static const char * | |
d031aafb | 134 | mt_register_name (int regnum) |
61def6bd | 135 | { |
58b78171 | 136 | static const char *const register_names[] = { |
61def6bd KB |
137 | /* CPU regs. */ |
138 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
139 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
140 | "pc", "IE", | |
141 | /* Co-processor regs. */ | |
142 | "", /* copro register. */ | |
143 | "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", | |
144 | "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15", | |
145 | "bypa", "bypb", "bypc", "flag", "context", "" /* mac. */ , "z1", "z2", | |
146 | "Ichannel", "Iscramb", "Qscramb", "out", "" /* ex-mac. */ , "Qchannel", | |
147 | /* Pseudo-registers. */ | |
148 | "coprocessor", "MAC" | |
149 | }; | |
60e81fcc NS |
150 | static const char *array_names[MT_COPRO_PSEUDOREG_REGS |
151 | * MT_COPRO_PSEUDOREG_DIM_1 | |
152 | * MT_COPRO_PSEUDOREG_DIM_2]; | |
153 | ||
154 | if (regnum < 0) | |
155 | return ""; | |
156 | if (regnum < ARRAY_SIZE (register_names)) | |
157 | return register_names[regnum]; | |
158 | if (array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY]) | |
159 | return array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY]; | |
160 | ||
161 | { | |
162 | char *name; | |
163 | const char *stub; | |
164 | unsigned dim_1; | |
165 | unsigned dim_2; | |
166 | unsigned index; | |
167 | ||
168 | regnum -= MT_COPRO_PSEUDOREG_ARRAY; | |
169 | index = regnum % MT_COPRO_PSEUDOREG_REGS; | |
170 | dim_2 = (regnum / MT_COPRO_PSEUDOREG_REGS) % MT_COPRO_PSEUDOREG_DIM_2; | |
171 | dim_1 = ((regnum / MT_COPRO_PSEUDOREG_REGS / MT_COPRO_PSEUDOREG_DIM_2) | |
172 | % MT_COPRO_PSEUDOREG_DIM_1); | |
173 | ||
174 | if (index == MT_COPRO_PSEUDOREG_REGS - 1) | |
175 | stub = register_names[MT_MAC_PSEUDOREG_REGNUM]; | |
176 | else if (index > MT_QCHANNEL_REGNUM - MT_CPR0_REGNUM) | |
177 | stub = ""; | |
178 | else | |
179 | stub = register_names[index + MT_CPR0_REGNUM]; | |
180 | if (!*stub) | |
181 | { | |
182 | array_names[regnum] = stub; | |
183 | return stub; | |
184 | } | |
185 | name = xmalloc (30); | |
186 | sprintf (name, "copro_%d_%d_%s", dim_1, dim_2, stub); | |
187 | array_names[regnum] = name; | |
188 | return name; | |
189 | } | |
190 | } | |
61def6bd | 191 | |
60e81fcc NS |
192 | /* Return the type of a coprocessor register. */ |
193 | ||
194 | static struct type * | |
195 | mt_copro_register_type (struct gdbarch *arch, int regnum) | |
196 | { | |
197 | switch (regnum) | |
198 | { | |
199 | case MT_INT_ENABLE_REGNUM: | |
200 | case MT_ICHANNEL_REGNUM: | |
201 | case MT_QCHANNEL_REGNUM: | |
202 | case MT_ISCRAMB_REGNUM: | |
203 | case MT_QSCRAMB_REGNUM: | |
204 | return builtin_type_int32; | |
205 | case MT_BYPA_REGNUM: | |
206 | case MT_BYPB_REGNUM: | |
207 | case MT_BYPC_REGNUM: | |
208 | case MT_Z1_REGNUM: | |
209 | case MT_Z2_REGNUM: | |
210 | case MT_OUT_REGNUM: | |
211 | return builtin_type_int16; | |
212 | case MT_EXMAC_REGNUM: | |
213 | case MT_MAC_REGNUM: | |
214 | return builtin_type_uint32; | |
215 | case MT_CONTEXT_REGNUM: | |
216 | return builtin_type_long_long; | |
217 | case MT_FLAG_REGNUM: | |
218 | return builtin_type_unsigned_char; | |
219 | default: | |
220 | if (regnum >= MT_CPR0_REGNUM && regnum <= MT_CPR15_REGNUM) | |
221 | return builtin_type_int16; | |
222 | else if (regnum == MT_CPR0_REGNUM + MT_COPRO_PSEUDOREG_REGS - 1) | |
223 | { | |
224 | if (gdbarch_bfd_arch_info (arch)->mach == bfd_mach_mrisc2 | |
225 | || gdbarch_bfd_arch_info (arch)->mach == bfd_mach_ms2) | |
226 | return builtin_type_uint64; | |
227 | else | |
228 | return builtin_type_uint32; | |
229 | } | |
230 | else | |
231 | return builtin_type_uint32; | |
232 | } | |
61def6bd KB |
233 | } |
234 | ||
235 | /* Given ARCH and a register number specified by REGNUM, return the | |
236 | type of that register. */ | |
237 | ||
238 | static struct type * | |
d031aafb | 239 | mt_register_type (struct gdbarch *arch, int regnum) |
61def6bd KB |
240 | { |
241 | static struct type *void_func_ptr = NULL; | |
242 | static struct type *void_ptr = NULL; | |
243 | static struct type *copro_type; | |
244 | ||
d031aafb | 245 | if (regnum >= 0 && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS) |
61def6bd KB |
246 | { |
247 | if (void_func_ptr == NULL) | |
248 | { | |
249 | struct type *temp; | |
250 | ||
251 | void_ptr = lookup_pointer_type (builtin_type_void); | |
252 | void_func_ptr = | |
253 | lookup_pointer_type (lookup_function_type (builtin_type_void)); | |
254 | temp = create_range_type (NULL, builtin_type_unsigned_int, 0, 1); | |
255 | copro_type = create_array_type (NULL, builtin_type_int16, temp); | |
256 | } | |
257 | switch (regnum) | |
258 | { | |
d031aafb NS |
259 | case MT_PC_REGNUM: |
260 | case MT_RA_REGNUM: | |
261 | case MT_IRA_REGNUM: | |
61def6bd | 262 | return void_func_ptr; |
d031aafb NS |
263 | case MT_SP_REGNUM: |
264 | case MT_FP_REGNUM: | |
61def6bd | 265 | return void_ptr; |
d031aafb NS |
266 | case MT_COPRO_REGNUM: |
267 | case MT_COPRO_PSEUDOREG_REGNUM: | |
61def6bd | 268 | return copro_type; |
d031aafb | 269 | case MT_MAC_PSEUDOREG_REGNUM: |
60e81fcc NS |
270 | return mt_copro_register_type (arch, |
271 | MT_CPR0_REGNUM | |
272 | + MT_COPRO_PSEUDOREG_REGS - 1); | |
61def6bd | 273 | default: |
d031aafb | 274 | if (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM) |
61def6bd | 275 | return builtin_type_int32; |
60e81fcc NS |
276 | else if (regnum < MT_COPRO_PSEUDOREG_ARRAY) |
277 | return mt_copro_register_type (arch, regnum); | |
278 | else | |
279 | { | |
280 | regnum -= MT_COPRO_PSEUDOREG_ARRAY; | |
281 | regnum %= MT_COPRO_PSEUDOREG_REGS; | |
282 | regnum += MT_CPR0_REGNUM; | |
283 | return mt_copro_register_type (arch, regnum); | |
284 | } | |
61def6bd KB |
285 | } |
286 | } | |
287 | internal_error (__FILE__, __LINE__, | |
d031aafb | 288 | _("mt_register_type: illegal register number %d"), regnum); |
61def6bd KB |
289 | } |
290 | ||
291 | /* Return true if register REGNUM is a member of the register group | |
292 | specified by GROUP. */ | |
293 | ||
294 | static int | |
d031aafb | 295 | mt_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
61def6bd KB |
296 | struct reggroup *group) |
297 | { | |
298 | /* Groups of registers that can be displayed via "info reg". */ | |
299 | if (group == all_reggroup) | |
300 | return (regnum >= 0 | |
d031aafb NS |
301 | && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS |
302 | && mt_register_name (regnum)[0] != '\0'); | |
61def6bd KB |
303 | |
304 | if (group == general_reggroup) | |
d031aafb | 305 | return (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM); |
61def6bd KB |
306 | |
307 | if (group == float_reggroup) | |
308 | return 0; /* No float regs. */ | |
309 | ||
310 | if (group == vector_reggroup) | |
311 | return 0; /* No vector regs. */ | |
312 | ||
313 | /* For any that are not handled above. */ | |
314 | return default_register_reggroup_p (gdbarch, regnum, group); | |
315 | } | |
316 | ||
317 | /* Return the return value convention used for a given type TYPE. | |
318 | Optionally, fetch or set the return value via READBUF or | |
319 | WRITEBUF respectively using REGCACHE for the register | |
320 | values. */ | |
321 | ||
322 | static enum return_value_convention | |
d031aafb | 323 | mt_return_value (struct gdbarch *gdbarch, struct type *type, |
61def6bd KB |
324 | struct regcache *regcache, gdb_byte *readbuf, |
325 | const gdb_byte *writebuf) | |
326 | { | |
327 | if (TYPE_LENGTH (type) > 4) | |
328 | { | |
329 | /* Return values > 4 bytes are returned in memory, | |
330 | pointed to by R11. */ | |
331 | if (readbuf) | |
332 | { | |
333 | ULONGEST addr; | |
334 | ||
d031aafb | 335 | regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr); |
61def6bd KB |
336 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
337 | } | |
338 | ||
339 | if (writebuf) | |
340 | { | |
341 | ULONGEST addr; | |
342 | ||
d031aafb | 343 | regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr); |
61def6bd KB |
344 | write_memory (addr, writebuf, TYPE_LENGTH (type)); |
345 | } | |
346 | ||
347 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
348 | } | |
349 | else | |
350 | { | |
351 | if (readbuf) | |
352 | { | |
353 | ULONGEST temp; | |
354 | ||
355 | /* Return values of <= 4 bytes are returned in R11. */ | |
d031aafb | 356 | regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &temp); |
61def6bd KB |
357 | store_unsigned_integer (readbuf, TYPE_LENGTH (type), temp); |
358 | } | |
359 | ||
360 | if (writebuf) | |
361 | { | |
362 | if (TYPE_LENGTH (type) < 4) | |
363 | { | |
364 | gdb_byte buf[4]; | |
365 | /* Add leading zeros to the value. */ | |
366 | memset (buf, 0, sizeof (buf)); | |
367 | memcpy (buf + sizeof (buf) - TYPE_LENGTH (type), | |
368 | writebuf, TYPE_LENGTH (type)); | |
d031aafb | 369 | regcache_cooked_write (regcache, MT_R11_REGNUM, buf); |
61def6bd KB |
370 | } |
371 | else /* (TYPE_LENGTH (type) == 4 */ | |
d031aafb | 372 | regcache_cooked_write (regcache, MT_R11_REGNUM, writebuf); |
61def6bd KB |
373 | } |
374 | ||
375 | return RETURN_VALUE_REGISTER_CONVENTION; | |
376 | } | |
377 | } | |
378 | ||
379 | /* If the input address, PC, is in a function prologue, return the | |
380 | address of the end of the prologue, otherwise return the input | |
381 | address. | |
382 | ||
383 | Note: PC is likely to be the function start, since this function | |
384 | is mainly used for advancing a breakpoint to the first line, or | |
385 | stepping to the first line when we have stepped into a function | |
386 | call. */ | |
387 | ||
388 | static CORE_ADDR | |
d031aafb | 389 | mt_skip_prologue (CORE_ADDR pc) |
61def6bd KB |
390 | { |
391 | CORE_ADDR func_addr = 0, func_end = 0; | |
392 | char *func_name; | |
393 | unsigned long instr; | |
394 | ||
395 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) | |
396 | { | |
397 | struct symtab_and_line sal; | |
398 | struct symbol *sym; | |
399 | ||
400 | /* Found a function. */ | |
401 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); | |
402 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
403 | { | |
404 | /* Don't use this trick for assembly source files. */ | |
405 | sal = find_pc_line (func_addr, 0); | |
406 | ||
407 | if (sal.end && sal.end < func_end) | |
408 | { | |
409 | /* Found a line number, use it as end of prologue. */ | |
410 | return sal.end; | |
411 | } | |
412 | } | |
413 | } | |
414 | ||
415 | /* No function symbol, or no line symbol. Use prologue scanning method. */ | |
416 | for (;; pc += 4) | |
417 | { | |
418 | instr = read_memory_unsigned_integer (pc, 4); | |
419 | if (instr == 0x12000000) /* nop */ | |
420 | continue; | |
421 | if (instr == 0x12ddc000) /* copy sp into fp */ | |
422 | continue; | |
423 | instr >>= 16; | |
424 | if (instr == 0x05dd) /* subi sp, sp, imm */ | |
425 | continue; | |
426 | if (instr >= 0x43c0 && instr <= 0x43df) /* push */ | |
427 | continue; | |
428 | /* Not an obvious prologue instruction. */ | |
429 | break; | |
430 | } | |
431 | ||
432 | return pc; | |
433 | } | |
434 | ||
435 | /* The breakpoint instruction must be the same size as the smallest | |
436 | instruction in the instruction set. | |
437 | ||
3950dc3f NS |
438 | The BP for ms1 is defined as 0x68000000 (BREAK). |
439 | The BP for ms2 is defined as 0x69000000 (illegal) */ | |
61def6bd KB |
440 | |
441 | static const gdb_byte * | |
d031aafb | 442 | mt_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
61def6bd | 443 | { |
3950dc3f NS |
444 | static gdb_byte ms1_breakpoint[] = { 0x68, 0, 0, 0 }; |
445 | static gdb_byte ms2_breakpoint[] = { 0x69, 0, 0, 0 }; | |
61def6bd KB |
446 | |
447 | *bp_size = 4; | |
3950dc3f NS |
448 | if (gdbarch_bfd_arch_info (current_gdbarch)->mach == bfd_mach_ms2) |
449 | return ms2_breakpoint; | |
450 | ||
451 | return ms1_breakpoint; | |
61def6bd KB |
452 | } |
453 | ||
60e81fcc NS |
454 | /* Select the correct coprocessor register bank. Return the pseudo |
455 | regnum we really want to read. */ | |
456 | ||
457 | static int | |
458 | mt_select_coprocessor (struct gdbarch *gdbarch, | |
459 | struct regcache *regcache, int regno) | |
460 | { | |
461 | unsigned index, base; | |
462 | gdb_byte copro[4]; | |
463 | ||
464 | /* Get the copro pseudo regnum. */ | |
465 | regcache_raw_read (regcache, MT_COPRO_REGNUM, copro); | |
466 | base = (extract_signed_integer (&copro[0], 2) * MT_COPRO_PSEUDOREG_DIM_2 | |
467 | + extract_signed_integer (&copro[2], 2)); | |
468 | ||
469 | regno -= MT_COPRO_PSEUDOREG_ARRAY; | |
470 | index = regno % MT_COPRO_PSEUDOREG_REGS; | |
471 | regno /= MT_COPRO_PSEUDOREG_REGS; | |
472 | if (base != regno) | |
473 | { | |
474 | /* Select the correct coprocessor register bank. Invalidate the | |
475 | coprocessor register cache. */ | |
476 | unsigned ix; | |
477 | ||
478 | store_signed_integer (&copro[0], 2, regno / MT_COPRO_PSEUDOREG_DIM_2); | |
479 | store_signed_integer (&copro[2], 2, regno % MT_COPRO_PSEUDOREG_DIM_2); | |
480 | regcache_raw_write (regcache, MT_COPRO_REGNUM, copro); | |
481 | ||
482 | /* We must flush the cache, as it is now invalid. */ | |
483 | for (ix = MT_NUM_CPU_REGS; ix != MT_NUM_REGS; ix++) | |
484 | set_register_cached (ix, 0); | |
485 | } | |
486 | ||
487 | return index; | |
488 | } | |
489 | ||
61def6bd KB |
490 | /* Fetch the pseudo registers: |
491 | ||
60e81fcc | 492 | There are two regular pseudo-registers: |
61def6bd KB |
493 | 1) The 'coprocessor' pseudo-register (which mirrors the |
494 | "real" coprocessor register sent by the target), and | |
495 | 2) The 'MAC' pseudo-register (which represents the union | |
496 | of the original 32 bit target MAC register and the new | |
60e81fcc NS |
497 | 8-bit extended-MAC register). |
498 | ||
499 | Additionally there is an array of coprocessor registers which track | |
500 | the coprocessor registers for each coprocessor. */ | |
61def6bd KB |
501 | |
502 | static void | |
d031aafb | 503 | mt_pseudo_register_read (struct gdbarch *gdbarch, |
61def6bd KB |
504 | struct regcache *regcache, int regno, gdb_byte *buf) |
505 | { | |
506 | switch (regno) | |
507 | { | |
d031aafb NS |
508 | case MT_COPRO_REGNUM: |
509 | case MT_COPRO_PSEUDOREG_REGNUM: | |
510 | regcache_raw_read (regcache, MT_COPRO_REGNUM, buf); | |
61def6bd | 511 | break; |
d031aafb NS |
512 | case MT_MAC_REGNUM: |
513 | case MT_MAC_PSEUDOREG_REGNUM: | |
3950dc3f NS |
514 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2 |
515 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) | |
61def6bd KB |
516 | { |
517 | ULONGEST oldmac = 0, ext_mac = 0; | |
518 | ULONGEST newmac; | |
519 | ||
d031aafb NS |
520 | regcache_cooked_read_unsigned (regcache, MT_MAC_REGNUM, &oldmac); |
521 | regcache_cooked_read_unsigned (regcache, MT_EXMAC_REGNUM, &ext_mac); | |
61def6bd KB |
522 | newmac = |
523 | (oldmac & 0xffffffff) | ((long long) (ext_mac & 0xff) << 32); | |
524 | store_signed_integer (buf, 8, newmac); | |
525 | } | |
526 | else | |
d031aafb | 527 | regcache_raw_read (regcache, MT_MAC_REGNUM, buf); |
61def6bd KB |
528 | break; |
529 | default: | |
60e81fcc NS |
530 | { |
531 | unsigned index = mt_select_coprocessor (gdbarch, regcache, regno); | |
532 | ||
533 | if (index == MT_COPRO_PSEUDOREG_REGS - 1) | |
534 | mt_pseudo_register_read (gdbarch, regcache, | |
535 | MT_COPRO_PSEUDOREG_REGNUM, buf); | |
536 | else if (index < MT_NUM_REGS - MT_CPR0_REGNUM) | |
537 | regcache_raw_read (regcache, index + MT_CPR0_REGNUM, buf); | |
538 | } | |
61def6bd KB |
539 | break; |
540 | } | |
541 | } | |
542 | ||
543 | /* Write the pseudo registers: | |
544 | ||
d031aafb | 545 | Mt pseudo-registers are stored directly to the target. The |
61def6bd KB |
546 | 'coprocessor' register is special, because when it is modified, all |
547 | the other coprocessor regs must be flushed from the reg cache. */ | |
548 | ||
549 | static void | |
d031aafb | 550 | mt_pseudo_register_write (struct gdbarch *gdbarch, |
61def6bd KB |
551 | struct regcache *regcache, |
552 | int regno, const gdb_byte *buf) | |
553 | { | |
554 | int i; | |
555 | ||
556 | switch (regno) | |
557 | { | |
d031aafb NS |
558 | case MT_COPRO_REGNUM: |
559 | case MT_COPRO_PSEUDOREG_REGNUM: | |
560 | regcache_raw_write (regcache, MT_COPRO_REGNUM, buf); | |
561 | for (i = MT_NUM_CPU_REGS; i < MT_NUM_REGS; i++) | |
61def6bd KB |
562 | set_register_cached (i, 0); |
563 | break; | |
d031aafb NS |
564 | case MT_MAC_REGNUM: |
565 | case MT_MAC_PSEUDOREG_REGNUM: | |
3950dc3f NS |
566 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2 |
567 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) | |
61def6bd KB |
568 | { |
569 | /* The 8-byte MAC pseudo-register must be broken down into two | |
570 | 32-byte registers. */ | |
571 | unsigned int oldmac, ext_mac; | |
572 | ULONGEST newmac; | |
573 | ||
574 | newmac = extract_unsigned_integer (buf, 8); | |
575 | oldmac = newmac & 0xffffffff; | |
576 | ext_mac = (newmac >> 32) & 0xff; | |
d031aafb NS |
577 | regcache_cooked_write_unsigned (regcache, MT_MAC_REGNUM, oldmac); |
578 | regcache_cooked_write_unsigned (regcache, MT_EXMAC_REGNUM, ext_mac); | |
61def6bd KB |
579 | } |
580 | else | |
d031aafb | 581 | regcache_raw_write (regcache, MT_MAC_REGNUM, buf); |
61def6bd KB |
582 | break; |
583 | default: | |
60e81fcc NS |
584 | { |
585 | unsigned index = mt_select_coprocessor (gdbarch, regcache, regno); | |
586 | ||
587 | if (index == MT_COPRO_PSEUDOREG_REGS - 1) | |
588 | mt_pseudo_register_write (gdbarch, regcache, | |
589 | MT_COPRO_PSEUDOREG_REGNUM, buf); | |
590 | else if (index < MT_NUM_REGS - MT_CPR0_REGNUM) | |
591 | regcache_raw_write (regcache, index + MT_CPR0_REGNUM, buf); | |
592 | } | |
61def6bd KB |
593 | break; |
594 | } | |
595 | } | |
596 | ||
597 | static CORE_ADDR | |
d031aafb | 598 | mt_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
61def6bd KB |
599 | { |
600 | /* Register size is 4 bytes. */ | |
601 | return align_down (sp, 4); | |
602 | } | |
603 | ||
604 | /* Implements the "info registers" command. When ``all'' is non-zero, | |
605 | the coprocessor registers will be printed in addition to the rest | |
606 | of the registers. */ | |
607 | ||
608 | static void | |
d031aafb | 609 | mt_registers_info (struct gdbarch *gdbarch, |
61def6bd KB |
610 | struct ui_file *file, |
611 | struct frame_info *frame, int regnum, int all) | |
612 | { | |
613 | if (regnum == -1) | |
614 | { | |
615 | int lim; | |
616 | ||
d031aafb | 617 | lim = all ? MT_NUM_REGS : MT_NUM_CPU_REGS; |
61def6bd KB |
618 | |
619 | for (regnum = 0; regnum < lim; regnum++) | |
620 | { | |
621 | /* Don't display the Qchannel register since it will be displayed | |
622 | along with Ichannel. (See below.) */ | |
d031aafb | 623 | if (regnum == MT_QCHANNEL_REGNUM) |
61def6bd KB |
624 | continue; |
625 | ||
d031aafb | 626 | mt_registers_info (gdbarch, file, frame, regnum, all); |
61def6bd KB |
627 | |
628 | /* Display the Qchannel register immediately after Ichannel. */ | |
d031aafb NS |
629 | if (regnum == MT_ICHANNEL_REGNUM) |
630 | mt_registers_info (gdbarch, file, frame, MT_QCHANNEL_REGNUM, all); | |
61def6bd KB |
631 | } |
632 | } | |
633 | else | |
634 | { | |
d031aafb | 635 | if (regnum == MT_EXMAC_REGNUM) |
61def6bd | 636 | return; |
d031aafb | 637 | else if (regnum == MT_CONTEXT_REGNUM) |
61def6bd KB |
638 | { |
639 | /* Special output handling for 38-bit context register. */ | |
640 | unsigned char *buff; | |
641 | unsigned int *bytes, i, regsize; | |
642 | ||
643 | regsize = register_size (gdbarch, regnum); | |
644 | ||
645 | buff = alloca (regsize); | |
646 | bytes = alloca (regsize * sizeof (*bytes)); | |
647 | ||
648 | frame_register_read (frame, regnum, buff); | |
649 | ||
650 | fputs_filtered (REGISTER_NAME (regnum), file); | |
651 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
652 | fputs_filtered ("0x", file); | |
653 | ||
654 | for (i = 0; i < regsize; i++) | |
655 | fprintf_filtered (file, "%02x", (unsigned int) | |
656 | extract_unsigned_integer (buff + i, 1)); | |
657 | fputs_filtered ("\t", file); | |
658 | print_longest (file, 'd', 0, | |
659 | extract_unsigned_integer (buff, regsize)); | |
660 | fputs_filtered ("\n", file); | |
661 | } | |
d031aafb NS |
662 | else if (regnum == MT_COPRO_REGNUM |
663 | || regnum == MT_COPRO_PSEUDOREG_REGNUM) | |
61def6bd KB |
664 | { |
665 | /* Special output handling for the 'coprocessor' register. */ | |
58b78171 | 666 | gdb_byte *buf; |
61def6bd | 667 | |
d031aafb NS |
668 | buf = alloca (register_size (gdbarch, MT_COPRO_REGNUM)); |
669 | frame_register_read (frame, MT_COPRO_REGNUM, buf); | |
61def6bd | 670 | /* And print. */ |
d031aafb | 671 | regnum = MT_COPRO_PSEUDOREG_REGNUM; |
61def6bd KB |
672 | fputs_filtered (REGISTER_NAME (regnum), file); |
673 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
674 | val_print (register_type (gdbarch, regnum), buf, | |
675 | 0, 0, file, 0, 1, 0, Val_no_prettyprint); | |
676 | fputs_filtered ("\n", file); | |
677 | } | |
d031aafb | 678 | else if (regnum == MT_MAC_REGNUM || regnum == MT_MAC_PSEUDOREG_REGNUM) |
61def6bd KB |
679 | { |
680 | ULONGEST oldmac, ext_mac, newmac; | |
58b78171 | 681 | gdb_byte buf[3 * sizeof (LONGEST)]; |
61def6bd KB |
682 | |
683 | /* Get the two "real" mac registers. */ | |
d031aafb | 684 | frame_register_read (frame, MT_MAC_REGNUM, buf); |
3950dc3f | 685 | oldmac = extract_unsigned_integer |
d031aafb | 686 | (buf, register_size (gdbarch, MT_MAC_REGNUM)); |
58b78171 NS |
687 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2 |
688 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2) | |
61def6bd | 689 | { |
d031aafb | 690 | frame_register_read (frame, MT_EXMAC_REGNUM, buf); |
3950dc3f | 691 | ext_mac = extract_unsigned_integer |
d031aafb | 692 | (buf, register_size (gdbarch, MT_EXMAC_REGNUM)); |
61def6bd KB |
693 | } |
694 | else | |
695 | ext_mac = 0; | |
696 | ||
697 | /* Add them together. */ | |
698 | newmac = (oldmac & 0xffffffff) + ((ext_mac & 0xff) << 32); | |
699 | ||
700 | /* And print. */ | |
d031aafb | 701 | regnum = MT_MAC_PSEUDOREG_REGNUM; |
61def6bd KB |
702 | fputs_filtered (REGISTER_NAME (regnum), file); |
703 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
704 | fputs_filtered ("0x", file); | |
705 | print_longest (file, 'x', 0, newmac); | |
706 | fputs_filtered ("\t", file); | |
707 | print_longest (file, 'u', 0, newmac); | |
708 | fputs_filtered ("\n", file); | |
709 | } | |
710 | else | |
711 | default_print_registers_info (gdbarch, file, frame, regnum, all); | |
712 | } | |
713 | } | |
714 | ||
715 | /* Set up the callee's arguments for an inferior function call. The | |
716 | arguments are pushed on the stack or are placed in registers as | |
717 | appropriate. It also sets up the return address (which points to | |
718 | the call dummy breakpoint). | |
719 | ||
720 | Returns the updated (and aligned) stack pointer. */ | |
721 | ||
722 | static CORE_ADDR | |
d031aafb | 723 | mt_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
61def6bd KB |
724 | struct regcache *regcache, CORE_ADDR bp_addr, |
725 | int nargs, struct value **args, CORE_ADDR sp, | |
726 | int struct_return, CORE_ADDR struct_addr) | |
727 | { | |
728 | #define wordsize 4 | |
d031aafb NS |
729 | gdb_byte buf[MT_MAX_STRUCT_SIZE]; |
730 | int argreg = MT_1ST_ARGREG; | |
61def6bd KB |
731 | int split_param_len = 0; |
732 | int stack_dest = sp; | |
733 | int slacklen; | |
734 | int typelen; | |
735 | int i, j; | |
736 | ||
d031aafb NS |
737 | /* First handle however many args we can fit into MT_1ST_ARGREG thru |
738 | MT_LAST_ARGREG. */ | |
739 | for (i = 0; i < nargs && argreg <= MT_LAST_ARGREG; i++) | |
61def6bd | 740 | { |
58b78171 | 741 | const gdb_byte *val; |
61def6bd KB |
742 | typelen = TYPE_LENGTH (value_type (args[i])); |
743 | switch (typelen) | |
744 | { | |
745 | case 1: | |
746 | case 2: | |
747 | case 3: | |
748 | case 4: | |
749 | regcache_cooked_write_unsigned (regcache, argreg++, | |
750 | extract_unsigned_integer | |
751 | (value_contents (args[i]), | |
752 | wordsize)); | |
753 | break; | |
754 | case 8: | |
755 | case 12: | |
756 | case 16: | |
757 | val = value_contents (args[i]); | |
758 | while (typelen > 0) | |
759 | { | |
d031aafb | 760 | if (argreg <= MT_LAST_ARGREG) |
61def6bd KB |
761 | { |
762 | /* This word of the argument is passed in a register. */ | |
763 | regcache_cooked_write_unsigned (regcache, argreg++, | |
764 | extract_unsigned_integer | |
765 | (val, wordsize)); | |
766 | typelen -= wordsize; | |
767 | val += wordsize; | |
768 | } | |
769 | else | |
770 | { | |
771 | /* Remainder of this arg must be passed on the stack | |
772 | (deferred to do later). */ | |
773 | split_param_len = typelen; | |
774 | memcpy (buf, val, typelen); | |
775 | break; /* No more args can be handled in regs. */ | |
776 | } | |
777 | } | |
778 | break; | |
779 | default: | |
780 | /* By reverse engineering of gcc output, args bigger than | |
781 | 16 bytes go on the stack, and their address is passed | |
782 | in the argreg. */ | |
783 | stack_dest -= typelen; | |
784 | write_memory (stack_dest, value_contents (args[i]), typelen); | |
785 | regcache_cooked_write_unsigned (regcache, argreg++, stack_dest); | |
786 | break; | |
787 | } | |
788 | } | |
789 | ||
790 | /* Next, the rest of the arguments go onto the stack, in reverse order. */ | |
791 | for (j = nargs - 1; j >= i; j--) | |
792 | { | |
58b78171 NS |
793 | gdb_byte *val; |
794 | ||
61def6bd KB |
795 | /* Right-justify the value in an aligned-length buffer. */ |
796 | typelen = TYPE_LENGTH (value_type (args[j])); | |
797 | slacklen = (wordsize - (typelen % wordsize)) % wordsize; | |
798 | val = alloca (typelen + slacklen); | |
799 | memcpy (val, value_contents (args[j]), typelen); | |
800 | memset (val + typelen, 0, slacklen); | |
801 | /* Now write this data to the stack. */ | |
802 | stack_dest -= typelen + slacklen; | |
803 | write_memory (stack_dest, val, typelen + slacklen); | |
804 | } | |
805 | ||
806 | /* Finally, if a param needs to be split between registers and stack, | |
807 | write the second half to the stack now. */ | |
808 | if (split_param_len != 0) | |
809 | { | |
810 | stack_dest -= split_param_len; | |
811 | write_memory (stack_dest, buf, split_param_len); | |
812 | } | |
813 | ||
814 | /* Set up return address (provided to us as bp_addr). */ | |
d031aafb | 815 | regcache_cooked_write_unsigned (regcache, MT_RA_REGNUM, bp_addr); |
61def6bd KB |
816 | |
817 | /* Store struct return address, if given. */ | |
818 | if (struct_return && struct_addr != 0) | |
d031aafb | 819 | regcache_cooked_write_unsigned (regcache, MT_R11_REGNUM, struct_addr); |
61def6bd KB |
820 | |
821 | /* Set aside 16 bytes for the callee to save regs 1-4. */ | |
822 | stack_dest -= 16; | |
823 | ||
824 | /* Update the stack pointer. */ | |
d031aafb | 825 | regcache_cooked_write_unsigned (regcache, MT_SP_REGNUM, stack_dest); |
61def6bd KB |
826 | |
827 | /* And that should do it. Return the new stack pointer. */ | |
828 | return stack_dest; | |
829 | } | |
830 | ||
831 | ||
832 | /* The 'unwind_cache' data structure. */ | |
833 | ||
d031aafb | 834 | struct mt_unwind_cache |
61def6bd KB |
835 | { |
836 | /* The previous frame's inner most stack address. | |
837 | Used as this frame ID's stack_addr. */ | |
838 | CORE_ADDR prev_sp; | |
839 | CORE_ADDR frame_base; | |
840 | int framesize; | |
841 | int frameless_p; | |
842 | ||
843 | /* Table indicating the location of each and every register. */ | |
844 | struct trad_frame_saved_reg *saved_regs; | |
845 | }; | |
846 | ||
847 | /* Initialize an unwind_cache. Build up the saved_regs table etc. for | |
848 | the frame. */ | |
849 | ||
d031aafb NS |
850 | static struct mt_unwind_cache * |
851 | mt_frame_unwind_cache (struct frame_info *next_frame, | |
61def6bd KB |
852 | void **this_prologue_cache) |
853 | { | |
854 | struct gdbarch *gdbarch; | |
d031aafb | 855 | struct mt_unwind_cache *info; |
61def6bd KB |
856 | CORE_ADDR next_addr, start_addr, end_addr, prologue_end_addr; |
857 | unsigned long instr, upper_half, delayed_store = 0; | |
858 | int regnum, offset; | |
859 | ULONGEST sp, fp; | |
860 | ||
861 | if ((*this_prologue_cache)) | |
862 | return (*this_prologue_cache); | |
863 | ||
864 | gdbarch = get_frame_arch (next_frame); | |
d031aafb | 865 | info = FRAME_OBSTACK_ZALLOC (struct mt_unwind_cache); |
61def6bd KB |
866 | (*this_prologue_cache) = info; |
867 | ||
868 | info->prev_sp = 0; | |
869 | info->framesize = 0; | |
870 | info->frame_base = 0; | |
871 | info->frameless_p = 1; | |
872 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
873 | ||
874 | /* Grab the frame-relative values of SP and FP, needed below. | |
875 | The frame_saved_register function will find them on the | |
876 | stack or in the registers as appropriate. */ | |
d031aafb NS |
877 | frame_unwind_unsigned_register (next_frame, MT_SP_REGNUM, &sp); |
878 | frame_unwind_unsigned_register (next_frame, MT_FP_REGNUM, &fp); | |
61def6bd KB |
879 | |
880 | start_addr = frame_func_unwind (next_frame); | |
881 | ||
882 | /* Return early if GDB couldn't find the function. */ | |
883 | if (start_addr == 0) | |
884 | return info; | |
885 | ||
886 | end_addr = frame_pc_unwind (next_frame); | |
887 | prologue_end_addr = skip_prologue_using_sal (start_addr); | |
888 | if (end_addr == 0) | |
889 | for (next_addr = start_addr; next_addr < end_addr; next_addr += 4) | |
890 | { | |
891 | instr = get_frame_memory_unsigned (next_frame, next_addr, 4); | |
892 | if (delayed_store) /* previous instr was a push */ | |
893 | { | |
894 | upper_half = delayed_store >> 16; | |
895 | regnum = upper_half & 0xf; | |
896 | offset = delayed_store & 0xffff; | |
897 | switch (upper_half & 0xfff0) | |
898 | { | |
899 | case 0x43c0: /* push using frame pointer */ | |
900 | info->saved_regs[regnum].addr = offset; | |
901 | break; | |
902 | case 0x43d0: /* push using stack pointer */ | |
903 | info->saved_regs[regnum].addr = offset; | |
904 | break; | |
905 | default: /* lint */ | |
906 | break; | |
907 | } | |
908 | delayed_store = 0; | |
909 | } | |
910 | ||
911 | switch (instr) | |
912 | { | |
913 | case 0x12000000: /* NO-OP */ | |
914 | continue; | |
915 | case 0x12ddc000: /* copy sp into fp */ | |
916 | info->frameless_p = 0; /* Record that the frame pointer is in use. */ | |
917 | continue; | |
918 | default: | |
919 | upper_half = instr >> 16; | |
920 | if (upper_half == 0x05dd || /* subi sp, sp, imm */ | |
921 | upper_half == 0x07dd) /* subui sp, sp, imm */ | |
922 | { | |
923 | /* Record the frame size. */ | |
924 | info->framesize = instr & 0xffff; | |
925 | continue; | |
926 | } | |
927 | if ((upper_half & 0xfff0) == 0x43c0 || /* frame push */ | |
928 | (upper_half & 0xfff0) == 0x43d0) /* stack push */ | |
929 | { | |
930 | /* Save this instruction, but don't record the | |
931 | pushed register as 'saved' until we see the | |
932 | next instruction. That's because of deferred stores | |
933 | on this target -- GDB won't be able to read the register | |
934 | from the stack until one instruction later. */ | |
935 | delayed_store = instr; | |
936 | continue; | |
937 | } | |
938 | /* Not a prologue instruction. Is this the end of the prologue? | |
939 | This is the most difficult decision; when to stop scanning. | |
940 | ||
941 | If we have no line symbol, then the best thing we can do | |
942 | is to stop scanning when we encounter an instruction that | |
943 | is not likely to be a part of the prologue. | |
944 | ||
945 | But if we do have a line symbol, then we should | |
946 | keep scanning until we reach it (or we reach end_addr). */ | |
947 | ||
948 | if (prologue_end_addr && (prologue_end_addr > (next_addr + 4))) | |
949 | continue; /* Keep scanning, recording saved_regs etc. */ | |
950 | else | |
951 | break; /* Quit scanning: breakpoint can be set here. */ | |
952 | } | |
953 | } | |
954 | ||
955 | /* Special handling for the "saved" address of the SP: | |
956 | The SP is of course never saved on the stack at all, so | |
957 | by convention what we put here is simply the previous | |
958 | _value_ of the SP (as opposed to an address where the | |
959 | previous value would have been pushed). This will also | |
960 | give us the frame base address. */ | |
961 | ||
962 | if (info->frameless_p) | |
963 | { | |
964 | info->frame_base = sp + info->framesize; | |
965 | info->prev_sp = sp + info->framesize; | |
966 | } | |
967 | else | |
968 | { | |
969 | info->frame_base = fp + info->framesize; | |
970 | info->prev_sp = fp + info->framesize; | |
971 | } | |
972 | /* Save prev_sp in saved_regs as a value, not as an address. */ | |
d031aafb | 973 | trad_frame_set_value (info->saved_regs, MT_SP_REGNUM, info->prev_sp); |
61def6bd KB |
974 | |
975 | /* Now convert frame offsets to actual addresses (not offsets). */ | |
d031aafb | 976 | for (regnum = 0; regnum < MT_NUM_REGS; regnum++) |
61def6bd KB |
977 | if (trad_frame_addr_p (info->saved_regs, regnum)) |
978 | info->saved_regs[regnum].addr += info->frame_base - info->framesize; | |
979 | ||
980 | /* The call instruction moves the caller's PC in the callee's RA reg. | |
981 | Since this is an unwind, do the reverse. Copy the location of RA | |
982 | into PC (the address / regnum) so that a request for PC will be | |
983 | converted into a request for the RA. */ | |
d031aafb | 984 | info->saved_regs[MT_PC_REGNUM] = info->saved_regs[MT_RA_REGNUM]; |
61def6bd KB |
985 | |
986 | return info; | |
987 | } | |
988 | ||
989 | static CORE_ADDR | |
d031aafb | 990 | mt_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
61def6bd KB |
991 | { |
992 | ULONGEST pc; | |
993 | ||
d031aafb | 994 | frame_unwind_unsigned_register (next_frame, MT_PC_REGNUM, &pc); |
61def6bd KB |
995 | return pc; |
996 | } | |
997 | ||
998 | static CORE_ADDR | |
d031aafb | 999 | mt_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
61def6bd KB |
1000 | { |
1001 | ULONGEST sp; | |
1002 | ||
d031aafb | 1003 | frame_unwind_unsigned_register (next_frame, MT_SP_REGNUM, &sp); |
61def6bd KB |
1004 | return sp; |
1005 | } | |
1006 | ||
1007 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
1008 | dummy frame. The frame ID's base needs to match the TOS value | |
1009 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1010 | breakpoint. */ | |
1011 | ||
1012 | static struct frame_id | |
d031aafb | 1013 | mt_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
61def6bd | 1014 | { |
d031aafb | 1015 | return frame_id_build (mt_unwind_sp (gdbarch, next_frame), |
61def6bd KB |
1016 | frame_pc_unwind (next_frame)); |
1017 | } | |
1018 | ||
1019 | /* Given a GDB frame, determine the address of the calling function's | |
1020 | frame. This will be used to create a new GDB frame struct. */ | |
1021 | ||
1022 | static void | |
d031aafb | 1023 | mt_frame_this_id (struct frame_info *next_frame, |
61def6bd KB |
1024 | void **this_prologue_cache, struct frame_id *this_id) |
1025 | { | |
d031aafb NS |
1026 | struct mt_unwind_cache *info = |
1027 | mt_frame_unwind_cache (next_frame, this_prologue_cache); | |
61def6bd KB |
1028 | |
1029 | if (!(info == NULL || info->prev_sp == 0)) | |
1030 | { | |
1031 | (*this_id) = frame_id_build (info->prev_sp, | |
1032 | frame_func_unwind (next_frame)); | |
1033 | } | |
1034 | return; | |
1035 | } | |
1036 | ||
1037 | static void | |
d031aafb | 1038 | mt_frame_prev_register (struct frame_info *next_frame, |
61def6bd KB |
1039 | void **this_prologue_cache, |
1040 | int regnum, int *optimizedp, | |
1041 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1042 | int *realnump, gdb_byte *bufferp) | |
1043 | { | |
d031aafb NS |
1044 | struct mt_unwind_cache *info = |
1045 | mt_frame_unwind_cache (next_frame, this_prologue_cache); | |
61def6bd KB |
1046 | |
1047 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1048 | optimizedp, lvalp, addrp, realnump, bufferp); | |
1049 | } | |
1050 | ||
1051 | static CORE_ADDR | |
d031aafb | 1052 | mt_frame_base_address (struct frame_info *next_frame, |
61def6bd KB |
1053 | void **this_prologue_cache) |
1054 | { | |
d031aafb NS |
1055 | struct mt_unwind_cache *info = |
1056 | mt_frame_unwind_cache (next_frame, this_prologue_cache); | |
61def6bd KB |
1057 | |
1058 | return info->frame_base; | |
1059 | } | |
1060 | ||
1061 | /* This is a shared interface: the 'frame_unwind' object is what's | |
1062 | returned by the 'sniffer' function, and in turn specifies how to | |
1063 | get a frame's ID and prev_regs. | |
1064 | ||
1065 | This exports the 'prev_register' and 'this_id' methods. */ | |
1066 | ||
d031aafb | 1067 | static const struct frame_unwind mt_frame_unwind = { |
61def6bd | 1068 | NORMAL_FRAME, |
d031aafb NS |
1069 | mt_frame_this_id, |
1070 | mt_frame_prev_register | |
61def6bd KB |
1071 | }; |
1072 | ||
1073 | /* The sniffer is a registered function that identifies our family of | |
1074 | frame unwind functions (this_id and prev_register). */ | |
1075 | ||
1076 | static const struct frame_unwind * | |
d031aafb | 1077 | mt_frame_sniffer (struct frame_info *next_frame) |
61def6bd | 1078 | { |
d031aafb | 1079 | return &mt_frame_unwind; |
61def6bd KB |
1080 | } |
1081 | ||
1082 | /* Another shared interface: the 'frame_base' object specifies how to | |
1083 | unwind a frame and secure the base addresses for frame objects | |
1084 | (locals, args). */ | |
1085 | ||
d031aafb NS |
1086 | static struct frame_base mt_frame_base = { |
1087 | &mt_frame_unwind, | |
1088 | mt_frame_base_address, | |
1089 | mt_frame_base_address, | |
1090 | mt_frame_base_address | |
61def6bd KB |
1091 | }; |
1092 | ||
1093 | static struct gdbarch * | |
d031aafb | 1094 | mt_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
61def6bd KB |
1095 | { |
1096 | struct gdbarch *gdbarch; | |
61def6bd KB |
1097 | |
1098 | /* Find a candidate among the list of pre-declared architectures. */ | |
1099 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1100 | if (arches != NULL) | |
1101 | return arches->gdbarch; | |
1102 | ||
1103 | /* None found, create a new architecture from the information | |
1104 | provided. */ | |
1105 | gdbarch = gdbarch_alloc (&info, NULL); | |
1106 | ||
1107 | switch (info.byte_order) | |
1108 | { | |
1109 | case BFD_ENDIAN_BIG: | |
1110 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
1111 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
1112 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1113 | break; | |
1114 | case BFD_ENDIAN_LITTLE: | |
1115 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
1116 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
1117 | set_gdbarch_long_double_format (gdbarch, | |
1118 | &floatformat_ieee_double_little); | |
1119 | break; | |
1120 | default: | |
1121 | internal_error (__FILE__, __LINE__, | |
d031aafb | 1122 | _("mt_gdbarch_init: bad byte order for float format")); |
61def6bd KB |
1123 | } |
1124 | ||
d031aafb NS |
1125 | set_gdbarch_register_name (gdbarch, mt_register_name); |
1126 | set_gdbarch_num_regs (gdbarch, MT_NUM_REGS); | |
1127 | set_gdbarch_num_pseudo_regs (gdbarch, MT_NUM_PSEUDO_REGS); | |
1128 | set_gdbarch_pc_regnum (gdbarch, MT_PC_REGNUM); | |
1129 | set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM); | |
1130 | set_gdbarch_pseudo_register_read (gdbarch, mt_pseudo_register_read); | |
1131 | set_gdbarch_pseudo_register_write (gdbarch, mt_pseudo_register_write); | |
1132 | set_gdbarch_skip_prologue (gdbarch, mt_skip_prologue); | |
61def6bd | 1133 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
d031aafb | 1134 | set_gdbarch_breakpoint_from_pc (gdbarch, mt_breakpoint_from_pc); |
61def6bd KB |
1135 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
1136 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
d031aafb NS |
1137 | set_gdbarch_print_insn (gdbarch, print_insn_mt); |
1138 | set_gdbarch_register_type (gdbarch, mt_register_type); | |
1139 | set_gdbarch_register_reggroup_p (gdbarch, mt_register_reggroup_p); | |
61def6bd | 1140 | |
d031aafb NS |
1141 | set_gdbarch_return_value (gdbarch, mt_return_value); |
1142 | set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM); | |
61def6bd | 1143 | |
d031aafb | 1144 | set_gdbarch_frame_align (gdbarch, mt_frame_align); |
61def6bd | 1145 | |
d031aafb | 1146 | set_gdbarch_print_registers_info (gdbarch, mt_registers_info); |
61def6bd | 1147 | |
d031aafb | 1148 | set_gdbarch_push_dummy_call (gdbarch, mt_push_dummy_call); |
61def6bd KB |
1149 | |
1150 | /* Target builtin data types. */ | |
1151 | set_gdbarch_short_bit (gdbarch, 16); | |
1152 | set_gdbarch_int_bit (gdbarch, 32); | |
1153 | set_gdbarch_long_bit (gdbarch, 32); | |
1154 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1155 | set_gdbarch_float_bit (gdbarch, 32); | |
1156 | set_gdbarch_double_bit (gdbarch, 64); | |
1157 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1158 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1159 | ||
1160 | /* Register the DWARF 2 sniffer first, and then the traditional prologue | |
1161 | based sniffer. */ | |
1162 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
d031aafb NS |
1163 | frame_unwind_append_sniffer (gdbarch, mt_frame_sniffer); |
1164 | frame_base_set_default (gdbarch, &mt_frame_base); | |
61def6bd KB |
1165 | |
1166 | /* Register the 'unwind_pc' method. */ | |
d031aafb NS |
1167 | set_gdbarch_unwind_pc (gdbarch, mt_unwind_pc); |
1168 | set_gdbarch_unwind_sp (gdbarch, mt_unwind_sp); | |
61def6bd KB |
1169 | |
1170 | /* Methods for saving / extracting a dummy frame's ID. | |
1171 | The ID's stack address must match the SP value returned by | |
1172 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
d031aafb | 1173 | set_gdbarch_unwind_dummy_id (gdbarch, mt_unwind_dummy_id); |
61def6bd KB |
1174 | |
1175 | return gdbarch; | |
1176 | } | |
1177 | ||
1178 | void | |
d031aafb | 1179 | _initialize_mt_tdep (void) |
61def6bd | 1180 | { |
d031aafb | 1181 | register_gdbarch_init (bfd_arch_mt, mt_gdbarch_init); |
61def6bd | 1182 | } |