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* cli/cli-script.c (do_fclose_cleanup): Remove.
[deliverable/binutils-gdb.git] / gdb / mt-tdep.c
CommitLineData
d031aafb 1/* Target-dependent code for Morpho mt processor, for GDB.
61def6bd 2
9b254dd1 3 Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
61def6bd
KB		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
61def6bd
KB		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
61def6bd
KB		 19
20/* Contributed by Michael Snyder, msnyder@redhat.com. */
21
22#include "defs.h"
23#include "frame.h"
24#include "frame-unwind.h"
25#include "frame-base.h"
26#include "symtab.h"
27#include "dis-asm.h"
28#include "arch-utils.h"
29#include "gdbtypes.h"
30#include "gdb_string.h"
31#include "regcache.h"
32#include "reggroups.h"
33#include "gdbcore.h"
34#include "trad-frame.h"
35#include "inferior.h"
36#include "dwarf2-frame.h"
37#include "infcall.h"
38#include "gdb_assert.h"
d8ca156b 39#include "language.h"
61def6bd 40
d031aafb 41enum mt_arch_constants
61def6bd 42{
d031aafb 43 MT_MAX_STRUCT_SIZE = 16
61def6bd
KB		 44};
45
d031aafb 46enum mt_gdb_regnums
61def6bd 47{
d031aafb
NS		 48 MT_R0_REGNUM, /* 32 bit regs. */
49 MT_R1_REGNUM,
50 MT_1ST_ARGREG = MT_R1_REGNUM,
51 MT_R2_REGNUM,
52 MT_R3_REGNUM,
53 MT_R4_REGNUM,
54 MT_LAST_ARGREG = MT_R4_REGNUM,
55 MT_R5_REGNUM,
56 MT_R6_REGNUM,
57 MT_R7_REGNUM,
58 MT_R8_REGNUM,
59 MT_R9_REGNUM,
60 MT_R10_REGNUM,
61 MT_R11_REGNUM,
62 MT_R12_REGNUM,
63 MT_FP_REGNUM = MT_R12_REGNUM,
64 MT_R13_REGNUM,
65 MT_SP_REGNUM = MT_R13_REGNUM,
66 MT_R14_REGNUM,
67 MT_RA_REGNUM = MT_R14_REGNUM,
68 MT_R15_REGNUM,
69 MT_IRA_REGNUM = MT_R15_REGNUM,
70 MT_PC_REGNUM,
61def6bd
KB		 71
72 /* Interrupt Enable pseudo-register, exported by SID. */
d031aafb 73 MT_INT_ENABLE_REGNUM,
61def6bd
KB		 74 /* End of CPU regs. */
75
d031aafb 76 MT_NUM_CPU_REGS,
61def6bd
KB		 77
78 /* Co-processor registers. */
d031aafb
NS		 79 MT_COPRO_REGNUM = MT_NUM_CPU_REGS, /* 16 bit regs. */
80 MT_CPR0_REGNUM,
81 MT_CPR1_REGNUM,
82 MT_CPR2_REGNUM,
83 MT_CPR3_REGNUM,
84 MT_CPR4_REGNUM,
85 MT_CPR5_REGNUM,
86 MT_CPR6_REGNUM,
87 MT_CPR7_REGNUM,
88 MT_CPR8_REGNUM,
89 MT_CPR9_REGNUM,
90 MT_CPR10_REGNUM,
91 MT_CPR11_REGNUM,
92 MT_CPR12_REGNUM,
93 MT_CPR13_REGNUM,
94 MT_CPR14_REGNUM,
95 MT_CPR15_REGNUM,
96 MT_BYPA_REGNUM, /* 32 bit regs. */
97 MT_BYPB_REGNUM,
98 MT_BYPC_REGNUM,
99 MT_FLAG_REGNUM,
100 MT_CONTEXT_REGNUM, /* 38 bits (treat as array of
61def6bd 101 six bytes). */
d031aafb
NS		 102 MT_MAC_REGNUM, /* 32 bits. */
103 MT_Z1_REGNUM, /* 16 bits. */
104 MT_Z2_REGNUM, /* 16 bits. */
105 MT_ICHANNEL_REGNUM, /* 32 bits. */
106 MT_ISCRAMB_REGNUM, /* 32 bits. */
107 MT_QSCRAMB_REGNUM, /* 32 bits. */
108 MT_OUT_REGNUM, /* 16 bits. */
109 MT_EXMAC_REGNUM, /* 32 bits (8 used). */
110 MT_QCHANNEL_REGNUM, /* 32 bits. */
03a73f77
MM		 111 MT_ZI2_REGNUM, /* 16 bits. */
112 MT_ZQ2_REGNUM, /* 16 bits. */
113 MT_CHANNEL2_REGNUM, /* 32 bits. */
114 MT_ISCRAMB2_REGNUM, /* 32 bits. */
115 MT_QSCRAMB2_REGNUM, /* 32 bits. */
116 MT_QCHANNEL2_REGNUM, /* 32 bits. */
61def6bd
KB		 117
118 /* Number of real registers. */
d031aafb 119 MT_NUM_REGS,
61def6bd
KB		 120
121 /* Pseudo-registers. */
d031aafb
NS		 122 MT_COPRO_PSEUDOREG_REGNUM = MT_NUM_REGS,
123 MT_MAC_PSEUDOREG_REGNUM,
60e81fcc
NS		 124 MT_COPRO_PSEUDOREG_ARRAY,
125
126 MT_COPRO_PSEUDOREG_DIM_1 = 2,
127 MT_COPRO_PSEUDOREG_DIM_2 = 8,
03a73f77
MM		 128 /* The number of pseudo-registers for each coprocessor. These
129 include the real coprocessor registers, the pseudo-registe for
130 the coprocessor number, and the pseudo-register for the MAC. */
131 MT_COPRO_PSEUDOREG_REGS = MT_NUM_REGS - MT_NUM_CPU_REGS + 2,
132 /* The register number of the MAC, relative to a given coprocessor. */
133 MT_COPRO_PSEUDOREG_MAC_REGNUM = MT_COPRO_PSEUDOREG_REGS - 1,
61def6bd
KB		 134
135 /* Two pseudo-regs ('coprocessor' and 'mac'). */
60e81fcc
NS		 136 MT_NUM_PSEUDO_REGS = 2 + (MT_COPRO_PSEUDOREG_REGS
137 * MT_COPRO_PSEUDOREG_DIM_1
138 * MT_COPRO_PSEUDOREG_DIM_2)
61def6bd
KB		 139};
140
141/* Return name of register number specified by REGNUM. */
142
143static const char *
d93859e2 144mt_register_name (struct gdbarch *gdbarch, int regnum)
61def6bd 145{
58b78171 146 static const char *const register_names[] = {
61def6bd
KB		 147 /* CPU regs. */
148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 "pc", "IE",
151 /* Co-processor regs. */
152 "", /* copro register. */
153 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
154 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15",
155 "bypa", "bypb", "bypc", "flag", "context", "" /* mac. */ , "z1", "z2",
156 "Ichannel", "Iscramb", "Qscramb", "out", "" /* ex-mac. */ , "Qchannel",
03a73f77 157 "zi2", "zq2", "Ichannel2", "Iscramb2", "Qscramb2", "Qchannel2",
61def6bd
KB		 158 /* Pseudo-registers. */
159 "coprocessor", "MAC"
160 };
60e81fcc
NS		 161 static const char *array_names[MT_COPRO_PSEUDOREG_REGS
162 * MT_COPRO_PSEUDOREG_DIM_1
163 * MT_COPRO_PSEUDOREG_DIM_2];
164
165 if (regnum < 0)
166 return "";
167 if (regnum < ARRAY_SIZE (register_names))
168 return register_names[regnum];
169 if (array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY])
170 return array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY];
171
172 {
173 char *name;
174 const char *stub;
175 unsigned dim_1;
176 unsigned dim_2;
177 unsigned index;
178
179 regnum -= MT_COPRO_PSEUDOREG_ARRAY;
180 index = regnum % MT_COPRO_PSEUDOREG_REGS;
181 dim_2 = (regnum / MT_COPRO_PSEUDOREG_REGS) % MT_COPRO_PSEUDOREG_DIM_2;
182 dim_1 = ((regnum / MT_COPRO_PSEUDOREG_REGS / MT_COPRO_PSEUDOREG_DIM_2)
183 % MT_COPRO_PSEUDOREG_DIM_1);
184
03a73f77 185 if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM)
60e81fcc 186 stub = register_names[MT_MAC_PSEUDOREG_REGNUM];
03a73f77 187 else if (index >= MT_NUM_REGS - MT_CPR0_REGNUM)
60e81fcc
NS		 188 stub = "";
189 else
190 stub = register_names[index + MT_CPR0_REGNUM];
191 if (!*stub)
192 {
193 array_names[regnum] = stub;
194 return stub;
195 }
196 name = xmalloc (30);
197 sprintf (name, "copro_%d_%d_%s", dim_1, dim_2, stub);
198 array_names[regnum] = name;
199 return name;
200 }
201}
61def6bd 202
60e81fcc
NS		 203/* Return the type of a coprocessor register. */
204
205static struct type *
206mt_copro_register_type (struct gdbarch *arch, int regnum)
207{
208 switch (regnum)
209 {
210 case MT_INT_ENABLE_REGNUM:
211 case MT_ICHANNEL_REGNUM:
212 case MT_QCHANNEL_REGNUM:
213 case MT_ISCRAMB_REGNUM:
214 case MT_QSCRAMB_REGNUM:
215 return builtin_type_int32;
216 case MT_BYPA_REGNUM:
217 case MT_BYPB_REGNUM:
218 case MT_BYPC_REGNUM:
219 case MT_Z1_REGNUM:
220 case MT_Z2_REGNUM:
221 case MT_OUT_REGNUM:
03a73f77
MM		 222 case MT_ZI2_REGNUM:
223 case MT_ZQ2_REGNUM:
60e81fcc
NS		 224 return builtin_type_int16;
225 case MT_EXMAC_REGNUM:
226 case MT_MAC_REGNUM:
227 return builtin_type_uint32;
228 case MT_CONTEXT_REGNUM:
0dfff4cb 229 return builtin_type (arch)->builtin_long_long;
60e81fcc 230 case MT_FLAG_REGNUM:
0dfff4cb 231 return builtin_type (arch)->builtin_unsigned_char;
60e81fcc
NS		 232 default:
233 if (regnum >= MT_CPR0_REGNUM && regnum <= MT_CPR15_REGNUM)
234 return builtin_type_int16;
03a73f77 235 else if (regnum == MT_CPR0_REGNUM + MT_COPRO_PSEUDOREG_MAC_REGNUM)
60e81fcc
NS		 236 {
237 if (gdbarch_bfd_arch_info (arch)->mach == bfd_mach_mrisc2
238 || gdbarch_bfd_arch_info (arch)->mach == bfd_mach_ms2)
239 return builtin_type_uint64;
240 else
241 return builtin_type_uint32;
242 }
243 else
244 return builtin_type_uint32;
245 }
61def6bd
KB		 246}
247
248/* Given ARCH and a register number specified by REGNUM, return the
249 type of that register. */
250
251static struct type *
d031aafb 252mt_register_type (struct gdbarch *arch, int regnum)
61def6bd 253{
fde6c819 254 static struct type *copro_type = NULL;
61def6bd 255
d031aafb 256 if (regnum >= 0 && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS)
61def6bd 257 {
fde6c819 258 if (copro_type == NULL)
61def6bd
KB		 259 {
260 struct type *temp;
6d84d3d8 261 temp = create_range_type (NULL, builtin_type_int32, 0, 1);
61def6bd
KB		 262 copro_type = create_array_type (NULL, builtin_type_int16, temp);
263 }
264 switch (regnum)
265 {
d031aafb
NS		 266 case MT_PC_REGNUM:
267 case MT_RA_REGNUM:
268 case MT_IRA_REGNUM:
fde6c819 269 return builtin_type (arch)->builtin_func_ptr;
d031aafb
NS		 270 case MT_SP_REGNUM:
271 case MT_FP_REGNUM:
fde6c819 272 return builtin_type (arch)->builtin_data_ptr;
d031aafb
NS		 273 case MT_COPRO_REGNUM:
274 case MT_COPRO_PSEUDOREG_REGNUM:
61def6bd 275 return copro_type;
d031aafb 276 case MT_MAC_PSEUDOREG_REGNUM:
60e81fcc
NS		 277 return mt_copro_register_type (arch,
278 MT_CPR0_REGNUM
03a73f77 279 + MT_COPRO_PSEUDOREG_MAC_REGNUM);
61def6bd 280 default:
d031aafb 281 if (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM)
61def6bd 282 return builtin_type_int32;
60e81fcc
NS		 283 else if (regnum < MT_COPRO_PSEUDOREG_ARRAY)
284 return mt_copro_register_type (arch, regnum);
285 else
286 {
287 regnum -= MT_COPRO_PSEUDOREG_ARRAY;
288 regnum %= MT_COPRO_PSEUDOREG_REGS;
289 regnum += MT_CPR0_REGNUM;
290 return mt_copro_register_type (arch, regnum);
291 }
61def6bd
KB		 292 }
293 }
294 internal_error (__FILE__, __LINE__,
d031aafb 295 _("mt_register_type: illegal register number %d"), regnum);
61def6bd
KB		 296}
297
298/* Return true if register REGNUM is a member of the register group
299 specified by GROUP. */
300
301static int
d031aafb 302mt_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
61def6bd
KB		 303 struct reggroup *group)
304{
305 /* Groups of registers that can be displayed via "info reg". */
306 if (group == all_reggroup)
307 return (regnum >= 0
d031aafb 308 && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS
d93859e2 309 && mt_register_name (gdbarch, regnum)[0] != '\0');
61def6bd
KB		 310
311 if (group == general_reggroup)
d031aafb 312 return (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM);
61def6bd
KB		 313
314 if (group == float_reggroup)
315 return 0; /* No float regs. */
316
317 if (group == vector_reggroup)
318 return 0; /* No vector regs. */
319
320 /* For any that are not handled above. */
321 return default_register_reggroup_p (gdbarch, regnum, group);
322}
323
324/* Return the return value convention used for a given type TYPE.
325 Optionally, fetch or set the return value via READBUF or
326 WRITEBUF respectively using REGCACHE for the register
327 values. */
328
329static enum return_value_convention
c055b101
CV		 330mt_return_value (struct gdbarch *gdbarch, struct type *func_type,
331 struct type *type, struct regcache *regcache,
332 gdb_byte *readbuf, const gdb_byte *writebuf)
61def6bd
KB		 333{
334 if (TYPE_LENGTH (type) > 4)
335 {
336 /* Return values > 4 bytes are returned in memory,
337 pointed to by R11. */
338 if (readbuf)
339 {
340 ULONGEST addr;
341
d031aafb 342 regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr);
61def6bd
KB		 343 read_memory (addr, readbuf, TYPE_LENGTH (type));
344 }
345
346 if (writebuf)
347 {
348 ULONGEST addr;
349
d031aafb 350 regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr);
61def6bd
KB		 351 write_memory (addr, writebuf, TYPE_LENGTH (type));
352 }
353
354 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
355 }
356 else
357 {
358 if (readbuf)
359 {
360 ULONGEST temp;
361
362 /* Return values of <= 4 bytes are returned in R11. */
d031aafb 363 regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &temp);
61def6bd
KB		 364 store_unsigned_integer (readbuf, TYPE_LENGTH (type), temp);
365 }
366
367 if (writebuf)
368 {
369 if (TYPE_LENGTH (type) < 4)
370 {
371 gdb_byte buf[4];
372 /* Add leading zeros to the value. */
373 memset (buf, 0, sizeof (buf));
374 memcpy (buf + sizeof (buf) - TYPE_LENGTH (type),
375 writebuf, TYPE_LENGTH (type));
d031aafb 376 regcache_cooked_write (regcache, MT_R11_REGNUM, buf);
61def6bd
KB		 377 }
378 else /* (TYPE_LENGTH (type) == 4 */
d031aafb 379 regcache_cooked_write (regcache, MT_R11_REGNUM, writebuf);
61def6bd
KB		 380 }
381
382 return RETURN_VALUE_REGISTER_CONVENTION;
383 }
384}
385
386/* If the input address, PC, is in a function prologue, return the
387 address of the end of the prologue, otherwise return the input
388 address.
389
390 Note: PC is likely to be the function start, since this function
391 is mainly used for advancing a breakpoint to the first line, or
392 stepping to the first line when we have stepped into a function
393 call. */
394
395static CORE_ADDR
6093d2eb 396mt_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
61def6bd
KB		 397{
398 CORE_ADDR func_addr = 0, func_end = 0;
399 char *func_name;
400 unsigned long instr;
401
402 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
403 {
404 struct symtab_and_line sal;
405 struct symbol *sym;
406
407 /* Found a function. */
2570f2b7 408 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL);
61def6bd
KB		 409 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
410 {
411 /* Don't use this trick for assembly source files. */
412 sal = find_pc_line (func_addr, 0);
413
414 if (sal.end && sal.end < func_end)
415 {
416 /* Found a line number, use it as end of prologue. */
417 return sal.end;
418 }
419 }
420 }
421
422 /* No function symbol, or no line symbol. Use prologue scanning method. */
423 for (;; pc += 4)
424 {
425 instr = read_memory_unsigned_integer (pc, 4);
426 if (instr == 0x12000000) /* nop */
427 continue;
428 if (instr == 0x12ddc000) /* copy sp into fp */
429 continue;
430 instr >>= 16;
431 if (instr == 0x05dd) /* subi sp, sp, imm */
432 continue;
433 if (instr >= 0x43c0 && instr <= 0x43df) /* push */
434 continue;
435 /* Not an obvious prologue instruction. */
436 break;
437 }
438
439 return pc;
440}
441
442/* The breakpoint instruction must be the same size as the smallest
443 instruction in the instruction set.
444
3950dc3f
NS		 445 The BP for ms1 is defined as 0x68000000 (BREAK).
446 The BP for ms2 is defined as 0x69000000 (illegal) */
61def6bd
KB		 447
448static const gdb_byte *
67d57894
MD		 449mt_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
450 int *bp_size)
61def6bd 451{
3950dc3f
NS		 452 static gdb_byte ms1_breakpoint[] = { 0x68, 0, 0, 0 };
453 static gdb_byte ms2_breakpoint[] = { 0x69, 0, 0, 0 };
61def6bd
KB		 454
455 *bp_size = 4;
67d57894 456 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
3950dc3f
NS		 457 return ms2_breakpoint;
458
459 return ms1_breakpoint;
61def6bd
KB		 460}
461
60e81fcc
NS		 462/* Select the correct coprocessor register bank. Return the pseudo
463 regnum we really want to read. */
464
465static int
466mt_select_coprocessor (struct gdbarch *gdbarch,
467 struct regcache *regcache, int regno)
468{
469 unsigned index, base;
470 gdb_byte copro[4];
471
472 /* Get the copro pseudo regnum. */
473 regcache_raw_read (regcache, MT_COPRO_REGNUM, copro);
474 base = (extract_signed_integer (&copro[0], 2) * MT_COPRO_PSEUDOREG_DIM_2
475 + extract_signed_integer (&copro[2], 2));
476
477 regno -= MT_COPRO_PSEUDOREG_ARRAY;
478 index = regno % MT_COPRO_PSEUDOREG_REGS;
479 regno /= MT_COPRO_PSEUDOREG_REGS;
480 if (base != regno)
481 {
482 /* Select the correct coprocessor register bank. Invalidate the
483 coprocessor register cache. */
484 unsigned ix;
485
486 store_signed_integer (&copro[0], 2, regno / MT_COPRO_PSEUDOREG_DIM_2);
487 store_signed_integer (&copro[2], 2, regno % MT_COPRO_PSEUDOREG_DIM_2);
488 regcache_raw_write (regcache, MT_COPRO_REGNUM, copro);
489
490 /* We must flush the cache, as it is now invalid. */
491 for (ix = MT_NUM_CPU_REGS; ix != MT_NUM_REGS; ix++)
9c5ea4d9 492 regcache_invalidate (regcache, ix);
60e81fcc
NS		 493 }
494
495 return index;
496}
497
61def6bd
KB		 498/* Fetch the pseudo registers:
499
60e81fcc 500 There are two regular pseudo-registers:
61def6bd
KB		 501 1) The 'coprocessor' pseudo-register (which mirrors the
502 "real" coprocessor register sent by the target), and
503 2) The 'MAC' pseudo-register (which represents the union
504 of the original 32 bit target MAC register and the new
60e81fcc
NS		 505 8-bit extended-MAC register).
506
507 Additionally there is an array of coprocessor registers which track
508 the coprocessor registers for each coprocessor. */
61def6bd
KB		 509
510static void
d031aafb 511mt_pseudo_register_read (struct gdbarch *gdbarch,
61def6bd
KB		 512 struct regcache *regcache, int regno, gdb_byte *buf)
513{
514 switch (regno)
515 {
d031aafb
NS		 516 case MT_COPRO_REGNUM:
517 case MT_COPRO_PSEUDOREG_REGNUM:
518 regcache_raw_read (regcache, MT_COPRO_REGNUM, buf);
61def6bd 519 break;
d031aafb
NS		 520 case MT_MAC_REGNUM:
521 case MT_MAC_PSEUDOREG_REGNUM:
3950dc3f
NS		 522 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2
523 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
61def6bd
KB		 524 {
525 ULONGEST oldmac = 0, ext_mac = 0;
526 ULONGEST newmac;
527
d031aafb
NS		 528 regcache_cooked_read_unsigned (regcache, MT_MAC_REGNUM, &oldmac);
529 regcache_cooked_read_unsigned (regcache, MT_EXMAC_REGNUM, &ext_mac);
61def6bd
KB		 530 newmac =
531 (oldmac & 0xffffffff) | ((long long) (ext_mac & 0xff) << 32);
532 store_signed_integer (buf, 8, newmac);
533 }
534 else
d031aafb 535 regcache_raw_read (regcache, MT_MAC_REGNUM, buf);
61def6bd
KB		 536 break;
537 default:
60e81fcc
NS		 538 {
539 unsigned index = mt_select_coprocessor (gdbarch, regcache, regno);
540
03a73f77 541 if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM)
60e81fcc 542 mt_pseudo_register_read (gdbarch, regcache,
03a73f77 543 MT_MAC_PSEUDOREG_REGNUM, buf);
60e81fcc
NS		 544 else if (index < MT_NUM_REGS - MT_CPR0_REGNUM)
545 regcache_raw_read (regcache, index + MT_CPR0_REGNUM, buf);
546 }
61def6bd
KB		 547 break;
548 }
549}
550
551/* Write the pseudo registers:
552
d031aafb 553 Mt pseudo-registers are stored directly to the target. The
61def6bd
KB		 554 'coprocessor' register is special, because when it is modified, all
555 the other coprocessor regs must be flushed from the reg cache. */
556
557static void
d031aafb 558mt_pseudo_register_write (struct gdbarch *gdbarch,
61def6bd
KB		 559 struct regcache *regcache,
560 int regno, const gdb_byte *buf)
561{
562 int i;
563
564 switch (regno)
565 {
d031aafb
NS		 566 case MT_COPRO_REGNUM:
567 case MT_COPRO_PSEUDOREG_REGNUM:
568 regcache_raw_write (regcache, MT_COPRO_REGNUM, buf);
569 for (i = MT_NUM_CPU_REGS; i < MT_NUM_REGS; i++)
9c5ea4d9 570 regcache_invalidate (regcache, i);
61def6bd 571 break;
d031aafb
NS		 572 case MT_MAC_REGNUM:
573 case MT_MAC_PSEUDOREG_REGNUM:
3950dc3f
NS		 574 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2
575 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
61def6bd
KB		 576 {
577 /* The 8-byte MAC pseudo-register must be broken down into two
578 32-byte registers. */
579 unsigned int oldmac, ext_mac;
580 ULONGEST newmac;
581
582 newmac = extract_unsigned_integer (buf, 8);
583 oldmac = newmac & 0xffffffff;
584 ext_mac = (newmac >> 32) & 0xff;
d031aafb
NS		 585 regcache_cooked_write_unsigned (regcache, MT_MAC_REGNUM, oldmac);
586 regcache_cooked_write_unsigned (regcache, MT_EXMAC_REGNUM, ext_mac);
61def6bd
KB		 587 }
588 else
d031aafb 589 regcache_raw_write (regcache, MT_MAC_REGNUM, buf);
61def6bd
KB		 590 break;
591 default:
60e81fcc
NS		 592 {
593 unsigned index = mt_select_coprocessor (gdbarch, regcache, regno);
594
03a73f77 595 if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM)
60e81fcc 596 mt_pseudo_register_write (gdbarch, regcache,
03a73f77 597 MT_MAC_PSEUDOREG_REGNUM, buf);
60e81fcc
NS		 598 else if (index < MT_NUM_REGS - MT_CPR0_REGNUM)
599 regcache_raw_write (regcache, index + MT_CPR0_REGNUM, buf);
600 }
61def6bd
KB		 601 break;
602 }
603}
604
605static CORE_ADDR
d031aafb 606mt_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
61def6bd
KB		 607{
608 /* Register size is 4 bytes. */
609 return align_down (sp, 4);
610}
611
612/* Implements the "info registers" command. When ``all'' is non-zero,
613 the coprocessor registers will be printed in addition to the rest
614 of the registers. */
615
616static void
d031aafb 617mt_registers_info (struct gdbarch *gdbarch,
d93859e2
UW		 618 struct ui_file *file,
619 struct frame_info *frame, int regnum, int all)
61def6bd
KB		 620{
621 if (regnum == -1)
622 {
623 int lim;
624
d031aafb 625 lim = all ? MT_NUM_REGS : MT_NUM_CPU_REGS;
61def6bd
KB		 626
627 for (regnum = 0; regnum < lim; regnum++)
628 {
629 /* Don't display the Qchannel register since it will be displayed
630 along with Ichannel. (See below.) */
d031aafb 631 if (regnum == MT_QCHANNEL_REGNUM)
61def6bd
KB		 632 continue;
633
d031aafb 634 mt_registers_info (gdbarch, file, frame, regnum, all);
61def6bd
KB		 635
636 /* Display the Qchannel register immediately after Ichannel. */
d031aafb
NS		 637 if (regnum == MT_ICHANNEL_REGNUM)
638 mt_registers_info (gdbarch, file, frame, MT_QCHANNEL_REGNUM, all);
61def6bd
KB		 639 }
640 }
641 else
642 {
d031aafb 643 if (regnum == MT_EXMAC_REGNUM)
61def6bd 644 return;
d031aafb 645 else if (regnum == MT_CONTEXT_REGNUM)
61def6bd
KB		 646 {
647 /* Special output handling for 38-bit context register. */
648 unsigned char *buff;
649 unsigned int *bytes, i, regsize;
650
651 regsize = register_size (gdbarch, regnum);
652
653 buff = alloca (regsize);
654 bytes = alloca (regsize * sizeof (*bytes));
655
656 frame_register_read (frame, regnum, buff);
657
c9f4d572 658 fputs_filtered (gdbarch_register_name
d93859e2 659 (gdbarch, regnum), file);
c9f4d572 660 print_spaces_filtered (15 - strlen (gdbarch_register_name
d93859e2 661 (gdbarch, regnum)),
c9f4d572 662 file);
61def6bd
KB		 663 fputs_filtered ("0x", file);
664
665 for (i = 0; i < regsize; i++)
666 fprintf_filtered (file, "%02x", (unsigned int)
667 extract_unsigned_integer (buff + i, 1));
668 fputs_filtered ("\t", file);
669 print_longest (file, 'd', 0,
670 extract_unsigned_integer (buff, regsize));
671 fputs_filtered ("\n", file);
672 }
d031aafb
NS		 673 else if (regnum == MT_COPRO_REGNUM
674 || regnum == MT_COPRO_PSEUDOREG_REGNUM)
61def6bd
KB		 675 {
676 /* Special output handling for the 'coprocessor' register. */
58b78171 677 gdb_byte *buf;
61def6bd 678
d031aafb
NS		 679 buf = alloca (register_size (gdbarch, MT_COPRO_REGNUM));
680 frame_register_read (frame, MT_COPRO_REGNUM, buf);
61def6bd 681 /* And print. */
d031aafb 682 regnum = MT_COPRO_PSEUDOREG_REGNUM;
d93859e2 683 fputs_filtered (gdbarch_register_name (gdbarch, regnum),
c9f4d572
UW		 684 file);
685 print_spaces_filtered (15 - strlen (gdbarch_register_name
d93859e2 686 (gdbarch, regnum)),
c9f4d572 687 file);
61def6bd 688 val_print (register_type (gdbarch, regnum), buf,
d8ca156b
JB		 689 0, 0, file, 0, 1, 0, Val_no_prettyprint,
690 current_language);
61def6bd
KB		 691 fputs_filtered ("\n", file);
692 }
d031aafb 693 else if (regnum == MT_MAC_REGNUM || regnum == MT_MAC_PSEUDOREG_REGNUM)
61def6bd
KB		 694 {
695 ULONGEST oldmac, ext_mac, newmac;
58b78171 696 gdb_byte buf[3 * sizeof (LONGEST)];
61def6bd
KB		 697
698 /* Get the two "real" mac registers. */
d031aafb 699 frame_register_read (frame, MT_MAC_REGNUM, buf);
3950dc3f 700 oldmac = extract_unsigned_integer
d031aafb 701 (buf, register_size (gdbarch, MT_MAC_REGNUM));
58b78171
NS		 702 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2
703 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
61def6bd 704 {
d031aafb 705 frame_register_read (frame, MT_EXMAC_REGNUM, buf);
3950dc3f 706 ext_mac = extract_unsigned_integer
d031aafb 707 (buf, register_size (gdbarch, MT_EXMAC_REGNUM));
61def6bd
KB		 708 }
709 else
710 ext_mac = 0;
711
712 /* Add them together. */
713 newmac = (oldmac & 0xffffffff) + ((ext_mac & 0xff) << 32);
714
715 /* And print. */
d031aafb 716 regnum = MT_MAC_PSEUDOREG_REGNUM;
d93859e2 717 fputs_filtered (gdbarch_register_name (gdbarch, regnum),
c9f4d572
UW		 718 file);
719 print_spaces_filtered (15 - strlen (gdbarch_register_name
d93859e2 720 (gdbarch, regnum)),
c9f4d572 721 file);
61def6bd
KB		 722 fputs_filtered ("0x", file);
723 print_longest (file, 'x', 0, newmac);
724 fputs_filtered ("\t", file);
725 print_longest (file, 'u', 0, newmac);
726 fputs_filtered ("\n", file);
727 }
728 else
729 default_print_registers_info (gdbarch, file, frame, regnum, all);
730 }
731}
732
733/* Set up the callee's arguments for an inferior function call. The
734 arguments are pushed on the stack or are placed in registers as
735 appropriate. It also sets up the return address (which points to
736 the call dummy breakpoint).
737
738 Returns the updated (and aligned) stack pointer. */
739
740static CORE_ADDR
d031aafb 741mt_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
61def6bd
KB		 742 struct regcache *regcache, CORE_ADDR bp_addr,
743 int nargs, struct value **args, CORE_ADDR sp,
744 int struct_return, CORE_ADDR struct_addr)
745{
746#define wordsize 4
d031aafb
NS		 747 gdb_byte buf[MT_MAX_STRUCT_SIZE];
748 int argreg = MT_1ST_ARGREG;
61def6bd
KB		 749 int split_param_len = 0;
750 int stack_dest = sp;
751 int slacklen;
752 int typelen;
753 int i, j;
754
d031aafb
NS		 755 /* First handle however many args we can fit into MT_1ST_ARGREG thru
756 MT_LAST_ARGREG. */
757 for (i = 0; i < nargs && argreg <= MT_LAST_ARGREG; i++)
61def6bd 758 {
58b78171 759 const gdb_byte *val;
61def6bd
KB		 760 typelen = TYPE_LENGTH (value_type (args[i]));
761 switch (typelen)
762 {
763 case 1:
764 case 2:
765 case 3:
766 case 4:
767 regcache_cooked_write_unsigned (regcache, argreg++,
768 extract_unsigned_integer
769 (value_contents (args[i]),
770 wordsize));
771 break;
772 case 8:
773 case 12:
774 case 16:
775 val = value_contents (args[i]);
776 while (typelen > 0)
777 {
d031aafb 778 if (argreg <= MT_LAST_ARGREG)
61def6bd
KB		 779 {
780 /* This word of the argument is passed in a register. */
781 regcache_cooked_write_unsigned (regcache, argreg++,
782 extract_unsigned_integer
783 (val, wordsize));
784 typelen -= wordsize;
785 val += wordsize;
786 }
787 else
788 {
789 /* Remainder of this arg must be passed on the stack
790 (deferred to do later). */
791 split_param_len = typelen;
792 memcpy (buf, val, typelen);
793 break; /* No more args can be handled in regs. */
794 }
795 }
796 break;
797 default:
798 /* By reverse engineering of gcc output, args bigger than
799 16 bytes go on the stack, and their address is passed
800 in the argreg. */
801 stack_dest -= typelen;
802 write_memory (stack_dest, value_contents (args[i]), typelen);
803 regcache_cooked_write_unsigned (regcache, argreg++, stack_dest);
804 break;
805 }
806 }
807
808 /* Next, the rest of the arguments go onto the stack, in reverse order. */
809 for (j = nargs - 1; j >= i; j--)
810 {
58b78171
NS		 811 gdb_byte *val;
812
61def6bd
KB		 813 /* Right-justify the value in an aligned-length buffer. */
814 typelen = TYPE_LENGTH (value_type (args[j]));
815 slacklen = (wordsize - (typelen % wordsize)) % wordsize;
816 val = alloca (typelen + slacklen);
817 memcpy (val, value_contents (args[j]), typelen);
818 memset (val + typelen, 0, slacklen);
819 /* Now write this data to the stack. */
820 stack_dest -= typelen + slacklen;
821 write_memory (stack_dest, val, typelen + slacklen);
822 }
823
824 /* Finally, if a param needs to be split between registers and stack,
825 write the second half to the stack now. */
826 if (split_param_len != 0)
827 {
828 stack_dest -= split_param_len;
829 write_memory (stack_dest, buf, split_param_len);
830 }
831
832 /* Set up return address (provided to us as bp_addr). */
d031aafb 833 regcache_cooked_write_unsigned (regcache, MT_RA_REGNUM, bp_addr);
61def6bd
KB		 834
835 /* Store struct return address, if given. */
836 if (struct_return && struct_addr != 0)
d031aafb 837 regcache_cooked_write_unsigned (regcache, MT_R11_REGNUM, struct_addr);
61def6bd
KB		 838
839 /* Set aside 16 bytes for the callee to save regs 1-4. */
840 stack_dest -= 16;
841
842 /* Update the stack pointer. */
d031aafb 843 regcache_cooked_write_unsigned (regcache, MT_SP_REGNUM, stack_dest);
61def6bd
KB		 844
845 /* And that should do it. Return the new stack pointer. */
846 return stack_dest;
847}
848
849
850/* The 'unwind_cache' data structure. */
851
d031aafb 852struct mt_unwind_cache
61def6bd
KB		 853{
854 /* The previous frame's inner most stack address.
855 Used as this frame ID's stack_addr. */
856 CORE_ADDR prev_sp;
857 CORE_ADDR frame_base;
858 int framesize;
859 int frameless_p;
860
861 /* Table indicating the location of each and every register. */
862 struct trad_frame_saved_reg *saved_regs;
863};
864
865/* Initialize an unwind_cache. Build up the saved_regs table etc. for
866 the frame. */
867
d031aafb 868static struct mt_unwind_cache *
94afd7a6 869mt_frame_unwind_cache (struct frame_info *this_frame,
61def6bd
KB		 870 void **this_prologue_cache)
871{
872 struct gdbarch *gdbarch;
d031aafb 873 struct mt_unwind_cache *info;
61def6bd
KB		 874 CORE_ADDR next_addr, start_addr, end_addr, prologue_end_addr;
875 unsigned long instr, upper_half, delayed_store = 0;
876 int regnum, offset;
877 ULONGEST sp, fp;
878
879 if ((*this_prologue_cache))
880 return (*this_prologue_cache);
881
94afd7a6 882 gdbarch = get_frame_arch (this_frame);
d031aafb 883 info = FRAME_OBSTACK_ZALLOC (struct mt_unwind_cache);
61def6bd
KB		 884 (*this_prologue_cache) = info;
885
886 info->prev_sp = 0;
887 info->framesize = 0;
888 info->frame_base = 0;
889 info->frameless_p = 1;
94afd7a6 890 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61def6bd
KB		 891
892 /* Grab the frame-relative values of SP and FP, needed below.
893 The frame_saved_register function will find them on the
894 stack or in the registers as appropriate. */
94afd7a6
UW		 895 sp = get_frame_register_unsigned (this_frame, MT_SP_REGNUM);
896 fp = get_frame_register_unsigned (this_frame, MT_FP_REGNUM);
61def6bd 897
94afd7a6 898 start_addr = get_frame_func (this_frame);
61def6bd
KB		 899
900 /* Return early if GDB couldn't find the function. */
901 if (start_addr == 0)
902 return info;
903
94afd7a6 904 end_addr = get_frame_pc (this_frame);
61def6bd
KB		 905 prologue_end_addr = skip_prologue_using_sal (start_addr);
906 if (end_addr == 0)
907 for (next_addr = start_addr; next_addr < end_addr; next_addr += 4)
908 {
94afd7a6 909 instr = get_frame_memory_unsigned (this_frame, next_addr, 4);
61def6bd
KB		 910 if (delayed_store) /* previous instr was a push */
911 {
912 upper_half = delayed_store >> 16;
913 regnum = upper_half & 0xf;
914 offset = delayed_store & 0xffff;
915 switch (upper_half & 0xfff0)
916 {
917 case 0x43c0: /* push using frame pointer */
918 info->saved_regs[regnum].addr = offset;
919 break;
920 case 0x43d0: /* push using stack pointer */
921 info->saved_regs[regnum].addr = offset;
922 break;
923 default: /* lint */
924 break;
925 }
926 delayed_store = 0;
927 }
928
929 switch (instr)
930 {
931 case 0x12000000: /* NO-OP */
932 continue;
933 case 0x12ddc000: /* copy sp into fp */
934 info->frameless_p = 0; /* Record that the frame pointer is in use. */
935 continue;
936 default:
937 upper_half = instr >> 16;
938 if (upper_half == 0x05dd || /* subi sp, sp, imm */
939 upper_half == 0x07dd) /* subui sp, sp, imm */
940 {
941 /* Record the frame size. */
942 info->framesize = instr & 0xffff;
943 continue;
944 }
945 if ((upper_half & 0xfff0) == 0x43c0 || /* frame push */
946 (upper_half & 0xfff0) == 0x43d0) /* stack push */
947 {
948 /* Save this instruction, but don't record the
949 pushed register as 'saved' until we see the
950 next instruction. That's because of deferred stores
951 on this target -- GDB won't be able to read the register
952 from the stack until one instruction later. */
953 delayed_store = instr;
954 continue;
955 }
956 /* Not a prologue instruction. Is this the end of the prologue?
957 This is the most difficult decision; when to stop scanning.
958
959 If we have no line symbol, then the best thing we can do
960 is to stop scanning when we encounter an instruction that
961 is not likely to be a part of the prologue.
962
963 But if we do have a line symbol, then we should
964 keep scanning until we reach it (or we reach end_addr). */
965
966 if (prologue_end_addr && (prologue_end_addr > (next_addr + 4)))
967 continue; /* Keep scanning, recording saved_regs etc. */
968 else
969 break; /* Quit scanning: breakpoint can be set here. */
970 }
971 }
972
973 /* Special handling for the "saved" address of the SP:
974 The SP is of course never saved on the stack at all, so
975 by convention what we put here is simply the previous
976 _value_ of the SP (as opposed to an address where the
977 previous value would have been pushed). This will also
978 give us the frame base address. */
979
980 if (info->frameless_p)
981 {
982 info->frame_base = sp + info->framesize;
983 info->prev_sp = sp + info->framesize;
984 }
985 else
986 {
987 info->frame_base = fp + info->framesize;
988 info->prev_sp = fp + info->framesize;
989 }
990 /* Save prev_sp in saved_regs as a value, not as an address. */
d031aafb 991 trad_frame_set_value (info->saved_regs, MT_SP_REGNUM, info->prev_sp);
61def6bd
KB		 992
993 /* Now convert frame offsets to actual addresses (not offsets). */
d031aafb 994 for (regnum = 0; regnum < MT_NUM_REGS; regnum++)
61def6bd
KB		 995 if (trad_frame_addr_p (info->saved_regs, regnum))
996 info->saved_regs[regnum].addr += info->frame_base - info->framesize;
997
998 /* The call instruction moves the caller's PC in the callee's RA reg.
999 Since this is an unwind, do the reverse. Copy the location of RA
1000 into PC (the address / regnum) so that a request for PC will be
1001 converted into a request for the RA. */
d031aafb 1002 info->saved_regs[MT_PC_REGNUM] = info->saved_regs[MT_RA_REGNUM];
61def6bd
KB		 1003
1004 return info;
1005}
1006
1007static CORE_ADDR
d031aafb 1008mt_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
61def6bd
KB		 1009{
1010 ULONGEST pc;
1011
11411de3 1012 pc = frame_unwind_register_unsigned (next_frame, MT_PC_REGNUM);
61def6bd
KB		 1013 return pc;
1014}
1015
1016static CORE_ADDR
d031aafb 1017mt_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
61def6bd
KB		 1018{
1019 ULONGEST sp;
1020
11411de3 1021 sp = frame_unwind_register_unsigned (next_frame, MT_SP_REGNUM);
61def6bd
KB		 1022 return sp;
1023}
1024
94afd7a6
UW		 1025/* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
1026 frame. The frame ID's base needs to match the TOS value saved by
1027 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
61def6bd
KB		 1028
1029static struct frame_id
94afd7a6 1030mt_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61def6bd 1031{
94afd7a6
UW		 1032 CORE_ADDR sp = get_frame_register_unsigned (this_frame, MT_SP_REGNUM);
1033 return frame_id_build (sp, get_frame_pc (this_frame));
61def6bd
KB		 1034}
1035
1036/* Given a GDB frame, determine the address of the calling function's
1037 frame. This will be used to create a new GDB frame struct. */
1038
1039static void
94afd7a6 1040mt_frame_this_id (struct frame_info *this_frame,
61def6bd
KB		 1041 void **this_prologue_cache, struct frame_id *this_id)
1042{
d031aafb 1043 struct mt_unwind_cache *info =
94afd7a6 1044 mt_frame_unwind_cache (this_frame, this_prologue_cache);
61def6bd
KB		 1045
1046 if (!(info == NULL || info->prev_sp == 0))
94afd7a6 1047 (*this_id) = frame_id_build (info->prev_sp, get_frame_func (this_frame));
93d42b30 1048
61def6bd
KB		 1049 return;
1050}
1051
94afd7a6
UW		 1052static struct value *
1053mt_frame_prev_register (struct frame_info *this_frame,
1054 void **this_prologue_cache, int regnum)
61def6bd 1055{
d031aafb 1056 struct mt_unwind_cache *info =
94afd7a6 1057 mt_frame_unwind_cache (this_frame, this_prologue_cache);
61def6bd 1058
94afd7a6 1059 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61def6bd
KB		 1060}
1061
1062static CORE_ADDR
94afd7a6 1063mt_frame_base_address (struct frame_info *this_frame,
61def6bd
KB		 1064 void **this_prologue_cache)
1065{
d031aafb 1066 struct mt_unwind_cache *info =
94afd7a6 1067 mt_frame_unwind_cache (this_frame, this_prologue_cache);
61def6bd
KB		 1068
1069 return info->frame_base;
1070}
1071
1072/* This is a shared interface: the 'frame_unwind' object is what's
1073 returned by the 'sniffer' function, and in turn specifies how to
1074 get a frame's ID and prev_regs.
1075
1076 This exports the 'prev_register' and 'this_id' methods. */
1077
d031aafb 1078static const struct frame_unwind mt_frame_unwind = {
61def6bd 1079 NORMAL_FRAME,
d031aafb 1080 mt_frame_this_id,
94afd7a6
UW		 1081 mt_frame_prev_register,
1082 NULL,
1083 default_frame_sniffer
61def6bd
KB		 1084};
1085
61def6bd
KB		 1086/* Another shared interface: the 'frame_base' object specifies how to
1087 unwind a frame and secure the base addresses for frame objects
1088 (locals, args). */
1089
d031aafb
NS		 1090static struct frame_base mt_frame_base = {
1091 &mt_frame_unwind,
1092 mt_frame_base_address,
1093 mt_frame_base_address,
1094 mt_frame_base_address
61def6bd
KB		 1095};
1096
1097static struct gdbarch *
d031aafb 1098mt_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
61def6bd
KB		 1099{
1100 struct gdbarch *gdbarch;
61def6bd
KB		 1101
1102 /* Find a candidate among the list of pre-declared architectures. */
1103 arches = gdbarch_list_lookup_by_info (arches, &info);
1104 if (arches != NULL)
1105 return arches->gdbarch;
1106
1107 /* None found, create a new architecture from the information
1108 provided. */
1109 gdbarch = gdbarch_alloc (&info, NULL);
1110
cb5c8c39
DJ		 1111 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1112 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1113 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
61def6bd 1114
d031aafb
NS		 1115 set_gdbarch_register_name (gdbarch, mt_register_name);
1116 set_gdbarch_num_regs (gdbarch, MT_NUM_REGS);
1117 set_gdbarch_num_pseudo_regs (gdbarch, MT_NUM_PSEUDO_REGS);
1118 set_gdbarch_pc_regnum (gdbarch, MT_PC_REGNUM);
1119 set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM);
1120 set_gdbarch_pseudo_register_read (gdbarch, mt_pseudo_register_read);
1121 set_gdbarch_pseudo_register_write (gdbarch, mt_pseudo_register_write);
1122 set_gdbarch_skip_prologue (gdbarch, mt_skip_prologue);
61def6bd 1123 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
d031aafb 1124 set_gdbarch_breakpoint_from_pc (gdbarch, mt_breakpoint_from_pc);
61def6bd
KB		 1125 set_gdbarch_decr_pc_after_break (gdbarch, 0);
1126 set_gdbarch_frame_args_skip (gdbarch, 0);
d031aafb
NS		 1127 set_gdbarch_print_insn (gdbarch, print_insn_mt);
1128 set_gdbarch_register_type (gdbarch, mt_register_type);
1129 set_gdbarch_register_reggroup_p (gdbarch, mt_register_reggroup_p);
61def6bd 1130
d031aafb
NS		 1131 set_gdbarch_return_value (gdbarch, mt_return_value);
1132 set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM);
61def6bd 1133
d031aafb 1134 set_gdbarch_frame_align (gdbarch, mt_frame_align);
61def6bd 1135
d031aafb 1136 set_gdbarch_print_registers_info (gdbarch, mt_registers_info);
61def6bd 1137
d031aafb 1138 set_gdbarch_push_dummy_call (gdbarch, mt_push_dummy_call);
61def6bd
KB		 1139
1140 /* Target builtin data types. */
1141 set_gdbarch_short_bit (gdbarch, 16);
1142 set_gdbarch_int_bit (gdbarch, 32);
1143 set_gdbarch_long_bit (gdbarch, 32);
1144 set_gdbarch_long_long_bit (gdbarch, 64);
1145 set_gdbarch_float_bit (gdbarch, 32);
1146 set_gdbarch_double_bit (gdbarch, 64);
1147 set_gdbarch_long_double_bit (gdbarch, 64);
1148 set_gdbarch_ptr_bit (gdbarch, 32);
1149
1150 /* Register the DWARF 2 sniffer first, and then the traditional prologue
1151 based sniffer. */
94afd7a6
UW		 1152 dwarf2_append_unwinders (gdbarch);
1153 frame_unwind_append_unwinder (gdbarch, &mt_frame_unwind);
d031aafb 1154 frame_base_set_default (gdbarch, &mt_frame_base);
61def6bd
KB		 1155
1156 /* Register the 'unwind_pc' method. */
d031aafb
NS		 1157 set_gdbarch_unwind_pc (gdbarch, mt_unwind_pc);
1158 set_gdbarch_unwind_sp (gdbarch, mt_unwind_sp);
61def6bd
KB		 1159
1160 /* Methods for saving / extracting a dummy frame's ID.
1161 The ID's stack address must match the SP value returned by
1162 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */
94afd7a6 1163 set_gdbarch_dummy_id (gdbarch, mt_dummy_id);
61def6bd
KB		 1164
1165 return gdbarch;
1166}
1167
1168void
d031aafb 1169_initialize_mt_tdep (void)
61def6bd 1170{
d031aafb 1171 register_gdbarch_init (bfd_arch_mt, mt_gdbarch_init);
61def6bd 1172}
GDB Binutils - Deliverables
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