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df7e5265 | 1 | /* Debug register code for x86 (i386 and x86-64). |
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2 | |
3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifdef GDBSERVER | |
21 | #include "server.h" | |
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22 | #else |
23 | #include "defs.h" | |
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24 | #include "inferior.h" |
25 | #endif | |
df7e5265 | 26 | #include "x86-dregs.h" |
3a8ee006 | 27 | |
df7e5265 | 28 | /* Support for hardware watchpoints and breakpoints using the x86 |
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29 | debug registers. |
30 | ||
31 | This provides several functions for inserting and removing | |
32 | hardware-assisted breakpoints and watchpoints, testing if one or | |
33 | more of the watchpoints triggered and at what address, checking | |
34 | whether a given region can be watched, etc. | |
35 | ||
36 | The functions below implement debug registers sharing by reference | |
37 | counts, and allow to watch regions up to 16 bytes long. */ | |
38 | ||
42995dbd GB |
39 | /* Accessor macros for low-level function vector. */ |
40 | ||
41 | /* Can we update the inferior's debug registers? */ | |
df7e5265 | 42 | #define x86_dr_low_can_set_addr() (x86_dr_low.set_addr != NULL) |
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43 | |
44 | /* Update the inferior's debug register REGNUM from STATE. */ | |
df7e5265 GB |
45 | #define x86_dr_low_set_addr(new_state, i) \ |
46 | (x86_dr_low.set_addr ((i), (new_state)->dr_mirror[(i)])) | |
42995dbd GB |
47 | |
48 | /* Return the inferior's debug register REGNUM. */ | |
df7e5265 | 49 | #define x86_dr_low_get_addr(i) (x86_dr_low.get_addr ((i))) |
42995dbd GB |
50 | |
51 | /* Can we update the inferior's DR7 control register? */ | |
df7e5265 | 52 | #define x86_dr_low_can_set_control() (x86_dr_low.set_control != NULL) |
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53 | |
54 | /* Update the inferior's DR7 debug control register from STATE. */ | |
df7e5265 GB |
55 | #define x86_dr_low_set_control(new_state) \ |
56 | (x86_dr_low.set_control ((new_state)->dr_control_mirror)) | |
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57 | |
58 | /* Return the value of the inferior's DR7 debug control register. */ | |
df7e5265 | 59 | #define x86_dr_low_get_control() (x86_dr_low.get_control ()) |
42995dbd GB |
60 | |
61 | /* Return the value of the inferior's DR6 debug status register. */ | |
df7e5265 | 62 | #define x86_dr_low_get_status() (x86_dr_low.get_status ()) |
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63 | |
64 | /* Return the debug register size, in bytes. */ | |
df7e5265 GB |
65 | #define x86_get_debug_register_length() \ |
66 | (x86_dr_low.debug_register_length) | |
42995dbd | 67 | |
3a8ee006 | 68 | /* Support for 8-byte wide hw watchpoints. */ |
df7e5265 | 69 | #define TARGET_HAS_DR_LEN_8 (x86_get_debug_register_length () == 8) |
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70 | |
71 | /* DR7 Debug Control register fields. */ | |
72 | ||
73 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
74 | #define DR_CONTROL_SHIFT 16 | |
75 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
76 | #define DR_CONTROL_SIZE 4 | |
77 | ||
78 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
79 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ | |
80 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
81 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
82 | ||
83 | /* This is here for completeness. No platform supports this | |
84 | functionality yet (as of March 2001). Note that the DE flag in the | |
85 | CR4 register needs to be set to support this. */ | |
86 | #ifndef DR_RW_IORW | |
87 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ | |
88 | #endif | |
89 | ||
90 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
91 | is so we could OR this with the read/write field defined above. */ | |
92 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ | |
93 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
94 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
95 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
96 | ||
97 | /* Local and Global Enable flags in DR7. | |
98 | ||
99 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
100 | enabled only for the current task; the processor automatically | |
101 | clears this flag on every task switch. When the Global Enable flag | |
102 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
103 | processor never clears this flag. | |
104 | ||
105 | Currently, all watchpoint are locally enabled. If you need to | |
106 | enable them globally, read the comment which pertains to this in | |
df7e5265 | 107 | x86_insert_aligned_watchpoint below. */ |
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108 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
109 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
110 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
111 | ||
112 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
113 | flags). These are only required on i386, to allow detection of the | |
114 | exact instruction which caused a watchpoint to break; i486 and | |
115 | later processors do that automatically. We set these flags for | |
116 | backwards compatibility. */ | |
117 | #define DR_LOCAL_SLOWDOWN (0x100) | |
118 | #define DR_GLOBAL_SLOWDOWN (0x200) | |
119 | ||
120 | /* Fields reserved by Intel. This includes the GD (General Detect | |
121 | Enable) flag, which causes a debug exception to be generated when a | |
122 | MOV instruction accesses one of the debug registers. | |
123 | ||
124 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
125 | #define DR_CONTROL_RESERVED (0xFC00) | |
126 | ||
127 | /* Auxiliary helper macros. */ | |
128 | ||
129 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
df7e5265 | 130 | #define X86_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
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131 | |
132 | /* The I'th debug register is vacant if its Local and Global Enable | |
133 | bits are reset in the Debug Control register. */ | |
df7e5265 | 134 | #define X86_DR_VACANT(state, i) \ |
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135 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) |
136 | ||
137 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
df7e5265 | 138 | #define X86_DR_LOCAL_ENABLE(state, i) \ |
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139 | do { \ |
140 | (state)->dr_control_mirror |= \ | |
141 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
142 | } while (0) | |
143 | ||
144 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
df7e5265 | 145 | #define X86_DR_GLOBAL_ENABLE(state, i) \ |
3a8ee006 GB |
146 | do { \ |
147 | (state)->dr_control_mirror |= \ | |
148 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
149 | } while (0) | |
150 | ||
151 | /* Disable the break/watchpoint in the I'th debug register. */ | |
df7e5265 | 152 | #define X86_DR_DISABLE(state, i) \ |
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153 | do { \ |
154 | (state)->dr_control_mirror &= \ | |
155 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
156 | } while (0) | |
157 | ||
158 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
df7e5265 | 159 | #define X86_DR_SET_RW_LEN(state, i, rwlen) \ |
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160 | do { \ |
161 | (state)->dr_control_mirror &= \ | |
162 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
163 | (state)->dr_control_mirror |= \ | |
164 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
165 | } while (0) | |
166 | ||
167 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
df7e5265 | 168 | #define X86_DR_GET_RW_LEN(dr7, i) \ |
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169 | (((dr7) \ |
170 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
171 | ||
172 | /* Did the watchpoint whose address is in the I'th register break? */ | |
df7e5265 | 173 | #define X86_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
3a8ee006 | 174 | |
df7e5265 GB |
175 | /* Types of operations supported by x86_handle_nonaligned_watchpoint. */ |
176 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } x86_wp_op_t; | |
3a8ee006 | 177 | |
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178 | /* Print the values of the mirrored debug registers. */ |
179 | ||
180 | static void | |
df7e5265 GB |
181 | x86_show_dr (struct x86_debug_reg_state *state, |
182 | const char *func, CORE_ADDR addr, | |
183 | int len, enum target_hw_bp_type type) | |
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184 | { |
185 | int i; | |
186 | ||
187 | debug_printf ("%s", func); | |
188 | if (addr || len) | |
189 | debug_printf (" (addr=%s, len=%d, type=%s)", | |
190 | phex (addr, 8), len, | |
191 | type == hw_write ? "data-write" | |
192 | : (type == hw_read ? "data-read" | |
193 | : (type == hw_access ? "data-read/write" | |
194 | : (type == hw_execute ? "instruction-execute" | |
195 | /* FIXME: if/when I/O read/write | |
196 | watchpoints are supported, add them | |
197 | here. */ | |
198 | : "??unknown??")))); | |
199 | debug_printf (":\n"); | |
200 | debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", | |
201 | phex (state->dr_control_mirror, 8), | |
202 | phex (state->dr_status_mirror, 8)); | |
97ea6506 | 203 | ALL_DEBUG_ADDRESS_REGISTERS (i) |
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204 | { |
205 | debug_printf ("\ | |
206 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
207 | i, phex (state->dr_mirror[i], | |
df7e5265 | 208 | x86_get_debug_register_length ()), |
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209 | state->dr_ref_count[i], |
210 | i + 1, phex (state->dr_mirror[i + 1], | |
df7e5265 | 211 | x86_get_debug_register_length ()), |
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212 | state->dr_ref_count[i + 1]); |
213 | i++; | |
214 | } | |
215 | } | |
216 | ||
217 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
218 | region of LEN bytes for accesses of type TYPE. LEN is assumed to | |
219 | have the value of 1, 2, or 4. */ | |
220 | ||
221 | static unsigned | |
df7e5265 | 222 | x86_length_and_rw_bits (int len, enum target_hw_bp_type type) |
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223 | { |
224 | unsigned rw; | |
225 | ||
226 | switch (type) | |
227 | { | |
228 | case hw_execute: | |
229 | rw = DR_RW_EXECUTE; | |
230 | break; | |
231 | case hw_write: | |
232 | rw = DR_RW_WRITE; | |
233 | break; | |
234 | case hw_read: | |
235 | internal_error (__FILE__, __LINE__, | |
236 | _("The i386 doesn't support " | |
237 | "data-read watchpoints.\n")); | |
238 | case hw_access: | |
239 | rw = DR_RW_READ; | |
240 | break; | |
241 | #if 0 | |
242 | /* Not yet supported. */ | |
243 | case hw_io_access: | |
244 | rw = DR_RW_IORW; | |
245 | break; | |
246 | #endif | |
247 | default: | |
248 | internal_error (__FILE__, __LINE__, _("\ | |
df7e5265 | 249 | Invalid hardware breakpoint type %d in x86_length_and_rw_bits.\n"), |
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250 | (int) type); |
251 | } | |
252 | ||
253 | switch (len) | |
254 | { | |
255 | case 1: | |
256 | return (DR_LEN_1 | rw); | |
257 | case 2: | |
258 | return (DR_LEN_2 | rw); | |
259 | case 4: | |
260 | return (DR_LEN_4 | rw); | |
261 | case 8: | |
262 | if (TARGET_HAS_DR_LEN_8) | |
263 | return (DR_LEN_8 | rw); | |
264 | /* ELSE FALL THROUGH */ | |
265 | default: | |
266 | internal_error (__FILE__, __LINE__, _("\ | |
df7e5265 | 267 | Invalid hardware breakpoint length %d in x86_length_and_rw_bits.\n"), len); |
3a8ee006 GB |
268 | } |
269 | } | |
270 | ||
271 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
272 | according to the length of the region to watch. LEN_RW_BITS is the | |
273 | value of the bits from DR7 which describes the length and access | |
274 | type of the region to be watched by this watchpoint. Return 0 on | |
275 | success, -1 on failure. */ | |
276 | ||
277 | static int | |
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278 | x86_insert_aligned_watchpoint (struct x86_debug_reg_state *state, |
279 | CORE_ADDR addr, unsigned len_rw_bits) | |
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280 | { |
281 | int i; | |
282 | ||
df7e5265 | 283 | if (!x86_dr_low_can_set_addr () || !x86_dr_low_can_set_control ()) |
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284 | return -1; |
285 | ||
286 | /* First, look for an occupied debug register with the same address | |
287 | and the same RW and LEN definitions. If we find one, we can | |
288 | reuse it for this watchpoint as well (and save a register). */ | |
97ea6506 | 289 | ALL_DEBUG_ADDRESS_REGISTERS (i) |
3a8ee006 | 290 | { |
df7e5265 | 291 | if (!X86_DR_VACANT (state, i) |
3a8ee006 | 292 | && state->dr_mirror[i] == addr |
df7e5265 | 293 | && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) |
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294 | { |
295 | state->dr_ref_count[i]++; | |
296 | return 0; | |
297 | } | |
298 | } | |
299 | ||
300 | /* Next, look for a vacant debug register. */ | |
97ea6506 | 301 | ALL_DEBUG_ADDRESS_REGISTERS (i) |
3a8ee006 | 302 | { |
df7e5265 | 303 | if (X86_DR_VACANT (state, i)) |
3a8ee006 GB |
304 | break; |
305 | } | |
306 | ||
307 | /* No more debug registers! */ | |
308 | if (i >= DR_NADDR) | |
309 | return -1; | |
310 | ||
311 | /* Now set up the register I to watch our region. */ | |
312 | ||
313 | /* Record the info in our local mirrored array. */ | |
314 | state->dr_mirror[i] = addr; | |
315 | state->dr_ref_count[i] = 1; | |
df7e5265 | 316 | X86_DR_SET_RW_LEN (state, i, len_rw_bits); |
3a8ee006 | 317 | /* Note: we only enable the watchpoint locally, i.e. in the current |
df7e5265 | 318 | task. Currently, no x86 target allows or supports global |
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319 | watchpoints; however, if any target would want that in the |
320 | future, GDB should probably provide a command to control whether | |
321 | to enable watchpoints globally or locally, and the code below | |
322 | should use global or local enable and slow-down flags as | |
323 | appropriate. */ | |
df7e5265 | 324 | X86_DR_LOCAL_ENABLE (state, i); |
3a8ee006 | 325 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; |
df7e5265 | 326 | state->dr_control_mirror &= X86_DR_CONTROL_MASK; |
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327 | |
328 | return 0; | |
329 | } | |
330 | ||
331 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
332 | according to the length of the region to watch. LEN_RW_BITS is the | |
333 | value of the bits from DR7 which describes the length and access | |
334 | type of the region watched by this watchpoint. Return 0 on | |
335 | success, -1 on failure. */ | |
336 | ||
337 | static int | |
df7e5265 GB |
338 | x86_remove_aligned_watchpoint (struct x86_debug_reg_state *state, |
339 | CORE_ADDR addr, unsigned len_rw_bits) | |
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340 | { |
341 | int i, retval = -1; | |
8e9db26e | 342 | int all_vacant = 1; |
3a8ee006 | 343 | |
97ea6506 | 344 | ALL_DEBUG_ADDRESS_REGISTERS (i) |
3a8ee006 | 345 | { |
df7e5265 | 346 | if (!X86_DR_VACANT (state, i) |
3a8ee006 | 347 | && state->dr_mirror[i] == addr |
df7e5265 | 348 | && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) |
3a8ee006 GB |
349 | { |
350 | if (--state->dr_ref_count[i] == 0) /* No longer in use? */ | |
351 | { | |
352 | /* Reset our mirror. */ | |
353 | state->dr_mirror[i] = 0; | |
df7e5265 | 354 | X86_DR_DISABLE (state, i); |
8e9db26e PA |
355 | /* Even though not strictly necessary, clear out all |
356 | bits in DR_CONTROL related to this debug register. | |
357 | Debug output is clearer when we don't have stale bits | |
358 | in place. This also allows the assertion below. */ | |
df7e5265 | 359 | X86_DR_SET_RW_LEN (state, i, 0); |
3a8ee006 GB |
360 | } |
361 | retval = 0; | |
362 | } | |
8e9db26e | 363 | |
df7e5265 | 364 | if (!X86_DR_VACANT (state, i)) |
8e9db26e | 365 | all_vacant = 0; |
3a8ee006 GB |
366 | } |
367 | ||
8e9db26e PA |
368 | if (all_vacant) |
369 | { | |
370 | /* Even though not strictly necessary, clear out all of | |
371 | DR_CONTROL, so that when we have no debug registers in use, | |
372 | we end up with DR_CONTROL == 0. The Linux support relies on | |
373 | this for an optimization. Plus, it makes for clearer debug | |
374 | output. */ | |
375 | state->dr_control_mirror &= ~DR_LOCAL_SLOWDOWN; | |
376 | ||
377 | gdb_assert (state->dr_control_mirror == 0); | |
378 | } | |
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379 | return retval; |
380 | } | |
381 | ||
382 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
383 | number of debug registers required to watch a region at address | |
384 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
385 | successful insertion or removal, a positive number when queried | |
386 | about the number of registers, or -1 on failure. If WHAT is not a | |
387 | valid value, bombs through internal_error. */ | |
388 | ||
389 | static int | |
df7e5265 GB |
390 | x86_handle_nonaligned_watchpoint (struct x86_debug_reg_state *state, |
391 | x86_wp_op_t what, CORE_ADDR addr, int len, | |
392 | enum target_hw_bp_type type) | |
3a8ee006 GB |
393 | { |
394 | int retval = 0; | |
395 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; | |
396 | ||
397 | static const int size_try_array[8][8] = | |
398 | { | |
399 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ | |
400 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
401 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
402 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
403 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
404 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
405 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
406 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
407 | }; | |
408 | ||
409 | while (len > 0) | |
410 | { | |
411 | int align = addr % max_wp_len; | |
412 | /* Four (eight on AMD64) is the maximum length a debug register | |
413 | can watch. */ | |
414 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); | |
415 | int size = size_try_array[try][align]; | |
416 | ||
417 | if (what == WP_COUNT) | |
418 | { | |
419 | /* size_try_array[] is defined such that each iteration | |
420 | through the loop is guaranteed to produce an address and a | |
421 | size that can be watched with a single debug register. | |
422 | Thus, for counting the registers required to watch a | |
423 | region, we simply need to increment the count on each | |
424 | iteration. */ | |
425 | retval++; | |
426 | } | |
427 | else | |
428 | { | |
df7e5265 | 429 | unsigned len_rw = x86_length_and_rw_bits (size, type); |
3a8ee006 GB |
430 | |
431 | if (what == WP_INSERT) | |
df7e5265 | 432 | retval = x86_insert_aligned_watchpoint (state, addr, len_rw); |
3a8ee006 | 433 | else if (what == WP_REMOVE) |
df7e5265 | 434 | retval = x86_remove_aligned_watchpoint (state, addr, len_rw); |
3a8ee006 GB |
435 | else |
436 | internal_error (__FILE__, __LINE__, _("\ | |
df7e5265 | 437 | Invalid value %d of operation in x86_handle_nonaligned_watchpoint.\n"), |
3a8ee006 GB |
438 | (int) what); |
439 | if (retval) | |
440 | break; | |
441 | } | |
442 | ||
443 | addr += size; | |
444 | len -= size; | |
445 | } | |
446 | ||
447 | return retval; | |
448 | } | |
449 | ||
450 | /* Update the inferior debug registers state, in STATE, with the | |
451 | new debug registers state, in NEW_STATE. */ | |
452 | ||
453 | static void | |
df7e5265 GB |
454 | x86_update_inferior_debug_regs (struct x86_debug_reg_state *state, |
455 | struct x86_debug_reg_state *new_state) | |
3a8ee006 GB |
456 | { |
457 | int i; | |
458 | ||
97ea6506 | 459 | ALL_DEBUG_ADDRESS_REGISTERS (i) |
3a8ee006 | 460 | { |
df7e5265 GB |
461 | if (X86_DR_VACANT (new_state, i) != X86_DR_VACANT (state, i)) |
462 | x86_dr_low_set_addr (new_state, i); | |
3a8ee006 GB |
463 | else |
464 | gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); | |
465 | } | |
466 | ||
467 | if (new_state->dr_control_mirror != state->dr_control_mirror) | |
df7e5265 | 468 | x86_dr_low_set_control (new_state); |
3a8ee006 GB |
469 | |
470 | *state = *new_state; | |
471 | } | |
472 | ||
473 | /* Insert a watchpoint to watch a memory region which starts at | |
474 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
475 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
476 | ||
477 | int | |
df7e5265 GB |
478 | x86_dr_insert_watchpoint (struct x86_debug_reg_state *state, |
479 | enum target_hw_bp_type type, | |
480 | CORE_ADDR addr, int len) | |
3a8ee006 GB |
481 | { |
482 | int retval; | |
483 | /* Work on a local copy of the debug registers, and on success, | |
484 | commit the change back to the inferior. */ | |
df7e5265 | 485 | struct x86_debug_reg_state local_state = *state; |
3a8ee006 GB |
486 | |
487 | if (type == hw_read) | |
488 | return 1; /* unsupported */ | |
489 | ||
490 | if (((len != 1 && len != 2 && len != 4) | |
491 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
492 | || addr % len != 0) | |
493 | { | |
df7e5265 GB |
494 | retval = x86_handle_nonaligned_watchpoint (&local_state, |
495 | WP_INSERT, | |
496 | addr, len, type); | |
3a8ee006 GB |
497 | } |
498 | else | |
499 | { | |
df7e5265 | 500 | unsigned len_rw = x86_length_and_rw_bits (len, type); |
3a8ee006 | 501 | |
df7e5265 GB |
502 | retval = x86_insert_aligned_watchpoint (&local_state, |
503 | addr, len_rw); | |
3a8ee006 GB |
504 | } |
505 | ||
506 | if (retval == 0) | |
df7e5265 | 507 | x86_update_inferior_debug_regs (state, &local_state); |
3a8ee006 | 508 | |
c5e92cca | 509 | if (show_debug_regs) |
df7e5265 | 510 | x86_show_dr (state, "insert_watchpoint", addr, len, type); |
3a8ee006 GB |
511 | |
512 | return retval; | |
513 | } | |
514 | ||
515 | /* Remove a watchpoint that watched the memory region which starts at | |
516 | address ADDR, whose length is LEN bytes, and for accesses of the | |
517 | type TYPE. Return 0 on success, -1 on failure. */ | |
518 | ||
519 | int | |
df7e5265 GB |
520 | x86_dr_remove_watchpoint (struct x86_debug_reg_state *state, |
521 | enum target_hw_bp_type type, | |
522 | CORE_ADDR addr, int len) | |
3a8ee006 GB |
523 | { |
524 | int retval; | |
525 | /* Work on a local copy of the debug registers, and on success, | |
526 | commit the change back to the inferior. */ | |
df7e5265 | 527 | struct x86_debug_reg_state local_state = *state; |
3a8ee006 GB |
528 | |
529 | if (((len != 1 && len != 2 && len != 4) | |
530 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
531 | || addr % len != 0) | |
532 | { | |
df7e5265 GB |
533 | retval = x86_handle_nonaligned_watchpoint (&local_state, |
534 | WP_REMOVE, | |
535 | addr, len, type); | |
3a8ee006 GB |
536 | } |
537 | else | |
538 | { | |
df7e5265 | 539 | unsigned len_rw = x86_length_and_rw_bits (len, type); |
3a8ee006 | 540 | |
df7e5265 GB |
541 | retval = x86_remove_aligned_watchpoint (&local_state, |
542 | addr, len_rw); | |
3a8ee006 GB |
543 | } |
544 | ||
545 | if (retval == 0) | |
df7e5265 | 546 | x86_update_inferior_debug_regs (state, &local_state); |
3a8ee006 | 547 | |
c5e92cca | 548 | if (show_debug_regs) |
df7e5265 | 549 | x86_show_dr (state, "remove_watchpoint", addr, len, type); |
3a8ee006 GB |
550 | |
551 | return retval; | |
552 | } | |
553 | ||
554 | /* Return non-zero if we can watch a memory region that starts at | |
555 | address ADDR and whose length is LEN bytes. */ | |
556 | ||
557 | int | |
df7e5265 GB |
558 | x86_dr_region_ok_for_watchpoint (struct x86_debug_reg_state *state, |
559 | CORE_ADDR addr, int len) | |
3a8ee006 GB |
560 | { |
561 | int nregs; | |
562 | ||
563 | /* Compute how many aligned watchpoints we would need to cover this | |
564 | region. */ | |
df7e5265 | 565 | nregs = x86_handle_nonaligned_watchpoint (state, WP_COUNT, |
3a8ee006 GB |
566 | addr, len, hw_write); |
567 | return nregs <= DR_NADDR ? 1 : 0; | |
568 | } | |
569 | ||
570 | /* If the inferior has some break/watchpoint that triggered, set the | |
571 | address associated with that break/watchpoint and return non-zero. | |
572 | Otherwise, return zero. */ | |
573 | ||
574 | int | |
df7e5265 GB |
575 | x86_dr_stopped_data_address (struct x86_debug_reg_state *state, |
576 | CORE_ADDR *addr_p) | |
3a8ee006 GB |
577 | { |
578 | CORE_ADDR addr = 0; | |
579 | int i; | |
580 | int rc = 0; | |
581 | /* The current thread's DR_STATUS. We always need to read this to | |
582 | check whether some watchpoint caused the trap. */ | |
583 | unsigned status; | |
584 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a | |
585 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
586 | unnecessary extra syscall when no watchpoint triggered. */ | |
587 | int control_p = 0; | |
588 | unsigned control = 0; | |
589 | ||
590 | /* In non-stop/async, threads can be running while we change the | |
591 | global dr_mirror (and friends). Say, we set a watchpoint, and | |
592 | let threads resume. Now, say you delete the watchpoint, or | |
593 | add/remove watchpoints such that dr_mirror changes while threads | |
594 | are running. On targets that support non-stop, | |
595 | inserting/deleting watchpoints updates the global dr_mirror only. | |
596 | It does not update the real thread's debug registers; that's only | |
597 | done prior to resume. Instead, if threads are running when the | |
598 | mirror changes, a temporary and transparent stop on all threads | |
599 | is forced so they can get their copy of the debug registers | |
600 | updated on re-resume. Now, say, a thread hit a watchpoint before | |
601 | having been updated with the new dr_mirror contents, and we | |
602 | haven't yet handled the corresponding SIGTRAP. If we trusted | |
603 | dr_mirror below, we'd mistake the real trapped address (from the | |
604 | last time we had updated debug registers in the thread) with | |
605 | whatever was currently in dr_mirror. So to fix this, dr_mirror | |
606 | always represents intention, what we _want_ threads to have in | |
607 | debug registers. To get at the address and cause of the trap, we | |
608 | need to read the state the thread still has in its debug | |
609 | registers. | |
610 | ||
611 | In sum, always get the current debug register values the current | |
612 | thread has, instead of trusting the global mirror. If the thread | |
613 | was running when we last changed watchpoints, the mirror no | |
614 | longer represents what was set in this thread's debug | |
615 | registers. */ | |
df7e5265 | 616 | status = x86_dr_low_get_status (); |
3a8ee006 | 617 | |
97ea6506 | 618 | ALL_DEBUG_ADDRESS_REGISTERS (i) |
3a8ee006 | 619 | { |
df7e5265 | 620 | if (!X86_DR_WATCH_HIT (status, i)) |
3a8ee006 GB |
621 | continue; |
622 | ||
623 | if (!control_p) | |
624 | { | |
df7e5265 | 625 | control = x86_dr_low_get_control (); |
3a8ee006 GB |
626 | control_p = 1; |
627 | } | |
628 | ||
629 | /* This second condition makes sure DRi is set up for a data | |
630 | watchpoint, not a hardware breakpoint. The reason is that | |
631 | GDB doesn't call the target_stopped_data_address method | |
632 | except for data watchpoints. In other words, I'm being | |
633 | paranoiac. */ | |
df7e5265 | 634 | if (X86_DR_GET_RW_LEN (control, i) != 0) |
3a8ee006 | 635 | { |
df7e5265 | 636 | addr = x86_dr_low_get_addr (i); |
3a8ee006 | 637 | rc = 1; |
c5e92cca | 638 | if (show_debug_regs) |
df7e5265 | 639 | x86_show_dr (state, "watchpoint_hit", addr, -1, hw_write); |
3a8ee006 GB |
640 | } |
641 | } | |
642 | ||
c5e92cca | 643 | if (show_debug_regs && addr == 0) |
df7e5265 | 644 | x86_show_dr (state, "stopped_data_addr", 0, 0, hw_write); |
3a8ee006 GB |
645 | |
646 | if (rc) | |
647 | *addr_p = addr; | |
648 | return rc; | |
649 | } | |
650 | ||
651 | /* Return non-zero if the inferior has some watchpoint that triggered. | |
652 | Otherwise return zero. */ | |
653 | ||
654 | int | |
df7e5265 | 655 | x86_dr_stopped_by_watchpoint (struct x86_debug_reg_state *state) |
3a8ee006 GB |
656 | { |
657 | CORE_ADDR addr = 0; | |
df7e5265 | 658 | return x86_dr_stopped_data_address (state, &addr); |
3a8ee006 | 659 | } |