Commit | Line | Data |
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4d157a3d | 1 | /* |
1f85ef50 | 2 | * Helper cpuid.h file copied from gcc-6.0.0. Code in gdb should not |
df7e5265 | 3 | * include this directly, but pull in x86-cpuid.h and use that func. |
4d157a3d MF |
4 | */ |
5 | /* | |
61baf725 | 6 | * Copyright (C) 2007-2017 Free Software Foundation, Inc. |
a055a187 L |
7 | * |
8 | * This file is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 3, or (at your option) any | |
11 | * later version. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * Under Section 7 of GPL version 3, you are granted additional | |
19 | * permissions described in the GCC Runtime Library Exception, version | |
20 | * 3.1, as published by the Free Software Foundation. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License and | |
23 | * a copy of the GCC Runtime Library Exception along with this program; | |
24 | * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
25 | * <http://www.gnu.org/licenses/>. | |
26 | */ | |
83ecb59f | 27 | |
a055a187 L |
28 | /* %ecx */ |
29 | #define bit_SSE3 (1 << 0) | |
30 | #define bit_PCLMUL (1 << 1) | |
4d157a3d | 31 | #define bit_LZCNT (1 << 5) |
a055a187 L |
32 | #define bit_SSSE3 (1 << 9) |
33 | #define bit_FMA (1 << 12) | |
34 | #define bit_CMPXCHG16B (1 << 13) | |
35 | #define bit_SSE4_1 (1 << 19) | |
36 | #define bit_SSE4_2 (1 << 20) | |
37 | #define bit_MOVBE (1 << 22) | |
38 | #define bit_POPCNT (1 << 23) | |
39 | #define bit_AES (1 << 25) | |
40 | #define bit_XSAVE (1 << 26) | |
41 | #define bit_OSXSAVE (1 << 27) | |
42 | #define bit_AVX (1 << 28) | |
4d157a3d MF |
43 | #define bit_F16C (1 << 29) |
44 | #define bit_RDRND (1 << 30) | |
83ecb59f | 45 | |
a055a187 L |
46 | /* %edx */ |
47 | #define bit_CMPXCHG8B (1 << 8) | |
48 | #define bit_CMOV (1 << 15) | |
49 | #define bit_MMX (1 << 23) | |
50 | #define bit_FXSAVE (1 << 24) | |
51 | #define bit_SSE (1 << 25) | |
52 | #define bit_SSE2 (1 << 26) | |
83ecb59f | 53 | |
a055a187 L |
54 | /* Extended Features */ |
55 | /* %ecx */ | |
56 | #define bit_LAHF_LM (1 << 0) | |
57 | #define bit_ABM (1 << 5) | |
58 | #define bit_SSE4a (1 << 6) | |
4d157a3d | 59 | #define bit_PRFCHW (1 << 8) |
a055a187 L |
60 | #define bit_XOP (1 << 11) |
61 | #define bit_LWP (1 << 15) | |
62 | #define bit_FMA4 (1 << 16) | |
4d157a3d | 63 | #define bit_TBM (1 << 21) |
1f85ef50 | 64 | #define bit_MWAITX (1 << 29) |
a9762ec7 | 65 | |
a055a187 | 66 | /* %edx */ |
1f85ef50 MS |
67 | #define bit_AVX5124VNNIW (1 << 2) |
68 | #define bit_AVX5124FMAPS (1 << 3) | |
4d157a3d | 69 | #define bit_MMXEXT (1 << 22) |
a055a187 L |
70 | #define bit_LM (1 << 29) |
71 | #define bit_3DNOWP (1 << 30) | |
72 | #define bit_3DNOW (1 << 31) | |
a9762ec7 | 73 | |
1f85ef50 MS |
74 | /* %ebx. */ |
75 | #define bit_CLZERO (1 << 0) | |
76 | ||
4d157a3d | 77 | /* Extended Features (%eax == 7) */ |
1f85ef50 | 78 | /* %ebx */ |
4d157a3d MF |
79 | #define bit_FSGSBASE (1 << 0) |
80 | #define bit_BMI (1 << 3) | |
81 | #define bit_HLE (1 << 4) | |
82 | #define bit_AVX2 (1 << 5) | |
83 | #define bit_BMI2 (1 << 8) | |
84 | #define bit_RTM (1 << 11) | |
1f85ef50 | 85 | #define bit_MPX (1 << 14) |
60650f2e | 86 | #define bit_AVX512F (1 << 16) |
1f85ef50 | 87 | #define bit_AVX512DQ (1 << 17) |
4d157a3d MF |
88 | #define bit_RDSEED (1 << 18) |
89 | #define bit_ADX (1 << 19) | |
1f85ef50 MS |
90 | #define bit_AVX512IFMA (1 << 21) |
91 | #define bit_CLFLUSHOPT (1 << 23) | |
92 | #define bit_CLWB (1 << 24) | |
60650f2e WT |
93 | #define bit_AVX512PF (1 << 26) |
94 | #define bit_AVX512ER (1 << 27) | |
95 | #define bit_AVX512CD (1 << 28) | |
96 | #define bit_SHA (1 << 29) | |
1f85ef50 MS |
97 | #define bit_AVX512BW (1 << 30) |
98 | #define bit_AVX512VL (1 << 31) | |
99 | ||
100 | /* %ecx */ | |
101 | #define bit_PREFETCHWT1 (1 << 0) | |
102 | #define bit_AVX512VBMI (1 << 1) | |
103 | #define bit_PKU (1 << 3) | |
104 | #define bit_OSPKE (1 << 4) | |
105 | ||
106 | /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */ | |
107 | #define bit_BNDREGS (1 << 3) | |
108 | #define bit_BNDCSR (1 << 4) | |
4d157a3d MF |
109 | |
110 | /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */ | |
111 | #define bit_XSAVEOPT (1 << 0) | |
1f85ef50 MS |
112 | #define bit_XSAVEC (1 << 1) |
113 | #define bit_XSAVES (1 << 3) | |
4d157a3d MF |
114 | |
115 | /* Signatures for different CPU implementations as returned in uses | |
116 | of cpuid with level 0. */ | |
117 | #define signature_AMD_ebx 0x68747541 | |
118 | #define signature_AMD_ecx 0x444d4163 | |
119 | #define signature_AMD_edx 0x69746e65 | |
120 | ||
121 | #define signature_CENTAUR_ebx 0x746e6543 | |
122 | #define signature_CENTAUR_ecx 0x736c7561 | |
123 | #define signature_CENTAUR_edx 0x48727561 | |
124 | ||
125 | #define signature_CYRIX_ebx 0x69727943 | |
126 | #define signature_CYRIX_ecx 0x64616574 | |
127 | #define signature_CYRIX_edx 0x736e4978 | |
128 | ||
129 | #define signature_INTEL_ebx 0x756e6547 | |
130 | #define signature_INTEL_ecx 0x6c65746e | |
131 | #define signature_INTEL_edx 0x49656e69 | |
132 | ||
133 | #define signature_TM1_ebx 0x6e617254 | |
134 | #define signature_TM1_ecx 0x55504361 | |
135 | #define signature_TM1_edx 0x74656d73 | |
136 | ||
137 | #define signature_TM2_ebx 0x756e6547 | |
138 | #define signature_TM2_ecx 0x3638784d | |
139 | #define signature_TM2_edx 0x54656e69 | |
140 | ||
141 | #define signature_NSC_ebx 0x646f6547 | |
142 | #define signature_NSC_ecx 0x43534e20 | |
143 | #define signature_NSC_edx 0x79622065 | |
144 | ||
145 | #define signature_NEXGEN_ebx 0x4778654e | |
146 | #define signature_NEXGEN_ecx 0x6e657669 | |
147 | #define signature_NEXGEN_edx 0x72446e65 | |
148 | ||
149 | #define signature_RISE_ebx 0x65736952 | |
150 | #define signature_RISE_ecx 0x65736952 | |
151 | #define signature_RISE_edx 0x65736952 | |
152 | ||
153 | #define signature_SIS_ebx 0x20536953 | |
154 | #define signature_SIS_ecx 0x20536953 | |
155 | #define signature_SIS_edx 0x20536953 | |
156 | ||
157 | #define signature_UMC_ebx 0x20434d55 | |
158 | #define signature_UMC_ecx 0x20434d55 | |
159 | #define signature_UMC_edx 0x20434d55 | |
160 | ||
161 | #define signature_VIA_ebx 0x20414956 | |
162 | #define signature_VIA_ecx 0x20414956 | |
163 | #define signature_VIA_edx 0x20414956 | |
164 | ||
165 | #define signature_VORTEX_ebx 0x74726f56 | |
166 | #define signature_VORTEX_ecx 0x436f5320 | |
167 | #define signature_VORTEX_edx 0x36387865 | |
83ecb59f | 168 | |
a055a187 L |
169 | #define __cpuid(level, a, b, c, d) \ |
170 | __asm__ ("cpuid\n\t" \ | |
171 | : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ | |
172 | : "0" (level)) | |
83ecb59f | 173 | |
a055a187 L |
174 | #define __cpuid_count(level, count, a, b, c, d) \ |
175 | __asm__ ("cpuid\n\t" \ | |
176 | : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ | |
177 | : "0" (level), "2" (count)) | |
1f85ef50 | 178 | |
83ecb59f | 179 | |
a055a187 L |
180 | /* Return highest supported input value for cpuid instruction. ext can |
181 | be either 0x0 or 0x8000000 to return highest supported value for | |
182 | basic or extended cpuid information. Function returns 0 if cpuid | |
183 | is not supported or whatever cpuid returns in eax register. If sig | |
184 | pointer is non-null, then first four bytes of the signature | |
185 | (as found in ebx register) are returned in location pointed by sig. */ | |
186 | ||
187 | static __inline unsigned int | |
188 | __get_cpuid_max (unsigned int __ext, unsigned int *__sig) | |
83ecb59f | 189 | { |
a055a187 | 190 | unsigned int __eax, __ebx, __ecx, __edx; |
83ecb59f | 191 | |
60650f2e | 192 | #ifndef __x86_64__ |
83ecb59f | 193 | /* See if we can use cpuid. On AMD64 we always can. */ |
4d157a3d | 194 | #if __GNUC__ >= 3 |
a055a187 L |
195 | __asm__ ("pushf{l|d}\n\t" |
196 | "pushf{l|d}\n\t" | |
197 | "pop{l}\t%0\n\t" | |
198 | "mov{l}\t{%0, %1|%1, %0}\n\t" | |
199 | "xor{l}\t{%2, %0|%0, %2}\n\t" | |
200 | "push{l}\t%0\n\t" | |
201 | "popf{l|d}\n\t" | |
202 | "pushf{l|d}\n\t" | |
203 | "pop{l}\t%0\n\t" | |
204 | "popf{l|d}\n\t" | |
205 | : "=&r" (__eax), "=&r" (__ebx) | |
206 | : "i" (0x00200000)); | |
207 | #else | |
208 | /* Host GCCs older than 3.0 weren't supporting Intel asm syntax | |
209 | nor alternatives in i386 code. */ | |
210 | __asm__ ("pushfl\n\t" | |
211 | "pushfl\n\t" | |
212 | "popl\t%0\n\t" | |
213 | "movl\t%0, %1\n\t" | |
214 | "xorl\t%2, %0\n\t" | |
215 | "pushl\t%0\n\t" | |
216 | "popfl\n\t" | |
217 | "pushfl\n\t" | |
218 | "popl\t%0\n\t" | |
219 | "popfl\n\t" | |
220 | : "=&r" (__eax), "=&r" (__ebx) | |
83ecb59f | 221 | : "i" (0x00200000)); |
83ecb59f JB |
222 | #endif |
223 | ||
a055a187 L |
224 | if (!((__eax ^ __ebx) & 0x00200000)) |
225 | return 0; | |
83ecb59f | 226 | #endif |
a055a187 L |
227 | |
228 | /* Host supports cpuid. Return highest supported cpuid input value. */ | |
229 | __cpuid (__ext, __eax, __ebx, __ecx, __edx); | |
230 | ||
231 | if (__sig) | |
232 | *__sig = __ebx; | |
233 | ||
234 | return __eax; | |
235 | } | |
236 | ||
1f85ef50 | 237 | /* Return cpuid data for requested cpuid leaf, as found in returned |
a055a187 L |
238 | eax, ebx, ecx and edx registers. The function checks if cpuid is |
239 | supported and returns 1 for valid cpuid information or 0 for | |
1f85ef50 | 240 | unsupported cpuid leaf. All pointers are required to be non-null. */ |
a055a187 L |
241 | |
242 | static __inline int | |
1f85ef50 | 243 | __get_cpuid (unsigned int __leaf, |
a055a187 L |
244 | unsigned int *__eax, unsigned int *__ebx, |
245 | unsigned int *__ecx, unsigned int *__edx) | |
246 | { | |
1f85ef50 MS |
247 | unsigned int __ext = __leaf & 0x80000000; |
248 | ||
249 | if (__get_cpuid_max (__ext, 0) < __leaf) | |
250 | return 0; | |
251 | ||
252 | __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx); | |
253 | return 1; | |
254 | } | |
255 | ||
256 | /* Same as above, but sub-leaf can be specified. */ | |
257 | ||
258 | static __inline int | |
259 | __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf, | |
260 | unsigned int *__eax, unsigned int *__ebx, | |
261 | unsigned int *__ecx, unsigned int *__edx) | |
262 | { | |
263 | unsigned int __ext = __leaf & 0x80000000; | |
a055a187 | 264 | |
1f85ef50 | 265 | if (__get_cpuid_max (__ext, 0) < __leaf) |
a055a187 L |
266 | return 0; |
267 | ||
1f85ef50 | 268 | __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx); |
a055a187 L |
269 | return 1; |
270 | } |