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a1217d97 | 1 | /* Target-machine dependent code for Nios II, for GDB. |
ecd75fc8 | 2 | Copyright (C) 2012-2014 Free Software Foundation, Inc. |
a1217d97 SL |
3 | Contributed by Peter Brookes (pbrookes@altera.com) |
4 | and Andrew Draper (adraper@altera.com). | |
5 | Contributed by Mentor Graphics, Inc. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "frame-unwind.h" | |
25 | #include "frame-base.h" | |
26 | #include "trad-frame.h" | |
27 | #include "dwarf2-frame.h" | |
28 | #include "symtab.h" | |
29 | #include "inferior.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcore.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "osabi.h" | |
34 | #include "target.h" | |
35 | #include "dis-asm.h" | |
36 | #include "regcache.h" | |
37 | #include "value.h" | |
38 | #include "symfile.h" | |
39 | #include "arch-utils.h" | |
40 | #include "floatformat.h" | |
a1217d97 SL |
41 | #include "infcall.h" |
42 | #include "regset.h" | |
43 | #include "target-descriptions.h" | |
44 | ||
45 | /* To get entry_point_address. */ | |
46 | #include "objfiles.h" | |
47 | ||
48 | /* Nios II ISA specific encodings and macros. */ | |
49 | #include "opcode/nios2.h" | |
50 | ||
51 | /* Nios II specific header. */ | |
52 | #include "nios2-tdep.h" | |
53 | ||
54 | #include "features/nios2.c" | |
55 | ||
56 | /* Control debugging information emitted in this file. */ | |
57 | ||
58 | static int nios2_debug = 0; | |
59 | ||
60 | /* The following structures are used in the cache for prologue | |
61 | analysis; see the reg_value and reg_saved tables in | |
62 | struct nios2_unwind_cache, respectively. */ | |
63 | ||
64 | /* struct reg_value is used to record that a register has the same value | |
65 | as reg at the given offset from the start of a function. */ | |
66 | ||
67 | struct reg_value | |
68 | { | |
69 | int reg; | |
70 | unsigned int offset; | |
71 | }; | |
72 | ||
73 | /* struct reg_saved is used to record that a register value has been saved at | |
74 | basereg + addr, for basereg >= 0. If basereg < 0, that indicates | |
75 | that the register is not known to have been saved. Note that when | |
76 | basereg == NIOS2_Z_REGNUM (that is, r0, which holds value 0), | |
77 | addr is an absolute address. */ | |
78 | ||
79 | struct reg_saved | |
80 | { | |
81 | int basereg; | |
82 | CORE_ADDR addr; | |
83 | }; | |
84 | ||
85 | struct nios2_unwind_cache | |
86 | { | |
87 | /* The frame's base, optionally used by the high-level debug info. */ | |
88 | CORE_ADDR base; | |
89 | ||
90 | /* The previous frame's inner most stack address. Used as this | |
91 | frame ID's stack_addr. */ | |
92 | CORE_ADDR cfa; | |
93 | ||
94 | /* The address of the first instruction in this function. */ | |
95 | CORE_ADDR pc; | |
96 | ||
97 | /* Which register holds the return address for the frame. */ | |
98 | int return_regnum; | |
99 | ||
100 | /* Table indicating what changes have been made to each register. */ | |
101 | struct reg_value reg_value[NIOS2_NUM_REGS]; | |
102 | ||
103 | /* Table indicating where each register has been saved. */ | |
104 | struct reg_saved reg_saved[NIOS2_NUM_REGS]; | |
105 | }; | |
106 | ||
107 | ||
108 | /* This array is a mapping from Dwarf-2 register numbering to GDB's. */ | |
109 | ||
110 | static int nios2_dwarf2gdb_regno_map[] = | |
111 | { | |
112 | 0, 1, 2, 3, | |
113 | 4, 5, 6, 7, | |
114 | 8, 9, 10, 11, | |
115 | 12, 13, 14, 15, | |
116 | 16, 17, 18, 19, | |
117 | 20, 21, 22, 23, | |
118 | 24, 25, | |
119 | NIOS2_GP_REGNUM, /* 26 */ | |
120 | NIOS2_SP_REGNUM, /* 27 */ | |
121 | NIOS2_FP_REGNUM, /* 28 */ | |
122 | NIOS2_EA_REGNUM, /* 29 */ | |
123 | NIOS2_BA_REGNUM, /* 30 */ | |
124 | NIOS2_RA_REGNUM, /* 31 */ | |
125 | NIOS2_PC_REGNUM, /* 32 */ | |
126 | NIOS2_STATUS_REGNUM, /* 33 */ | |
127 | NIOS2_ESTATUS_REGNUM, /* 34 */ | |
128 | NIOS2_BSTATUS_REGNUM, /* 35 */ | |
129 | NIOS2_IENABLE_REGNUM, /* 36 */ | |
130 | NIOS2_IPENDING_REGNUM, /* 37 */ | |
131 | NIOS2_CPUID_REGNUM, /* 38 */ | |
132 | 39, /* CTL6 */ /* 39 */ | |
133 | NIOS2_EXCEPTION_REGNUM, /* 40 */ | |
134 | NIOS2_PTEADDR_REGNUM, /* 41 */ | |
135 | NIOS2_TLBACC_REGNUM, /* 42 */ | |
136 | NIOS2_TLBMISC_REGNUM, /* 43 */ | |
137 | NIOS2_ECCINJ_REGNUM, /* 44 */ | |
138 | NIOS2_BADADDR_REGNUM, /* 45 */ | |
139 | NIOS2_CONFIG_REGNUM, /* 46 */ | |
140 | NIOS2_MPUBASE_REGNUM, /* 47 */ | |
141 | NIOS2_MPUACC_REGNUM /* 48 */ | |
142 | }; | |
143 | ||
144 | ||
145 | /* Implement the dwarf2_reg_to_regnum gdbarch method. */ | |
146 | ||
147 | static int | |
148 | nios2_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg) | |
149 | { | |
150 | if (dw_reg < 0 || dw_reg > NIOS2_NUM_REGS) | |
151 | { | |
1e52bda6 | 152 | warning (_("Dwarf-2 uses unmapped register #%d"), dw_reg); |
a1217d97 SL |
153 | return dw_reg; |
154 | } | |
155 | ||
156 | return nios2_dwarf2gdb_regno_map[dw_reg]; | |
157 | } | |
158 | ||
159 | /* Canonical names for the 49 registers. */ | |
160 | ||
161 | static const char *const nios2_reg_names[NIOS2_NUM_REGS] = | |
162 | { | |
163 | "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", | |
164 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
165 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
0b76b0ce | 166 | "et", "bt", "gp", "sp", "fp", "ea", "sstatus", "ra", |
a1217d97 SL |
167 | "pc", |
168 | "status", "estatus", "bstatus", "ienable", | |
169 | "ipending", "cpuid", "ctl6", "exception", | |
170 | "pteaddr", "tlbacc", "tlbmisc", "eccinj", | |
171 | "badaddr", "config", "mpubase", "mpuacc" | |
172 | }; | |
173 | ||
174 | /* Implement the register_name gdbarch method. */ | |
175 | ||
176 | static const char * | |
177 | nios2_register_name (struct gdbarch *gdbarch, int regno) | |
178 | { | |
179 | /* Use mnemonic aliases for GPRs. */ | |
180 | if (regno >= 0 && regno < NIOS2_NUM_REGS) | |
181 | return nios2_reg_names[regno]; | |
182 | else | |
183 | return tdesc_register_name (gdbarch, regno); | |
184 | } | |
185 | ||
186 | /* Implement the register_type gdbarch method. */ | |
187 | ||
188 | static struct type * | |
189 | nios2_register_type (struct gdbarch *gdbarch, int regno) | |
190 | { | |
191 | /* If the XML description has register information, use that to | |
192 | determine the register type. */ | |
193 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
194 | return tdesc_register_type (gdbarch, regno); | |
195 | ||
196 | if (regno == NIOS2_PC_REGNUM) | |
197 | return builtin_type (gdbarch)->builtin_func_ptr; | |
198 | else if (regno == NIOS2_SP_REGNUM) | |
199 | return builtin_type (gdbarch)->builtin_data_ptr; | |
200 | else | |
201 | return builtin_type (gdbarch)->builtin_uint32; | |
202 | } | |
203 | ||
204 | /* Given a return value in REGCACHE with a type VALTYPE, | |
205 | extract and copy its value into VALBUF. */ | |
206 | ||
207 | static void | |
208 | nios2_extract_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
209 | struct regcache *regcache, gdb_byte *valbuf) | |
210 | { | |
211 | int len = TYPE_LENGTH (valtype); | |
212 | ||
213 | /* Return values of up to 8 bytes are returned in $r2 $r3. */ | |
214 | if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) | |
215 | regcache_cooked_read (regcache, NIOS2_R2_REGNUM, valbuf); | |
216 | else | |
217 | { | |
218 | gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) | |
219 | + register_size (gdbarch, NIOS2_R3_REGNUM))); | |
220 | regcache_cooked_read (regcache, NIOS2_R2_REGNUM, valbuf); | |
221 | regcache_cooked_read (regcache, NIOS2_R3_REGNUM, valbuf + 4); | |
222 | } | |
223 | } | |
224 | ||
225 | /* Write into appropriate registers a function return value | |
226 | of type TYPE, given in virtual format. */ | |
227 | ||
228 | static void | |
229 | nios2_store_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
230 | struct regcache *regcache, const gdb_byte *valbuf) | |
231 | { | |
232 | int len = TYPE_LENGTH (valtype); | |
233 | ||
234 | /* Return values of up to 8 bytes are returned in $r2 $r3. */ | |
235 | if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) | |
236 | regcache_cooked_write (regcache, NIOS2_R2_REGNUM, valbuf); | |
237 | else | |
238 | { | |
239 | gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) | |
240 | + register_size (gdbarch, NIOS2_R3_REGNUM))); | |
241 | regcache_cooked_write (regcache, NIOS2_R2_REGNUM, valbuf); | |
242 | regcache_cooked_write (regcache, NIOS2_R3_REGNUM, valbuf + 4); | |
243 | } | |
244 | } | |
245 | ||
246 | ||
247 | /* Set up the default values of the registers. */ | |
248 | ||
249 | static void | |
250 | nios2_setup_default (struct nios2_unwind_cache *cache) | |
251 | { | |
252 | int i; | |
253 | ||
254 | for (i = 0; i < NIOS2_NUM_REGS; i++) | |
255 | { | |
256 | /* All registers start off holding their previous values. */ | |
257 | cache->reg_value[i].reg = i; | |
258 | cache->reg_value[i].offset = 0; | |
259 | ||
260 | /* All registers start off not saved. */ | |
261 | cache->reg_saved[i].basereg = -1; | |
262 | cache->reg_saved[i].addr = 0; | |
263 | } | |
264 | } | |
265 | ||
266 | /* Initialize the unwind cache. */ | |
267 | ||
268 | static void | |
269 | nios2_init_cache (struct nios2_unwind_cache *cache, CORE_ADDR pc) | |
270 | { | |
271 | cache->base = 0; | |
272 | cache->cfa = 0; | |
273 | cache->pc = pc; | |
274 | cache->return_regnum = NIOS2_RA_REGNUM; | |
275 | nios2_setup_default (cache); | |
276 | } | |
277 | ||
278 | /* Helper function to identify when we're in a function epilogue; | |
279 | that is, the part of the function from the point at which the | |
280 | stack adjustment is made, to the return or sibcall. On Nios II, | |
281 | we want to check that the CURRENT_PC is a return-type instruction | |
282 | and that the previous instruction is a stack adjustment. | |
283 | START_PC is the beginning of the function in question. */ | |
284 | ||
285 | static int | |
286 | nios2_in_epilogue_p (struct gdbarch *gdbarch, | |
287 | CORE_ADDR current_pc, | |
288 | CORE_ADDR start_pc) | |
289 | { | |
290 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
291 | ||
292 | /* There has to be a previous instruction in the function. */ | |
293 | if (current_pc > start_pc) | |
294 | { | |
295 | ||
296 | /* Check whether the previous instruction was a stack | |
297 | adjustment. */ | |
298 | unsigned int insn | |
299 | = read_memory_unsigned_integer (current_pc - NIOS2_OPCODE_SIZE, | |
300 | NIOS2_OPCODE_SIZE, byte_order); | |
301 | ||
302 | if ((insn & 0xffc0003c) == 0xdec00004 /* ADDI sp, sp, */ | |
303 | || (insn & 0xffc1ffff) == 0xdec1883a /* ADD sp, sp, */ | |
304 | || (insn & 0xffc0003f) == 0xdec00017) /* LDW sp, constant(sp) */ | |
305 | { | |
306 | /* Then check if it's followed by a return or a tail | |
307 | call. */ | |
308 | insn = read_memory_unsigned_integer (current_pc, NIOS2_OPCODE_SIZE, | |
309 | byte_order); | |
310 | ||
311 | if (insn == 0xf800283a /* RET */ | |
312 | || insn == 0xe800083a /* ERET */ | |
313 | || (insn & 0x07ffffff) == 0x0000683a /* JMP */ | |
314 | || (insn & 0xffc0003f) == 6) /* BR */ | |
315 | return 1; | |
316 | } | |
317 | } | |
318 | return 0; | |
319 | } | |
320 | ||
321 | /* Implement the in_function_epilogue_p gdbarch method. */ | |
322 | ||
323 | static int | |
324 | nios2_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
325 | { | |
326 | CORE_ADDR func_addr; | |
327 | ||
328 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
329 | return nios2_in_epilogue_p (gdbarch, pc, func_addr); | |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | /* Define some instruction patterns supporting wildcard bits via a | |
335 | mask. */ | |
336 | ||
337 | typedef struct | |
338 | { | |
339 | unsigned int insn; | |
340 | unsigned int mask; | |
341 | } wild_insn; | |
342 | ||
343 | static const wild_insn profiler_insn[] = | |
344 | { | |
345 | { 0x0010e03a, 0x00000000 }, /* nextpc r8 */ | |
346 | { 0xf813883a, 0x00000000 }, /* mov r9,ra */ | |
347 | { 0x02800034, 0x003fffc0 }, /* movhi r10,257 */ | |
348 | { 0x52800004, 0x003fffc0 }, /* addi r10,r10,-31992 */ | |
349 | { 0x00000000, 0xffffffc0 }, /* call <mcount> */ | |
350 | { 0x483f883a, 0x00000000 } /* mov ra,r9 */ | |
351 | }; | |
352 | ||
353 | static const wild_insn irqentry_insn[] = | |
354 | { | |
355 | { 0x0031307a, 0x00000000 }, /* rdctl et,estatus */ | |
356 | { 0xc600004c, 0x00000000 }, /* andi et,et,1 */ | |
357 | { 0xc0000026, 0x003fffc0 }, /* beq et,zero, <software_exception> */ | |
358 | { 0x0031313a, 0x00000000 }, /* rdctl et,ipending */ | |
359 | { 0xc0000026, 0x003fffc0 } /* beq et,zero, <software_exception> */ | |
360 | }; | |
361 | ||
362 | ||
363 | /* Attempt to match SEQUENCE, which is COUNT insns long, at START_PC. */ | |
364 | ||
365 | static int | |
366 | nios2_match_sequence (struct gdbarch *gdbarch, CORE_ADDR start_pc, | |
367 | const wild_insn *sequence, int count) | |
368 | { | |
369 | CORE_ADDR pc = start_pc; | |
370 | int i; | |
371 | unsigned int insn; | |
372 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
373 | ||
374 | for (i = 0 ; i < count ; i++) | |
375 | { | |
376 | insn = read_memory_unsigned_integer (pc, NIOS2_OPCODE_SIZE, byte_order); | |
377 | if ((insn & ~sequence[i].mask) != sequence[i].insn) | |
378 | return 0; | |
379 | ||
380 | pc += NIOS2_OPCODE_SIZE; | |
381 | } | |
382 | ||
383 | return 1; | |
384 | } | |
385 | ||
386 | /* Do prologue analysis, returning the PC of the first instruction | |
387 | after the function prologue. Assumes CACHE has already been | |
388 | initialized. THIS_FRAME can be null, in which case we are only | |
389 | interested in skipping the prologue. Otherwise CACHE is filled in | |
390 | from the frame information. | |
391 | ||
392 | The prologue will consist of the following parts: | |
393 | 1) Optional profiling instrumentation. The old version uses six | |
394 | instructions. We step over this if there is an exact match. | |
395 | nextpc r8 | |
396 | mov r9, ra | |
397 | movhi r10, %hiadj(.LP2) | |
398 | addi r10, r10, %lo(.LP2) | |
399 | call mcount | |
400 | mov ra, r9 | |
401 | The new version uses two or three instructions (the last of | |
402 | these might get merged in with the STW which saves RA to the | |
403 | stack). We interpret these. | |
404 | mov r8, ra | |
405 | call mcount | |
406 | mov ra, r8 | |
407 | ||
408 | 2) Optional interrupt entry decision. Again, we step over | |
409 | this if there is an exact match. | |
410 | rdctl et,estatus | |
411 | andi et,et,1 | |
412 | beq et,zero, <software_exception> | |
413 | rdctl et,ipending | |
414 | beq et,zero, <software_exception> | |
415 | ||
416 | 3) A stack adjustment or stack which, which will be one of: | |
417 | addi sp, sp, -constant | |
418 | or: | |
419 | movi r8, constant | |
420 | sub sp, sp, r8 | |
421 | or | |
422 | movhi r8, constant | |
423 | addi r8, r8, constant | |
424 | sub sp, sp, r8 | |
425 | or | |
426 | movhi rx, %hiadj(newstack) | |
427 | addhi rx, rx, %lo(newstack) | |
428 | stw sp, constant(rx) | |
429 | mov sp, rx | |
430 | ||
431 | 4) An optional stack check, which can take either of these forms: | |
432 | bgeu sp, rx, +8 | |
433 | break 3 | |
434 | or | |
435 | bltu sp, rx, .Lstack_overflow | |
436 | ... | |
437 | .Lstack_overflow: | |
438 | break 3 | |
439 | ||
440 | 5) Saving any registers which need to be saved. These will | |
441 | normally just be stored onto the stack: | |
442 | stw rx, constant(sp) | |
443 | but in the large frame case will use r8 as an offset back | |
444 | to the cfa: | |
445 | add r8, r8, sp | |
446 | stw rx, -constant(r8) | |
447 | ||
448 | Saving control registers looks slightly different: | |
449 | rdctl rx, ctlN | |
450 | stw rx, constant(sp) | |
451 | ||
452 | 6) An optional FP setup, either if the user has requested a | |
453 | frame pointer or if the function calls alloca. | |
454 | This is always: | |
455 | mov fp, sp | |
456 | ||
457 | The prologue instructions may be interleaved, and the register | |
458 | saves and FP setup can occur in either order. | |
459 | ||
460 | To cope with all this variability we decode all the instructions | |
461 | from the start of the prologue until we hit a branch, call or | |
462 | return. For each of the instructions mentioned in 3, 4 and 5 we | |
463 | handle the limited cases of stores to the stack and operations | |
464 | on constant values. */ | |
465 | ||
466 | static CORE_ADDR | |
467 | nios2_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc, | |
468 | const CORE_ADDR current_pc, | |
469 | struct nios2_unwind_cache *cache, | |
470 | struct frame_info *this_frame) | |
471 | { | |
472 | /* Maximum lines of prologue to check. | |
473 | Note that this number should not be too large, else we can | |
474 | potentially end up iterating through unmapped memory. */ | |
475 | CORE_ADDR limit_pc = start_pc + 200; | |
476 | int regno; | |
477 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
478 | ||
479 | /* Does the frame set up the FP register? */ | |
480 | int base_reg = 0; | |
481 | ||
482 | struct reg_value *value = cache->reg_value; | |
483 | struct reg_value temp_value[NIOS2_NUM_REGS]; | |
484 | ||
485 | int i; | |
486 | ||
487 | /* Save the starting PC so we can correct the pc after running | |
488 | through the prolog, using symbol info. */ | |
489 | CORE_ADDR pc = start_pc; | |
490 | ||
491 | /* Is this an exception handler? */ | |
492 | int exception_handler = 0; | |
493 | ||
494 | /* What was the original value of SP (or fake original value for | |
495 | functions which switch stacks? */ | |
496 | CORE_ADDR frame_high; | |
497 | ||
498 | /* Is this the end of the prologue? */ | |
499 | int within_prologue = 1; | |
500 | ||
501 | CORE_ADDR prologue_end; | |
502 | ||
503 | /* Is this the innermost function? */ | |
504 | int innermost = (this_frame ? (frame_relative_level (this_frame) == 0) : 1); | |
505 | ||
506 | if (nios2_debug) | |
507 | fprintf_unfiltered (gdb_stdlog, | |
508 | "{ nios2_analyze_prologue start=%s, current=%s ", | |
509 | paddress (gdbarch, start_pc), | |
510 | paddress (gdbarch, current_pc)); | |
511 | ||
512 | /* Set up the default values of the registers. */ | |
513 | nios2_setup_default (cache); | |
514 | ||
515 | /* If the first few instructions are the profile entry, then skip | |
516 | over them. Newer versions of the compiler use more efficient | |
517 | profiling code. */ | |
518 | if (nios2_match_sequence (gdbarch, pc, profiler_insn, | |
519 | ARRAY_SIZE (profiler_insn))) | |
520 | pc += ARRAY_SIZE (profiler_insn) * NIOS2_OPCODE_SIZE; | |
521 | ||
522 | /* If the first few instructions are an interrupt entry, then skip | |
523 | over them too. */ | |
524 | if (nios2_match_sequence (gdbarch, pc, irqentry_insn, | |
525 | ARRAY_SIZE (irqentry_insn))) | |
526 | { | |
527 | pc += ARRAY_SIZE (irqentry_insn) * NIOS2_OPCODE_SIZE; | |
528 | exception_handler = 1; | |
529 | } | |
530 | ||
531 | prologue_end = start_pc; | |
532 | ||
533 | /* Find the prologue instructions. */ | |
534 | while (pc < limit_pc && within_prologue) | |
535 | { | |
536 | /* Present instruction. */ | |
537 | uint32_t insn; | |
538 | ||
539 | int prologue_insn = 0; | |
540 | ||
541 | if (pc == current_pc) | |
542 | { | |
543 | /* When we reach the current PC we must save the current | |
544 | register state (for the backtrace) but keep analysing | |
545 | because there might be more to find out (eg. is this an | |
546 | exception handler). */ | |
547 | memcpy (temp_value, value, sizeof (temp_value)); | |
548 | value = temp_value; | |
549 | if (nios2_debug) | |
550 | fprintf_unfiltered (gdb_stdlog, "*"); | |
551 | } | |
552 | ||
553 | insn = read_memory_unsigned_integer (pc, NIOS2_OPCODE_SIZE, byte_order); | |
554 | pc += NIOS2_OPCODE_SIZE; | |
555 | ||
556 | if (nios2_debug) | |
557 | fprintf_unfiltered (gdb_stdlog, "[%08X]", insn); | |
558 | ||
559 | /* The following instructions can appear in the prologue. */ | |
560 | ||
561 | if ((insn & 0x0001ffff) == 0x0001883a) | |
562 | { | |
563 | /* ADD rc, ra, rb (also used for MOV) */ | |
564 | ||
565 | int ra = GET_IW_A (insn); | |
566 | int rb = GET_IW_B (insn); | |
567 | int rc = GET_IW_C (insn); | |
568 | ||
569 | if (rc == NIOS2_SP_REGNUM | |
570 | && rb == 0 | |
571 | && value[ra].reg == cache->reg_saved[NIOS2_SP_REGNUM].basereg) | |
572 | { | |
573 | /* If the previous value of SP is available somewhere | |
574 | near the new stack pointer value then this is a | |
575 | stack switch. */ | |
576 | ||
577 | /* If any registers were saved on the stack before then | |
578 | we can't backtrace into them now. */ | |
579 | for (i = 0 ; i < NIOS2_NUM_REGS ; i++) | |
580 | { | |
581 | if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) | |
582 | cache->reg_saved[i].basereg = -1; | |
583 | if (value[i].reg == NIOS2_SP_REGNUM) | |
584 | value[i].reg = -1; | |
585 | } | |
586 | ||
587 | /* Create a fake "high water mark" 4 bytes above where SP | |
588 | was stored and fake up the registers to be consistent | |
589 | with that. */ | |
590 | value[NIOS2_SP_REGNUM].reg = NIOS2_SP_REGNUM; | |
591 | value[NIOS2_SP_REGNUM].offset | |
592 | = (value[ra].offset | |
593 | - cache->reg_saved[NIOS2_SP_REGNUM].addr | |
594 | - 4); | |
595 | cache->reg_saved[NIOS2_SP_REGNUM].basereg = NIOS2_SP_REGNUM; | |
596 | cache->reg_saved[NIOS2_SP_REGNUM].addr = -4; | |
597 | } | |
598 | ||
599 | else if (rc != 0) | |
600 | { | |
601 | if (value[rb].reg == 0) | |
602 | value[rc].reg = value[ra].reg; | |
603 | else if (value[ra].reg == 0) | |
604 | value[rc].reg = value[rb].reg; | |
605 | else | |
606 | value[rc].reg = -1; | |
607 | value[rc].offset = value[ra].offset + value[rb].offset; | |
608 | } | |
609 | prologue_insn = 1; | |
610 | } | |
611 | ||
612 | else if ((insn & 0x0001ffff) == 0x0001983a) | |
613 | { | |
614 | /* SUB rc, ra, rb */ | |
615 | ||
616 | int ra = GET_IW_A (insn); | |
617 | int rb = GET_IW_B (insn); | |
618 | int rc = GET_IW_C (insn); | |
619 | ||
620 | if (rc != 0) | |
621 | { | |
622 | if (value[rb].reg == 0) | |
623 | value[rc].reg = value[ra].reg; | |
624 | else | |
625 | value[rc].reg = -1; | |
626 | value[rc].offset = value[ra].offset - value[rb].offset; | |
627 | } | |
628 | } | |
629 | ||
630 | else if ((insn & 0x0000003f) == 0x00000004) | |
631 | { | |
632 | /* ADDI rb, ra, immed (also used for MOVI) */ | |
633 | short immed = GET_IW_IMM16 (insn); | |
634 | int ra = GET_IW_A (insn); | |
635 | int rb = GET_IW_B (insn); | |
636 | ||
637 | /* The first stack adjustment is part of the prologue. | |
638 | Any subsequent stack adjustments are either down to | |
639 | alloca or the epilogue so stop analysing when we hit | |
640 | them. */ | |
641 | if (rb == NIOS2_SP_REGNUM | |
642 | && (value[rb].offset != 0 || value[ra].reg != NIOS2_SP_REGNUM)) | |
643 | break; | |
644 | ||
645 | if (rb != 0) | |
646 | { | |
647 | value[rb].reg = value[ra].reg; | |
648 | value[rb].offset = value[ra].offset + immed; | |
649 | } | |
650 | ||
651 | prologue_insn = 1; | |
652 | } | |
653 | ||
654 | else if ((insn & 0x0000003f) == 0x00000034) | |
655 | { | |
656 | /* ORHI rb, ra, immed (also used for MOVHI) */ | |
657 | unsigned int immed = GET_IW_IMM16 (insn); | |
658 | int ra = GET_IW_A (insn); | |
659 | int rb = GET_IW_B (insn); | |
660 | ||
661 | if (rb != 0) | |
662 | { | |
663 | value[rb].reg = (value[ra].reg == 0) ? 0 : -1; | |
664 | value[rb].offset = value[ra].offset | (immed << 16); | |
665 | } | |
666 | } | |
667 | ||
668 | else if ((insn & IW_OP_MASK) == OP_STW | |
669 | || (insn & IW_OP_MASK) == OP_STWIO) | |
670 | { | |
671 | /* STW rb, immediate(ra) */ | |
672 | ||
673 | short immed16 = GET_IW_IMM16 (insn); | |
674 | int ra = GET_IW_A (insn); | |
675 | int rb = GET_IW_B (insn); | |
676 | ||
677 | /* Are we storing the original value of a register? | |
678 | For exception handlers the value of EA-4 (return | |
679 | address from interrupts etc) is sometimes stored. */ | |
680 | int orig = value[rb].reg; | |
681 | if (orig > 0 | |
682 | && (value[rb].offset == 0 | |
683 | || (orig == NIOS2_EA_REGNUM && value[rb].offset == -4))) | |
684 | { | |
685 | /* We are most interested in stores to the stack, but | |
686 | also take note of stores to other places as they | |
687 | might be useful later. */ | |
688 | if ((value[ra].reg == NIOS2_SP_REGNUM | |
689 | && cache->reg_saved[orig].basereg != NIOS2_SP_REGNUM) | |
690 | || cache->reg_saved[orig].basereg == -1) | |
691 | { | |
692 | if (pc < current_pc) | |
693 | { | |
694 | /* Save off callee saved registers. */ | |
695 | cache->reg_saved[orig].basereg = value[ra].reg; | |
696 | cache->reg_saved[orig].addr | |
697 | = value[ra].offset + GET_IW_IMM16 (insn); | |
698 | } | |
699 | ||
700 | prologue_insn = 1; | |
701 | ||
702 | if (orig == NIOS2_EA_REGNUM || orig == NIOS2_ESTATUS_REGNUM) | |
703 | exception_handler = 1; | |
704 | } | |
705 | } | |
706 | else | |
707 | /* Non-stack memory writes are not part of the | |
708 | prologue. */ | |
709 | within_prologue = 0; | |
710 | } | |
711 | ||
712 | else if ((insn & 0xffc1f83f) == 0x0001303a) | |
713 | { | |
714 | /* RDCTL rC, ctlN */ | |
715 | int rc = GET_IW_C (insn); | |
716 | int n = GET_IW_CONTROL_REGNUM (insn); | |
717 | ||
718 | if (rc != 0) | |
719 | { | |
720 | value[rc].reg = NIOS2_STATUS_REGNUM + n; | |
721 | value[rc].offset = 0; | |
722 | } | |
723 | ||
724 | prologue_insn = 1; | |
725 | } | |
726 | ||
727 | else if ((insn & 0x0000003f) == 0 | |
728 | && value[8].reg == NIOS2_RA_REGNUM | |
729 | && value[8].offset == 0 | |
730 | && value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM | |
731 | && value[NIOS2_SP_REGNUM].offset == 0) | |
732 | { | |
733 | /* A CALL instruction. This is treated as a call to mcount | |
734 | if ra has been stored into r8 beforehand and if it's | |
735 | before the stack adjust. | |
736 | Note mcount corrupts r2-r3, r9-r15 & ra. */ | |
737 | for (i = 2 ; i <= 3 ; i++) | |
738 | value[i].reg = -1; | |
739 | for (i = 9 ; i <= 15 ; i++) | |
740 | value[i].reg = -1; | |
741 | value[NIOS2_RA_REGNUM].reg = -1; | |
742 | ||
743 | prologue_insn = 1; | |
744 | } | |
745 | ||
746 | else if ((insn & 0xf83fffff) == 0xd800012e) | |
747 | { | |
748 | /* BGEU sp, rx, +8 | |
749 | BREAK 3 | |
750 | This instruction sequence is used in stack checking; | |
751 | we can ignore it. */ | |
752 | unsigned int next_insn | |
753 | = read_memory_unsigned_integer (pc, NIOS2_OPCODE_SIZE, byte_order); | |
754 | ||
755 | if (next_insn != 0x003da0fa) | |
756 | within_prologue = 0; | |
757 | else | |
758 | pc += NIOS2_OPCODE_SIZE; | |
759 | } | |
760 | ||
761 | else if ((insn & 0xf800003f) == 0xd8000036) | |
762 | { | |
763 | /* BLTU sp, rx, .Lstackoverflow | |
764 | If the location branched to holds a BREAK 3 instruction | |
765 | then this is also stack overflow detection. We can | |
766 | ignore it. */ | |
767 | CORE_ADDR target_pc = pc + ((insn & 0x3fffc0) >> 6); | |
768 | unsigned int target_insn | |
769 | = read_memory_unsigned_integer (target_pc, NIOS2_OPCODE_SIZE, | |
770 | byte_order); | |
771 | ||
772 | if (target_insn != 0x003da0fa) | |
773 | within_prologue = 0; | |
774 | } | |
775 | ||
776 | /* Any other instructions are allowed to be moved up into the | |
777 | prologue. If we reach a branch, call or return then the | |
778 | prologue is considered over. We also consider a second stack | |
779 | adjustment as terminating the prologue (see above). */ | |
780 | else | |
781 | { | |
782 | switch (GET_IW_OP (insn)) | |
783 | { | |
784 | case OP_BEQ: | |
785 | case OP_BGE: | |
786 | case OP_BGEU: | |
787 | case OP_BLT: | |
788 | case OP_BLTU: | |
789 | case OP_BNE: | |
790 | case OP_BR: | |
791 | case OP_CALL: | |
792 | within_prologue = 0; | |
793 | break; | |
794 | case OP_OPX: | |
795 | if (GET_IW_OPX (insn) == OPX_RET | |
796 | || GET_IW_OPX (insn) == OPX_ERET | |
797 | || GET_IW_OPX (insn) == OPX_BRET | |
798 | || GET_IW_OPX (insn) == OPX_CALLR | |
799 | || GET_IW_OPX (insn) == OPX_JMP) | |
800 | within_prologue = 0; | |
801 | break; | |
802 | default: | |
803 | break; | |
804 | } | |
805 | } | |
806 | ||
807 | if (prologue_insn) | |
808 | prologue_end = pc; | |
809 | } | |
810 | ||
811 | /* If THIS_FRAME is NULL, we are being called from skip_prologue | |
812 | and are only interested in the PROLOGUE_END value, so just | |
813 | return that now and skip over the cache updates, which depend | |
814 | on having frame information. */ | |
815 | if (this_frame == NULL) | |
816 | return prologue_end; | |
817 | ||
818 | /* If we are in the function epilogue and have already popped | |
819 | registers off the stack in preparation for returning, then we | |
820 | want to go back to the original register values. */ | |
821 | if (innermost && nios2_in_epilogue_p (gdbarch, current_pc, start_pc)) | |
822 | nios2_setup_default (cache); | |
823 | ||
824 | /* Exception handlers use a different return address register. */ | |
825 | if (exception_handler) | |
826 | cache->return_regnum = NIOS2_EA_REGNUM; | |
827 | ||
828 | if (nios2_debug) | |
829 | fprintf_unfiltered (gdb_stdlog, "\n-> retreg=%d, ", cache->return_regnum); | |
830 | ||
831 | if (cache->reg_value[NIOS2_FP_REGNUM].reg == NIOS2_SP_REGNUM) | |
832 | /* If the FP now holds an offset from the CFA then this is a | |
833 | normal frame which uses the frame pointer. */ | |
834 | base_reg = NIOS2_FP_REGNUM; | |
835 | else if (cache->reg_value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM) | |
836 | /* FP doesn't hold an offset from the CFA. If SP still holds an | |
837 | offset from the CFA then we might be in a function which omits | |
838 | the frame pointer, or we might be partway through the prologue. | |
839 | In both cases we can find the CFA using SP. */ | |
840 | base_reg = NIOS2_SP_REGNUM; | |
841 | else | |
842 | { | |
843 | /* Somehow the stack pointer has been corrupted. | |
844 | We can't return. */ | |
845 | if (nios2_debug) | |
846 | fprintf_unfiltered (gdb_stdlog, "<can't reach cfa> }\n"); | |
847 | return 0; | |
848 | } | |
849 | ||
850 | if (cache->reg_value[base_reg].offset == 0 | |
851 | || cache->reg_saved[NIOS2_RA_REGNUM].basereg != NIOS2_SP_REGNUM | |
852 | || cache->reg_saved[cache->return_regnum].basereg != NIOS2_SP_REGNUM) | |
853 | { | |
854 | /* If the frame didn't adjust the stack, didn't save RA or | |
855 | didn't save EA in an exception handler then it must either | |
856 | be a leaf function (doesn't call any other functions) or it | |
857 | can't return. If it has called another function then it | |
858 | can't be a leaf, so set base == 0 to indicate that we can't | |
859 | backtrace past it. */ | |
860 | ||
861 | if (!innermost) | |
862 | { | |
863 | /* If it isn't the innermost function then it can't be a | |
864 | leaf, unless it was interrupted. Check whether RA for | |
865 | this frame is the same as PC. If so then it probably | |
866 | wasn't interrupted. */ | |
867 | CORE_ADDR ra | |
868 | = get_frame_register_unsigned (this_frame, NIOS2_RA_REGNUM); | |
869 | ||
870 | if (ra == current_pc) | |
871 | { | |
872 | if (nios2_debug) | |
873 | fprintf_unfiltered | |
874 | (gdb_stdlog, | |
875 | "<noreturn ADJUST %s, r31@r%d+?>, r%d@r%d+?> }\n", | |
876 | paddress (gdbarch, cache->reg_value[base_reg].offset), | |
877 | cache->reg_saved[NIOS2_RA_REGNUM].basereg, | |
878 | cache->return_regnum, | |
879 | cache->reg_saved[cache->return_regnum].basereg); | |
880 | return 0; | |
881 | } | |
882 | } | |
883 | } | |
884 | ||
885 | /* Get the value of whichever register we are using for the | |
886 | base. */ | |
887 | cache->base = get_frame_register_unsigned (this_frame, base_reg); | |
888 | ||
889 | /* What was the value of SP at the start of this function (or just | |
890 | after the stack switch). */ | |
891 | frame_high = cache->base - cache->reg_value[base_reg].offset; | |
892 | ||
893 | /* Adjust all the saved registers such that they contain addresses | |
894 | instead of offsets. */ | |
895 | for (i = 0; i < NIOS2_NUM_REGS; i++) | |
896 | if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) | |
897 | { | |
898 | cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; | |
899 | cache->reg_saved[i].addr += frame_high; | |
900 | } | |
901 | ||
902 | for (i = 0; i < NIOS2_NUM_REGS; i++) | |
903 | if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) | |
904 | { | |
905 | CORE_ADDR gp = get_frame_register_unsigned (this_frame, | |
906 | NIOS2_GP_REGNUM); | |
907 | ||
908 | for ( ; i < NIOS2_NUM_REGS; i++) | |
909 | if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) | |
910 | { | |
911 | cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; | |
912 | cache->reg_saved[i].addr += gp; | |
913 | } | |
914 | } | |
915 | ||
916 | /* Work out what the value of SP was on the first instruction of | |
917 | this function. If we didn't switch stacks then this can be | |
918 | trivially computed from the base address. */ | |
919 | if (cache->reg_saved[NIOS2_SP_REGNUM].basereg == NIOS2_Z_REGNUM) | |
920 | cache->cfa | |
921 | = read_memory_unsigned_integer (cache->reg_saved[NIOS2_SP_REGNUM].addr, | |
922 | 4, byte_order); | |
923 | else | |
924 | cache->cfa = frame_high; | |
925 | ||
926 | /* Exception handlers restore ESTATUS into STATUS. */ | |
927 | if (exception_handler) | |
928 | { | |
929 | cache->reg_saved[NIOS2_STATUS_REGNUM] | |
930 | = cache->reg_saved[NIOS2_ESTATUS_REGNUM]; | |
931 | cache->reg_saved[NIOS2_ESTATUS_REGNUM].basereg = -1; | |
932 | } | |
933 | ||
934 | if (nios2_debug) | |
935 | fprintf_unfiltered (gdb_stdlog, "cfa=%s }\n", | |
936 | paddress (gdbarch, cache->cfa)); | |
937 | ||
938 | return prologue_end; | |
939 | } | |
940 | ||
941 | /* Implement the skip_prologue gdbarch hook. */ | |
942 | ||
943 | static CORE_ADDR | |
944 | nios2_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) | |
945 | { | |
946 | CORE_ADDR limit_pc; | |
947 | CORE_ADDR func_addr; | |
948 | ||
949 | struct nios2_unwind_cache cache; | |
950 | ||
951 | /* See if we can determine the end of the prologue via the symbol | |
952 | table. If so, then return either PC, or the PC after the | |
953 | prologue, whichever is greater. */ | |
954 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) | |
955 | { | |
956 | CORE_ADDR post_prologue_pc | |
957 | = skip_prologue_using_sal (gdbarch, func_addr); | |
958 | ||
959 | if (post_prologue_pc != 0) | |
960 | return max (start_pc, post_prologue_pc); | |
961 | } | |
962 | ||
963 | /* Prologue analysis does the rest.... */ | |
964 | nios2_init_cache (&cache, start_pc); | |
965 | return nios2_analyze_prologue (gdbarch, start_pc, start_pc, &cache, NULL); | |
966 | } | |
967 | ||
968 | /* Implement the breakpoint_from_pc gdbarch hook. */ | |
969 | ||
970 | static const gdb_byte* | |
971 | nios2_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr, | |
972 | int *bp_size) | |
973 | { | |
974 | /* break encoding: 31->27 26->22 21->17 16->11 10->6 5->0 */ | |
975 | /* 00000 00000 0x1d 0x2d 11111 0x3a */ | |
976 | /* 00000 00000 11101 101101 11111 111010 */ | |
977 | /* In bytes: 00000000 00111011 01101111 11111010 */ | |
978 | /* 0x0 0x3b 0x6f 0xfa */ | |
979 | static const gdb_byte breakpoint_le[] = {0xfa, 0x6f, 0x3b, 0x0}; | |
980 | static const gdb_byte breakpoint_be[] = {0x0, 0x3b, 0x6f, 0xfa}; | |
981 | ||
982 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
983 | ||
984 | *bp_size = 4; | |
985 | if (gdbarch_byte_order_for_code (gdbarch) == BFD_ENDIAN_BIG) | |
986 | return breakpoint_be; | |
987 | else | |
988 | return breakpoint_le; | |
989 | } | |
990 | ||
991 | /* Implement the print_insn gdbarch method. */ | |
992 | ||
993 | static int | |
994 | nios2_print_insn (bfd_vma memaddr, disassemble_info *info) | |
995 | { | |
996 | if (info->endian == BFD_ENDIAN_BIG) | |
997 | return print_insn_big_nios2 (memaddr, info); | |
998 | else | |
999 | return print_insn_little_nios2 (memaddr, info); | |
1000 | } | |
1001 | ||
1002 | ||
1003 | /* Implement the frame_align gdbarch method. */ | |
1004 | ||
1005 | static CORE_ADDR | |
1006 | nios2_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1007 | { | |
1008 | return align_down (addr, 4); | |
1009 | } | |
1010 | ||
1011 | ||
1012 | /* Implement the return_value gdbarch method. */ | |
1013 | ||
1014 | static enum return_value_convention | |
1015 | nios2_return_value (struct gdbarch *gdbarch, struct value *function, | |
1016 | struct type *type, struct regcache *regcache, | |
1017 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
1018 | { | |
1019 | if (TYPE_LENGTH (type) > 8) | |
1020 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1021 | ||
1022 | if (readbuf) | |
1023 | nios2_extract_return_value (gdbarch, type, regcache, readbuf); | |
1024 | if (writebuf) | |
1025 | nios2_store_return_value (gdbarch, type, regcache, writebuf); | |
1026 | ||
1027 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1028 | } | |
1029 | ||
1030 | /* Implement the dummy_id gdbarch method. */ | |
1031 | ||
1032 | static struct frame_id | |
1033 | nios2_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1034 | { | |
1035 | return frame_id_build | |
1036 | (get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM), | |
1037 | get_frame_pc (this_frame)); | |
1038 | } | |
1039 | ||
1040 | /* Implement the push_dummy_call gdbarch method. */ | |
1041 | ||
1042 | static CORE_ADDR | |
1043 | nios2_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1044 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1045 | int nargs, struct value **args, CORE_ADDR sp, | |
1046 | int struct_return, CORE_ADDR struct_addr) | |
1047 | { | |
1048 | int argreg; | |
1049 | int float_argreg; | |
1050 | int argnum; | |
1051 | int len = 0; | |
1052 | int stack_offset = 0; | |
1053 | CORE_ADDR func_addr = find_function_addr (function, NULL); | |
1054 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1055 | ||
1056 | /* Set the return address register to point to the entry point of | |
1057 | the program, where a breakpoint lies in wait. */ | |
1058 | regcache_cooked_write_signed (regcache, NIOS2_RA_REGNUM, bp_addr); | |
1059 | ||
1060 | /* Now make space on the stack for the args. */ | |
1061 | for (argnum = 0; argnum < nargs; argnum++) | |
1062 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), 4); | |
1063 | sp -= len; | |
1064 | ||
1065 | /* Initialize the register pointer. */ | |
1066 | argreg = NIOS2_FIRST_ARGREG; | |
1067 | ||
1068 | /* The struct_return pointer occupies the first parameter-passing | |
1069 | register. */ | |
1070 | if (struct_return) | |
1071 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); | |
1072 | ||
1073 | /* Now load as many as possible of the first arguments into | |
1074 | registers, and push the rest onto the stack. Loop through args | |
1075 | from first to last. */ | |
1076 | for (argnum = 0; argnum < nargs; argnum++) | |
1077 | { | |
1078 | const gdb_byte *val; | |
1079 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
1080 | struct value *arg = args[argnum]; | |
1081 | struct type *arg_type = check_typedef (value_type (arg)); | |
1082 | int len = TYPE_LENGTH (arg_type); | |
1083 | enum type_code typecode = TYPE_CODE (arg_type); | |
1084 | ||
1085 | val = value_contents (arg); | |
1086 | ||
1087 | /* Copy the argument to general registers or the stack in | |
1088 | register-sized pieces. Large arguments are split between | |
1089 | registers and stack. */ | |
1090 | while (len > 0) | |
1091 | { | |
1092 | int partial_len = (len < 4 ? len : 4); | |
1093 | ||
1094 | if (argreg <= NIOS2_LAST_ARGREG) | |
1095 | { | |
1096 | /* The argument is being passed in a register. */ | |
1097 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len, | |
1098 | byte_order); | |
1099 | ||
1100 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
1101 | argreg++; | |
1102 | } | |
1103 | else | |
1104 | { | |
1105 | /* The argument is being passed on the stack. */ | |
1106 | CORE_ADDR addr = sp + stack_offset; | |
1107 | ||
1108 | write_memory (addr, val, partial_len); | |
1109 | stack_offset += align_up (partial_len, 4); | |
1110 | } | |
1111 | ||
1112 | len -= partial_len; | |
1113 | val += partial_len; | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | regcache_cooked_write_signed (regcache, NIOS2_SP_REGNUM, sp); | |
1118 | ||
1119 | /* Return adjusted stack pointer. */ | |
1120 | return sp; | |
1121 | } | |
1122 | ||
1123 | /* Implement the unwind_pc gdbarch method. */ | |
1124 | ||
1125 | static CORE_ADDR | |
1126 | nios2_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1127 | { | |
1128 | gdb_byte buf[4]; | |
1129 | ||
1130 | frame_unwind_register (next_frame, NIOS2_PC_REGNUM, buf); | |
1131 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); | |
1132 | } | |
1133 | ||
1134 | /* Implement the unwind_sp gdbarch method. */ | |
1135 | ||
1136 | static CORE_ADDR | |
1137 | nios2_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1138 | { | |
1139 | return frame_unwind_register_unsigned (this_frame, NIOS2_SP_REGNUM); | |
1140 | } | |
1141 | ||
1142 | /* Use prologue analysis to fill in the register cache | |
1143 | *THIS_PROLOGUE_CACHE for THIS_FRAME. This function initializes | |
1144 | *THIS_PROLOGUE_CACHE first. */ | |
1145 | ||
1146 | static struct nios2_unwind_cache * | |
1147 | nios2_frame_unwind_cache (struct frame_info *this_frame, | |
1148 | void **this_prologue_cache) | |
1149 | { | |
1150 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1151 | CORE_ADDR current_pc; | |
1152 | struct nios2_unwind_cache *cache; | |
1153 | int i; | |
1154 | ||
1155 | if (*this_prologue_cache) | |
1156 | return *this_prologue_cache; | |
1157 | ||
1158 | cache = FRAME_OBSTACK_ZALLOC (struct nios2_unwind_cache); | |
1159 | *this_prologue_cache = cache; | |
1160 | ||
1161 | /* Zero all fields. */ | |
1162 | nios2_init_cache (cache, get_frame_func (this_frame)); | |
1163 | ||
1164 | /* Prologue analysis does the rest... */ | |
1165 | current_pc = get_frame_pc (this_frame); | |
1166 | if (cache->pc != 0) | |
1167 | nios2_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); | |
1168 | ||
1169 | return cache; | |
1170 | } | |
1171 | ||
1172 | /* Implement the this_id function for the normal unwinder. */ | |
1173 | ||
1174 | static void | |
1175 | nios2_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
1176 | struct frame_id *this_id) | |
1177 | { | |
1178 | struct nios2_unwind_cache *cache = | |
1179 | nios2_frame_unwind_cache (this_frame, this_cache); | |
1180 | ||
1181 | /* This marks the outermost frame. */ | |
1182 | if (cache->base == 0) | |
1183 | return; | |
1184 | ||
1185 | *this_id = frame_id_build (cache->cfa, cache->pc); | |
1186 | } | |
1187 | ||
1188 | /* Implement the prev_register function for the normal unwinder. */ | |
1189 | ||
1190 | static struct value * | |
1191 | nios2_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1192 | int regnum) | |
1193 | { | |
1194 | struct nios2_unwind_cache *cache = | |
1195 | nios2_frame_unwind_cache (this_frame, this_cache); | |
1196 | ||
1197 | gdb_assert (regnum >= 0 && regnum < NIOS2_NUM_REGS); | |
1198 | ||
1199 | /* The PC of the previous frame is stored in the RA register of | |
1200 | the current frame. Frob regnum so that we pull the value from | |
1201 | the correct place. */ | |
1202 | if (regnum == NIOS2_PC_REGNUM) | |
1203 | regnum = cache->return_regnum; | |
1204 | ||
1205 | if (regnum == NIOS2_SP_REGNUM && cache->cfa) | |
1206 | return frame_unwind_got_constant (this_frame, regnum, cache->cfa); | |
1207 | ||
1208 | /* If we've worked out where a register is stored then load it from | |
1209 | there. */ | |
1210 | if (cache->reg_saved[regnum].basereg == NIOS2_Z_REGNUM) | |
1211 | return frame_unwind_got_memory (this_frame, regnum, | |
1212 | cache->reg_saved[regnum].addr); | |
1213 | ||
1214 | return frame_unwind_got_register (this_frame, regnum, regnum); | |
1215 | } | |
1216 | ||
1217 | /* Implement the this_base, this_locals, and this_args hooks | |
1218 | for the normal unwinder. */ | |
1219 | ||
1220 | static CORE_ADDR | |
1221 | nios2_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
1222 | { | |
1223 | struct nios2_unwind_cache *info | |
1224 | = nios2_frame_unwind_cache (this_frame, this_cache); | |
1225 | ||
1226 | return info->base; | |
1227 | } | |
1228 | ||
1229 | /* Data structures for the normal prologue-analysis-based | |
1230 | unwinder. */ | |
1231 | ||
1232 | static const struct frame_unwind nios2_frame_unwind = | |
1233 | { | |
1234 | NORMAL_FRAME, | |
1235 | default_frame_unwind_stop_reason, | |
1236 | nios2_frame_this_id, | |
1237 | nios2_frame_prev_register, | |
1238 | NULL, | |
1239 | default_frame_sniffer | |
1240 | }; | |
1241 | ||
1242 | static const struct frame_base nios2_frame_base = | |
1243 | { | |
1244 | &nios2_frame_unwind, | |
1245 | nios2_frame_base_address, | |
1246 | nios2_frame_base_address, | |
1247 | nios2_frame_base_address | |
1248 | }; | |
1249 | ||
1250 | /* Fill in the register cache *THIS_CACHE for THIS_FRAME for use | |
1251 | in the stub unwinder. */ | |
1252 | ||
1253 | static struct trad_frame_cache * | |
1254 | nios2_stub_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1255 | { | |
1256 | CORE_ADDR pc; | |
1257 | CORE_ADDR start_addr; | |
1258 | CORE_ADDR stack_addr; | |
1259 | struct trad_frame_cache *this_trad_cache; | |
1260 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1261 | int num_regs = gdbarch_num_regs (gdbarch); | |
1262 | ||
1263 | if (*this_cache != NULL) | |
1264 | return *this_cache; | |
1265 | this_trad_cache = trad_frame_cache_zalloc (this_frame); | |
1266 | *this_cache = this_trad_cache; | |
1267 | ||
1268 | /* The return address is in the link register. */ | |
1269 | trad_frame_set_reg_realreg (this_trad_cache, | |
1270 | gdbarch_pc_regnum (gdbarch), | |
1271 | NIOS2_RA_REGNUM); | |
1272 | ||
1273 | /* Frame ID, since it's a frameless / stackless function, no stack | |
1274 | space is allocated and SP on entry is the current SP. */ | |
1275 | pc = get_frame_pc (this_frame); | |
1276 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
1277 | stack_addr = get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM); | |
1278 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); | |
1279 | /* Assume that the frame's base is the same as the stack pointer. */ | |
1280 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
1281 | ||
1282 | return this_trad_cache; | |
1283 | } | |
1284 | ||
1285 | /* Implement the this_id function for the stub unwinder. */ | |
1286 | ||
1287 | static void | |
1288 | nios2_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
1289 | struct frame_id *this_id) | |
1290 | { | |
1291 | struct trad_frame_cache *this_trad_cache | |
1292 | = nios2_stub_frame_cache (this_frame, this_cache); | |
1293 | ||
1294 | trad_frame_get_id (this_trad_cache, this_id); | |
1295 | } | |
1296 | ||
1297 | /* Implement the prev_register function for the stub unwinder. */ | |
1298 | ||
1299 | static struct value * | |
1300 | nios2_stub_frame_prev_register (struct frame_info *this_frame, | |
1301 | void **this_cache, int regnum) | |
1302 | { | |
1303 | struct trad_frame_cache *this_trad_cache | |
1304 | = nios2_stub_frame_cache (this_frame, this_cache); | |
1305 | ||
1306 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
1307 | } | |
1308 | ||
1309 | /* Implement the sniffer function for the stub unwinder. | |
1310 | This unwinder is used for cases where the normal | |
1311 | prologue-analysis-based unwinder can't work, | |
1312 | such as PLT stubs. */ | |
1313 | ||
1314 | static int | |
1315 | nios2_stub_frame_sniffer (const struct frame_unwind *self, | |
1316 | struct frame_info *this_frame, void **cache) | |
1317 | { | |
1318 | gdb_byte dummy[4]; | |
1319 | struct obj_section *s; | |
1320 | CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
1321 | ||
1322 | /* Use the stub unwinder for unreadable code. */ | |
1323 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) | |
1324 | return 1; | |
1325 | ||
3e5d3a5a | 1326 | if (in_plt_section (pc)) |
a1217d97 SL |
1327 | return 1; |
1328 | ||
1329 | return 0; | |
1330 | } | |
1331 | ||
a1217d97 SL |
1332 | /* Define the data structures for the stub unwinder. */ |
1333 | ||
1334 | static const struct frame_unwind nios2_stub_frame_unwind = | |
1335 | { | |
1336 | NORMAL_FRAME, | |
1337 | default_frame_unwind_stop_reason, | |
1338 | nios2_stub_frame_this_id, | |
1339 | nios2_stub_frame_prev_register, | |
1340 | NULL, | |
1341 | nios2_stub_frame_sniffer | |
1342 | }; | |
1343 | ||
a1217d97 SL |
1344 | /* Helper function to read an instruction at PC. */ |
1345 | ||
1346 | static unsigned long | |
1347 | nios2_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1348 | { | |
1349 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1350 | ||
1351 | return read_memory_unsigned_integer (pc, NIOS2_OPCODE_SIZE, byte_order); | |
1352 | } | |
1353 | ||
1354 | /* Determine where to set a single step breakpoint while considering | |
1355 | branch prediction. */ | |
1356 | ||
1357 | static CORE_ADDR | |
1358 | nios2_get_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
1359 | { | |
1360 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1361 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1362 | unsigned long inst; | |
1363 | int op; | |
1364 | int imm16; | |
1365 | int ra; | |
1366 | int rb; | |
1367 | int ras; | |
1368 | int rbs; | |
1369 | unsigned int rau; | |
1370 | unsigned int rbu; | |
1371 | ||
1372 | inst = nios2_fetch_instruction (gdbarch, pc); | |
1373 | pc += NIOS2_OPCODE_SIZE; | |
1374 | ||
1375 | imm16 = (short) GET_IW_IMM16 (inst); | |
1376 | ra = GET_IW_A (inst); | |
1377 | rb = GET_IW_B (inst); | |
1378 | ras = get_frame_register_signed (frame, ra); | |
1379 | rbs = get_frame_register_signed (frame, rb); | |
1380 | rau = get_frame_register_unsigned (frame, ra); | |
1381 | rbu = get_frame_register_unsigned (frame, rb); | |
1382 | ||
1383 | switch (GET_IW_OP (inst)) | |
1384 | { | |
1385 | case OP_BEQ: | |
1386 | if (ras == rbs) | |
1387 | pc += imm16; | |
1388 | break; | |
1389 | ||
1390 | case OP_BGE: | |
1391 | if (ras >= rbs) | |
1392 | pc += imm16; | |
1393 | break; | |
1394 | ||
1395 | case OP_BGEU: | |
1396 | if (rau >= rbu) | |
1397 | pc += imm16; | |
1398 | break; | |
1399 | ||
1400 | case OP_BLT: | |
1401 | if (ras < rbs) | |
1402 | pc += imm16; | |
1403 | break; | |
1404 | ||
1405 | case OP_BLTU: | |
1406 | if (rau < rbu) | |
1407 | pc += imm16; | |
1408 | break; | |
1409 | ||
1410 | case OP_BNE: | |
1411 | if (ras != rbs) | |
1412 | pc += imm16; | |
1413 | break; | |
1414 | ||
1415 | case OP_BR: | |
1416 | pc += imm16; | |
1417 | break; | |
1418 | ||
1419 | case OP_JMPI: | |
1420 | case OP_CALL: | |
1421 | pc = (pc & 0xf0000000) | (GET_IW_IMM26 (inst) << 2); | |
1422 | break; | |
1423 | ||
1424 | case OP_OPX: | |
1425 | switch (GET_IW_OPX (inst)) | |
1426 | { | |
1427 | case OPX_JMP: | |
1428 | case OPX_CALLR: | |
1429 | case OPX_RET: | |
1430 | pc = ras; | |
1431 | break; | |
1432 | ||
1433 | case OPX_TRAP: | |
1434 | if (tdep->syscall_next_pc != NULL) | |
1435 | return tdep->syscall_next_pc (frame); | |
1436 | ||
1437 | default: | |
1438 | break; | |
1439 | } | |
1440 | break; | |
1441 | default: | |
1442 | break; | |
1443 | } | |
1444 | return pc; | |
1445 | } | |
1446 | ||
1447 | /* Implement the software_single_step gdbarch method. */ | |
1448 | ||
1449 | static int | |
1450 | nios2_software_single_step (struct frame_info *frame) | |
1451 | { | |
1452 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1453 | struct address_space *aspace = get_frame_address_space (frame); | |
1454 | CORE_ADDR next_pc = nios2_get_next_pc (frame, get_frame_pc (frame)); | |
1455 | ||
1456 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); | |
1457 | ||
1458 | return 1; | |
1459 | } | |
1460 | ||
1461 | /* Implement the get_longjump_target gdbarch method. */ | |
1462 | ||
1463 | static int | |
1464 | nios2_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
1465 | { | |
1466 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1467 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1468 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1469 | CORE_ADDR jb_addr = get_frame_register_unsigned (frame, NIOS2_R4_REGNUM); | |
1470 | gdb_byte buf[4]; | |
1471 | ||
1472 | if (target_read_memory (jb_addr + (tdep->jb_pc * 4), buf, 4)) | |
1473 | return 0; | |
1474 | ||
1475 | *pc = extract_unsigned_integer (buf, 4, byte_order); | |
1476 | return 1; | |
1477 | } | |
1478 | ||
1479 | /* Initialize the Nios II gdbarch. */ | |
1480 | ||
1481 | static struct gdbarch * | |
1482 | nios2_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1483 | { | |
1484 | struct gdbarch *gdbarch; | |
1485 | struct gdbarch_tdep *tdep; | |
1486 | int register_bytes, i; | |
1487 | struct tdesc_arch_data *tdesc_data = NULL; | |
1488 | const struct target_desc *tdesc = info.target_desc; | |
1489 | ||
1490 | if (!tdesc_has_registers (tdesc)) | |
1491 | /* Pick a default target description. */ | |
1492 | tdesc = tdesc_nios2; | |
1493 | ||
1494 | /* Check any target description for validity. */ | |
1495 | if (tdesc_has_registers (tdesc)) | |
1496 | { | |
1497 | const struct tdesc_feature *feature; | |
1498 | int valid_p; | |
1499 | ||
1500 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nios2.cpu"); | |
1501 | if (feature == NULL) | |
1502 | return NULL; | |
1503 | ||
1504 | tdesc_data = tdesc_data_alloc (); | |
1505 | ||
1506 | valid_p = 1; | |
1507 | ||
1508 | for (i = 0; i < NIOS2_NUM_REGS; i++) | |
1509 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
1510 | nios2_reg_names[i]); | |
1511 | ||
1512 | if (!valid_p) | |
1513 | { | |
1514 | tdesc_data_cleanup (tdesc_data); | |
1515 | return NULL; | |
1516 | } | |
1517 | } | |
1518 | ||
1519 | /* Find a candidate among the list of pre-declared architectures. */ | |
1520 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1521 | if (arches != NULL) | |
1522 | return arches->gdbarch; | |
1523 | ||
1524 | /* None found, create a new architecture from the information | |
1525 | provided. */ | |
1526 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
1527 | gdbarch = gdbarch_alloc (&info, tdep); | |
1528 | ||
1529 | /* longjmp support not enabled by default. */ | |
1530 | tdep->jb_pc = -1; | |
1531 | ||
1532 | /* Data type sizes. */ | |
1533 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1534 | set_gdbarch_addr_bit (gdbarch, 32); | |
1535 | set_gdbarch_short_bit (gdbarch, 16); | |
1536 | set_gdbarch_int_bit (gdbarch, 32); | |
1537 | set_gdbarch_long_bit (gdbarch, 32); | |
1538 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1539 | set_gdbarch_float_bit (gdbarch, 32); | |
1540 | set_gdbarch_double_bit (gdbarch, 64); | |
1541 | ||
1542 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
1543 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1544 | ||
1545 | /* The register set. */ | |
1546 | set_gdbarch_num_regs (gdbarch, NIOS2_NUM_REGS); | |
1547 | set_gdbarch_sp_regnum (gdbarch, NIOS2_SP_REGNUM); | |
1548 | set_gdbarch_pc_regnum (gdbarch, NIOS2_PC_REGNUM); /* Pseudo register PC */ | |
1549 | ||
1550 | set_gdbarch_register_name (gdbarch, nios2_register_name); | |
1551 | set_gdbarch_register_type (gdbarch, nios2_register_type); | |
1552 | ||
1553 | /* Provide register mappings for stabs and dwarf2. */ | |
1554 | set_gdbarch_stab_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); | |
1555 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); | |
1556 | ||
1557 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1558 | ||
1559 | /* Call dummy code. */ | |
1560 | set_gdbarch_frame_align (gdbarch, nios2_frame_align); | |
1561 | ||
1562 | set_gdbarch_return_value (gdbarch, nios2_return_value); | |
1563 | ||
1564 | set_gdbarch_skip_prologue (gdbarch, nios2_skip_prologue); | |
1565 | set_gdbarch_in_function_epilogue_p (gdbarch, nios2_in_function_epilogue_p); | |
1566 | set_gdbarch_breakpoint_from_pc (gdbarch, nios2_breakpoint_from_pc); | |
1567 | ||
1568 | set_gdbarch_dummy_id (gdbarch, nios2_dummy_id); | |
1569 | set_gdbarch_unwind_pc (gdbarch, nios2_unwind_pc); | |
1570 | set_gdbarch_unwind_sp (gdbarch, nios2_unwind_sp); | |
1571 | ||
1572 | /* The dwarf2 unwinder will normally produce the best results if | |
1573 | the debug information is available, so register it first. */ | |
1574 | dwarf2_append_unwinders (gdbarch); | |
1575 | frame_unwind_append_unwinder (gdbarch, &nios2_stub_frame_unwind); | |
1576 | frame_unwind_append_unwinder (gdbarch, &nios2_frame_unwind); | |
1577 | ||
1578 | /* Single stepping. */ | |
1579 | set_gdbarch_software_single_step (gdbarch, nios2_software_single_step); | |
1580 | ||
1581 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
1582 | gdbarch_init_osabi (info, gdbarch); | |
1583 | ||
1584 | if (tdep->jb_pc >= 0) | |
1585 | set_gdbarch_get_longjmp_target (gdbarch, nios2_get_longjmp_target); | |
1586 | ||
1587 | frame_base_set_default (gdbarch, &nios2_frame_base); | |
1588 | ||
1589 | set_gdbarch_print_insn (gdbarch, nios2_print_insn); | |
1590 | ||
1591 | /* Enable inferior call support. */ | |
1592 | set_gdbarch_push_dummy_call (gdbarch, nios2_push_dummy_call); | |
1593 | ||
1594 | if (tdesc_data) | |
1595 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
1596 | ||
1597 | return gdbarch; | |
1598 | } | |
1599 | ||
1600 | extern initialize_file_ftype _initialize_nios2_tdep; /* -Wmissing-prototypes */ | |
1601 | ||
1602 | void | |
1603 | _initialize_nios2_tdep (void) | |
1604 | { | |
1605 | gdbarch_register (bfd_arch_nios2, nios2_gdbarch_init, NULL); | |
1606 | initialize_tdesc_nios2 (); | |
1607 | ||
1608 | /* Allow debugging this file's internals. */ | |
1609 | add_setshow_boolean_cmd ("nios2", class_maintenance, &nios2_debug, | |
1610 | _("Set Nios II debugging."), | |
1611 | _("Show Nios II debugging."), | |
1612 | _("When on, Nios II specific debugging is enabled."), | |
1613 | NULL, | |
1614 | NULL, | |
1615 | &setdebuglist, &showdebuglist); | |
1616 | } |