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a994fec4 | 1 | /* Target-dependent code for the 32-bit OpenRISC 1000, for the GDB. |
e2882c85 | 2 | Copyright (C) 2008-2018 Free Software Foundation, Inc. |
a994fec4 FJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #include "defs.h" | |
20 | #include "frame.h" | |
21 | #include "inferior.h" | |
22 | #include "symtab.h" | |
23 | #include "value.h" | |
24 | #include "gdbcmd.h" | |
25 | #include "language.h" | |
26 | #include "gdbcore.h" | |
27 | #include "symfile.h" | |
28 | #include "objfiles.h" | |
29 | #include "gdbtypes.h" | |
30 | #include "target.h" | |
31 | #include "regcache.h" | |
32 | #include "safe-ctype.h" | |
33 | #include "block.h" | |
34 | #include "reggroups.h" | |
35 | #include "arch-utils.h" | |
36 | #include "frame.h" | |
37 | #include "frame-unwind.h" | |
38 | #include "frame-base.h" | |
39 | #include "dwarf2-frame.h" | |
40 | #include "trad-frame.h" | |
41 | #include "regset.h" | |
42 | #include "remote.h" | |
43 | #include "target-descriptions.h" | |
44 | #include <inttypes.h> | |
45 | #include "dis-asm.h" | |
46 | ||
47 | /* OpenRISC specific includes. */ | |
48 | #include "or1k-tdep.h" | |
49 | #include "features/or1k.c" | |
50 | \f | |
51 | ||
52 | /* Global debug flag. */ | |
53 | ||
54 | static int or1k_debug = 0; | |
55 | ||
56 | static void | |
57 | show_or1k_debug (struct ui_file *file, int from_tty, | |
38af1824 | 58 | struct cmd_list_element *c, const char *value) |
a994fec4 FJ |
59 | { |
60 | fprintf_filtered (file, _("OpenRISC debugging is %s.\n"), value); | |
61 | } | |
62 | ||
63 | ||
64 | /* The target-dependent structure for gdbarch. */ | |
65 | ||
66 | struct gdbarch_tdep | |
67 | { | |
68 | int bytes_per_word; | |
69 | int bytes_per_address; | |
70 | CGEN_CPU_DESC gdb_cgen_cpu_desc; | |
71 | }; | |
72 | ||
73 | /* Support functions for the architecture definition. */ | |
74 | ||
75 | /* Get an instruction from memory. */ | |
76 | ||
77 | static ULONGEST | |
78 | or1k_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) | |
79 | { | |
80 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
81 | gdb_byte buf[OR1K_INSTLEN]; | |
82 | ||
83 | if (target_read_code (addr, buf, OR1K_INSTLEN)) { | |
84 | memory_error (TARGET_XFER_E_IO, addr); | |
85 | } | |
86 | ||
87 | return extract_unsigned_integer (buf, OR1K_INSTLEN, byte_order); | |
88 | } | |
89 | ||
90 | /* Generic function to read bits from an instruction. */ | |
91 | ||
92 | static bool | |
93 | or1k_analyse_inst (uint32_t inst, const char *format, ...) | |
94 | { | |
95 | /* Break out each field in turn, validating as we go. */ | |
96 | va_list ap; | |
97 | int i; | |
98 | int iptr = 0; /* Instruction pointer */ | |
99 | ||
100 | va_start (ap, format); | |
101 | ||
102 | for (i = 0; 0 != format[i];) | |
103 | { | |
104 | const char *start_ptr; | |
105 | char *end_ptr; | |
106 | ||
107 | uint32_t bits; /* Bit substring of interest */ | |
108 | uint32_t width; /* Substring width */ | |
109 | uint32_t *arg_ptr; | |
110 | ||
111 | switch (format[i]) | |
112 | { | |
113 | case ' ': | |
114 | i++; | |
115 | break; /* Formatting: ignored */ | |
116 | ||
117 | case '0': | |
118 | case '1': /* Constant bit field */ | |
119 | bits = (inst >> (OR1K_INSTBITLEN - iptr - 1)) & 0x1; | |
120 | ||
121 | if ((format[i] - '0') != bits) | |
122 | return false; | |
123 | ||
124 | iptr++; | |
125 | i++; | |
126 | break; | |
127 | ||
128 | case '%': /* Bit field */ | |
129 | i++; | |
130 | start_ptr = &(format[i]); | |
131 | width = strtoul (start_ptr, &end_ptr, 10); | |
132 | ||
133 | /* Check we got something, and if so skip on. */ | |
134 | if (start_ptr == end_ptr) | |
96647014 | 135 | error (_("bitstring \"%s\" at offset %d has no length field."), |
38af1824 | 136 | format, i); |
a994fec4 FJ |
137 | |
138 | i += end_ptr - start_ptr; | |
139 | ||
140 | /* Look for and skip the terminating 'b'. If it's not there, we | |
141 | still give a fatal error, because these are fixed strings that | |
142 | just should not be wrong. */ | |
143 | if ('b' != format[i++]) | |
96647014 | 144 | error (_("bitstring \"%s\" at offset %d has no terminating 'b'."), |
38af1824 | 145 | format, i); |
a994fec4 FJ |
146 | |
147 | /* Break out the field. There is a special case with a bit width | |
148 | of 32. */ | |
149 | if (32 == width) | |
150 | bits = inst; | |
151 | else | |
152 | bits = | |
153 | (inst >> (OR1K_INSTBITLEN - iptr - width)) & ((1 << width) - 1); | |
154 | ||
155 | arg_ptr = va_arg (ap, uint32_t *); | |
156 | *arg_ptr = bits; | |
157 | iptr += width; | |
158 | break; | |
159 | ||
160 | default: | |
96647014 | 161 | error (_("invalid character in bitstring \"%s\" at offset %d."), |
38af1824 | 162 | format, i); |
a994fec4 FJ |
163 | break; |
164 | } | |
165 | } | |
166 | ||
167 | /* Is the length OK? */ | |
168 | gdb_assert (OR1K_INSTBITLEN == iptr); | |
169 | ||
170 | return true; /* Success */ | |
171 | } | |
172 | ||
173 | /* This is used to parse l.addi instructions during various prologue | |
174 | analysis routines. The l.addi instruction has semantics: | |
175 | ||
176 | assembly: l.addi rD,rA,I | |
177 | implementation: rD = rA + sign_extend(Immediate) | |
178 | ||
179 | The rd_ptr, ra_ptr and simm_ptr must be non NULL pointers and are used | |
180 | to store the parse results. Upon successful parsing true is returned, | |
181 | false on failure. */ | |
182 | ||
183 | static bool | |
184 | or1k_analyse_l_addi (uint32_t inst, unsigned int *rd_ptr, | |
185 | unsigned int *ra_ptr, int *simm_ptr) | |
186 | { | |
187 | /* Instruction fields */ | |
188 | uint32_t rd, ra, i; | |
189 | ||
190 | if (or1k_analyse_inst (inst, "10 0111 %5b %5b %16b", &rd, &ra, &i)) | |
191 | { | |
192 | /* Found it. Construct the result fields. */ | |
193 | *rd_ptr = (unsigned int) rd; | |
194 | *ra_ptr = (unsigned int) ra; | |
195 | *simm_ptr = (int) (((i & 0x8000) == 0x8000) ? 0xffff0000 | i : i); | |
196 | ||
197 | return true; /* Success */ | |
198 | } | |
199 | else | |
200 | return false; /* Failure */ | |
201 | } | |
202 | ||
203 | /* This is used to to parse store instructions during various prologue | |
204 | analysis routines. The l.sw instruction has semantics: | |
205 | ||
206 | assembly: l.sw I(rA),rB | |
207 | implementation: store rB contents to memory at effective address of | |
208 | rA + sign_extend(Immediate) | |
209 | ||
210 | The simm_ptr, ra_ptr and rb_ptr must be non NULL pointers and are used | |
211 | to store the parse results. Upon successful parsing true is returned, | |
212 | false on failure. */ | |
213 | ||
214 | static bool | |
215 | or1k_analyse_l_sw (uint32_t inst, int *simm_ptr, unsigned int *ra_ptr, | |
216 | unsigned int *rb_ptr) | |
217 | { | |
218 | /* Instruction fields */ | |
219 | uint32_t ihi, ilo, ra, rb; | |
220 | ||
221 | if (or1k_analyse_inst (inst, "11 0101 %5b %5b %5b %11b", &ihi, &ra, &rb, | |
222 | &ilo)) | |
223 | ||
224 | { | |
225 | /* Found it. Construct the result fields. */ | |
226 | *simm_ptr = (int) ((ihi << 11) | ilo); | |
227 | *simm_ptr |= ((ihi & 0x10) == 0x10) ? 0xffff0000 : 0; | |
228 | ||
229 | *ra_ptr = (unsigned int) ra; | |
230 | *rb_ptr = (unsigned int) rb; | |
231 | ||
232 | return true; /* Success */ | |
233 | } | |
234 | else | |
235 | return false; /* Failure */ | |
236 | } | |
237 | \f | |
238 | ||
239 | /* Functions defining the architecture. */ | |
240 | ||
241 | /* Implement the return_value gdbarch method. */ | |
242 | ||
243 | static enum return_value_convention | |
244 | or1k_return_value (struct gdbarch *gdbarch, struct value *functype, | |
245 | struct type *valtype, struct regcache *regcache, | |
246 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
247 | { | |
248 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
249 | enum type_code rv_type = TYPE_CODE (valtype); | |
250 | unsigned int rv_size = TYPE_LENGTH (valtype); | |
251 | int bpw = (gdbarch_tdep (gdbarch))->bytes_per_word; | |
252 | ||
253 | /* Deal with struct/union as addresses. If an array won't fit in a | |
254 | single register it is returned as address. Anything larger than 2 | |
255 | registers needs to also be passed as address (matches gcc | |
256 | default_return_in_memory). */ | |
257 | if ((TYPE_CODE_STRUCT == rv_type) || (TYPE_CODE_UNION == rv_type) | |
258 | || ((TYPE_CODE_ARRAY == rv_type) && (rv_size > bpw)) | |
259 | || (rv_size > 2 * bpw)) | |
260 | { | |
261 | if (readbuf != NULL) | |
262 | { | |
263 | ULONGEST tmp; | |
264 | ||
265 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp); | |
266 | read_memory (tmp, readbuf, rv_size); | |
267 | } | |
268 | if (writebuf != NULL) | |
269 | { | |
270 | ULONGEST tmp; | |
271 | ||
272 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp); | |
273 | write_memory (tmp, writebuf, rv_size); | |
274 | } | |
275 | ||
276 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
277 | } | |
278 | ||
279 | if (rv_size <= bpw) | |
280 | { | |
281 | /* Up to one word scalars are returned in R11. */ | |
282 | if (readbuf != NULL) | |
283 | { | |
284 | ULONGEST tmp; | |
285 | ||
286 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp); | |
287 | store_unsigned_integer (readbuf, rv_size, byte_order, tmp); | |
288 | ||
289 | } | |
290 | if (writebuf != NULL) | |
291 | { | |
292 | gdb_byte *buf = XCNEWVEC(gdb_byte, bpw); | |
293 | ||
294 | if (BFD_ENDIAN_BIG == byte_order) | |
295 | memcpy (buf + (sizeof (gdb_byte) * bpw) - rv_size, writebuf, | |
296 | rv_size); | |
297 | else | |
298 | memcpy (buf, writebuf, rv_size); | |
299 | ||
300 | regcache_cooked_write (regcache, OR1K_RV_REGNUM, buf); | |
301 | ||
302 | free (buf); | |
303 | } | |
304 | } | |
305 | else | |
306 | { | |
307 | /* 2 word scalars are returned in r11/r12 (with the MS word in r11). */ | |
308 | if (readbuf != NULL) | |
309 | { | |
310 | ULONGEST tmp_lo; | |
311 | ULONGEST tmp_hi; | |
312 | ULONGEST tmp; | |
313 | ||
314 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, | |
315 | &tmp_hi); | |
316 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM + 1, | |
317 | &tmp_lo); | |
318 | tmp = (tmp_hi << (bpw * 8)) | tmp_lo; | |
319 | ||
320 | store_unsigned_integer (readbuf, rv_size, byte_order, tmp); | |
321 | } | |
322 | if (writebuf != NULL) | |
323 | { | |
324 | gdb_byte *buf_lo = XCNEWVEC(gdb_byte, bpw); | |
325 | gdb_byte *buf_hi = XCNEWVEC(gdb_byte, bpw); | |
326 | ||
327 | /* This is cheating. We assume that we fit in 2 words exactly, | |
328 | which wouldn't work if we had (say) a 6-byte scalar type on a | |
329 | big endian architecture (with the OpenRISC 1000 usually is). */ | |
330 | memcpy (buf_hi, writebuf, rv_size - bpw); | |
331 | memcpy (buf_lo, writebuf + bpw, bpw); | |
332 | ||
333 | regcache_cooked_write (regcache, OR1K_RV_REGNUM, buf_hi); | |
334 | regcache_cooked_write (regcache, OR1K_RV_REGNUM + 1, buf_lo); | |
335 | ||
336 | free (buf_lo); | |
337 | free (buf_hi); | |
338 | } | |
339 | } | |
340 | ||
341 | return RETURN_VALUE_REGISTER_CONVENTION; | |
342 | } | |
343 | ||
344 | /* OR1K always uses a l.trap instruction for breakpoints. */ | |
345 | ||
346 | constexpr gdb_byte or1k_break_insn[] = {0x21, 0x00, 0x00, 0x01}; | |
347 | ||
348 | typedef BP_MANIPULATION (or1k_break_insn) or1k_breakpoint; | |
349 | ||
350 | /* Implement the single_step_through_delay gdbarch method. */ | |
351 | ||
352 | static int | |
353 | or1k_single_step_through_delay (struct gdbarch *gdbarch, | |
354 | struct frame_info *this_frame) | |
355 | { | |
356 | ULONGEST val; | |
357 | CORE_ADDR ppc; | |
358 | CORE_ADDR npc; | |
359 | CGEN_FIELDS tmp_fields; | |
360 | const CGEN_INSN *insn; | |
361 | struct regcache *regcache = get_current_regcache (); | |
362 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
363 | ||
364 | /* Get the previous and current instruction addresses. If they are not | |
365 | adjacent, we cannot be in a delay slot. */ | |
366 | regcache_cooked_read_unsigned (regcache, OR1K_PPC_REGNUM, &val); | |
367 | ppc = (CORE_ADDR) val; | |
368 | regcache_cooked_read_unsigned (regcache, OR1K_NPC_REGNUM, &val); | |
369 | npc = (CORE_ADDR) val; | |
370 | ||
371 | if (0x4 != (npc - ppc)) | |
372 | return 0; | |
373 | ||
374 | insn = cgen_lookup_insn (tdep->gdb_cgen_cpu_desc, | |
38af1824 SH |
375 | NULL, |
376 | or1k_fetch_instruction (gdbarch, ppc), | |
377 | NULL, 32, &tmp_fields, 0); | |
a994fec4 FJ |
378 | |
379 | /* NULL here would mean the last instruction was not understood by cgen. | |
380 | This should not usually happen, but if does its not a delay slot. */ | |
381 | if (insn == NULL) | |
382 | return 0; | |
383 | ||
384 | /* TODO: we should add a delay slot flag to the CGEN_INSN and remove | |
385 | this hard coded test. */ | |
386 | return ((CGEN_INSN_NUM (insn) == OR1K_INSN_L_J) | |
387 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JAL) | |
388 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JR) | |
389 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JALR) | |
390 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_BNF) | |
391 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_BF)); | |
392 | } | |
393 | ||
394 | /* Name for or1k general registers. */ | |
395 | ||
396 | static const char *const or1k_reg_names[OR1K_NUM_REGS] = { | |
397 | /* general purpose registers */ | |
398 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
399 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
400 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
401 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
402 | ||
403 | /* previous program counter, next program counter and status register */ | |
404 | "ppc", "npc", "sr" | |
405 | }; | |
406 | ||
407 | static int | |
408 | or1k_is_arg_reg (unsigned int regnum) | |
409 | { | |
410 | return (OR1K_FIRST_ARG_REGNUM <= regnum) | |
411 | && (regnum <= OR1K_LAST_ARG_REGNUM); | |
412 | } | |
413 | ||
414 | static int | |
415 | or1k_is_callee_saved_reg (unsigned int regnum) | |
416 | { | |
417 | return (OR1K_FIRST_SAVED_REGNUM <= regnum) && (0 == regnum % 2); | |
418 | } | |
419 | ||
420 | /* Implement the skip_prologue gdbarch method. */ | |
421 | ||
422 | static CORE_ADDR | |
423 | or1k_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
424 | { | |
425 | CORE_ADDR start_pc; | |
426 | CORE_ADDR addr; | |
427 | uint32_t inst; | |
428 | ||
429 | unsigned int ra, rb, rd; /* for instruction analysis */ | |
430 | int simm; | |
431 | ||
432 | int frame_size = 0; | |
433 | ||
434 | /* Try using SAL first if we have symbolic information available. This | |
435 | only works for DWARF 2, not STABS. */ | |
436 | ||
437 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
438 | { | |
439 | CORE_ADDR prologue_end = skip_prologue_using_sal (gdbarch, pc); | |
440 | ||
441 | if (0 != prologue_end) | |
442 | { | |
443 | struct symtab_and_line prologue_sal = find_pc_line (start_pc, 0); | |
444 | struct compunit_symtab *compunit | |
445 | = SYMTAB_COMPUNIT (prologue_sal.symtab); | |
446 | const char *debug_format = COMPUNIT_DEBUGFORMAT (compunit); | |
447 | ||
448 | if ((NULL != debug_format) | |
449 | && (strlen ("dwarf") <= strlen (debug_format)) | |
450 | && (0 == strncasecmp ("dwarf", debug_format, strlen ("dwarf")))) | |
451 | return (prologue_end > pc) ? prologue_end : pc; | |
452 | } | |
453 | } | |
454 | ||
455 | /* Look to see if we can find any of the standard prologue sequence. All | |
456 | quite difficult, since any or all of it may be missing. So this is | |
457 | just a best guess! */ | |
458 | ||
459 | addr = pc; /* Where we have got to */ | |
460 | inst = or1k_fetch_instruction (gdbarch, addr); | |
461 | ||
462 | /* Look for the new stack pointer being set up. */ | |
463 | if (or1k_analyse_l_addi (inst, &rd, &ra, &simm) | |
464 | && (OR1K_SP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) | |
465 | && (simm < 0) && (0 == (simm % 4))) | |
466 | { | |
467 | frame_size = -simm; | |
468 | addr += OR1K_INSTLEN; | |
469 | inst = or1k_fetch_instruction (gdbarch, addr); | |
470 | } | |
471 | ||
472 | /* Look for the frame pointer being manipulated. */ | |
473 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
474 | && (OR1K_SP_REGNUM == ra) && (OR1K_FP_REGNUM == rb) | |
475 | && (simm >= 0) && (0 == (simm % 4))) | |
476 | { | |
477 | addr += OR1K_INSTLEN; | |
478 | inst = or1k_fetch_instruction (gdbarch, addr); | |
479 | ||
480 | gdb_assert (or1k_analyse_l_addi (inst, &rd, &ra, &simm) | |
481 | && (OR1K_FP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) | |
482 | && (simm == frame_size)); | |
483 | ||
484 | addr += OR1K_INSTLEN; | |
485 | inst = or1k_fetch_instruction (gdbarch, addr); | |
486 | } | |
487 | ||
488 | /* Look for the link register being saved. */ | |
489 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
490 | && (OR1K_SP_REGNUM == ra) && (OR1K_LR_REGNUM == rb) | |
491 | && (simm >= 0) && (0 == (simm % 4))) | |
492 | { | |
493 | addr += OR1K_INSTLEN; | |
494 | inst = or1k_fetch_instruction (gdbarch, addr); | |
495 | } | |
496 | ||
497 | /* Look for arguments or callee-saved register being saved. The register | |
498 | must be one of the arguments (r3-r8) or the 10 callee saved registers | |
499 | (r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, r30). The base | |
500 | register must be the FP (for the args) or the SP (for the callee_saved | |
501 | registers). */ | |
502 | while (1) | |
503 | { | |
504 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
505 | && (((OR1K_FP_REGNUM == ra) && or1k_is_arg_reg (rb)) | |
506 | || ((OR1K_SP_REGNUM == ra) && or1k_is_callee_saved_reg (rb))) | |
507 | && (0 == (simm % 4))) | |
508 | { | |
509 | addr += OR1K_INSTLEN; | |
510 | inst = or1k_fetch_instruction (gdbarch, addr); | |
511 | } | |
512 | else | |
513 | { | |
514 | /* Nothing else to look for. We have found the end of the | |
515 | prologue. */ | |
516 | break; | |
517 | } | |
518 | } | |
519 | return addr; | |
520 | } | |
521 | ||
522 | /* Implement the frame_align gdbarch method. */ | |
523 | ||
524 | static CORE_ADDR | |
525 | or1k_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
526 | { | |
527 | return align_down (sp, OR1K_STACK_ALIGN); | |
528 | } | |
529 | ||
530 | /* Implement the unwind_pc gdbarch method. */ | |
531 | ||
532 | static CORE_ADDR | |
533 | or1k_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
534 | { | |
535 | CORE_ADDR pc; | |
536 | ||
537 | if (or1k_debug) | |
538 | fprintf_unfiltered (gdb_stdlog, "or1k_unwind_pc, next_frame=%d\n", | |
539 | frame_relative_level (next_frame)); | |
540 | ||
541 | pc = frame_unwind_register_unsigned (next_frame, OR1K_NPC_REGNUM); | |
542 | ||
543 | if (or1k_debug) | |
96647014 SH |
544 | fprintf_unfiltered (gdb_stdlog, "or1k_unwind_pc, pc=%s\n", |
545 | paddress (gdbarch, pc)); | |
a994fec4 FJ |
546 | |
547 | return pc; | |
548 | } | |
549 | ||
550 | /* Implement the unwind_sp gdbarch method. */ | |
551 | ||
552 | static CORE_ADDR | |
553 | or1k_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
554 | { | |
555 | CORE_ADDR sp; | |
556 | ||
557 | if (or1k_debug) | |
558 | fprintf_unfiltered (gdb_stdlog, "or1k_unwind_sp, next_frame=%d\n", | |
559 | frame_relative_level (next_frame)); | |
560 | ||
561 | sp = frame_unwind_register_unsigned (next_frame, OR1K_SP_REGNUM); | |
562 | ||
563 | if (or1k_debug) | |
96647014 SH |
564 | fprintf_unfiltered (gdb_stdlog, "or1k_unwind_sp, sp=%s\n", |
565 | paddress (gdbarch, sp)); | |
a994fec4 FJ |
566 | |
567 | return sp; | |
568 | } | |
569 | ||
570 | /* Implement the push_dummy_code gdbarch method. */ | |
571 | ||
572 | static CORE_ADDR | |
573 | or1k_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
574 | CORE_ADDR function, struct value **args, int nargs, | |
575 | struct type *value_type, CORE_ADDR * real_pc, | |
576 | CORE_ADDR * bp_addr, struct regcache *regcache) | |
577 | { | |
578 | CORE_ADDR bp_slot; | |
579 | ||
580 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
581 | bp_slot = sp - 4; | |
582 | /* Store the address of that breakpoint. */ | |
583 | *bp_addr = bp_slot; | |
584 | /* keeping the stack aligned. */ | |
585 | sp = or1k_frame_align (gdbarch, bp_slot); | |
586 | /* The call starts at the callee's entry point. */ | |
587 | *real_pc = function; | |
588 | ||
589 | return sp; | |
590 | } | |
591 | ||
592 | /* Implement the push_dummy_call gdbarch method. */ | |
593 | ||
594 | static CORE_ADDR | |
595 | or1k_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
596 | struct regcache *regcache, CORE_ADDR bp_addr, | |
597 | int nargs, struct value **args, CORE_ADDR sp, | |
598 | int struct_return, CORE_ADDR struct_addr) | |
599 | { | |
600 | ||
601 | int argreg; | |
602 | int argnum; | |
603 | int first_stack_arg; | |
604 | int stack_offset = 0; | |
605 | int heap_offset = 0; | |
606 | CORE_ADDR heap_sp = sp - 128; | |
607 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
608 | int bpa = (gdbarch_tdep (gdbarch))->bytes_per_address; | |
609 | int bpw = (gdbarch_tdep (gdbarch))->bytes_per_word; | |
610 | struct type *func_type = value_type (function); | |
611 | ||
612 | /* Return address */ | |
613 | regcache_cooked_write_unsigned (regcache, OR1K_LR_REGNUM, bp_addr); | |
614 | ||
615 | /* Register for the next argument. */ | |
616 | argreg = OR1K_FIRST_ARG_REGNUM; | |
617 | ||
618 | /* Location for a returned structure. This is passed as a silent first | |
619 | argument. */ | |
620 | if (struct_return) | |
621 | { | |
622 | regcache_cooked_write_unsigned (regcache, OR1K_FIRST_ARG_REGNUM, | |
623 | struct_addr); | |
624 | argreg++; | |
625 | } | |
626 | ||
627 | /* Put as many args as possible in registers. */ | |
628 | for (argnum = 0; argnum < nargs; argnum++) | |
629 | { | |
630 | const gdb_byte *val; | |
631 | gdb_byte valbuf[sizeof (ULONGEST)]; | |
632 | ||
633 | struct value *arg = args[argnum]; | |
634 | struct type *arg_type = check_typedef (value_type (arg)); | |
635 | int len = TYPE_LENGTH (arg_type); | |
636 | enum type_code typecode = TYPE_CODE (arg_type); | |
637 | ||
638 | if (TYPE_VARARGS (func_type) && argnum >= TYPE_NFIELDS (func_type)) | |
639 | break; /* end or regular args, varargs go to stack. */ | |
640 | ||
641 | /* Extract the value, either a reference or the data. */ | |
642 | if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode) | |
643 | || (len > bpw * 2)) | |
644 | { | |
645 | CORE_ADDR valaddr = value_address (arg); | |
646 | ||
647 | /* If the arg is fabricated (i.e. 3*i, instead of i) valaddr is | |
648 | undefined. */ | |
649 | if (valaddr == 0) | |
650 | { | |
651 | /* The argument needs to be copied into the target space. | |
652 | Since the bottom of the stack is reserved for function | |
653 | arguments we store this at the these at the top growing | |
654 | down. */ | |
655 | heap_offset += align_up (len, bpw); | |
656 | valaddr = heap_sp + heap_offset; | |
657 | ||
658 | write_memory (valaddr, value_contents (arg), len); | |
659 | } | |
660 | ||
661 | /* The ABI passes all structures by reference, so get its | |
662 | address. */ | |
663 | store_unsigned_integer (valbuf, bpa, byte_order, valaddr); | |
664 | len = bpa; | |
665 | val = valbuf; | |
666 | } | |
667 | else | |
668 | { | |
669 | /* Everything else, we just get the value. */ | |
670 | val = value_contents (arg); | |
671 | } | |
672 | ||
673 | /* Stick the value in a register. */ | |
674 | if (len > bpw) | |
675 | { | |
676 | /* Big scalars use two registers, but need NOT be pair aligned. */ | |
677 | ||
678 | if (argreg <= (OR1K_LAST_ARG_REGNUM - 1)) | |
679 | { | |
680 | ULONGEST regval = extract_unsigned_integer (val, len, | |
681 | byte_order); | |
682 | ||
683 | unsigned int bits_per_word = bpw * 8; | |
684 | ULONGEST mask = (((ULONGEST) 1) << bits_per_word) - 1; | |
685 | ULONGEST lo = regval & mask; | |
686 | ULONGEST hi = regval >> bits_per_word; | |
687 | ||
688 | regcache_cooked_write_unsigned (regcache, argreg, hi); | |
689 | regcache_cooked_write_unsigned (regcache, argreg + 1, lo); | |
690 | argreg += 2; | |
691 | } | |
692 | else | |
693 | { | |
694 | /* Run out of regs */ | |
695 | break; | |
696 | } | |
697 | } | |
698 | else if (argreg <= OR1K_LAST_ARG_REGNUM) | |
699 | { | |
700 | /* Smaller scalars fit in a single register. */ | |
701 | regcache_cooked_write_unsigned | |
702 | (regcache, argreg, extract_unsigned_integer (val, len, | |
703 | byte_order)); | |
704 | argreg++; | |
705 | } | |
706 | else | |
707 | { | |
708 | /* Ran out of regs. */ | |
709 | break; | |
710 | } | |
711 | } | |
712 | ||
713 | first_stack_arg = argnum; | |
714 | ||
715 | /* If we get here with argnum < nargs, then arguments remain to be | |
716 | placed on the stack. This is tricky, since they must be pushed in | |
717 | reverse order and the stack in the end must be aligned. The only | |
718 | solution is to do it in two stages, the first to compute the stack | |
719 | size, the second to save the args. */ | |
720 | ||
721 | for (argnum = first_stack_arg; argnum < nargs; argnum++) | |
722 | { | |
723 | struct value *arg = args[argnum]; | |
724 | struct type *arg_type = check_typedef (value_type (arg)); | |
725 | int len = TYPE_LENGTH (arg_type); | |
726 | enum type_code typecode = TYPE_CODE (arg_type); | |
727 | ||
728 | if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode) | |
729 | || (len > bpw * 2)) | |
730 | { | |
731 | /* Structures are passed as addresses. */ | |
732 | sp -= bpa; | |
733 | } | |
734 | else | |
735 | { | |
736 | /* Big scalars use more than one word. Code here allows for | |
737 | future quad-word entities (e.g. long double.) */ | |
738 | sp -= align_up (len, bpw); | |
739 | } | |
740 | ||
741 | /* Ensure our dummy heap doesn't touch the stack, this could only | |
742 | happen if we have many arguments including fabricated arguments. */ | |
743 | gdb_assert (heap_offset == 0 || ((heap_sp + heap_offset) < sp)); | |
744 | } | |
745 | ||
746 | sp = gdbarch_frame_align (gdbarch, sp); | |
747 | stack_offset = 0; | |
748 | ||
749 | /* Push the remaining args on the stack. */ | |
750 | for (argnum = first_stack_arg; argnum < nargs; argnum++) | |
751 | { | |
752 | const gdb_byte *val; | |
753 | gdb_byte valbuf[sizeof (ULONGEST)]; | |
754 | ||
755 | struct value *arg = args[argnum]; | |
756 | struct type *arg_type = check_typedef (value_type (arg)); | |
757 | int len = TYPE_LENGTH (arg_type); | |
758 | enum type_code typecode = TYPE_CODE (arg_type); | |
759 | /* The EABI passes structures that do not fit in a register by | |
760 | reference. In all other cases, pass the structure by value. */ | |
761 | if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode) | |
762 | || (len > bpw * 2)) | |
763 | { | |
764 | store_unsigned_integer (valbuf, bpa, byte_order, | |
765 | value_address (arg)); | |
766 | len = bpa; | |
767 | val = valbuf; | |
768 | } | |
769 | else | |
770 | val = value_contents (arg); | |
771 | ||
772 | while (len > 0) | |
773 | { | |
774 | int partial_len = (len < bpw ? len : bpw); | |
775 | ||
776 | write_memory (sp + stack_offset, val, partial_len); | |
777 | stack_offset += align_up (partial_len, bpw); | |
778 | len -= partial_len; | |
779 | val += partial_len; | |
780 | } | |
781 | } | |
782 | ||
783 | /* Save the updated stack pointer. */ | |
784 | regcache_cooked_write_unsigned (regcache, OR1K_SP_REGNUM, sp); | |
785 | ||
786 | if (heap_offset > 0) | |
787 | sp = heap_sp; | |
788 | ||
789 | return sp; | |
790 | } | |
791 | ||
792 | /* Implement the dummy_id gdbarch method. */ | |
793 | ||
794 | static struct frame_id | |
795 | or1k_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
796 | { | |
797 | return frame_id_build (get_frame_sp (this_frame), | |
798 | get_frame_pc (this_frame)); | |
799 | } | |
800 | \f | |
801 | ||
802 | /* Support functions for frame handling. */ | |
803 | ||
804 | /* Initialize a prologue cache | |
805 | ||
806 | We build a cache, saying where registers of the prev frame can be found | |
807 | from the data so far set up in this this. | |
808 | ||
809 | We also compute a unique ID for this frame, based on the function start | |
810 | address and the stack pointer (as it will be, even if it has yet to be | |
811 | computed. | |
812 | ||
813 | STACK FORMAT | |
814 | ============ | |
815 | ||
816 | The OR1K has a falling stack frame and a simple prolog. The Stack | |
817 | pointer is R1 and the frame pointer R2. The frame base is therefore the | |
818 | address held in R2 and the stack pointer (R1) is the frame base of the | |
819 | next frame. | |
820 | ||
821 | l.addi r1,r1,-frame_size # SP now points to end of new stack frame | |
822 | ||
823 | The stack pointer may not be set up in a frameless function (e.g. a | |
824 | simple leaf function). | |
825 | ||
826 | l.sw fp_loc(r1),r2 # old FP saved in new stack frame | |
827 | l.addi r2,r1,frame_size # FP now points to base of new stack frame | |
828 | ||
829 | The frame pointer is not necessarily saved right at the end of the stack | |
830 | frame - OR1K saves enough space for any args to called functions right | |
831 | at the end (this is a difference from the Architecture Manual). | |
832 | ||
833 | l.sw lr_loc(r1),r9 # Link (return) address | |
834 | ||
835 | The link register is usally saved at fp_loc - 4. It may not be saved at | |
836 | all in a leaf function. | |
837 | ||
838 | l.sw reg_loc(r1),ry # Save any callee saved regs | |
839 | ||
840 | The offsets x for the callee saved registers generally (always?) rise in | |
841 | increments of 4, starting at fp_loc + 4. If the frame pointer is | |
842 | omitted (an option to GCC), then it may not be saved at all. There may | |
843 | be no callee saved registers. | |
844 | ||
845 | So in summary none of this may be present. However what is present | |
846 | seems always to follow this fixed order, and occur before any | |
847 | substantive code (it is possible for GCC to have more flexible | |
848 | scheduling of the prologue, but this does not seem to occur for OR1K). | |
849 | ||
850 | ANALYSIS | |
851 | ======== | |
852 | ||
853 | This prolog is used, even for -O3 with GCC. | |
854 | ||
855 | All this analysis must allow for the possibility that the PC is in the | |
856 | middle of the prologue. Data in the cache should only be set up insofar | |
857 | as it has been computed. | |
858 | ||
859 | HOWEVER. The frame_id must be created with the SP *as it will be* at | |
860 | the end of the Prologue. Otherwise a recursive call, checking the frame | |
861 | with the PC at the start address will end up with the same frame_id as | |
862 | the caller. | |
863 | ||
864 | A suite of "helper" routines are used, allowing reuse for | |
865 | or1k_skip_prologue(). | |
866 | ||
867 | Reportedly, this is only valid for frames less than 0x7fff in size. */ | |
868 | ||
869 | static struct trad_frame_cache * | |
870 | or1k_frame_cache (struct frame_info *this_frame, void **prologue_cache) | |
871 | { | |
872 | struct gdbarch *gdbarch; | |
873 | struct trad_frame_cache *info; | |
874 | ||
875 | CORE_ADDR this_pc; | |
876 | CORE_ADDR this_sp; | |
877 | CORE_ADDR this_sp_for_id; | |
878 | int frame_size = 0; | |
879 | ||
880 | CORE_ADDR start_addr; | |
881 | CORE_ADDR end_addr; | |
882 | ||
883 | if (or1k_debug) | |
884 | fprintf_unfiltered (gdb_stdlog, | |
96647014 SH |
885 | "or1k_frame_cache, prologue_cache = %s\n", |
886 | host_address_to_string (*prologue_cache)); | |
a994fec4 FJ |
887 | |
888 | /* Nothing to do if we already have this info. */ | |
889 | if (NULL != *prologue_cache) | |
890 | return (struct trad_frame_cache *) *prologue_cache; | |
891 | ||
892 | /* Get a new prologue cache and populate it with default values. */ | |
893 | info = trad_frame_cache_zalloc (this_frame); | |
894 | *prologue_cache = info; | |
895 | ||
896 | /* Find the start address of this function (which is a normal frame, even | |
897 | if the next frame is the sentinel frame) and the end of its prologue. */ | |
898 | this_pc = get_frame_pc (this_frame); | |
899 | find_pc_partial_function (this_pc, NULL, &start_addr, NULL); | |
900 | ||
901 | /* Get the stack pointer if we have one (if there's no process executing | |
902 | yet we won't have a frame. */ | |
903 | this_sp = (NULL == this_frame) ? 0 : | |
904 | get_frame_register_unsigned (this_frame, OR1K_SP_REGNUM); | |
905 | ||
906 | /* Return early if GDB couldn't find the function. */ | |
907 | if (start_addr == 0) | |
908 | { | |
909 | if (or1k_debug) | |
910 | fprintf_unfiltered (gdb_stdlog, " couldn't find function\n"); | |
911 | ||
912 | /* JPB: 28-Apr-11. This is a temporary patch, to get round GDB | |
913 | crashing right at the beginning. Build the frame ID as best we | |
914 | can. */ | |
915 | trad_frame_set_id (info, frame_id_build (this_sp, this_pc)); | |
916 | ||
917 | return info; | |
918 | } | |
919 | ||
920 | /* The default frame base of this frame (for ID purposes only - frame | |
921 | base is an overloaded term) is its stack pointer. For now we use the | |
922 | value of the SP register in this frame. However if the PC is in the | |
923 | prologue of this frame, before the SP has been set up, then the value | |
924 | will actually be that of the prev frame, and we'll need to adjust it | |
925 | later. */ | |
926 | trad_frame_set_this_base (info, this_sp); | |
927 | this_sp_for_id = this_sp; | |
928 | ||
929 | /* The default is to find the PC of the previous frame in the link | |
930 | register of this frame. This may be changed if we find the link | |
931 | register was saved on the stack. */ | |
932 | trad_frame_set_reg_realreg (info, OR1K_NPC_REGNUM, OR1K_LR_REGNUM); | |
933 | ||
934 | /* We should only examine code that is in the prologue. This is all code | |
935 | up to (but not including) end_addr. We should only populate the cache | |
936 | while the address is up to (but not including) the PC or end_addr, | |
937 | whichever is first. */ | |
938 | gdbarch = get_frame_arch (this_frame); | |
939 | end_addr = or1k_skip_prologue (gdbarch, start_addr); | |
940 | ||
941 | /* All the following analysis only occurs if we are in the prologue and | |
942 | have executed the code. Check we have a sane prologue size, and if | |
943 | zero we are frameless and can give up here. */ | |
944 | if (end_addr < start_addr) | |
38af1824 SH |
945 | error (_("end addr %s is less than start addr %s"), |
946 | paddress (gdbarch, end_addr), paddress (gdbarch, start_addr)); | |
a994fec4 FJ |
947 | |
948 | if (end_addr == start_addr) | |
949 | frame_size = 0; | |
950 | else | |
951 | { | |
952 | /* We have a frame. Look for the various components. */ | |
953 | CORE_ADDR addr = start_addr; /* Where we have got to */ | |
954 | uint32_t inst = or1k_fetch_instruction (gdbarch, addr); | |
955 | ||
956 | unsigned int ra, rb, rd; /* for instruction analysis */ | |
957 | int simm; | |
958 | ||
959 | /* Look for the new stack pointer being set up. */ | |
960 | if (or1k_analyse_l_addi (inst, &rd, &ra, &simm) | |
961 | && (OR1K_SP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) | |
962 | && (simm < 0) && (0 == (simm % 4))) | |
963 | { | |
964 | frame_size = -simm; | |
965 | addr += OR1K_INSTLEN; | |
966 | inst = or1k_fetch_instruction (gdbarch, addr); | |
967 | ||
968 | /* If the PC has not actually got to this point, then the frame | |
969 | base will be wrong, and we adjust it. | |
970 | ||
971 | If we are past this point, then we need to populate the stack | |
972 | accordingly. */ | |
973 | if (this_pc <= addr) | |
974 | { | |
975 | /* Only do if executing. */ | |
976 | if (0 != this_sp) | |
977 | { | |
978 | this_sp_for_id = this_sp + frame_size; | |
979 | trad_frame_set_this_base (info, this_sp_for_id); | |
980 | } | |
981 | } | |
982 | else | |
983 | { | |
984 | /* We are past this point, so the stack pointer of the prev | |
985 | frame is frame_size greater than the stack pointer of this | |
986 | frame. */ | |
987 | trad_frame_set_reg_value (info, OR1K_SP_REGNUM, | |
988 | this_sp + frame_size); | |
989 | } | |
990 | } | |
991 | ||
992 | /* From now on we are only populating the cache, so we stop once we | |
993 | get to either the end OR the current PC. */ | |
994 | end_addr = (this_pc < end_addr) ? this_pc : end_addr; | |
995 | ||
996 | /* Look for the frame pointer being manipulated. */ | |
997 | if ((addr < end_addr) | |
998 | && or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
999 | && (OR1K_SP_REGNUM == ra) && (OR1K_FP_REGNUM == rb) | |
1000 | && (simm >= 0) && (0 == (simm % 4))) | |
1001 | { | |
1002 | addr += OR1K_INSTLEN; | |
1003 | inst = or1k_fetch_instruction (gdbarch, addr); | |
1004 | ||
1005 | /* At this stage, we can find the frame pointer of the previous | |
1006 | frame on the stack of the current frame. */ | |
1007 | trad_frame_set_reg_addr (info, OR1K_FP_REGNUM, this_sp + simm); | |
1008 | ||
1009 | /* Look for the new frame pointer being set up. */ | |
1010 | if ((addr < end_addr) | |
1011 | && or1k_analyse_l_addi (inst, &rd, &ra, &simm) | |
1012 | && (OR1K_FP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) | |
1013 | && (simm == frame_size)) | |
1014 | { | |
1015 | addr += OR1K_INSTLEN; | |
1016 | inst = or1k_fetch_instruction (gdbarch, addr); | |
1017 | ||
1018 | /* If we have got this far, the stack pointer of the previous | |
1019 | frame is the frame pointer of this frame. */ | |
1020 | trad_frame_set_reg_realreg (info, OR1K_SP_REGNUM, | |
1021 | OR1K_FP_REGNUM); | |
1022 | } | |
1023 | } | |
1024 | ||
1025 | /* Look for the link register being saved. */ | |
1026 | if ((addr < end_addr) | |
1027 | && or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
1028 | && (OR1K_SP_REGNUM == ra) && (OR1K_LR_REGNUM == rb) | |
1029 | && (simm >= 0) && (0 == (simm % 4))) | |
1030 | { | |
1031 | addr += OR1K_INSTLEN; | |
1032 | inst = or1k_fetch_instruction (gdbarch, addr); | |
1033 | ||
1034 | /* If the link register is saved in the this frame, it holds the | |
1035 | value of the PC in the previous frame. This overwrites the | |
1036 | previous information about finding the PC in the link | |
1037 | register. */ | |
1038 | trad_frame_set_reg_addr (info, OR1K_NPC_REGNUM, this_sp + simm); | |
1039 | } | |
1040 | ||
1041 | /* Look for arguments or callee-saved register being saved. The | |
1042 | register must be one of the arguments (r3-r8) or the 10 callee | |
1043 | saved registers (r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, | |
1044 | r30). The base register must be the FP (for the args) or the SP | |
1045 | (for the callee_saved registers). */ | |
1046 | while (addr < end_addr) | |
1047 | { | |
1048 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
1049 | && (((OR1K_FP_REGNUM == ra) && or1k_is_arg_reg (rb)) | |
1050 | || ((OR1K_SP_REGNUM == ra) | |
1051 | && or1k_is_callee_saved_reg (rb))) | |
1052 | && (0 == (simm % 4))) | |
1053 | { | |
1054 | addr += OR1K_INSTLEN; | |
1055 | inst = or1k_fetch_instruction (gdbarch, addr); | |
1056 | ||
1057 | /* The register in the previous frame can be found at this | |
1058 | location in this frame. */ | |
1059 | trad_frame_set_reg_addr (info, rb, this_sp + simm); | |
1060 | } | |
1061 | else | |
1062 | break; /* Not a register save instruction. */ | |
1063 | } | |
1064 | } | |
1065 | ||
1066 | /* Build the frame ID */ | |
1067 | trad_frame_set_id (info, frame_id_build (this_sp_for_id, start_addr)); | |
1068 | ||
1069 | if (or1k_debug) | |
1070 | { | |
96647014 SH |
1071 | fprintf_unfiltered (gdb_stdlog, " this_sp_for_id = %s\n", |
1072 | paddress (gdbarch, this_sp_for_id)); | |
1073 | fprintf_unfiltered (gdb_stdlog, " start_addr = %s\n", | |
1074 | paddress (gdbarch, start_addr)); | |
a994fec4 FJ |
1075 | } |
1076 | ||
1077 | return info; | |
1078 | } | |
1079 | ||
1080 | /* Implement the this_id function for the stub unwinder. */ | |
1081 | ||
1082 | static void | |
1083 | or1k_frame_this_id (struct frame_info *this_frame, | |
1084 | void **prologue_cache, struct frame_id *this_id) | |
1085 | { | |
1086 | struct trad_frame_cache *info = or1k_frame_cache (this_frame, | |
1087 | prologue_cache); | |
1088 | ||
1089 | trad_frame_get_id (info, this_id); | |
1090 | } | |
1091 | ||
1092 | /* Implement the prev_register function for the stub unwinder. */ | |
1093 | ||
1094 | static struct value * | |
1095 | or1k_frame_prev_register (struct frame_info *this_frame, | |
1096 | void **prologue_cache, int regnum) | |
1097 | { | |
1098 | struct trad_frame_cache *info = or1k_frame_cache (this_frame, | |
1099 | prologue_cache); | |
1100 | ||
1101 | return trad_frame_get_register (info, this_frame, regnum); | |
1102 | } | |
1103 | ||
1104 | /* Data structures for the normal prologue-analysis-based unwinder. */ | |
1105 | ||
1106 | static const struct frame_unwind or1k_frame_unwind = { | |
1107 | NORMAL_FRAME, | |
1108 | default_frame_unwind_stop_reason, | |
1109 | or1k_frame_this_id, | |
1110 | or1k_frame_prev_register, | |
1111 | NULL, | |
1112 | default_frame_sniffer, | |
1113 | NULL, | |
1114 | }; | |
1115 | ||
1116 | /* Architecture initialization for OpenRISC 1000. */ | |
1117 | ||
1118 | static struct gdbarch * | |
1119 | or1k_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1120 | { | |
1121 | struct gdbarch *gdbarch; | |
1122 | struct gdbarch_tdep *tdep; | |
1123 | const struct bfd_arch_info *binfo; | |
1124 | struct tdesc_arch_data *tdesc_data = NULL; | |
1125 | const struct target_desc *tdesc = info.target_desc; | |
1126 | ||
1127 | /* Find a candidate among the list of pre-declared architectures. */ | |
1128 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1129 | if (NULL != arches) | |
1130 | return arches->gdbarch; | |
1131 | ||
1132 | /* None found, create a new architecture from the information | |
1133 | provided. Can't initialize all the target dependencies until we | |
1134 | actually know which target we are talking to, but put in some defaults | |
1135 | for now. */ | |
1136 | binfo = info.bfd_arch_info; | |
1137 | tdep = XCNEW (struct gdbarch_tdep); | |
1138 | tdep->bytes_per_word = binfo->bits_per_word / binfo->bits_per_byte; | |
1139 | tdep->bytes_per_address = binfo->bits_per_address / binfo->bits_per_byte; | |
1140 | gdbarch = gdbarch_alloc (&info, tdep); | |
1141 | ||
1142 | /* Target data types */ | |
1143 | set_gdbarch_short_bit (gdbarch, 16); | |
1144 | set_gdbarch_int_bit (gdbarch, 32); | |
1145 | set_gdbarch_long_bit (gdbarch, 32); | |
1146 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1147 | set_gdbarch_float_bit (gdbarch, 32); | |
1148 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
1149 | set_gdbarch_double_bit (gdbarch, 64); | |
1150 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1151 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1152 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
1153 | set_gdbarch_ptr_bit (gdbarch, binfo->bits_per_address); | |
1154 | set_gdbarch_addr_bit (gdbarch, binfo->bits_per_address); | |
1155 | set_gdbarch_char_signed (gdbarch, 1); | |
1156 | ||
1157 | /* Information about the target architecture */ | |
1158 | set_gdbarch_return_value (gdbarch, or1k_return_value); | |
1159 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, | |
1160 | or1k_breakpoint::kind_from_pc); | |
1161 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1162 | or1k_breakpoint::bp_from_kind); | |
1163 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
1164 | ||
1165 | /* Register architecture */ | |
1166 | set_gdbarch_num_regs (gdbarch, OR1K_NUM_REGS); | |
1167 | set_gdbarch_num_pseudo_regs (gdbarch, OR1K_NUM_PSEUDO_REGS); | |
1168 | set_gdbarch_sp_regnum (gdbarch, OR1K_SP_REGNUM); | |
1169 | set_gdbarch_pc_regnum (gdbarch, OR1K_NPC_REGNUM); | |
1170 | set_gdbarch_ps_regnum (gdbarch, OR1K_SR_REGNUM); | |
1171 | set_gdbarch_deprecated_fp_regnum (gdbarch, OR1K_FP_REGNUM); | |
1172 | ||
1173 | /* Functions to analyse frames */ | |
1174 | set_gdbarch_skip_prologue (gdbarch, or1k_skip_prologue); | |
1175 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1176 | set_gdbarch_frame_align (gdbarch, or1k_frame_align); | |
1177 | set_gdbarch_frame_red_zone_size (gdbarch, OR1K_FRAME_RED_ZONE_SIZE); | |
1178 | ||
1179 | /* Functions to access frame data */ | |
1180 | set_gdbarch_unwind_pc (gdbarch, or1k_unwind_pc); | |
1181 | set_gdbarch_unwind_sp (gdbarch, or1k_unwind_sp); | |
1182 | ||
1183 | /* Functions handling dummy frames */ | |
1184 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1185 | set_gdbarch_push_dummy_code (gdbarch, or1k_push_dummy_code); | |
1186 | set_gdbarch_push_dummy_call (gdbarch, or1k_push_dummy_call); | |
1187 | set_gdbarch_dummy_id (gdbarch, or1k_dummy_id); | |
1188 | ||
1189 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our | |
1190 | own unwinder. */ | |
1191 | dwarf2_append_unwinders (gdbarch); | |
1192 | frame_unwind_append_unwinder (gdbarch, &or1k_frame_unwind); | |
1193 | ||
1194 | /* Get a CGEN CPU descriptor for this architecture. */ | |
1195 | { | |
1196 | ||
1197 | const char *mach_name = binfo->printable_name; | |
1198 | enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG | |
1199 | ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); | |
1200 | ||
1201 | tdep->gdb_cgen_cpu_desc = | |
1202 | or1k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, | |
1203 | CGEN_CPU_OPEN_ENDIAN, endian, CGEN_CPU_OPEN_END); | |
1204 | ||
1205 | or1k_cgen_init_asm (tdep->gdb_cgen_cpu_desc); | |
1206 | } | |
1207 | ||
1208 | /* If this mach has a delay slot. */ | |
1209 | if (binfo->mach == bfd_mach_or1k) | |
1210 | set_gdbarch_single_step_through_delay (gdbarch, | |
1211 | or1k_single_step_through_delay); | |
1212 | ||
1213 | if (!tdesc_has_registers (info.target_desc)) | |
1214 | /* Pick a default target description. */ | |
1215 | tdesc = tdesc_or1k; | |
1216 | ||
1217 | /* Check any target description for validity. */ | |
1218 | if (tdesc_has_registers (tdesc)) | |
1219 | { | |
1220 | const struct tdesc_feature *feature; | |
1221 | int valid_p; | |
1222 | int i; | |
1223 | ||
1224 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.or1k.group0"); | |
1225 | if (feature == NULL) | |
1226 | return NULL; | |
1227 | ||
1228 | tdesc_data = tdesc_data_alloc (); | |
1229 | ||
1230 | valid_p = 1; | |
1231 | ||
1232 | for (i = 0; i < OR1K_NUM_REGS; i++) | |
1233 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
1234 | or1k_reg_names[i]); | |
1235 | ||
1236 | if (!valid_p) | |
1237 | { | |
1238 | tdesc_data_cleanup (tdesc_data); | |
1239 | return NULL; | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | if (tdesc_data != NULL) | |
1244 | { | |
1245 | /* If we are using tdesc, register our own reggroups, otherwise we | |
1246 | will used the defaults. */ | |
1247 | reggroup_add (gdbarch, general_reggroup); | |
1248 | reggroup_add (gdbarch, system_reggroup); | |
1249 | reggroup_add (gdbarch, float_reggroup); | |
1250 | reggroup_add (gdbarch, vector_reggroup); | |
1251 | reggroup_add (gdbarch, all_reggroup); | |
1252 | reggroup_add (gdbarch, save_reggroup); | |
1253 | reggroup_add (gdbarch, restore_reggroup); | |
1254 | ||
1255 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
1256 | } | |
1257 | ||
1258 | return gdbarch; | |
1259 | } | |
1260 | ||
1261 | /* Dump the target specific data for this architecture. */ | |
1262 | ||
1263 | static void | |
1264 | or1k_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
1265 | { | |
1266 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1267 | ||
1268 | if (NULL == tdep) | |
1269 | return; /* Nothing to report */ | |
1270 | ||
1271 | fprintf_unfiltered (file, "or1k_dump_tdep: %d bytes per word\n", | |
1272 | tdep->bytes_per_word); | |
1273 | fprintf_unfiltered (file, "or1k_dump_tdep: %d bytes per address\n", | |
1274 | tdep->bytes_per_address); | |
1275 | } | |
1276 | \f | |
1277 | ||
1278 | void | |
1279 | _initialize_or1k_tdep (void) | |
1280 | { | |
1281 | /* Register this architecture. */ | |
1282 | gdbarch_register (bfd_arch_or1k, or1k_gdbarch_init, or1k_dump_tdep); | |
1283 | ||
1284 | initialize_tdesc_or1k (); | |
1285 | ||
1286 | /* Debugging flag. */ | |
1287 | add_setshow_boolean_cmd ("or1k", class_maintenance, &or1k_debug, | |
1288 | _("Set OpenRISC debugging."), | |
1289 | _("Show OpenRISC debugging."), | |
1290 | _("When on, OpenRISC specific debugging is enabled."), | |
1291 | NULL, | |
1292 | show_or1k_debug, | |
1293 | &setdebuglist, &showdebuglist); | |
1294 | } |