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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
e2882c85 | 3 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
c877c8e6 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
19 | |
20 | #include "defs.h" | |
76727919 | 21 | #include "observable.h" |
c877c8e6 KB |
22 | #include "frame.h" |
23 | #include "inferior.h" | |
6ffbb7ab | 24 | #include "gdbthread.h" |
c877c8e6 | 25 | #include "gdbcore.h" |
4e052eda | 26 | #include "regcache.h" |
1d75a658 | 27 | #include "regset.h" |
10d6c8cd DJ |
28 | #include "target.h" |
29 | #include "linux-nat.h" | |
c877c8e6 | 30 | #include <sys/types.h> |
c877c8e6 KB |
31 | #include <signal.h> |
32 | #include <sys/user.h> | |
33 | #include <sys/ioctl.h> | |
2555fe1a | 34 | #include "gdb_wait.h" |
c877c8e6 KB |
35 | #include <fcntl.h> |
36 | #include <sys/procfs.h> | |
5826e159 | 37 | #include "nat/gdb_ptrace.h" |
bcc0c096 | 38 | #include "inf-ptrace.h" |
c877c8e6 | 39 | |
0df8b418 | 40 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 41 | #include "gregset.h" |
16333c4f | 42 | #include "ppc-tdep.h" |
7284e1be UW |
43 | #include "ppc-linux-tdep.h" |
44 | ||
b7622095 LM |
45 | /* Required when using the AUXV. */ |
46 | #include "elf/common.h" | |
47 | #include "auxv.h" | |
48 | ||
bd64614e PFC |
49 | #include "arch/ppc-linux-common.h" |
50 | #include "arch/ppc-linux-tdesc.h" | |
514c5338 | 51 | #include "nat/ppc-linux.h" |
01904826 | 52 | |
6ffbb7ab | 53 | /* Similarly for the hardware watchpoint support. These requests are used |
926bf92d | 54 | when the PowerPC HWDEBUG ptrace interface is not available. */ |
e0d24f8d WZ |
55 | #ifndef PTRACE_GET_DEBUGREG |
56 | #define PTRACE_GET_DEBUGREG 25 | |
57 | #endif | |
58 | #ifndef PTRACE_SET_DEBUGREG | |
59 | #define PTRACE_SET_DEBUGREG 26 | |
60 | #endif | |
61 | #ifndef PTRACE_GETSIGINFO | |
62 | #define PTRACE_GETSIGINFO 0x4202 | |
63 | #endif | |
01904826 | 64 | |
926bf92d UW |
65 | /* These requests are used when the PowerPC HWDEBUG ptrace interface is |
66 | available. It exposes the debug facilities of PowerPC processors, as well | |
67 | as additional features of BookE processors, such as ranged breakpoints and | |
68 | watchpoints and hardware-accelerated condition evaluation. */ | |
6ffbb7ab TJB |
69 | #ifndef PPC_PTRACE_GETHWDBGINFO |
70 | ||
926bf92d UW |
71 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG |
72 | ptrace interface is not present in ptrace.h, so we'll have to pretty much | |
73 | include it all here so that the code at least compiles on older systems. */ | |
6ffbb7ab TJB |
74 | #define PPC_PTRACE_GETHWDBGINFO 0x89 |
75 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
76 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
77 | ||
78 | struct ppc_debug_info | |
79 | { | |
0df8b418 | 80 | uint32_t version; /* Only version 1 exists to date. */ |
6ffbb7ab TJB |
81 | uint32_t num_instruction_bps; |
82 | uint32_t num_data_bps; | |
83 | uint32_t num_condition_regs; | |
84 | uint32_t data_bp_alignment; | |
0df8b418 | 85 | uint32_t sizeof_condition; /* size of the DVC register. */ |
6ffbb7ab TJB |
86 | uint64_t features; |
87 | }; | |
88 | ||
89 | /* Features will have bits indicating whether there is support for: */ | |
90 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
91 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
92 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
93 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
94 | ||
95 | struct ppc_hw_breakpoint | |
96 | { | |
97 | uint32_t version; /* currently, version must be 1 */ | |
98 | uint32_t trigger_type; /* only some combinations allowed */ | |
99 | uint32_t addr_mode; /* address match mode */ | |
100 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
101 | uint64_t addr; /* break/watchpoint address */ | |
102 | uint64_t addr2; /* range end or mask */ | |
103 | uint64_t condition_value; /* contents of the DVC register */ | |
104 | }; | |
105 | ||
106 | /* Trigger type. */ | |
107 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
108 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
109 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
110 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
111 | ||
112 | /* Address mode. */ | |
113 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
114 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
115 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
116 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
117 | ||
118 | /* Condition mode. */ | |
119 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
120 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
121 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
122 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
123 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
124 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
125 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
126 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
127 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) | |
128 | #endif /* PPC_PTRACE_GETHWDBGINFO */ | |
129 | ||
e23b9d6e UW |
130 | /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider |
131 | watchpoint (up to 512 bytes). */ | |
132 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR | |
133 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | |
134 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */ | |
6ffbb7ab | 135 | |
1dfe79e8 SDJ |
136 | /* Similarly for the general-purpose (gp0 -- gp31) |
137 | and floating-point registers (fp0 -- fp31). */ | |
138 | #ifndef PTRACE_GETREGS | |
139 | #define PTRACE_GETREGS 12 | |
140 | #endif | |
141 | #ifndef PTRACE_SETREGS | |
142 | #define PTRACE_SETREGS 13 | |
143 | #endif | |
144 | #ifndef PTRACE_GETFPREGS | |
145 | #define PTRACE_GETFPREGS 14 | |
146 | #endif | |
147 | #ifndef PTRACE_SETFPREGS | |
148 | #define PTRACE_SETFPREGS 15 | |
149 | #endif | |
150 | ||
9abe5450 EZ |
151 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
152 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
153 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
154 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
155 | flat array of chars, so that it is easier to manipulate for gdb. | |
156 | ||
157 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
158 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 159 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
160 | Appended to this there is space for the VRSAVE register: 4 bytes. |
161 | Even though this vrsave register is not included in the regset | |
162 | typedef, it is handled by the ptrace requests. | |
163 | ||
9abe5450 EZ |
164 | The layout is like this (where x is the actual value of the vscr reg): */ |
165 | ||
166 | /* *INDENT-OFF* */ | |
167 | /* | |
1d75a658 | 168 | Big-Endian: |
9abe5450 EZ |
169 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| |
170 | <-------> <-------><-------><-> | |
171 | VR0 VR31 VSCR VRSAVE | |
1d75a658 PFC |
172 | Little-Endian: |
173 | |.|.|.|.|.....|.|.|.|.||X|.|.|.||.| | |
174 | <-------> <-------><-------><-> | |
175 | VR0 VR31 VSCR VRSAVE | |
9abe5450 EZ |
176 | */ |
177 | /* *INDENT-ON* */ | |
178 | ||
d078308a | 179 | typedef char gdb_vrregset_t[PPC_LINUX_SIZEOF_VRREGSET]; |
9abe5450 | 180 | |
604c2f83 LM |
181 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
182 | with the existing FPR and VMX registers. | |
183 | ||
184 | VSR doubleword 0 VSR doubleword 1 | |
185 | ---------------------------------------------------------------- | |
186 | VSR[0] | FPR[0] | | | |
187 | ---------------------------------------------------------------- | |
188 | VSR[1] | FPR[1] | | | |
189 | ---------------------------------------------------------------- | |
190 | | ... | | | |
191 | | ... | | | |
192 | ---------------------------------------------------------------- | |
193 | VSR[30] | FPR[30] | | | |
194 | ---------------------------------------------------------------- | |
195 | VSR[31] | FPR[31] | | | |
196 | ---------------------------------------------------------------- | |
197 | VSR[32] | VR[0] | | |
198 | ---------------------------------------------------------------- | |
199 | VSR[33] | VR[1] | | |
200 | ---------------------------------------------------------------- | |
201 | | ... | | |
202 | | ... | | |
203 | ---------------------------------------------------------------- | |
204 | VSR[62] | VR[30] | | |
205 | ---------------------------------------------------------------- | |
206 | VSR[63] | VR[31] | | |
207 | ---------------------------------------------------------------- | |
208 | ||
209 | VSX has 64 128bit registers. The first 32 registers overlap with | |
210 | the FP registers (doubleword 0) and hence extend them with additional | |
211 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
212 | registers. */ | |
d078308a | 213 | typedef char gdb_vsxregset_t[PPC_LINUX_SIZEOF_VSXREGSET]; |
01904826 | 214 | |
b021a221 | 215 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 216 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
217 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
218 | ptrace calls only access the lower half of each register, to allow | |
219 | them to behave the same way they do on non-SPE systems. There's a | |
220 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
221 | read and write the top halves of all the general-purpose registers | |
222 | at once, along with some SPE-specific registers. | |
01904826 JB |
223 | |
224 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 225 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 226 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
227 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
228 | bottom halves together. | |
01904826 JB |
229 | |
230 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
231 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
232 | struct gdb_evrregset_t | |
233 | { | |
234 | unsigned long evr[32]; | |
235 | unsigned long long acc; | |
236 | unsigned long spefscr; | |
237 | }; | |
238 | ||
604c2f83 LM |
239 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
240 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
241 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
242 | gotten an error. Note that VSX registers 32 through 63 overlap | |
243 | with VR registers 0 through 31. */ | |
244 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
245 | |
246 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
247 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
248 | registers. Zero if we've tried one of them and gotten an | |
249 | error. */ | |
9abe5450 EZ |
250 | int have_ptrace_getvrregs = 1; |
251 | ||
01904826 JB |
252 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
253 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
254 | registers. Zero if we've tried one of them and gotten an | |
255 | error. */ | |
256 | int have_ptrace_getsetevrregs = 1; | |
257 | ||
1dfe79e8 SDJ |
258 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
259 | PTRACE_SETREGS requests, for reading and writing the | |
260 | general-purpose registers. Zero if we've tried one of | |
261 | them and gotten an error. */ | |
262 | int have_ptrace_getsetregs = 1; | |
263 | ||
264 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
265 | PTRACE_SETFPREGS requests, for reading and writing the | |
266 | floating-pointers registers. Zero if we've tried one of | |
267 | them and gotten an error. */ | |
268 | int have_ptrace_getsetfpregs = 1; | |
269 | ||
f6ac5f3d PA |
270 | struct ppc_linux_nat_target final : public linux_nat_target |
271 | { | |
272 | /* Add our register access methods. */ | |
273 | void fetch_registers (struct regcache *, int) override; | |
274 | void store_registers (struct regcache *, int) override; | |
275 | ||
276 | /* Add our breakpoint/watchpoint methods. */ | |
277 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
278 | ||
279 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
280 | override; | |
281 | ||
282 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
283 | override; | |
284 | ||
285 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
286 | ||
287 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
288 | struct expression *) override; | |
289 | ||
290 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
291 | struct expression *) override; | |
292 | ||
293 | int insert_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
294 | override; | |
295 | ||
296 | int remove_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
297 | override; | |
298 | ||
57810aa7 | 299 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 300 | |
57810aa7 | 301 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 302 | |
57810aa7 | 303 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d | 304 | |
57810aa7 | 305 | bool can_accel_watchpoint_condition (CORE_ADDR, int, int, struct expression *) |
f6ac5f3d PA |
306 | override; |
307 | ||
308 | int masked_watch_num_registers (CORE_ADDR, CORE_ADDR) override; | |
309 | ||
310 | int ranged_break_num_registers () override; | |
311 | ||
312 | const struct target_desc *read_description () override; | |
313 | ||
314 | int auxv_parse (gdb_byte **readptr, | |
315 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
316 | override; | |
135340af PA |
317 | |
318 | /* Override linux_nat_target low methods. */ | |
319 | void low_new_thread (struct lwp_info *lp) override; | |
f6ac5f3d PA |
320 | }; |
321 | ||
322 | static ppc_linux_nat_target the_ppc_linux_nat_target; | |
323 | ||
16333c4f EZ |
324 | /* *INDENT-OFF* */ |
325 | /* registers layout, as presented by the ptrace interface: | |
326 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
327 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
328 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
329 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
330 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
331 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
332 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
333 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
334 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
335 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
336 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
337 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f EZ |
338 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
339 | /* *INDENT_ON * */ | |
c877c8e6 | 340 | |
45229ea4 | 341 | static int |
e101270f | 342 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 343 | { |
16333c4f | 344 | int u_addr = -1; |
e101270f | 345 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
346 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
347 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 348 | int wordsize = sizeof (long); |
16333c4f | 349 | |
0df8b418 | 350 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
351 | if (regno >= tdep->ppc_gp0_regnum |
352 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 353 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 354 | |
49ff75ad JB |
355 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
356 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
357 | slot each in 64-bit interface. */ | |
383f0f5b JB |
358 | if (tdep->ppc_fp0_regnum >= 0 |
359 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
360 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
361 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 362 | |
0df8b418 | 363 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 364 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 365 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 366 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 367 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 368 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 369 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 370 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 371 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 372 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 373 | u_addr = PT_CTR * wordsize; |
f8c59253 | 374 | #ifdef PT_MQ |
dc5cfeb6 | 375 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 376 | u_addr = PT_MQ * wordsize; |
f8c59253 | 377 | #endif |
dc5cfeb6 | 378 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 379 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
380 | if (regno == PPC_ORIG_R3_REGNUM) |
381 | u_addr = PT_ORIG_R3 * wordsize; | |
382 | if (regno == PPC_TRAP_REGNUM) | |
383 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
384 | if (tdep->ppc_fpscr_regnum >= 0 |
385 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
386 | { |
387 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
388 | kernel headers incorrectly contained the 32-bit definition of | |
389 | PT_FPSCR. For the 32-bit definition, floating-point | |
390 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 391 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
392 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
393 | hence no adjustment is necessary. Hack around this. */ | |
394 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
395 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
396 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
397 | slot and not just its second word. The PT_FPSCR supplied when | |
398 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
399 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
400 | && PT_FPSCR == (48 + 2*32 + 1)) | |
401 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
402 | else |
403 | u_addr = PT_FPSCR * wordsize; | |
404 | } | |
16333c4f | 405 | return u_addr; |
c877c8e6 KB |
406 | } |
407 | ||
604c2f83 LM |
408 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
409 | registers set mechanism, as opposed to the interface for all the | |
410 | other registers, that stores/fetches each register individually. */ | |
411 | static void | |
2c3305f6 | 412 | fetch_vsx_registers (struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
413 | { |
414 | int ret; | |
415 | gdb_vsxregset_t regs; | |
2c3305f6 | 416 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 LM |
417 | |
418 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
419 | if (ret < 0) | |
420 | { | |
421 | if (errno == EIO) | |
422 | { | |
423 | have_ptrace_getsetvsxregs = 0; | |
424 | return; | |
425 | } | |
2c3305f6 | 426 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
427 | } |
428 | ||
2c3305f6 PFC |
429 | vsxregset->supply_regset (vsxregset, regcache, regno, ®s, |
430 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
431 | } |
432 | ||
9abe5450 EZ |
433 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
434 | registers set mechanism, as opposed to the interface for all the | |
435 | other registers, that stores/fetches each register individually. */ | |
436 | static void | |
1d75a658 PFC |
437 | fetch_altivec_registers (struct regcache *regcache, int tid, |
438 | int regno) | |
9abe5450 EZ |
439 | { |
440 | int ret; | |
9abe5450 | 441 | gdb_vrregset_t regs; |
ac7936df | 442 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 443 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
444 | |
445 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
446 | if (ret < 0) | |
447 | { | |
448 | if (errno == EIO) | |
449 | { | |
450 | have_ptrace_getvrregs = 0; | |
451 | return; | |
452 | } | |
1d75a658 | 453 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 454 | } |
1d75a658 PFC |
455 | |
456 | vrregset->supply_regset (vrregset, regcache, regno, ®s, | |
457 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
458 | } |
459 | ||
01904826 JB |
460 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
461 | SPE-specific registers, and place the results in EVRREGSET. If we | |
462 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
463 | zeros. | |
464 | ||
465 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
466 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
467 | set_spe_registers. */ | |
468 | static void | |
469 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
470 | { | |
471 | if (have_ptrace_getsetevrregs) | |
472 | { | |
473 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
474 | return; | |
475 | else | |
476 | { | |
477 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
478 | we just return zeros. */ | |
479 | if (errno == EIO) | |
480 | have_ptrace_getsetevrregs = 0; | |
481 | else | |
482 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 483 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
484 | } |
485 | } | |
486 | ||
487 | memset (evrregset, 0, sizeof (*evrregset)); | |
488 | } | |
489 | ||
6ced10dd JB |
490 | /* Supply values from TID for SPE-specific raw registers: the upper |
491 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
492 | be the number of an upper half register, acc, spefscr, or -1 to | |
493 | supply the values of all registers. */ | |
01904826 | 494 | static void |
56be3814 | 495 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 496 | { |
ac7936df | 497 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 498 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
499 | struct gdb_evrregset_t evrregs; |
500 | ||
6ced10dd | 501 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 502 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 503 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 504 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 505 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 506 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 507 | |
01904826 JB |
508 | get_spe_registers (tid, &evrregs); |
509 | ||
6ced10dd | 510 | if (regno == -1) |
01904826 | 511 | { |
6ced10dd JB |
512 | int i; |
513 | ||
514 | for (i = 0; i < ppc_num_gprs; i++) | |
73e1c03f | 515 | regcache->raw_supply (tdep->ppc_ev0_upper_regnum + i, &evrregs.evr[i]); |
01904826 | 516 | } |
6ced10dd JB |
517 | else if (tdep->ppc_ev0_upper_regnum <= regno |
518 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
73e1c03f SM |
519 | regcache->raw_supply (regno, |
520 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
521 | |
522 | if (regno == -1 | |
523 | || regno == tdep->ppc_acc_regnum) | |
73e1c03f | 524 | regcache->raw_supply (tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
525 | |
526 | if (regno == -1 | |
527 | || regno == tdep->ppc_spefscr_regnum) | |
73e1c03f | 528 | regcache->raw_supply (tdep->ppc_spefscr_regnum, &evrregs.spefscr); |
01904826 JB |
529 | } |
530 | ||
45229ea4 | 531 | static void |
56be3814 | 532 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 533 | { |
ac7936df | 534 | struct gdbarch *gdbarch = regcache->arch (); |
45229ea4 | 535 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 536 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 537 | int bytes_transferred; |
0f068fb5 | 538 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 539 | |
be8626e0 | 540 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
541 | { |
542 | /* If this is the first time through, or if it is not the first | |
543 | time through, and we have comfirmed that there is kernel | |
544 | support for such a ptrace request, then go and fetch the | |
545 | register. */ | |
546 | if (have_ptrace_getvrregs) | |
547 | { | |
1d75a658 | 548 | fetch_altivec_registers (regcache, tid, regno); |
9abe5450 EZ |
549 | return; |
550 | } | |
551 | /* If we have discovered that there is no ptrace support for | |
552 | AltiVec registers, fall through and return zeroes, because | |
553 | regaddr will be -1 in this case. */ | |
554 | } | |
604c2f83 LM |
555 | if (vsx_register_p (gdbarch, regno)) |
556 | { | |
557 | if (have_ptrace_getsetvsxregs) | |
558 | { | |
2c3305f6 | 559 | fetch_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
560 | return; |
561 | } | |
562 | } | |
be8626e0 | 563 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 564 | { |
56be3814 | 565 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
566 | return; |
567 | } | |
9abe5450 | 568 | |
45229ea4 EZ |
569 | if (regaddr == -1) |
570 | { | |
40a6adc1 | 571 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
73e1c03f | 572 | regcache->raw_supply (regno, buf); |
45229ea4 EZ |
573 | return; |
574 | } | |
575 | ||
411cb3f9 | 576 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
577 | 32-bit platform, 64-bit floating-point registers will require two |
578 | transfers. */ | |
4a19ea35 | 579 | for (bytes_transferred = 0; |
40a6adc1 | 580 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 581 | bytes_transferred += sizeof (long)) |
45229ea4 | 582 | { |
11fde611 JK |
583 | long l; |
584 | ||
45229ea4 | 585 | errno = 0; |
11fde611 | 586 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 587 | regaddr += sizeof (long); |
45229ea4 EZ |
588 | if (errno != 0) |
589 | { | |
bc97b3ba | 590 | char message[128]; |
8c042590 PM |
591 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
592 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 593 | perror_with_name (message); |
45229ea4 | 594 | } |
11fde611 | 595 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 596 | } |
56d0d96a | 597 | |
4a19ea35 JB |
598 | /* Now supply the register. Keep in mind that the regcache's idea |
599 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 600 | (long). */ |
40a6adc1 | 601 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
602 | { |
603 | /* Little-endian values are always found at the left end of the | |
604 | bytes transferred. */ | |
73e1c03f | 605 | regcache->raw_supply (regno, buf); |
4a19ea35 | 606 | } |
40a6adc1 | 607 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
608 | { |
609 | /* Big-endian values are found at the right end of the bytes | |
610 | transferred. */ | |
40a6adc1 | 611 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
73e1c03f | 612 | regcache->raw_supply (regno, buf + padding); |
4a19ea35 JB |
613 | } |
614 | else | |
a44bddec | 615 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 616 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 617 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
618 | } |
619 | ||
1dfe79e8 SDJ |
620 | /* This function actually issues the request to ptrace, telling |
621 | it to get all general-purpose registers and put them into the | |
622 | specified regset. | |
623 | ||
624 | If the ptrace request does not exist, this function returns 0 | |
625 | and properly sets the have_ptrace_* flag. If the request fails, | |
626 | this function calls perror_with_name. Otherwise, if the request | |
627 | succeeds, then the regcache gets filled and 1 is returned. */ | |
628 | static int | |
629 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
630 | { | |
1dfe79e8 SDJ |
631 | gdb_gregset_t gregset; |
632 | ||
633 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
634 | { | |
635 | if (errno == EIO) | |
636 | { | |
637 | have_ptrace_getsetregs = 0; | |
638 | return 0; | |
639 | } | |
640 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
641 | } | |
642 | ||
643 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
644 | ||
645 | return 1; | |
646 | } | |
647 | ||
648 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
649 | responsible for verifying if this target has the ptrace request | |
650 | that can be used to fetch all general-purpose registers at one | |
651 | shot. If it doesn't, then we should fetch them using the | |
652 | old-fashioned way, which is to iterate over the registers and | |
653 | request them one by one. */ | |
654 | static void | |
655 | fetch_gp_regs (struct regcache *regcache, int tid) | |
656 | { | |
ac7936df | 657 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
658 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
659 | int i; | |
660 | ||
661 | if (have_ptrace_getsetregs) | |
662 | if (fetch_all_gp_regs (regcache, tid)) | |
663 | return; | |
664 | ||
665 | /* If we've hit this point, it doesn't really matter which | |
666 | architecture we are using. We just need to read the | |
667 | registers in the "old-fashioned way". */ | |
668 | for (i = 0; i < ppc_num_gprs; i++) | |
669 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
670 | } | |
671 | ||
672 | /* This function actually issues the request to ptrace, telling | |
673 | it to get all floating-point registers and put them into the | |
674 | specified regset. | |
675 | ||
676 | If the ptrace request does not exist, this function returns 0 | |
677 | and properly sets the have_ptrace_* flag. If the request fails, | |
678 | this function calls perror_with_name. Otherwise, if the request | |
679 | succeeds, then the regcache gets filled and 1 is returned. */ | |
680 | static int | |
681 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
682 | { | |
683 | gdb_fpregset_t fpregs; | |
684 | ||
685 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
686 | { | |
687 | if (errno == EIO) | |
688 | { | |
689 | have_ptrace_getsetfpregs = 0; | |
690 | return 0; | |
691 | } | |
692 | perror_with_name (_("Couldn't get floating-point registers.")); | |
693 | } | |
694 | ||
695 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
696 | ||
697 | return 1; | |
698 | } | |
699 | ||
700 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
701 | responsible for verifying if this target has the ptrace request | |
702 | that can be used to fetch all floating-point registers at one | |
703 | shot. If it doesn't, then we should fetch them using the | |
704 | old-fashioned way, which is to iterate over the registers and | |
705 | request them one by one. */ | |
706 | static void | |
707 | fetch_fp_regs (struct regcache *regcache, int tid) | |
708 | { | |
ac7936df | 709 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
710 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
711 | int i; | |
712 | ||
713 | if (have_ptrace_getsetfpregs) | |
714 | if (fetch_all_fp_regs (regcache, tid)) | |
715 | return; | |
716 | ||
717 | /* If we've hit this point, it doesn't really matter which | |
718 | architecture we are using. We just need to read the | |
719 | registers in the "old-fashioned way". */ | |
720 | for (i = 0; i < ppc_num_fprs; i++) | |
721 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
722 | } | |
723 | ||
45229ea4 | 724 | static void |
56be3814 | 725 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 | 726 | { |
ac7936df | 727 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 728 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9abe5450 | 729 | |
1dfe79e8 | 730 | fetch_gp_regs (regcache, tid); |
32b99774 | 731 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 732 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 733 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 734 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 735 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 736 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 737 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 738 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 739 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 740 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 741 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 742 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 743 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 744 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 745 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
746 | if (ppc_linux_trap_reg_p (gdbarch)) |
747 | { | |
748 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
749 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
750 | } | |
32b99774 | 751 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 752 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
753 | if (have_ptrace_getvrregs) |
754 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 755 | fetch_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
756 | if (have_ptrace_getsetvsxregs) |
757 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 758 | fetch_vsx_registers (regcache, tid, -1); |
6ced10dd | 759 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 760 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
761 | } |
762 | ||
763 | /* Fetch registers from the child process. Fetch all registers if | |
764 | regno == -1, otherwise fetch all general registers or all floating | |
765 | point registers depending upon the value of regno. */ | |
f6ac5f3d PA |
766 | void |
767 | ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
45229ea4 | 768 | { |
222312d3 | 769 | pid_t tid = get_ptrace_pid (regcache->ptid ()); |
05f13b9c | 770 | |
9abe5450 | 771 | if (regno == -1) |
56be3814 | 772 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 773 | else |
56be3814 | 774 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
775 | } |
776 | ||
604c2f83 | 777 | static void |
2c3305f6 | 778 | store_vsx_registers (const struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
779 | { |
780 | int ret; | |
781 | gdb_vsxregset_t regs; | |
2c3305f6 | 782 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 | 783 | |
9fe70b4f | 784 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
785 | if (ret < 0) |
786 | { | |
787 | if (errno == EIO) | |
788 | { | |
789 | have_ptrace_getsetvsxregs = 0; | |
790 | return; | |
791 | } | |
2c3305f6 | 792 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
793 | } |
794 | ||
2c3305f6 PFC |
795 | vsxregset->collect_regset (vsxregset, regcache, regno, ®s, |
796 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
797 | |
798 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
799 | if (ret < 0) | |
2c3305f6 | 800 | perror_with_name (_("Unable to store VSX registers")); |
604c2f83 LM |
801 | } |
802 | ||
9abe5450 | 803 | static void |
1d75a658 PFC |
804 | store_altivec_registers (const struct regcache *regcache, int tid, |
805 | int regno) | |
9abe5450 EZ |
806 | { |
807 | int ret; | |
9abe5450 | 808 | gdb_vrregset_t regs; |
ac7936df | 809 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 810 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
811 | |
812 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
813 | if (ret < 0) | |
814 | { | |
815 | if (errno == EIO) | |
816 | { | |
817 | have_ptrace_getvrregs = 0; | |
818 | return; | |
819 | } | |
1d75a658 | 820 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 EZ |
821 | } |
822 | ||
1d75a658 PFC |
823 | vrregset->collect_regset (vrregset, regcache, regno, ®s, |
824 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
825 | |
826 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
827 | if (ret < 0) | |
1d75a658 | 828 | perror_with_name (_("Unable to store AltiVec registers")); |
9abe5450 EZ |
829 | } |
830 | ||
01904826 JB |
831 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
832 | general-purpose registers and its SPE-specific registers to the | |
833 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
834 | nothing. | |
835 | ||
836 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
837 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
838 | get_spe_registers. */ | |
839 | static void | |
840 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
841 | { | |
842 | if (have_ptrace_getsetevrregs) | |
843 | { | |
844 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
845 | return; | |
846 | else | |
847 | { | |
848 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
849 | supported; we fail silently, and don't try the call | |
850 | again. */ | |
851 | if (errno == EIO) | |
852 | have_ptrace_getsetevrregs = 0; | |
853 | else | |
854 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 855 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
856 | } |
857 | } | |
858 | } | |
859 | ||
6ced10dd JB |
860 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
861 | If REGNO is -1, write the values of all the SPE-specific | |
862 | registers. */ | |
01904826 | 863 | static void |
56be3814 | 864 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 865 | { |
ac7936df | 866 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 867 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
868 | struct gdb_evrregset_t evrregs; |
869 | ||
6ced10dd | 870 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 871 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 872 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 873 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 874 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 875 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 876 | |
6ced10dd JB |
877 | if (regno == -1) |
878 | /* Since we're going to write out every register, the code below | |
879 | should store to every field of evrregs; if that doesn't happen, | |
880 | make it obvious by initializing it with suspicious values. */ | |
881 | memset (&evrregs, 42, sizeof (evrregs)); | |
882 | else | |
883 | /* We can only read and write the entire EVR register set at a | |
884 | time, so to write just a single register, we do a | |
885 | read-modify-write maneuver. */ | |
886 | get_spe_registers (tid, &evrregs); | |
887 | ||
888 | if (regno == -1) | |
01904826 | 889 | { |
6ced10dd JB |
890 | int i; |
891 | ||
892 | for (i = 0; i < ppc_num_gprs; i++) | |
34a79281 SM |
893 | regcache->raw_collect (tdep->ppc_ev0_upper_regnum + i, |
894 | &evrregs.evr[i]); | |
01904826 | 895 | } |
6ced10dd JB |
896 | else if (tdep->ppc_ev0_upper_regnum <= regno |
897 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
34a79281 SM |
898 | regcache->raw_collect (regno, |
899 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
900 | |
901 | if (regno == -1 | |
902 | || regno == tdep->ppc_acc_regnum) | |
34a79281 SM |
903 | regcache->raw_collect (tdep->ppc_acc_regnum, |
904 | &evrregs.acc); | |
6ced10dd JB |
905 | |
906 | if (regno == -1 | |
907 | || regno == tdep->ppc_spefscr_regnum) | |
34a79281 SM |
908 | regcache->raw_collect (tdep->ppc_spefscr_regnum, |
909 | &evrregs.spefscr); | |
01904826 JB |
910 | |
911 | /* Write back the modified register set. */ | |
912 | set_spe_registers (tid, &evrregs); | |
913 | } | |
914 | ||
45229ea4 | 915 | static void |
56be3814 | 916 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 917 | { |
ac7936df | 918 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 919 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
45229ea4 | 920 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 921 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 922 | int i; |
4a19ea35 | 923 | size_t bytes_to_transfer; |
0f068fb5 | 924 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 925 | |
be8626e0 | 926 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 927 | { |
1d75a658 | 928 | store_altivec_registers (regcache, tid, regno); |
45229ea4 EZ |
929 | return; |
930 | } | |
604c2f83 LM |
931 | if (vsx_register_p (gdbarch, regno)) |
932 | { | |
2c3305f6 | 933 | store_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
934 | return; |
935 | } | |
be8626e0 | 936 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 937 | { |
56be3814 | 938 | store_spe_register (regcache, tid, regno); |
01904826 JB |
939 | return; |
940 | } | |
45229ea4 | 941 | |
9abe5450 EZ |
942 | if (regaddr == -1) |
943 | return; | |
944 | ||
4a19ea35 JB |
945 | /* First collect the register. Keep in mind that the regcache's |
946 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 947 | (long). */ |
56d0d96a | 948 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
949 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
950 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
951 | { |
952 | /* Little-endian values always sit at the left end of the buffer. */ | |
34a79281 | 953 | regcache->raw_collect (regno, buf); |
4a19ea35 | 954 | } |
40a6adc1 | 955 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
956 | { |
957 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 958 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
34a79281 | 959 | regcache->raw_collect (regno, buf + padding); |
4a19ea35 JB |
960 | } |
961 | ||
411cb3f9 | 962 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 963 | { |
11fde611 JK |
964 | long l; |
965 | ||
966 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 967 | errno = 0; |
11fde611 | 968 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 969 | regaddr += sizeof (long); |
e3f36dbd KB |
970 | |
971 | if (errno == EIO | |
7284e1be UW |
972 | && (regno == tdep->ppc_fpscr_regnum |
973 | || regno == PPC_ORIG_R3_REGNUM | |
974 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 975 | { |
7284e1be UW |
976 | /* Some older kernel versions don't allow fpscr, orig_r3 |
977 | or trap to be written. */ | |
e3f36dbd KB |
978 | continue; |
979 | } | |
980 | ||
45229ea4 EZ |
981 | if (errno != 0) |
982 | { | |
bc97b3ba | 983 | char message[128]; |
8c042590 PM |
984 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
985 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 986 | perror_with_name (message); |
45229ea4 EZ |
987 | } |
988 | } | |
989 | } | |
990 | ||
1dfe79e8 SDJ |
991 | /* This function actually issues the request to ptrace, telling |
992 | it to store all general-purpose registers present in the specified | |
993 | regset. | |
994 | ||
995 | If the ptrace request does not exist, this function returns 0 | |
996 | and properly sets the have_ptrace_* flag. If the request fails, | |
997 | this function calls perror_with_name. Otherwise, if the request | |
998 | succeeds, then the regcache is stored and 1 is returned. */ | |
999 | static int | |
1000 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1001 | { | |
1dfe79e8 SDJ |
1002 | gdb_gregset_t gregset; |
1003 | ||
1004 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1005 | { | |
1006 | if (errno == EIO) | |
1007 | { | |
1008 | have_ptrace_getsetregs = 0; | |
1009 | return 0; | |
1010 | } | |
1011 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1012 | } | |
1013 | ||
1014 | fill_gregset (regcache, &gregset, regno); | |
1015 | ||
1016 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1017 | { | |
1018 | if (errno == EIO) | |
1019 | { | |
1020 | have_ptrace_getsetregs = 0; | |
1021 | return 0; | |
1022 | } | |
1023 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1024 | } | |
1025 | ||
1026 | return 1; | |
1027 | } | |
1028 | ||
1029 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1030 | responsible for verifying if this target has the ptrace request | |
1031 | that can be used to store all general-purpose registers at one | |
1032 | shot. If it doesn't, then we should store them using the | |
1033 | old-fashioned way, which is to iterate over the registers and | |
1034 | store them one by one. */ | |
45229ea4 | 1035 | static void |
1dfe79e8 | 1036 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1037 | { |
ac7936df | 1038 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1039 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dfe79e8 SDJ |
1040 | int i; |
1041 | ||
1042 | if (have_ptrace_getsetregs) | |
1043 | if (store_all_gp_regs (regcache, tid, regno)) | |
1044 | return; | |
1045 | ||
1046 | /* If we hit this point, it doesn't really matter which | |
1047 | architecture we are using. We just need to store the | |
1048 | registers in the "old-fashioned way". */ | |
6ced10dd | 1049 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1050 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1051 | } |
1052 | ||
1053 | /* This function actually issues the request to ptrace, telling | |
1054 | it to store all floating-point registers present in the specified | |
1055 | regset. | |
1056 | ||
1057 | If the ptrace request does not exist, this function returns 0 | |
1058 | and properly sets the have_ptrace_* flag. If the request fails, | |
1059 | this function calls perror_with_name. Otherwise, if the request | |
1060 | succeeds, then the regcache is stored and 1 is returned. */ | |
1061 | static int | |
1062 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1063 | { | |
1064 | gdb_fpregset_t fpregs; | |
1065 | ||
1066 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1067 | { | |
1068 | if (errno == EIO) | |
1069 | { | |
1070 | have_ptrace_getsetfpregs = 0; | |
1071 | return 0; | |
1072 | } | |
1073 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1074 | } | |
1075 | ||
1076 | fill_fpregset (regcache, &fpregs, regno); | |
1077 | ||
1078 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1079 | { | |
1080 | if (errno == EIO) | |
1081 | { | |
1082 | have_ptrace_getsetfpregs = 0; | |
1083 | return 0; | |
1084 | } | |
1085 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1086 | } | |
1087 | ||
1088 | return 1; | |
1089 | } | |
1090 | ||
1091 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1092 | responsible for verifying if this target has the ptrace request | |
1093 | that can be used to store all floating-point registers at one | |
1094 | shot. If it doesn't, then we should store them using the | |
1095 | old-fashioned way, which is to iterate over the registers and | |
1096 | store them one by one. */ | |
1097 | static void | |
1098 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1099 | { | |
ac7936df | 1100 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1101 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1102 | int i; | |
1103 | ||
1104 | if (have_ptrace_getsetfpregs) | |
1105 | if (store_all_fp_regs (regcache, tid, regno)) | |
1106 | return; | |
1107 | ||
1108 | /* If we hit this point, it doesn't really matter which | |
1109 | architecture we are using. We just need to store the | |
1110 | registers in the "old-fashioned way". */ | |
1111 | for (i = 0; i < ppc_num_fprs; i++) | |
1112 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1113 | } | |
1114 | ||
1115 | static void | |
1116 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1117 | { | |
ac7936df | 1118 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1119 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1120 | ||
1121 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1122 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1123 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1124 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1125 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1126 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1127 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1128 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1129 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1130 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1131 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1132 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1133 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1134 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1135 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1136 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1137 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1138 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1139 | if (ppc_linux_trap_reg_p (gdbarch)) |
1140 | { | |
1141 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1142 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1143 | } | |
9abe5450 EZ |
1144 | if (have_ptrace_getvrregs) |
1145 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 1146 | store_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
1147 | if (have_ptrace_getsetvsxregs) |
1148 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 1149 | store_vsx_registers (regcache, tid, -1); |
6ced10dd | 1150 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1151 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
1152 | } |
1153 | ||
6ffbb7ab | 1154 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
0ec848ad | 1155 | static CORE_ADDR |
b261e0c5 | 1156 | ppc_linux_get_hwcap (void) |
6ffbb7ab TJB |
1157 | { |
1158 | CORE_ADDR field; | |
1159 | ||
8b88a78e | 1160 | if (target_auxv_search (current_top_target (), AT_HWCAP, &field) != 1) |
0ec848ad | 1161 | return 0; |
6ffbb7ab | 1162 | |
0ec848ad | 1163 | return field; |
6ffbb7ab TJB |
1164 | } |
1165 | ||
1166 | /* The cached DABR value, to install in new threads. | |
926bf92d UW |
1167 | This variable is used when the PowerPC HWDEBUG ptrace |
1168 | interface is not available. */ | |
6ffbb7ab TJB |
1169 | static long saved_dabr_value; |
1170 | ||
1171 | /* Global structure that will store information about the available | |
926bf92d UW |
1172 | features provided by the PowerPC HWDEBUG ptrace interface. */ |
1173 | static struct ppc_debug_info hwdebug_info; | |
6ffbb7ab TJB |
1174 | |
1175 | /* Global variable that holds the maximum number of slots that the | |
926bf92d UW |
1176 | kernel will use. This is only used when PowerPC HWDEBUG ptrace interface |
1177 | is available. */ | |
6ffbb7ab TJB |
1178 | static size_t max_slots_number = 0; |
1179 | ||
1180 | struct hw_break_tuple | |
1181 | { | |
1182 | long slot; | |
1183 | struct ppc_hw_breakpoint *hw_break; | |
1184 | }; | |
1185 | ||
1186 | /* This is an internal VEC created to store information about *points inserted | |
926bf92d UW |
1187 | for each thread. This is used when PowerPC HWDEBUG ptrace interface is |
1188 | available. */ | |
6ffbb7ab TJB |
1189 | typedef struct thread_points |
1190 | { | |
1191 | /* The TID to which this *point relates. */ | |
1192 | int tid; | |
1193 | /* Information about the *point, such as its address, type, etc. | |
1194 | ||
1195 | Each element inside this vector corresponds to a hardware | |
1196 | breakpoint or watchpoint in the thread represented by TID. The maximum | |
1197 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of | |
1198 | the tuple is NULL, then the position in the vector is free. */ | |
1199 | struct hw_break_tuple *hw_breaks; | |
1200 | } *thread_points_p; | |
1201 | DEF_VEC_P (thread_points_p); | |
1202 | ||
1203 | VEC(thread_points_p) *ppc_threads = NULL; | |
1204 | ||
926bf92d UW |
1205 | /* The version of the PowerPC HWDEBUG kernel interface that we will use, if |
1206 | available. */ | |
6ffbb7ab TJB |
1207 | #define PPC_DEBUG_CURRENT_VERSION 1 |
1208 | ||
926bf92d | 1209 | /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */ |
e0d24f8d | 1210 | static int |
926bf92d | 1211 | have_ptrace_hwdebug_interface (void) |
e0d24f8d | 1212 | { |
926bf92d | 1213 | static int have_ptrace_hwdebug_interface = -1; |
e0d24f8d | 1214 | |
926bf92d | 1215 | if (have_ptrace_hwdebug_interface == -1) |
6ffbb7ab TJB |
1216 | { |
1217 | int tid; | |
e0d24f8d | 1218 | |
e38504b3 | 1219 | tid = inferior_ptid.lwp (); |
6ffbb7ab | 1220 | if (tid == 0) |
e99b03dc | 1221 | tid = inferior_ptid.pid (); |
e0d24f8d | 1222 | |
926bf92d UW |
1223 | /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ |
1224 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) | |
6ffbb7ab | 1225 | { |
926bf92d | 1226 | /* Check whether PowerPC HWDEBUG ptrace interface is functional and |
0c56f59b | 1227 | provides any supported feature. */ |
926bf92d | 1228 | if (hwdebug_info.features != 0) |
0c56f59b | 1229 | { |
926bf92d UW |
1230 | have_ptrace_hwdebug_interface = 1; |
1231 | max_slots_number = hwdebug_info.num_instruction_bps | |
1232 | + hwdebug_info.num_data_bps | |
1233 | + hwdebug_info.num_condition_regs; | |
1234 | return have_ptrace_hwdebug_interface; | |
0c56f59b | 1235 | } |
6ffbb7ab | 1236 | } |
926bf92d UW |
1237 | /* Old school interface and no PowerPC HWDEBUG ptrace support. */ |
1238 | have_ptrace_hwdebug_interface = 0; | |
1239 | memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info)); | |
6ffbb7ab TJB |
1240 | } |
1241 | ||
926bf92d | 1242 | return have_ptrace_hwdebug_interface; |
e0d24f8d WZ |
1243 | } |
1244 | ||
f6ac5f3d PA |
1245 | int |
1246 | ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, int ot) | |
b7622095 | 1247 | { |
6ffbb7ab | 1248 | int total_hw_wp, total_hw_bp; |
b7622095 | 1249 | |
926bf92d | 1250 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab | 1251 | { |
926bf92d UW |
1252 | /* When PowerPC HWDEBUG ptrace interface is available, the number of |
1253 | available hardware watchpoints and breakpoints is stored at the | |
1254 | hwdebug_info struct. */ | |
1255 | total_hw_bp = hwdebug_info.num_instruction_bps; | |
1256 | total_hw_wp = hwdebug_info.num_data_bps; | |
6ffbb7ab TJB |
1257 | } |
1258 | else | |
1259 | { | |
926bf92d UW |
1260 | /* When we do not have PowerPC HWDEBUG ptrace interface, we should |
1261 | consider having 1 hardware watchpoint and no hardware breakpoints. */ | |
6ffbb7ab TJB |
1262 | total_hw_bp = 0; |
1263 | total_hw_wp = 1; | |
1264 | } | |
b7622095 | 1265 | |
6ffbb7ab TJB |
1266 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
1267 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
1268 | { | |
bb08bdbd | 1269 | if (cnt + ot > total_hw_wp) |
6ffbb7ab TJB |
1270 | return -1; |
1271 | } | |
1272 | else if (type == bp_hardware_breakpoint) | |
1273 | { | |
572f6555 EBM |
1274 | if (total_hw_bp == 0) |
1275 | { | |
1276 | /* No hardware breakpoint support. */ | |
1277 | return 0; | |
1278 | } | |
6ffbb7ab TJB |
1279 | if (cnt > total_hw_bp) |
1280 | return -1; | |
1281 | } | |
1282 | ||
926bf92d | 1283 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1284 | { |
1285 | int tid; | |
1286 | ptid_t ptid = inferior_ptid; | |
1287 | ||
0df8b418 MS |
1288 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
1289 | and whether the target has DABR. If either answer is no, the | |
1290 | ptrace call will return -1. Fail in that case. */ | |
e38504b3 | 1291 | tid = ptid.lwp (); |
6ffbb7ab | 1292 | if (tid == 0) |
e99b03dc | 1293 | tid = ptid.pid (); |
6ffbb7ab TJB |
1294 | |
1295 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | return 1; | |
b7622095 LM |
1300 | } |
1301 | ||
f6ac5f3d PA |
1302 | int |
1303 | ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e0d24f8d WZ |
1304 | { |
1305 | /* Handle sub-8-byte quantities. */ | |
1306 | if (len <= 0) | |
1307 | return 0; | |
1308 | ||
926bf92d UW |
1309 | /* The PowerPC HWDEBUG ptrace interface tells if there are alignment |
1310 | restrictions for watchpoints in the processors. In that case, we use that | |
1311 | information to determine the hardcoded watchable region for | |
1312 | watchpoints. */ | |
1313 | if (have_ptrace_hwdebug_interface ()) | |
6ffbb7ab | 1314 | { |
e23b9d6e | 1315 | int region_size; |
4feebbdd EBM |
1316 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
1317 | watchpoints and can watch any access within an arbitrary memory | |
1318 | region. This is useful to watch arrays and structs, for instance. It | |
1319 | takes two hardware watchpoints though. */ | |
e09342b5 | 1320 | if (len > 1 |
926bf92d | 1321 | && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
4feebbdd | 1322 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
e09342b5 | 1323 | return 2; |
e23b9d6e UW |
1324 | /* Check if the processor provides DAWR interface. */ |
1325 | if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) | |
1326 | /* DAWR interface allows to watch up to 512 byte wide ranges which | |
1327 | can't cross a 512 byte boundary. */ | |
1328 | region_size = 512; | |
1329 | else | |
1330 | region_size = hwdebug_info.data_bp_alignment; | |
4feebbdd EBM |
1331 | /* Server processors provide one hardware watchpoint and addr+len should |
1332 | fall in the watchable region provided by the ptrace interface. */ | |
e23b9d6e UW |
1333 | if (region_size |
1334 | && (addr + len > (addr & ~(region_size - 1)) + region_size)) | |
0cf6dd15 | 1335 | return 0; |
6ffbb7ab | 1336 | } |
b7622095 | 1337 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
926bf92d UW |
1338 | processors (i.e., server processors). Without the new PowerPC HWDEBUG |
1339 | ptrace interface, DAC-based processors (i.e., embedded processors) will | |
1340 | use addresses aligned to 4-bytes due to the way the read/write flags are | |
6ffbb7ab TJB |
1341 | passed in the old ptrace interface. */ |
1342 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1343 | && (addr + len) > (addr & ~3) + 4) | |
1344 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1345 | return 0; |
1346 | ||
1347 | return 1; | |
1348 | } | |
1349 | ||
6ffbb7ab | 1350 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
e4166a49 | 1351 | static int |
926bf92d | 1352 | hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
6ffbb7ab | 1353 | { |
ad422571 TJB |
1354 | return (a->trigger_type == b->trigger_type |
1355 | && a->addr_mode == b->addr_mode | |
1356 | && a->condition_mode == b->condition_mode | |
1357 | && a->addr == b->addr | |
1358 | && a->addr2 == b->addr2 | |
6ffbb7ab TJB |
1359 | && a->condition_value == b->condition_value); |
1360 | } | |
1361 | ||
1362 | /* This function can be used to retrieve a thread_points by the TID of the | |
1363 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, | |
1364 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the | |
1365 | provided TID will be created and returned. */ | |
1366 | static struct thread_points * | |
926bf92d | 1367 | hwdebug_find_thread_points_by_tid (int tid, int alloc_new) |
6ffbb7ab TJB |
1368 | { |
1369 | int i; | |
1370 | struct thread_points *t; | |
1371 | ||
1372 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) | |
1373 | if (t->tid == tid) | |
1374 | return t; | |
1375 | ||
1376 | t = NULL; | |
1377 | ||
1378 | /* Do we need to allocate a new point_item | |
1379 | if the wanted one does not exist? */ | |
1380 | if (alloc_new) | |
1381 | { | |
8d749320 SM |
1382 | t = XNEW (struct thread_points); |
1383 | t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number); | |
6ffbb7ab TJB |
1384 | t->tid = tid; |
1385 | VEC_safe_push (thread_points_p, ppc_threads, t); | |
1386 | } | |
1387 | ||
1388 | return t; | |
1389 | } | |
1390 | ||
1391 | /* This function is a generic wrapper that is responsible for inserting a | |
1392 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1393 | kernel) and registering it internally in GDB. */ | |
1394 | static void | |
926bf92d | 1395 | hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1396 | { |
1397 | int i; | |
1398 | long slot; | |
a90ecff8 | 1399 | gdb::unique_xmalloc_ptr<ppc_hw_breakpoint> p (XDUP (ppc_hw_breakpoint, b)); |
6ffbb7ab | 1400 | struct hw_break_tuple *hw_breaks; |
6ffbb7ab | 1401 | struct thread_points *t; |
6ffbb7ab | 1402 | |
6ffbb7ab | 1403 | errno = 0; |
a90ecff8 | 1404 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ()); |
6ffbb7ab TJB |
1405 | if (slot < 0) |
1406 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); | |
1407 | ||
1408 | /* Everything went fine, so we have to register this *point. */ | |
926bf92d | 1409 | t = hwdebug_find_thread_points_by_tid (tid, 1); |
6ffbb7ab TJB |
1410 | gdb_assert (t != NULL); |
1411 | hw_breaks = t->hw_breaks; | |
1412 | ||
1413 | /* Find a free element in the hw_breaks vector. */ | |
1414 | for (i = 0; i < max_slots_number; i++) | |
1415 | if (hw_breaks[i].hw_break == NULL) | |
1416 | { | |
1417 | hw_breaks[i].slot = slot; | |
a90ecff8 | 1418 | hw_breaks[i].hw_break = p.release (); |
6ffbb7ab TJB |
1419 | break; |
1420 | } | |
1421 | ||
1422 | gdb_assert (i != max_slots_number); | |
6ffbb7ab TJB |
1423 | } |
1424 | ||
1425 | /* This function is a generic wrapper that is responsible for removing a | |
1426 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1427 | kernel), and unregistering it internally at GDB. */ | |
1428 | static void | |
926bf92d | 1429 | hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1430 | { |
1431 | int i; | |
1432 | struct hw_break_tuple *hw_breaks; | |
1433 | struct thread_points *t; | |
1434 | ||
926bf92d | 1435 | t = hwdebug_find_thread_points_by_tid (tid, 0); |
6ffbb7ab TJB |
1436 | gdb_assert (t != NULL); |
1437 | hw_breaks = t->hw_breaks; | |
1438 | ||
1439 | for (i = 0; i < max_slots_number; i++) | |
926bf92d | 1440 | if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b)) |
6ffbb7ab TJB |
1441 | break; |
1442 | ||
1443 | gdb_assert (i != max_slots_number); | |
1444 | ||
1445 | /* We have to ignore ENOENT errors because the kernel implements hardware | |
1446 | breakpoints/watchpoints as "one-shot", that is, they are automatically | |
1447 | deleted when hit. */ | |
1448 | errno = 0; | |
1449 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) | |
1450 | if (errno != ENOENT) | |
0df8b418 MS |
1451 | perror_with_name (_("Unexpected error deleting " |
1452 | "breakpoint or watchpoint")); | |
6ffbb7ab TJB |
1453 | |
1454 | xfree (hw_breaks[i].hw_break); | |
1455 | hw_breaks[i].hw_break = NULL; | |
1456 | } | |
9f0bdab8 | 1457 | |
f1310107 TJB |
1458 | /* Return the number of registers needed for a ranged breakpoint. */ |
1459 | ||
f6ac5f3d PA |
1460 | int |
1461 | ppc_linux_nat_target::ranged_break_num_registers () | |
f1310107 | 1462 | { |
926bf92d UW |
1463 | return ((have_ptrace_hwdebug_interface () |
1464 | && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? | |
f1310107 TJB |
1465 | 2 : -1); |
1466 | } | |
1467 | ||
1468 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for | |
1469 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ | |
1470 | ||
f6ac5f3d PA |
1471 | int |
1472 | ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1473 | struct bp_target_info *bp_tgt) | |
e0d24f8d | 1474 | { |
9f0bdab8 | 1475 | struct lwp_info *lp; |
6ffbb7ab TJB |
1476 | struct ppc_hw_breakpoint p; |
1477 | ||
926bf92d | 1478 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1479 | return -1; |
1480 | ||
ad422571 TJB |
1481 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1482 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 | 1483 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
0d5ed153 | 1484 | p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address); |
6ffbb7ab TJB |
1485 | p.condition_value = 0; |
1486 | ||
f1310107 TJB |
1487 | if (bp_tgt->length) |
1488 | { | |
1489 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1490 | ||
1491 | /* The breakpoint will trigger if the address of the instruction is | |
1492 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
1493 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1494 | } | |
1495 | else | |
1496 | { | |
1497 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1498 | p.addr2 = 0; | |
1499 | } | |
1500 | ||
4c38200f | 1501 | ALL_LWPS (lp) |
e38504b3 | 1502 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1503 | |
1504 | return 0; | |
1505 | } | |
1506 | ||
f6ac5f3d PA |
1507 | int |
1508 | ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1509 | struct bp_target_info *bp_tgt) | |
6ffbb7ab | 1510 | { |
6ffbb7ab TJB |
1511 | struct lwp_info *lp; |
1512 | struct ppc_hw_breakpoint p; | |
b7622095 | 1513 | |
926bf92d | 1514 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1515 | return -1; |
1516 | ||
ad422571 TJB |
1517 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1518 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1519 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1520 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1521 | p.condition_value = 0; |
1522 | ||
f1310107 TJB |
1523 | if (bp_tgt->length) |
1524 | { | |
1525 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1526 | ||
1527 | /* The breakpoint will trigger if the address of the instruction is within | |
1528 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
1529 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1530 | } | |
1531 | else | |
1532 | { | |
1533 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1534 | p.addr2 = 0; | |
1535 | } | |
1536 | ||
4c38200f | 1537 | ALL_LWPS (lp) |
e38504b3 | 1538 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1539 | |
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | static int | |
e76460db | 1544 | get_trigger_type (enum target_hw_bp_type type) |
6ffbb7ab TJB |
1545 | { |
1546 | int t; | |
1547 | ||
e76460db | 1548 | if (type == hw_read) |
6ffbb7ab | 1549 | t = PPC_BREAKPOINT_TRIGGER_READ; |
e76460db | 1550 | else if (type == hw_write) |
6ffbb7ab | 1551 | t = PPC_BREAKPOINT_TRIGGER_WRITE; |
b7622095 | 1552 | else |
6ffbb7ab TJB |
1553 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
1554 | ||
1555 | return t; | |
1556 | } | |
1557 | ||
9c06b0b4 TJB |
1558 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
1559 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1560 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1561 | an error on failure. */ | |
1562 | ||
f6ac5f3d PA |
1563 | int |
1564 | ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
1565 | target_hw_bp_type rw) | |
9c06b0b4 | 1566 | { |
9c06b0b4 TJB |
1567 | struct lwp_info *lp; |
1568 | struct ppc_hw_breakpoint p; | |
1569 | ||
926bf92d | 1570 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1571 | |
1572 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1573 | p.trigger_type = get_trigger_type (rw); | |
1574 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1575 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1576 | p.addr = addr; | |
1577 | p.addr2 = mask; | |
1578 | p.condition_value = 0; | |
1579 | ||
4c38200f | 1580 | ALL_LWPS (lp) |
e38504b3 | 1581 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
9c06b0b4 TJB |
1582 | |
1583 | return 0; | |
1584 | } | |
1585 | ||
1586 | /* Remove a masked watchpoint at ADDR with the mask MASK. | |
1587 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1588 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1589 | an error on failure. */ | |
1590 | ||
f6ac5f3d PA |
1591 | int |
1592 | ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
1593 | target_hw_bp_type rw) | |
9c06b0b4 | 1594 | { |
9c06b0b4 TJB |
1595 | struct lwp_info *lp; |
1596 | struct ppc_hw_breakpoint p; | |
1597 | ||
926bf92d | 1598 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1599 | |
1600 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1601 | p.trigger_type = get_trigger_type (rw); | |
1602 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1603 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1604 | p.addr = addr; | |
1605 | p.addr2 = mask; | |
1606 | p.condition_value = 0; | |
1607 | ||
4c38200f | 1608 | ALL_LWPS (lp) |
e38504b3 | 1609 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
9c06b0b4 TJB |
1610 | |
1611 | return 0; | |
1612 | } | |
1613 | ||
0cf6dd15 TJB |
1614 | /* Check whether we have at least one free DVC register. */ |
1615 | static int | |
1616 | can_use_watchpoint_cond_accel (void) | |
1617 | { | |
1618 | struct thread_points *p; | |
e38504b3 | 1619 | int tid = inferior_ptid.lwp (); |
926bf92d | 1620 | int cnt = hwdebug_info.num_condition_regs, i; |
0cf6dd15 | 1621 | |
926bf92d | 1622 | if (!have_ptrace_hwdebug_interface () || cnt == 0) |
0cf6dd15 TJB |
1623 | return 0; |
1624 | ||
926bf92d | 1625 | p = hwdebug_find_thread_points_by_tid (tid, 0); |
0cf6dd15 TJB |
1626 | |
1627 | if (p) | |
1628 | { | |
1629 | for (i = 0; i < max_slots_number; i++) | |
1630 | if (p->hw_breaks[i].hw_break != NULL | |
1631 | && (p->hw_breaks[i].hw_break->condition_mode | |
1632 | != PPC_BREAKPOINT_CONDITION_NONE)) | |
1633 | cnt--; | |
1634 | ||
1635 | /* There are no available slots now. */ | |
1636 | if (cnt <= 0) | |
1637 | return 0; | |
1638 | } | |
1639 | ||
1640 | return 1; | |
1641 | } | |
1642 | ||
1643 | /* Calculate the enable bits and the contents of the Data Value Compare | |
1644 | debug register present in BookE processors. | |
1645 | ||
1646 | ADDR is the address to be watched, LEN is the length of watched data | |
1647 | and DATA_VALUE is the value which will trigger the watchpoint. | |
1648 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
1649 | CONDITION_VALUE will hold the value which should be put in the | |
1650 | DVC register. */ | |
1651 | static void | |
1652 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, | |
1653 | uint32_t *condition_mode, uint64_t *condition_value) | |
1654 | { | |
1655 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, | |
1656 | rightmost_enabled_byte; | |
1657 | CORE_ADDR addr_end_data, addr_end_dvc; | |
1658 | ||
1659 | /* The DVC register compares bytes within fixed-length windows which | |
1660 | are word-aligned, with length equal to that of the DVC register. | |
1661 | We need to calculate where our watch region is relative to that | |
1662 | window and enable comparison of the bytes which fall within it. */ | |
1663 | ||
926bf92d | 1664 | align_offset = addr % hwdebug_info.sizeof_condition; |
0cf6dd15 TJB |
1665 | addr_end_data = addr + len; |
1666 | addr_end_dvc = (addr - align_offset | |
926bf92d | 1667 | + hwdebug_info.sizeof_condition); |
0cf6dd15 TJB |
1668 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? |
1669 | addr_end_data - addr_end_dvc : 0; | |
1670 | num_byte_enable = len - num_bytes_off_dvc; | |
1671 | /* Here, bytes are numbered from right to left. */ | |
1672 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
1673 | addr_end_dvc - addr_end_data : 0; | |
1674 | ||
1675 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
1676 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
1677 | *condition_mode |
1678 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
1679 | |
1680 | /* Now we need to match the position within the DVC of the comparison | |
1681 | value with where the watch region is relative to the window | |
1682 | (i.e., the ALIGN_OFFSET). */ | |
1683 | ||
1684 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
1685 | << rightmost_enabled_byte * 8); | |
1686 | } | |
1687 | ||
1688 | /* Return the number of memory locations that need to be accessed to | |
1689 | evaluate the expression which generated the given value chain. | |
1690 | Returns -1 if there's any register access involved, or if there are | |
1691 | other kinds of values which are not acceptable in a condition | |
1692 | expression (e.g., lval_computed or lval_internalvar). */ | |
1693 | static int | |
a6535de1 | 1694 | num_memory_accesses (const std::vector<value_ref_ptr> &chain) |
0cf6dd15 TJB |
1695 | { |
1696 | int found_memory_cnt = 0; | |
0cf6dd15 TJB |
1697 | |
1698 | /* The idea here is that evaluating an expression generates a series | |
1699 | of values, one holding the value of every subexpression. (The | |
1700 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
1701 | a*b+c.) GDB's values hold almost enough information to establish | |
1702 | the criteria given above --- they identify memory lvalues, | |
1703 | register lvalues, computed values, etcetera. So we can evaluate | |
1704 | the expression, and then scan the chain of values that leaves | |
1705 | behind to determine the memory locations involved in the evaluation | |
1706 | of an expression. | |
1707 | ||
1708 | However, I don't think that the values returned by inferior | |
1709 | function calls are special in any way. So this function may not | |
1710 | notice that an expression contains an inferior function call. | |
1711 | FIXME. */ | |
1712 | ||
a6535de1 | 1713 | for (const value_ref_ptr &iter : chain) |
0cf6dd15 | 1714 | { |
a6535de1 TT |
1715 | struct value *v = iter.get (); |
1716 | ||
0cf6dd15 TJB |
1717 | /* Constants and values from the history are fine. */ |
1718 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) | |
1719 | continue; | |
1720 | else if (VALUE_LVAL (v) == lval_memory) | |
1721 | { | |
1722 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
1723 | we either just used its address (e.g., `a' in `a.b') or | |
1724 | we never needed it at all (e.g., `a' in `a,b'). */ | |
1725 | if (!value_lazy (v)) | |
1726 | found_memory_cnt++; | |
1727 | } | |
0df8b418 | 1728 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
1729 | else |
1730 | return -1; | |
1731 | } | |
1732 | ||
1733 | return found_memory_cnt; | |
1734 | } | |
1735 | ||
1736 | /* Verifies whether the expression COND can be implemented using the | |
1737 | DVC (Data Value Compare) register in BookE processors. The expression | |
1738 | must test the watch value for equality with a constant expression. | |
1739 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
1740 | which the watch value should be compared and LEN will contain the size |
1741 | of the constant. */ | |
0cf6dd15 TJB |
1742 | static int |
1743 | check_condition (CORE_ADDR watch_addr, struct expression *cond, | |
e7db58ea | 1744 | CORE_ADDR *data_value, int *len) |
0cf6dd15 TJB |
1745 | { |
1746 | int pc = 1, num_accesses_left, num_accesses_right; | |
a6535de1 TT |
1747 | struct value *left_val, *right_val; |
1748 | std::vector<value_ref_ptr> left_chain, right_chain; | |
0cf6dd15 TJB |
1749 | |
1750 | if (cond->elts[0].opcode != BINOP_EQUAL) | |
1751 | return 0; | |
1752 | ||
3a1115a0 | 1753 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0); |
0cf6dd15 TJB |
1754 | num_accesses_left = num_memory_accesses (left_chain); |
1755 | ||
1756 | if (left_val == NULL || num_accesses_left < 0) | |
a6535de1 | 1757 | return 0; |
0cf6dd15 | 1758 | |
3a1115a0 | 1759 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0); |
0cf6dd15 TJB |
1760 | num_accesses_right = num_memory_accesses (right_chain); |
1761 | ||
1762 | if (right_val == NULL || num_accesses_right < 0) | |
a6535de1 | 1763 | return 0; |
0cf6dd15 TJB |
1764 | |
1765 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
1766 | && VALUE_LVAL (left_val) == lval_memory | |
1767 | && value_address (left_val) == watch_addr) | |
e7db58ea TJB |
1768 | { |
1769 | *data_value = value_as_long (right_val); | |
1770 | ||
1771 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
1772 | the same type as the memory region referenced by LEFT_VAL. */ | |
1773 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); | |
1774 | } | |
0cf6dd15 TJB |
1775 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
1776 | && VALUE_LVAL (right_val) == lval_memory | |
1777 | && value_address (right_val) == watch_addr) | |
e7db58ea TJB |
1778 | { |
1779 | *data_value = value_as_long (left_val); | |
1780 | ||
1781 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
1782 | the same type as the memory region referenced by RIGHT_VAL. */ | |
1783 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); | |
1784 | } | |
0cf6dd15 | 1785 | else |
a6535de1 | 1786 | return 0; |
0cf6dd15 TJB |
1787 | |
1788 | return 1; | |
1789 | } | |
1790 | ||
1791 | /* Return non-zero if the target is capable of using hardware to evaluate | |
1792 | the condition expression, thus only triggering the watchpoint when it is | |
1793 | true. */ | |
57810aa7 | 1794 | bool |
f6ac5f3d PA |
1795 | ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, int len, |
1796 | int rw, | |
1797 | struct expression *cond) | |
0cf6dd15 TJB |
1798 | { |
1799 | CORE_ADDR data_value; | |
1800 | ||
926bf92d UW |
1801 | return (have_ptrace_hwdebug_interface () |
1802 | && hwdebug_info.num_condition_regs > 0 | |
e7db58ea | 1803 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
1804 | } |
1805 | ||
e09342b5 TJB |
1806 | /* Set up P with the parameters necessary to request a watchpoint covering |
1807 | LEN bytes starting at ADDR and if possible with condition expression COND | |
1808 | evaluated by hardware. INSERT tells if we are creating a request for | |
1809 | inserting or removing the watchpoint. */ | |
1810 | ||
1811 | static void | |
1812 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, | |
e76460db PA |
1813 | int len, enum target_hw_bp_type type, |
1814 | struct expression *cond, int insert) | |
e09342b5 | 1815 | { |
f16c4e8b | 1816 | if (len == 1 |
926bf92d | 1817 | || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) |
e09342b5 TJB |
1818 | { |
1819 | int use_condition; | |
1820 | CORE_ADDR data_value; | |
1821 | ||
1822 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
926bf92d | 1823 | : hwdebug_info.num_condition_regs > 0); |
e7db58ea TJB |
1824 | if (cond && use_condition && check_condition (addr, cond, |
1825 | &data_value, &len)) | |
e09342b5 TJB |
1826 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
1827 | &p->condition_value); | |
1828 | else | |
1829 | { | |
1830 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1831 | p->condition_value = 0; | |
1832 | } | |
1833 | ||
1834 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1835 | p->addr2 = 0; | |
1836 | } | |
1837 | else | |
1838 | { | |
1839 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1840 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1841 | p->condition_value = 0; | |
1842 | ||
1843 | /* The watchpoint will trigger if the address of the memory access is | |
1844 | within the defined range, as follows: p->addr <= address < p->addr2. | |
1845 | ||
1846 | Note that the above sentence just documents how ptrace interprets | |
1847 | its arguments; the watchpoint is set to watch the range defined by | |
1848 | the user _inclusively_, as specified by the user interface. */ | |
1849 | p->addr2 = (uint64_t) addr + len; | |
1850 | } | |
1851 | ||
1852 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
e76460db | 1853 | p->trigger_type = get_trigger_type (type); |
e09342b5 TJB |
1854 | p->addr = (uint64_t) addr; |
1855 | } | |
1856 | ||
f6ac5f3d PA |
1857 | int |
1858 | ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
1859 | enum target_hw_bp_type type, | |
1860 | struct expression *cond) | |
6ffbb7ab TJB |
1861 | { |
1862 | struct lwp_info *lp; | |
6ffbb7ab TJB |
1863 | int ret = -1; |
1864 | ||
926bf92d | 1865 | if (have_ptrace_hwdebug_interface ()) |
e0d24f8d | 1866 | { |
6ffbb7ab TJB |
1867 | struct ppc_hw_breakpoint p; |
1868 | ||
e76460db | 1869 | create_watchpoint_request (&p, addr, len, type, cond, 1); |
6ffbb7ab | 1870 | |
4c38200f | 1871 | ALL_LWPS (lp) |
e38504b3 | 1872 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1873 | |
1874 | ret = 0; | |
e0d24f8d | 1875 | } |
6ffbb7ab TJB |
1876 | else |
1877 | { | |
1878 | long dabr_value; | |
1879 | long read_mode, write_mode; | |
e0d24f8d | 1880 | |
6ffbb7ab TJB |
1881 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
1882 | { | |
1883 | /* PowerPC 440 requires only the read/write flags to be passed | |
1884 | to the kernel. */ | |
ad422571 | 1885 | read_mode = 1; |
6ffbb7ab TJB |
1886 | write_mode = 2; |
1887 | } | |
1888 | else | |
1889 | { | |
1890 | /* PowerPC 970 and other DABR-based processors are required to pass | |
1891 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 1892 | read_mode = 5; |
6ffbb7ab TJB |
1893 | write_mode = 6; |
1894 | } | |
1c86e440 | 1895 | |
6ffbb7ab | 1896 | dabr_value = addr & ~(read_mode | write_mode); |
e76460db | 1897 | switch (type) |
6ffbb7ab TJB |
1898 | { |
1899 | case hw_read: | |
1900 | /* Set read and translate bits. */ | |
1901 | dabr_value |= read_mode; | |
1902 | break; | |
1903 | case hw_write: | |
1904 | /* Set write and translate bits. */ | |
1905 | dabr_value |= write_mode; | |
1906 | break; | |
1907 | case hw_access: | |
1908 | /* Set read, write and translate bits. */ | |
1909 | dabr_value |= read_mode | write_mode; | |
1910 | break; | |
1911 | } | |
1c86e440 | 1912 | |
6ffbb7ab TJB |
1913 | saved_dabr_value = dabr_value; |
1914 | ||
4c38200f | 1915 | ALL_LWPS (lp) |
e38504b3 | 1916 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, |
0cf6dd15 | 1917 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
1918 | return -1; |
1919 | ||
1920 | ret = 0; | |
1921 | } | |
1922 | ||
1923 | return ret; | |
e0d24f8d WZ |
1924 | } |
1925 | ||
f6ac5f3d PA |
1926 | int |
1927 | ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
1928 | enum target_hw_bp_type type, | |
1929 | struct expression *cond) | |
e0d24f8d | 1930 | { |
9f0bdab8 | 1931 | struct lwp_info *lp; |
6ffbb7ab | 1932 | int ret = -1; |
9f0bdab8 | 1933 | |
926bf92d | 1934 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1935 | { |
1936 | struct ppc_hw_breakpoint p; | |
1937 | ||
e76460db | 1938 | create_watchpoint_request (&p, addr, len, type, cond, 0); |
6ffbb7ab | 1939 | |
4c38200f | 1940 | ALL_LWPS (lp) |
e38504b3 | 1941 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1942 | |
1943 | ret = 0; | |
1944 | } | |
1945 | else | |
1946 | { | |
1947 | saved_dabr_value = 0; | |
4c38200f | 1948 | ALL_LWPS (lp) |
e38504b3 | 1949 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, |
0cf6dd15 | 1950 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
1951 | return -1; |
1952 | ||
1953 | ret = 0; | |
1954 | } | |
1955 | ||
1956 | return ret; | |
e0d24f8d WZ |
1957 | } |
1958 | ||
135340af PA |
1959 | void |
1960 | ppc_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e0d24f8d | 1961 | { |
e38504b3 | 1962 | int tid = lp->ptid.lwp (); |
6ffbb7ab | 1963 | |
926bf92d | 1964 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1965 | { |
1966 | int i; | |
1967 | struct thread_points *p; | |
1968 | struct hw_break_tuple *hw_breaks; | |
1969 | ||
1970 | if (VEC_empty (thread_points_p, ppc_threads)) | |
1971 | return; | |
1972 | ||
0df8b418 | 1973 | /* Get a list of breakpoints from any thread. */ |
6ffbb7ab TJB |
1974 | p = VEC_last (thread_points_p, ppc_threads); |
1975 | hw_breaks = p->hw_breaks; | |
1976 | ||
0df8b418 | 1977 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
6ffbb7ab TJB |
1978 | for (i = 0; i < max_slots_number; i++) |
1979 | if (hw_breaks[i].hw_break) | |
aacbb8a5 LM |
1980 | { |
1981 | /* Older kernels did not make new threads inherit their parent | |
1982 | thread's debug state, so we always clear the slot and replicate | |
1983 | the debug state ourselves, ensuring compatibility with all | |
1984 | kernels. */ | |
1985 | ||
1986 | /* The ppc debug resource accounting is done through "slots". | |
1987 | Ask the kernel the deallocate this specific *point's slot. */ | |
1988 | ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot); | |
1989 | ||
926bf92d | 1990 | hwdebug_insert_point (hw_breaks[i].hw_break, tid); |
aacbb8a5 | 1991 | } |
6ffbb7ab TJB |
1992 | } |
1993 | else | |
1994 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); | |
1995 | } | |
1996 | ||
1997 | static void | |
1998 | ppc_linux_thread_exit (struct thread_info *tp, int silent) | |
1999 | { | |
2000 | int i; | |
e38504b3 | 2001 | int tid = tp->ptid.lwp (); |
6ffbb7ab TJB |
2002 | struct hw_break_tuple *hw_breaks; |
2003 | struct thread_points *t = NULL, *p; | |
2004 | ||
926bf92d | 2005 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2006 | return; |
2007 | ||
2008 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) | |
2009 | if (p->tid == tid) | |
2010 | { | |
2011 | t = p; | |
2012 | break; | |
2013 | } | |
2014 | ||
2015 | if (t == NULL) | |
2016 | return; | |
2017 | ||
2018 | VEC_unordered_remove (thread_points_p, ppc_threads, i); | |
2019 | ||
2020 | hw_breaks = t->hw_breaks; | |
2021 | ||
2022 | for (i = 0; i < max_slots_number; i++) | |
2023 | if (hw_breaks[i].hw_break) | |
2024 | xfree (hw_breaks[i].hw_break); | |
2025 | ||
2026 | xfree (t->hw_breaks); | |
2027 | xfree (t); | |
e0d24f8d WZ |
2028 | } |
2029 | ||
57810aa7 | 2030 | bool |
f6ac5f3d | 2031 | ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e0d24f8d | 2032 | { |
f865ee35 | 2033 | siginfo_t siginfo; |
e0d24f8d | 2034 | |
f865ee35 | 2035 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
57810aa7 | 2036 | return false; |
e0d24f8d | 2037 | |
f865ee35 JK |
2038 | if (siginfo.si_signo != SIGTRAP |
2039 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 2040 | return false; |
e0d24f8d | 2041 | |
926bf92d | 2042 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2043 | { |
2044 | int i; | |
2045 | struct thread_points *t; | |
2046 | struct hw_break_tuple *hw_breaks; | |
2047 | /* The index (or slot) of the *point is passed in the si_errno field. */ | |
f865ee35 | 2048 | int slot = siginfo.si_errno; |
6ffbb7ab | 2049 | |
e38504b3 | 2050 | t = hwdebug_find_thread_points_by_tid (inferior_ptid.lwp (), 0); |
6ffbb7ab TJB |
2051 | |
2052 | /* Find out if this *point is a hardware breakpoint. | |
2053 | If so, we should return 0. */ | |
2054 | if (t) | |
2055 | { | |
2056 | hw_breaks = t->hw_breaks; | |
2057 | for (i = 0; i < max_slots_number; i++) | |
2058 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot | |
2059 | && hw_breaks[i].hw_break->trigger_type | |
2060 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) | |
57810aa7 | 2061 | return false; |
6ffbb7ab TJB |
2062 | } |
2063 | } | |
2064 | ||
f865ee35 | 2065 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 2066 | return true; |
e0d24f8d WZ |
2067 | } |
2068 | ||
57810aa7 | 2069 | bool |
f6ac5f3d | 2070 | ppc_linux_nat_target::stopped_by_watchpoint () |
9f0bdab8 DJ |
2071 | { |
2072 | CORE_ADDR addr; | |
f6ac5f3d | 2073 | return stopped_data_address (&addr); |
9f0bdab8 DJ |
2074 | } |
2075 | ||
57810aa7 | 2076 | bool |
f6ac5f3d PA |
2077 | ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
2078 | CORE_ADDR start, | |
2079 | int length) | |
5009afc5 | 2080 | { |
b7622095 LM |
2081 | int mask; |
2082 | ||
926bf92d | 2083 | if (have_ptrace_hwdebug_interface () |
6ffbb7ab TJB |
2084 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2085 | return start <= addr && start + length >= addr; | |
2086 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
b7622095 LM |
2087 | mask = 3; |
2088 | else | |
2089 | mask = 7; | |
2090 | ||
2091 | addr &= ~mask; | |
2092 | ||
0df8b418 | 2093 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 2094 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
2095 | } |
2096 | ||
9c06b0b4 TJB |
2097 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
2098 | ||
f6ac5f3d PA |
2099 | int |
2100 | ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, CORE_ADDR mask) | |
9c06b0b4 | 2101 | { |
926bf92d UW |
2102 | if (!have_ptrace_hwdebug_interface () |
2103 | || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
9c06b0b4 TJB |
2104 | return -1; |
2105 | else if ((mask & 0xC0000000) != 0xC0000000) | |
2106 | { | |
2107 | warning (_("The given mask covers kernel address space " | |
2108 | "and cannot be used.\n")); | |
2109 | ||
2110 | return -2; | |
2111 | } | |
2112 | else | |
2113 | return 2; | |
2114 | } | |
2115 | ||
f6ac5f3d PA |
2116 | void |
2117 | ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
45229ea4 | 2118 | { |
222312d3 | 2119 | pid_t tid = get_ptrace_pid (regcache->ptid ()); |
05f13b9c | 2120 | |
45229ea4 | 2121 | if (regno >= 0) |
56be3814 | 2122 | store_register (regcache, tid, regno); |
45229ea4 | 2123 | else |
56be3814 | 2124 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
2125 | } |
2126 | ||
f2db237a AM |
2127 | /* Functions for transferring registers between a gregset_t or fpregset_t |
2128 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
0df8b418 | 2129 | by the ptrace interface, not the current program's ABI. Eg. if a |
f2db237a AM |
2130 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
2131 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
2132 | ||
50c9bd31 | 2133 | void |
7f7fe91e | 2134 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 2135 | { |
f2db237a | 2136 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2137 | |
f2db237a | 2138 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
2139 | } |
2140 | ||
fdb28ac4 | 2141 | void |
7f7fe91e UW |
2142 | fill_gregset (const struct regcache *regcache, |
2143 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 2144 | { |
f2db237a | 2145 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2146 | |
f2db237a AM |
2147 | if (regno == -1) |
2148 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
2149 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
2150 | } |
2151 | ||
50c9bd31 | 2152 | void |
7f7fe91e | 2153 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 2154 | { |
f2db237a AM |
2155 | const struct regset *regset = ppc_linux_fpregset (); |
2156 | ||
2157 | ppc_supply_fpregset (regset, regcache, -1, | |
2158 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 2159 | } |
fdb28ac4 | 2160 | |
fdb28ac4 | 2161 | void |
7f7fe91e UW |
2162 | fill_fpregset (const struct regcache *regcache, |
2163 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 2164 | { |
f2db237a AM |
2165 | const struct regset *regset = ppc_linux_fpregset (); |
2166 | ||
2167 | ppc_collect_fpregset (regset, regcache, regno, | |
2168 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 2169 | } |
10d6c8cd | 2170 | |
2e077f5e PFC |
2171 | int |
2172 | ppc_linux_nat_target::auxv_parse (gdb_byte **readptr, | |
2173 | gdb_byte *endptr, CORE_ADDR *typep, | |
2174 | CORE_ADDR *valp) | |
409c383c | 2175 | { |
e38504b3 | 2176 | int tid = inferior_ptid.lwp (); |
409c383c | 2177 | if (tid == 0) |
e99b03dc | 2178 | tid = inferior_ptid.pid (); |
409c383c | 2179 | |
2e077f5e | 2180 | int sizeof_auxv_field = ppc_linux_target_wordsize (tid); |
409c383c | 2181 | |
f5656ead | 2182 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
409c383c UW |
2183 | gdb_byte *ptr = *readptr; |
2184 | ||
2185 | if (endptr == ptr) | |
2186 | return 0; | |
2187 | ||
2188 | if (endptr - ptr < sizeof_auxv_field * 2) | |
2189 | return -1; | |
2190 | ||
e17a4113 | 2191 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c | 2192 | ptr += sizeof_auxv_field; |
e17a4113 | 2193 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c UW |
2194 | ptr += sizeof_auxv_field; |
2195 | ||
2196 | *readptr = ptr; | |
2197 | return 1; | |
2198 | } | |
2199 | ||
f6ac5f3d PA |
2200 | const struct target_desc * |
2201 | ppc_linux_nat_target::read_description () | |
310a98e1 | 2202 | { |
e38504b3 | 2203 | int tid = inferior_ptid.lwp (); |
7284e1be | 2204 | if (tid == 0) |
e99b03dc | 2205 | tid = inferior_ptid.pid (); |
7284e1be | 2206 | |
310a98e1 DJ |
2207 | if (have_ptrace_getsetevrregs) |
2208 | { | |
2209 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
2210 | |
2211 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
2212 | return tdesc_powerpc_e500l; |
2213 | ||
2214 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
2215 | Anything else needs to be reported. */ | |
2216 | else if (errno != EIO) | |
2217 | perror_with_name (_("Unable to fetch SPE registers")); | |
2218 | } | |
2219 | ||
bd64614e PFC |
2220 | struct ppc_linux_features features = ppc_linux_no_features; |
2221 | ||
2e077f5e | 2222 | features.wordsize = ppc_linux_target_wordsize (tid); |
bd64614e | 2223 | |
0ec848ad | 2224 | CORE_ADDR hwcap = ppc_linux_get_hwcap (); |
bd64614e | 2225 | |
0154d990 | 2226 | if (have_ptrace_getsetvsxregs |
bd64614e | 2227 | && (hwcap & PPC_FEATURE_HAS_VSX)) |
604c2f83 LM |
2228 | { |
2229 | gdb_vsxregset_t vsxregset; | |
2230 | ||
2231 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
bd64614e | 2232 | features.vsx = true; |
604c2f83 LM |
2233 | |
2234 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
2235 | Anything else needs to be reported. */ | |
2236 | else if (errno != EIO) | |
2237 | perror_with_name (_("Unable to fetch VSX registers")); | |
2238 | } | |
2239 | ||
0154d990 | 2240 | if (have_ptrace_getvrregs |
bd64614e | 2241 | && (hwcap & PPC_FEATURE_HAS_ALTIVEC)) |
7284e1be UW |
2242 | { |
2243 | gdb_vrregset_t vrregset; | |
2244 | ||
2245 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
bd64614e | 2246 | features.altivec = true; |
7284e1be UW |
2247 | |
2248 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
2249 | Anything else needs to be reported. */ | |
2250 | else if (errno != EIO) | |
2251 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
2252 | } |
2253 | ||
bd64614e PFC |
2254 | if (hwcap & PPC_FEATURE_CELL) |
2255 | features.cell = true; | |
7284e1be | 2256 | |
bd64614e | 2257 | features.isa205 = ppc_linux_has_isa205 (hwcap); |
604c2f83 | 2258 | |
bd64614e | 2259 | return ppc_linux_match_description (features); |
310a98e1 DJ |
2260 | } |
2261 | ||
10d6c8cd DJ |
2262 | void |
2263 | _initialize_ppc_linux_nat (void) | |
2264 | { | |
f6ac5f3d | 2265 | linux_target = &the_ppc_linux_nat_target; |
310a98e1 | 2266 | |
76727919 | 2267 | gdb::observers::thread_exit.attach (ppc_linux_thread_exit); |
6ffbb7ab | 2268 | |
10d6c8cd | 2269 | /* Register the target. */ |
d9f719f1 | 2270 | add_inf_child_target (linux_target); |
10d6c8cd | 2271 | } |