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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
42a4f53d | 3 | Copyright (C) 1988-2019 Free Software Foundation, Inc. |
c877c8e6 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
19 | |
20 | #include "defs.h" | |
76727919 | 21 | #include "observable.h" |
c877c8e6 KB |
22 | #include "frame.h" |
23 | #include "inferior.h" | |
6ffbb7ab | 24 | #include "gdbthread.h" |
c877c8e6 | 25 | #include "gdbcore.h" |
4e052eda | 26 | #include "regcache.h" |
1d75a658 | 27 | #include "regset.h" |
10d6c8cd DJ |
28 | #include "target.h" |
29 | #include "linux-nat.h" | |
c877c8e6 | 30 | #include <sys/types.h> |
c877c8e6 KB |
31 | #include <signal.h> |
32 | #include <sys/user.h> | |
33 | #include <sys/ioctl.h> | |
7ca18ed6 | 34 | #include <sys/uio.h> |
0747795c | 35 | #include "common/gdb_wait.h" |
c877c8e6 KB |
36 | #include <fcntl.h> |
37 | #include <sys/procfs.h> | |
5826e159 | 38 | #include "nat/gdb_ptrace.h" |
64f57f3d | 39 | #include "nat/linux-ptrace.h" |
bcc0c096 | 40 | #include "inf-ptrace.h" |
c877c8e6 | 41 | |
0df8b418 | 42 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 43 | #include "gregset.h" |
16333c4f | 44 | #include "ppc-tdep.h" |
7284e1be UW |
45 | #include "ppc-linux-tdep.h" |
46 | ||
b7622095 LM |
47 | /* Required when using the AUXV. */ |
48 | #include "elf/common.h" | |
49 | #include "auxv.h" | |
50 | ||
bd64614e PFC |
51 | #include "arch/ppc-linux-common.h" |
52 | #include "arch/ppc-linux-tdesc.h" | |
514c5338 | 53 | #include "nat/ppc-linux.h" |
01904826 | 54 | |
6ffbb7ab | 55 | /* Similarly for the hardware watchpoint support. These requests are used |
926bf92d | 56 | when the PowerPC HWDEBUG ptrace interface is not available. */ |
e0d24f8d WZ |
57 | #ifndef PTRACE_GET_DEBUGREG |
58 | #define PTRACE_GET_DEBUGREG 25 | |
59 | #endif | |
60 | #ifndef PTRACE_SET_DEBUGREG | |
61 | #define PTRACE_SET_DEBUGREG 26 | |
62 | #endif | |
63 | #ifndef PTRACE_GETSIGINFO | |
64 | #define PTRACE_GETSIGINFO 0x4202 | |
65 | #endif | |
01904826 | 66 | |
926bf92d UW |
67 | /* These requests are used when the PowerPC HWDEBUG ptrace interface is |
68 | available. It exposes the debug facilities of PowerPC processors, as well | |
69 | as additional features of BookE processors, such as ranged breakpoints and | |
70 | watchpoints and hardware-accelerated condition evaluation. */ | |
6ffbb7ab TJB |
71 | #ifndef PPC_PTRACE_GETHWDBGINFO |
72 | ||
926bf92d UW |
73 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG |
74 | ptrace interface is not present in ptrace.h, so we'll have to pretty much | |
75 | include it all here so that the code at least compiles on older systems. */ | |
6ffbb7ab TJB |
76 | #define PPC_PTRACE_GETHWDBGINFO 0x89 |
77 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
78 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
79 | ||
80 | struct ppc_debug_info | |
81 | { | |
0df8b418 | 82 | uint32_t version; /* Only version 1 exists to date. */ |
6ffbb7ab TJB |
83 | uint32_t num_instruction_bps; |
84 | uint32_t num_data_bps; | |
85 | uint32_t num_condition_regs; | |
86 | uint32_t data_bp_alignment; | |
0df8b418 | 87 | uint32_t sizeof_condition; /* size of the DVC register. */ |
6ffbb7ab TJB |
88 | uint64_t features; |
89 | }; | |
90 | ||
91 | /* Features will have bits indicating whether there is support for: */ | |
92 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
93 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
94 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
95 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
96 | ||
97 | struct ppc_hw_breakpoint | |
98 | { | |
99 | uint32_t version; /* currently, version must be 1 */ | |
100 | uint32_t trigger_type; /* only some combinations allowed */ | |
101 | uint32_t addr_mode; /* address match mode */ | |
102 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
103 | uint64_t addr; /* break/watchpoint address */ | |
104 | uint64_t addr2; /* range end or mask */ | |
105 | uint64_t condition_value; /* contents of the DVC register */ | |
106 | }; | |
107 | ||
108 | /* Trigger type. */ | |
109 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
110 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
111 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
112 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
113 | ||
114 | /* Address mode. */ | |
115 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
116 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
117 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
118 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
119 | ||
120 | /* Condition mode. */ | |
121 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
122 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
123 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
124 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
125 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
126 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
127 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
128 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
129 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) | |
130 | #endif /* PPC_PTRACE_GETHWDBGINFO */ | |
131 | ||
e23b9d6e UW |
132 | /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider |
133 | watchpoint (up to 512 bytes). */ | |
134 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR | |
135 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | |
136 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */ | |
6ffbb7ab | 137 | |
1dfe79e8 SDJ |
138 | /* Similarly for the general-purpose (gp0 -- gp31) |
139 | and floating-point registers (fp0 -- fp31). */ | |
140 | #ifndef PTRACE_GETREGS | |
141 | #define PTRACE_GETREGS 12 | |
142 | #endif | |
143 | #ifndef PTRACE_SETREGS | |
144 | #define PTRACE_SETREGS 13 | |
145 | #endif | |
146 | #ifndef PTRACE_GETFPREGS | |
147 | #define PTRACE_GETFPREGS 14 | |
148 | #endif | |
149 | #ifndef PTRACE_SETFPREGS | |
150 | #define PTRACE_SETFPREGS 15 | |
151 | #endif | |
152 | ||
9abe5450 EZ |
153 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
154 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
155 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
156 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
157 | flat array of chars, so that it is easier to manipulate for gdb. | |
158 | ||
159 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
160 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 161 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
162 | Appended to this there is space for the VRSAVE register: 4 bytes. |
163 | Even though this vrsave register is not included in the regset | |
164 | typedef, it is handled by the ptrace requests. | |
165 | ||
9abe5450 EZ |
166 | The layout is like this (where x is the actual value of the vscr reg): */ |
167 | ||
168 | /* *INDENT-OFF* */ | |
169 | /* | |
1d75a658 | 170 | Big-Endian: |
9abe5450 EZ |
171 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| |
172 | <-------> <-------><-------><-> | |
173 | VR0 VR31 VSCR VRSAVE | |
1d75a658 PFC |
174 | Little-Endian: |
175 | |.|.|.|.|.....|.|.|.|.||X|.|.|.||.| | |
176 | <-------> <-------><-------><-> | |
177 | VR0 VR31 VSCR VRSAVE | |
9abe5450 EZ |
178 | */ |
179 | /* *INDENT-ON* */ | |
180 | ||
d078308a | 181 | typedef char gdb_vrregset_t[PPC_LINUX_SIZEOF_VRREGSET]; |
9abe5450 | 182 | |
604c2f83 LM |
183 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
184 | with the existing FPR and VMX registers. | |
185 | ||
186 | VSR doubleword 0 VSR doubleword 1 | |
187 | ---------------------------------------------------------------- | |
188 | VSR[0] | FPR[0] | | | |
189 | ---------------------------------------------------------------- | |
190 | VSR[1] | FPR[1] | | | |
191 | ---------------------------------------------------------------- | |
192 | | ... | | | |
193 | | ... | | | |
194 | ---------------------------------------------------------------- | |
195 | VSR[30] | FPR[30] | | | |
196 | ---------------------------------------------------------------- | |
197 | VSR[31] | FPR[31] | | | |
198 | ---------------------------------------------------------------- | |
199 | VSR[32] | VR[0] | | |
200 | ---------------------------------------------------------------- | |
201 | VSR[33] | VR[1] | | |
202 | ---------------------------------------------------------------- | |
203 | | ... | | |
204 | | ... | | |
205 | ---------------------------------------------------------------- | |
206 | VSR[62] | VR[30] | | |
207 | ---------------------------------------------------------------- | |
208 | VSR[63] | VR[31] | | |
209 | ---------------------------------------------------------------- | |
210 | ||
211 | VSX has 64 128bit registers. The first 32 registers overlap with | |
212 | the FP registers (doubleword 0) and hence extend them with additional | |
213 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
214 | registers. */ | |
d078308a | 215 | typedef char gdb_vsxregset_t[PPC_LINUX_SIZEOF_VSXREGSET]; |
01904826 | 216 | |
b021a221 | 217 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 218 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
219 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
220 | ptrace calls only access the lower half of each register, to allow | |
221 | them to behave the same way they do on non-SPE systems. There's a | |
222 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
223 | read and write the top halves of all the general-purpose registers | |
224 | at once, along with some SPE-specific registers. | |
01904826 JB |
225 | |
226 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 227 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 228 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
229 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
230 | bottom halves together. | |
01904826 JB |
231 | |
232 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
233 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
234 | struct gdb_evrregset_t | |
235 | { | |
236 | unsigned long evr[32]; | |
237 | unsigned long long acc; | |
238 | unsigned long spefscr; | |
239 | }; | |
240 | ||
604c2f83 LM |
241 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
242 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
243 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
244 | gotten an error. Note that VSX registers 32 through 63 overlap | |
245 | with VR registers 0 through 31. */ | |
246 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
247 | |
248 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
249 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
250 | registers. Zero if we've tried one of them and gotten an | |
251 | error. */ | |
9abe5450 EZ |
252 | int have_ptrace_getvrregs = 1; |
253 | ||
01904826 JB |
254 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
255 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
256 | registers. Zero if we've tried one of them and gotten an | |
257 | error. */ | |
258 | int have_ptrace_getsetevrregs = 1; | |
259 | ||
1dfe79e8 SDJ |
260 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
261 | PTRACE_SETREGS requests, for reading and writing the | |
262 | general-purpose registers. Zero if we've tried one of | |
263 | them and gotten an error. */ | |
264 | int have_ptrace_getsetregs = 1; | |
265 | ||
266 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
267 | PTRACE_SETFPREGS requests, for reading and writing the | |
268 | floating-pointers registers. Zero if we've tried one of | |
269 | them and gotten an error. */ | |
270 | int have_ptrace_getsetfpregs = 1; | |
271 | ||
f6ac5f3d PA |
272 | struct ppc_linux_nat_target final : public linux_nat_target |
273 | { | |
274 | /* Add our register access methods. */ | |
275 | void fetch_registers (struct regcache *, int) override; | |
276 | void store_registers (struct regcache *, int) override; | |
277 | ||
278 | /* Add our breakpoint/watchpoint methods. */ | |
279 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
280 | ||
281 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
282 | override; | |
283 | ||
284 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
285 | override; | |
286 | ||
287 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
288 | ||
289 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
290 | struct expression *) override; | |
291 | ||
292 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
293 | struct expression *) override; | |
294 | ||
295 | int insert_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
296 | override; | |
297 | ||
298 | int remove_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
299 | override; | |
300 | ||
57810aa7 | 301 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 302 | |
57810aa7 | 303 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 304 | |
57810aa7 | 305 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d | 306 | |
57810aa7 | 307 | bool can_accel_watchpoint_condition (CORE_ADDR, int, int, struct expression *) |
f6ac5f3d PA |
308 | override; |
309 | ||
310 | int masked_watch_num_registers (CORE_ADDR, CORE_ADDR) override; | |
311 | ||
312 | int ranged_break_num_registers () override; | |
313 | ||
314 | const struct target_desc *read_description () override; | |
315 | ||
316 | int auxv_parse (gdb_byte **readptr, | |
317 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
318 | override; | |
135340af PA |
319 | |
320 | /* Override linux_nat_target low methods. */ | |
321 | void low_new_thread (struct lwp_info *lp) override; | |
f6ac5f3d PA |
322 | }; |
323 | ||
324 | static ppc_linux_nat_target the_ppc_linux_nat_target; | |
325 | ||
16333c4f EZ |
326 | /* *INDENT-OFF* */ |
327 | /* registers layout, as presented by the ptrace interface: | |
328 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
329 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
330 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
331 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
332 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
333 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
334 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
335 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
336 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
337 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
338 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
339 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f EZ |
340 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
341 | /* *INDENT_ON * */ | |
c877c8e6 | 342 | |
45229ea4 | 343 | static int |
e101270f | 344 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 345 | { |
16333c4f | 346 | int u_addr = -1; |
e101270f | 347 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
348 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
349 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 350 | int wordsize = sizeof (long); |
16333c4f | 351 | |
0df8b418 | 352 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
353 | if (regno >= tdep->ppc_gp0_regnum |
354 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 355 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 356 | |
49ff75ad JB |
357 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
358 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
359 | slot each in 64-bit interface. */ | |
383f0f5b JB |
360 | if (tdep->ppc_fp0_regnum >= 0 |
361 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
362 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
363 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 364 | |
0df8b418 | 365 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 366 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 367 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 368 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 369 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 370 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 371 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 372 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 373 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 374 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 375 | u_addr = PT_CTR * wordsize; |
f8c59253 | 376 | #ifdef PT_MQ |
dc5cfeb6 | 377 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 378 | u_addr = PT_MQ * wordsize; |
f8c59253 | 379 | #endif |
dc5cfeb6 | 380 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 381 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
382 | if (regno == PPC_ORIG_R3_REGNUM) |
383 | u_addr = PT_ORIG_R3 * wordsize; | |
384 | if (regno == PPC_TRAP_REGNUM) | |
385 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
386 | if (tdep->ppc_fpscr_regnum >= 0 |
387 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
388 | { |
389 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
390 | kernel headers incorrectly contained the 32-bit definition of | |
391 | PT_FPSCR. For the 32-bit definition, floating-point | |
392 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 393 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
394 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
395 | hence no adjustment is necessary. Hack around this. */ | |
396 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
397 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
398 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
399 | slot and not just its second word. The PT_FPSCR supplied when | |
400 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
401 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
402 | && PT_FPSCR == (48 + 2*32 + 1)) | |
403 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
404 | else |
405 | u_addr = PT_FPSCR * wordsize; | |
406 | } | |
16333c4f | 407 | return u_addr; |
c877c8e6 KB |
408 | } |
409 | ||
604c2f83 LM |
410 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
411 | registers set mechanism, as opposed to the interface for all the | |
412 | other registers, that stores/fetches each register individually. */ | |
413 | static void | |
2c3305f6 | 414 | fetch_vsx_registers (struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
415 | { |
416 | int ret; | |
417 | gdb_vsxregset_t regs; | |
2c3305f6 | 418 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 LM |
419 | |
420 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
421 | if (ret < 0) | |
422 | { | |
423 | if (errno == EIO) | |
424 | { | |
425 | have_ptrace_getsetvsxregs = 0; | |
426 | return; | |
427 | } | |
2c3305f6 | 428 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
429 | } |
430 | ||
2c3305f6 PFC |
431 | vsxregset->supply_regset (vsxregset, regcache, regno, ®s, |
432 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
433 | } |
434 | ||
9abe5450 EZ |
435 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
436 | registers set mechanism, as opposed to the interface for all the | |
437 | other registers, that stores/fetches each register individually. */ | |
438 | static void | |
1d75a658 PFC |
439 | fetch_altivec_registers (struct regcache *regcache, int tid, |
440 | int regno) | |
9abe5450 EZ |
441 | { |
442 | int ret; | |
9abe5450 | 443 | gdb_vrregset_t regs; |
ac7936df | 444 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 445 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
446 | |
447 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
448 | if (ret < 0) | |
449 | { | |
450 | if (errno == EIO) | |
451 | { | |
452 | have_ptrace_getvrregs = 0; | |
453 | return; | |
454 | } | |
1d75a658 | 455 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 456 | } |
1d75a658 PFC |
457 | |
458 | vrregset->supply_regset (vrregset, regcache, regno, ®s, | |
459 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
460 | } |
461 | ||
01904826 JB |
462 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
463 | SPE-specific registers, and place the results in EVRREGSET. If we | |
464 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
465 | zeros. | |
466 | ||
467 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
468 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
469 | set_spe_registers. */ | |
470 | static void | |
471 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
472 | { | |
473 | if (have_ptrace_getsetevrregs) | |
474 | { | |
475 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
476 | return; | |
477 | else | |
478 | { | |
479 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
480 | we just return zeros. */ | |
481 | if (errno == EIO) | |
482 | have_ptrace_getsetevrregs = 0; | |
483 | else | |
484 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 485 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
486 | } |
487 | } | |
488 | ||
489 | memset (evrregset, 0, sizeof (*evrregset)); | |
490 | } | |
491 | ||
6ced10dd JB |
492 | /* Supply values from TID for SPE-specific raw registers: the upper |
493 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
494 | be the number of an upper half register, acc, spefscr, or -1 to | |
495 | supply the values of all registers. */ | |
01904826 | 496 | static void |
56be3814 | 497 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 498 | { |
ac7936df | 499 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 500 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
501 | struct gdb_evrregset_t evrregs; |
502 | ||
6ced10dd | 503 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 504 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 505 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 506 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 507 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 508 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 509 | |
01904826 JB |
510 | get_spe_registers (tid, &evrregs); |
511 | ||
6ced10dd | 512 | if (regno == -1) |
01904826 | 513 | { |
6ced10dd JB |
514 | int i; |
515 | ||
516 | for (i = 0; i < ppc_num_gprs; i++) | |
73e1c03f | 517 | regcache->raw_supply (tdep->ppc_ev0_upper_regnum + i, &evrregs.evr[i]); |
01904826 | 518 | } |
6ced10dd JB |
519 | else if (tdep->ppc_ev0_upper_regnum <= regno |
520 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
73e1c03f SM |
521 | regcache->raw_supply (regno, |
522 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
523 | |
524 | if (regno == -1 | |
525 | || regno == tdep->ppc_acc_regnum) | |
73e1c03f | 526 | regcache->raw_supply (tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
527 | |
528 | if (regno == -1 | |
529 | || regno == tdep->ppc_spefscr_regnum) | |
73e1c03f | 530 | regcache->raw_supply (tdep->ppc_spefscr_regnum, &evrregs.spefscr); |
01904826 JB |
531 | } |
532 | ||
7ca18ed6 EBM |
533 | /* Use ptrace to fetch all registers from the register set with note |
534 | type REGSET_ID, size REGSIZE, and layout described by REGSET, from | |
535 | process/thread TID and supply their values to REGCACHE. If ptrace | |
536 | returns ENODATA to indicate the regset is unavailable, mark the | |
537 | registers as unavailable in REGCACHE. */ | |
538 | ||
539 | static void | |
540 | fetch_regset (struct regcache *regcache, int tid, | |
541 | int regset_id, int regsetsize, const struct regset *regset) | |
542 | { | |
543 | void *buf = alloca (regsetsize); | |
544 | struct iovec iov; | |
545 | ||
546 | iov.iov_base = buf; | |
547 | iov.iov_len = regsetsize; | |
548 | ||
549 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) | |
550 | { | |
551 | if (errno == ENODATA) | |
552 | regset->supply_regset (regset, regcache, -1, NULL, regsetsize); | |
553 | else | |
554 | perror_with_name (_("Couldn't get register set")); | |
555 | } | |
556 | else | |
557 | regset->supply_regset (regset, regcache, -1, buf, regsetsize); | |
558 | } | |
559 | ||
560 | /* Use ptrace to store register REGNUM of the regset with note type | |
561 | REGSET_ID, size REGSETSIZE, and layout described by REGSET, from | |
562 | REGCACHE back to process/thread TID. If REGNUM is -1 all registers | |
563 | in the set are collected and stored. */ | |
564 | ||
565 | static void | |
566 | store_regset (const struct regcache *regcache, int tid, int regnum, | |
567 | int regset_id, int regsetsize, const struct regset *regset) | |
568 | { | |
569 | void *buf = alloca (regsetsize); | |
570 | struct iovec iov; | |
571 | ||
572 | iov.iov_base = buf; | |
573 | iov.iov_len = regsetsize; | |
574 | ||
575 | /* Make sure that the buffer that will be stored has up to date values | |
576 | for the registers that won't be collected. */ | |
577 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) | |
578 | perror_with_name (_("Couldn't get register set")); | |
579 | ||
580 | regset->collect_regset (regset, regcache, regnum, buf, regsetsize); | |
581 | ||
582 | if (ptrace (PTRACE_SETREGSET, tid, regset_id, &iov) < 0) | |
583 | perror_with_name (_("Couldn't set register set")); | |
584 | } | |
585 | ||
586 | /* Check whether the kernel provides a register set with number | |
587 | REGSET_ID of size REGSETSIZE for process/thread TID. */ | |
588 | ||
589 | static bool | |
590 | check_regset (int tid, int regset_id, int regsetsize) | |
591 | { | |
592 | void *buf = alloca (regsetsize); | |
593 | struct iovec iov; | |
594 | ||
595 | iov.iov_base = buf; | |
596 | iov.iov_len = regsetsize; | |
597 | ||
598 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0 | |
599 | || errno == ENODATA) | |
600 | return true; | |
601 | else | |
602 | return false; | |
603 | } | |
604 | ||
45229ea4 | 605 | static void |
56be3814 | 606 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 607 | { |
ac7936df | 608 | struct gdbarch *gdbarch = regcache->arch (); |
7ca18ed6 | 609 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
45229ea4 | 610 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 611 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 612 | int bytes_transferred; |
0f068fb5 | 613 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 614 | |
be8626e0 | 615 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
616 | { |
617 | /* If this is the first time through, or if it is not the first | |
618 | time through, and we have comfirmed that there is kernel | |
619 | support for such a ptrace request, then go and fetch the | |
620 | register. */ | |
621 | if (have_ptrace_getvrregs) | |
622 | { | |
1d75a658 | 623 | fetch_altivec_registers (regcache, tid, regno); |
9abe5450 EZ |
624 | return; |
625 | } | |
626 | /* If we have discovered that there is no ptrace support for | |
627 | AltiVec registers, fall through and return zeroes, because | |
628 | regaddr will be -1 in this case. */ | |
629 | } | |
3d907528 | 630 | else if (vsx_register_p (gdbarch, regno)) |
604c2f83 LM |
631 | { |
632 | if (have_ptrace_getsetvsxregs) | |
633 | { | |
2c3305f6 | 634 | fetch_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
635 | return; |
636 | } | |
637 | } | |
be8626e0 | 638 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 639 | { |
56be3814 | 640 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
641 | return; |
642 | } | |
7ca18ed6 EBM |
643 | else if (regno == PPC_DSCR_REGNUM) |
644 | { | |
645 | gdb_assert (tdep->ppc_dscr_regnum != -1); | |
646 | ||
647 | fetch_regset (regcache, tid, NT_PPC_DSCR, | |
648 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
649 | &ppc32_linux_dscrregset); | |
650 | return; | |
651 | } | |
652 | else if (regno == PPC_PPR_REGNUM) | |
653 | { | |
654 | gdb_assert (tdep->ppc_ppr_regnum != -1); | |
655 | ||
656 | fetch_regset (regcache, tid, NT_PPC_PPR, | |
657 | PPC_LINUX_SIZEOF_PPRREGSET, | |
658 | &ppc32_linux_pprregset); | |
659 | return; | |
660 | } | |
f2cf6173 EBM |
661 | else if (regno == PPC_TAR_REGNUM) |
662 | { | |
663 | gdb_assert (tdep->ppc_tar_regnum != -1); | |
664 | ||
665 | fetch_regset (regcache, tid, NT_PPC_TAR, | |
666 | PPC_LINUX_SIZEOF_TARREGSET, | |
667 | &ppc32_linux_tarregset); | |
668 | return; | |
669 | } | |
232bfb86 EBM |
670 | else if (PPC_IS_EBB_REGNUM (regno)) |
671 | { | |
672 | gdb_assert (tdep->have_ebb); | |
673 | ||
674 | fetch_regset (regcache, tid, NT_PPC_EBB, | |
675 | PPC_LINUX_SIZEOF_EBBREGSET, | |
676 | &ppc32_linux_ebbregset); | |
677 | return; | |
678 | } | |
679 | else if (PPC_IS_PMU_REGNUM (regno)) | |
680 | { | |
681 | gdb_assert (tdep->ppc_mmcr0_regnum != -1); | |
682 | ||
683 | fetch_regset (regcache, tid, NT_PPC_PMU, | |
684 | PPC_LINUX_SIZEOF_PMUREGSET, | |
685 | &ppc32_linux_pmuregset); | |
686 | return; | |
687 | } | |
8d619c01 EBM |
688 | else if (PPC_IS_TMSPR_REGNUM (regno)) |
689 | { | |
690 | gdb_assert (tdep->have_htm_spr); | |
691 | ||
692 | fetch_regset (regcache, tid, NT_PPC_TM_SPR, | |
693 | PPC_LINUX_SIZEOF_TM_SPRREGSET, | |
694 | &ppc32_linux_tm_sprregset); | |
695 | return; | |
696 | } | |
697 | else if (PPC_IS_CKPTGP_REGNUM (regno)) | |
698 | { | |
699 | gdb_assert (tdep->have_htm_core); | |
700 | ||
701 | const struct regset *cgprregset = ppc_linux_cgprregset (gdbarch); | |
702 | fetch_regset (regcache, tid, NT_PPC_TM_CGPR, | |
703 | (tdep->wordsize == 4? | |
704 | PPC32_LINUX_SIZEOF_CGPRREGSET | |
705 | : PPC64_LINUX_SIZEOF_CGPRREGSET), | |
706 | cgprregset); | |
707 | return; | |
708 | } | |
709 | else if (PPC_IS_CKPTFP_REGNUM (regno)) | |
710 | { | |
711 | gdb_assert (tdep->have_htm_fpu); | |
712 | ||
713 | fetch_regset (regcache, tid, NT_PPC_TM_CFPR, | |
714 | PPC_LINUX_SIZEOF_CFPRREGSET, | |
715 | &ppc32_linux_cfprregset); | |
716 | return; | |
717 | } | |
718 | else if (PPC_IS_CKPTVMX_REGNUM (regno)) | |
719 | { | |
720 | gdb_assert (tdep->have_htm_altivec); | |
721 | ||
722 | const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch); | |
723 | fetch_regset (regcache, tid, NT_PPC_TM_CVMX, | |
724 | PPC_LINUX_SIZEOF_CVMXREGSET, | |
725 | cvmxregset); | |
726 | return; | |
727 | } | |
728 | else if (PPC_IS_CKPTVSX_REGNUM (regno)) | |
729 | { | |
730 | gdb_assert (tdep->have_htm_vsx); | |
731 | ||
732 | fetch_regset (regcache, tid, NT_PPC_TM_CVSX, | |
733 | PPC_LINUX_SIZEOF_CVSXREGSET, | |
734 | &ppc32_linux_cvsxregset); | |
735 | return; | |
736 | } | |
737 | else if (regno == PPC_CPPR_REGNUM) | |
738 | { | |
739 | gdb_assert (tdep->ppc_cppr_regnum != -1); | |
740 | ||
741 | fetch_regset (regcache, tid, NT_PPC_TM_CPPR, | |
742 | PPC_LINUX_SIZEOF_CPPRREGSET, | |
743 | &ppc32_linux_cpprregset); | |
744 | return; | |
745 | } | |
746 | else if (regno == PPC_CDSCR_REGNUM) | |
747 | { | |
748 | gdb_assert (tdep->ppc_cdscr_regnum != -1); | |
749 | ||
750 | fetch_regset (regcache, tid, NT_PPC_TM_CDSCR, | |
751 | PPC_LINUX_SIZEOF_CDSCRREGSET, | |
752 | &ppc32_linux_cdscrregset); | |
753 | return; | |
754 | } | |
755 | else if (regno == PPC_CTAR_REGNUM) | |
756 | { | |
757 | gdb_assert (tdep->ppc_ctar_regnum != -1); | |
758 | ||
759 | fetch_regset (regcache, tid, NT_PPC_TM_CTAR, | |
760 | PPC_LINUX_SIZEOF_CTARREGSET, | |
761 | &ppc32_linux_ctarregset); | |
762 | return; | |
763 | } | |
9abe5450 | 764 | |
45229ea4 EZ |
765 | if (regaddr == -1) |
766 | { | |
40a6adc1 | 767 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
73e1c03f | 768 | regcache->raw_supply (regno, buf); |
45229ea4 EZ |
769 | return; |
770 | } | |
771 | ||
411cb3f9 | 772 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
773 | 32-bit platform, 64-bit floating-point registers will require two |
774 | transfers. */ | |
4a19ea35 | 775 | for (bytes_transferred = 0; |
40a6adc1 | 776 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 777 | bytes_transferred += sizeof (long)) |
45229ea4 | 778 | { |
11fde611 JK |
779 | long l; |
780 | ||
45229ea4 | 781 | errno = 0; |
11fde611 | 782 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 783 | regaddr += sizeof (long); |
45229ea4 EZ |
784 | if (errno != 0) |
785 | { | |
bc97b3ba | 786 | char message[128]; |
8c042590 PM |
787 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
788 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 789 | perror_with_name (message); |
45229ea4 | 790 | } |
11fde611 | 791 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 792 | } |
56d0d96a | 793 | |
4a19ea35 JB |
794 | /* Now supply the register. Keep in mind that the regcache's idea |
795 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 796 | (long). */ |
40a6adc1 | 797 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
798 | { |
799 | /* Little-endian values are always found at the left end of the | |
800 | bytes transferred. */ | |
73e1c03f | 801 | regcache->raw_supply (regno, buf); |
4a19ea35 | 802 | } |
40a6adc1 | 803 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
804 | { |
805 | /* Big-endian values are found at the right end of the bytes | |
806 | transferred. */ | |
40a6adc1 | 807 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
73e1c03f | 808 | regcache->raw_supply (regno, buf + padding); |
4a19ea35 JB |
809 | } |
810 | else | |
a44bddec | 811 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 812 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 813 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
814 | } |
815 | ||
1dfe79e8 SDJ |
816 | /* This function actually issues the request to ptrace, telling |
817 | it to get all general-purpose registers and put them into the | |
818 | specified regset. | |
819 | ||
820 | If the ptrace request does not exist, this function returns 0 | |
821 | and properly sets the have_ptrace_* flag. If the request fails, | |
822 | this function calls perror_with_name. Otherwise, if the request | |
823 | succeeds, then the regcache gets filled and 1 is returned. */ | |
824 | static int | |
825 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
826 | { | |
1dfe79e8 SDJ |
827 | gdb_gregset_t gregset; |
828 | ||
829 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
830 | { | |
831 | if (errno == EIO) | |
832 | { | |
833 | have_ptrace_getsetregs = 0; | |
834 | return 0; | |
835 | } | |
836 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
837 | } | |
838 | ||
839 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
840 | ||
841 | return 1; | |
842 | } | |
843 | ||
844 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
845 | responsible for verifying if this target has the ptrace request | |
846 | that can be used to fetch all general-purpose registers at one | |
847 | shot. If it doesn't, then we should fetch them using the | |
848 | old-fashioned way, which is to iterate over the registers and | |
849 | request them one by one. */ | |
850 | static void | |
851 | fetch_gp_regs (struct regcache *regcache, int tid) | |
852 | { | |
ac7936df | 853 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
854 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
855 | int i; | |
856 | ||
857 | if (have_ptrace_getsetregs) | |
858 | if (fetch_all_gp_regs (regcache, tid)) | |
859 | return; | |
860 | ||
861 | /* If we've hit this point, it doesn't really matter which | |
862 | architecture we are using. We just need to read the | |
863 | registers in the "old-fashioned way". */ | |
864 | for (i = 0; i < ppc_num_gprs; i++) | |
865 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
866 | } | |
867 | ||
868 | /* This function actually issues the request to ptrace, telling | |
869 | it to get all floating-point registers and put them into the | |
870 | specified regset. | |
871 | ||
872 | If the ptrace request does not exist, this function returns 0 | |
873 | and properly sets the have_ptrace_* flag. If the request fails, | |
874 | this function calls perror_with_name. Otherwise, if the request | |
875 | succeeds, then the regcache gets filled and 1 is returned. */ | |
876 | static int | |
877 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
878 | { | |
879 | gdb_fpregset_t fpregs; | |
880 | ||
881 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
882 | { | |
883 | if (errno == EIO) | |
884 | { | |
885 | have_ptrace_getsetfpregs = 0; | |
886 | return 0; | |
887 | } | |
888 | perror_with_name (_("Couldn't get floating-point registers.")); | |
889 | } | |
890 | ||
891 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
892 | ||
893 | return 1; | |
894 | } | |
895 | ||
896 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
897 | responsible for verifying if this target has the ptrace request | |
898 | that can be used to fetch all floating-point registers at one | |
899 | shot. If it doesn't, then we should fetch them using the | |
900 | old-fashioned way, which is to iterate over the registers and | |
901 | request them one by one. */ | |
902 | static void | |
903 | fetch_fp_regs (struct regcache *regcache, int tid) | |
904 | { | |
ac7936df | 905 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
906 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
907 | int i; | |
908 | ||
909 | if (have_ptrace_getsetfpregs) | |
910 | if (fetch_all_fp_regs (regcache, tid)) | |
911 | return; | |
912 | ||
913 | /* If we've hit this point, it doesn't really matter which | |
914 | architecture we are using. We just need to read the | |
915 | registers in the "old-fashioned way". */ | |
916 | for (i = 0; i < ppc_num_fprs; i++) | |
917 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
918 | } | |
919 | ||
45229ea4 | 920 | static void |
56be3814 | 921 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 | 922 | { |
ac7936df | 923 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 924 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9abe5450 | 925 | |
1dfe79e8 | 926 | fetch_gp_regs (regcache, tid); |
32b99774 | 927 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 928 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 929 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 930 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 931 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 932 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 933 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 934 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 935 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 936 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 937 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 938 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 939 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 940 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 941 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
942 | if (ppc_linux_trap_reg_p (gdbarch)) |
943 | { | |
944 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
945 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
946 | } | |
32b99774 | 947 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 948 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
949 | if (have_ptrace_getvrregs) |
950 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 951 | fetch_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
952 | if (have_ptrace_getsetvsxregs) |
953 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 954 | fetch_vsx_registers (regcache, tid, -1); |
6ced10dd | 955 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 956 | fetch_spe_register (regcache, tid, -1); |
7ca18ed6 EBM |
957 | if (tdep->ppc_ppr_regnum != -1) |
958 | fetch_regset (regcache, tid, NT_PPC_PPR, | |
959 | PPC_LINUX_SIZEOF_PPRREGSET, | |
960 | &ppc32_linux_pprregset); | |
961 | if (tdep->ppc_dscr_regnum != -1) | |
962 | fetch_regset (regcache, tid, NT_PPC_DSCR, | |
963 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
964 | &ppc32_linux_dscrregset); | |
f2cf6173 EBM |
965 | if (tdep->ppc_tar_regnum != -1) |
966 | fetch_regset (regcache, tid, NT_PPC_TAR, | |
967 | PPC_LINUX_SIZEOF_TARREGSET, | |
968 | &ppc32_linux_tarregset); | |
232bfb86 EBM |
969 | if (tdep->have_ebb) |
970 | fetch_regset (regcache, tid, NT_PPC_EBB, | |
971 | PPC_LINUX_SIZEOF_EBBREGSET, | |
972 | &ppc32_linux_ebbregset); | |
973 | if (tdep->ppc_mmcr0_regnum != -1) | |
974 | fetch_regset (regcache, tid, NT_PPC_PMU, | |
975 | PPC_LINUX_SIZEOF_PMUREGSET, | |
976 | &ppc32_linux_pmuregset); | |
8d619c01 EBM |
977 | if (tdep->have_htm_spr) |
978 | fetch_regset (regcache, tid, NT_PPC_TM_SPR, | |
979 | PPC_LINUX_SIZEOF_TM_SPRREGSET, | |
980 | &ppc32_linux_tm_sprregset); | |
981 | if (tdep->have_htm_core) | |
982 | { | |
983 | const struct regset *cgprregset = ppc_linux_cgprregset (gdbarch); | |
984 | fetch_regset (regcache, tid, NT_PPC_TM_CGPR, | |
985 | (tdep->wordsize == 4? | |
986 | PPC32_LINUX_SIZEOF_CGPRREGSET | |
987 | : PPC64_LINUX_SIZEOF_CGPRREGSET), | |
988 | cgprregset); | |
989 | } | |
990 | if (tdep->have_htm_fpu) | |
991 | fetch_regset (regcache, tid, NT_PPC_TM_CFPR, | |
992 | PPC_LINUX_SIZEOF_CFPRREGSET, | |
993 | &ppc32_linux_cfprregset); | |
994 | if (tdep->have_htm_altivec) | |
995 | { | |
996 | const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch); | |
997 | fetch_regset (regcache, tid, NT_PPC_TM_CVMX, | |
998 | PPC_LINUX_SIZEOF_CVMXREGSET, | |
999 | cvmxregset); | |
1000 | } | |
1001 | if (tdep->have_htm_vsx) | |
1002 | fetch_regset (regcache, tid, NT_PPC_TM_CVSX, | |
1003 | PPC_LINUX_SIZEOF_CVSXREGSET, | |
1004 | &ppc32_linux_cvsxregset); | |
1005 | if (tdep->ppc_cppr_regnum != -1) | |
1006 | fetch_regset (regcache, tid, NT_PPC_TM_CPPR, | |
1007 | PPC_LINUX_SIZEOF_CPPRREGSET, | |
1008 | &ppc32_linux_cpprregset); | |
1009 | if (tdep->ppc_cdscr_regnum != -1) | |
1010 | fetch_regset (regcache, tid, NT_PPC_TM_CDSCR, | |
1011 | PPC_LINUX_SIZEOF_CDSCRREGSET, | |
1012 | &ppc32_linux_cdscrregset); | |
1013 | if (tdep->ppc_ctar_regnum != -1) | |
1014 | fetch_regset (regcache, tid, NT_PPC_TM_CTAR, | |
1015 | PPC_LINUX_SIZEOF_CTARREGSET, | |
1016 | &ppc32_linux_ctarregset); | |
45229ea4 EZ |
1017 | } |
1018 | ||
1019 | /* Fetch registers from the child process. Fetch all registers if | |
1020 | regno == -1, otherwise fetch all general registers or all floating | |
1021 | point registers depending upon the value of regno. */ | |
f6ac5f3d PA |
1022 | void |
1023 | ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
45229ea4 | 1024 | { |
222312d3 | 1025 | pid_t tid = get_ptrace_pid (regcache->ptid ()); |
05f13b9c | 1026 | |
9abe5450 | 1027 | if (regno == -1) |
56be3814 | 1028 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 1029 | else |
56be3814 | 1030 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
1031 | } |
1032 | ||
604c2f83 | 1033 | static void |
2c3305f6 | 1034 | store_vsx_registers (const struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
1035 | { |
1036 | int ret; | |
1037 | gdb_vsxregset_t regs; | |
2c3305f6 | 1038 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 | 1039 | |
9fe70b4f | 1040 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
1041 | if (ret < 0) |
1042 | { | |
1043 | if (errno == EIO) | |
1044 | { | |
1045 | have_ptrace_getsetvsxregs = 0; | |
1046 | return; | |
1047 | } | |
2c3305f6 | 1048 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
1049 | } |
1050 | ||
2c3305f6 PFC |
1051 | vsxregset->collect_regset (vsxregset, regcache, regno, ®s, |
1052 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
1053 | |
1054 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
1055 | if (ret < 0) | |
2c3305f6 | 1056 | perror_with_name (_("Unable to store VSX registers")); |
604c2f83 LM |
1057 | } |
1058 | ||
9abe5450 | 1059 | static void |
1d75a658 PFC |
1060 | store_altivec_registers (const struct regcache *regcache, int tid, |
1061 | int regno) | |
9abe5450 EZ |
1062 | { |
1063 | int ret; | |
9abe5450 | 1064 | gdb_vrregset_t regs; |
ac7936df | 1065 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 1066 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
1067 | |
1068 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
1069 | if (ret < 0) | |
1070 | { | |
1071 | if (errno == EIO) | |
1072 | { | |
1073 | have_ptrace_getvrregs = 0; | |
1074 | return; | |
1075 | } | |
1d75a658 | 1076 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 EZ |
1077 | } |
1078 | ||
1d75a658 PFC |
1079 | vrregset->collect_regset (vrregset, regcache, regno, ®s, |
1080 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
1081 | |
1082 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
1083 | if (ret < 0) | |
1d75a658 | 1084 | perror_with_name (_("Unable to store AltiVec registers")); |
9abe5450 EZ |
1085 | } |
1086 | ||
01904826 JB |
1087 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
1088 | general-purpose registers and its SPE-specific registers to the | |
1089 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
1090 | nothing. | |
1091 | ||
1092 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
1093 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
1094 | get_spe_registers. */ | |
1095 | static void | |
1096 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
1097 | { | |
1098 | if (have_ptrace_getsetevrregs) | |
1099 | { | |
1100 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
1101 | return; | |
1102 | else | |
1103 | { | |
1104 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
1105 | supported; we fail silently, and don't try the call | |
1106 | again. */ | |
1107 | if (errno == EIO) | |
1108 | have_ptrace_getsetevrregs = 0; | |
1109 | else | |
1110 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 1111 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
1112 | } |
1113 | } | |
1114 | } | |
1115 | ||
6ced10dd JB |
1116 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
1117 | If REGNO is -1, write the values of all the SPE-specific | |
1118 | registers. */ | |
01904826 | 1119 | static void |
56be3814 | 1120 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 1121 | { |
ac7936df | 1122 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1123 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
1124 | struct gdb_evrregset_t evrregs; |
1125 | ||
6ced10dd | 1126 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 1127 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 1128 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 1129 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 1130 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 1131 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 1132 | |
6ced10dd JB |
1133 | if (regno == -1) |
1134 | /* Since we're going to write out every register, the code below | |
1135 | should store to every field of evrregs; if that doesn't happen, | |
1136 | make it obvious by initializing it with suspicious values. */ | |
1137 | memset (&evrregs, 42, sizeof (evrregs)); | |
1138 | else | |
1139 | /* We can only read and write the entire EVR register set at a | |
1140 | time, so to write just a single register, we do a | |
1141 | read-modify-write maneuver. */ | |
1142 | get_spe_registers (tid, &evrregs); | |
1143 | ||
1144 | if (regno == -1) | |
01904826 | 1145 | { |
6ced10dd JB |
1146 | int i; |
1147 | ||
1148 | for (i = 0; i < ppc_num_gprs; i++) | |
34a79281 SM |
1149 | regcache->raw_collect (tdep->ppc_ev0_upper_regnum + i, |
1150 | &evrregs.evr[i]); | |
01904826 | 1151 | } |
6ced10dd JB |
1152 | else if (tdep->ppc_ev0_upper_regnum <= regno |
1153 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
34a79281 SM |
1154 | regcache->raw_collect (regno, |
1155 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
1156 | |
1157 | if (regno == -1 | |
1158 | || regno == tdep->ppc_acc_regnum) | |
34a79281 SM |
1159 | regcache->raw_collect (tdep->ppc_acc_regnum, |
1160 | &evrregs.acc); | |
6ced10dd JB |
1161 | |
1162 | if (regno == -1 | |
1163 | || regno == tdep->ppc_spefscr_regnum) | |
34a79281 SM |
1164 | regcache->raw_collect (tdep->ppc_spefscr_regnum, |
1165 | &evrregs.spefscr); | |
01904826 JB |
1166 | |
1167 | /* Write back the modified register set. */ | |
1168 | set_spe_registers (tid, &evrregs); | |
1169 | } | |
1170 | ||
45229ea4 | 1171 | static void |
56be3814 | 1172 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1173 | { |
ac7936df | 1174 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1175 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
45229ea4 | 1176 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 1177 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 1178 | int i; |
4a19ea35 | 1179 | size_t bytes_to_transfer; |
0f068fb5 | 1180 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 1181 | |
be8626e0 | 1182 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 1183 | { |
1d75a658 | 1184 | store_altivec_registers (regcache, tid, regno); |
45229ea4 EZ |
1185 | return; |
1186 | } | |
3d907528 | 1187 | else if (vsx_register_p (gdbarch, regno)) |
604c2f83 | 1188 | { |
2c3305f6 | 1189 | store_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
1190 | return; |
1191 | } | |
be8626e0 | 1192 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 1193 | { |
56be3814 | 1194 | store_spe_register (regcache, tid, regno); |
01904826 JB |
1195 | return; |
1196 | } | |
7ca18ed6 EBM |
1197 | else if (regno == PPC_DSCR_REGNUM) |
1198 | { | |
1199 | gdb_assert (tdep->ppc_dscr_regnum != -1); | |
1200 | ||
1201 | store_regset (regcache, tid, regno, NT_PPC_DSCR, | |
1202 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
1203 | &ppc32_linux_dscrregset); | |
1204 | return; | |
1205 | } | |
1206 | else if (regno == PPC_PPR_REGNUM) | |
1207 | { | |
1208 | gdb_assert (tdep->ppc_ppr_regnum != -1); | |
1209 | ||
1210 | store_regset (regcache, tid, regno, NT_PPC_PPR, | |
1211 | PPC_LINUX_SIZEOF_PPRREGSET, | |
1212 | &ppc32_linux_pprregset); | |
1213 | return; | |
1214 | } | |
f2cf6173 EBM |
1215 | else if (regno == PPC_TAR_REGNUM) |
1216 | { | |
1217 | gdb_assert (tdep->ppc_tar_regnum != -1); | |
1218 | ||
1219 | store_regset (regcache, tid, regno, NT_PPC_TAR, | |
1220 | PPC_LINUX_SIZEOF_TARREGSET, | |
1221 | &ppc32_linux_tarregset); | |
1222 | return; | |
1223 | } | |
232bfb86 EBM |
1224 | else if (PPC_IS_EBB_REGNUM (regno)) |
1225 | { | |
1226 | gdb_assert (tdep->have_ebb); | |
1227 | ||
1228 | store_regset (regcache, tid, regno, NT_PPC_EBB, | |
1229 | PPC_LINUX_SIZEOF_EBBREGSET, | |
1230 | &ppc32_linux_ebbregset); | |
1231 | return; | |
1232 | } | |
1233 | else if (PPC_IS_PMU_REGNUM (regno)) | |
1234 | { | |
1235 | gdb_assert (tdep->ppc_mmcr0_regnum != -1); | |
1236 | ||
1237 | store_regset (regcache, tid, regno, NT_PPC_PMU, | |
1238 | PPC_LINUX_SIZEOF_PMUREGSET, | |
1239 | &ppc32_linux_pmuregset); | |
1240 | return; | |
1241 | } | |
8d619c01 EBM |
1242 | else if (PPC_IS_TMSPR_REGNUM (regno)) |
1243 | { | |
1244 | gdb_assert (tdep->have_htm_spr); | |
1245 | ||
1246 | store_regset (regcache, tid, regno, NT_PPC_TM_SPR, | |
1247 | PPC_LINUX_SIZEOF_TM_SPRREGSET, | |
1248 | &ppc32_linux_tm_sprregset); | |
1249 | return; | |
1250 | } | |
1251 | else if (PPC_IS_CKPTGP_REGNUM (regno)) | |
1252 | { | |
1253 | gdb_assert (tdep->have_htm_core); | |
1254 | ||
1255 | const struct regset *cgprregset = ppc_linux_cgprregset (gdbarch); | |
1256 | store_regset (regcache, tid, regno, NT_PPC_TM_CGPR, | |
1257 | (tdep->wordsize == 4? | |
1258 | PPC32_LINUX_SIZEOF_CGPRREGSET | |
1259 | : PPC64_LINUX_SIZEOF_CGPRREGSET), | |
1260 | cgprregset); | |
1261 | return; | |
1262 | } | |
1263 | else if (PPC_IS_CKPTFP_REGNUM (regno)) | |
1264 | { | |
1265 | gdb_assert (tdep->have_htm_fpu); | |
1266 | ||
1267 | store_regset (regcache, tid, regno, NT_PPC_TM_CFPR, | |
1268 | PPC_LINUX_SIZEOF_CFPRREGSET, | |
1269 | &ppc32_linux_cfprregset); | |
1270 | return; | |
1271 | } | |
1272 | else if (PPC_IS_CKPTVMX_REGNUM (regno)) | |
1273 | { | |
1274 | gdb_assert (tdep->have_htm_altivec); | |
1275 | ||
1276 | const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch); | |
1277 | store_regset (regcache, tid, regno, NT_PPC_TM_CVMX, | |
1278 | PPC_LINUX_SIZEOF_CVMXREGSET, | |
1279 | cvmxregset); | |
1280 | return; | |
1281 | } | |
1282 | else if (PPC_IS_CKPTVSX_REGNUM (regno)) | |
1283 | { | |
1284 | gdb_assert (tdep->have_htm_vsx); | |
1285 | ||
1286 | store_regset (regcache, tid, regno, NT_PPC_TM_CVSX, | |
1287 | PPC_LINUX_SIZEOF_CVSXREGSET, | |
1288 | &ppc32_linux_cvsxregset); | |
1289 | return; | |
1290 | } | |
1291 | else if (regno == PPC_CPPR_REGNUM) | |
1292 | { | |
1293 | gdb_assert (tdep->ppc_cppr_regnum != -1); | |
1294 | ||
1295 | store_regset (regcache, tid, regno, NT_PPC_TM_CPPR, | |
1296 | PPC_LINUX_SIZEOF_CPPRREGSET, | |
1297 | &ppc32_linux_cpprregset); | |
1298 | return; | |
1299 | } | |
1300 | else if (regno == PPC_CDSCR_REGNUM) | |
1301 | { | |
1302 | gdb_assert (tdep->ppc_cdscr_regnum != -1); | |
1303 | ||
1304 | store_regset (regcache, tid, regno, NT_PPC_TM_CDSCR, | |
1305 | PPC_LINUX_SIZEOF_CDSCRREGSET, | |
1306 | &ppc32_linux_cdscrregset); | |
1307 | return; | |
1308 | } | |
1309 | else if (regno == PPC_CTAR_REGNUM) | |
1310 | { | |
1311 | gdb_assert (tdep->ppc_ctar_regnum != -1); | |
1312 | ||
1313 | store_regset (regcache, tid, regno, NT_PPC_TM_CTAR, | |
1314 | PPC_LINUX_SIZEOF_CTARREGSET, | |
1315 | &ppc32_linux_ctarregset); | |
1316 | return; | |
1317 | } | |
45229ea4 | 1318 | |
9abe5450 EZ |
1319 | if (regaddr == -1) |
1320 | return; | |
1321 | ||
4a19ea35 JB |
1322 | /* First collect the register. Keep in mind that the regcache's |
1323 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1324 | (long). */ |
56d0d96a | 1325 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
1326 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
1327 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
1328 | { |
1329 | /* Little-endian values always sit at the left end of the buffer. */ | |
34a79281 | 1330 | regcache->raw_collect (regno, buf); |
4a19ea35 | 1331 | } |
40a6adc1 | 1332 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1333 | { |
1334 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 1335 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
34a79281 | 1336 | regcache->raw_collect (regno, buf + padding); |
4a19ea35 JB |
1337 | } |
1338 | ||
411cb3f9 | 1339 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 1340 | { |
11fde611 JK |
1341 | long l; |
1342 | ||
1343 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 1344 | errno = 0; |
11fde611 | 1345 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 1346 | regaddr += sizeof (long); |
e3f36dbd KB |
1347 | |
1348 | if (errno == EIO | |
7284e1be UW |
1349 | && (regno == tdep->ppc_fpscr_regnum |
1350 | || regno == PPC_ORIG_R3_REGNUM | |
1351 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1352 | { |
7284e1be UW |
1353 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1354 | or trap to be written. */ | |
e3f36dbd KB |
1355 | continue; |
1356 | } | |
1357 | ||
45229ea4 EZ |
1358 | if (errno != 0) |
1359 | { | |
bc97b3ba | 1360 | char message[128]; |
8c042590 PM |
1361 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
1362 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 1363 | perror_with_name (message); |
45229ea4 EZ |
1364 | } |
1365 | } | |
1366 | } | |
1367 | ||
1dfe79e8 SDJ |
1368 | /* This function actually issues the request to ptrace, telling |
1369 | it to store all general-purpose registers present in the specified | |
1370 | regset. | |
1371 | ||
1372 | If the ptrace request does not exist, this function returns 0 | |
1373 | and properly sets the have_ptrace_* flag. If the request fails, | |
1374 | this function calls perror_with_name. Otherwise, if the request | |
1375 | succeeds, then the regcache is stored and 1 is returned. */ | |
1376 | static int | |
1377 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1378 | { | |
1dfe79e8 SDJ |
1379 | gdb_gregset_t gregset; |
1380 | ||
1381 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1382 | { | |
1383 | if (errno == EIO) | |
1384 | { | |
1385 | have_ptrace_getsetregs = 0; | |
1386 | return 0; | |
1387 | } | |
1388 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1389 | } | |
1390 | ||
1391 | fill_gregset (regcache, &gregset, regno); | |
1392 | ||
1393 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1394 | { | |
1395 | if (errno == EIO) | |
1396 | { | |
1397 | have_ptrace_getsetregs = 0; | |
1398 | return 0; | |
1399 | } | |
1400 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1401 | } | |
1402 | ||
1403 | return 1; | |
1404 | } | |
1405 | ||
1406 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1407 | responsible for verifying if this target has the ptrace request | |
1408 | that can be used to store all general-purpose registers at one | |
1409 | shot. If it doesn't, then we should store them using the | |
1410 | old-fashioned way, which is to iterate over the registers and | |
1411 | store them one by one. */ | |
45229ea4 | 1412 | static void |
1dfe79e8 | 1413 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1414 | { |
ac7936df | 1415 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1416 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dfe79e8 SDJ |
1417 | int i; |
1418 | ||
1419 | if (have_ptrace_getsetregs) | |
1420 | if (store_all_gp_regs (regcache, tid, regno)) | |
1421 | return; | |
1422 | ||
1423 | /* If we hit this point, it doesn't really matter which | |
1424 | architecture we are using. We just need to store the | |
1425 | registers in the "old-fashioned way". */ | |
6ced10dd | 1426 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1427 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1428 | } |
1429 | ||
1430 | /* This function actually issues the request to ptrace, telling | |
1431 | it to store all floating-point registers present in the specified | |
1432 | regset. | |
1433 | ||
1434 | If the ptrace request does not exist, this function returns 0 | |
1435 | and properly sets the have_ptrace_* flag. If the request fails, | |
1436 | this function calls perror_with_name. Otherwise, if the request | |
1437 | succeeds, then the regcache is stored and 1 is returned. */ | |
1438 | static int | |
1439 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1440 | { | |
1441 | gdb_fpregset_t fpregs; | |
1442 | ||
1443 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1444 | { | |
1445 | if (errno == EIO) | |
1446 | { | |
1447 | have_ptrace_getsetfpregs = 0; | |
1448 | return 0; | |
1449 | } | |
1450 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1451 | } | |
1452 | ||
1453 | fill_fpregset (regcache, &fpregs, regno); | |
1454 | ||
1455 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1456 | { | |
1457 | if (errno == EIO) | |
1458 | { | |
1459 | have_ptrace_getsetfpregs = 0; | |
1460 | return 0; | |
1461 | } | |
1462 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1463 | } | |
1464 | ||
1465 | return 1; | |
1466 | } | |
1467 | ||
1468 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1469 | responsible for verifying if this target has the ptrace request | |
1470 | that can be used to store all floating-point registers at one | |
1471 | shot. If it doesn't, then we should store them using the | |
1472 | old-fashioned way, which is to iterate over the registers and | |
1473 | store them one by one. */ | |
1474 | static void | |
1475 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1476 | { | |
ac7936df | 1477 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1478 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1479 | int i; | |
1480 | ||
1481 | if (have_ptrace_getsetfpregs) | |
1482 | if (store_all_fp_regs (regcache, tid, regno)) | |
1483 | return; | |
1484 | ||
1485 | /* If we hit this point, it doesn't really matter which | |
1486 | architecture we are using. We just need to store the | |
1487 | registers in the "old-fashioned way". */ | |
1488 | for (i = 0; i < ppc_num_fprs; i++) | |
1489 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1490 | } | |
1491 | ||
1492 | static void | |
1493 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1494 | { | |
ac7936df | 1495 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1496 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1497 | ||
1498 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1499 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1500 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1501 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1502 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1503 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1504 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1505 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1506 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1507 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1508 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1509 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1510 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1511 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1512 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1513 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1514 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1515 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1516 | if (ppc_linux_trap_reg_p (gdbarch)) |
1517 | { | |
1518 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1519 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1520 | } | |
9abe5450 EZ |
1521 | if (have_ptrace_getvrregs) |
1522 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 1523 | store_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
1524 | if (have_ptrace_getsetvsxregs) |
1525 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 1526 | store_vsx_registers (regcache, tid, -1); |
6ced10dd | 1527 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1528 | store_spe_register (regcache, tid, -1); |
7ca18ed6 EBM |
1529 | if (tdep->ppc_ppr_regnum != -1) |
1530 | store_regset (regcache, tid, -1, NT_PPC_PPR, | |
1531 | PPC_LINUX_SIZEOF_PPRREGSET, | |
1532 | &ppc32_linux_pprregset); | |
1533 | if (tdep->ppc_dscr_regnum != -1) | |
1534 | store_regset (regcache, tid, -1, NT_PPC_DSCR, | |
1535 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
1536 | &ppc32_linux_dscrregset); | |
f2cf6173 EBM |
1537 | if (tdep->ppc_tar_regnum != -1) |
1538 | store_regset (regcache, tid, -1, NT_PPC_TAR, | |
1539 | PPC_LINUX_SIZEOF_TARREGSET, | |
1540 | &ppc32_linux_tarregset); | |
232bfb86 EBM |
1541 | |
1542 | if (tdep->ppc_mmcr0_regnum != -1) | |
1543 | store_regset (regcache, tid, -1, NT_PPC_PMU, | |
1544 | PPC_LINUX_SIZEOF_PMUREGSET, | |
1545 | &ppc32_linux_pmuregset); | |
1546 | ||
8d619c01 EBM |
1547 | if (tdep->have_htm_spr) |
1548 | store_regset (regcache, tid, -1, NT_PPC_TM_SPR, | |
1549 | PPC_LINUX_SIZEOF_TM_SPRREGSET, | |
1550 | &ppc32_linux_tm_sprregset); | |
1551 | ||
1552 | /* Because the EBB and checkpointed HTM registers can be | |
1553 | unavailable, attempts to store them here would cause this | |
1554 | function to fail most of the time, so we ignore them. */ | |
45229ea4 EZ |
1555 | } |
1556 | ||
6ffbb7ab | 1557 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
0ec848ad | 1558 | static CORE_ADDR |
b261e0c5 | 1559 | ppc_linux_get_hwcap (void) |
6ffbb7ab TJB |
1560 | { |
1561 | CORE_ADDR field; | |
1562 | ||
8b88a78e | 1563 | if (target_auxv_search (current_top_target (), AT_HWCAP, &field) != 1) |
0ec848ad | 1564 | return 0; |
6ffbb7ab | 1565 | |
0ec848ad | 1566 | return field; |
6ffbb7ab TJB |
1567 | } |
1568 | ||
7ca18ed6 EBM |
1569 | /* Fetch the AT_HWCAP2 entry from the aux vector. */ |
1570 | ||
1571 | static CORE_ADDR | |
1572 | ppc_linux_get_hwcap2 (void) | |
1573 | { | |
1574 | CORE_ADDR field; | |
1575 | ||
1576 | if (target_auxv_search (current_top_target (), AT_HWCAP2, &field) != 1) | |
1577 | return 0; | |
1578 | ||
1579 | return field; | |
1580 | } | |
1581 | ||
6ffbb7ab | 1582 | /* The cached DABR value, to install in new threads. |
926bf92d UW |
1583 | This variable is used when the PowerPC HWDEBUG ptrace |
1584 | interface is not available. */ | |
6ffbb7ab TJB |
1585 | static long saved_dabr_value; |
1586 | ||
1587 | /* Global structure that will store information about the available | |
926bf92d UW |
1588 | features provided by the PowerPC HWDEBUG ptrace interface. */ |
1589 | static struct ppc_debug_info hwdebug_info; | |
6ffbb7ab TJB |
1590 | |
1591 | /* Global variable that holds the maximum number of slots that the | |
926bf92d UW |
1592 | kernel will use. This is only used when PowerPC HWDEBUG ptrace interface |
1593 | is available. */ | |
6ffbb7ab TJB |
1594 | static size_t max_slots_number = 0; |
1595 | ||
1596 | struct hw_break_tuple | |
1597 | { | |
1598 | long slot; | |
1599 | struct ppc_hw_breakpoint *hw_break; | |
1600 | }; | |
1601 | ||
1602 | /* This is an internal VEC created to store information about *points inserted | |
926bf92d UW |
1603 | for each thread. This is used when PowerPC HWDEBUG ptrace interface is |
1604 | available. */ | |
6ffbb7ab TJB |
1605 | typedef struct thread_points |
1606 | { | |
1607 | /* The TID to which this *point relates. */ | |
1608 | int tid; | |
1609 | /* Information about the *point, such as its address, type, etc. | |
1610 | ||
1611 | Each element inside this vector corresponds to a hardware | |
1612 | breakpoint or watchpoint in the thread represented by TID. The maximum | |
1613 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of | |
1614 | the tuple is NULL, then the position in the vector is free. */ | |
1615 | struct hw_break_tuple *hw_breaks; | |
1616 | } *thread_points_p; | |
1617 | DEF_VEC_P (thread_points_p); | |
1618 | ||
1619 | VEC(thread_points_p) *ppc_threads = NULL; | |
1620 | ||
926bf92d UW |
1621 | /* The version of the PowerPC HWDEBUG kernel interface that we will use, if |
1622 | available. */ | |
6ffbb7ab TJB |
1623 | #define PPC_DEBUG_CURRENT_VERSION 1 |
1624 | ||
926bf92d | 1625 | /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */ |
e0d24f8d | 1626 | static int |
926bf92d | 1627 | have_ptrace_hwdebug_interface (void) |
e0d24f8d | 1628 | { |
926bf92d | 1629 | static int have_ptrace_hwdebug_interface = -1; |
e0d24f8d | 1630 | |
926bf92d | 1631 | if (have_ptrace_hwdebug_interface == -1) |
6ffbb7ab TJB |
1632 | { |
1633 | int tid; | |
e0d24f8d | 1634 | |
e38504b3 | 1635 | tid = inferior_ptid.lwp (); |
6ffbb7ab | 1636 | if (tid == 0) |
e99b03dc | 1637 | tid = inferior_ptid.pid (); |
e0d24f8d | 1638 | |
926bf92d UW |
1639 | /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ |
1640 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) | |
6ffbb7ab | 1641 | { |
926bf92d | 1642 | /* Check whether PowerPC HWDEBUG ptrace interface is functional and |
0c56f59b | 1643 | provides any supported feature. */ |
926bf92d | 1644 | if (hwdebug_info.features != 0) |
0c56f59b | 1645 | { |
926bf92d UW |
1646 | have_ptrace_hwdebug_interface = 1; |
1647 | max_slots_number = hwdebug_info.num_instruction_bps | |
1648 | + hwdebug_info.num_data_bps | |
1649 | + hwdebug_info.num_condition_regs; | |
1650 | return have_ptrace_hwdebug_interface; | |
0c56f59b | 1651 | } |
6ffbb7ab | 1652 | } |
926bf92d UW |
1653 | /* Old school interface and no PowerPC HWDEBUG ptrace support. */ |
1654 | have_ptrace_hwdebug_interface = 0; | |
1655 | memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info)); | |
6ffbb7ab TJB |
1656 | } |
1657 | ||
926bf92d | 1658 | return have_ptrace_hwdebug_interface; |
e0d24f8d WZ |
1659 | } |
1660 | ||
f6ac5f3d PA |
1661 | int |
1662 | ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, int ot) | |
b7622095 | 1663 | { |
6ffbb7ab | 1664 | int total_hw_wp, total_hw_bp; |
b7622095 | 1665 | |
926bf92d | 1666 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab | 1667 | { |
926bf92d UW |
1668 | /* When PowerPC HWDEBUG ptrace interface is available, the number of |
1669 | available hardware watchpoints and breakpoints is stored at the | |
1670 | hwdebug_info struct. */ | |
1671 | total_hw_bp = hwdebug_info.num_instruction_bps; | |
1672 | total_hw_wp = hwdebug_info.num_data_bps; | |
6ffbb7ab TJB |
1673 | } |
1674 | else | |
1675 | { | |
926bf92d UW |
1676 | /* When we do not have PowerPC HWDEBUG ptrace interface, we should |
1677 | consider having 1 hardware watchpoint and no hardware breakpoints. */ | |
6ffbb7ab TJB |
1678 | total_hw_bp = 0; |
1679 | total_hw_wp = 1; | |
1680 | } | |
b7622095 | 1681 | |
6ffbb7ab TJB |
1682 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
1683 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
1684 | { | |
bb08bdbd | 1685 | if (cnt + ot > total_hw_wp) |
6ffbb7ab TJB |
1686 | return -1; |
1687 | } | |
1688 | else if (type == bp_hardware_breakpoint) | |
1689 | { | |
572f6555 EBM |
1690 | if (total_hw_bp == 0) |
1691 | { | |
1692 | /* No hardware breakpoint support. */ | |
1693 | return 0; | |
1694 | } | |
6ffbb7ab TJB |
1695 | if (cnt > total_hw_bp) |
1696 | return -1; | |
1697 | } | |
1698 | ||
926bf92d | 1699 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1700 | { |
1701 | int tid; | |
1702 | ptid_t ptid = inferior_ptid; | |
1703 | ||
0df8b418 MS |
1704 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
1705 | and whether the target has DABR. If either answer is no, the | |
1706 | ptrace call will return -1. Fail in that case. */ | |
e38504b3 | 1707 | tid = ptid.lwp (); |
6ffbb7ab | 1708 | if (tid == 0) |
e99b03dc | 1709 | tid = ptid.pid (); |
6ffbb7ab TJB |
1710 | |
1711 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1712 | return 0; | |
1713 | } | |
1714 | ||
1715 | return 1; | |
b7622095 LM |
1716 | } |
1717 | ||
f6ac5f3d PA |
1718 | int |
1719 | ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e0d24f8d WZ |
1720 | { |
1721 | /* Handle sub-8-byte quantities. */ | |
1722 | if (len <= 0) | |
1723 | return 0; | |
1724 | ||
926bf92d UW |
1725 | /* The PowerPC HWDEBUG ptrace interface tells if there are alignment |
1726 | restrictions for watchpoints in the processors. In that case, we use that | |
1727 | information to determine the hardcoded watchable region for | |
1728 | watchpoints. */ | |
1729 | if (have_ptrace_hwdebug_interface ()) | |
6ffbb7ab | 1730 | { |
e23b9d6e | 1731 | int region_size; |
4feebbdd EBM |
1732 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
1733 | watchpoints and can watch any access within an arbitrary memory | |
1734 | region. This is useful to watch arrays and structs, for instance. It | |
1735 | takes two hardware watchpoints though. */ | |
e09342b5 | 1736 | if (len > 1 |
926bf92d | 1737 | && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
4feebbdd | 1738 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
e09342b5 | 1739 | return 2; |
e23b9d6e UW |
1740 | /* Check if the processor provides DAWR interface. */ |
1741 | if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) | |
1742 | /* DAWR interface allows to watch up to 512 byte wide ranges which | |
1743 | can't cross a 512 byte boundary. */ | |
1744 | region_size = 512; | |
1745 | else | |
1746 | region_size = hwdebug_info.data_bp_alignment; | |
4feebbdd EBM |
1747 | /* Server processors provide one hardware watchpoint and addr+len should |
1748 | fall in the watchable region provided by the ptrace interface. */ | |
e23b9d6e UW |
1749 | if (region_size |
1750 | && (addr + len > (addr & ~(region_size - 1)) + region_size)) | |
0cf6dd15 | 1751 | return 0; |
6ffbb7ab | 1752 | } |
b7622095 | 1753 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
926bf92d UW |
1754 | processors (i.e., server processors). Without the new PowerPC HWDEBUG |
1755 | ptrace interface, DAC-based processors (i.e., embedded processors) will | |
1756 | use addresses aligned to 4-bytes due to the way the read/write flags are | |
6ffbb7ab TJB |
1757 | passed in the old ptrace interface. */ |
1758 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1759 | && (addr + len) > (addr & ~3) + 4) | |
1760 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1761 | return 0; |
1762 | ||
1763 | return 1; | |
1764 | } | |
1765 | ||
6ffbb7ab | 1766 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
e4166a49 | 1767 | static int |
926bf92d | 1768 | hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
6ffbb7ab | 1769 | { |
ad422571 TJB |
1770 | return (a->trigger_type == b->trigger_type |
1771 | && a->addr_mode == b->addr_mode | |
1772 | && a->condition_mode == b->condition_mode | |
1773 | && a->addr == b->addr | |
1774 | && a->addr2 == b->addr2 | |
6ffbb7ab TJB |
1775 | && a->condition_value == b->condition_value); |
1776 | } | |
1777 | ||
1778 | /* This function can be used to retrieve a thread_points by the TID of the | |
1779 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, | |
1780 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the | |
1781 | provided TID will be created and returned. */ | |
1782 | static struct thread_points * | |
926bf92d | 1783 | hwdebug_find_thread_points_by_tid (int tid, int alloc_new) |
6ffbb7ab TJB |
1784 | { |
1785 | int i; | |
1786 | struct thread_points *t; | |
1787 | ||
1788 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) | |
1789 | if (t->tid == tid) | |
1790 | return t; | |
1791 | ||
1792 | t = NULL; | |
1793 | ||
1794 | /* Do we need to allocate a new point_item | |
1795 | if the wanted one does not exist? */ | |
1796 | if (alloc_new) | |
1797 | { | |
8d749320 SM |
1798 | t = XNEW (struct thread_points); |
1799 | t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number); | |
6ffbb7ab TJB |
1800 | t->tid = tid; |
1801 | VEC_safe_push (thread_points_p, ppc_threads, t); | |
1802 | } | |
1803 | ||
1804 | return t; | |
1805 | } | |
1806 | ||
1807 | /* This function is a generic wrapper that is responsible for inserting a | |
1808 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1809 | kernel) and registering it internally in GDB. */ | |
1810 | static void | |
926bf92d | 1811 | hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1812 | { |
1813 | int i; | |
1814 | long slot; | |
a90ecff8 | 1815 | gdb::unique_xmalloc_ptr<ppc_hw_breakpoint> p (XDUP (ppc_hw_breakpoint, b)); |
6ffbb7ab | 1816 | struct hw_break_tuple *hw_breaks; |
6ffbb7ab | 1817 | struct thread_points *t; |
6ffbb7ab | 1818 | |
6ffbb7ab | 1819 | errno = 0; |
a90ecff8 | 1820 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ()); |
6ffbb7ab TJB |
1821 | if (slot < 0) |
1822 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); | |
1823 | ||
1824 | /* Everything went fine, so we have to register this *point. */ | |
926bf92d | 1825 | t = hwdebug_find_thread_points_by_tid (tid, 1); |
6ffbb7ab TJB |
1826 | gdb_assert (t != NULL); |
1827 | hw_breaks = t->hw_breaks; | |
1828 | ||
1829 | /* Find a free element in the hw_breaks vector. */ | |
1830 | for (i = 0; i < max_slots_number; i++) | |
1831 | if (hw_breaks[i].hw_break == NULL) | |
1832 | { | |
1833 | hw_breaks[i].slot = slot; | |
a90ecff8 | 1834 | hw_breaks[i].hw_break = p.release (); |
6ffbb7ab TJB |
1835 | break; |
1836 | } | |
1837 | ||
1838 | gdb_assert (i != max_slots_number); | |
6ffbb7ab TJB |
1839 | } |
1840 | ||
1841 | /* This function is a generic wrapper that is responsible for removing a | |
1842 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1843 | kernel), and unregistering it internally at GDB. */ | |
1844 | static void | |
926bf92d | 1845 | hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1846 | { |
1847 | int i; | |
1848 | struct hw_break_tuple *hw_breaks; | |
1849 | struct thread_points *t; | |
1850 | ||
926bf92d | 1851 | t = hwdebug_find_thread_points_by_tid (tid, 0); |
6ffbb7ab TJB |
1852 | gdb_assert (t != NULL); |
1853 | hw_breaks = t->hw_breaks; | |
1854 | ||
1855 | for (i = 0; i < max_slots_number; i++) | |
926bf92d | 1856 | if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b)) |
6ffbb7ab TJB |
1857 | break; |
1858 | ||
1859 | gdb_assert (i != max_slots_number); | |
1860 | ||
1861 | /* We have to ignore ENOENT errors because the kernel implements hardware | |
1862 | breakpoints/watchpoints as "one-shot", that is, they are automatically | |
1863 | deleted when hit. */ | |
1864 | errno = 0; | |
1865 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) | |
1866 | if (errno != ENOENT) | |
0df8b418 MS |
1867 | perror_with_name (_("Unexpected error deleting " |
1868 | "breakpoint or watchpoint")); | |
6ffbb7ab TJB |
1869 | |
1870 | xfree (hw_breaks[i].hw_break); | |
1871 | hw_breaks[i].hw_break = NULL; | |
1872 | } | |
9f0bdab8 | 1873 | |
f1310107 TJB |
1874 | /* Return the number of registers needed for a ranged breakpoint. */ |
1875 | ||
f6ac5f3d PA |
1876 | int |
1877 | ppc_linux_nat_target::ranged_break_num_registers () | |
f1310107 | 1878 | { |
926bf92d UW |
1879 | return ((have_ptrace_hwdebug_interface () |
1880 | && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? | |
f1310107 TJB |
1881 | 2 : -1); |
1882 | } | |
1883 | ||
1884 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for | |
1885 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ | |
1886 | ||
f6ac5f3d PA |
1887 | int |
1888 | ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1889 | struct bp_target_info *bp_tgt) | |
e0d24f8d | 1890 | { |
9f0bdab8 | 1891 | struct lwp_info *lp; |
6ffbb7ab TJB |
1892 | struct ppc_hw_breakpoint p; |
1893 | ||
926bf92d | 1894 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1895 | return -1; |
1896 | ||
ad422571 TJB |
1897 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1898 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 | 1899 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
0d5ed153 | 1900 | p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address); |
6ffbb7ab TJB |
1901 | p.condition_value = 0; |
1902 | ||
f1310107 TJB |
1903 | if (bp_tgt->length) |
1904 | { | |
1905 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1906 | ||
1907 | /* The breakpoint will trigger if the address of the instruction is | |
1908 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
1909 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1910 | } | |
1911 | else | |
1912 | { | |
1913 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1914 | p.addr2 = 0; | |
1915 | } | |
1916 | ||
4c38200f | 1917 | ALL_LWPS (lp) |
e38504b3 | 1918 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1919 | |
1920 | return 0; | |
1921 | } | |
1922 | ||
f6ac5f3d PA |
1923 | int |
1924 | ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1925 | struct bp_target_info *bp_tgt) | |
6ffbb7ab | 1926 | { |
6ffbb7ab TJB |
1927 | struct lwp_info *lp; |
1928 | struct ppc_hw_breakpoint p; | |
b7622095 | 1929 | |
926bf92d | 1930 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1931 | return -1; |
1932 | ||
ad422571 TJB |
1933 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1934 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1935 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1936 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1937 | p.condition_value = 0; |
1938 | ||
f1310107 TJB |
1939 | if (bp_tgt->length) |
1940 | { | |
1941 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1942 | ||
1943 | /* The breakpoint will trigger if the address of the instruction is within | |
1944 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
1945 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1946 | } | |
1947 | else | |
1948 | { | |
1949 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1950 | p.addr2 = 0; | |
1951 | } | |
1952 | ||
4c38200f | 1953 | ALL_LWPS (lp) |
e38504b3 | 1954 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1955 | |
1956 | return 0; | |
1957 | } | |
1958 | ||
1959 | static int | |
e76460db | 1960 | get_trigger_type (enum target_hw_bp_type type) |
6ffbb7ab TJB |
1961 | { |
1962 | int t; | |
1963 | ||
e76460db | 1964 | if (type == hw_read) |
6ffbb7ab | 1965 | t = PPC_BREAKPOINT_TRIGGER_READ; |
e76460db | 1966 | else if (type == hw_write) |
6ffbb7ab | 1967 | t = PPC_BREAKPOINT_TRIGGER_WRITE; |
b7622095 | 1968 | else |
6ffbb7ab TJB |
1969 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
1970 | ||
1971 | return t; | |
1972 | } | |
1973 | ||
9c06b0b4 TJB |
1974 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
1975 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1976 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1977 | an error on failure. */ | |
1978 | ||
f6ac5f3d PA |
1979 | int |
1980 | ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
1981 | target_hw_bp_type rw) | |
9c06b0b4 | 1982 | { |
9c06b0b4 TJB |
1983 | struct lwp_info *lp; |
1984 | struct ppc_hw_breakpoint p; | |
1985 | ||
926bf92d | 1986 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1987 | |
1988 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1989 | p.trigger_type = get_trigger_type (rw); | |
1990 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1991 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1992 | p.addr = addr; | |
1993 | p.addr2 = mask; | |
1994 | p.condition_value = 0; | |
1995 | ||
4c38200f | 1996 | ALL_LWPS (lp) |
e38504b3 | 1997 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
9c06b0b4 TJB |
1998 | |
1999 | return 0; | |
2000 | } | |
2001 | ||
2002 | /* Remove a masked watchpoint at ADDR with the mask MASK. | |
2003 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
2004 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
2005 | an error on failure. */ | |
2006 | ||
f6ac5f3d PA |
2007 | int |
2008 | ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
2009 | target_hw_bp_type rw) | |
9c06b0b4 | 2010 | { |
9c06b0b4 TJB |
2011 | struct lwp_info *lp; |
2012 | struct ppc_hw_breakpoint p; | |
2013 | ||
926bf92d | 2014 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
2015 | |
2016 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
2017 | p.trigger_type = get_trigger_type (rw); | |
2018 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
2019 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2020 | p.addr = addr; | |
2021 | p.addr2 = mask; | |
2022 | p.condition_value = 0; | |
2023 | ||
4c38200f | 2024 | ALL_LWPS (lp) |
e38504b3 | 2025 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
9c06b0b4 TJB |
2026 | |
2027 | return 0; | |
2028 | } | |
2029 | ||
0cf6dd15 TJB |
2030 | /* Check whether we have at least one free DVC register. */ |
2031 | static int | |
2032 | can_use_watchpoint_cond_accel (void) | |
2033 | { | |
2034 | struct thread_points *p; | |
e38504b3 | 2035 | int tid = inferior_ptid.lwp (); |
926bf92d | 2036 | int cnt = hwdebug_info.num_condition_regs, i; |
0cf6dd15 | 2037 | |
926bf92d | 2038 | if (!have_ptrace_hwdebug_interface () || cnt == 0) |
0cf6dd15 TJB |
2039 | return 0; |
2040 | ||
926bf92d | 2041 | p = hwdebug_find_thread_points_by_tid (tid, 0); |
0cf6dd15 TJB |
2042 | |
2043 | if (p) | |
2044 | { | |
2045 | for (i = 0; i < max_slots_number; i++) | |
2046 | if (p->hw_breaks[i].hw_break != NULL | |
2047 | && (p->hw_breaks[i].hw_break->condition_mode | |
2048 | != PPC_BREAKPOINT_CONDITION_NONE)) | |
2049 | cnt--; | |
2050 | ||
2051 | /* There are no available slots now. */ | |
2052 | if (cnt <= 0) | |
2053 | return 0; | |
2054 | } | |
2055 | ||
2056 | return 1; | |
2057 | } | |
2058 | ||
2059 | /* Calculate the enable bits and the contents of the Data Value Compare | |
2060 | debug register present in BookE processors. | |
2061 | ||
2062 | ADDR is the address to be watched, LEN is the length of watched data | |
2063 | and DATA_VALUE is the value which will trigger the watchpoint. | |
2064 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
2065 | CONDITION_VALUE will hold the value which should be put in the | |
2066 | DVC register. */ | |
2067 | static void | |
2068 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, | |
2069 | uint32_t *condition_mode, uint64_t *condition_value) | |
2070 | { | |
2071 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, | |
2072 | rightmost_enabled_byte; | |
2073 | CORE_ADDR addr_end_data, addr_end_dvc; | |
2074 | ||
2075 | /* The DVC register compares bytes within fixed-length windows which | |
2076 | are word-aligned, with length equal to that of the DVC register. | |
2077 | We need to calculate where our watch region is relative to that | |
2078 | window and enable comparison of the bytes which fall within it. */ | |
2079 | ||
926bf92d | 2080 | align_offset = addr % hwdebug_info.sizeof_condition; |
0cf6dd15 TJB |
2081 | addr_end_data = addr + len; |
2082 | addr_end_dvc = (addr - align_offset | |
926bf92d | 2083 | + hwdebug_info.sizeof_condition); |
0cf6dd15 TJB |
2084 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? |
2085 | addr_end_data - addr_end_dvc : 0; | |
2086 | num_byte_enable = len - num_bytes_off_dvc; | |
2087 | /* Here, bytes are numbered from right to left. */ | |
2088 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
2089 | addr_end_dvc - addr_end_data : 0; | |
2090 | ||
2091 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
2092 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
2093 | *condition_mode |
2094 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
2095 | |
2096 | /* Now we need to match the position within the DVC of the comparison | |
2097 | value with where the watch region is relative to the window | |
2098 | (i.e., the ALIGN_OFFSET). */ | |
2099 | ||
2100 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
2101 | << rightmost_enabled_byte * 8); | |
2102 | } | |
2103 | ||
2104 | /* Return the number of memory locations that need to be accessed to | |
2105 | evaluate the expression which generated the given value chain. | |
2106 | Returns -1 if there's any register access involved, or if there are | |
2107 | other kinds of values which are not acceptable in a condition | |
2108 | expression (e.g., lval_computed or lval_internalvar). */ | |
2109 | static int | |
a6535de1 | 2110 | num_memory_accesses (const std::vector<value_ref_ptr> &chain) |
0cf6dd15 TJB |
2111 | { |
2112 | int found_memory_cnt = 0; | |
0cf6dd15 TJB |
2113 | |
2114 | /* The idea here is that evaluating an expression generates a series | |
2115 | of values, one holding the value of every subexpression. (The | |
2116 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
2117 | a*b+c.) GDB's values hold almost enough information to establish | |
2118 | the criteria given above --- they identify memory lvalues, | |
2119 | register lvalues, computed values, etcetera. So we can evaluate | |
2120 | the expression, and then scan the chain of values that leaves | |
2121 | behind to determine the memory locations involved in the evaluation | |
2122 | of an expression. | |
2123 | ||
2124 | However, I don't think that the values returned by inferior | |
2125 | function calls are special in any way. So this function may not | |
2126 | notice that an expression contains an inferior function call. | |
2127 | FIXME. */ | |
2128 | ||
a6535de1 | 2129 | for (const value_ref_ptr &iter : chain) |
0cf6dd15 | 2130 | { |
a6535de1 TT |
2131 | struct value *v = iter.get (); |
2132 | ||
0cf6dd15 TJB |
2133 | /* Constants and values from the history are fine. */ |
2134 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) | |
2135 | continue; | |
2136 | else if (VALUE_LVAL (v) == lval_memory) | |
2137 | { | |
2138 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
2139 | we either just used its address (e.g., `a' in `a.b') or | |
2140 | we never needed it at all (e.g., `a' in `a,b'). */ | |
2141 | if (!value_lazy (v)) | |
2142 | found_memory_cnt++; | |
2143 | } | |
0df8b418 | 2144 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
2145 | else |
2146 | return -1; | |
2147 | } | |
2148 | ||
2149 | return found_memory_cnt; | |
2150 | } | |
2151 | ||
2152 | /* Verifies whether the expression COND can be implemented using the | |
2153 | DVC (Data Value Compare) register in BookE processors. The expression | |
2154 | must test the watch value for equality with a constant expression. | |
2155 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
2156 | which the watch value should be compared and LEN will contain the size |
2157 | of the constant. */ | |
0cf6dd15 TJB |
2158 | static int |
2159 | check_condition (CORE_ADDR watch_addr, struct expression *cond, | |
e7db58ea | 2160 | CORE_ADDR *data_value, int *len) |
0cf6dd15 TJB |
2161 | { |
2162 | int pc = 1, num_accesses_left, num_accesses_right; | |
a6535de1 TT |
2163 | struct value *left_val, *right_val; |
2164 | std::vector<value_ref_ptr> left_chain, right_chain; | |
0cf6dd15 TJB |
2165 | |
2166 | if (cond->elts[0].opcode != BINOP_EQUAL) | |
2167 | return 0; | |
2168 | ||
3a1115a0 | 2169 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0); |
0cf6dd15 TJB |
2170 | num_accesses_left = num_memory_accesses (left_chain); |
2171 | ||
2172 | if (left_val == NULL || num_accesses_left < 0) | |
a6535de1 | 2173 | return 0; |
0cf6dd15 | 2174 | |
3a1115a0 | 2175 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0); |
0cf6dd15 TJB |
2176 | num_accesses_right = num_memory_accesses (right_chain); |
2177 | ||
2178 | if (right_val == NULL || num_accesses_right < 0) | |
a6535de1 | 2179 | return 0; |
0cf6dd15 TJB |
2180 | |
2181 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
2182 | && VALUE_LVAL (left_val) == lval_memory | |
2183 | && value_address (left_val) == watch_addr) | |
e7db58ea TJB |
2184 | { |
2185 | *data_value = value_as_long (right_val); | |
2186 | ||
2187 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
2188 | the same type as the memory region referenced by LEFT_VAL. */ | |
2189 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); | |
2190 | } | |
0cf6dd15 TJB |
2191 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
2192 | && VALUE_LVAL (right_val) == lval_memory | |
2193 | && value_address (right_val) == watch_addr) | |
e7db58ea TJB |
2194 | { |
2195 | *data_value = value_as_long (left_val); | |
2196 | ||
2197 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
2198 | the same type as the memory region referenced by RIGHT_VAL. */ | |
2199 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); | |
2200 | } | |
0cf6dd15 | 2201 | else |
a6535de1 | 2202 | return 0; |
0cf6dd15 TJB |
2203 | |
2204 | return 1; | |
2205 | } | |
2206 | ||
2207 | /* Return non-zero if the target is capable of using hardware to evaluate | |
2208 | the condition expression, thus only triggering the watchpoint when it is | |
2209 | true. */ | |
57810aa7 | 2210 | bool |
f6ac5f3d PA |
2211 | ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, int len, |
2212 | int rw, | |
2213 | struct expression *cond) | |
0cf6dd15 TJB |
2214 | { |
2215 | CORE_ADDR data_value; | |
2216 | ||
926bf92d UW |
2217 | return (have_ptrace_hwdebug_interface () |
2218 | && hwdebug_info.num_condition_regs > 0 | |
e7db58ea | 2219 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
2220 | } |
2221 | ||
e09342b5 TJB |
2222 | /* Set up P with the parameters necessary to request a watchpoint covering |
2223 | LEN bytes starting at ADDR and if possible with condition expression COND | |
2224 | evaluated by hardware. INSERT tells if we are creating a request for | |
2225 | inserting or removing the watchpoint. */ | |
2226 | ||
2227 | static void | |
2228 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, | |
e76460db PA |
2229 | int len, enum target_hw_bp_type type, |
2230 | struct expression *cond, int insert) | |
e09342b5 | 2231 | { |
f16c4e8b | 2232 | if (len == 1 |
926bf92d | 2233 | || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) |
e09342b5 TJB |
2234 | { |
2235 | int use_condition; | |
2236 | CORE_ADDR data_value; | |
2237 | ||
2238 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
926bf92d | 2239 | : hwdebug_info.num_condition_regs > 0); |
e7db58ea TJB |
2240 | if (cond && use_condition && check_condition (addr, cond, |
2241 | &data_value, &len)) | |
e09342b5 TJB |
2242 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
2243 | &p->condition_value); | |
2244 | else | |
2245 | { | |
2246 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2247 | p->condition_value = 0; | |
2248 | } | |
2249 | ||
2250 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2251 | p->addr2 = 0; | |
2252 | } | |
2253 | else | |
2254 | { | |
2255 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2256 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2257 | p->condition_value = 0; | |
2258 | ||
2259 | /* The watchpoint will trigger if the address of the memory access is | |
2260 | within the defined range, as follows: p->addr <= address < p->addr2. | |
2261 | ||
2262 | Note that the above sentence just documents how ptrace interprets | |
2263 | its arguments; the watchpoint is set to watch the range defined by | |
2264 | the user _inclusively_, as specified by the user interface. */ | |
2265 | p->addr2 = (uint64_t) addr + len; | |
2266 | } | |
2267 | ||
2268 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
e76460db | 2269 | p->trigger_type = get_trigger_type (type); |
e09342b5 TJB |
2270 | p->addr = (uint64_t) addr; |
2271 | } | |
2272 | ||
f6ac5f3d PA |
2273 | int |
2274 | ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
2275 | enum target_hw_bp_type type, | |
2276 | struct expression *cond) | |
6ffbb7ab TJB |
2277 | { |
2278 | struct lwp_info *lp; | |
6ffbb7ab TJB |
2279 | int ret = -1; |
2280 | ||
926bf92d | 2281 | if (have_ptrace_hwdebug_interface ()) |
e0d24f8d | 2282 | { |
6ffbb7ab TJB |
2283 | struct ppc_hw_breakpoint p; |
2284 | ||
e76460db | 2285 | create_watchpoint_request (&p, addr, len, type, cond, 1); |
6ffbb7ab | 2286 | |
4c38200f | 2287 | ALL_LWPS (lp) |
e38504b3 | 2288 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
2289 | |
2290 | ret = 0; | |
e0d24f8d | 2291 | } |
6ffbb7ab TJB |
2292 | else |
2293 | { | |
2294 | long dabr_value; | |
2295 | long read_mode, write_mode; | |
e0d24f8d | 2296 | |
6ffbb7ab TJB |
2297 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2298 | { | |
2299 | /* PowerPC 440 requires only the read/write flags to be passed | |
2300 | to the kernel. */ | |
ad422571 | 2301 | read_mode = 1; |
6ffbb7ab TJB |
2302 | write_mode = 2; |
2303 | } | |
2304 | else | |
2305 | { | |
2306 | /* PowerPC 970 and other DABR-based processors are required to pass | |
2307 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 2308 | read_mode = 5; |
6ffbb7ab TJB |
2309 | write_mode = 6; |
2310 | } | |
1c86e440 | 2311 | |
6ffbb7ab | 2312 | dabr_value = addr & ~(read_mode | write_mode); |
e76460db | 2313 | switch (type) |
6ffbb7ab TJB |
2314 | { |
2315 | case hw_read: | |
2316 | /* Set read and translate bits. */ | |
2317 | dabr_value |= read_mode; | |
2318 | break; | |
2319 | case hw_write: | |
2320 | /* Set write and translate bits. */ | |
2321 | dabr_value |= write_mode; | |
2322 | break; | |
2323 | case hw_access: | |
2324 | /* Set read, write and translate bits. */ | |
2325 | dabr_value |= read_mode | write_mode; | |
2326 | break; | |
2327 | } | |
1c86e440 | 2328 | |
6ffbb7ab TJB |
2329 | saved_dabr_value = dabr_value; |
2330 | ||
4c38200f | 2331 | ALL_LWPS (lp) |
e38504b3 | 2332 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, |
0cf6dd15 | 2333 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2334 | return -1; |
2335 | ||
2336 | ret = 0; | |
2337 | } | |
2338 | ||
2339 | return ret; | |
e0d24f8d WZ |
2340 | } |
2341 | ||
f6ac5f3d PA |
2342 | int |
2343 | ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
2344 | enum target_hw_bp_type type, | |
2345 | struct expression *cond) | |
e0d24f8d | 2346 | { |
9f0bdab8 | 2347 | struct lwp_info *lp; |
6ffbb7ab | 2348 | int ret = -1; |
9f0bdab8 | 2349 | |
926bf92d | 2350 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2351 | { |
2352 | struct ppc_hw_breakpoint p; | |
2353 | ||
e76460db | 2354 | create_watchpoint_request (&p, addr, len, type, cond, 0); |
6ffbb7ab | 2355 | |
4c38200f | 2356 | ALL_LWPS (lp) |
e38504b3 | 2357 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
2358 | |
2359 | ret = 0; | |
2360 | } | |
2361 | else | |
2362 | { | |
2363 | saved_dabr_value = 0; | |
4c38200f | 2364 | ALL_LWPS (lp) |
e38504b3 | 2365 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, |
0cf6dd15 | 2366 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2367 | return -1; |
2368 | ||
2369 | ret = 0; | |
2370 | } | |
2371 | ||
2372 | return ret; | |
e0d24f8d WZ |
2373 | } |
2374 | ||
135340af PA |
2375 | void |
2376 | ppc_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e0d24f8d | 2377 | { |
e38504b3 | 2378 | int tid = lp->ptid.lwp (); |
6ffbb7ab | 2379 | |
926bf92d | 2380 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2381 | { |
2382 | int i; | |
2383 | struct thread_points *p; | |
2384 | struct hw_break_tuple *hw_breaks; | |
2385 | ||
2386 | if (VEC_empty (thread_points_p, ppc_threads)) | |
2387 | return; | |
2388 | ||
0df8b418 | 2389 | /* Get a list of breakpoints from any thread. */ |
6ffbb7ab TJB |
2390 | p = VEC_last (thread_points_p, ppc_threads); |
2391 | hw_breaks = p->hw_breaks; | |
2392 | ||
0df8b418 | 2393 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
6ffbb7ab TJB |
2394 | for (i = 0; i < max_slots_number; i++) |
2395 | if (hw_breaks[i].hw_break) | |
aacbb8a5 LM |
2396 | { |
2397 | /* Older kernels did not make new threads inherit their parent | |
2398 | thread's debug state, so we always clear the slot and replicate | |
2399 | the debug state ourselves, ensuring compatibility with all | |
2400 | kernels. */ | |
2401 | ||
2402 | /* The ppc debug resource accounting is done through "slots". | |
2403 | Ask the kernel the deallocate this specific *point's slot. */ | |
2404 | ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot); | |
2405 | ||
926bf92d | 2406 | hwdebug_insert_point (hw_breaks[i].hw_break, tid); |
aacbb8a5 | 2407 | } |
6ffbb7ab TJB |
2408 | } |
2409 | else | |
2410 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); | |
2411 | } | |
2412 | ||
2413 | static void | |
2414 | ppc_linux_thread_exit (struct thread_info *tp, int silent) | |
2415 | { | |
2416 | int i; | |
e38504b3 | 2417 | int tid = tp->ptid.lwp (); |
6ffbb7ab TJB |
2418 | struct hw_break_tuple *hw_breaks; |
2419 | struct thread_points *t = NULL, *p; | |
2420 | ||
926bf92d | 2421 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2422 | return; |
2423 | ||
2424 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) | |
2425 | if (p->tid == tid) | |
2426 | { | |
2427 | t = p; | |
2428 | break; | |
2429 | } | |
2430 | ||
2431 | if (t == NULL) | |
2432 | return; | |
2433 | ||
2434 | VEC_unordered_remove (thread_points_p, ppc_threads, i); | |
2435 | ||
2436 | hw_breaks = t->hw_breaks; | |
2437 | ||
2438 | for (i = 0; i < max_slots_number; i++) | |
2439 | if (hw_breaks[i].hw_break) | |
2440 | xfree (hw_breaks[i].hw_break); | |
2441 | ||
2442 | xfree (t->hw_breaks); | |
2443 | xfree (t); | |
e0d24f8d WZ |
2444 | } |
2445 | ||
57810aa7 | 2446 | bool |
f6ac5f3d | 2447 | ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e0d24f8d | 2448 | { |
f865ee35 | 2449 | siginfo_t siginfo; |
e0d24f8d | 2450 | |
f865ee35 | 2451 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
57810aa7 | 2452 | return false; |
e0d24f8d | 2453 | |
f865ee35 JK |
2454 | if (siginfo.si_signo != SIGTRAP |
2455 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 2456 | return false; |
e0d24f8d | 2457 | |
926bf92d | 2458 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2459 | { |
2460 | int i; | |
2461 | struct thread_points *t; | |
2462 | struct hw_break_tuple *hw_breaks; | |
2463 | /* The index (or slot) of the *point is passed in the si_errno field. */ | |
f865ee35 | 2464 | int slot = siginfo.si_errno; |
6ffbb7ab | 2465 | |
e38504b3 | 2466 | t = hwdebug_find_thread_points_by_tid (inferior_ptid.lwp (), 0); |
6ffbb7ab TJB |
2467 | |
2468 | /* Find out if this *point is a hardware breakpoint. | |
2469 | If so, we should return 0. */ | |
2470 | if (t) | |
2471 | { | |
2472 | hw_breaks = t->hw_breaks; | |
2473 | for (i = 0; i < max_slots_number; i++) | |
2474 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot | |
2475 | && hw_breaks[i].hw_break->trigger_type | |
2476 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) | |
57810aa7 | 2477 | return false; |
6ffbb7ab TJB |
2478 | } |
2479 | } | |
2480 | ||
f865ee35 | 2481 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 2482 | return true; |
e0d24f8d WZ |
2483 | } |
2484 | ||
57810aa7 | 2485 | bool |
f6ac5f3d | 2486 | ppc_linux_nat_target::stopped_by_watchpoint () |
9f0bdab8 DJ |
2487 | { |
2488 | CORE_ADDR addr; | |
f6ac5f3d | 2489 | return stopped_data_address (&addr); |
9f0bdab8 DJ |
2490 | } |
2491 | ||
57810aa7 | 2492 | bool |
f6ac5f3d PA |
2493 | ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
2494 | CORE_ADDR start, | |
2495 | int length) | |
5009afc5 | 2496 | { |
b7622095 LM |
2497 | int mask; |
2498 | ||
926bf92d | 2499 | if (have_ptrace_hwdebug_interface () |
6ffbb7ab TJB |
2500 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2501 | return start <= addr && start + length >= addr; | |
2502 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
b7622095 LM |
2503 | mask = 3; |
2504 | else | |
2505 | mask = 7; | |
2506 | ||
2507 | addr &= ~mask; | |
2508 | ||
0df8b418 | 2509 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 2510 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
2511 | } |
2512 | ||
9c06b0b4 TJB |
2513 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
2514 | ||
f6ac5f3d PA |
2515 | int |
2516 | ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, CORE_ADDR mask) | |
9c06b0b4 | 2517 | { |
926bf92d UW |
2518 | if (!have_ptrace_hwdebug_interface () |
2519 | || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
9c06b0b4 TJB |
2520 | return -1; |
2521 | else if ((mask & 0xC0000000) != 0xC0000000) | |
2522 | { | |
2523 | warning (_("The given mask covers kernel address space " | |
2524 | "and cannot be used.\n")); | |
2525 | ||
2526 | return -2; | |
2527 | } | |
2528 | else | |
2529 | return 2; | |
2530 | } | |
2531 | ||
f6ac5f3d PA |
2532 | void |
2533 | ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
45229ea4 | 2534 | { |
222312d3 | 2535 | pid_t tid = get_ptrace_pid (regcache->ptid ()); |
05f13b9c | 2536 | |
45229ea4 | 2537 | if (regno >= 0) |
56be3814 | 2538 | store_register (regcache, tid, regno); |
45229ea4 | 2539 | else |
56be3814 | 2540 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
2541 | } |
2542 | ||
f2db237a AM |
2543 | /* Functions for transferring registers between a gregset_t or fpregset_t |
2544 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
0df8b418 | 2545 | by the ptrace interface, not the current program's ABI. Eg. if a |
f2db237a AM |
2546 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
2547 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
2548 | ||
50c9bd31 | 2549 | void |
7f7fe91e | 2550 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 2551 | { |
f2db237a | 2552 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2553 | |
f2db237a | 2554 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
2555 | } |
2556 | ||
fdb28ac4 | 2557 | void |
7f7fe91e UW |
2558 | fill_gregset (const struct regcache *regcache, |
2559 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 2560 | { |
f2db237a | 2561 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2562 | |
f2db237a AM |
2563 | if (regno == -1) |
2564 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
2565 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
2566 | } |
2567 | ||
50c9bd31 | 2568 | void |
7f7fe91e | 2569 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 2570 | { |
f2db237a AM |
2571 | const struct regset *regset = ppc_linux_fpregset (); |
2572 | ||
2573 | ppc_supply_fpregset (regset, regcache, -1, | |
2574 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 2575 | } |
fdb28ac4 | 2576 | |
fdb28ac4 | 2577 | void |
7f7fe91e UW |
2578 | fill_fpregset (const struct regcache *regcache, |
2579 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 2580 | { |
f2db237a AM |
2581 | const struct regset *regset = ppc_linux_fpregset (); |
2582 | ||
2583 | ppc_collect_fpregset (regset, regcache, regno, | |
2584 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 2585 | } |
10d6c8cd | 2586 | |
2e077f5e PFC |
2587 | int |
2588 | ppc_linux_nat_target::auxv_parse (gdb_byte **readptr, | |
2589 | gdb_byte *endptr, CORE_ADDR *typep, | |
2590 | CORE_ADDR *valp) | |
409c383c | 2591 | { |
e38504b3 | 2592 | int tid = inferior_ptid.lwp (); |
409c383c | 2593 | if (tid == 0) |
e99b03dc | 2594 | tid = inferior_ptid.pid (); |
409c383c | 2595 | |
2e077f5e | 2596 | int sizeof_auxv_field = ppc_linux_target_wordsize (tid); |
409c383c | 2597 | |
f5656ead | 2598 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
409c383c UW |
2599 | gdb_byte *ptr = *readptr; |
2600 | ||
2601 | if (endptr == ptr) | |
2602 | return 0; | |
2603 | ||
2604 | if (endptr - ptr < sizeof_auxv_field * 2) | |
2605 | return -1; | |
2606 | ||
e17a4113 | 2607 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c | 2608 | ptr += sizeof_auxv_field; |
e17a4113 | 2609 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c UW |
2610 | ptr += sizeof_auxv_field; |
2611 | ||
2612 | *readptr = ptr; | |
2613 | return 1; | |
2614 | } | |
2615 | ||
f6ac5f3d PA |
2616 | const struct target_desc * |
2617 | ppc_linux_nat_target::read_description () | |
310a98e1 | 2618 | { |
e38504b3 | 2619 | int tid = inferior_ptid.lwp (); |
7284e1be | 2620 | if (tid == 0) |
e99b03dc | 2621 | tid = inferior_ptid.pid (); |
7284e1be | 2622 | |
310a98e1 DJ |
2623 | if (have_ptrace_getsetevrregs) |
2624 | { | |
2625 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
2626 | |
2627 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
2628 | return tdesc_powerpc_e500l; |
2629 | ||
2630 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
2631 | Anything else needs to be reported. */ | |
2632 | else if (errno != EIO) | |
2633 | perror_with_name (_("Unable to fetch SPE registers")); | |
2634 | } | |
2635 | ||
bd64614e PFC |
2636 | struct ppc_linux_features features = ppc_linux_no_features; |
2637 | ||
2e077f5e | 2638 | features.wordsize = ppc_linux_target_wordsize (tid); |
bd64614e | 2639 | |
0ec848ad | 2640 | CORE_ADDR hwcap = ppc_linux_get_hwcap (); |
7ca18ed6 | 2641 | CORE_ADDR hwcap2 = ppc_linux_get_hwcap2 (); |
bd64614e | 2642 | |
0154d990 | 2643 | if (have_ptrace_getsetvsxregs |
bd64614e | 2644 | && (hwcap & PPC_FEATURE_HAS_VSX)) |
604c2f83 LM |
2645 | { |
2646 | gdb_vsxregset_t vsxregset; | |
2647 | ||
2648 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
bd64614e | 2649 | features.vsx = true; |
604c2f83 LM |
2650 | |
2651 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
2652 | Anything else needs to be reported. */ | |
2653 | else if (errno != EIO) | |
2654 | perror_with_name (_("Unable to fetch VSX registers")); | |
2655 | } | |
2656 | ||
0154d990 | 2657 | if (have_ptrace_getvrregs |
bd64614e | 2658 | && (hwcap & PPC_FEATURE_HAS_ALTIVEC)) |
7284e1be UW |
2659 | { |
2660 | gdb_vrregset_t vrregset; | |
2661 | ||
2662 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
bd64614e | 2663 | features.altivec = true; |
7284e1be UW |
2664 | |
2665 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
2666 | Anything else needs to be reported. */ | |
2667 | else if (errno != EIO) | |
2668 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
2669 | } |
2670 | ||
bd64614e PFC |
2671 | if (hwcap & PPC_FEATURE_CELL) |
2672 | features.cell = true; | |
7284e1be | 2673 | |
bd64614e | 2674 | features.isa205 = ppc_linux_has_isa205 (hwcap); |
604c2f83 | 2675 | |
7ca18ed6 EBM |
2676 | if ((hwcap2 & PPC_FEATURE2_DSCR) |
2677 | && check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET) | |
2678 | && check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)) | |
f2cf6173 EBM |
2679 | { |
2680 | features.ppr_dscr = true; | |
2681 | if ((hwcap2 & PPC_FEATURE2_ARCH_2_07) | |
2682 | && (hwcap2 & PPC_FEATURE2_TAR) | |
232bfb86 EBM |
2683 | && (hwcap2 & PPC_FEATURE2_EBB) |
2684 | && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET) | |
2685 | && check_regset (tid, NT_PPC_EBB, PPC_LINUX_SIZEOF_EBBREGSET) | |
2686 | && check_regset (tid, NT_PPC_PMU, PPC_LINUX_SIZEOF_PMUREGSET)) | |
8d619c01 EBM |
2687 | { |
2688 | features.isa207 = true; | |
2689 | if ((hwcap2 & PPC_FEATURE2_HTM) | |
2690 | && check_regset (tid, NT_PPC_TM_SPR, | |
2691 | PPC_LINUX_SIZEOF_TM_SPRREGSET)) | |
2692 | features.htm = true; | |
2693 | } | |
f2cf6173 | 2694 | } |
7ca18ed6 | 2695 | |
bd64614e | 2696 | return ppc_linux_match_description (features); |
310a98e1 DJ |
2697 | } |
2698 | ||
10d6c8cd DJ |
2699 | void |
2700 | _initialize_ppc_linux_nat (void) | |
2701 | { | |
f6ac5f3d | 2702 | linux_target = &the_ppc_linux_nat_target; |
310a98e1 | 2703 | |
76727919 | 2704 | gdb::observers::thread_exit.attach (ppc_linux_thread_exit); |
6ffbb7ab | 2705 | |
10d6c8cd | 2706 | /* Register the target. */ |
d9f719f1 | 2707 | add_inf_child_target (linux_target); |
10d6c8cd | 2708 | } |