Commit | Line | Data |
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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
0b302171 JB |
3 | Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free |
4 | Software Foundation, Inc. | |
c877c8e6 KB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
20 | |
21 | #include "defs.h" | |
e162d11b | 22 | #include "gdb_string.h" |
6ffbb7ab | 23 | #include "observer.h" |
c877c8e6 KB |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
6ffbb7ab | 26 | #include "gdbthread.h" |
c877c8e6 | 27 | #include "gdbcore.h" |
4e052eda | 28 | #include "regcache.h" |
383f0f5b | 29 | #include "gdb_assert.h" |
10d6c8cd DJ |
30 | #include "target.h" |
31 | #include "linux-nat.h" | |
c877c8e6 | 32 | |
411cb3f9 | 33 | #include <stdint.h> |
c877c8e6 KB |
34 | #include <sys/types.h> |
35 | #include <sys/param.h> | |
36 | #include <signal.h> | |
37 | #include <sys/user.h> | |
38 | #include <sys/ioctl.h> | |
2555fe1a | 39 | #include "gdb_wait.h" |
c877c8e6 KB |
40 | #include <fcntl.h> |
41 | #include <sys/procfs.h> | |
45229ea4 | 42 | #include <sys/ptrace.h> |
c877c8e6 | 43 | |
0df8b418 | 44 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 45 | #include "gregset.h" |
16333c4f | 46 | #include "ppc-tdep.h" |
7284e1be UW |
47 | #include "ppc-linux-tdep.h" |
48 | ||
b7622095 LM |
49 | /* Required when using the AUXV. */ |
50 | #include "elf/common.h" | |
51 | #include "auxv.h" | |
52 | ||
7284e1be UW |
53 | /* This sometimes isn't defined. */ |
54 | #ifndef PT_ORIG_R3 | |
55 | #define PT_ORIG_R3 34 | |
56 | #endif | |
57 | #ifndef PT_TRAP | |
58 | #define PT_TRAP 40 | |
59 | #endif | |
c60c0f5f | 60 | |
69abc51c TJB |
61 | /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>. |
62 | If they aren't, we can provide them ourselves (their values are fixed | |
63 | because they are part of the kernel ABI). They are used in the AT_HWCAP | |
64 | entry of the AUXV. */ | |
f4d9bade UW |
65 | #ifndef PPC_FEATURE_CELL |
66 | #define PPC_FEATURE_CELL 0x00010000 | |
67 | #endif | |
b7622095 LM |
68 | #ifndef PPC_FEATURE_BOOKE |
69 | #define PPC_FEATURE_BOOKE 0x00008000 | |
70 | #endif | |
f04c6d38 TJB |
71 | #ifndef PPC_FEATURE_HAS_DFP |
72 | #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */ | |
69abc51c | 73 | #endif |
b7622095 | 74 | |
9abe5450 EZ |
75 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
76 | configure time check. Some older glibc's (for instance 2.2.1) | |
77 | don't have a specific powerpc version of ptrace.h, and fall back on | |
78 | a generic one. In such cases, sys/ptrace.h defines | |
79 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
80 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
81 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
82 | much useless. */ | |
83 | ||
84 | /* These definitions should really come from the glibc header files, | |
85 | but Glibc doesn't know about the vrregs yet. */ | |
86 | #ifndef PTRACE_GETVRREGS | |
87 | #define PTRACE_GETVRREGS 18 | |
88 | #define PTRACE_SETVRREGS 19 | |
89 | #endif | |
90 | ||
604c2f83 LM |
91 | /* PTRACE requests for POWER7 VSX registers. */ |
92 | #ifndef PTRACE_GETVSXREGS | |
93 | #define PTRACE_GETVSXREGS 27 | |
94 | #define PTRACE_SETVSXREGS 28 | |
95 | #endif | |
01904826 JB |
96 | |
97 | /* Similarly for the ptrace requests for getting / setting the SPE | |
98 | registers (ev0 -- ev31, acc, and spefscr). See the description of | |
99 | gdb_evrregset_t for details. */ | |
100 | #ifndef PTRACE_GETEVRREGS | |
101 | #define PTRACE_GETEVRREGS 20 | |
102 | #define PTRACE_SETEVRREGS 21 | |
103 | #endif | |
104 | ||
6ffbb7ab TJB |
105 | /* Similarly for the hardware watchpoint support. These requests are used |
106 | when the BookE kernel interface is not available. */ | |
e0d24f8d WZ |
107 | #ifndef PTRACE_GET_DEBUGREG |
108 | #define PTRACE_GET_DEBUGREG 25 | |
109 | #endif | |
110 | #ifndef PTRACE_SET_DEBUGREG | |
111 | #define PTRACE_SET_DEBUGREG 26 | |
112 | #endif | |
113 | #ifndef PTRACE_GETSIGINFO | |
114 | #define PTRACE_GETSIGINFO 0x4202 | |
115 | #endif | |
01904826 | 116 | |
6ffbb7ab TJB |
117 | /* These requests are used when the BookE kernel interface is available. |
118 | It exposes the additional debug features of BookE processors, such as | |
119 | ranged breakpoints and watchpoints and hardware-accelerated condition | |
120 | evaluation. */ | |
121 | #ifndef PPC_PTRACE_GETHWDBGINFO | |
122 | ||
123 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the new BookE | |
124 | interface is not present in ptrace.h, so we'll have to pretty much include | |
125 | it all here so that the code at least compiles on older systems. */ | |
126 | #define PPC_PTRACE_GETHWDBGINFO 0x89 | |
127 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
128 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
129 | ||
130 | struct ppc_debug_info | |
131 | { | |
0df8b418 | 132 | uint32_t version; /* Only version 1 exists to date. */ |
6ffbb7ab TJB |
133 | uint32_t num_instruction_bps; |
134 | uint32_t num_data_bps; | |
135 | uint32_t num_condition_regs; | |
136 | uint32_t data_bp_alignment; | |
0df8b418 | 137 | uint32_t sizeof_condition; /* size of the DVC register. */ |
6ffbb7ab TJB |
138 | uint64_t features; |
139 | }; | |
140 | ||
141 | /* Features will have bits indicating whether there is support for: */ | |
142 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
143 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
144 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
145 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
146 | ||
147 | struct ppc_hw_breakpoint | |
148 | { | |
149 | uint32_t version; /* currently, version must be 1 */ | |
150 | uint32_t trigger_type; /* only some combinations allowed */ | |
151 | uint32_t addr_mode; /* address match mode */ | |
152 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
153 | uint64_t addr; /* break/watchpoint address */ | |
154 | uint64_t addr2; /* range end or mask */ | |
155 | uint64_t condition_value; /* contents of the DVC register */ | |
156 | }; | |
157 | ||
158 | /* Trigger type. */ | |
159 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
160 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
161 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
162 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
163 | ||
164 | /* Address mode. */ | |
165 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
166 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
167 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
168 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
169 | ||
170 | /* Condition mode. */ | |
171 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
172 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
173 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
174 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
175 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
176 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
177 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
178 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
179 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) | |
180 | #endif /* PPC_PTRACE_GETHWDBGINFO */ | |
181 | ||
182 | ||
183 | ||
1dfe79e8 SDJ |
184 | /* Similarly for the general-purpose (gp0 -- gp31) |
185 | and floating-point registers (fp0 -- fp31). */ | |
186 | #ifndef PTRACE_GETREGS | |
187 | #define PTRACE_GETREGS 12 | |
188 | #endif | |
189 | #ifndef PTRACE_SETREGS | |
190 | #define PTRACE_SETREGS 13 | |
191 | #endif | |
192 | #ifndef PTRACE_GETFPREGS | |
193 | #define PTRACE_GETFPREGS 14 | |
194 | #endif | |
195 | #ifndef PTRACE_SETFPREGS | |
196 | #define PTRACE_SETFPREGS 15 | |
197 | #endif | |
198 | ||
9abe5450 EZ |
199 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
200 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
201 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
202 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
203 | flat array of chars, so that it is easier to manipulate for gdb. | |
204 | ||
205 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
206 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 207 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
208 | Appended to this there is space for the VRSAVE register: 4 bytes. |
209 | Even though this vrsave register is not included in the regset | |
210 | typedef, it is handled by the ptrace requests. | |
211 | ||
212 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
213 | therefore the offset at which the real value of the VSCR register | |
214 | is located will be always 12 bytes. | |
215 | ||
216 | The layout is like this (where x is the actual value of the vscr reg): */ | |
217 | ||
218 | /* *INDENT-OFF* */ | |
219 | /* | |
220 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
221 | <-------> <-------><-------><-> | |
222 | VR0 VR31 VSCR VRSAVE | |
223 | */ | |
224 | /* *INDENT-ON* */ | |
225 | ||
226 | #define SIZEOF_VRREGS 33*16+4 | |
227 | ||
228 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
229 | ||
604c2f83 LM |
230 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
231 | with the existing FPR and VMX registers. | |
232 | ||
233 | VSR doubleword 0 VSR doubleword 1 | |
234 | ---------------------------------------------------------------- | |
235 | VSR[0] | FPR[0] | | | |
236 | ---------------------------------------------------------------- | |
237 | VSR[1] | FPR[1] | | | |
238 | ---------------------------------------------------------------- | |
239 | | ... | | | |
240 | | ... | | | |
241 | ---------------------------------------------------------------- | |
242 | VSR[30] | FPR[30] | | | |
243 | ---------------------------------------------------------------- | |
244 | VSR[31] | FPR[31] | | | |
245 | ---------------------------------------------------------------- | |
246 | VSR[32] | VR[0] | | |
247 | ---------------------------------------------------------------- | |
248 | VSR[33] | VR[1] | | |
249 | ---------------------------------------------------------------- | |
250 | | ... | | |
251 | | ... | | |
252 | ---------------------------------------------------------------- | |
253 | VSR[62] | VR[30] | | |
254 | ---------------------------------------------------------------- | |
255 | VSR[63] | VR[31] | | |
256 | ---------------------------------------------------------------- | |
257 | ||
258 | VSX has 64 128bit registers. The first 32 registers overlap with | |
259 | the FP registers (doubleword 0) and hence extend them with additional | |
260 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
261 | registers. */ | |
262 | #define SIZEOF_VSXREGS 32*8 | |
263 | ||
264 | typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; | |
01904826 | 265 | |
b021a221 | 266 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 267 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
268 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
269 | ptrace calls only access the lower half of each register, to allow | |
270 | them to behave the same way they do on non-SPE systems. There's a | |
271 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
272 | read and write the top halves of all the general-purpose registers | |
273 | at once, along with some SPE-specific registers. | |
01904826 JB |
274 | |
275 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 276 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 277 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
278 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
279 | bottom halves together. | |
01904826 JB |
280 | |
281 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
282 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
283 | struct gdb_evrregset_t | |
284 | { | |
285 | unsigned long evr[32]; | |
286 | unsigned long long acc; | |
287 | unsigned long spefscr; | |
288 | }; | |
289 | ||
604c2f83 LM |
290 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
291 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
292 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
293 | gotten an error. Note that VSX registers 32 through 63 overlap | |
294 | with VR registers 0 through 31. */ | |
295 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
296 | |
297 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
298 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
299 | registers. Zero if we've tried one of them and gotten an | |
300 | error. */ | |
9abe5450 EZ |
301 | int have_ptrace_getvrregs = 1; |
302 | ||
01904826 JB |
303 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
304 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
305 | registers. Zero if we've tried one of them and gotten an | |
306 | error. */ | |
307 | int have_ptrace_getsetevrregs = 1; | |
308 | ||
1dfe79e8 SDJ |
309 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
310 | PTRACE_SETREGS requests, for reading and writing the | |
311 | general-purpose registers. Zero if we've tried one of | |
312 | them and gotten an error. */ | |
313 | int have_ptrace_getsetregs = 1; | |
314 | ||
315 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
316 | PTRACE_SETFPREGS requests, for reading and writing the | |
317 | floating-pointers registers. Zero if we've tried one of | |
318 | them and gotten an error. */ | |
319 | int have_ptrace_getsetfpregs = 1; | |
320 | ||
16333c4f EZ |
321 | /* *INDENT-OFF* */ |
322 | /* registers layout, as presented by the ptrace interface: | |
323 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
324 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
325 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
326 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
327 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
328 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
329 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
330 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
331 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
332 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
333 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
334 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f EZ |
335 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
336 | /* *INDENT_ON * */ | |
c877c8e6 | 337 | |
45229ea4 | 338 | static int |
e101270f | 339 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 340 | { |
16333c4f | 341 | int u_addr = -1; |
e101270f | 342 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
343 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
344 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 345 | int wordsize = sizeof (long); |
16333c4f | 346 | |
0df8b418 | 347 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
348 | if (regno >= tdep->ppc_gp0_regnum |
349 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 350 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 351 | |
49ff75ad JB |
352 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
353 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
354 | slot each in 64-bit interface. */ | |
383f0f5b JB |
355 | if (tdep->ppc_fp0_regnum >= 0 |
356 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
357 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
358 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 359 | |
0df8b418 | 360 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 361 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 362 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 363 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 364 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 365 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 366 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 367 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 368 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 369 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 370 | u_addr = PT_CTR * wordsize; |
f8c59253 | 371 | #ifdef PT_MQ |
dc5cfeb6 | 372 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 373 | u_addr = PT_MQ * wordsize; |
f8c59253 | 374 | #endif |
dc5cfeb6 | 375 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 376 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
377 | if (regno == PPC_ORIG_R3_REGNUM) |
378 | u_addr = PT_ORIG_R3 * wordsize; | |
379 | if (regno == PPC_TRAP_REGNUM) | |
380 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
381 | if (tdep->ppc_fpscr_regnum >= 0 |
382 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
383 | { |
384 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
385 | kernel headers incorrectly contained the 32-bit definition of | |
386 | PT_FPSCR. For the 32-bit definition, floating-point | |
387 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 388 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
389 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
390 | hence no adjustment is necessary. Hack around this. */ | |
391 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
392 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
393 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
394 | slot and not just its second word. The PT_FPSCR supplied when | |
395 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
396 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
397 | && PT_FPSCR == (48 + 2*32 + 1)) | |
398 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
399 | else |
400 | u_addr = PT_FPSCR * wordsize; | |
401 | } | |
16333c4f | 402 | return u_addr; |
c877c8e6 KB |
403 | } |
404 | ||
604c2f83 LM |
405 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
406 | registers set mechanism, as opposed to the interface for all the | |
407 | other registers, that stores/fetches each register individually. */ | |
408 | static void | |
409 | fetch_vsx_register (struct regcache *regcache, int tid, int regno) | |
410 | { | |
411 | int ret; | |
412 | gdb_vsxregset_t regs; | |
413 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
414 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
415 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
416 | ||
417 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
418 | if (ret < 0) | |
419 | { | |
420 | if (errno == EIO) | |
421 | { | |
422 | have_ptrace_getsetvsxregs = 0; | |
423 | return; | |
424 | } | |
425 | perror_with_name (_("Unable to fetch VSX register")); | |
426 | } | |
427 | ||
428 | regcache_raw_supply (regcache, regno, | |
429 | regs + (regno - tdep->ppc_vsr0_upper_regnum) | |
430 | * vsxregsize); | |
431 | } | |
432 | ||
9abe5450 EZ |
433 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
434 | registers set mechanism, as opposed to the interface for all the | |
435 | other registers, that stores/fetches each register individually. */ | |
436 | static void | |
56be3814 | 437 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
438 | { |
439 | int ret; | |
440 | int offset = 0; | |
441 | gdb_vrregset_t regs; | |
40a6adc1 MD |
442 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
443 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
444 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
445 | |
446 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
447 | if (ret < 0) | |
448 | { | |
449 | if (errno == EIO) | |
450 | { | |
451 | have_ptrace_getvrregs = 0; | |
452 | return; | |
453 | } | |
e2e0b3e5 | 454 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
455 | } |
456 | ||
457 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
458 | long on the hardware. We deal only with the lower 4 bytes of the | |
459 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
460 | there is no need to define an offset for it. */ | |
461 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 462 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 463 | |
56be3814 | 464 | regcache_raw_supply (regcache, regno, |
0df8b418 MS |
465 | regs + (regno |
466 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
467 | } |
468 | ||
01904826 JB |
469 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
470 | SPE-specific registers, and place the results in EVRREGSET. If we | |
471 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
472 | zeros. | |
473 | ||
474 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
475 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
476 | set_spe_registers. */ | |
477 | static void | |
478 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
479 | { | |
480 | if (have_ptrace_getsetevrregs) | |
481 | { | |
482 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
483 | return; | |
484 | else | |
485 | { | |
486 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
487 | we just return zeros. */ | |
488 | if (errno == EIO) | |
489 | have_ptrace_getsetevrregs = 0; | |
490 | else | |
491 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 492 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
493 | } |
494 | } | |
495 | ||
496 | memset (evrregset, 0, sizeof (*evrregset)); | |
497 | } | |
498 | ||
6ced10dd JB |
499 | /* Supply values from TID for SPE-specific raw registers: the upper |
500 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
501 | be the number of an upper half register, acc, spefscr, or -1 to | |
502 | supply the values of all registers. */ | |
01904826 | 503 | static void |
56be3814 | 504 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 505 | { |
40a6adc1 MD |
506 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
507 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
508 | struct gdb_evrregset_t evrregs; |
509 | ||
6ced10dd | 510 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 511 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 512 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 513 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 514 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 515 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 516 | |
01904826 JB |
517 | get_spe_registers (tid, &evrregs); |
518 | ||
6ced10dd | 519 | if (regno == -1) |
01904826 | 520 | { |
6ced10dd JB |
521 | int i; |
522 | ||
523 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 524 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 525 | &evrregs.evr[i]); |
01904826 | 526 | } |
6ced10dd JB |
527 | else if (tdep->ppc_ev0_upper_regnum <= regno |
528 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 529 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
530 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
531 | ||
532 | if (regno == -1 | |
533 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 534 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
535 | |
536 | if (regno == -1 | |
537 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 538 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 539 | &evrregs.spefscr); |
01904826 JB |
540 | } |
541 | ||
45229ea4 | 542 | static void |
56be3814 | 543 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 544 | { |
40a6adc1 MD |
545 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
546 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 547 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 548 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 549 | int bytes_transferred; |
0df8b418 | 550 | unsigned int offset; /* Offset of registers within the u area. */ |
d9d9c31f | 551 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 552 | |
be8626e0 | 553 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
554 | { |
555 | /* If this is the first time through, or if it is not the first | |
556 | time through, and we have comfirmed that there is kernel | |
557 | support for such a ptrace request, then go and fetch the | |
558 | register. */ | |
559 | if (have_ptrace_getvrregs) | |
560 | { | |
56be3814 | 561 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
562 | return; |
563 | } | |
564 | /* If we have discovered that there is no ptrace support for | |
565 | AltiVec registers, fall through and return zeroes, because | |
566 | regaddr will be -1 in this case. */ | |
567 | } | |
604c2f83 LM |
568 | if (vsx_register_p (gdbarch, regno)) |
569 | { | |
570 | if (have_ptrace_getsetvsxregs) | |
571 | { | |
572 | fetch_vsx_register (regcache, tid, regno); | |
573 | return; | |
574 | } | |
575 | } | |
be8626e0 | 576 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 577 | { |
56be3814 | 578 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
579 | return; |
580 | } | |
9abe5450 | 581 | |
45229ea4 EZ |
582 | if (regaddr == -1) |
583 | { | |
40a6adc1 | 584 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 585 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
586 | return; |
587 | } | |
588 | ||
411cb3f9 | 589 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
590 | 32-bit platform, 64-bit floating-point registers will require two |
591 | transfers. */ | |
4a19ea35 | 592 | for (bytes_transferred = 0; |
40a6adc1 | 593 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 594 | bytes_transferred += sizeof (long)) |
45229ea4 | 595 | { |
11fde611 JK |
596 | long l; |
597 | ||
45229ea4 | 598 | errno = 0; |
11fde611 | 599 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 600 | regaddr += sizeof (long); |
45229ea4 EZ |
601 | if (errno != 0) |
602 | { | |
bc97b3ba JB |
603 | char message[128]; |
604 | sprintf (message, "reading register %s (#%d)", | |
40a6adc1 | 605 | gdbarch_register_name (gdbarch, regno), regno); |
bc97b3ba | 606 | perror_with_name (message); |
45229ea4 | 607 | } |
11fde611 | 608 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 609 | } |
56d0d96a | 610 | |
4a19ea35 JB |
611 | /* Now supply the register. Keep in mind that the regcache's idea |
612 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 613 | (long). */ |
40a6adc1 | 614 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
615 | { |
616 | /* Little-endian values are always found at the left end of the | |
617 | bytes transferred. */ | |
56be3814 | 618 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 | 619 | } |
40a6adc1 | 620 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
621 | { |
622 | /* Big-endian values are found at the right end of the bytes | |
623 | transferred. */ | |
40a6adc1 | 624 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
56be3814 | 625 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
626 | } |
627 | else | |
a44bddec | 628 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 629 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 630 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
631 | } |
632 | ||
604c2f83 LM |
633 | static void |
634 | supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
635 | { | |
636 | int i; | |
637 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
638 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
639 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
640 | ||
641 | for (i = 0; i < ppc_num_vshrs; i++) | |
642 | { | |
643 | regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
644 | *vsxregsetp + i * vsxregsize); | |
645 | } | |
646 | } | |
647 | ||
9abe5450 | 648 | static void |
56be3814 | 649 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
650 | { |
651 | int i; | |
40a6adc1 MD |
652 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
653 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 654 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
655 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
656 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
657 | |
658 | for (i = 0; i < num_of_vrregs; i++) | |
659 | { | |
660 | /* The last 2 registers of this set are only 32 bit long, not | |
661 | 128. However an offset is necessary only for VSCR because it | |
662 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
663 | slot. */ | |
664 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 665 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 666 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 667 | else |
56be3814 | 668 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 669 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
670 | } |
671 | } | |
672 | ||
604c2f83 LM |
673 | static void |
674 | fetch_vsx_registers (struct regcache *regcache, int tid) | |
675 | { | |
676 | int ret; | |
677 | gdb_vsxregset_t regs; | |
678 | ||
679 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
680 | if (ret < 0) | |
681 | { | |
682 | if (errno == EIO) | |
683 | { | |
684 | have_ptrace_getsetvsxregs = 0; | |
685 | return; | |
686 | } | |
687 | perror_with_name (_("Unable to fetch VSX registers")); | |
688 | } | |
689 | supply_vsxregset (regcache, ®s); | |
690 | } | |
691 | ||
9abe5450 | 692 | static void |
56be3814 | 693 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
694 | { |
695 | int ret; | |
696 | gdb_vrregset_t regs; | |
697 | ||
698 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
699 | if (ret < 0) | |
700 | { | |
701 | if (errno == EIO) | |
702 | { | |
703 | have_ptrace_getvrregs = 0; | |
704 | return; | |
705 | } | |
e2e0b3e5 | 706 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 707 | } |
56be3814 | 708 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
709 | } |
710 | ||
1dfe79e8 SDJ |
711 | /* This function actually issues the request to ptrace, telling |
712 | it to get all general-purpose registers and put them into the | |
713 | specified regset. | |
714 | ||
715 | If the ptrace request does not exist, this function returns 0 | |
716 | and properly sets the have_ptrace_* flag. If the request fails, | |
717 | this function calls perror_with_name. Otherwise, if the request | |
718 | succeeds, then the regcache gets filled and 1 is returned. */ | |
719 | static int | |
720 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
721 | { | |
722 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
723 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
724 | gdb_gregset_t gregset; | |
725 | ||
726 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
727 | { | |
728 | if (errno == EIO) | |
729 | { | |
730 | have_ptrace_getsetregs = 0; | |
731 | return 0; | |
732 | } | |
733 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
734 | } | |
735 | ||
736 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
737 | ||
738 | return 1; | |
739 | } | |
740 | ||
741 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
742 | responsible for verifying if this target has the ptrace request | |
743 | that can be used to fetch all general-purpose registers at one | |
744 | shot. If it doesn't, then we should fetch them using the | |
745 | old-fashioned way, which is to iterate over the registers and | |
746 | request them one by one. */ | |
747 | static void | |
748 | fetch_gp_regs (struct regcache *regcache, int tid) | |
749 | { | |
750 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
751 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
752 | int i; | |
753 | ||
754 | if (have_ptrace_getsetregs) | |
755 | if (fetch_all_gp_regs (regcache, tid)) | |
756 | return; | |
757 | ||
758 | /* If we've hit this point, it doesn't really matter which | |
759 | architecture we are using. We just need to read the | |
760 | registers in the "old-fashioned way". */ | |
761 | for (i = 0; i < ppc_num_gprs; i++) | |
762 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
763 | } | |
764 | ||
765 | /* This function actually issues the request to ptrace, telling | |
766 | it to get all floating-point registers and put them into the | |
767 | specified regset. | |
768 | ||
769 | If the ptrace request does not exist, this function returns 0 | |
770 | and properly sets the have_ptrace_* flag. If the request fails, | |
771 | this function calls perror_with_name. Otherwise, if the request | |
772 | succeeds, then the regcache gets filled and 1 is returned. */ | |
773 | static int | |
774 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
775 | { | |
776 | gdb_fpregset_t fpregs; | |
777 | ||
778 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
779 | { | |
780 | if (errno == EIO) | |
781 | { | |
782 | have_ptrace_getsetfpregs = 0; | |
783 | return 0; | |
784 | } | |
785 | perror_with_name (_("Couldn't get floating-point registers.")); | |
786 | } | |
787 | ||
788 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
789 | ||
790 | return 1; | |
791 | } | |
792 | ||
793 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
794 | responsible for verifying if this target has the ptrace request | |
795 | that can be used to fetch all floating-point registers at one | |
796 | shot. If it doesn't, then we should fetch them using the | |
797 | old-fashioned way, which is to iterate over the registers and | |
798 | request them one by one. */ | |
799 | static void | |
800 | fetch_fp_regs (struct regcache *regcache, int tid) | |
801 | { | |
802 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
803 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
804 | int i; | |
805 | ||
806 | if (have_ptrace_getsetfpregs) | |
807 | if (fetch_all_fp_regs (regcache, tid)) | |
808 | return; | |
809 | ||
810 | /* If we've hit this point, it doesn't really matter which | |
811 | architecture we are using. We just need to read the | |
812 | registers in the "old-fashioned way". */ | |
813 | for (i = 0; i < ppc_num_fprs; i++) | |
814 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
815 | } | |
816 | ||
45229ea4 | 817 | static void |
56be3814 | 818 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
819 | { |
820 | int i; | |
40a6adc1 MD |
821 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
822 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 823 | |
1dfe79e8 | 824 | fetch_gp_regs (regcache, tid); |
32b99774 | 825 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 826 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 827 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 828 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 829 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 830 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 831 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 832 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 833 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 834 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 835 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 836 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 837 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 838 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 839 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
840 | if (ppc_linux_trap_reg_p (gdbarch)) |
841 | { | |
842 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
843 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
844 | } | |
32b99774 | 845 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 846 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
847 | if (have_ptrace_getvrregs) |
848 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 849 | fetch_altivec_registers (regcache, tid); |
604c2f83 LM |
850 | if (have_ptrace_getsetvsxregs) |
851 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
852 | fetch_vsx_registers (regcache, tid); | |
6ced10dd | 853 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 854 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
855 | } |
856 | ||
857 | /* Fetch registers from the child process. Fetch all registers if | |
858 | regno == -1, otherwise fetch all general registers or all floating | |
859 | point registers depending upon the value of regno. */ | |
10d6c8cd | 860 | static void |
28439f5e PA |
861 | ppc_linux_fetch_inferior_registers (struct target_ops *ops, |
862 | struct regcache *regcache, int regno) | |
45229ea4 | 863 | { |
0df8b418 | 864 | /* Overload thread id onto process id. */ |
05f13b9c EZ |
865 | int tid = TIDGET (inferior_ptid); |
866 | ||
0df8b418 | 867 | /* No thread id, just use process id. */ |
05f13b9c EZ |
868 | if (tid == 0) |
869 | tid = PIDGET (inferior_ptid); | |
870 | ||
9abe5450 | 871 | if (regno == -1) |
56be3814 | 872 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 873 | else |
56be3814 | 874 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
875 | } |
876 | ||
0df8b418 | 877 | /* Store one VSX register. */ |
604c2f83 LM |
878 | static void |
879 | store_vsx_register (const struct regcache *regcache, int tid, int regno) | |
880 | { | |
881 | int ret; | |
882 | gdb_vsxregset_t regs; | |
883 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
884 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
885 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
886 | ||
9fe70b4f | 887 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
888 | if (ret < 0) |
889 | { | |
890 | if (errno == EIO) | |
891 | { | |
892 | have_ptrace_getsetvsxregs = 0; | |
893 | return; | |
894 | } | |
895 | perror_with_name (_("Unable to fetch VSX register")); | |
896 | } | |
897 | ||
898 | regcache_raw_collect (regcache, regno, regs + | |
899 | (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); | |
900 | ||
901 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
902 | if (ret < 0) | |
903 | perror_with_name (_("Unable to store VSX register")); | |
904 | } | |
905 | ||
0df8b418 | 906 | /* Store one register. */ |
9abe5450 | 907 | static void |
56be3814 | 908 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
909 | { |
910 | int ret; | |
911 | int offset = 0; | |
912 | gdb_vrregset_t regs; | |
40a6adc1 MD |
913 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
914 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
915 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
916 | |
917 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
918 | if (ret < 0) | |
919 | { | |
920 | if (errno == EIO) | |
921 | { | |
922 | have_ptrace_getvrregs = 0; | |
923 | return; | |
924 | } | |
e2e0b3e5 | 925 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
926 | } |
927 | ||
928 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
929 | long on the hardware. */ | |
930 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 931 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 932 | |
56be3814 | 933 | regcache_raw_collect (regcache, regno, |
0df8b418 MS |
934 | regs + (regno |
935 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
936 | |
937 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
938 | if (ret < 0) | |
e2e0b3e5 | 939 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
940 | } |
941 | ||
01904826 JB |
942 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
943 | general-purpose registers and its SPE-specific registers to the | |
944 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
945 | nothing. | |
946 | ||
947 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
948 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
949 | get_spe_registers. */ | |
950 | static void | |
951 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
952 | { | |
953 | if (have_ptrace_getsetevrregs) | |
954 | { | |
955 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
956 | return; | |
957 | else | |
958 | { | |
959 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
960 | supported; we fail silently, and don't try the call | |
961 | again. */ | |
962 | if (errno == EIO) | |
963 | have_ptrace_getsetevrregs = 0; | |
964 | else | |
965 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 966 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
967 | } |
968 | } | |
969 | } | |
970 | ||
6ced10dd JB |
971 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
972 | If REGNO is -1, write the values of all the SPE-specific | |
973 | registers. */ | |
01904826 | 974 | static void |
56be3814 | 975 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 976 | { |
40a6adc1 MD |
977 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
978 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
979 | struct gdb_evrregset_t evrregs; |
980 | ||
6ced10dd | 981 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 982 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 983 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 984 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 985 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 986 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 987 | |
6ced10dd JB |
988 | if (regno == -1) |
989 | /* Since we're going to write out every register, the code below | |
990 | should store to every field of evrregs; if that doesn't happen, | |
991 | make it obvious by initializing it with suspicious values. */ | |
992 | memset (&evrregs, 42, sizeof (evrregs)); | |
993 | else | |
994 | /* We can only read and write the entire EVR register set at a | |
995 | time, so to write just a single register, we do a | |
996 | read-modify-write maneuver. */ | |
997 | get_spe_registers (tid, &evrregs); | |
998 | ||
999 | if (regno == -1) | |
01904826 | 1000 | { |
6ced10dd JB |
1001 | int i; |
1002 | ||
1003 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 1004 | regcache_raw_collect (regcache, |
6ced10dd JB |
1005 | tdep->ppc_ev0_upper_regnum + i, |
1006 | &evrregs.evr[i]); | |
01904826 | 1007 | } |
6ced10dd JB |
1008 | else if (tdep->ppc_ev0_upper_regnum <= regno |
1009 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 1010 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
1011 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
1012 | ||
1013 | if (regno == -1 | |
1014 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 1015 | regcache_raw_collect (regcache, |
6ced10dd JB |
1016 | tdep->ppc_acc_regnum, |
1017 | &evrregs.acc); | |
1018 | ||
1019 | if (regno == -1 | |
1020 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 1021 | regcache_raw_collect (regcache, |
6ced10dd JB |
1022 | tdep->ppc_spefscr_regnum, |
1023 | &evrregs.spefscr); | |
01904826 JB |
1024 | |
1025 | /* Write back the modified register set. */ | |
1026 | set_spe_registers (tid, &evrregs); | |
1027 | } | |
1028 | ||
45229ea4 | 1029 | static void |
56be3814 | 1030 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1031 | { |
40a6adc1 MD |
1032 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1033 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 1034 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 1035 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 1036 | int i; |
4a19ea35 | 1037 | size_t bytes_to_transfer; |
d9d9c31f | 1038 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 1039 | |
be8626e0 | 1040 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 1041 | { |
56be3814 | 1042 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
1043 | return; |
1044 | } | |
604c2f83 LM |
1045 | if (vsx_register_p (gdbarch, regno)) |
1046 | { | |
1047 | store_vsx_register (regcache, tid, regno); | |
1048 | return; | |
1049 | } | |
be8626e0 | 1050 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 1051 | { |
56be3814 | 1052 | store_spe_register (regcache, tid, regno); |
01904826 JB |
1053 | return; |
1054 | } | |
45229ea4 | 1055 | |
9abe5450 EZ |
1056 | if (regaddr == -1) |
1057 | return; | |
1058 | ||
4a19ea35 JB |
1059 | /* First collect the register. Keep in mind that the regcache's |
1060 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1061 | (long). */ |
56d0d96a | 1062 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
1063 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
1064 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
1065 | { |
1066 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 1067 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 1068 | } |
40a6adc1 | 1069 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1070 | { |
1071 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 1072 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
56be3814 | 1073 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
1074 | } |
1075 | ||
411cb3f9 | 1076 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 1077 | { |
11fde611 JK |
1078 | long l; |
1079 | ||
1080 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 1081 | errno = 0; |
11fde611 | 1082 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 1083 | regaddr += sizeof (long); |
e3f36dbd KB |
1084 | |
1085 | if (errno == EIO | |
7284e1be UW |
1086 | && (regno == tdep->ppc_fpscr_regnum |
1087 | || regno == PPC_ORIG_R3_REGNUM | |
1088 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1089 | { |
7284e1be UW |
1090 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1091 | or trap to be written. */ | |
e3f36dbd KB |
1092 | continue; |
1093 | } | |
1094 | ||
45229ea4 EZ |
1095 | if (errno != 0) |
1096 | { | |
bc97b3ba JB |
1097 | char message[128]; |
1098 | sprintf (message, "writing register %s (#%d)", | |
40a6adc1 | 1099 | gdbarch_register_name (gdbarch, regno), regno); |
bc97b3ba | 1100 | perror_with_name (message); |
45229ea4 EZ |
1101 | } |
1102 | } | |
1103 | } | |
1104 | ||
604c2f83 LM |
1105 | static void |
1106 | fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
1107 | { | |
1108 | int i; | |
1109 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1110 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1111 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
1112 | ||
1113 | for (i = 0; i < ppc_num_vshrs; i++) | |
1114 | regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
1115 | *vsxregsetp + i * vsxregsize); | |
1116 | } | |
1117 | ||
9abe5450 | 1118 | static void |
56be3814 | 1119 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
1120 | { |
1121 | int i; | |
40a6adc1 MD |
1122 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1123 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 1124 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
1125 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
1126 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
1127 | |
1128 | for (i = 0; i < num_of_vrregs; i++) | |
1129 | { | |
1130 | /* The last 2 registers of this set are only 32 bit long, not | |
1131 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
1132 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 1133 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1134 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 1135 | else |
56be3814 | 1136 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1137 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
1138 | } |
1139 | } | |
1140 | ||
604c2f83 LM |
1141 | static void |
1142 | store_vsx_registers (const struct regcache *regcache, int tid) | |
1143 | { | |
1144 | int ret; | |
1145 | gdb_vsxregset_t regs; | |
1146 | ||
1147 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
1148 | if (ret < 0) | |
1149 | { | |
1150 | if (errno == EIO) | |
1151 | { | |
1152 | have_ptrace_getsetvsxregs = 0; | |
1153 | return; | |
1154 | } | |
1155 | perror_with_name (_("Couldn't get VSX registers")); | |
1156 | } | |
1157 | ||
1158 | fill_vsxregset (regcache, ®s); | |
1159 | ||
1160 | if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) | |
1161 | perror_with_name (_("Couldn't write VSX registers")); | |
1162 | } | |
1163 | ||
9abe5450 | 1164 | static void |
56be3814 | 1165 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
1166 | { |
1167 | int ret; | |
1168 | gdb_vrregset_t regs; | |
1169 | ||
0897f59b | 1170 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
1171 | if (ret < 0) |
1172 | { | |
1173 | if (errno == EIO) | |
1174 | { | |
1175 | have_ptrace_getvrregs = 0; | |
1176 | return; | |
1177 | } | |
e2e0b3e5 | 1178 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
1179 | } |
1180 | ||
56be3814 | 1181 | fill_vrregset (regcache, ®s); |
9abe5450 | 1182 | |
0897f59b | 1183 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 1184 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
1185 | } |
1186 | ||
1dfe79e8 SDJ |
1187 | /* This function actually issues the request to ptrace, telling |
1188 | it to store all general-purpose registers present in the specified | |
1189 | regset. | |
1190 | ||
1191 | If the ptrace request does not exist, this function returns 0 | |
1192 | and properly sets the have_ptrace_* flag. If the request fails, | |
1193 | this function calls perror_with_name. Otherwise, if the request | |
1194 | succeeds, then the regcache is stored and 1 is returned. */ | |
1195 | static int | |
1196 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1197 | { | |
1198 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1199 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1200 | gdb_gregset_t gregset; | |
1201 | ||
1202 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1203 | { | |
1204 | if (errno == EIO) | |
1205 | { | |
1206 | have_ptrace_getsetregs = 0; | |
1207 | return 0; | |
1208 | } | |
1209 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1210 | } | |
1211 | ||
1212 | fill_gregset (regcache, &gregset, regno); | |
1213 | ||
1214 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1215 | { | |
1216 | if (errno == EIO) | |
1217 | { | |
1218 | have_ptrace_getsetregs = 0; | |
1219 | return 0; | |
1220 | } | |
1221 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1222 | } | |
1223 | ||
1224 | return 1; | |
1225 | } | |
1226 | ||
1227 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1228 | responsible for verifying if this target has the ptrace request | |
1229 | that can be used to store all general-purpose registers at one | |
1230 | shot. If it doesn't, then we should store them using the | |
1231 | old-fashioned way, which is to iterate over the registers and | |
1232 | store them one by one. */ | |
45229ea4 | 1233 | static void |
1dfe79e8 | 1234 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1235 | { |
40a6adc1 MD |
1236 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1237 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dfe79e8 SDJ |
1238 | int i; |
1239 | ||
1240 | if (have_ptrace_getsetregs) | |
1241 | if (store_all_gp_regs (regcache, tid, regno)) | |
1242 | return; | |
1243 | ||
1244 | /* If we hit this point, it doesn't really matter which | |
1245 | architecture we are using. We just need to store the | |
1246 | registers in the "old-fashioned way". */ | |
6ced10dd | 1247 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1248 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1249 | } |
1250 | ||
1251 | /* This function actually issues the request to ptrace, telling | |
1252 | it to store all floating-point registers present in the specified | |
1253 | regset. | |
1254 | ||
1255 | If the ptrace request does not exist, this function returns 0 | |
1256 | and properly sets the have_ptrace_* flag. If the request fails, | |
1257 | this function calls perror_with_name. Otherwise, if the request | |
1258 | succeeds, then the regcache is stored and 1 is returned. */ | |
1259 | static int | |
1260 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1261 | { | |
1262 | gdb_fpregset_t fpregs; | |
1263 | ||
1264 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1265 | { | |
1266 | if (errno == EIO) | |
1267 | { | |
1268 | have_ptrace_getsetfpregs = 0; | |
1269 | return 0; | |
1270 | } | |
1271 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1272 | } | |
1273 | ||
1274 | fill_fpregset (regcache, &fpregs, regno); | |
1275 | ||
1276 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1277 | { | |
1278 | if (errno == EIO) | |
1279 | { | |
1280 | have_ptrace_getsetfpregs = 0; | |
1281 | return 0; | |
1282 | } | |
1283 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1284 | } | |
1285 | ||
1286 | return 1; | |
1287 | } | |
1288 | ||
1289 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1290 | responsible for verifying if this target has the ptrace request | |
1291 | that can be used to store all floating-point registers at one | |
1292 | shot. If it doesn't, then we should store them using the | |
1293 | old-fashioned way, which is to iterate over the registers and | |
1294 | store them one by one. */ | |
1295 | static void | |
1296 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1297 | { | |
1298 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1299 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1300 | int i; | |
1301 | ||
1302 | if (have_ptrace_getsetfpregs) | |
1303 | if (store_all_fp_regs (regcache, tid, regno)) | |
1304 | return; | |
1305 | ||
1306 | /* If we hit this point, it doesn't really matter which | |
1307 | architecture we are using. We just need to store the | |
1308 | registers in the "old-fashioned way". */ | |
1309 | for (i = 0; i < ppc_num_fprs; i++) | |
1310 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1311 | } | |
1312 | ||
1313 | static void | |
1314 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1315 | { | |
1316 | int i; | |
1317 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1318 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1319 | ||
1320 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1321 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1322 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1323 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1324 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1325 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1326 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1327 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1328 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1329 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1330 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1331 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1332 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1333 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1334 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1335 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1336 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1337 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1338 | if (ppc_linux_trap_reg_p (gdbarch)) |
1339 | { | |
1340 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1341 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1342 | } | |
9abe5450 EZ |
1343 | if (have_ptrace_getvrregs) |
1344 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 1345 | store_altivec_registers (regcache, tid); |
604c2f83 LM |
1346 | if (have_ptrace_getsetvsxregs) |
1347 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
1348 | store_vsx_registers (regcache, tid); | |
6ced10dd | 1349 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1350 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
1351 | } |
1352 | ||
6ffbb7ab | 1353 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
b261e0c5 UW |
1354 | static unsigned long |
1355 | ppc_linux_get_hwcap (void) | |
6ffbb7ab TJB |
1356 | { |
1357 | CORE_ADDR field; | |
1358 | ||
1359 | if (target_auxv_search (¤t_target, AT_HWCAP, &field)) | |
1360 | return (unsigned long) field; | |
1361 | ||
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | /* The cached DABR value, to install in new threads. | |
1366 | This variable is used when we are dealing with non-BookE | |
1367 | processors. */ | |
1368 | static long saved_dabr_value; | |
1369 | ||
1370 | /* Global structure that will store information about the available | |
1371 | features on this BookE processor. */ | |
1372 | static struct ppc_debug_info booke_debug_info; | |
1373 | ||
1374 | /* Global variable that holds the maximum number of slots that the | |
1375 | kernel will use. This is only used when the processor is BookE. */ | |
1376 | static size_t max_slots_number = 0; | |
1377 | ||
1378 | struct hw_break_tuple | |
1379 | { | |
1380 | long slot; | |
1381 | struct ppc_hw_breakpoint *hw_break; | |
1382 | }; | |
1383 | ||
1384 | /* This is an internal VEC created to store information about *points inserted | |
1385 | for each thread. This is used for BookE processors. */ | |
1386 | typedef struct thread_points | |
1387 | { | |
1388 | /* The TID to which this *point relates. */ | |
1389 | int tid; | |
1390 | /* Information about the *point, such as its address, type, etc. | |
1391 | ||
1392 | Each element inside this vector corresponds to a hardware | |
1393 | breakpoint or watchpoint in the thread represented by TID. The maximum | |
1394 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of | |
1395 | the tuple is NULL, then the position in the vector is free. */ | |
1396 | struct hw_break_tuple *hw_breaks; | |
1397 | } *thread_points_p; | |
1398 | DEF_VEC_P (thread_points_p); | |
1399 | ||
1400 | VEC(thread_points_p) *ppc_threads = NULL; | |
1401 | ||
1402 | /* The version of the kernel interface that we will use if the processor is | |
1403 | BookE. */ | |
1404 | #define PPC_DEBUG_CURRENT_VERSION 1 | |
1405 | ||
1406 | /* Returns non-zero if we support the ptrace interface which enables | |
1407 | booke debugging resources. */ | |
e0d24f8d | 1408 | static int |
6ffbb7ab | 1409 | have_ptrace_booke_interface (void) |
e0d24f8d | 1410 | { |
6ffbb7ab | 1411 | static int have_ptrace_booke_interface = -1; |
e0d24f8d | 1412 | |
6ffbb7ab TJB |
1413 | if (have_ptrace_booke_interface == -1) |
1414 | { | |
1415 | int tid; | |
e0d24f8d | 1416 | |
6ffbb7ab TJB |
1417 | tid = TIDGET (inferior_ptid); |
1418 | if (tid == 0) | |
1419 | tid = PIDGET (inferior_ptid); | |
e0d24f8d | 1420 | |
6ffbb7ab TJB |
1421 | /* Check for kernel support for BOOKE debug registers. */ |
1422 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &booke_debug_info) >= 0) | |
1423 | { | |
0c56f59b EBM |
1424 | /* Check whether ptrace BOOKE interface is functional and |
1425 | provides any supported feature. */ | |
1426 | if (booke_debug_info.features != 0) | |
1427 | { | |
1428 | have_ptrace_booke_interface = 1; | |
1429 | max_slots_number = booke_debug_info.num_instruction_bps | |
1430 | + booke_debug_info.num_data_bps | |
1431 | + booke_debug_info.num_condition_regs; | |
1432 | return have_ptrace_booke_interface; | |
1433 | } | |
6ffbb7ab | 1434 | } |
0c56f59b EBM |
1435 | /* Old school interface and no BOOKE debug registers support. */ |
1436 | have_ptrace_booke_interface = 0; | |
1437 | memset (&booke_debug_info, 0, sizeof (struct ppc_debug_info)); | |
6ffbb7ab TJB |
1438 | } |
1439 | ||
1440 | return have_ptrace_booke_interface; | |
e0d24f8d WZ |
1441 | } |
1442 | ||
6ffbb7ab TJB |
1443 | static int |
1444 | ppc_linux_can_use_hw_breakpoint (int type, int cnt, int ot) | |
b7622095 | 1445 | { |
6ffbb7ab | 1446 | int total_hw_wp, total_hw_bp; |
b7622095 | 1447 | |
6ffbb7ab TJB |
1448 | if (have_ptrace_booke_interface ()) |
1449 | { | |
1450 | /* For PPC BookE processors, the number of available hardware | |
1451 | watchpoints and breakpoints is stored at the booke_debug_info | |
1452 | struct. */ | |
1453 | total_hw_bp = booke_debug_info.num_instruction_bps; | |
1454 | total_hw_wp = booke_debug_info.num_data_bps; | |
1455 | } | |
1456 | else | |
1457 | { | |
1458 | /* For PPC server processors, we accept 1 hardware watchpoint and 0 | |
1459 | hardware breakpoints. */ | |
1460 | total_hw_bp = 0; | |
1461 | total_hw_wp = 1; | |
1462 | } | |
b7622095 | 1463 | |
6ffbb7ab TJB |
1464 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
1465 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
1466 | { | |
bb08bdbd | 1467 | if (cnt + ot > total_hw_wp) |
6ffbb7ab TJB |
1468 | return -1; |
1469 | } | |
1470 | else if (type == bp_hardware_breakpoint) | |
1471 | { | |
1472 | if (cnt > total_hw_bp) | |
1473 | return -1; | |
1474 | } | |
1475 | ||
1476 | if (!have_ptrace_booke_interface ()) | |
1477 | { | |
1478 | int tid; | |
1479 | ptid_t ptid = inferior_ptid; | |
1480 | ||
0df8b418 MS |
1481 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
1482 | and whether the target has DABR. If either answer is no, the | |
1483 | ptrace call will return -1. Fail in that case. */ | |
6ffbb7ab TJB |
1484 | tid = TIDGET (ptid); |
1485 | if (tid == 0) | |
1486 | tid = PIDGET (ptid); | |
1487 | ||
1488 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1489 | return 0; | |
1490 | } | |
1491 | ||
1492 | return 1; | |
b7622095 LM |
1493 | } |
1494 | ||
e0d24f8d WZ |
1495 | static int |
1496 | ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
1497 | { | |
1498 | /* Handle sub-8-byte quantities. */ | |
1499 | if (len <= 0) | |
1500 | return 0; | |
1501 | ||
6ffbb7ab TJB |
1502 | /* The new BookE ptrace interface tells if there are alignment restrictions |
1503 | for watchpoints in the processors. In that case, we use that information | |
1504 | to determine the hardcoded watchable region for watchpoints. */ | |
1505 | if (have_ptrace_booke_interface ()) | |
1506 | { | |
e09342b5 TJB |
1507 | /* DAC-based processors (i.e., embedded processors), like the PowerPC 440 |
1508 | have ranged watchpoints and can watch any access within an arbitrary | |
1509 | memory region. This is useful to watch arrays and structs, for | |
1510 | instance. It takes two hardware watchpoints though. */ | |
1511 | if (len > 1 | |
1512 | && booke_debug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE) | |
1513 | return 2; | |
1514 | else if (booke_debug_info.data_bp_alignment | |
1515 | && (addr + len > (addr & ~(booke_debug_info.data_bp_alignment - 1)) | |
1516 | + booke_debug_info.data_bp_alignment)) | |
0cf6dd15 | 1517 | return 0; |
6ffbb7ab | 1518 | } |
b7622095 | 1519 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
6ffbb7ab TJB |
1520 | processors (i.e., server processors). Without the new BookE ptrace |
1521 | interface, DAC-based processors (i.e., embedded processors) will use | |
b7622095 | 1522 | addresses aligned to 4-bytes due to the way the read/write flags are |
6ffbb7ab TJB |
1523 | passed in the old ptrace interface. */ |
1524 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1525 | && (addr + len) > (addr & ~3) + 4) | |
1526 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1527 | return 0; |
1528 | ||
1529 | return 1; | |
1530 | } | |
1531 | ||
6ffbb7ab | 1532 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
e4166a49 | 1533 | static int |
6ffbb7ab TJB |
1534 | booke_cmp_hw_point (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
1535 | { | |
ad422571 TJB |
1536 | return (a->trigger_type == b->trigger_type |
1537 | && a->addr_mode == b->addr_mode | |
1538 | && a->condition_mode == b->condition_mode | |
1539 | && a->addr == b->addr | |
1540 | && a->addr2 == b->addr2 | |
6ffbb7ab TJB |
1541 | && a->condition_value == b->condition_value); |
1542 | } | |
1543 | ||
1544 | /* This function can be used to retrieve a thread_points by the TID of the | |
1545 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, | |
1546 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the | |
1547 | provided TID will be created and returned. */ | |
1548 | static struct thread_points * | |
1549 | booke_find_thread_points_by_tid (int tid, int alloc_new) | |
1550 | { | |
1551 | int i; | |
1552 | struct thread_points *t; | |
1553 | ||
1554 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) | |
1555 | if (t->tid == tid) | |
1556 | return t; | |
1557 | ||
1558 | t = NULL; | |
1559 | ||
1560 | /* Do we need to allocate a new point_item | |
1561 | if the wanted one does not exist? */ | |
1562 | if (alloc_new) | |
1563 | { | |
1564 | t = xmalloc (sizeof (struct thread_points)); | |
0df8b418 MS |
1565 | t->hw_breaks |
1566 | = xzalloc (max_slots_number * sizeof (struct hw_break_tuple)); | |
6ffbb7ab TJB |
1567 | t->tid = tid; |
1568 | VEC_safe_push (thread_points_p, ppc_threads, t); | |
1569 | } | |
1570 | ||
1571 | return t; | |
1572 | } | |
1573 | ||
1574 | /* This function is a generic wrapper that is responsible for inserting a | |
1575 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1576 | kernel) and registering it internally in GDB. */ | |
1577 | static void | |
1578 | booke_insert_point (struct ppc_hw_breakpoint *b, int tid) | |
1579 | { | |
1580 | int i; | |
1581 | long slot; | |
1582 | struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint)); | |
1583 | struct hw_break_tuple *hw_breaks; | |
1584 | struct cleanup *c = make_cleanup (xfree, p); | |
1585 | struct thread_points *t; | |
1586 | struct hw_break_tuple *tuple; | |
1587 | ||
1588 | memcpy (p, b, sizeof (struct ppc_hw_breakpoint)); | |
1589 | ||
1590 | errno = 0; | |
1591 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p); | |
1592 | if (slot < 0) | |
1593 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); | |
1594 | ||
1595 | /* Everything went fine, so we have to register this *point. */ | |
1596 | t = booke_find_thread_points_by_tid (tid, 1); | |
1597 | gdb_assert (t != NULL); | |
1598 | hw_breaks = t->hw_breaks; | |
1599 | ||
1600 | /* Find a free element in the hw_breaks vector. */ | |
1601 | for (i = 0; i < max_slots_number; i++) | |
1602 | if (hw_breaks[i].hw_break == NULL) | |
1603 | { | |
1604 | hw_breaks[i].slot = slot; | |
1605 | hw_breaks[i].hw_break = p; | |
1606 | break; | |
1607 | } | |
1608 | ||
1609 | gdb_assert (i != max_slots_number); | |
1610 | ||
1611 | discard_cleanups (c); | |
1612 | } | |
1613 | ||
1614 | /* This function is a generic wrapper that is responsible for removing a | |
1615 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1616 | kernel), and unregistering it internally at GDB. */ | |
1617 | static void | |
1618 | booke_remove_point (struct ppc_hw_breakpoint *b, int tid) | |
1619 | { | |
1620 | int i; | |
1621 | struct hw_break_tuple *hw_breaks; | |
1622 | struct thread_points *t; | |
1623 | ||
1624 | t = booke_find_thread_points_by_tid (tid, 0); | |
1625 | gdb_assert (t != NULL); | |
1626 | hw_breaks = t->hw_breaks; | |
1627 | ||
1628 | for (i = 0; i < max_slots_number; i++) | |
1629 | if (hw_breaks[i].hw_break && booke_cmp_hw_point (hw_breaks[i].hw_break, b)) | |
1630 | break; | |
1631 | ||
1632 | gdb_assert (i != max_slots_number); | |
1633 | ||
1634 | /* We have to ignore ENOENT errors because the kernel implements hardware | |
1635 | breakpoints/watchpoints as "one-shot", that is, they are automatically | |
1636 | deleted when hit. */ | |
1637 | errno = 0; | |
1638 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) | |
1639 | if (errno != ENOENT) | |
0df8b418 MS |
1640 | perror_with_name (_("Unexpected error deleting " |
1641 | "breakpoint or watchpoint")); | |
6ffbb7ab TJB |
1642 | |
1643 | xfree (hw_breaks[i].hw_break); | |
1644 | hw_breaks[i].hw_break = NULL; | |
1645 | } | |
9f0bdab8 | 1646 | |
f1310107 TJB |
1647 | /* Return the number of registers needed for a ranged breakpoint. */ |
1648 | ||
1649 | static int | |
1650 | ppc_linux_ranged_break_num_registers (struct target_ops *target) | |
1651 | { | |
1652 | return ((have_ptrace_booke_interface () | |
1653 | && booke_debug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? | |
1654 | 2 : -1); | |
1655 | } | |
1656 | ||
1657 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for | |
1658 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ | |
1659 | ||
2c387241 | 1660 | static int |
6ffbb7ab TJB |
1661 | ppc_linux_insert_hw_breakpoint (struct gdbarch *gdbarch, |
1662 | struct bp_target_info *bp_tgt) | |
e0d24f8d | 1663 | { |
9f0bdab8 | 1664 | struct lwp_info *lp; |
6ffbb7ab TJB |
1665 | struct ppc_hw_breakpoint p; |
1666 | ||
1667 | if (!have_ptrace_booke_interface ()) | |
1668 | return -1; | |
1669 | ||
ad422571 TJB |
1670 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1671 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1672 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1673 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1674 | p.condition_value = 0; |
1675 | ||
f1310107 TJB |
1676 | if (bp_tgt->length) |
1677 | { | |
1678 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1679 | ||
1680 | /* The breakpoint will trigger if the address of the instruction is | |
1681 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
1682 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1683 | } | |
1684 | else | |
1685 | { | |
1686 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1687 | p.addr2 = 0; | |
1688 | } | |
1689 | ||
4c38200f PA |
1690 | ALL_LWPS (lp) |
1691 | booke_insert_point (&p, TIDGET (lp->ptid)); | |
6ffbb7ab TJB |
1692 | |
1693 | return 0; | |
1694 | } | |
1695 | ||
1696 | static int | |
1697 | ppc_linux_remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1698 | struct bp_target_info *bp_tgt) | |
1699 | { | |
6ffbb7ab TJB |
1700 | struct lwp_info *lp; |
1701 | struct ppc_hw_breakpoint p; | |
b7622095 | 1702 | |
6ffbb7ab TJB |
1703 | if (!have_ptrace_booke_interface ()) |
1704 | return -1; | |
1705 | ||
ad422571 TJB |
1706 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1707 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1708 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1709 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1710 | p.condition_value = 0; |
1711 | ||
f1310107 TJB |
1712 | if (bp_tgt->length) |
1713 | { | |
1714 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1715 | ||
1716 | /* The breakpoint will trigger if the address of the instruction is within | |
1717 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
1718 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1719 | } | |
1720 | else | |
1721 | { | |
1722 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1723 | p.addr2 = 0; | |
1724 | } | |
1725 | ||
4c38200f PA |
1726 | ALL_LWPS (lp) |
1727 | booke_remove_point (&p, TIDGET (lp->ptid)); | |
6ffbb7ab TJB |
1728 | |
1729 | return 0; | |
1730 | } | |
1731 | ||
1732 | static int | |
1733 | get_trigger_type (int rw) | |
1734 | { | |
1735 | int t; | |
1736 | ||
1737 | if (rw == hw_read) | |
1738 | t = PPC_BREAKPOINT_TRIGGER_READ; | |
1739 | else if (rw == hw_write) | |
1740 | t = PPC_BREAKPOINT_TRIGGER_WRITE; | |
b7622095 | 1741 | else |
6ffbb7ab TJB |
1742 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
1743 | ||
1744 | return t; | |
1745 | } | |
1746 | ||
9c06b0b4 TJB |
1747 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
1748 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1749 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1750 | an error on failure. */ | |
1751 | ||
1752 | static int | |
1753 | ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, | |
1754 | CORE_ADDR mask, int rw) | |
1755 | { | |
9c06b0b4 TJB |
1756 | struct lwp_info *lp; |
1757 | struct ppc_hw_breakpoint p; | |
1758 | ||
1759 | gdb_assert (have_ptrace_booke_interface ()); | |
1760 | ||
1761 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1762 | p.trigger_type = get_trigger_type (rw); | |
1763 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1764 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1765 | p.addr = addr; | |
1766 | p.addr2 = mask; | |
1767 | p.condition_value = 0; | |
1768 | ||
4c38200f PA |
1769 | ALL_LWPS (lp) |
1770 | booke_insert_point (&p, TIDGET (lp->ptid)); | |
9c06b0b4 TJB |
1771 | |
1772 | return 0; | |
1773 | } | |
1774 | ||
1775 | /* Remove a masked watchpoint at ADDR with the mask MASK. | |
1776 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1777 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1778 | an error on failure. */ | |
1779 | ||
1780 | static int | |
1781 | ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, | |
1782 | CORE_ADDR mask, int rw) | |
1783 | { | |
9c06b0b4 TJB |
1784 | struct lwp_info *lp; |
1785 | struct ppc_hw_breakpoint p; | |
1786 | ||
1787 | gdb_assert (have_ptrace_booke_interface ()); | |
1788 | ||
1789 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1790 | p.trigger_type = get_trigger_type (rw); | |
1791 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1792 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1793 | p.addr = addr; | |
1794 | p.addr2 = mask; | |
1795 | p.condition_value = 0; | |
1796 | ||
4c38200f PA |
1797 | ALL_LWPS (lp) |
1798 | booke_remove_point (&p, TIDGET (lp->ptid)); | |
9c06b0b4 TJB |
1799 | |
1800 | return 0; | |
1801 | } | |
1802 | ||
0cf6dd15 TJB |
1803 | /* Check whether we have at least one free DVC register. */ |
1804 | static int | |
1805 | can_use_watchpoint_cond_accel (void) | |
1806 | { | |
1807 | struct thread_points *p; | |
1808 | int tid = TIDGET (inferior_ptid); | |
1809 | int cnt = booke_debug_info.num_condition_regs, i; | |
1810 | CORE_ADDR tmp_value; | |
1811 | ||
1812 | if (!have_ptrace_booke_interface () || cnt == 0) | |
1813 | return 0; | |
1814 | ||
1815 | p = booke_find_thread_points_by_tid (tid, 0); | |
1816 | ||
1817 | if (p) | |
1818 | { | |
1819 | for (i = 0; i < max_slots_number; i++) | |
1820 | if (p->hw_breaks[i].hw_break != NULL | |
1821 | && (p->hw_breaks[i].hw_break->condition_mode | |
1822 | != PPC_BREAKPOINT_CONDITION_NONE)) | |
1823 | cnt--; | |
1824 | ||
1825 | /* There are no available slots now. */ | |
1826 | if (cnt <= 0) | |
1827 | return 0; | |
1828 | } | |
1829 | ||
1830 | return 1; | |
1831 | } | |
1832 | ||
1833 | /* Calculate the enable bits and the contents of the Data Value Compare | |
1834 | debug register present in BookE processors. | |
1835 | ||
1836 | ADDR is the address to be watched, LEN is the length of watched data | |
1837 | and DATA_VALUE is the value which will trigger the watchpoint. | |
1838 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
1839 | CONDITION_VALUE will hold the value which should be put in the | |
1840 | DVC register. */ | |
1841 | static void | |
1842 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, | |
1843 | uint32_t *condition_mode, uint64_t *condition_value) | |
1844 | { | |
1845 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, | |
1846 | rightmost_enabled_byte; | |
1847 | CORE_ADDR addr_end_data, addr_end_dvc; | |
1848 | ||
1849 | /* The DVC register compares bytes within fixed-length windows which | |
1850 | are word-aligned, with length equal to that of the DVC register. | |
1851 | We need to calculate where our watch region is relative to that | |
1852 | window and enable comparison of the bytes which fall within it. */ | |
1853 | ||
1854 | align_offset = addr % booke_debug_info.sizeof_condition; | |
1855 | addr_end_data = addr + len; | |
1856 | addr_end_dvc = (addr - align_offset | |
1857 | + booke_debug_info.sizeof_condition); | |
1858 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? | |
1859 | addr_end_data - addr_end_dvc : 0; | |
1860 | num_byte_enable = len - num_bytes_off_dvc; | |
1861 | /* Here, bytes are numbered from right to left. */ | |
1862 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
1863 | addr_end_dvc - addr_end_data : 0; | |
1864 | ||
1865 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
1866 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
1867 | *condition_mode |
1868 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
1869 | |
1870 | /* Now we need to match the position within the DVC of the comparison | |
1871 | value with where the watch region is relative to the window | |
1872 | (i.e., the ALIGN_OFFSET). */ | |
1873 | ||
1874 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
1875 | << rightmost_enabled_byte * 8); | |
1876 | } | |
1877 | ||
1878 | /* Return the number of memory locations that need to be accessed to | |
1879 | evaluate the expression which generated the given value chain. | |
1880 | Returns -1 if there's any register access involved, or if there are | |
1881 | other kinds of values which are not acceptable in a condition | |
1882 | expression (e.g., lval_computed or lval_internalvar). */ | |
1883 | static int | |
1884 | num_memory_accesses (struct value *v) | |
1885 | { | |
1886 | int found_memory_cnt = 0; | |
1887 | struct value *head = v; | |
1888 | ||
1889 | /* The idea here is that evaluating an expression generates a series | |
1890 | of values, one holding the value of every subexpression. (The | |
1891 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
1892 | a*b+c.) GDB's values hold almost enough information to establish | |
1893 | the criteria given above --- they identify memory lvalues, | |
1894 | register lvalues, computed values, etcetera. So we can evaluate | |
1895 | the expression, and then scan the chain of values that leaves | |
1896 | behind to determine the memory locations involved in the evaluation | |
1897 | of an expression. | |
1898 | ||
1899 | However, I don't think that the values returned by inferior | |
1900 | function calls are special in any way. So this function may not | |
1901 | notice that an expression contains an inferior function call. | |
1902 | FIXME. */ | |
1903 | ||
1904 | for (; v; v = value_next (v)) | |
1905 | { | |
1906 | /* Constants and values from the history are fine. */ | |
1907 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) | |
1908 | continue; | |
1909 | else if (VALUE_LVAL (v) == lval_memory) | |
1910 | { | |
1911 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
1912 | we either just used its address (e.g., `a' in `a.b') or | |
1913 | we never needed it at all (e.g., `a' in `a,b'). */ | |
1914 | if (!value_lazy (v)) | |
1915 | found_memory_cnt++; | |
1916 | } | |
0df8b418 | 1917 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
1918 | else |
1919 | return -1; | |
1920 | } | |
1921 | ||
1922 | return found_memory_cnt; | |
1923 | } | |
1924 | ||
1925 | /* Verifies whether the expression COND can be implemented using the | |
1926 | DVC (Data Value Compare) register in BookE processors. The expression | |
1927 | must test the watch value for equality with a constant expression. | |
1928 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
1929 | which the watch value should be compared and LEN will contain the size |
1930 | of the constant. */ | |
0cf6dd15 TJB |
1931 | static int |
1932 | check_condition (CORE_ADDR watch_addr, struct expression *cond, | |
e7db58ea | 1933 | CORE_ADDR *data_value, int *len) |
0cf6dd15 TJB |
1934 | { |
1935 | int pc = 1, num_accesses_left, num_accesses_right; | |
1936 | struct value *left_val, *right_val, *left_chain, *right_chain; | |
1937 | ||
1938 | if (cond->elts[0].opcode != BINOP_EQUAL) | |
1939 | return 0; | |
1940 | ||
1941 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain); | |
1942 | num_accesses_left = num_memory_accesses (left_chain); | |
1943 | ||
1944 | if (left_val == NULL || num_accesses_left < 0) | |
1945 | { | |
1946 | free_value_chain (left_chain); | |
1947 | ||
1948 | return 0; | |
1949 | } | |
1950 | ||
1951 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain); | |
1952 | num_accesses_right = num_memory_accesses (right_chain); | |
1953 | ||
1954 | if (right_val == NULL || num_accesses_right < 0) | |
1955 | { | |
1956 | free_value_chain (left_chain); | |
1957 | free_value_chain (right_chain); | |
1958 | ||
1959 | return 0; | |
1960 | } | |
1961 | ||
1962 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
1963 | && VALUE_LVAL (left_val) == lval_memory | |
1964 | && value_address (left_val) == watch_addr) | |
e7db58ea TJB |
1965 | { |
1966 | *data_value = value_as_long (right_val); | |
1967 | ||
1968 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
1969 | the same type as the memory region referenced by LEFT_VAL. */ | |
1970 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); | |
1971 | } | |
0cf6dd15 TJB |
1972 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
1973 | && VALUE_LVAL (right_val) == lval_memory | |
1974 | && value_address (right_val) == watch_addr) | |
e7db58ea TJB |
1975 | { |
1976 | *data_value = value_as_long (left_val); | |
1977 | ||
1978 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
1979 | the same type as the memory region referenced by RIGHT_VAL. */ | |
1980 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); | |
1981 | } | |
0cf6dd15 TJB |
1982 | else |
1983 | { | |
1984 | free_value_chain (left_chain); | |
1985 | free_value_chain (right_chain); | |
1986 | ||
1987 | return 0; | |
1988 | } | |
1989 | ||
1990 | free_value_chain (left_chain); | |
1991 | free_value_chain (right_chain); | |
1992 | ||
1993 | return 1; | |
1994 | } | |
1995 | ||
1996 | /* Return non-zero if the target is capable of using hardware to evaluate | |
1997 | the condition expression, thus only triggering the watchpoint when it is | |
1998 | true. */ | |
1999 | static int | |
2000 | ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr, int len, int rw, | |
2001 | struct expression *cond) | |
2002 | { | |
2003 | CORE_ADDR data_value; | |
2004 | ||
2005 | return (have_ptrace_booke_interface () | |
2006 | && booke_debug_info.num_condition_regs > 0 | |
e7db58ea | 2007 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
2008 | } |
2009 | ||
e09342b5 TJB |
2010 | /* Set up P with the parameters necessary to request a watchpoint covering |
2011 | LEN bytes starting at ADDR and if possible with condition expression COND | |
2012 | evaluated by hardware. INSERT tells if we are creating a request for | |
2013 | inserting or removing the watchpoint. */ | |
2014 | ||
2015 | static void | |
2016 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, | |
2017 | int len, int rw, struct expression *cond, | |
2018 | int insert) | |
2019 | { | |
f16c4e8b AS |
2020 | if (len == 1 |
2021 | || !(booke_debug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) | |
e09342b5 TJB |
2022 | { |
2023 | int use_condition; | |
2024 | CORE_ADDR data_value; | |
2025 | ||
2026 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
2027 | : booke_debug_info.num_condition_regs > 0); | |
e7db58ea TJB |
2028 | if (cond && use_condition && check_condition (addr, cond, |
2029 | &data_value, &len)) | |
e09342b5 TJB |
2030 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
2031 | &p->condition_value); | |
2032 | else | |
2033 | { | |
2034 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2035 | p->condition_value = 0; | |
2036 | } | |
2037 | ||
2038 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2039 | p->addr2 = 0; | |
2040 | } | |
2041 | else | |
2042 | { | |
2043 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2044 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2045 | p->condition_value = 0; | |
2046 | ||
2047 | /* The watchpoint will trigger if the address of the memory access is | |
2048 | within the defined range, as follows: p->addr <= address < p->addr2. | |
2049 | ||
2050 | Note that the above sentence just documents how ptrace interprets | |
2051 | its arguments; the watchpoint is set to watch the range defined by | |
2052 | the user _inclusively_, as specified by the user interface. */ | |
2053 | p->addr2 = (uint64_t) addr + len; | |
2054 | } | |
2055 | ||
2056 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
2057 | p->trigger_type = get_trigger_type (rw); | |
2058 | p->addr = (uint64_t) addr; | |
2059 | } | |
2060 | ||
6ffbb7ab | 2061 | static int |
0cf6dd15 TJB |
2062 | ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw, |
2063 | struct expression *cond) | |
6ffbb7ab TJB |
2064 | { |
2065 | struct lwp_info *lp; | |
6ffbb7ab TJB |
2066 | int ret = -1; |
2067 | ||
2068 | if (have_ptrace_booke_interface ()) | |
e0d24f8d | 2069 | { |
6ffbb7ab TJB |
2070 | struct ppc_hw_breakpoint p; |
2071 | ||
e09342b5 | 2072 | create_watchpoint_request (&p, addr, len, rw, cond, 1); |
6ffbb7ab | 2073 | |
4c38200f PA |
2074 | ALL_LWPS (lp) |
2075 | booke_insert_point (&p, TIDGET (lp->ptid)); | |
6ffbb7ab TJB |
2076 | |
2077 | ret = 0; | |
e0d24f8d | 2078 | } |
6ffbb7ab TJB |
2079 | else |
2080 | { | |
2081 | long dabr_value; | |
2082 | long read_mode, write_mode; | |
e0d24f8d | 2083 | |
6ffbb7ab TJB |
2084 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2085 | { | |
2086 | /* PowerPC 440 requires only the read/write flags to be passed | |
2087 | to the kernel. */ | |
ad422571 | 2088 | read_mode = 1; |
6ffbb7ab TJB |
2089 | write_mode = 2; |
2090 | } | |
2091 | else | |
2092 | { | |
2093 | /* PowerPC 970 and other DABR-based processors are required to pass | |
2094 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 2095 | read_mode = 5; |
6ffbb7ab TJB |
2096 | write_mode = 6; |
2097 | } | |
1c86e440 | 2098 | |
6ffbb7ab TJB |
2099 | dabr_value = addr & ~(read_mode | write_mode); |
2100 | switch (rw) | |
2101 | { | |
2102 | case hw_read: | |
2103 | /* Set read and translate bits. */ | |
2104 | dabr_value |= read_mode; | |
2105 | break; | |
2106 | case hw_write: | |
2107 | /* Set write and translate bits. */ | |
2108 | dabr_value |= write_mode; | |
2109 | break; | |
2110 | case hw_access: | |
2111 | /* Set read, write and translate bits. */ | |
2112 | dabr_value |= read_mode | write_mode; | |
2113 | break; | |
2114 | } | |
1c86e440 | 2115 | |
6ffbb7ab TJB |
2116 | saved_dabr_value = dabr_value; |
2117 | ||
4c38200f PA |
2118 | ALL_LWPS (lp) |
2119 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (lp->ptid), 0, | |
0cf6dd15 | 2120 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2121 | return -1; |
2122 | ||
2123 | ret = 0; | |
2124 | } | |
2125 | ||
2126 | return ret; | |
e0d24f8d WZ |
2127 | } |
2128 | ||
2c387241 | 2129 | static int |
0cf6dd15 TJB |
2130 | ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw, |
2131 | struct expression *cond) | |
e0d24f8d | 2132 | { |
9f0bdab8 | 2133 | struct lwp_info *lp; |
6ffbb7ab | 2134 | int ret = -1; |
9f0bdab8 | 2135 | |
6ffbb7ab TJB |
2136 | if (have_ptrace_booke_interface ()) |
2137 | { | |
2138 | struct ppc_hw_breakpoint p; | |
2139 | ||
e09342b5 | 2140 | create_watchpoint_request (&p, addr, len, rw, cond, 0); |
6ffbb7ab | 2141 | |
4c38200f PA |
2142 | ALL_LWPS (lp) |
2143 | booke_remove_point (&p, TIDGET (lp->ptid)); | |
6ffbb7ab TJB |
2144 | |
2145 | ret = 0; | |
2146 | } | |
2147 | else | |
2148 | { | |
2149 | saved_dabr_value = 0; | |
4c38200f PA |
2150 | ALL_LWPS (lp) |
2151 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (lp->ptid), 0, | |
0cf6dd15 | 2152 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2153 | return -1; |
2154 | ||
2155 | ret = 0; | |
2156 | } | |
2157 | ||
2158 | return ret; | |
e0d24f8d WZ |
2159 | } |
2160 | ||
9f0bdab8 | 2161 | static void |
7b50312a | 2162 | ppc_linux_new_thread (struct lwp_info *lp) |
e0d24f8d | 2163 | { |
7b50312a | 2164 | int tid = TIDGET (lp->ptid); |
6ffbb7ab TJB |
2165 | |
2166 | if (have_ptrace_booke_interface ()) | |
2167 | { | |
2168 | int i; | |
2169 | struct thread_points *p; | |
2170 | struct hw_break_tuple *hw_breaks; | |
2171 | ||
2172 | if (VEC_empty (thread_points_p, ppc_threads)) | |
2173 | return; | |
2174 | ||
0df8b418 | 2175 | /* Get a list of breakpoints from any thread. */ |
6ffbb7ab TJB |
2176 | p = VEC_last (thread_points_p, ppc_threads); |
2177 | hw_breaks = p->hw_breaks; | |
2178 | ||
0df8b418 | 2179 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
6ffbb7ab TJB |
2180 | for (i = 0; i < max_slots_number; i++) |
2181 | if (hw_breaks[i].hw_break) | |
2182 | booke_insert_point (hw_breaks[i].hw_break, tid); | |
2183 | } | |
2184 | else | |
2185 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); | |
2186 | } | |
2187 | ||
2188 | static void | |
2189 | ppc_linux_thread_exit (struct thread_info *tp, int silent) | |
2190 | { | |
2191 | int i; | |
2192 | int tid = TIDGET (tp->ptid); | |
2193 | struct hw_break_tuple *hw_breaks; | |
2194 | struct thread_points *t = NULL, *p; | |
2195 | ||
2196 | if (!have_ptrace_booke_interface ()) | |
2197 | return; | |
2198 | ||
2199 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) | |
2200 | if (p->tid == tid) | |
2201 | { | |
2202 | t = p; | |
2203 | break; | |
2204 | } | |
2205 | ||
2206 | if (t == NULL) | |
2207 | return; | |
2208 | ||
2209 | VEC_unordered_remove (thread_points_p, ppc_threads, i); | |
2210 | ||
2211 | hw_breaks = t->hw_breaks; | |
2212 | ||
2213 | for (i = 0; i < max_slots_number; i++) | |
2214 | if (hw_breaks[i].hw_break) | |
2215 | xfree (hw_breaks[i].hw_break); | |
2216 | ||
2217 | xfree (t->hw_breaks); | |
2218 | xfree (t); | |
e0d24f8d WZ |
2219 | } |
2220 | ||
2221 | static int | |
9f0bdab8 | 2222 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) |
e0d24f8d | 2223 | { |
f865ee35 | 2224 | siginfo_t siginfo; |
e0d24f8d | 2225 | |
f865ee35 JK |
2226 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
2227 | return 0; | |
e0d24f8d | 2228 | |
f865ee35 JK |
2229 | if (siginfo.si_signo != SIGTRAP |
2230 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e0d24f8d WZ |
2231 | return 0; |
2232 | ||
6ffbb7ab TJB |
2233 | if (have_ptrace_booke_interface ()) |
2234 | { | |
2235 | int i; | |
2236 | struct thread_points *t; | |
2237 | struct hw_break_tuple *hw_breaks; | |
2238 | /* The index (or slot) of the *point is passed in the si_errno field. */ | |
f865ee35 | 2239 | int slot = siginfo.si_errno; |
6ffbb7ab TJB |
2240 | |
2241 | t = booke_find_thread_points_by_tid (TIDGET (inferior_ptid), 0); | |
2242 | ||
2243 | /* Find out if this *point is a hardware breakpoint. | |
2244 | If so, we should return 0. */ | |
2245 | if (t) | |
2246 | { | |
2247 | hw_breaks = t->hw_breaks; | |
2248 | for (i = 0; i < max_slots_number; i++) | |
2249 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot | |
2250 | && hw_breaks[i].hw_break->trigger_type | |
2251 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) | |
2252 | return 0; | |
2253 | } | |
2254 | } | |
2255 | ||
f865ee35 | 2256 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e0d24f8d WZ |
2257 | return 1; |
2258 | } | |
2259 | ||
9f0bdab8 DJ |
2260 | static int |
2261 | ppc_linux_stopped_by_watchpoint (void) | |
2262 | { | |
2263 | CORE_ADDR addr; | |
2264 | return ppc_linux_stopped_data_address (¤t_target, &addr); | |
2265 | } | |
2266 | ||
5009afc5 AS |
2267 | static int |
2268 | ppc_linux_watchpoint_addr_within_range (struct target_ops *target, | |
2269 | CORE_ADDR addr, | |
2270 | CORE_ADDR start, int length) | |
2271 | { | |
b7622095 LM |
2272 | int mask; |
2273 | ||
6ffbb7ab TJB |
2274 | if (have_ptrace_booke_interface () |
2275 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
2276 | return start <= addr && start + length >= addr; | |
2277 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
b7622095 LM |
2278 | mask = 3; |
2279 | else | |
2280 | mask = 7; | |
2281 | ||
2282 | addr &= ~mask; | |
2283 | ||
0df8b418 | 2284 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 2285 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
2286 | } |
2287 | ||
9c06b0b4 TJB |
2288 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
2289 | ||
2290 | static int | |
2291 | ppc_linux_masked_watch_num_registers (struct target_ops *target, | |
2292 | CORE_ADDR addr, CORE_ADDR mask) | |
2293 | { | |
2294 | if (!have_ptrace_booke_interface () | |
2295 | || (booke_debug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
2296 | return -1; | |
2297 | else if ((mask & 0xC0000000) != 0xC0000000) | |
2298 | { | |
2299 | warning (_("The given mask covers kernel address space " | |
2300 | "and cannot be used.\n")); | |
2301 | ||
2302 | return -2; | |
2303 | } | |
2304 | else | |
2305 | return 2; | |
2306 | } | |
2307 | ||
10d6c8cd | 2308 | static void |
28439f5e PA |
2309 | ppc_linux_store_inferior_registers (struct target_ops *ops, |
2310 | struct regcache *regcache, int regno) | |
45229ea4 | 2311 | { |
0df8b418 | 2312 | /* Overload thread id onto process id. */ |
05f13b9c EZ |
2313 | int tid = TIDGET (inferior_ptid); |
2314 | ||
0df8b418 | 2315 | /* No thread id, just use process id. */ |
05f13b9c EZ |
2316 | if (tid == 0) |
2317 | tid = PIDGET (inferior_ptid); | |
2318 | ||
45229ea4 | 2319 | if (regno >= 0) |
56be3814 | 2320 | store_register (regcache, tid, regno); |
45229ea4 | 2321 | else |
56be3814 | 2322 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
2323 | } |
2324 | ||
f2db237a AM |
2325 | /* Functions for transferring registers between a gregset_t or fpregset_t |
2326 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
0df8b418 | 2327 | by the ptrace interface, not the current program's ABI. Eg. if a |
f2db237a AM |
2328 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
2329 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
2330 | ||
50c9bd31 | 2331 | void |
7f7fe91e | 2332 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 2333 | { |
f2db237a | 2334 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2335 | |
f2db237a | 2336 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
2337 | } |
2338 | ||
fdb28ac4 | 2339 | void |
7f7fe91e UW |
2340 | fill_gregset (const struct regcache *regcache, |
2341 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 2342 | { |
f2db237a | 2343 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2344 | |
f2db237a AM |
2345 | if (regno == -1) |
2346 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
2347 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
2348 | } |
2349 | ||
50c9bd31 | 2350 | void |
7f7fe91e | 2351 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 2352 | { |
f2db237a AM |
2353 | const struct regset *regset = ppc_linux_fpregset (); |
2354 | ||
2355 | ppc_supply_fpregset (regset, regcache, -1, | |
2356 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 2357 | } |
fdb28ac4 | 2358 | |
fdb28ac4 | 2359 | void |
7f7fe91e UW |
2360 | fill_fpregset (const struct regcache *regcache, |
2361 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 2362 | { |
f2db237a AM |
2363 | const struct regset *regset = ppc_linux_fpregset (); |
2364 | ||
2365 | ppc_collect_fpregset (regset, regcache, regno, | |
2366 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 2367 | } |
10d6c8cd | 2368 | |
409c383c UW |
2369 | static int |
2370 | ppc_linux_target_wordsize (void) | |
2371 | { | |
2372 | int wordsize = 4; | |
2373 | ||
2374 | /* Check for 64-bit inferior process. This is the case when the host is | |
2375 | 64-bit, and in addition the top bit of the MSR register is set. */ | |
2376 | #ifdef __powerpc64__ | |
2377 | long msr; | |
2378 | ||
2379 | int tid = TIDGET (inferior_ptid); | |
2380 | if (tid == 0) | |
2381 | tid = PIDGET (inferior_ptid); | |
2382 | ||
2383 | errno = 0; | |
2384 | msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); | |
2385 | if (errno == 0 && msr < 0) | |
2386 | wordsize = 8; | |
2387 | #endif | |
2388 | ||
2389 | return wordsize; | |
2390 | } | |
2391 | ||
2392 | static int | |
2393 | ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr, | |
2394 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
2395 | { | |
2396 | int sizeof_auxv_field = ppc_linux_target_wordsize (); | |
e17a4113 | 2397 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch); |
409c383c UW |
2398 | gdb_byte *ptr = *readptr; |
2399 | ||
2400 | if (endptr == ptr) | |
2401 | return 0; | |
2402 | ||
2403 | if (endptr - ptr < sizeof_auxv_field * 2) | |
2404 | return -1; | |
2405 | ||
e17a4113 | 2406 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c | 2407 | ptr += sizeof_auxv_field; |
e17a4113 | 2408 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c UW |
2409 | ptr += sizeof_auxv_field; |
2410 | ||
2411 | *readptr = ptr; | |
2412 | return 1; | |
2413 | } | |
2414 | ||
310a98e1 DJ |
2415 | static const struct target_desc * |
2416 | ppc_linux_read_description (struct target_ops *ops) | |
2417 | { | |
7284e1be | 2418 | int altivec = 0; |
604c2f83 | 2419 | int vsx = 0; |
69abc51c | 2420 | int isa205 = 0; |
f4d9bade | 2421 | int cell = 0; |
7284e1be UW |
2422 | |
2423 | int tid = TIDGET (inferior_ptid); | |
2424 | if (tid == 0) | |
2425 | tid = PIDGET (inferior_ptid); | |
2426 | ||
310a98e1 DJ |
2427 | if (have_ptrace_getsetevrregs) |
2428 | { | |
2429 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
2430 | |
2431 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
2432 | return tdesc_powerpc_e500l; |
2433 | ||
2434 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
2435 | Anything else needs to be reported. */ | |
2436 | else if (errno != EIO) | |
2437 | perror_with_name (_("Unable to fetch SPE registers")); | |
2438 | } | |
2439 | ||
604c2f83 LM |
2440 | if (have_ptrace_getsetvsxregs) |
2441 | { | |
2442 | gdb_vsxregset_t vsxregset; | |
2443 | ||
2444 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
2445 | vsx = 1; | |
2446 | ||
2447 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
2448 | Anything else needs to be reported. */ | |
2449 | else if (errno != EIO) | |
2450 | perror_with_name (_("Unable to fetch VSX registers")); | |
2451 | } | |
2452 | ||
7284e1be UW |
2453 | if (have_ptrace_getvrregs) |
2454 | { | |
2455 | gdb_vrregset_t vrregset; | |
2456 | ||
2457 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
2458 | altivec = 1; | |
2459 | ||
2460 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
2461 | Anything else needs to be reported. */ | |
2462 | else if (errno != EIO) | |
2463 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
2464 | } |
2465 | ||
f04c6d38 | 2466 | /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases |
0df8b418 | 2467 | the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this |
f04c6d38 TJB |
2468 | ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only |
2469 | PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher | |
2470 | half of the register are for Decimal Floating Point, we check if that | |
2471 | feature is available to decide the size of the FPSCR. */ | |
2472 | if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP) | |
69abc51c TJB |
2473 | isa205 = 1; |
2474 | ||
f4d9bade UW |
2475 | if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL) |
2476 | cell = 1; | |
2477 | ||
409c383c UW |
2478 | if (ppc_linux_target_wordsize () == 8) |
2479 | { | |
f4d9bade UW |
2480 | if (cell) |
2481 | return tdesc_powerpc_cell64l; | |
2482 | else if (vsx) | |
409c383c UW |
2483 | return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; |
2484 | else if (altivec) | |
0df8b418 MS |
2485 | return isa205 |
2486 | ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; | |
409c383c UW |
2487 | |
2488 | return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; | |
2489 | } | |
7284e1be | 2490 | |
f4d9bade UW |
2491 | if (cell) |
2492 | return tdesc_powerpc_cell32l; | |
2493 | else if (vsx) | |
69abc51c | 2494 | return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; |
604c2f83 | 2495 | else if (altivec) |
69abc51c | 2496 | return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; |
604c2f83 | 2497 | |
69abc51c | 2498 | return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; |
310a98e1 DJ |
2499 | } |
2500 | ||
10d6c8cd DJ |
2501 | void _initialize_ppc_linux_nat (void); |
2502 | ||
2503 | void | |
2504 | _initialize_ppc_linux_nat (void) | |
2505 | { | |
2506 | struct target_ops *t; | |
2507 | ||
2508 | /* Fill in the generic GNU/Linux methods. */ | |
2509 | t = linux_target (); | |
2510 | ||
2511 | /* Add our register access methods. */ | |
2512 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; | |
2513 | t->to_store_registers = ppc_linux_store_inferior_registers; | |
2514 | ||
6ffbb7ab TJB |
2515 | /* Add our breakpoint/watchpoint methods. */ |
2516 | t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint; | |
2517 | t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint; | |
2518 | t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint; | |
e0d24f8d WZ |
2519 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; |
2520 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; | |
2521 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; | |
9c06b0b4 TJB |
2522 | t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint; |
2523 | t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint; | |
e0d24f8d WZ |
2524 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; |
2525 | t->to_stopped_data_address = ppc_linux_stopped_data_address; | |
5009afc5 | 2526 | t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; |
0df8b418 MS |
2527 | t->to_can_accel_watchpoint_condition |
2528 | = ppc_linux_can_accel_watchpoint_condition; | |
9c06b0b4 | 2529 | t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers; |
f1310107 | 2530 | t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers; |
e0d24f8d | 2531 | |
310a98e1 | 2532 | t->to_read_description = ppc_linux_read_description; |
409c383c | 2533 | t->to_auxv_parse = ppc_linux_auxv_parse; |
310a98e1 | 2534 | |
6ffbb7ab TJB |
2535 | observer_attach_thread_exit (ppc_linux_thread_exit); |
2536 | ||
10d6c8cd | 2537 | /* Register the target. */ |
f973ed9c | 2538 | linux_nat_add_target (t); |
9f0bdab8 | 2539 | linux_nat_set_new_thread (t, ppc_linux_new_thread); |
10d6c8cd | 2540 | } |