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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003, |
0fb0cc75 | 4 | 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. |
c877c8e6 KB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
20 | |
21 | #include "defs.h" | |
e162d11b | 22 | #include "gdb_string.h" |
c877c8e6 KB |
23 | #include "frame.h" |
24 | #include "inferior.h" | |
25 | #include "gdbcore.h" | |
4e052eda | 26 | #include "regcache.h" |
383f0f5b | 27 | #include "gdb_assert.h" |
10d6c8cd DJ |
28 | #include "target.h" |
29 | #include "linux-nat.h" | |
c877c8e6 | 30 | |
411cb3f9 | 31 | #include <stdint.h> |
c877c8e6 KB |
32 | #include <sys/types.h> |
33 | #include <sys/param.h> | |
34 | #include <signal.h> | |
35 | #include <sys/user.h> | |
36 | #include <sys/ioctl.h> | |
2555fe1a | 37 | #include "gdb_wait.h" |
c877c8e6 KB |
38 | #include <fcntl.h> |
39 | #include <sys/procfs.h> | |
45229ea4 | 40 | #include <sys/ptrace.h> |
c877c8e6 | 41 | |
c60c0f5f MS |
42 | /* Prototypes for supply_gregset etc. */ |
43 | #include "gregset.h" | |
16333c4f | 44 | #include "ppc-tdep.h" |
7284e1be UW |
45 | #include "ppc-linux-tdep.h" |
46 | ||
b7622095 LM |
47 | /* Required when using the AUXV. */ |
48 | #include "elf/common.h" | |
49 | #include "auxv.h" | |
50 | ||
7284e1be UW |
51 | /* This sometimes isn't defined. */ |
52 | #ifndef PT_ORIG_R3 | |
53 | #define PT_ORIG_R3 34 | |
54 | #endif | |
55 | #ifndef PT_TRAP | |
56 | #define PT_TRAP 40 | |
57 | #endif | |
c60c0f5f | 58 | |
69abc51c TJB |
59 | /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>. |
60 | If they aren't, we can provide them ourselves (their values are fixed | |
61 | because they are part of the kernel ABI). They are used in the AT_HWCAP | |
62 | entry of the AUXV. */ | |
b7622095 LM |
63 | #ifndef PPC_FEATURE_BOOKE |
64 | #define PPC_FEATURE_BOOKE 0x00008000 | |
65 | #endif | |
f04c6d38 TJB |
66 | #ifndef PPC_FEATURE_HAS_DFP |
67 | #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */ | |
69abc51c | 68 | #endif |
b7622095 | 69 | |
9abe5450 EZ |
70 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
71 | configure time check. Some older glibc's (for instance 2.2.1) | |
72 | don't have a specific powerpc version of ptrace.h, and fall back on | |
73 | a generic one. In such cases, sys/ptrace.h defines | |
74 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
75 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
76 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
77 | much useless. */ | |
78 | ||
79 | /* These definitions should really come from the glibc header files, | |
80 | but Glibc doesn't know about the vrregs yet. */ | |
81 | #ifndef PTRACE_GETVRREGS | |
82 | #define PTRACE_GETVRREGS 18 | |
83 | #define PTRACE_SETVRREGS 19 | |
84 | #endif | |
85 | ||
604c2f83 LM |
86 | /* PTRACE requests for POWER7 VSX registers. */ |
87 | #ifndef PTRACE_GETVSXREGS | |
88 | #define PTRACE_GETVSXREGS 27 | |
89 | #define PTRACE_SETVSXREGS 28 | |
90 | #endif | |
01904826 JB |
91 | |
92 | /* Similarly for the ptrace requests for getting / setting the SPE | |
93 | registers (ev0 -- ev31, acc, and spefscr). See the description of | |
94 | gdb_evrregset_t for details. */ | |
95 | #ifndef PTRACE_GETEVRREGS | |
96 | #define PTRACE_GETEVRREGS 20 | |
97 | #define PTRACE_SETEVRREGS 21 | |
98 | #endif | |
99 | ||
e0d24f8d WZ |
100 | /* Similarly for the hardware watchpoint support. */ |
101 | #ifndef PTRACE_GET_DEBUGREG | |
102 | #define PTRACE_GET_DEBUGREG 25 | |
103 | #endif | |
104 | #ifndef PTRACE_SET_DEBUGREG | |
105 | #define PTRACE_SET_DEBUGREG 26 | |
106 | #endif | |
107 | #ifndef PTRACE_GETSIGINFO | |
108 | #define PTRACE_GETSIGINFO 0x4202 | |
109 | #endif | |
01904826 | 110 | |
1dfe79e8 SDJ |
111 | /* Similarly for the general-purpose (gp0 -- gp31) |
112 | and floating-point registers (fp0 -- fp31). */ | |
113 | #ifndef PTRACE_GETREGS | |
114 | #define PTRACE_GETREGS 12 | |
115 | #endif | |
116 | #ifndef PTRACE_SETREGS | |
117 | #define PTRACE_SETREGS 13 | |
118 | #endif | |
119 | #ifndef PTRACE_GETFPREGS | |
120 | #define PTRACE_GETFPREGS 14 | |
121 | #endif | |
122 | #ifndef PTRACE_SETFPREGS | |
123 | #define PTRACE_SETFPREGS 15 | |
124 | #endif | |
125 | ||
9abe5450 EZ |
126 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
127 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
128 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
129 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
130 | flat array of chars, so that it is easier to manipulate for gdb. | |
131 | ||
132 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
133 | which is only 4 bytes long, but is fetched as a 16 bytes | |
134 | quantity. Up to here we have the elf_vrregset_t structure. | |
135 | Appended to this there is space for the VRSAVE register: 4 bytes. | |
136 | Even though this vrsave register is not included in the regset | |
137 | typedef, it is handled by the ptrace requests. | |
138 | ||
139 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
140 | therefore the offset at which the real value of the VSCR register | |
141 | is located will be always 12 bytes. | |
142 | ||
143 | The layout is like this (where x is the actual value of the vscr reg): */ | |
144 | ||
145 | /* *INDENT-OFF* */ | |
146 | /* | |
147 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
148 | <-------> <-------><-------><-> | |
149 | VR0 VR31 VSCR VRSAVE | |
150 | */ | |
151 | /* *INDENT-ON* */ | |
152 | ||
153 | #define SIZEOF_VRREGS 33*16+4 | |
154 | ||
155 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
156 | ||
604c2f83 LM |
157 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
158 | with the existing FPR and VMX registers. | |
159 | ||
160 | VSR doubleword 0 VSR doubleword 1 | |
161 | ---------------------------------------------------------------- | |
162 | VSR[0] | FPR[0] | | | |
163 | ---------------------------------------------------------------- | |
164 | VSR[1] | FPR[1] | | | |
165 | ---------------------------------------------------------------- | |
166 | | ... | | | |
167 | | ... | | | |
168 | ---------------------------------------------------------------- | |
169 | VSR[30] | FPR[30] | | | |
170 | ---------------------------------------------------------------- | |
171 | VSR[31] | FPR[31] | | | |
172 | ---------------------------------------------------------------- | |
173 | VSR[32] | VR[0] | | |
174 | ---------------------------------------------------------------- | |
175 | VSR[33] | VR[1] | | |
176 | ---------------------------------------------------------------- | |
177 | | ... | | |
178 | | ... | | |
179 | ---------------------------------------------------------------- | |
180 | VSR[62] | VR[30] | | |
181 | ---------------------------------------------------------------- | |
182 | VSR[63] | VR[31] | | |
183 | ---------------------------------------------------------------- | |
184 | ||
185 | VSX has 64 128bit registers. The first 32 registers overlap with | |
186 | the FP registers (doubleword 0) and hence extend them with additional | |
187 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
188 | registers. */ | |
189 | #define SIZEOF_VSXREGS 32*8 | |
190 | ||
191 | typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; | |
01904826 JB |
192 | |
193 | /* On PPC processors that support the the Signal Processing Extension | |
194 | (SPE) APU, the general-purpose registers are 64 bits long. | |
411cb3f9 PG |
195 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
196 | ptrace calls only access the lower half of each register, to allow | |
197 | them to behave the same way they do on non-SPE systems. There's a | |
198 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
199 | read and write the top halves of all the general-purpose registers | |
200 | at once, along with some SPE-specific registers. | |
01904826 JB |
201 | |
202 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd JB |
203 | bits long. It has unnamed raw registers that hold the upper halves |
204 | of the gprs, and the the full 64-bit SIMD views of the registers, | |
205 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and | |
206 | bottom halves together. | |
01904826 JB |
207 | |
208 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
209 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
210 | struct gdb_evrregset_t | |
211 | { | |
212 | unsigned long evr[32]; | |
213 | unsigned long long acc; | |
214 | unsigned long spefscr; | |
215 | }; | |
216 | ||
604c2f83 LM |
217 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
218 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
219 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
220 | gotten an error. Note that VSX registers 32 through 63 overlap | |
221 | with VR registers 0 through 31. */ | |
222 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
223 | |
224 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
225 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
226 | registers. Zero if we've tried one of them and gotten an | |
227 | error. */ | |
9abe5450 EZ |
228 | int have_ptrace_getvrregs = 1; |
229 | ||
01904826 JB |
230 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
231 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
232 | registers. Zero if we've tried one of them and gotten an | |
233 | error. */ | |
234 | int have_ptrace_getsetevrregs = 1; | |
235 | ||
1dfe79e8 SDJ |
236 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
237 | PTRACE_SETREGS requests, for reading and writing the | |
238 | general-purpose registers. Zero if we've tried one of | |
239 | them and gotten an error. */ | |
240 | int have_ptrace_getsetregs = 1; | |
241 | ||
242 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
243 | PTRACE_SETFPREGS requests, for reading and writing the | |
244 | floating-pointers registers. Zero if we've tried one of | |
245 | them and gotten an error. */ | |
246 | int have_ptrace_getsetfpregs = 1; | |
247 | ||
16333c4f EZ |
248 | /* *INDENT-OFF* */ |
249 | /* registers layout, as presented by the ptrace interface: | |
250 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
251 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
252 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
253 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
254 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
255 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
256 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
257 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
258 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ | |
259 | /* *INDENT_ON * */ | |
c877c8e6 | 260 | |
45229ea4 | 261 | static int |
e101270f | 262 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 263 | { |
16333c4f | 264 | int u_addr = -1; |
e101270f | 265 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
266 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
267 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 268 | int wordsize = sizeof (long); |
16333c4f EZ |
269 | |
270 | /* General purpose registers occupy 1 slot each in the buffer */ | |
8bf659e8 JB |
271 | if (regno >= tdep->ppc_gp0_regnum |
272 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 273 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 274 | |
49ff75ad JB |
275 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
276 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
277 | slot each in 64-bit interface. */ | |
383f0f5b JB |
278 | if (tdep->ppc_fp0_regnum >= 0 |
279 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
280 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
281 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f EZ |
282 | |
283 | /* UISA special purpose registers: 1 slot each */ | |
e101270f | 284 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 285 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 286 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 287 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 288 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 289 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 290 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 291 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 292 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 293 | u_addr = PT_CTR * wordsize; |
f8c59253 | 294 | #ifdef PT_MQ |
dc5cfeb6 | 295 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 296 | u_addr = PT_MQ * wordsize; |
f8c59253 | 297 | #endif |
dc5cfeb6 | 298 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 299 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
300 | if (regno == PPC_ORIG_R3_REGNUM) |
301 | u_addr = PT_ORIG_R3 * wordsize; | |
302 | if (regno == PPC_TRAP_REGNUM) | |
303 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
304 | if (tdep->ppc_fpscr_regnum >= 0 |
305 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
306 | { |
307 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
308 | kernel headers incorrectly contained the 32-bit definition of | |
309 | PT_FPSCR. For the 32-bit definition, floating-point | |
310 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 311 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
312 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
313 | hence no adjustment is necessary. Hack around this. */ | |
314 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
315 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
316 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
317 | slot and not just its second word. The PT_FPSCR supplied when | |
318 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
319 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
320 | && PT_FPSCR == (48 + 2*32 + 1)) | |
321 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
322 | else |
323 | u_addr = PT_FPSCR * wordsize; | |
324 | } | |
16333c4f | 325 | return u_addr; |
c877c8e6 KB |
326 | } |
327 | ||
604c2f83 LM |
328 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
329 | registers set mechanism, as opposed to the interface for all the | |
330 | other registers, that stores/fetches each register individually. */ | |
331 | static void | |
332 | fetch_vsx_register (struct regcache *regcache, int tid, int regno) | |
333 | { | |
334 | int ret; | |
335 | gdb_vsxregset_t regs; | |
336 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
337 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
338 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
339 | ||
340 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
341 | if (ret < 0) | |
342 | { | |
343 | if (errno == EIO) | |
344 | { | |
345 | have_ptrace_getsetvsxregs = 0; | |
346 | return; | |
347 | } | |
348 | perror_with_name (_("Unable to fetch VSX register")); | |
349 | } | |
350 | ||
351 | regcache_raw_supply (regcache, regno, | |
352 | regs + (regno - tdep->ppc_vsr0_upper_regnum) | |
353 | * vsxregsize); | |
354 | } | |
355 | ||
9abe5450 EZ |
356 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
357 | registers set mechanism, as opposed to the interface for all the | |
358 | other registers, that stores/fetches each register individually. */ | |
359 | static void | |
56be3814 | 360 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
361 | { |
362 | int ret; | |
363 | int offset = 0; | |
364 | gdb_vrregset_t regs; | |
40a6adc1 MD |
365 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
366 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
367 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
368 | |
369 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
370 | if (ret < 0) | |
371 | { | |
372 | if (errno == EIO) | |
373 | { | |
374 | have_ptrace_getvrregs = 0; | |
375 | return; | |
376 | } | |
e2e0b3e5 | 377 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
378 | } |
379 | ||
380 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
381 | long on the hardware. We deal only with the lower 4 bytes of the | |
382 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
383 | there is no need to define an offset for it. */ | |
384 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 385 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 386 | |
56be3814 | 387 | regcache_raw_supply (regcache, regno, |
23a6d369 | 388 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
389 | } |
390 | ||
01904826 JB |
391 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
392 | SPE-specific registers, and place the results in EVRREGSET. If we | |
393 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
394 | zeros. | |
395 | ||
396 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
397 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
398 | set_spe_registers. */ | |
399 | static void | |
400 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
401 | { | |
402 | if (have_ptrace_getsetevrregs) | |
403 | { | |
404 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
405 | return; | |
406 | else | |
407 | { | |
408 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
409 | we just return zeros. */ | |
410 | if (errno == EIO) | |
411 | have_ptrace_getsetevrregs = 0; | |
412 | else | |
413 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 414 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
415 | } |
416 | } | |
417 | ||
418 | memset (evrregset, 0, sizeof (*evrregset)); | |
419 | } | |
420 | ||
6ced10dd JB |
421 | /* Supply values from TID for SPE-specific raw registers: the upper |
422 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
423 | be the number of an upper half register, acc, spefscr, or -1 to | |
424 | supply the values of all registers. */ | |
01904826 | 425 | static void |
56be3814 | 426 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 427 | { |
40a6adc1 MD |
428 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
429 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
430 | struct gdb_evrregset_t evrregs; |
431 | ||
6ced10dd | 432 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 433 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 434 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 435 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 436 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 437 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 438 | |
01904826 JB |
439 | get_spe_registers (tid, &evrregs); |
440 | ||
6ced10dd | 441 | if (regno == -1) |
01904826 | 442 | { |
6ced10dd JB |
443 | int i; |
444 | ||
445 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 446 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 447 | &evrregs.evr[i]); |
01904826 | 448 | } |
6ced10dd JB |
449 | else if (tdep->ppc_ev0_upper_regnum <= regno |
450 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 451 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
452 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
453 | ||
454 | if (regno == -1 | |
455 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 456 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
457 | |
458 | if (regno == -1 | |
459 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 460 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 461 | &evrregs.spefscr); |
01904826 JB |
462 | } |
463 | ||
45229ea4 | 464 | static void |
56be3814 | 465 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 466 | { |
40a6adc1 MD |
467 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
468 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 469 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 470 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 471 | int bytes_transferred; |
45229ea4 | 472 | unsigned int offset; /* Offset of registers within the u area. */ |
d9d9c31f | 473 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 474 | |
be8626e0 | 475 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
476 | { |
477 | /* If this is the first time through, or if it is not the first | |
478 | time through, and we have comfirmed that there is kernel | |
479 | support for such a ptrace request, then go and fetch the | |
480 | register. */ | |
481 | if (have_ptrace_getvrregs) | |
482 | { | |
56be3814 | 483 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
484 | return; |
485 | } | |
486 | /* If we have discovered that there is no ptrace support for | |
487 | AltiVec registers, fall through and return zeroes, because | |
488 | regaddr will be -1 in this case. */ | |
489 | } | |
604c2f83 LM |
490 | if (vsx_register_p (gdbarch, regno)) |
491 | { | |
492 | if (have_ptrace_getsetvsxregs) | |
493 | { | |
494 | fetch_vsx_register (regcache, tid, regno); | |
495 | return; | |
496 | } | |
497 | } | |
be8626e0 | 498 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 499 | { |
56be3814 | 500 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
501 | return; |
502 | } | |
9abe5450 | 503 | |
45229ea4 EZ |
504 | if (regaddr == -1) |
505 | { | |
40a6adc1 | 506 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 507 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
508 | return; |
509 | } | |
510 | ||
411cb3f9 | 511 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
512 | 32-bit platform, 64-bit floating-point registers will require two |
513 | transfers. */ | |
4a19ea35 | 514 | for (bytes_transferred = 0; |
40a6adc1 | 515 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 516 | bytes_transferred += sizeof (long)) |
45229ea4 EZ |
517 | { |
518 | errno = 0; | |
411cb3f9 PG |
519 | *(long *) &buf[bytes_transferred] |
520 | = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); | |
521 | regaddr += sizeof (long); | |
45229ea4 EZ |
522 | if (errno != 0) |
523 | { | |
bc97b3ba JB |
524 | char message[128]; |
525 | sprintf (message, "reading register %s (#%d)", | |
40a6adc1 | 526 | gdbarch_register_name (gdbarch, regno), regno); |
bc97b3ba | 527 | perror_with_name (message); |
45229ea4 EZ |
528 | } |
529 | } | |
56d0d96a | 530 | |
4a19ea35 JB |
531 | /* Now supply the register. Keep in mind that the regcache's idea |
532 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 533 | (long). */ |
40a6adc1 | 534 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
535 | { |
536 | /* Little-endian values are always found at the left end of the | |
537 | bytes transferred. */ | |
56be3814 | 538 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 | 539 | } |
40a6adc1 | 540 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
541 | { |
542 | /* Big-endian values are found at the right end of the bytes | |
543 | transferred. */ | |
40a6adc1 | 544 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
56be3814 | 545 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
546 | } |
547 | else | |
a44bddec | 548 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 549 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 550 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
551 | } |
552 | ||
604c2f83 LM |
553 | static void |
554 | supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
555 | { | |
556 | int i; | |
557 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
558 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
559 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
560 | ||
561 | for (i = 0; i < ppc_num_vshrs; i++) | |
562 | { | |
563 | regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
564 | *vsxregsetp + i * vsxregsize); | |
565 | } | |
566 | } | |
567 | ||
9abe5450 | 568 | static void |
56be3814 | 569 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
570 | { |
571 | int i; | |
40a6adc1 MD |
572 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
573 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 574 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
575 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
576 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
577 | |
578 | for (i = 0; i < num_of_vrregs; i++) | |
579 | { | |
580 | /* The last 2 registers of this set are only 32 bit long, not | |
581 | 128. However an offset is necessary only for VSCR because it | |
582 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
583 | slot. */ | |
584 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 585 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 586 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 587 | else |
56be3814 | 588 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 589 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
590 | } |
591 | } | |
592 | ||
604c2f83 LM |
593 | static void |
594 | fetch_vsx_registers (struct regcache *regcache, int tid) | |
595 | { | |
596 | int ret; | |
597 | gdb_vsxregset_t regs; | |
598 | ||
599 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
600 | if (ret < 0) | |
601 | { | |
602 | if (errno == EIO) | |
603 | { | |
604 | have_ptrace_getsetvsxregs = 0; | |
605 | return; | |
606 | } | |
607 | perror_with_name (_("Unable to fetch VSX registers")); | |
608 | } | |
609 | supply_vsxregset (regcache, ®s); | |
610 | } | |
611 | ||
9abe5450 | 612 | static void |
56be3814 | 613 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
614 | { |
615 | int ret; | |
616 | gdb_vrregset_t regs; | |
617 | ||
618 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
619 | if (ret < 0) | |
620 | { | |
621 | if (errno == EIO) | |
622 | { | |
623 | have_ptrace_getvrregs = 0; | |
624 | return; | |
625 | } | |
e2e0b3e5 | 626 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 627 | } |
56be3814 | 628 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
629 | } |
630 | ||
1dfe79e8 SDJ |
631 | /* This function actually issues the request to ptrace, telling |
632 | it to get all general-purpose registers and put them into the | |
633 | specified regset. | |
634 | ||
635 | If the ptrace request does not exist, this function returns 0 | |
636 | and properly sets the have_ptrace_* flag. If the request fails, | |
637 | this function calls perror_with_name. Otherwise, if the request | |
638 | succeeds, then the regcache gets filled and 1 is returned. */ | |
639 | static int | |
640 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
641 | { | |
642 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
643 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
644 | gdb_gregset_t gregset; | |
645 | ||
646 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
647 | { | |
648 | if (errno == EIO) | |
649 | { | |
650 | have_ptrace_getsetregs = 0; | |
651 | return 0; | |
652 | } | |
653 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
654 | } | |
655 | ||
656 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
657 | ||
658 | return 1; | |
659 | } | |
660 | ||
661 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
662 | responsible for verifying if this target has the ptrace request | |
663 | that can be used to fetch all general-purpose registers at one | |
664 | shot. If it doesn't, then we should fetch them using the | |
665 | old-fashioned way, which is to iterate over the registers and | |
666 | request them one by one. */ | |
667 | static void | |
668 | fetch_gp_regs (struct regcache *regcache, int tid) | |
669 | { | |
670 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
671 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
672 | int i; | |
673 | ||
674 | if (have_ptrace_getsetregs) | |
675 | if (fetch_all_gp_regs (regcache, tid)) | |
676 | return; | |
677 | ||
678 | /* If we've hit this point, it doesn't really matter which | |
679 | architecture we are using. We just need to read the | |
680 | registers in the "old-fashioned way". */ | |
681 | for (i = 0; i < ppc_num_gprs; i++) | |
682 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
683 | } | |
684 | ||
685 | /* This function actually issues the request to ptrace, telling | |
686 | it to get all floating-point registers and put them into the | |
687 | specified regset. | |
688 | ||
689 | If the ptrace request does not exist, this function returns 0 | |
690 | and properly sets the have_ptrace_* flag. If the request fails, | |
691 | this function calls perror_with_name. Otherwise, if the request | |
692 | succeeds, then the regcache gets filled and 1 is returned. */ | |
693 | static int | |
694 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
695 | { | |
696 | gdb_fpregset_t fpregs; | |
697 | ||
698 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
699 | { | |
700 | if (errno == EIO) | |
701 | { | |
702 | have_ptrace_getsetfpregs = 0; | |
703 | return 0; | |
704 | } | |
705 | perror_with_name (_("Couldn't get floating-point registers.")); | |
706 | } | |
707 | ||
708 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
709 | ||
710 | return 1; | |
711 | } | |
712 | ||
713 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
714 | responsible for verifying if this target has the ptrace request | |
715 | that can be used to fetch all floating-point registers at one | |
716 | shot. If it doesn't, then we should fetch them using the | |
717 | old-fashioned way, which is to iterate over the registers and | |
718 | request them one by one. */ | |
719 | static void | |
720 | fetch_fp_regs (struct regcache *regcache, int tid) | |
721 | { | |
722 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
723 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
724 | int i; | |
725 | ||
726 | if (have_ptrace_getsetfpregs) | |
727 | if (fetch_all_fp_regs (regcache, tid)) | |
728 | return; | |
729 | ||
730 | /* If we've hit this point, it doesn't really matter which | |
731 | architecture we are using. We just need to read the | |
732 | registers in the "old-fashioned way". */ | |
733 | for (i = 0; i < ppc_num_fprs; i++) | |
734 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
735 | } | |
736 | ||
45229ea4 | 737 | static void |
56be3814 | 738 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
739 | { |
740 | int i; | |
40a6adc1 MD |
741 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
742 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 743 | |
1dfe79e8 | 744 | fetch_gp_regs (regcache, tid); |
32b99774 | 745 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 746 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 747 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 748 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 749 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 750 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 751 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 752 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 753 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 754 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 755 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 756 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 757 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 758 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 759 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
760 | if (ppc_linux_trap_reg_p (gdbarch)) |
761 | { | |
762 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
763 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
764 | } | |
32b99774 | 765 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 766 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
767 | if (have_ptrace_getvrregs) |
768 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 769 | fetch_altivec_registers (regcache, tid); |
604c2f83 LM |
770 | if (have_ptrace_getsetvsxregs) |
771 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
772 | fetch_vsx_registers (regcache, tid); | |
6ced10dd | 773 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 774 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
775 | } |
776 | ||
777 | /* Fetch registers from the child process. Fetch all registers if | |
778 | regno == -1, otherwise fetch all general registers or all floating | |
779 | point registers depending upon the value of regno. */ | |
10d6c8cd | 780 | static void |
28439f5e PA |
781 | ppc_linux_fetch_inferior_registers (struct target_ops *ops, |
782 | struct regcache *regcache, int regno) | |
45229ea4 | 783 | { |
9abe5450 | 784 | /* Overload thread id onto process id */ |
05f13b9c EZ |
785 | int tid = TIDGET (inferior_ptid); |
786 | ||
787 | /* No thread id, just use process id */ | |
788 | if (tid == 0) | |
789 | tid = PIDGET (inferior_ptid); | |
790 | ||
9abe5450 | 791 | if (regno == -1) |
56be3814 | 792 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 793 | else |
56be3814 | 794 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
795 | } |
796 | ||
604c2f83 LM |
797 | /* Store one VSX register. */ |
798 | static void | |
799 | store_vsx_register (const struct regcache *regcache, int tid, int regno) | |
800 | { | |
801 | int ret; | |
802 | gdb_vsxregset_t regs; | |
803 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
804 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
805 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
806 | ||
807 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
808 | if (ret < 0) | |
809 | { | |
810 | if (errno == EIO) | |
811 | { | |
812 | have_ptrace_getsetvsxregs = 0; | |
813 | return; | |
814 | } | |
815 | perror_with_name (_("Unable to fetch VSX register")); | |
816 | } | |
817 | ||
818 | regcache_raw_collect (regcache, regno, regs + | |
819 | (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); | |
820 | ||
821 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
822 | if (ret < 0) | |
823 | perror_with_name (_("Unable to store VSX register")); | |
824 | } | |
825 | ||
45229ea4 | 826 | /* Store one register. */ |
9abe5450 | 827 | static void |
56be3814 | 828 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
829 | { |
830 | int ret; | |
831 | int offset = 0; | |
832 | gdb_vrregset_t regs; | |
40a6adc1 MD |
833 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
834 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
835 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
836 | |
837 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
838 | if (ret < 0) | |
839 | { | |
840 | if (errno == EIO) | |
841 | { | |
842 | have_ptrace_getvrregs = 0; | |
843 | return; | |
844 | } | |
e2e0b3e5 | 845 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
846 | } |
847 | ||
848 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
849 | long on the hardware. */ | |
850 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 851 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 852 | |
56be3814 | 853 | regcache_raw_collect (regcache, regno, |
822c9732 | 854 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
855 | |
856 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
857 | if (ret < 0) | |
e2e0b3e5 | 858 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
859 | } |
860 | ||
01904826 JB |
861 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
862 | general-purpose registers and its SPE-specific registers to the | |
863 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
864 | nothing. | |
865 | ||
866 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
867 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
868 | get_spe_registers. */ | |
869 | static void | |
870 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
871 | { | |
872 | if (have_ptrace_getsetevrregs) | |
873 | { | |
874 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
875 | return; | |
876 | else | |
877 | { | |
878 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
879 | supported; we fail silently, and don't try the call | |
880 | again. */ | |
881 | if (errno == EIO) | |
882 | have_ptrace_getsetevrregs = 0; | |
883 | else | |
884 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 885 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
886 | } |
887 | } | |
888 | } | |
889 | ||
6ced10dd JB |
890 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
891 | If REGNO is -1, write the values of all the SPE-specific | |
892 | registers. */ | |
01904826 | 893 | static void |
56be3814 | 894 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 895 | { |
40a6adc1 MD |
896 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
897 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
898 | struct gdb_evrregset_t evrregs; |
899 | ||
6ced10dd | 900 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 901 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 902 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 903 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 904 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 905 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 906 | |
6ced10dd JB |
907 | if (regno == -1) |
908 | /* Since we're going to write out every register, the code below | |
909 | should store to every field of evrregs; if that doesn't happen, | |
910 | make it obvious by initializing it with suspicious values. */ | |
911 | memset (&evrregs, 42, sizeof (evrregs)); | |
912 | else | |
913 | /* We can only read and write the entire EVR register set at a | |
914 | time, so to write just a single register, we do a | |
915 | read-modify-write maneuver. */ | |
916 | get_spe_registers (tid, &evrregs); | |
917 | ||
918 | if (regno == -1) | |
01904826 | 919 | { |
6ced10dd JB |
920 | int i; |
921 | ||
922 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 923 | regcache_raw_collect (regcache, |
6ced10dd JB |
924 | tdep->ppc_ev0_upper_regnum + i, |
925 | &evrregs.evr[i]); | |
01904826 | 926 | } |
6ced10dd JB |
927 | else if (tdep->ppc_ev0_upper_regnum <= regno |
928 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 929 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
930 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
931 | ||
932 | if (regno == -1 | |
933 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 934 | regcache_raw_collect (regcache, |
6ced10dd JB |
935 | tdep->ppc_acc_regnum, |
936 | &evrregs.acc); | |
937 | ||
938 | if (regno == -1 | |
939 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 940 | regcache_raw_collect (regcache, |
6ced10dd JB |
941 | tdep->ppc_spefscr_regnum, |
942 | &evrregs.spefscr); | |
01904826 JB |
943 | |
944 | /* Write back the modified register set. */ | |
945 | set_spe_registers (tid, &evrregs); | |
946 | } | |
947 | ||
45229ea4 | 948 | static void |
56be3814 | 949 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 950 | { |
40a6adc1 MD |
951 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
952 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 953 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 954 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 955 | int i; |
4a19ea35 | 956 | size_t bytes_to_transfer; |
d9d9c31f | 957 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 958 | |
be8626e0 | 959 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 960 | { |
56be3814 | 961 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
962 | return; |
963 | } | |
604c2f83 LM |
964 | if (vsx_register_p (gdbarch, regno)) |
965 | { | |
966 | store_vsx_register (regcache, tid, regno); | |
967 | return; | |
968 | } | |
be8626e0 | 969 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 970 | { |
56be3814 | 971 | store_spe_register (regcache, tid, regno); |
01904826 JB |
972 | return; |
973 | } | |
45229ea4 | 974 | |
9abe5450 EZ |
975 | if (regaddr == -1) |
976 | return; | |
977 | ||
4a19ea35 JB |
978 | /* First collect the register. Keep in mind that the regcache's |
979 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 980 | (long). */ |
56d0d96a | 981 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
982 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
983 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
984 | { |
985 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 986 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 987 | } |
40a6adc1 | 988 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
989 | { |
990 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 991 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
56be3814 | 992 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
993 | } |
994 | ||
411cb3f9 | 995 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 EZ |
996 | { |
997 | errno = 0; | |
411cb3f9 PG |
998 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, |
999 | *(long *) &buf[i]); | |
1000 | regaddr += sizeof (long); | |
e3f36dbd KB |
1001 | |
1002 | if (errno == EIO | |
7284e1be UW |
1003 | && (regno == tdep->ppc_fpscr_regnum |
1004 | || regno == PPC_ORIG_R3_REGNUM | |
1005 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1006 | { |
7284e1be UW |
1007 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1008 | or trap to be written. */ | |
e3f36dbd KB |
1009 | continue; |
1010 | } | |
1011 | ||
45229ea4 EZ |
1012 | if (errno != 0) |
1013 | { | |
bc97b3ba JB |
1014 | char message[128]; |
1015 | sprintf (message, "writing register %s (#%d)", | |
40a6adc1 | 1016 | gdbarch_register_name (gdbarch, regno), regno); |
bc97b3ba | 1017 | perror_with_name (message); |
45229ea4 EZ |
1018 | } |
1019 | } | |
1020 | } | |
1021 | ||
604c2f83 LM |
1022 | static void |
1023 | fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
1024 | { | |
1025 | int i; | |
1026 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1027 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1028 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
1029 | ||
1030 | for (i = 0; i < ppc_num_vshrs; i++) | |
1031 | regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
1032 | *vsxregsetp + i * vsxregsize); | |
1033 | } | |
1034 | ||
9abe5450 | 1035 | static void |
56be3814 | 1036 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
1037 | { |
1038 | int i; | |
40a6adc1 MD |
1039 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1040 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 1041 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
1042 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
1043 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
1044 | |
1045 | for (i = 0; i < num_of_vrregs; i++) | |
1046 | { | |
1047 | /* The last 2 registers of this set are only 32 bit long, not | |
1048 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
1049 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 1050 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1051 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 1052 | else |
56be3814 | 1053 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1054 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
1055 | } |
1056 | } | |
1057 | ||
604c2f83 LM |
1058 | static void |
1059 | store_vsx_registers (const struct regcache *regcache, int tid) | |
1060 | { | |
1061 | int ret; | |
1062 | gdb_vsxregset_t regs; | |
1063 | ||
1064 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
1065 | if (ret < 0) | |
1066 | { | |
1067 | if (errno == EIO) | |
1068 | { | |
1069 | have_ptrace_getsetvsxregs = 0; | |
1070 | return; | |
1071 | } | |
1072 | perror_with_name (_("Couldn't get VSX registers")); | |
1073 | } | |
1074 | ||
1075 | fill_vsxregset (regcache, ®s); | |
1076 | ||
1077 | if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) | |
1078 | perror_with_name (_("Couldn't write VSX registers")); | |
1079 | } | |
1080 | ||
9abe5450 | 1081 | static void |
56be3814 | 1082 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
1083 | { |
1084 | int ret; | |
1085 | gdb_vrregset_t regs; | |
1086 | ||
0897f59b | 1087 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
1088 | if (ret < 0) |
1089 | { | |
1090 | if (errno == EIO) | |
1091 | { | |
1092 | have_ptrace_getvrregs = 0; | |
1093 | return; | |
1094 | } | |
e2e0b3e5 | 1095 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
1096 | } |
1097 | ||
56be3814 | 1098 | fill_vrregset (regcache, ®s); |
9abe5450 | 1099 | |
0897f59b | 1100 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 1101 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
1102 | } |
1103 | ||
1dfe79e8 SDJ |
1104 | /* This function actually issues the request to ptrace, telling |
1105 | it to store all general-purpose registers present in the specified | |
1106 | regset. | |
1107 | ||
1108 | If the ptrace request does not exist, this function returns 0 | |
1109 | and properly sets the have_ptrace_* flag. If the request fails, | |
1110 | this function calls perror_with_name. Otherwise, if the request | |
1111 | succeeds, then the regcache is stored and 1 is returned. */ | |
1112 | static int | |
1113 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1114 | { | |
1115 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1116 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1117 | gdb_gregset_t gregset; | |
1118 | ||
1119 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1120 | { | |
1121 | if (errno == EIO) | |
1122 | { | |
1123 | have_ptrace_getsetregs = 0; | |
1124 | return 0; | |
1125 | } | |
1126 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1127 | } | |
1128 | ||
1129 | fill_gregset (regcache, &gregset, regno); | |
1130 | ||
1131 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1132 | { | |
1133 | if (errno == EIO) | |
1134 | { | |
1135 | have_ptrace_getsetregs = 0; | |
1136 | return 0; | |
1137 | } | |
1138 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1139 | } | |
1140 | ||
1141 | return 1; | |
1142 | } | |
1143 | ||
1144 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1145 | responsible for verifying if this target has the ptrace request | |
1146 | that can be used to store all general-purpose registers at one | |
1147 | shot. If it doesn't, then we should store them using the | |
1148 | old-fashioned way, which is to iterate over the registers and | |
1149 | store them one by one. */ | |
45229ea4 | 1150 | static void |
1dfe79e8 | 1151 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1152 | { |
40a6adc1 MD |
1153 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1154 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dfe79e8 SDJ |
1155 | int i; |
1156 | ||
1157 | if (have_ptrace_getsetregs) | |
1158 | if (store_all_gp_regs (regcache, tid, regno)) | |
1159 | return; | |
1160 | ||
1161 | /* If we hit this point, it doesn't really matter which | |
1162 | architecture we are using. We just need to store the | |
1163 | registers in the "old-fashioned way". */ | |
6ced10dd | 1164 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1165 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1166 | } |
1167 | ||
1168 | /* This function actually issues the request to ptrace, telling | |
1169 | it to store all floating-point registers present in the specified | |
1170 | regset. | |
1171 | ||
1172 | If the ptrace request does not exist, this function returns 0 | |
1173 | and properly sets the have_ptrace_* flag. If the request fails, | |
1174 | this function calls perror_with_name. Otherwise, if the request | |
1175 | succeeds, then the regcache is stored and 1 is returned. */ | |
1176 | static int | |
1177 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1178 | { | |
1179 | gdb_fpregset_t fpregs; | |
1180 | ||
1181 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1182 | { | |
1183 | if (errno == EIO) | |
1184 | { | |
1185 | have_ptrace_getsetfpregs = 0; | |
1186 | return 0; | |
1187 | } | |
1188 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1189 | } | |
1190 | ||
1191 | fill_fpregset (regcache, &fpregs, regno); | |
1192 | ||
1193 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1194 | { | |
1195 | if (errno == EIO) | |
1196 | { | |
1197 | have_ptrace_getsetfpregs = 0; | |
1198 | return 0; | |
1199 | } | |
1200 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1201 | } | |
1202 | ||
1203 | return 1; | |
1204 | } | |
1205 | ||
1206 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1207 | responsible for verifying if this target has the ptrace request | |
1208 | that can be used to store all floating-point registers at one | |
1209 | shot. If it doesn't, then we should store them using the | |
1210 | old-fashioned way, which is to iterate over the registers and | |
1211 | store them one by one. */ | |
1212 | static void | |
1213 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1214 | { | |
1215 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1216 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1217 | int i; | |
1218 | ||
1219 | if (have_ptrace_getsetfpregs) | |
1220 | if (store_all_fp_regs (regcache, tid, regno)) | |
1221 | return; | |
1222 | ||
1223 | /* If we hit this point, it doesn't really matter which | |
1224 | architecture we are using. We just need to store the | |
1225 | registers in the "old-fashioned way". */ | |
1226 | for (i = 0; i < ppc_num_fprs; i++) | |
1227 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1228 | } | |
1229 | ||
1230 | static void | |
1231 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1232 | { | |
1233 | int i; | |
1234 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1235 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1236 | ||
1237 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1238 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1239 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1240 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1241 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1242 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1243 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1244 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1245 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1246 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1247 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1248 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1249 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1250 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1251 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1252 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1253 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1254 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1255 | if (ppc_linux_trap_reg_p (gdbarch)) |
1256 | { | |
1257 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1258 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1259 | } | |
9abe5450 EZ |
1260 | if (have_ptrace_getvrregs) |
1261 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 1262 | store_altivec_registers (regcache, tid); |
604c2f83 LM |
1263 | if (have_ptrace_getsetvsxregs) |
1264 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
1265 | store_vsx_registers (regcache, tid); | |
6ced10dd | 1266 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1267 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
1268 | } |
1269 | ||
e0d24f8d WZ |
1270 | static int |
1271 | ppc_linux_check_watch_resources (int type, int cnt, int ot) | |
1272 | { | |
1273 | int tid; | |
1274 | ptid_t ptid = inferior_ptid; | |
1275 | ||
1276 | /* DABR (data address breakpoint register) is optional for PPC variants. | |
1277 | Some variants have one DABR, others have none. So CNT can't be larger | |
1278 | than 1. */ | |
1279 | if (cnt > 1) | |
1280 | return 0; | |
1281 | ||
1282 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether | |
1283 | the target has DABR. If either answer is no, the ptrace call will | |
1284 | return -1. Fail in that case. */ | |
1285 | tid = TIDGET (ptid); | |
1286 | if (tid == 0) | |
1287 | tid = PIDGET (ptid); | |
1288 | ||
1289 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1290 | return 0; | |
1291 | return 1; | |
1292 | } | |
1293 | ||
b7622095 LM |
1294 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
1295 | unsigned long ppc_linux_get_hwcap (void) | |
1296 | { | |
1297 | CORE_ADDR field; | |
1298 | ||
fcb09a75 | 1299 | if (target_auxv_search (¤t_target, AT_HWCAP, &field)) |
b7622095 LM |
1300 | return (unsigned long) field; |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
e0d24f8d WZ |
1305 | static int |
1306 | ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
1307 | { | |
1308 | /* Handle sub-8-byte quantities. */ | |
1309 | if (len <= 0) | |
1310 | return 0; | |
1311 | ||
b7622095 LM |
1312 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
1313 | processors. DAC-based processors, like the PowerPC 440, will use | |
1314 | addresses aligned to 4-bytes due to the way the read/write flags are | |
1315 | passed at the moment. */ | |
1316 | if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1317 | && (addr + len) > (addr & ~3) + 4) | |
1318 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1319 | return 0; |
1320 | ||
1321 | return 1; | |
1322 | } | |
1323 | ||
9f0bdab8 DJ |
1324 | /* The cached DABR value, to install in new threads. */ |
1325 | static long saved_dabr_value; | |
1326 | ||
e0d24f8d | 1327 | /* Set a watchpoint of type TYPE at address ADDR. */ |
2c387241 | 1328 | static int |
e0d24f8d WZ |
1329 | ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw) |
1330 | { | |
9f0bdab8 DJ |
1331 | struct lwp_info *lp; |
1332 | ptid_t ptid; | |
e0d24f8d | 1333 | long dabr_value; |
b7622095 LM |
1334 | long read_mode, write_mode; |
1335 | ||
1336 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1337 | { | |
1338 | /* PowerPC 440 requires only the read/write flags to be passed | |
1339 | to the kernel. */ | |
1340 | read_mode = 1; | |
1341 | write_mode = 2; | |
1342 | } | |
1343 | else | |
1344 | { | |
1345 | /* PowerPC 970 and other DABR-based processors are required to pass | |
1346 | the Breakpoint Translation bit together with the flags. */ | |
1347 | read_mode = 5; | |
1348 | write_mode = 6; | |
1349 | } | |
1350 | ||
1351 | dabr_value = addr & ~(read_mode | write_mode); | |
e0d24f8d WZ |
1352 | switch (rw) |
1353 | { | |
1354 | case hw_read: | |
1355 | /* Set read and translate bits. */ | |
b7622095 | 1356 | dabr_value |= read_mode; |
e0d24f8d WZ |
1357 | break; |
1358 | case hw_write: | |
1359 | /* Set write and translate bits. */ | |
b7622095 | 1360 | dabr_value |= write_mode; |
e0d24f8d WZ |
1361 | break; |
1362 | case hw_access: | |
1363 | /* Set read, write and translate bits. */ | |
b7622095 | 1364 | dabr_value |= read_mode | write_mode; |
e0d24f8d WZ |
1365 | break; |
1366 | } | |
1367 | ||
1c86e440 LM |
1368 | saved_dabr_value = dabr_value; |
1369 | ||
9f0bdab8 DJ |
1370 | ALL_LWPS (lp, ptid) |
1371 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) | |
1372 | return -1; | |
1c86e440 | 1373 | |
9f0bdab8 | 1374 | return 0; |
e0d24f8d WZ |
1375 | } |
1376 | ||
2c387241 AM |
1377 | static int |
1378 | ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw) | |
e0d24f8d | 1379 | { |
9f0bdab8 DJ |
1380 | struct lwp_info *lp; |
1381 | ptid_t ptid; | |
1382 | long dabr_value = 0; | |
1383 | ||
1384 | saved_dabr_value = 0; | |
1385 | ALL_LWPS (lp, ptid) | |
1386 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) | |
1387 | return -1; | |
1388 | return 0; | |
e0d24f8d WZ |
1389 | } |
1390 | ||
9f0bdab8 DJ |
1391 | static void |
1392 | ppc_linux_new_thread (ptid_t ptid) | |
e0d24f8d | 1393 | { |
9f0bdab8 | 1394 | ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value); |
e0d24f8d WZ |
1395 | } |
1396 | ||
1397 | static int | |
9f0bdab8 | 1398 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) |
e0d24f8d | 1399 | { |
9f0bdab8 | 1400 | struct siginfo *siginfo_p; |
e0d24f8d | 1401 | |
9f0bdab8 | 1402 | siginfo_p = linux_nat_get_siginfo (inferior_ptid); |
e0d24f8d | 1403 | |
9f0bdab8 DJ |
1404 | if (siginfo_p->si_signo != SIGTRAP |
1405 | || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e0d24f8d WZ |
1406 | return 0; |
1407 | ||
407f1a2e | 1408 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr; |
e0d24f8d WZ |
1409 | return 1; |
1410 | } | |
1411 | ||
9f0bdab8 DJ |
1412 | static int |
1413 | ppc_linux_stopped_by_watchpoint (void) | |
1414 | { | |
1415 | CORE_ADDR addr; | |
1416 | return ppc_linux_stopped_data_address (¤t_target, &addr); | |
1417 | } | |
1418 | ||
5009afc5 AS |
1419 | static int |
1420 | ppc_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1421 | CORE_ADDR addr, | |
1422 | CORE_ADDR start, int length) | |
1423 | { | |
b7622095 LM |
1424 | int mask; |
1425 | ||
1426 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1427 | mask = 3; | |
1428 | else | |
1429 | mask = 7; | |
1430 | ||
1431 | addr &= ~mask; | |
1432 | ||
1433 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ | |
1434 | return start <= addr + mask && start + length - 1 >= addr; | |
5009afc5 AS |
1435 | } |
1436 | ||
10d6c8cd | 1437 | static void |
28439f5e PA |
1438 | ppc_linux_store_inferior_registers (struct target_ops *ops, |
1439 | struct regcache *regcache, int regno) | |
45229ea4 | 1440 | { |
05f13b9c EZ |
1441 | /* Overload thread id onto process id */ |
1442 | int tid = TIDGET (inferior_ptid); | |
1443 | ||
1444 | /* No thread id, just use process id */ | |
1445 | if (tid == 0) | |
1446 | tid = PIDGET (inferior_ptid); | |
1447 | ||
45229ea4 | 1448 | if (regno >= 0) |
56be3814 | 1449 | store_register (regcache, tid, regno); |
45229ea4 | 1450 | else |
56be3814 | 1451 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
1452 | } |
1453 | ||
f2db237a AM |
1454 | /* Functions for transferring registers between a gregset_t or fpregset_t |
1455 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
1456 | by the ptrace interface, not the current program's ABI. eg. If a | |
1457 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we | |
1458 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
1459 | ||
50c9bd31 | 1460 | void |
7f7fe91e | 1461 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 1462 | { |
f2db237a | 1463 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 1464 | |
f2db237a | 1465 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
1466 | } |
1467 | ||
fdb28ac4 | 1468 | void |
7f7fe91e UW |
1469 | fill_gregset (const struct regcache *regcache, |
1470 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 1471 | { |
f2db237a | 1472 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 1473 | |
f2db237a AM |
1474 | if (regno == -1) |
1475 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
1476 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
1477 | } |
1478 | ||
50c9bd31 | 1479 | void |
7f7fe91e | 1480 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 1481 | { |
f2db237a AM |
1482 | const struct regset *regset = ppc_linux_fpregset (); |
1483 | ||
1484 | ppc_supply_fpregset (regset, regcache, -1, | |
1485 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 1486 | } |
fdb28ac4 | 1487 | |
fdb28ac4 | 1488 | void |
7f7fe91e UW |
1489 | fill_fpregset (const struct regcache *regcache, |
1490 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 1491 | { |
f2db237a AM |
1492 | const struct regset *regset = ppc_linux_fpregset (); |
1493 | ||
1494 | ppc_collect_fpregset (regset, regcache, regno, | |
1495 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 1496 | } |
10d6c8cd | 1497 | |
409c383c UW |
1498 | static int |
1499 | ppc_linux_target_wordsize (void) | |
1500 | { | |
1501 | int wordsize = 4; | |
1502 | ||
1503 | /* Check for 64-bit inferior process. This is the case when the host is | |
1504 | 64-bit, and in addition the top bit of the MSR register is set. */ | |
1505 | #ifdef __powerpc64__ | |
1506 | long msr; | |
1507 | ||
1508 | int tid = TIDGET (inferior_ptid); | |
1509 | if (tid == 0) | |
1510 | tid = PIDGET (inferior_ptid); | |
1511 | ||
1512 | errno = 0; | |
1513 | msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); | |
1514 | if (errno == 0 && msr < 0) | |
1515 | wordsize = 8; | |
1516 | #endif | |
1517 | ||
1518 | return wordsize; | |
1519 | } | |
1520 | ||
1521 | static int | |
1522 | ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr, | |
1523 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
1524 | { | |
1525 | int sizeof_auxv_field = ppc_linux_target_wordsize (); | |
1526 | gdb_byte *ptr = *readptr; | |
1527 | ||
1528 | if (endptr == ptr) | |
1529 | return 0; | |
1530 | ||
1531 | if (endptr - ptr < sizeof_auxv_field * 2) | |
1532 | return -1; | |
1533 | ||
1534 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field); | |
1535 | ptr += sizeof_auxv_field; | |
1536 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field); | |
1537 | ptr += sizeof_auxv_field; | |
1538 | ||
1539 | *readptr = ptr; | |
1540 | return 1; | |
1541 | } | |
1542 | ||
310a98e1 DJ |
1543 | static const struct target_desc * |
1544 | ppc_linux_read_description (struct target_ops *ops) | |
1545 | { | |
7284e1be | 1546 | int altivec = 0; |
604c2f83 | 1547 | int vsx = 0; |
69abc51c | 1548 | int isa205 = 0; |
7284e1be UW |
1549 | |
1550 | int tid = TIDGET (inferior_ptid); | |
1551 | if (tid == 0) | |
1552 | tid = PIDGET (inferior_ptid); | |
1553 | ||
310a98e1 DJ |
1554 | if (have_ptrace_getsetevrregs) |
1555 | { | |
1556 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
1557 | |
1558 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
1559 | return tdesc_powerpc_e500l; |
1560 | ||
1561 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
1562 | Anything else needs to be reported. */ | |
1563 | else if (errno != EIO) | |
1564 | perror_with_name (_("Unable to fetch SPE registers")); | |
1565 | } | |
1566 | ||
604c2f83 LM |
1567 | if (have_ptrace_getsetvsxregs) |
1568 | { | |
1569 | gdb_vsxregset_t vsxregset; | |
1570 | ||
1571 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
1572 | vsx = 1; | |
1573 | ||
1574 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
1575 | Anything else needs to be reported. */ | |
1576 | else if (errno != EIO) | |
1577 | perror_with_name (_("Unable to fetch VSX registers")); | |
1578 | } | |
1579 | ||
7284e1be UW |
1580 | if (have_ptrace_getvrregs) |
1581 | { | |
1582 | gdb_vrregset_t vrregset; | |
1583 | ||
1584 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
1585 | altivec = 1; | |
1586 | ||
1587 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
1588 | Anything else needs to be reported. */ | |
1589 | else if (errno != EIO) | |
1590 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
1591 | } |
1592 | ||
f04c6d38 TJB |
1593 | /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases |
1594 | the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this | |
1595 | ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only | |
1596 | PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher | |
1597 | half of the register are for Decimal Floating Point, we check if that | |
1598 | feature is available to decide the size of the FPSCR. */ | |
1599 | if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP) | |
69abc51c TJB |
1600 | isa205 = 1; |
1601 | ||
409c383c UW |
1602 | if (ppc_linux_target_wordsize () == 8) |
1603 | { | |
1604 | if (vsx) | |
1605 | return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; | |
1606 | else if (altivec) | |
1607 | return isa205? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; | |
1608 | ||
1609 | return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; | |
1610 | } | |
7284e1be | 1611 | |
604c2f83 | 1612 | if (vsx) |
69abc51c | 1613 | return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; |
604c2f83 | 1614 | else if (altivec) |
69abc51c | 1615 | return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; |
604c2f83 | 1616 | |
69abc51c | 1617 | return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; |
310a98e1 DJ |
1618 | } |
1619 | ||
10d6c8cd DJ |
1620 | void _initialize_ppc_linux_nat (void); |
1621 | ||
1622 | void | |
1623 | _initialize_ppc_linux_nat (void) | |
1624 | { | |
1625 | struct target_ops *t; | |
1626 | ||
1627 | /* Fill in the generic GNU/Linux methods. */ | |
1628 | t = linux_target (); | |
1629 | ||
1630 | /* Add our register access methods. */ | |
1631 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; | |
1632 | t->to_store_registers = ppc_linux_store_inferior_registers; | |
1633 | ||
e0d24f8d WZ |
1634 | /* Add our watchpoint methods. */ |
1635 | t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources; | |
1636 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; | |
1637 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; | |
1638 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; | |
1639 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; | |
1640 | t->to_stopped_data_address = ppc_linux_stopped_data_address; | |
5009afc5 | 1641 | t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; |
e0d24f8d | 1642 | |
310a98e1 | 1643 | t->to_read_description = ppc_linux_read_description; |
409c383c | 1644 | t->to_auxv_parse = ppc_linux_auxv_parse; |
310a98e1 | 1645 | |
10d6c8cd | 1646 | /* Register the target. */ |
f973ed9c | 1647 | linux_nat_add_target (t); |
9f0bdab8 | 1648 | linux_nat_set_new_thread (t, ppc_linux_new_thread); |
10d6c8cd | 1649 | } |