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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
ecd75fc8 | 3 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
c877c8e6 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
19 | |
20 | #include "defs.h" | |
6ffbb7ab | 21 | #include "observer.h" |
c877c8e6 KB |
22 | #include "frame.h" |
23 | #include "inferior.h" | |
6ffbb7ab | 24 | #include "gdbthread.h" |
c877c8e6 | 25 | #include "gdbcore.h" |
4e052eda | 26 | #include "regcache.h" |
10d6c8cd DJ |
27 | #include "target.h" |
28 | #include "linux-nat.h" | |
c877c8e6 | 29 | |
411cb3f9 | 30 | #include <stdint.h> |
c877c8e6 | 31 | #include <sys/types.h> |
c877c8e6 KB |
32 | #include <signal.h> |
33 | #include <sys/user.h> | |
34 | #include <sys/ioctl.h> | |
2555fe1a | 35 | #include "gdb_wait.h" |
c877c8e6 KB |
36 | #include <fcntl.h> |
37 | #include <sys/procfs.h> | |
45229ea4 | 38 | #include <sys/ptrace.h> |
c877c8e6 | 39 | |
0df8b418 | 40 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 41 | #include "gregset.h" |
16333c4f | 42 | #include "ppc-tdep.h" |
7284e1be UW |
43 | #include "ppc-linux-tdep.h" |
44 | ||
b7622095 LM |
45 | /* Required when using the AUXV. */ |
46 | #include "elf/common.h" | |
47 | #include "auxv.h" | |
48 | ||
7284e1be UW |
49 | /* This sometimes isn't defined. */ |
50 | #ifndef PT_ORIG_R3 | |
51 | #define PT_ORIG_R3 34 | |
52 | #endif | |
53 | #ifndef PT_TRAP | |
54 | #define PT_TRAP 40 | |
55 | #endif | |
c60c0f5f | 56 | |
69abc51c TJB |
57 | /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>. |
58 | If they aren't, we can provide them ourselves (their values are fixed | |
59 | because they are part of the kernel ABI). They are used in the AT_HWCAP | |
60 | entry of the AUXV. */ | |
f4d9bade UW |
61 | #ifndef PPC_FEATURE_CELL |
62 | #define PPC_FEATURE_CELL 0x00010000 | |
63 | #endif | |
b7622095 LM |
64 | #ifndef PPC_FEATURE_BOOKE |
65 | #define PPC_FEATURE_BOOKE 0x00008000 | |
66 | #endif | |
f04c6d38 TJB |
67 | #ifndef PPC_FEATURE_HAS_DFP |
68 | #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */ | |
69abc51c | 69 | #endif |
b7622095 | 70 | |
9abe5450 EZ |
71 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
72 | configure time check. Some older glibc's (for instance 2.2.1) | |
73 | don't have a specific powerpc version of ptrace.h, and fall back on | |
74 | a generic one. In such cases, sys/ptrace.h defines | |
75 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
76 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
77 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
78 | much useless. */ | |
79 | ||
80 | /* These definitions should really come from the glibc header files, | |
81 | but Glibc doesn't know about the vrregs yet. */ | |
82 | #ifndef PTRACE_GETVRREGS | |
83 | #define PTRACE_GETVRREGS 18 | |
84 | #define PTRACE_SETVRREGS 19 | |
85 | #endif | |
86 | ||
604c2f83 LM |
87 | /* PTRACE requests for POWER7 VSX registers. */ |
88 | #ifndef PTRACE_GETVSXREGS | |
89 | #define PTRACE_GETVSXREGS 27 | |
90 | #define PTRACE_SETVSXREGS 28 | |
91 | #endif | |
01904826 JB |
92 | |
93 | /* Similarly for the ptrace requests for getting / setting the SPE | |
94 | registers (ev0 -- ev31, acc, and spefscr). See the description of | |
95 | gdb_evrregset_t for details. */ | |
96 | #ifndef PTRACE_GETEVRREGS | |
97 | #define PTRACE_GETEVRREGS 20 | |
98 | #define PTRACE_SETEVRREGS 21 | |
99 | #endif | |
100 | ||
6ffbb7ab | 101 | /* Similarly for the hardware watchpoint support. These requests are used |
926bf92d | 102 | when the PowerPC HWDEBUG ptrace interface is not available. */ |
e0d24f8d WZ |
103 | #ifndef PTRACE_GET_DEBUGREG |
104 | #define PTRACE_GET_DEBUGREG 25 | |
105 | #endif | |
106 | #ifndef PTRACE_SET_DEBUGREG | |
107 | #define PTRACE_SET_DEBUGREG 26 | |
108 | #endif | |
109 | #ifndef PTRACE_GETSIGINFO | |
110 | #define PTRACE_GETSIGINFO 0x4202 | |
111 | #endif | |
01904826 | 112 | |
926bf92d UW |
113 | /* These requests are used when the PowerPC HWDEBUG ptrace interface is |
114 | available. It exposes the debug facilities of PowerPC processors, as well | |
115 | as additional features of BookE processors, such as ranged breakpoints and | |
116 | watchpoints and hardware-accelerated condition evaluation. */ | |
6ffbb7ab TJB |
117 | #ifndef PPC_PTRACE_GETHWDBGINFO |
118 | ||
926bf92d UW |
119 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG |
120 | ptrace interface is not present in ptrace.h, so we'll have to pretty much | |
121 | include it all here so that the code at least compiles on older systems. */ | |
6ffbb7ab TJB |
122 | #define PPC_PTRACE_GETHWDBGINFO 0x89 |
123 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
124 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
125 | ||
126 | struct ppc_debug_info | |
127 | { | |
0df8b418 | 128 | uint32_t version; /* Only version 1 exists to date. */ |
6ffbb7ab TJB |
129 | uint32_t num_instruction_bps; |
130 | uint32_t num_data_bps; | |
131 | uint32_t num_condition_regs; | |
132 | uint32_t data_bp_alignment; | |
0df8b418 | 133 | uint32_t sizeof_condition; /* size of the DVC register. */ |
6ffbb7ab TJB |
134 | uint64_t features; |
135 | }; | |
136 | ||
137 | /* Features will have bits indicating whether there is support for: */ | |
138 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
139 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
140 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
141 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
142 | ||
143 | struct ppc_hw_breakpoint | |
144 | { | |
145 | uint32_t version; /* currently, version must be 1 */ | |
146 | uint32_t trigger_type; /* only some combinations allowed */ | |
147 | uint32_t addr_mode; /* address match mode */ | |
148 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
149 | uint64_t addr; /* break/watchpoint address */ | |
150 | uint64_t addr2; /* range end or mask */ | |
151 | uint64_t condition_value; /* contents of the DVC register */ | |
152 | }; | |
153 | ||
154 | /* Trigger type. */ | |
155 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
156 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
157 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
158 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
159 | ||
160 | /* Address mode. */ | |
161 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
162 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
163 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
164 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
165 | ||
166 | /* Condition mode. */ | |
167 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
168 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
169 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
170 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
171 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
172 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
173 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
174 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
175 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) | |
176 | #endif /* PPC_PTRACE_GETHWDBGINFO */ | |
177 | ||
e23b9d6e UW |
178 | /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider |
179 | watchpoint (up to 512 bytes). */ | |
180 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR | |
181 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | |
182 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */ | |
6ffbb7ab | 183 | |
1dfe79e8 SDJ |
184 | /* Similarly for the general-purpose (gp0 -- gp31) |
185 | and floating-point registers (fp0 -- fp31). */ | |
186 | #ifndef PTRACE_GETREGS | |
187 | #define PTRACE_GETREGS 12 | |
188 | #endif | |
189 | #ifndef PTRACE_SETREGS | |
190 | #define PTRACE_SETREGS 13 | |
191 | #endif | |
192 | #ifndef PTRACE_GETFPREGS | |
193 | #define PTRACE_GETFPREGS 14 | |
194 | #endif | |
195 | #ifndef PTRACE_SETFPREGS | |
196 | #define PTRACE_SETFPREGS 15 | |
197 | #endif | |
198 | ||
9abe5450 EZ |
199 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
200 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
201 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
202 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
203 | flat array of chars, so that it is easier to manipulate for gdb. | |
204 | ||
205 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
206 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 207 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
208 | Appended to this there is space for the VRSAVE register: 4 bytes. |
209 | Even though this vrsave register is not included in the regset | |
210 | typedef, it is handled by the ptrace requests. | |
211 | ||
212 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
213 | therefore the offset at which the real value of the VSCR register | |
214 | is located will be always 12 bytes. | |
215 | ||
216 | The layout is like this (where x is the actual value of the vscr reg): */ | |
217 | ||
218 | /* *INDENT-OFF* */ | |
219 | /* | |
220 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
221 | <-------> <-------><-------><-> | |
222 | VR0 VR31 VSCR VRSAVE | |
223 | */ | |
224 | /* *INDENT-ON* */ | |
225 | ||
226 | #define SIZEOF_VRREGS 33*16+4 | |
227 | ||
228 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
229 | ||
604c2f83 LM |
230 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
231 | with the existing FPR and VMX registers. | |
232 | ||
233 | VSR doubleword 0 VSR doubleword 1 | |
234 | ---------------------------------------------------------------- | |
235 | VSR[0] | FPR[0] | | | |
236 | ---------------------------------------------------------------- | |
237 | VSR[1] | FPR[1] | | | |
238 | ---------------------------------------------------------------- | |
239 | | ... | | | |
240 | | ... | | | |
241 | ---------------------------------------------------------------- | |
242 | VSR[30] | FPR[30] | | | |
243 | ---------------------------------------------------------------- | |
244 | VSR[31] | FPR[31] | | | |
245 | ---------------------------------------------------------------- | |
246 | VSR[32] | VR[0] | | |
247 | ---------------------------------------------------------------- | |
248 | VSR[33] | VR[1] | | |
249 | ---------------------------------------------------------------- | |
250 | | ... | | |
251 | | ... | | |
252 | ---------------------------------------------------------------- | |
253 | VSR[62] | VR[30] | | |
254 | ---------------------------------------------------------------- | |
255 | VSR[63] | VR[31] | | |
256 | ---------------------------------------------------------------- | |
257 | ||
258 | VSX has 64 128bit registers. The first 32 registers overlap with | |
259 | the FP registers (doubleword 0) and hence extend them with additional | |
260 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
261 | registers. */ | |
262 | #define SIZEOF_VSXREGS 32*8 | |
263 | ||
264 | typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; | |
01904826 | 265 | |
b021a221 | 266 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 267 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
268 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
269 | ptrace calls only access the lower half of each register, to allow | |
270 | them to behave the same way they do on non-SPE systems. There's a | |
271 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
272 | read and write the top halves of all the general-purpose registers | |
273 | at once, along with some SPE-specific registers. | |
01904826 JB |
274 | |
275 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 276 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 277 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
278 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
279 | bottom halves together. | |
01904826 JB |
280 | |
281 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
282 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
283 | struct gdb_evrregset_t | |
284 | { | |
285 | unsigned long evr[32]; | |
286 | unsigned long long acc; | |
287 | unsigned long spefscr; | |
288 | }; | |
289 | ||
604c2f83 LM |
290 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
291 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
292 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
293 | gotten an error. Note that VSX registers 32 through 63 overlap | |
294 | with VR registers 0 through 31. */ | |
295 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
296 | |
297 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
298 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
299 | registers. Zero if we've tried one of them and gotten an | |
300 | error. */ | |
9abe5450 EZ |
301 | int have_ptrace_getvrregs = 1; |
302 | ||
01904826 JB |
303 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
304 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
305 | registers. Zero if we've tried one of them and gotten an | |
306 | error. */ | |
307 | int have_ptrace_getsetevrregs = 1; | |
308 | ||
1dfe79e8 SDJ |
309 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
310 | PTRACE_SETREGS requests, for reading and writing the | |
311 | general-purpose registers. Zero if we've tried one of | |
312 | them and gotten an error. */ | |
313 | int have_ptrace_getsetregs = 1; | |
314 | ||
315 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
316 | PTRACE_SETFPREGS requests, for reading and writing the | |
317 | floating-pointers registers. Zero if we've tried one of | |
318 | them and gotten an error. */ | |
319 | int have_ptrace_getsetfpregs = 1; | |
320 | ||
16333c4f EZ |
321 | /* *INDENT-OFF* */ |
322 | /* registers layout, as presented by the ptrace interface: | |
323 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
324 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
325 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
326 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
327 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
328 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
329 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
330 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
331 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
332 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
333 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
334 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f EZ |
335 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
336 | /* *INDENT_ON * */ | |
c877c8e6 | 337 | |
45229ea4 | 338 | static int |
e101270f | 339 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 340 | { |
16333c4f | 341 | int u_addr = -1; |
e101270f | 342 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
343 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
344 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 345 | int wordsize = sizeof (long); |
16333c4f | 346 | |
0df8b418 | 347 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
348 | if (regno >= tdep->ppc_gp0_regnum |
349 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 350 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 351 | |
49ff75ad JB |
352 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
353 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
354 | slot each in 64-bit interface. */ | |
383f0f5b JB |
355 | if (tdep->ppc_fp0_regnum >= 0 |
356 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
357 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
358 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 359 | |
0df8b418 | 360 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 361 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 362 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 363 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 364 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 365 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 366 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 367 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 368 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 369 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 370 | u_addr = PT_CTR * wordsize; |
f8c59253 | 371 | #ifdef PT_MQ |
dc5cfeb6 | 372 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 373 | u_addr = PT_MQ * wordsize; |
f8c59253 | 374 | #endif |
dc5cfeb6 | 375 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 376 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
377 | if (regno == PPC_ORIG_R3_REGNUM) |
378 | u_addr = PT_ORIG_R3 * wordsize; | |
379 | if (regno == PPC_TRAP_REGNUM) | |
380 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
381 | if (tdep->ppc_fpscr_regnum >= 0 |
382 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
383 | { |
384 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
385 | kernel headers incorrectly contained the 32-bit definition of | |
386 | PT_FPSCR. For the 32-bit definition, floating-point | |
387 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 388 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
389 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
390 | hence no adjustment is necessary. Hack around this. */ | |
391 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
392 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
393 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
394 | slot and not just its second word. The PT_FPSCR supplied when | |
395 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
396 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
397 | && PT_FPSCR == (48 + 2*32 + 1)) | |
398 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
399 | else |
400 | u_addr = PT_FPSCR * wordsize; | |
401 | } | |
16333c4f | 402 | return u_addr; |
c877c8e6 KB |
403 | } |
404 | ||
604c2f83 LM |
405 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
406 | registers set mechanism, as opposed to the interface for all the | |
407 | other registers, that stores/fetches each register individually. */ | |
408 | static void | |
409 | fetch_vsx_register (struct regcache *regcache, int tid, int regno) | |
410 | { | |
411 | int ret; | |
412 | gdb_vsxregset_t regs; | |
413 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
414 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
415 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
416 | ||
417 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
418 | if (ret < 0) | |
419 | { | |
420 | if (errno == EIO) | |
421 | { | |
422 | have_ptrace_getsetvsxregs = 0; | |
423 | return; | |
424 | } | |
425 | perror_with_name (_("Unable to fetch VSX register")); | |
426 | } | |
427 | ||
428 | regcache_raw_supply (regcache, regno, | |
429 | regs + (regno - tdep->ppc_vsr0_upper_regnum) | |
430 | * vsxregsize); | |
431 | } | |
432 | ||
9abe5450 EZ |
433 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
434 | registers set mechanism, as opposed to the interface for all the | |
435 | other registers, that stores/fetches each register individually. */ | |
436 | static void | |
56be3814 | 437 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
438 | { |
439 | int ret; | |
440 | int offset = 0; | |
441 | gdb_vrregset_t regs; | |
40a6adc1 MD |
442 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
443 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
444 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
445 | |
446 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
447 | if (ret < 0) | |
448 | { | |
449 | if (errno == EIO) | |
450 | { | |
451 | have_ptrace_getvrregs = 0; | |
452 | return; | |
453 | } | |
e2e0b3e5 | 454 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
455 | } |
456 | ||
457 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
458 | long on the hardware. We deal only with the lower 4 bytes of the | |
459 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
460 | there is no need to define an offset for it. */ | |
461 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 462 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 463 | |
56be3814 | 464 | regcache_raw_supply (regcache, regno, |
0df8b418 MS |
465 | regs + (regno |
466 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
467 | } |
468 | ||
01904826 JB |
469 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
470 | SPE-specific registers, and place the results in EVRREGSET. If we | |
471 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
472 | zeros. | |
473 | ||
474 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
475 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
476 | set_spe_registers. */ | |
477 | static void | |
478 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
479 | { | |
480 | if (have_ptrace_getsetevrregs) | |
481 | { | |
482 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
483 | return; | |
484 | else | |
485 | { | |
486 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
487 | we just return zeros. */ | |
488 | if (errno == EIO) | |
489 | have_ptrace_getsetevrregs = 0; | |
490 | else | |
491 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 492 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
493 | } |
494 | } | |
495 | ||
496 | memset (evrregset, 0, sizeof (*evrregset)); | |
497 | } | |
498 | ||
6ced10dd JB |
499 | /* Supply values from TID for SPE-specific raw registers: the upper |
500 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
501 | be the number of an upper half register, acc, spefscr, or -1 to | |
502 | supply the values of all registers. */ | |
01904826 | 503 | static void |
56be3814 | 504 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 505 | { |
40a6adc1 MD |
506 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
507 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
508 | struct gdb_evrregset_t evrregs; |
509 | ||
6ced10dd | 510 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 511 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 512 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 513 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 514 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 515 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 516 | |
01904826 JB |
517 | get_spe_registers (tid, &evrregs); |
518 | ||
6ced10dd | 519 | if (regno == -1) |
01904826 | 520 | { |
6ced10dd JB |
521 | int i; |
522 | ||
523 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 524 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 525 | &evrregs.evr[i]); |
01904826 | 526 | } |
6ced10dd JB |
527 | else if (tdep->ppc_ev0_upper_regnum <= regno |
528 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 529 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
530 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
531 | ||
532 | if (regno == -1 | |
533 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 534 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
535 | |
536 | if (regno == -1 | |
537 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 538 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 539 | &evrregs.spefscr); |
01904826 JB |
540 | } |
541 | ||
45229ea4 | 542 | static void |
56be3814 | 543 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 544 | { |
40a6adc1 MD |
545 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
546 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 547 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 548 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 549 | int bytes_transferred; |
0df8b418 | 550 | unsigned int offset; /* Offset of registers within the u area. */ |
e362b510 | 551 | gdb_byte buf[MAX_REGISTER_SIZE]; |
45229ea4 | 552 | |
be8626e0 | 553 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
554 | { |
555 | /* If this is the first time through, or if it is not the first | |
556 | time through, and we have comfirmed that there is kernel | |
557 | support for such a ptrace request, then go and fetch the | |
558 | register. */ | |
559 | if (have_ptrace_getvrregs) | |
560 | { | |
56be3814 | 561 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
562 | return; |
563 | } | |
564 | /* If we have discovered that there is no ptrace support for | |
565 | AltiVec registers, fall through and return zeroes, because | |
566 | regaddr will be -1 in this case. */ | |
567 | } | |
604c2f83 LM |
568 | if (vsx_register_p (gdbarch, regno)) |
569 | { | |
570 | if (have_ptrace_getsetvsxregs) | |
571 | { | |
572 | fetch_vsx_register (regcache, tid, regno); | |
573 | return; | |
574 | } | |
575 | } | |
be8626e0 | 576 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 577 | { |
56be3814 | 578 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
579 | return; |
580 | } | |
9abe5450 | 581 | |
45229ea4 EZ |
582 | if (regaddr == -1) |
583 | { | |
40a6adc1 | 584 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 585 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
586 | return; |
587 | } | |
588 | ||
411cb3f9 | 589 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
590 | 32-bit platform, 64-bit floating-point registers will require two |
591 | transfers. */ | |
4a19ea35 | 592 | for (bytes_transferred = 0; |
40a6adc1 | 593 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 594 | bytes_transferred += sizeof (long)) |
45229ea4 | 595 | { |
11fde611 JK |
596 | long l; |
597 | ||
45229ea4 | 598 | errno = 0; |
11fde611 | 599 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 600 | regaddr += sizeof (long); |
45229ea4 EZ |
601 | if (errno != 0) |
602 | { | |
bc97b3ba | 603 | char message[128]; |
8c042590 PM |
604 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
605 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 606 | perror_with_name (message); |
45229ea4 | 607 | } |
11fde611 | 608 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 609 | } |
56d0d96a | 610 | |
4a19ea35 JB |
611 | /* Now supply the register. Keep in mind that the regcache's idea |
612 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 613 | (long). */ |
40a6adc1 | 614 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
615 | { |
616 | /* Little-endian values are always found at the left end of the | |
617 | bytes transferred. */ | |
56be3814 | 618 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 | 619 | } |
40a6adc1 | 620 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
621 | { |
622 | /* Big-endian values are found at the right end of the bytes | |
623 | transferred. */ | |
40a6adc1 | 624 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
56be3814 | 625 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
626 | } |
627 | else | |
a44bddec | 628 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 629 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 630 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
631 | } |
632 | ||
604c2f83 LM |
633 | static void |
634 | supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
635 | { | |
636 | int i; | |
637 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
638 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
639 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
640 | ||
641 | for (i = 0; i < ppc_num_vshrs; i++) | |
642 | { | |
643 | regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
644 | *vsxregsetp + i * vsxregsize); | |
645 | } | |
646 | } | |
647 | ||
9abe5450 | 648 | static void |
56be3814 | 649 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
650 | { |
651 | int i; | |
40a6adc1 MD |
652 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
653 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 654 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
655 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
656 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
657 | |
658 | for (i = 0; i < num_of_vrregs; i++) | |
659 | { | |
660 | /* The last 2 registers of this set are only 32 bit long, not | |
661 | 128. However an offset is necessary only for VSCR because it | |
662 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
663 | slot. */ | |
664 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 665 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 666 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 667 | else |
56be3814 | 668 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 669 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
670 | } |
671 | } | |
672 | ||
604c2f83 LM |
673 | static void |
674 | fetch_vsx_registers (struct regcache *regcache, int tid) | |
675 | { | |
676 | int ret; | |
677 | gdb_vsxregset_t regs; | |
678 | ||
679 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
680 | if (ret < 0) | |
681 | { | |
682 | if (errno == EIO) | |
683 | { | |
684 | have_ptrace_getsetvsxregs = 0; | |
685 | return; | |
686 | } | |
687 | perror_with_name (_("Unable to fetch VSX registers")); | |
688 | } | |
689 | supply_vsxregset (regcache, ®s); | |
690 | } | |
691 | ||
9abe5450 | 692 | static void |
56be3814 | 693 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
694 | { |
695 | int ret; | |
696 | gdb_vrregset_t regs; | |
697 | ||
698 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
699 | if (ret < 0) | |
700 | { | |
701 | if (errno == EIO) | |
702 | { | |
703 | have_ptrace_getvrregs = 0; | |
704 | return; | |
705 | } | |
e2e0b3e5 | 706 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 707 | } |
56be3814 | 708 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
709 | } |
710 | ||
1dfe79e8 SDJ |
711 | /* This function actually issues the request to ptrace, telling |
712 | it to get all general-purpose registers and put them into the | |
713 | specified regset. | |
714 | ||
715 | If the ptrace request does not exist, this function returns 0 | |
716 | and properly sets the have_ptrace_* flag. If the request fails, | |
717 | this function calls perror_with_name. Otherwise, if the request | |
718 | succeeds, then the regcache gets filled and 1 is returned. */ | |
719 | static int | |
720 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
721 | { | |
722 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
723 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
724 | gdb_gregset_t gregset; | |
725 | ||
726 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
727 | { | |
728 | if (errno == EIO) | |
729 | { | |
730 | have_ptrace_getsetregs = 0; | |
731 | return 0; | |
732 | } | |
733 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
734 | } | |
735 | ||
736 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
737 | ||
738 | return 1; | |
739 | } | |
740 | ||
741 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
742 | responsible for verifying if this target has the ptrace request | |
743 | that can be used to fetch all general-purpose registers at one | |
744 | shot. If it doesn't, then we should fetch them using the | |
745 | old-fashioned way, which is to iterate over the registers and | |
746 | request them one by one. */ | |
747 | static void | |
748 | fetch_gp_regs (struct regcache *regcache, int tid) | |
749 | { | |
750 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
751 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
752 | int i; | |
753 | ||
754 | if (have_ptrace_getsetregs) | |
755 | if (fetch_all_gp_regs (regcache, tid)) | |
756 | return; | |
757 | ||
758 | /* If we've hit this point, it doesn't really matter which | |
759 | architecture we are using. We just need to read the | |
760 | registers in the "old-fashioned way". */ | |
761 | for (i = 0; i < ppc_num_gprs; i++) | |
762 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
763 | } | |
764 | ||
765 | /* This function actually issues the request to ptrace, telling | |
766 | it to get all floating-point registers and put them into the | |
767 | specified regset. | |
768 | ||
769 | If the ptrace request does not exist, this function returns 0 | |
770 | and properly sets the have_ptrace_* flag. If the request fails, | |
771 | this function calls perror_with_name. Otherwise, if the request | |
772 | succeeds, then the regcache gets filled and 1 is returned. */ | |
773 | static int | |
774 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
775 | { | |
776 | gdb_fpregset_t fpregs; | |
777 | ||
778 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
779 | { | |
780 | if (errno == EIO) | |
781 | { | |
782 | have_ptrace_getsetfpregs = 0; | |
783 | return 0; | |
784 | } | |
785 | perror_with_name (_("Couldn't get floating-point registers.")); | |
786 | } | |
787 | ||
788 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
789 | ||
790 | return 1; | |
791 | } | |
792 | ||
793 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
794 | responsible for verifying if this target has the ptrace request | |
795 | that can be used to fetch all floating-point registers at one | |
796 | shot. If it doesn't, then we should fetch them using the | |
797 | old-fashioned way, which is to iterate over the registers and | |
798 | request them one by one. */ | |
799 | static void | |
800 | fetch_fp_regs (struct regcache *regcache, int tid) | |
801 | { | |
802 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
803 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
804 | int i; | |
805 | ||
806 | if (have_ptrace_getsetfpregs) | |
807 | if (fetch_all_fp_regs (regcache, tid)) | |
808 | return; | |
809 | ||
810 | /* If we've hit this point, it doesn't really matter which | |
811 | architecture we are using. We just need to read the | |
812 | registers in the "old-fashioned way". */ | |
813 | for (i = 0; i < ppc_num_fprs; i++) | |
814 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
815 | } | |
816 | ||
45229ea4 | 817 | static void |
56be3814 | 818 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
819 | { |
820 | int i; | |
40a6adc1 MD |
821 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
822 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 823 | |
1dfe79e8 | 824 | fetch_gp_regs (regcache, tid); |
32b99774 | 825 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 826 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 827 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 828 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 829 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 830 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 831 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 832 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 833 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 834 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 835 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 836 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 837 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 838 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 839 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
840 | if (ppc_linux_trap_reg_p (gdbarch)) |
841 | { | |
842 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
843 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
844 | } | |
32b99774 | 845 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 846 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
847 | if (have_ptrace_getvrregs) |
848 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 849 | fetch_altivec_registers (regcache, tid); |
604c2f83 LM |
850 | if (have_ptrace_getsetvsxregs) |
851 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
852 | fetch_vsx_registers (regcache, tid); | |
6ced10dd | 853 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 854 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
855 | } |
856 | ||
857 | /* Fetch registers from the child process. Fetch all registers if | |
858 | regno == -1, otherwise fetch all general registers or all floating | |
859 | point registers depending upon the value of regno. */ | |
10d6c8cd | 860 | static void |
28439f5e PA |
861 | ppc_linux_fetch_inferior_registers (struct target_ops *ops, |
862 | struct regcache *regcache, int regno) | |
45229ea4 | 863 | { |
0df8b418 | 864 | /* Overload thread id onto process id. */ |
dfd4cc63 | 865 | int tid = ptid_get_lwp (inferior_ptid); |
05f13b9c | 866 | |
0df8b418 | 867 | /* No thread id, just use process id. */ |
05f13b9c | 868 | if (tid == 0) |
dfd4cc63 | 869 | tid = ptid_get_pid (inferior_ptid); |
05f13b9c | 870 | |
9abe5450 | 871 | if (regno == -1) |
56be3814 | 872 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 873 | else |
56be3814 | 874 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
875 | } |
876 | ||
0df8b418 | 877 | /* Store one VSX register. */ |
604c2f83 LM |
878 | static void |
879 | store_vsx_register (const struct regcache *regcache, int tid, int regno) | |
880 | { | |
881 | int ret; | |
882 | gdb_vsxregset_t regs; | |
883 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
884 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
885 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
886 | ||
9fe70b4f | 887 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
888 | if (ret < 0) |
889 | { | |
890 | if (errno == EIO) | |
891 | { | |
892 | have_ptrace_getsetvsxregs = 0; | |
893 | return; | |
894 | } | |
895 | perror_with_name (_("Unable to fetch VSX register")); | |
896 | } | |
897 | ||
898 | regcache_raw_collect (regcache, regno, regs + | |
899 | (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); | |
900 | ||
901 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
902 | if (ret < 0) | |
903 | perror_with_name (_("Unable to store VSX register")); | |
904 | } | |
905 | ||
0df8b418 | 906 | /* Store one register. */ |
9abe5450 | 907 | static void |
56be3814 | 908 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
909 | { |
910 | int ret; | |
911 | int offset = 0; | |
912 | gdb_vrregset_t regs; | |
40a6adc1 MD |
913 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
914 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
915 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
916 | |
917 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
918 | if (ret < 0) | |
919 | { | |
920 | if (errno == EIO) | |
921 | { | |
922 | have_ptrace_getvrregs = 0; | |
923 | return; | |
924 | } | |
e2e0b3e5 | 925 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
926 | } |
927 | ||
928 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
929 | long on the hardware. */ | |
930 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 931 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 932 | |
56be3814 | 933 | regcache_raw_collect (regcache, regno, |
0df8b418 MS |
934 | regs + (regno |
935 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
936 | |
937 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
938 | if (ret < 0) | |
e2e0b3e5 | 939 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
940 | } |
941 | ||
01904826 JB |
942 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
943 | general-purpose registers and its SPE-specific registers to the | |
944 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
945 | nothing. | |
946 | ||
947 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
948 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
949 | get_spe_registers. */ | |
950 | static void | |
951 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
952 | { | |
953 | if (have_ptrace_getsetevrregs) | |
954 | { | |
955 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
956 | return; | |
957 | else | |
958 | { | |
959 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
960 | supported; we fail silently, and don't try the call | |
961 | again. */ | |
962 | if (errno == EIO) | |
963 | have_ptrace_getsetevrregs = 0; | |
964 | else | |
965 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 966 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
967 | } |
968 | } | |
969 | } | |
970 | ||
6ced10dd JB |
971 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
972 | If REGNO is -1, write the values of all the SPE-specific | |
973 | registers. */ | |
01904826 | 974 | static void |
56be3814 | 975 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 976 | { |
40a6adc1 MD |
977 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
978 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
979 | struct gdb_evrregset_t evrregs; |
980 | ||
6ced10dd | 981 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 982 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 983 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 984 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 985 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 986 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 987 | |
6ced10dd JB |
988 | if (regno == -1) |
989 | /* Since we're going to write out every register, the code below | |
990 | should store to every field of evrregs; if that doesn't happen, | |
991 | make it obvious by initializing it with suspicious values. */ | |
992 | memset (&evrregs, 42, sizeof (evrregs)); | |
993 | else | |
994 | /* We can only read and write the entire EVR register set at a | |
995 | time, so to write just a single register, we do a | |
996 | read-modify-write maneuver. */ | |
997 | get_spe_registers (tid, &evrregs); | |
998 | ||
999 | if (regno == -1) | |
01904826 | 1000 | { |
6ced10dd JB |
1001 | int i; |
1002 | ||
1003 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 1004 | regcache_raw_collect (regcache, |
6ced10dd JB |
1005 | tdep->ppc_ev0_upper_regnum + i, |
1006 | &evrregs.evr[i]); | |
01904826 | 1007 | } |
6ced10dd JB |
1008 | else if (tdep->ppc_ev0_upper_regnum <= regno |
1009 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 1010 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
1011 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
1012 | ||
1013 | if (regno == -1 | |
1014 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 1015 | regcache_raw_collect (regcache, |
6ced10dd JB |
1016 | tdep->ppc_acc_regnum, |
1017 | &evrregs.acc); | |
1018 | ||
1019 | if (regno == -1 | |
1020 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 1021 | regcache_raw_collect (regcache, |
6ced10dd JB |
1022 | tdep->ppc_spefscr_regnum, |
1023 | &evrregs.spefscr); | |
01904826 JB |
1024 | |
1025 | /* Write back the modified register set. */ | |
1026 | set_spe_registers (tid, &evrregs); | |
1027 | } | |
1028 | ||
45229ea4 | 1029 | static void |
56be3814 | 1030 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1031 | { |
40a6adc1 MD |
1032 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1033 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 1034 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 1035 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 1036 | int i; |
4a19ea35 | 1037 | size_t bytes_to_transfer; |
e362b510 | 1038 | gdb_byte buf[MAX_REGISTER_SIZE]; |
45229ea4 | 1039 | |
be8626e0 | 1040 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 1041 | { |
56be3814 | 1042 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
1043 | return; |
1044 | } | |
604c2f83 LM |
1045 | if (vsx_register_p (gdbarch, regno)) |
1046 | { | |
1047 | store_vsx_register (regcache, tid, regno); | |
1048 | return; | |
1049 | } | |
be8626e0 | 1050 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 1051 | { |
56be3814 | 1052 | store_spe_register (regcache, tid, regno); |
01904826 JB |
1053 | return; |
1054 | } | |
45229ea4 | 1055 | |
9abe5450 EZ |
1056 | if (regaddr == -1) |
1057 | return; | |
1058 | ||
4a19ea35 JB |
1059 | /* First collect the register. Keep in mind that the regcache's |
1060 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1061 | (long). */ |
56d0d96a | 1062 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
1063 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
1064 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
1065 | { |
1066 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 1067 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 1068 | } |
40a6adc1 | 1069 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1070 | { |
1071 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 1072 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
56be3814 | 1073 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
1074 | } |
1075 | ||
411cb3f9 | 1076 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 1077 | { |
11fde611 JK |
1078 | long l; |
1079 | ||
1080 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 1081 | errno = 0; |
11fde611 | 1082 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 1083 | regaddr += sizeof (long); |
e3f36dbd KB |
1084 | |
1085 | if (errno == EIO | |
7284e1be UW |
1086 | && (regno == tdep->ppc_fpscr_regnum |
1087 | || regno == PPC_ORIG_R3_REGNUM | |
1088 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1089 | { |
7284e1be UW |
1090 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1091 | or trap to be written. */ | |
e3f36dbd KB |
1092 | continue; |
1093 | } | |
1094 | ||
45229ea4 EZ |
1095 | if (errno != 0) |
1096 | { | |
bc97b3ba | 1097 | char message[128]; |
8c042590 PM |
1098 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
1099 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 1100 | perror_with_name (message); |
45229ea4 EZ |
1101 | } |
1102 | } | |
1103 | } | |
1104 | ||
604c2f83 LM |
1105 | static void |
1106 | fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
1107 | { | |
1108 | int i; | |
1109 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1110 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1111 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
1112 | ||
1113 | for (i = 0; i < ppc_num_vshrs; i++) | |
1114 | regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
1115 | *vsxregsetp + i * vsxregsize); | |
1116 | } | |
1117 | ||
9abe5450 | 1118 | static void |
56be3814 | 1119 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
1120 | { |
1121 | int i; | |
40a6adc1 MD |
1122 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1123 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 1124 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
1125 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
1126 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
1127 | |
1128 | for (i = 0; i < num_of_vrregs; i++) | |
1129 | { | |
1130 | /* The last 2 registers of this set are only 32 bit long, not | |
1131 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
1132 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 1133 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1134 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 1135 | else |
56be3814 | 1136 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1137 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
1138 | } |
1139 | } | |
1140 | ||
604c2f83 LM |
1141 | static void |
1142 | store_vsx_registers (const struct regcache *regcache, int tid) | |
1143 | { | |
1144 | int ret; | |
1145 | gdb_vsxregset_t regs; | |
1146 | ||
1147 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
1148 | if (ret < 0) | |
1149 | { | |
1150 | if (errno == EIO) | |
1151 | { | |
1152 | have_ptrace_getsetvsxregs = 0; | |
1153 | return; | |
1154 | } | |
1155 | perror_with_name (_("Couldn't get VSX registers")); | |
1156 | } | |
1157 | ||
1158 | fill_vsxregset (regcache, ®s); | |
1159 | ||
1160 | if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) | |
1161 | perror_with_name (_("Couldn't write VSX registers")); | |
1162 | } | |
1163 | ||
9abe5450 | 1164 | static void |
56be3814 | 1165 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
1166 | { |
1167 | int ret; | |
1168 | gdb_vrregset_t regs; | |
1169 | ||
0897f59b | 1170 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
1171 | if (ret < 0) |
1172 | { | |
1173 | if (errno == EIO) | |
1174 | { | |
1175 | have_ptrace_getvrregs = 0; | |
1176 | return; | |
1177 | } | |
e2e0b3e5 | 1178 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
1179 | } |
1180 | ||
56be3814 | 1181 | fill_vrregset (regcache, ®s); |
9abe5450 | 1182 | |
0897f59b | 1183 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 1184 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
1185 | } |
1186 | ||
1dfe79e8 SDJ |
1187 | /* This function actually issues the request to ptrace, telling |
1188 | it to store all general-purpose registers present in the specified | |
1189 | regset. | |
1190 | ||
1191 | If the ptrace request does not exist, this function returns 0 | |
1192 | and properly sets the have_ptrace_* flag. If the request fails, | |
1193 | this function calls perror_with_name. Otherwise, if the request | |
1194 | succeeds, then the regcache is stored and 1 is returned. */ | |
1195 | static int | |
1196 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1197 | { | |
1198 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1199 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1200 | gdb_gregset_t gregset; | |
1201 | ||
1202 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1203 | { | |
1204 | if (errno == EIO) | |
1205 | { | |
1206 | have_ptrace_getsetregs = 0; | |
1207 | return 0; | |
1208 | } | |
1209 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1210 | } | |
1211 | ||
1212 | fill_gregset (regcache, &gregset, regno); | |
1213 | ||
1214 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1215 | { | |
1216 | if (errno == EIO) | |
1217 | { | |
1218 | have_ptrace_getsetregs = 0; | |
1219 | return 0; | |
1220 | } | |
1221 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1222 | } | |
1223 | ||
1224 | return 1; | |
1225 | } | |
1226 | ||
1227 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1228 | responsible for verifying if this target has the ptrace request | |
1229 | that can be used to store all general-purpose registers at one | |
1230 | shot. If it doesn't, then we should store them using the | |
1231 | old-fashioned way, which is to iterate over the registers and | |
1232 | store them one by one. */ | |
45229ea4 | 1233 | static void |
1dfe79e8 | 1234 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1235 | { |
40a6adc1 MD |
1236 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1237 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dfe79e8 SDJ |
1238 | int i; |
1239 | ||
1240 | if (have_ptrace_getsetregs) | |
1241 | if (store_all_gp_regs (regcache, tid, regno)) | |
1242 | return; | |
1243 | ||
1244 | /* If we hit this point, it doesn't really matter which | |
1245 | architecture we are using. We just need to store the | |
1246 | registers in the "old-fashioned way". */ | |
6ced10dd | 1247 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1248 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1249 | } |
1250 | ||
1251 | /* This function actually issues the request to ptrace, telling | |
1252 | it to store all floating-point registers present in the specified | |
1253 | regset. | |
1254 | ||
1255 | If the ptrace request does not exist, this function returns 0 | |
1256 | and properly sets the have_ptrace_* flag. If the request fails, | |
1257 | this function calls perror_with_name. Otherwise, if the request | |
1258 | succeeds, then the regcache is stored and 1 is returned. */ | |
1259 | static int | |
1260 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1261 | { | |
1262 | gdb_fpregset_t fpregs; | |
1263 | ||
1264 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1265 | { | |
1266 | if (errno == EIO) | |
1267 | { | |
1268 | have_ptrace_getsetfpregs = 0; | |
1269 | return 0; | |
1270 | } | |
1271 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1272 | } | |
1273 | ||
1274 | fill_fpregset (regcache, &fpregs, regno); | |
1275 | ||
1276 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1277 | { | |
1278 | if (errno == EIO) | |
1279 | { | |
1280 | have_ptrace_getsetfpregs = 0; | |
1281 | return 0; | |
1282 | } | |
1283 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1284 | } | |
1285 | ||
1286 | return 1; | |
1287 | } | |
1288 | ||
1289 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1290 | responsible for verifying if this target has the ptrace request | |
1291 | that can be used to store all floating-point registers at one | |
1292 | shot. If it doesn't, then we should store them using the | |
1293 | old-fashioned way, which is to iterate over the registers and | |
1294 | store them one by one. */ | |
1295 | static void | |
1296 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1297 | { | |
1298 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1299 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1300 | int i; | |
1301 | ||
1302 | if (have_ptrace_getsetfpregs) | |
1303 | if (store_all_fp_regs (regcache, tid, regno)) | |
1304 | return; | |
1305 | ||
1306 | /* If we hit this point, it doesn't really matter which | |
1307 | architecture we are using. We just need to store the | |
1308 | registers in the "old-fashioned way". */ | |
1309 | for (i = 0; i < ppc_num_fprs; i++) | |
1310 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1311 | } | |
1312 | ||
1313 | static void | |
1314 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1315 | { | |
1316 | int i; | |
1317 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1318 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1319 | ||
1320 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1321 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1322 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1323 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1324 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1325 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1326 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1327 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1328 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1329 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1330 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1331 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1332 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1333 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1334 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1335 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1336 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1337 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1338 | if (ppc_linux_trap_reg_p (gdbarch)) |
1339 | { | |
1340 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1341 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1342 | } | |
9abe5450 EZ |
1343 | if (have_ptrace_getvrregs) |
1344 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 1345 | store_altivec_registers (regcache, tid); |
604c2f83 LM |
1346 | if (have_ptrace_getsetvsxregs) |
1347 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
1348 | store_vsx_registers (regcache, tid); | |
6ced10dd | 1349 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1350 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
1351 | } |
1352 | ||
6ffbb7ab | 1353 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
b261e0c5 UW |
1354 | static unsigned long |
1355 | ppc_linux_get_hwcap (void) | |
6ffbb7ab TJB |
1356 | { |
1357 | CORE_ADDR field; | |
1358 | ||
1359 | if (target_auxv_search (¤t_target, AT_HWCAP, &field)) | |
1360 | return (unsigned long) field; | |
1361 | ||
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | /* The cached DABR value, to install in new threads. | |
926bf92d UW |
1366 | This variable is used when the PowerPC HWDEBUG ptrace |
1367 | interface is not available. */ | |
6ffbb7ab TJB |
1368 | static long saved_dabr_value; |
1369 | ||
1370 | /* Global structure that will store information about the available | |
926bf92d UW |
1371 | features provided by the PowerPC HWDEBUG ptrace interface. */ |
1372 | static struct ppc_debug_info hwdebug_info; | |
6ffbb7ab TJB |
1373 | |
1374 | /* Global variable that holds the maximum number of slots that the | |
926bf92d UW |
1375 | kernel will use. This is only used when PowerPC HWDEBUG ptrace interface |
1376 | is available. */ | |
6ffbb7ab TJB |
1377 | static size_t max_slots_number = 0; |
1378 | ||
1379 | struct hw_break_tuple | |
1380 | { | |
1381 | long slot; | |
1382 | struct ppc_hw_breakpoint *hw_break; | |
1383 | }; | |
1384 | ||
1385 | /* This is an internal VEC created to store information about *points inserted | |
926bf92d UW |
1386 | for each thread. This is used when PowerPC HWDEBUG ptrace interface is |
1387 | available. */ | |
6ffbb7ab TJB |
1388 | typedef struct thread_points |
1389 | { | |
1390 | /* The TID to which this *point relates. */ | |
1391 | int tid; | |
1392 | /* Information about the *point, such as its address, type, etc. | |
1393 | ||
1394 | Each element inside this vector corresponds to a hardware | |
1395 | breakpoint or watchpoint in the thread represented by TID. The maximum | |
1396 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of | |
1397 | the tuple is NULL, then the position in the vector is free. */ | |
1398 | struct hw_break_tuple *hw_breaks; | |
1399 | } *thread_points_p; | |
1400 | DEF_VEC_P (thread_points_p); | |
1401 | ||
1402 | VEC(thread_points_p) *ppc_threads = NULL; | |
1403 | ||
926bf92d UW |
1404 | /* The version of the PowerPC HWDEBUG kernel interface that we will use, if |
1405 | available. */ | |
6ffbb7ab TJB |
1406 | #define PPC_DEBUG_CURRENT_VERSION 1 |
1407 | ||
926bf92d | 1408 | /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */ |
e0d24f8d | 1409 | static int |
926bf92d | 1410 | have_ptrace_hwdebug_interface (void) |
e0d24f8d | 1411 | { |
926bf92d | 1412 | static int have_ptrace_hwdebug_interface = -1; |
e0d24f8d | 1413 | |
926bf92d | 1414 | if (have_ptrace_hwdebug_interface == -1) |
6ffbb7ab TJB |
1415 | { |
1416 | int tid; | |
e0d24f8d | 1417 | |
dfd4cc63 | 1418 | tid = ptid_get_lwp (inferior_ptid); |
6ffbb7ab | 1419 | if (tid == 0) |
dfd4cc63 | 1420 | tid = ptid_get_pid (inferior_ptid); |
e0d24f8d | 1421 | |
926bf92d UW |
1422 | /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ |
1423 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) | |
6ffbb7ab | 1424 | { |
926bf92d | 1425 | /* Check whether PowerPC HWDEBUG ptrace interface is functional and |
0c56f59b | 1426 | provides any supported feature. */ |
926bf92d | 1427 | if (hwdebug_info.features != 0) |
0c56f59b | 1428 | { |
926bf92d UW |
1429 | have_ptrace_hwdebug_interface = 1; |
1430 | max_slots_number = hwdebug_info.num_instruction_bps | |
1431 | + hwdebug_info.num_data_bps | |
1432 | + hwdebug_info.num_condition_regs; | |
1433 | return have_ptrace_hwdebug_interface; | |
0c56f59b | 1434 | } |
6ffbb7ab | 1435 | } |
926bf92d UW |
1436 | /* Old school interface and no PowerPC HWDEBUG ptrace support. */ |
1437 | have_ptrace_hwdebug_interface = 0; | |
1438 | memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info)); | |
6ffbb7ab TJB |
1439 | } |
1440 | ||
926bf92d | 1441 | return have_ptrace_hwdebug_interface; |
e0d24f8d WZ |
1442 | } |
1443 | ||
6ffbb7ab | 1444 | static int |
5461485a TT |
1445 | ppc_linux_can_use_hw_breakpoint (struct target_ops *self, |
1446 | int type, int cnt, int ot) | |
b7622095 | 1447 | { |
6ffbb7ab | 1448 | int total_hw_wp, total_hw_bp; |
b7622095 | 1449 | |
926bf92d | 1450 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab | 1451 | { |
926bf92d UW |
1452 | /* When PowerPC HWDEBUG ptrace interface is available, the number of |
1453 | available hardware watchpoints and breakpoints is stored at the | |
1454 | hwdebug_info struct. */ | |
1455 | total_hw_bp = hwdebug_info.num_instruction_bps; | |
1456 | total_hw_wp = hwdebug_info.num_data_bps; | |
6ffbb7ab TJB |
1457 | } |
1458 | else | |
1459 | { | |
926bf92d UW |
1460 | /* When we do not have PowerPC HWDEBUG ptrace interface, we should |
1461 | consider having 1 hardware watchpoint and no hardware breakpoints. */ | |
6ffbb7ab TJB |
1462 | total_hw_bp = 0; |
1463 | total_hw_wp = 1; | |
1464 | } | |
b7622095 | 1465 | |
6ffbb7ab TJB |
1466 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
1467 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
1468 | { | |
bb08bdbd | 1469 | if (cnt + ot > total_hw_wp) |
6ffbb7ab TJB |
1470 | return -1; |
1471 | } | |
1472 | else if (type == bp_hardware_breakpoint) | |
1473 | { | |
572f6555 EBM |
1474 | if (total_hw_bp == 0) |
1475 | { | |
1476 | /* No hardware breakpoint support. */ | |
1477 | return 0; | |
1478 | } | |
6ffbb7ab TJB |
1479 | if (cnt > total_hw_bp) |
1480 | return -1; | |
1481 | } | |
1482 | ||
926bf92d | 1483 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1484 | { |
1485 | int tid; | |
1486 | ptid_t ptid = inferior_ptid; | |
1487 | ||
0df8b418 MS |
1488 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
1489 | and whether the target has DABR. If either answer is no, the | |
1490 | ptrace call will return -1. Fail in that case. */ | |
dfd4cc63 | 1491 | tid = ptid_get_lwp (ptid); |
6ffbb7ab | 1492 | if (tid == 0) |
dfd4cc63 | 1493 | tid = ptid_get_pid (ptid); |
6ffbb7ab TJB |
1494 | |
1495 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1496 | return 0; | |
1497 | } | |
1498 | ||
1499 | return 1; | |
b7622095 LM |
1500 | } |
1501 | ||
e0d24f8d | 1502 | static int |
31568a15 TT |
1503 | ppc_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1504 | CORE_ADDR addr, int len) | |
e0d24f8d WZ |
1505 | { |
1506 | /* Handle sub-8-byte quantities. */ | |
1507 | if (len <= 0) | |
1508 | return 0; | |
1509 | ||
926bf92d UW |
1510 | /* The PowerPC HWDEBUG ptrace interface tells if there are alignment |
1511 | restrictions for watchpoints in the processors. In that case, we use that | |
1512 | information to determine the hardcoded watchable region for | |
1513 | watchpoints. */ | |
1514 | if (have_ptrace_hwdebug_interface ()) | |
6ffbb7ab | 1515 | { |
e23b9d6e | 1516 | int region_size; |
4feebbdd EBM |
1517 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
1518 | watchpoints and can watch any access within an arbitrary memory | |
1519 | region. This is useful to watch arrays and structs, for instance. It | |
1520 | takes two hardware watchpoints though. */ | |
e09342b5 | 1521 | if (len > 1 |
926bf92d | 1522 | && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
4feebbdd | 1523 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
e09342b5 | 1524 | return 2; |
e23b9d6e UW |
1525 | /* Check if the processor provides DAWR interface. */ |
1526 | if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) | |
1527 | /* DAWR interface allows to watch up to 512 byte wide ranges which | |
1528 | can't cross a 512 byte boundary. */ | |
1529 | region_size = 512; | |
1530 | else | |
1531 | region_size = hwdebug_info.data_bp_alignment; | |
4feebbdd EBM |
1532 | /* Server processors provide one hardware watchpoint and addr+len should |
1533 | fall in the watchable region provided by the ptrace interface. */ | |
e23b9d6e UW |
1534 | if (region_size |
1535 | && (addr + len > (addr & ~(region_size - 1)) + region_size)) | |
0cf6dd15 | 1536 | return 0; |
6ffbb7ab | 1537 | } |
b7622095 | 1538 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
926bf92d UW |
1539 | processors (i.e., server processors). Without the new PowerPC HWDEBUG |
1540 | ptrace interface, DAC-based processors (i.e., embedded processors) will | |
1541 | use addresses aligned to 4-bytes due to the way the read/write flags are | |
6ffbb7ab TJB |
1542 | passed in the old ptrace interface. */ |
1543 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1544 | && (addr + len) > (addr & ~3) + 4) | |
1545 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1546 | return 0; |
1547 | ||
1548 | return 1; | |
1549 | } | |
1550 | ||
6ffbb7ab | 1551 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
e4166a49 | 1552 | static int |
926bf92d | 1553 | hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
6ffbb7ab | 1554 | { |
ad422571 TJB |
1555 | return (a->trigger_type == b->trigger_type |
1556 | && a->addr_mode == b->addr_mode | |
1557 | && a->condition_mode == b->condition_mode | |
1558 | && a->addr == b->addr | |
1559 | && a->addr2 == b->addr2 | |
6ffbb7ab TJB |
1560 | && a->condition_value == b->condition_value); |
1561 | } | |
1562 | ||
1563 | /* This function can be used to retrieve a thread_points by the TID of the | |
1564 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, | |
1565 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the | |
1566 | provided TID will be created and returned. */ | |
1567 | static struct thread_points * | |
926bf92d | 1568 | hwdebug_find_thread_points_by_tid (int tid, int alloc_new) |
6ffbb7ab TJB |
1569 | { |
1570 | int i; | |
1571 | struct thread_points *t; | |
1572 | ||
1573 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) | |
1574 | if (t->tid == tid) | |
1575 | return t; | |
1576 | ||
1577 | t = NULL; | |
1578 | ||
1579 | /* Do we need to allocate a new point_item | |
1580 | if the wanted one does not exist? */ | |
1581 | if (alloc_new) | |
1582 | { | |
1583 | t = xmalloc (sizeof (struct thread_points)); | |
0df8b418 MS |
1584 | t->hw_breaks |
1585 | = xzalloc (max_slots_number * sizeof (struct hw_break_tuple)); | |
6ffbb7ab TJB |
1586 | t->tid = tid; |
1587 | VEC_safe_push (thread_points_p, ppc_threads, t); | |
1588 | } | |
1589 | ||
1590 | return t; | |
1591 | } | |
1592 | ||
1593 | /* This function is a generic wrapper that is responsible for inserting a | |
1594 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1595 | kernel) and registering it internally in GDB. */ | |
1596 | static void | |
926bf92d | 1597 | hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1598 | { |
1599 | int i; | |
1600 | long slot; | |
1601 | struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint)); | |
1602 | struct hw_break_tuple *hw_breaks; | |
1603 | struct cleanup *c = make_cleanup (xfree, p); | |
1604 | struct thread_points *t; | |
1605 | struct hw_break_tuple *tuple; | |
1606 | ||
1607 | memcpy (p, b, sizeof (struct ppc_hw_breakpoint)); | |
1608 | ||
1609 | errno = 0; | |
1610 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p); | |
1611 | if (slot < 0) | |
1612 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); | |
1613 | ||
1614 | /* Everything went fine, so we have to register this *point. */ | |
926bf92d | 1615 | t = hwdebug_find_thread_points_by_tid (tid, 1); |
6ffbb7ab TJB |
1616 | gdb_assert (t != NULL); |
1617 | hw_breaks = t->hw_breaks; | |
1618 | ||
1619 | /* Find a free element in the hw_breaks vector. */ | |
1620 | for (i = 0; i < max_slots_number; i++) | |
1621 | if (hw_breaks[i].hw_break == NULL) | |
1622 | { | |
1623 | hw_breaks[i].slot = slot; | |
1624 | hw_breaks[i].hw_break = p; | |
1625 | break; | |
1626 | } | |
1627 | ||
1628 | gdb_assert (i != max_slots_number); | |
1629 | ||
1630 | discard_cleanups (c); | |
1631 | } | |
1632 | ||
1633 | /* This function is a generic wrapper that is responsible for removing a | |
1634 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1635 | kernel), and unregistering it internally at GDB. */ | |
1636 | static void | |
926bf92d | 1637 | hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1638 | { |
1639 | int i; | |
1640 | struct hw_break_tuple *hw_breaks; | |
1641 | struct thread_points *t; | |
1642 | ||
926bf92d | 1643 | t = hwdebug_find_thread_points_by_tid (tid, 0); |
6ffbb7ab TJB |
1644 | gdb_assert (t != NULL); |
1645 | hw_breaks = t->hw_breaks; | |
1646 | ||
1647 | for (i = 0; i < max_slots_number; i++) | |
926bf92d | 1648 | if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b)) |
6ffbb7ab TJB |
1649 | break; |
1650 | ||
1651 | gdb_assert (i != max_slots_number); | |
1652 | ||
1653 | /* We have to ignore ENOENT errors because the kernel implements hardware | |
1654 | breakpoints/watchpoints as "one-shot", that is, they are automatically | |
1655 | deleted when hit. */ | |
1656 | errno = 0; | |
1657 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) | |
1658 | if (errno != ENOENT) | |
0df8b418 MS |
1659 | perror_with_name (_("Unexpected error deleting " |
1660 | "breakpoint or watchpoint")); | |
6ffbb7ab TJB |
1661 | |
1662 | xfree (hw_breaks[i].hw_break); | |
1663 | hw_breaks[i].hw_break = NULL; | |
1664 | } | |
9f0bdab8 | 1665 | |
f1310107 TJB |
1666 | /* Return the number of registers needed for a ranged breakpoint. */ |
1667 | ||
1668 | static int | |
1669 | ppc_linux_ranged_break_num_registers (struct target_ops *target) | |
1670 | { | |
926bf92d UW |
1671 | return ((have_ptrace_hwdebug_interface () |
1672 | && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? | |
f1310107 TJB |
1673 | 2 : -1); |
1674 | } | |
1675 | ||
1676 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for | |
1677 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ | |
1678 | ||
2c387241 | 1679 | static int |
23a26771 TT |
1680 | ppc_linux_insert_hw_breakpoint (struct target_ops *self, |
1681 | struct gdbarch *gdbarch, | |
6ffbb7ab | 1682 | struct bp_target_info *bp_tgt) |
e0d24f8d | 1683 | { |
9f0bdab8 | 1684 | struct lwp_info *lp; |
6ffbb7ab TJB |
1685 | struct ppc_hw_breakpoint p; |
1686 | ||
926bf92d | 1687 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1688 | return -1; |
1689 | ||
ad422571 TJB |
1690 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1691 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 | 1692 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
0d5ed153 | 1693 | p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address); |
6ffbb7ab TJB |
1694 | p.condition_value = 0; |
1695 | ||
f1310107 TJB |
1696 | if (bp_tgt->length) |
1697 | { | |
1698 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1699 | ||
1700 | /* The breakpoint will trigger if the address of the instruction is | |
1701 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
1702 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1703 | } | |
1704 | else | |
1705 | { | |
1706 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1707 | p.addr2 = 0; | |
1708 | } | |
1709 | ||
4c38200f | 1710 | ALL_LWPS (lp) |
dfd4cc63 | 1711 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
1712 | |
1713 | return 0; | |
1714 | } | |
1715 | ||
1716 | static int | |
a64dc96c TT |
1717 | ppc_linux_remove_hw_breakpoint (struct target_ops *self, |
1718 | struct gdbarch *gdbarch, | |
6ffbb7ab TJB |
1719 | struct bp_target_info *bp_tgt) |
1720 | { | |
6ffbb7ab TJB |
1721 | struct lwp_info *lp; |
1722 | struct ppc_hw_breakpoint p; | |
b7622095 | 1723 | |
926bf92d | 1724 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1725 | return -1; |
1726 | ||
ad422571 TJB |
1727 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1728 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1729 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1730 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1731 | p.condition_value = 0; |
1732 | ||
f1310107 TJB |
1733 | if (bp_tgt->length) |
1734 | { | |
1735 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1736 | ||
1737 | /* The breakpoint will trigger if the address of the instruction is within | |
1738 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
1739 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1740 | } | |
1741 | else | |
1742 | { | |
1743 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1744 | p.addr2 = 0; | |
1745 | } | |
1746 | ||
4c38200f | 1747 | ALL_LWPS (lp) |
dfd4cc63 | 1748 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
1749 | |
1750 | return 0; | |
1751 | } | |
1752 | ||
1753 | static int | |
1754 | get_trigger_type (int rw) | |
1755 | { | |
1756 | int t; | |
1757 | ||
1758 | if (rw == hw_read) | |
1759 | t = PPC_BREAKPOINT_TRIGGER_READ; | |
1760 | else if (rw == hw_write) | |
1761 | t = PPC_BREAKPOINT_TRIGGER_WRITE; | |
b7622095 | 1762 | else |
6ffbb7ab TJB |
1763 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
1764 | ||
1765 | return t; | |
1766 | } | |
1767 | ||
9c06b0b4 TJB |
1768 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
1769 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1770 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1771 | an error on failure. */ | |
1772 | ||
1773 | static int | |
1774 | ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, | |
1775 | CORE_ADDR mask, int rw) | |
1776 | { | |
9c06b0b4 TJB |
1777 | struct lwp_info *lp; |
1778 | struct ppc_hw_breakpoint p; | |
1779 | ||
926bf92d | 1780 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1781 | |
1782 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1783 | p.trigger_type = get_trigger_type (rw); | |
1784 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1785 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1786 | p.addr = addr; | |
1787 | p.addr2 = mask; | |
1788 | p.condition_value = 0; | |
1789 | ||
4c38200f | 1790 | ALL_LWPS (lp) |
dfd4cc63 | 1791 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
9c06b0b4 TJB |
1792 | |
1793 | return 0; | |
1794 | } | |
1795 | ||
1796 | /* Remove a masked watchpoint at ADDR with the mask MASK. | |
1797 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1798 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1799 | an error on failure. */ | |
1800 | ||
1801 | static int | |
1802 | ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, | |
1803 | CORE_ADDR mask, int rw) | |
1804 | { | |
9c06b0b4 TJB |
1805 | struct lwp_info *lp; |
1806 | struct ppc_hw_breakpoint p; | |
1807 | ||
926bf92d | 1808 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1809 | |
1810 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1811 | p.trigger_type = get_trigger_type (rw); | |
1812 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1813 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1814 | p.addr = addr; | |
1815 | p.addr2 = mask; | |
1816 | p.condition_value = 0; | |
1817 | ||
4c38200f | 1818 | ALL_LWPS (lp) |
dfd4cc63 | 1819 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
9c06b0b4 TJB |
1820 | |
1821 | return 0; | |
1822 | } | |
1823 | ||
0cf6dd15 TJB |
1824 | /* Check whether we have at least one free DVC register. */ |
1825 | static int | |
1826 | can_use_watchpoint_cond_accel (void) | |
1827 | { | |
1828 | struct thread_points *p; | |
dfd4cc63 | 1829 | int tid = ptid_get_lwp (inferior_ptid); |
926bf92d | 1830 | int cnt = hwdebug_info.num_condition_regs, i; |
0cf6dd15 TJB |
1831 | CORE_ADDR tmp_value; |
1832 | ||
926bf92d | 1833 | if (!have_ptrace_hwdebug_interface () || cnt == 0) |
0cf6dd15 TJB |
1834 | return 0; |
1835 | ||
926bf92d | 1836 | p = hwdebug_find_thread_points_by_tid (tid, 0); |
0cf6dd15 TJB |
1837 | |
1838 | if (p) | |
1839 | { | |
1840 | for (i = 0; i < max_slots_number; i++) | |
1841 | if (p->hw_breaks[i].hw_break != NULL | |
1842 | && (p->hw_breaks[i].hw_break->condition_mode | |
1843 | != PPC_BREAKPOINT_CONDITION_NONE)) | |
1844 | cnt--; | |
1845 | ||
1846 | /* There are no available slots now. */ | |
1847 | if (cnt <= 0) | |
1848 | return 0; | |
1849 | } | |
1850 | ||
1851 | return 1; | |
1852 | } | |
1853 | ||
1854 | /* Calculate the enable bits and the contents of the Data Value Compare | |
1855 | debug register present in BookE processors. | |
1856 | ||
1857 | ADDR is the address to be watched, LEN is the length of watched data | |
1858 | and DATA_VALUE is the value which will trigger the watchpoint. | |
1859 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
1860 | CONDITION_VALUE will hold the value which should be put in the | |
1861 | DVC register. */ | |
1862 | static void | |
1863 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, | |
1864 | uint32_t *condition_mode, uint64_t *condition_value) | |
1865 | { | |
1866 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, | |
1867 | rightmost_enabled_byte; | |
1868 | CORE_ADDR addr_end_data, addr_end_dvc; | |
1869 | ||
1870 | /* The DVC register compares bytes within fixed-length windows which | |
1871 | are word-aligned, with length equal to that of the DVC register. | |
1872 | We need to calculate where our watch region is relative to that | |
1873 | window and enable comparison of the bytes which fall within it. */ | |
1874 | ||
926bf92d | 1875 | align_offset = addr % hwdebug_info.sizeof_condition; |
0cf6dd15 TJB |
1876 | addr_end_data = addr + len; |
1877 | addr_end_dvc = (addr - align_offset | |
926bf92d | 1878 | + hwdebug_info.sizeof_condition); |
0cf6dd15 TJB |
1879 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? |
1880 | addr_end_data - addr_end_dvc : 0; | |
1881 | num_byte_enable = len - num_bytes_off_dvc; | |
1882 | /* Here, bytes are numbered from right to left. */ | |
1883 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
1884 | addr_end_dvc - addr_end_data : 0; | |
1885 | ||
1886 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
1887 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
1888 | *condition_mode |
1889 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
1890 | |
1891 | /* Now we need to match the position within the DVC of the comparison | |
1892 | value with where the watch region is relative to the window | |
1893 | (i.e., the ALIGN_OFFSET). */ | |
1894 | ||
1895 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
1896 | << rightmost_enabled_byte * 8); | |
1897 | } | |
1898 | ||
1899 | /* Return the number of memory locations that need to be accessed to | |
1900 | evaluate the expression which generated the given value chain. | |
1901 | Returns -1 if there's any register access involved, or if there are | |
1902 | other kinds of values which are not acceptable in a condition | |
1903 | expression (e.g., lval_computed or lval_internalvar). */ | |
1904 | static int | |
1905 | num_memory_accesses (struct value *v) | |
1906 | { | |
1907 | int found_memory_cnt = 0; | |
1908 | struct value *head = v; | |
1909 | ||
1910 | /* The idea here is that evaluating an expression generates a series | |
1911 | of values, one holding the value of every subexpression. (The | |
1912 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
1913 | a*b+c.) GDB's values hold almost enough information to establish | |
1914 | the criteria given above --- they identify memory lvalues, | |
1915 | register lvalues, computed values, etcetera. So we can evaluate | |
1916 | the expression, and then scan the chain of values that leaves | |
1917 | behind to determine the memory locations involved in the evaluation | |
1918 | of an expression. | |
1919 | ||
1920 | However, I don't think that the values returned by inferior | |
1921 | function calls are special in any way. So this function may not | |
1922 | notice that an expression contains an inferior function call. | |
1923 | FIXME. */ | |
1924 | ||
1925 | for (; v; v = value_next (v)) | |
1926 | { | |
1927 | /* Constants and values from the history are fine. */ | |
1928 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) | |
1929 | continue; | |
1930 | else if (VALUE_LVAL (v) == lval_memory) | |
1931 | { | |
1932 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
1933 | we either just used its address (e.g., `a' in `a.b') or | |
1934 | we never needed it at all (e.g., `a' in `a,b'). */ | |
1935 | if (!value_lazy (v)) | |
1936 | found_memory_cnt++; | |
1937 | } | |
0df8b418 | 1938 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
1939 | else |
1940 | return -1; | |
1941 | } | |
1942 | ||
1943 | return found_memory_cnt; | |
1944 | } | |
1945 | ||
1946 | /* Verifies whether the expression COND can be implemented using the | |
1947 | DVC (Data Value Compare) register in BookE processors. The expression | |
1948 | must test the watch value for equality with a constant expression. | |
1949 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
1950 | which the watch value should be compared and LEN will contain the size |
1951 | of the constant. */ | |
0cf6dd15 TJB |
1952 | static int |
1953 | check_condition (CORE_ADDR watch_addr, struct expression *cond, | |
e7db58ea | 1954 | CORE_ADDR *data_value, int *len) |
0cf6dd15 TJB |
1955 | { |
1956 | int pc = 1, num_accesses_left, num_accesses_right; | |
1957 | struct value *left_val, *right_val, *left_chain, *right_chain; | |
1958 | ||
1959 | if (cond->elts[0].opcode != BINOP_EQUAL) | |
1960 | return 0; | |
1961 | ||
3a1115a0 | 1962 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0); |
0cf6dd15 TJB |
1963 | num_accesses_left = num_memory_accesses (left_chain); |
1964 | ||
1965 | if (left_val == NULL || num_accesses_left < 0) | |
1966 | { | |
1967 | free_value_chain (left_chain); | |
1968 | ||
1969 | return 0; | |
1970 | } | |
1971 | ||
3a1115a0 | 1972 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0); |
0cf6dd15 TJB |
1973 | num_accesses_right = num_memory_accesses (right_chain); |
1974 | ||
1975 | if (right_val == NULL || num_accesses_right < 0) | |
1976 | { | |
1977 | free_value_chain (left_chain); | |
1978 | free_value_chain (right_chain); | |
1979 | ||
1980 | return 0; | |
1981 | } | |
1982 | ||
1983 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
1984 | && VALUE_LVAL (left_val) == lval_memory | |
1985 | && value_address (left_val) == watch_addr) | |
e7db58ea TJB |
1986 | { |
1987 | *data_value = value_as_long (right_val); | |
1988 | ||
1989 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
1990 | the same type as the memory region referenced by LEFT_VAL. */ | |
1991 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); | |
1992 | } | |
0cf6dd15 TJB |
1993 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
1994 | && VALUE_LVAL (right_val) == lval_memory | |
1995 | && value_address (right_val) == watch_addr) | |
e7db58ea TJB |
1996 | { |
1997 | *data_value = value_as_long (left_val); | |
1998 | ||
1999 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
2000 | the same type as the memory region referenced by RIGHT_VAL. */ | |
2001 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); | |
2002 | } | |
0cf6dd15 TJB |
2003 | else |
2004 | { | |
2005 | free_value_chain (left_chain); | |
2006 | free_value_chain (right_chain); | |
2007 | ||
2008 | return 0; | |
2009 | } | |
2010 | ||
2011 | free_value_chain (left_chain); | |
2012 | free_value_chain (right_chain); | |
2013 | ||
2014 | return 1; | |
2015 | } | |
2016 | ||
2017 | /* Return non-zero if the target is capable of using hardware to evaluate | |
2018 | the condition expression, thus only triggering the watchpoint when it is | |
2019 | true. */ | |
2020 | static int | |
c3a5ff89 TT |
2021 | ppc_linux_can_accel_watchpoint_condition (struct target_ops *self, |
2022 | CORE_ADDR addr, int len, int rw, | |
0cf6dd15 TJB |
2023 | struct expression *cond) |
2024 | { | |
2025 | CORE_ADDR data_value; | |
2026 | ||
926bf92d UW |
2027 | return (have_ptrace_hwdebug_interface () |
2028 | && hwdebug_info.num_condition_regs > 0 | |
e7db58ea | 2029 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
2030 | } |
2031 | ||
e09342b5 TJB |
2032 | /* Set up P with the parameters necessary to request a watchpoint covering |
2033 | LEN bytes starting at ADDR and if possible with condition expression COND | |
2034 | evaluated by hardware. INSERT tells if we are creating a request for | |
2035 | inserting or removing the watchpoint. */ | |
2036 | ||
2037 | static void | |
2038 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, | |
2039 | int len, int rw, struct expression *cond, | |
2040 | int insert) | |
2041 | { | |
f16c4e8b | 2042 | if (len == 1 |
926bf92d | 2043 | || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) |
e09342b5 TJB |
2044 | { |
2045 | int use_condition; | |
2046 | CORE_ADDR data_value; | |
2047 | ||
2048 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
926bf92d | 2049 | : hwdebug_info.num_condition_regs > 0); |
e7db58ea TJB |
2050 | if (cond && use_condition && check_condition (addr, cond, |
2051 | &data_value, &len)) | |
e09342b5 TJB |
2052 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
2053 | &p->condition_value); | |
2054 | else | |
2055 | { | |
2056 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2057 | p->condition_value = 0; | |
2058 | } | |
2059 | ||
2060 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2061 | p->addr2 = 0; | |
2062 | } | |
2063 | else | |
2064 | { | |
2065 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2066 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2067 | p->condition_value = 0; | |
2068 | ||
2069 | /* The watchpoint will trigger if the address of the memory access is | |
2070 | within the defined range, as follows: p->addr <= address < p->addr2. | |
2071 | ||
2072 | Note that the above sentence just documents how ptrace interprets | |
2073 | its arguments; the watchpoint is set to watch the range defined by | |
2074 | the user _inclusively_, as specified by the user interface. */ | |
2075 | p->addr2 = (uint64_t) addr + len; | |
2076 | } | |
2077 | ||
2078 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
2079 | p->trigger_type = get_trigger_type (rw); | |
2080 | p->addr = (uint64_t) addr; | |
2081 | } | |
2082 | ||
6ffbb7ab | 2083 | static int |
7bb99c53 TT |
2084 | ppc_linux_insert_watchpoint (struct target_ops *self, |
2085 | CORE_ADDR addr, int len, int rw, | |
0cf6dd15 | 2086 | struct expression *cond) |
6ffbb7ab TJB |
2087 | { |
2088 | struct lwp_info *lp; | |
6ffbb7ab TJB |
2089 | int ret = -1; |
2090 | ||
926bf92d | 2091 | if (have_ptrace_hwdebug_interface ()) |
e0d24f8d | 2092 | { |
6ffbb7ab TJB |
2093 | struct ppc_hw_breakpoint p; |
2094 | ||
e09342b5 | 2095 | create_watchpoint_request (&p, addr, len, rw, cond, 1); |
6ffbb7ab | 2096 | |
4c38200f | 2097 | ALL_LWPS (lp) |
dfd4cc63 | 2098 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
2099 | |
2100 | ret = 0; | |
e0d24f8d | 2101 | } |
6ffbb7ab TJB |
2102 | else |
2103 | { | |
2104 | long dabr_value; | |
2105 | long read_mode, write_mode; | |
e0d24f8d | 2106 | |
6ffbb7ab TJB |
2107 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2108 | { | |
2109 | /* PowerPC 440 requires only the read/write flags to be passed | |
2110 | to the kernel. */ | |
ad422571 | 2111 | read_mode = 1; |
6ffbb7ab TJB |
2112 | write_mode = 2; |
2113 | } | |
2114 | else | |
2115 | { | |
2116 | /* PowerPC 970 and other DABR-based processors are required to pass | |
2117 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 2118 | read_mode = 5; |
6ffbb7ab TJB |
2119 | write_mode = 6; |
2120 | } | |
1c86e440 | 2121 | |
6ffbb7ab TJB |
2122 | dabr_value = addr & ~(read_mode | write_mode); |
2123 | switch (rw) | |
2124 | { | |
2125 | case hw_read: | |
2126 | /* Set read and translate bits. */ | |
2127 | dabr_value |= read_mode; | |
2128 | break; | |
2129 | case hw_write: | |
2130 | /* Set write and translate bits. */ | |
2131 | dabr_value |= write_mode; | |
2132 | break; | |
2133 | case hw_access: | |
2134 | /* Set read, write and translate bits. */ | |
2135 | dabr_value |= read_mode | write_mode; | |
2136 | break; | |
2137 | } | |
1c86e440 | 2138 | |
6ffbb7ab TJB |
2139 | saved_dabr_value = dabr_value; |
2140 | ||
4c38200f | 2141 | ALL_LWPS (lp) |
dfd4cc63 | 2142 | if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, |
0cf6dd15 | 2143 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2144 | return -1; |
2145 | ||
2146 | ret = 0; | |
2147 | } | |
2148 | ||
2149 | return ret; | |
e0d24f8d WZ |
2150 | } |
2151 | ||
2c387241 | 2152 | static int |
11b5219a TT |
2153 | ppc_linux_remove_watchpoint (struct target_ops *self, |
2154 | CORE_ADDR addr, int len, int rw, | |
0cf6dd15 | 2155 | struct expression *cond) |
e0d24f8d | 2156 | { |
9f0bdab8 | 2157 | struct lwp_info *lp; |
6ffbb7ab | 2158 | int ret = -1; |
9f0bdab8 | 2159 | |
926bf92d | 2160 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2161 | { |
2162 | struct ppc_hw_breakpoint p; | |
2163 | ||
e09342b5 | 2164 | create_watchpoint_request (&p, addr, len, rw, cond, 0); |
6ffbb7ab | 2165 | |
4c38200f | 2166 | ALL_LWPS (lp) |
dfd4cc63 | 2167 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
2168 | |
2169 | ret = 0; | |
2170 | } | |
2171 | else | |
2172 | { | |
2173 | saved_dabr_value = 0; | |
4c38200f | 2174 | ALL_LWPS (lp) |
dfd4cc63 | 2175 | if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, |
0cf6dd15 | 2176 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2177 | return -1; |
2178 | ||
2179 | ret = 0; | |
2180 | } | |
2181 | ||
2182 | return ret; | |
e0d24f8d WZ |
2183 | } |
2184 | ||
9f0bdab8 | 2185 | static void |
7b50312a | 2186 | ppc_linux_new_thread (struct lwp_info *lp) |
e0d24f8d | 2187 | { |
dfd4cc63 | 2188 | int tid = ptid_get_lwp (lp->ptid); |
6ffbb7ab | 2189 | |
926bf92d | 2190 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2191 | { |
2192 | int i; | |
2193 | struct thread_points *p; | |
2194 | struct hw_break_tuple *hw_breaks; | |
2195 | ||
2196 | if (VEC_empty (thread_points_p, ppc_threads)) | |
2197 | return; | |
2198 | ||
0df8b418 | 2199 | /* Get a list of breakpoints from any thread. */ |
6ffbb7ab TJB |
2200 | p = VEC_last (thread_points_p, ppc_threads); |
2201 | hw_breaks = p->hw_breaks; | |
2202 | ||
0df8b418 | 2203 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
6ffbb7ab TJB |
2204 | for (i = 0; i < max_slots_number; i++) |
2205 | if (hw_breaks[i].hw_break) | |
aacbb8a5 LM |
2206 | { |
2207 | /* Older kernels did not make new threads inherit their parent | |
2208 | thread's debug state, so we always clear the slot and replicate | |
2209 | the debug state ourselves, ensuring compatibility with all | |
2210 | kernels. */ | |
2211 | ||
2212 | /* The ppc debug resource accounting is done through "slots". | |
2213 | Ask the kernel the deallocate this specific *point's slot. */ | |
2214 | ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot); | |
2215 | ||
926bf92d | 2216 | hwdebug_insert_point (hw_breaks[i].hw_break, tid); |
aacbb8a5 | 2217 | } |
6ffbb7ab TJB |
2218 | } |
2219 | else | |
2220 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); | |
2221 | } | |
2222 | ||
2223 | static void | |
2224 | ppc_linux_thread_exit (struct thread_info *tp, int silent) | |
2225 | { | |
2226 | int i; | |
dfd4cc63 | 2227 | int tid = ptid_get_lwp (tp->ptid); |
6ffbb7ab TJB |
2228 | struct hw_break_tuple *hw_breaks; |
2229 | struct thread_points *t = NULL, *p; | |
2230 | ||
926bf92d | 2231 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2232 | return; |
2233 | ||
2234 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) | |
2235 | if (p->tid == tid) | |
2236 | { | |
2237 | t = p; | |
2238 | break; | |
2239 | } | |
2240 | ||
2241 | if (t == NULL) | |
2242 | return; | |
2243 | ||
2244 | VEC_unordered_remove (thread_points_p, ppc_threads, i); | |
2245 | ||
2246 | hw_breaks = t->hw_breaks; | |
2247 | ||
2248 | for (i = 0; i < max_slots_number; i++) | |
2249 | if (hw_breaks[i].hw_break) | |
2250 | xfree (hw_breaks[i].hw_break); | |
2251 | ||
2252 | xfree (t->hw_breaks); | |
2253 | xfree (t); | |
e0d24f8d WZ |
2254 | } |
2255 | ||
2256 | static int | |
9f0bdab8 | 2257 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) |
e0d24f8d | 2258 | { |
f865ee35 | 2259 | siginfo_t siginfo; |
e0d24f8d | 2260 | |
f865ee35 JK |
2261 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
2262 | return 0; | |
e0d24f8d | 2263 | |
f865ee35 JK |
2264 | if (siginfo.si_signo != SIGTRAP |
2265 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e0d24f8d WZ |
2266 | return 0; |
2267 | ||
926bf92d | 2268 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2269 | { |
2270 | int i; | |
2271 | struct thread_points *t; | |
2272 | struct hw_break_tuple *hw_breaks; | |
2273 | /* The index (or slot) of the *point is passed in the si_errno field. */ | |
f865ee35 | 2274 | int slot = siginfo.si_errno; |
6ffbb7ab | 2275 | |
dfd4cc63 | 2276 | t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0); |
6ffbb7ab TJB |
2277 | |
2278 | /* Find out if this *point is a hardware breakpoint. | |
2279 | If so, we should return 0. */ | |
2280 | if (t) | |
2281 | { | |
2282 | hw_breaks = t->hw_breaks; | |
2283 | for (i = 0; i < max_slots_number; i++) | |
2284 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot | |
2285 | && hw_breaks[i].hw_break->trigger_type | |
2286 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) | |
2287 | return 0; | |
2288 | } | |
2289 | } | |
2290 | ||
f865ee35 | 2291 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e0d24f8d WZ |
2292 | return 1; |
2293 | } | |
2294 | ||
9f0bdab8 | 2295 | static int |
6a109b6b | 2296 | ppc_linux_stopped_by_watchpoint (struct target_ops *ops) |
9f0bdab8 DJ |
2297 | { |
2298 | CORE_ADDR addr; | |
6a109b6b | 2299 | return ppc_linux_stopped_data_address (ops, &addr); |
9f0bdab8 DJ |
2300 | } |
2301 | ||
5009afc5 AS |
2302 | static int |
2303 | ppc_linux_watchpoint_addr_within_range (struct target_ops *target, | |
2304 | CORE_ADDR addr, | |
2305 | CORE_ADDR start, int length) | |
2306 | { | |
b7622095 LM |
2307 | int mask; |
2308 | ||
926bf92d | 2309 | if (have_ptrace_hwdebug_interface () |
6ffbb7ab TJB |
2310 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2311 | return start <= addr && start + length >= addr; | |
2312 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
b7622095 LM |
2313 | mask = 3; |
2314 | else | |
2315 | mask = 7; | |
2316 | ||
2317 | addr &= ~mask; | |
2318 | ||
0df8b418 | 2319 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 2320 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
2321 | } |
2322 | ||
9c06b0b4 TJB |
2323 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
2324 | ||
2325 | static int | |
2326 | ppc_linux_masked_watch_num_registers (struct target_ops *target, | |
2327 | CORE_ADDR addr, CORE_ADDR mask) | |
2328 | { | |
926bf92d UW |
2329 | if (!have_ptrace_hwdebug_interface () |
2330 | || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
9c06b0b4 TJB |
2331 | return -1; |
2332 | else if ((mask & 0xC0000000) != 0xC0000000) | |
2333 | { | |
2334 | warning (_("The given mask covers kernel address space " | |
2335 | "and cannot be used.\n")); | |
2336 | ||
2337 | return -2; | |
2338 | } | |
2339 | else | |
2340 | return 2; | |
2341 | } | |
2342 | ||
10d6c8cd | 2343 | static void |
28439f5e PA |
2344 | ppc_linux_store_inferior_registers (struct target_ops *ops, |
2345 | struct regcache *regcache, int regno) | |
45229ea4 | 2346 | { |
0df8b418 | 2347 | /* Overload thread id onto process id. */ |
dfd4cc63 | 2348 | int tid = ptid_get_lwp (inferior_ptid); |
05f13b9c | 2349 | |
0df8b418 | 2350 | /* No thread id, just use process id. */ |
05f13b9c | 2351 | if (tid == 0) |
dfd4cc63 | 2352 | tid = ptid_get_pid (inferior_ptid); |
05f13b9c | 2353 | |
45229ea4 | 2354 | if (regno >= 0) |
56be3814 | 2355 | store_register (regcache, tid, regno); |
45229ea4 | 2356 | else |
56be3814 | 2357 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
2358 | } |
2359 | ||
f2db237a AM |
2360 | /* Functions for transferring registers between a gregset_t or fpregset_t |
2361 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
0df8b418 | 2362 | by the ptrace interface, not the current program's ABI. Eg. if a |
f2db237a AM |
2363 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
2364 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
2365 | ||
50c9bd31 | 2366 | void |
7f7fe91e | 2367 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 2368 | { |
f2db237a | 2369 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2370 | |
f2db237a | 2371 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
2372 | } |
2373 | ||
fdb28ac4 | 2374 | void |
7f7fe91e UW |
2375 | fill_gregset (const struct regcache *regcache, |
2376 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 2377 | { |
f2db237a | 2378 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2379 | |
f2db237a AM |
2380 | if (regno == -1) |
2381 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
2382 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
2383 | } |
2384 | ||
50c9bd31 | 2385 | void |
7f7fe91e | 2386 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 2387 | { |
f2db237a AM |
2388 | const struct regset *regset = ppc_linux_fpregset (); |
2389 | ||
2390 | ppc_supply_fpregset (regset, regcache, -1, | |
2391 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 2392 | } |
fdb28ac4 | 2393 | |
fdb28ac4 | 2394 | void |
7f7fe91e UW |
2395 | fill_fpregset (const struct regcache *regcache, |
2396 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 2397 | { |
f2db237a AM |
2398 | const struct regset *regset = ppc_linux_fpregset (); |
2399 | ||
2400 | ppc_collect_fpregset (regset, regcache, regno, | |
2401 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 2402 | } |
10d6c8cd | 2403 | |
409c383c UW |
2404 | static int |
2405 | ppc_linux_target_wordsize (void) | |
2406 | { | |
2407 | int wordsize = 4; | |
2408 | ||
2409 | /* Check for 64-bit inferior process. This is the case when the host is | |
2410 | 64-bit, and in addition the top bit of the MSR register is set. */ | |
2411 | #ifdef __powerpc64__ | |
2412 | long msr; | |
2413 | ||
dfd4cc63 | 2414 | int tid = ptid_get_lwp (inferior_ptid); |
409c383c | 2415 | if (tid == 0) |
dfd4cc63 | 2416 | tid = ptid_get_pid (inferior_ptid); |
409c383c UW |
2417 | |
2418 | errno = 0; | |
2419 | msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); | |
2420 | if (errno == 0 && msr < 0) | |
2421 | wordsize = 8; | |
2422 | #endif | |
2423 | ||
2424 | return wordsize; | |
2425 | } | |
2426 | ||
2427 | static int | |
2428 | ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr, | |
2429 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
2430 | { | |
2431 | int sizeof_auxv_field = ppc_linux_target_wordsize (); | |
f5656ead | 2432 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
409c383c UW |
2433 | gdb_byte *ptr = *readptr; |
2434 | ||
2435 | if (endptr == ptr) | |
2436 | return 0; | |
2437 | ||
2438 | if (endptr - ptr < sizeof_auxv_field * 2) | |
2439 | return -1; | |
2440 | ||
e17a4113 | 2441 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c | 2442 | ptr += sizeof_auxv_field; |
e17a4113 | 2443 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c UW |
2444 | ptr += sizeof_auxv_field; |
2445 | ||
2446 | *readptr = ptr; | |
2447 | return 1; | |
2448 | } | |
2449 | ||
310a98e1 DJ |
2450 | static const struct target_desc * |
2451 | ppc_linux_read_description (struct target_ops *ops) | |
2452 | { | |
7284e1be | 2453 | int altivec = 0; |
604c2f83 | 2454 | int vsx = 0; |
69abc51c | 2455 | int isa205 = 0; |
f4d9bade | 2456 | int cell = 0; |
7284e1be | 2457 | |
dfd4cc63 | 2458 | int tid = ptid_get_lwp (inferior_ptid); |
7284e1be | 2459 | if (tid == 0) |
dfd4cc63 | 2460 | tid = ptid_get_pid (inferior_ptid); |
7284e1be | 2461 | |
310a98e1 DJ |
2462 | if (have_ptrace_getsetevrregs) |
2463 | { | |
2464 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
2465 | |
2466 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
2467 | return tdesc_powerpc_e500l; |
2468 | ||
2469 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
2470 | Anything else needs to be reported. */ | |
2471 | else if (errno != EIO) | |
2472 | perror_with_name (_("Unable to fetch SPE registers")); | |
2473 | } | |
2474 | ||
604c2f83 LM |
2475 | if (have_ptrace_getsetvsxregs) |
2476 | { | |
2477 | gdb_vsxregset_t vsxregset; | |
2478 | ||
2479 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
2480 | vsx = 1; | |
2481 | ||
2482 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
2483 | Anything else needs to be reported. */ | |
2484 | else if (errno != EIO) | |
2485 | perror_with_name (_("Unable to fetch VSX registers")); | |
2486 | } | |
2487 | ||
7284e1be UW |
2488 | if (have_ptrace_getvrregs) |
2489 | { | |
2490 | gdb_vrregset_t vrregset; | |
2491 | ||
2492 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
2493 | altivec = 1; | |
2494 | ||
2495 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
2496 | Anything else needs to be reported. */ | |
2497 | else if (errno != EIO) | |
2498 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
2499 | } |
2500 | ||
f04c6d38 | 2501 | /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases |
0df8b418 | 2502 | the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this |
f04c6d38 TJB |
2503 | ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only |
2504 | PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher | |
2505 | half of the register are for Decimal Floating Point, we check if that | |
2506 | feature is available to decide the size of the FPSCR. */ | |
2507 | if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP) | |
69abc51c TJB |
2508 | isa205 = 1; |
2509 | ||
f4d9bade UW |
2510 | if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL) |
2511 | cell = 1; | |
2512 | ||
409c383c UW |
2513 | if (ppc_linux_target_wordsize () == 8) |
2514 | { | |
f4d9bade UW |
2515 | if (cell) |
2516 | return tdesc_powerpc_cell64l; | |
2517 | else if (vsx) | |
409c383c UW |
2518 | return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; |
2519 | else if (altivec) | |
0df8b418 MS |
2520 | return isa205 |
2521 | ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; | |
409c383c UW |
2522 | |
2523 | return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; | |
2524 | } | |
7284e1be | 2525 | |
f4d9bade UW |
2526 | if (cell) |
2527 | return tdesc_powerpc_cell32l; | |
2528 | else if (vsx) | |
69abc51c | 2529 | return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; |
604c2f83 | 2530 | else if (altivec) |
69abc51c | 2531 | return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; |
604c2f83 | 2532 | |
69abc51c | 2533 | return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; |
310a98e1 DJ |
2534 | } |
2535 | ||
10d6c8cd DJ |
2536 | void _initialize_ppc_linux_nat (void); |
2537 | ||
2538 | void | |
2539 | _initialize_ppc_linux_nat (void) | |
2540 | { | |
2541 | struct target_ops *t; | |
2542 | ||
2543 | /* Fill in the generic GNU/Linux methods. */ | |
2544 | t = linux_target (); | |
2545 | ||
2546 | /* Add our register access methods. */ | |
2547 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; | |
2548 | t->to_store_registers = ppc_linux_store_inferior_registers; | |
2549 | ||
6ffbb7ab TJB |
2550 | /* Add our breakpoint/watchpoint methods. */ |
2551 | t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint; | |
2552 | t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint; | |
2553 | t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint; | |
e0d24f8d WZ |
2554 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; |
2555 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; | |
2556 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; | |
9c06b0b4 TJB |
2557 | t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint; |
2558 | t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint; | |
e0d24f8d WZ |
2559 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; |
2560 | t->to_stopped_data_address = ppc_linux_stopped_data_address; | |
5009afc5 | 2561 | t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; |
0df8b418 MS |
2562 | t->to_can_accel_watchpoint_condition |
2563 | = ppc_linux_can_accel_watchpoint_condition; | |
9c06b0b4 | 2564 | t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers; |
f1310107 | 2565 | t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers; |
e0d24f8d | 2566 | |
310a98e1 | 2567 | t->to_read_description = ppc_linux_read_description; |
409c383c | 2568 | t->to_auxv_parse = ppc_linux_auxv_parse; |
310a98e1 | 2569 | |
6ffbb7ab TJB |
2570 | observer_attach_thread_exit (ppc_linux_thread_exit); |
2571 | ||
10d6c8cd | 2572 | /* Register the target. */ |
f973ed9c | 2573 | linux_nat_add_target (t); |
9f0bdab8 | 2574 | linux_nat_set_new_thread (t, ppc_linux_new_thread); |
10d6c8cd | 2575 | } |