Commit | Line | Data |
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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003, |
4 | 2004, 2005, 2006, 2007 Free Software Foundation, Inc. | |
c877c8e6 KB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
c877c8e6 KB |
22 | |
23 | #include "defs.h" | |
e162d11b | 24 | #include "gdb_string.h" |
c877c8e6 KB |
25 | #include "frame.h" |
26 | #include "inferior.h" | |
27 | #include "gdbcore.h" | |
4e052eda | 28 | #include "regcache.h" |
383f0f5b | 29 | #include "gdb_assert.h" |
10d6c8cd DJ |
30 | #include "target.h" |
31 | #include "linux-nat.h" | |
c877c8e6 | 32 | |
411cb3f9 | 33 | #include <stdint.h> |
c877c8e6 KB |
34 | #include <sys/types.h> |
35 | #include <sys/param.h> | |
36 | #include <signal.h> | |
37 | #include <sys/user.h> | |
38 | #include <sys/ioctl.h> | |
2555fe1a | 39 | #include "gdb_wait.h" |
c877c8e6 KB |
40 | #include <fcntl.h> |
41 | #include <sys/procfs.h> | |
45229ea4 | 42 | #include <sys/ptrace.h> |
c877c8e6 | 43 | |
c60c0f5f MS |
44 | /* Prototypes for supply_gregset etc. */ |
45 | #include "gregset.h" | |
16333c4f | 46 | #include "ppc-tdep.h" |
c60c0f5f | 47 | |
9abe5450 EZ |
48 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
49 | configure time check. Some older glibc's (for instance 2.2.1) | |
50 | don't have a specific powerpc version of ptrace.h, and fall back on | |
51 | a generic one. In such cases, sys/ptrace.h defines | |
52 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
53 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
54 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
55 | much useless. */ | |
56 | ||
57 | /* These definitions should really come from the glibc header files, | |
58 | but Glibc doesn't know about the vrregs yet. */ | |
59 | #ifndef PTRACE_GETVRREGS | |
60 | #define PTRACE_GETVRREGS 18 | |
61 | #define PTRACE_SETVRREGS 19 | |
62 | #endif | |
63 | ||
01904826 JB |
64 | |
65 | /* Similarly for the ptrace requests for getting / setting the SPE | |
66 | registers (ev0 -- ev31, acc, and spefscr). See the description of | |
67 | gdb_evrregset_t for details. */ | |
68 | #ifndef PTRACE_GETEVRREGS | |
69 | #define PTRACE_GETEVRREGS 20 | |
70 | #define PTRACE_SETEVRREGS 21 | |
71 | #endif | |
72 | ||
e0d24f8d WZ |
73 | /* Similarly for the hardware watchpoint support. */ |
74 | #ifndef PTRACE_GET_DEBUGREG | |
75 | #define PTRACE_GET_DEBUGREG 25 | |
76 | #endif | |
77 | #ifndef PTRACE_SET_DEBUGREG | |
78 | #define PTRACE_SET_DEBUGREG 26 | |
79 | #endif | |
80 | #ifndef PTRACE_GETSIGINFO | |
81 | #define PTRACE_GETSIGINFO 0x4202 | |
82 | #endif | |
01904826 | 83 | |
9abe5450 EZ |
84 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
85 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
86 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
87 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
88 | flat array of chars, so that it is easier to manipulate for gdb. | |
89 | ||
90 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
91 | which is only 4 bytes long, but is fetched as a 16 bytes | |
92 | quantity. Up to here we have the elf_vrregset_t structure. | |
93 | Appended to this there is space for the VRSAVE register: 4 bytes. | |
94 | Even though this vrsave register is not included in the regset | |
95 | typedef, it is handled by the ptrace requests. | |
96 | ||
97 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
98 | therefore the offset at which the real value of the VSCR register | |
99 | is located will be always 12 bytes. | |
100 | ||
101 | The layout is like this (where x is the actual value of the vscr reg): */ | |
102 | ||
103 | /* *INDENT-OFF* */ | |
104 | /* | |
105 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
106 | <-------> <-------><-------><-> | |
107 | VR0 VR31 VSCR VRSAVE | |
108 | */ | |
109 | /* *INDENT-ON* */ | |
110 | ||
111 | #define SIZEOF_VRREGS 33*16+4 | |
112 | ||
113 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
114 | ||
01904826 JB |
115 | |
116 | /* On PPC processors that support the the Signal Processing Extension | |
117 | (SPE) APU, the general-purpose registers are 64 bits long. | |
411cb3f9 PG |
118 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
119 | ptrace calls only access the lower half of each register, to allow | |
120 | them to behave the same way they do on non-SPE systems. There's a | |
121 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
122 | read and write the top halves of all the general-purpose registers | |
123 | at once, along with some SPE-specific registers. | |
01904826 JB |
124 | |
125 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd JB |
126 | bits long. It has unnamed raw registers that hold the upper halves |
127 | of the gprs, and the the full 64-bit SIMD views of the registers, | |
128 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and | |
129 | bottom halves together. | |
01904826 JB |
130 | |
131 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
132 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
133 | struct gdb_evrregset_t | |
134 | { | |
135 | unsigned long evr[32]; | |
136 | unsigned long long acc; | |
137 | unsigned long spefscr; | |
138 | }; | |
139 | ||
140 | ||
141 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
142 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
143 | registers. Zero if we've tried one of them and gotten an | |
144 | error. */ | |
9abe5450 EZ |
145 | int have_ptrace_getvrregs = 1; |
146 | ||
e0d24f8d | 147 | static CORE_ADDR last_stopped_data_address = 0; |
01904826 JB |
148 | |
149 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and | |
150 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
151 | registers. Zero if we've tried one of them and gotten an | |
152 | error. */ | |
153 | int have_ptrace_getsetevrregs = 1; | |
154 | ||
16333c4f EZ |
155 | /* *INDENT-OFF* */ |
156 | /* registers layout, as presented by the ptrace interface: | |
157 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
158 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
159 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
160 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
161 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
162 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
163 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
164 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
165 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ | |
166 | /* *INDENT_ON * */ | |
c877c8e6 | 167 | |
45229ea4 EZ |
168 | static int |
169 | ppc_register_u_addr (int regno) | |
c877c8e6 | 170 | { |
16333c4f | 171 | int u_addr = -1; |
dc5cfeb6 | 172 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
56d0d96a AC |
173 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
174 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 175 | int wordsize = sizeof (long); |
16333c4f EZ |
176 | |
177 | /* General purpose registers occupy 1 slot each in the buffer */ | |
8bf659e8 JB |
178 | if (regno >= tdep->ppc_gp0_regnum |
179 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 180 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 181 | |
49ff75ad JB |
182 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
183 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
184 | slot each in 64-bit interface. */ | |
383f0f5b JB |
185 | if (tdep->ppc_fp0_regnum >= 0 |
186 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
187 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
188 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f EZ |
189 | |
190 | /* UISA special purpose registers: 1 slot each */ | |
191 | if (regno == PC_REGNUM) | |
49ff75ad | 192 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 193 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 194 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 195 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 196 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 197 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 198 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 199 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 200 | u_addr = PT_CTR * wordsize; |
f8c59253 | 201 | #ifdef PT_MQ |
dc5cfeb6 | 202 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 203 | u_addr = PT_MQ * wordsize; |
f8c59253 | 204 | #endif |
dc5cfeb6 | 205 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 206 | u_addr = PT_MSR * wordsize; |
383f0f5b JB |
207 | if (tdep->ppc_fpscr_regnum >= 0 |
208 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
209 | { |
210 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
211 | kernel headers incorrectly contained the 32-bit definition of | |
212 | PT_FPSCR. For the 32-bit definition, floating-point | |
213 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
214 | the secondhalf of such a slot-pair (hence +1). For 64-bit, | |
215 | the FPSCR instead occupies the full 64-bit 2-word-slot and | |
216 | hence no adjustment is necessary. Hack around this. */ | |
217 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
218 | u_addr = (48 + 32) * wordsize; | |
219 | else | |
220 | u_addr = PT_FPSCR * wordsize; | |
221 | } | |
16333c4f | 222 | return u_addr; |
c877c8e6 KB |
223 | } |
224 | ||
9abe5450 EZ |
225 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
226 | registers set mechanism, as opposed to the interface for all the | |
227 | other registers, that stores/fetches each register individually. */ | |
228 | static void | |
56be3814 | 229 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
230 | { |
231 | int ret; | |
232 | int offset = 0; | |
233 | gdb_vrregset_t regs; | |
234 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3acba339 | 235 | int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); |
9abe5450 EZ |
236 | |
237 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
238 | if (ret < 0) | |
239 | { | |
240 | if (errno == EIO) | |
241 | { | |
242 | have_ptrace_getvrregs = 0; | |
243 | return; | |
244 | } | |
e2e0b3e5 | 245 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
246 | } |
247 | ||
248 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
249 | long on the hardware. We deal only with the lower 4 bytes of the | |
250 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
251 | there is no need to define an offset for it. */ | |
252 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
3acba339 | 253 | offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 254 | |
56be3814 | 255 | regcache_raw_supply (regcache, regno, |
23a6d369 | 256 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
257 | } |
258 | ||
01904826 JB |
259 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
260 | SPE-specific registers, and place the results in EVRREGSET. If we | |
261 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
262 | zeros. | |
263 | ||
264 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
265 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
266 | set_spe_registers. */ | |
267 | static void | |
268 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
269 | { | |
270 | if (have_ptrace_getsetevrregs) | |
271 | { | |
272 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
273 | return; | |
274 | else | |
275 | { | |
276 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
277 | we just return zeros. */ | |
278 | if (errno == EIO) | |
279 | have_ptrace_getsetevrregs = 0; | |
280 | else | |
281 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 282 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
283 | } |
284 | } | |
285 | ||
286 | memset (evrregset, 0, sizeof (*evrregset)); | |
287 | } | |
288 | ||
6ced10dd JB |
289 | /* Supply values from TID for SPE-specific raw registers: the upper |
290 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
291 | be the number of an upper half register, acc, spefscr, or -1 to | |
292 | supply the values of all registers. */ | |
01904826 | 293 | static void |
56be3814 | 294 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 JB |
295 | { |
296 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
297 | struct gdb_evrregset_t evrregs; | |
298 | ||
6ced10dd JB |
299 | gdb_assert (sizeof (evrregs.evr[0]) |
300 | == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum)); | |
301 | gdb_assert (sizeof (evrregs.acc) | |
302 | == register_size (current_gdbarch, tdep->ppc_acc_regnum)); | |
303 | gdb_assert (sizeof (evrregs.spefscr) | |
304 | == register_size (current_gdbarch, tdep->ppc_spefscr_regnum)); | |
305 | ||
01904826 JB |
306 | get_spe_registers (tid, &evrregs); |
307 | ||
6ced10dd | 308 | if (regno == -1) |
01904826 | 309 | { |
6ced10dd JB |
310 | int i; |
311 | ||
312 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 313 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 314 | &evrregs.evr[i]); |
01904826 | 315 | } |
6ced10dd JB |
316 | else if (tdep->ppc_ev0_upper_regnum <= regno |
317 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 318 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
319 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
320 | ||
321 | if (regno == -1 | |
322 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 323 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
324 | |
325 | if (regno == -1 | |
326 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 327 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 328 | &evrregs.spefscr); |
01904826 JB |
329 | } |
330 | ||
45229ea4 | 331 | static void |
56be3814 | 332 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 333 | { |
366f009f | 334 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 | 335 | /* This isn't really an address. But ptrace thinks of it as one. */ |
0397dee1 | 336 | CORE_ADDR regaddr = ppc_register_u_addr (regno); |
4a19ea35 | 337 | int bytes_transferred; |
45229ea4 | 338 | unsigned int offset; /* Offset of registers within the u area. */ |
d9d9c31f | 339 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 340 | |
9abe5450 EZ |
341 | if (altivec_register_p (regno)) |
342 | { | |
343 | /* If this is the first time through, or if it is not the first | |
344 | time through, and we have comfirmed that there is kernel | |
345 | support for such a ptrace request, then go and fetch the | |
346 | register. */ | |
347 | if (have_ptrace_getvrregs) | |
348 | { | |
56be3814 | 349 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
350 | return; |
351 | } | |
352 | /* If we have discovered that there is no ptrace support for | |
353 | AltiVec registers, fall through and return zeroes, because | |
354 | regaddr will be -1 in this case. */ | |
355 | } | |
01904826 JB |
356 | else if (spe_register_p (regno)) |
357 | { | |
56be3814 | 358 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
359 | return; |
360 | } | |
9abe5450 | 361 | |
45229ea4 EZ |
362 | if (regaddr == -1) |
363 | { | |
3acba339 | 364 | memset (buf, '\0', register_size (current_gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 365 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
366 | return; |
367 | } | |
368 | ||
411cb3f9 | 369 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
370 | 32-bit platform, 64-bit floating-point registers will require two |
371 | transfers. */ | |
4a19ea35 | 372 | for (bytes_transferred = 0; |
8327ccee | 373 | bytes_transferred < register_size (current_gdbarch, regno); |
411cb3f9 | 374 | bytes_transferred += sizeof (long)) |
45229ea4 EZ |
375 | { |
376 | errno = 0; | |
411cb3f9 PG |
377 | *(long *) &buf[bytes_transferred] |
378 | = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); | |
379 | regaddr += sizeof (long); | |
45229ea4 EZ |
380 | if (errno != 0) |
381 | { | |
bc97b3ba JB |
382 | char message[128]; |
383 | sprintf (message, "reading register %s (#%d)", | |
45229ea4 | 384 | REGISTER_NAME (regno), regno); |
bc97b3ba | 385 | perror_with_name (message); |
45229ea4 EZ |
386 | } |
387 | } | |
56d0d96a | 388 | |
4a19ea35 JB |
389 | /* Now supply the register. Keep in mind that the regcache's idea |
390 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 391 | (long). */ |
4a19ea35 JB |
392 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
393 | { | |
394 | /* Little-endian values are always found at the left end of the | |
395 | bytes transferred. */ | |
56be3814 | 396 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 JB |
397 | } |
398 | else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) | |
399 | { | |
400 | /* Big-endian values are found at the right end of the bytes | |
401 | transferred. */ | |
402 | size_t padding = (bytes_transferred | |
403 | - register_size (current_gdbarch, regno)); | |
56be3814 | 404 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
405 | } |
406 | else | |
a44bddec | 407 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 408 | _("fetch_register: unexpected byte order: %d"), |
a44bddec | 409 | gdbarch_byte_order (current_gdbarch)); |
45229ea4 EZ |
410 | } |
411 | ||
9abe5450 | 412 | static void |
56be3814 | 413 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
414 | { |
415 | int i; | |
416 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
417 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; | |
3acba339 AC |
418 | int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); |
419 | int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
420 | |
421 | for (i = 0; i < num_of_vrregs; i++) | |
422 | { | |
423 | /* The last 2 registers of this set are only 32 bit long, not | |
424 | 128. However an offset is necessary only for VSCR because it | |
425 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
426 | slot. */ | |
427 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 428 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 429 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 430 | else |
56be3814 | 431 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 432 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
433 | } |
434 | } | |
435 | ||
436 | static void | |
56be3814 | 437 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
438 | { |
439 | int ret; | |
440 | gdb_vrregset_t regs; | |
441 | ||
442 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
443 | if (ret < 0) | |
444 | { | |
445 | if (errno == EIO) | |
446 | { | |
447 | have_ptrace_getvrregs = 0; | |
448 | return; | |
449 | } | |
e2e0b3e5 | 450 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 451 | } |
56be3814 | 452 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
453 | } |
454 | ||
45229ea4 | 455 | static void |
56be3814 | 456 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
457 | { |
458 | int i; | |
9abe5450 EZ |
459 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
460 | ||
6ced10dd | 461 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 462 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
32b99774 JB |
463 | if (tdep->ppc_fp0_regnum >= 0) |
464 | for (i = 0; i < ppc_num_fprs; i++) | |
56be3814 UW |
465 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
466 | fetch_register (regcache, tid, PC_REGNUM); | |
32b99774 | 467 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 468 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 469 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 470 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 471 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 472 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 473 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 474 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 475 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 476 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 477 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 478 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 479 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 480 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
481 | if (have_ptrace_getvrregs) |
482 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 483 | fetch_altivec_registers (regcache, tid); |
6ced10dd | 484 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 485 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
486 | } |
487 | ||
488 | /* Fetch registers from the child process. Fetch all registers if | |
489 | regno == -1, otherwise fetch all general registers or all floating | |
490 | point registers depending upon the value of regno. */ | |
10d6c8cd | 491 | static void |
56be3814 | 492 | ppc_linux_fetch_inferior_registers (struct regcache *regcache, int regno) |
45229ea4 | 493 | { |
9abe5450 | 494 | /* Overload thread id onto process id */ |
05f13b9c EZ |
495 | int tid = TIDGET (inferior_ptid); |
496 | ||
497 | /* No thread id, just use process id */ | |
498 | if (tid == 0) | |
499 | tid = PIDGET (inferior_ptid); | |
500 | ||
9abe5450 | 501 | if (regno == -1) |
56be3814 | 502 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 503 | else |
56be3814 | 504 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
505 | } |
506 | ||
507 | /* Store one register. */ | |
9abe5450 | 508 | static void |
56be3814 | 509 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
510 | { |
511 | int ret; | |
512 | int offset = 0; | |
513 | gdb_vrregset_t regs; | |
514 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3acba339 | 515 | int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); |
9abe5450 EZ |
516 | |
517 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
518 | if (ret < 0) | |
519 | { | |
520 | if (errno == EIO) | |
521 | { | |
522 | have_ptrace_getvrregs = 0; | |
523 | return; | |
524 | } | |
e2e0b3e5 | 525 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
526 | } |
527 | ||
528 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
529 | long on the hardware. */ | |
530 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
3acba339 | 531 | offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 532 | |
56be3814 | 533 | regcache_raw_collect (regcache, regno, |
822c9732 | 534 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
535 | |
536 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
537 | if (ret < 0) | |
e2e0b3e5 | 538 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
539 | } |
540 | ||
01904826 JB |
541 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
542 | general-purpose registers and its SPE-specific registers to the | |
543 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
544 | nothing. | |
545 | ||
546 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
547 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
548 | get_spe_registers. */ | |
549 | static void | |
550 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
551 | { | |
552 | if (have_ptrace_getsetevrregs) | |
553 | { | |
554 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
555 | return; | |
556 | else | |
557 | { | |
558 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
559 | supported; we fail silently, and don't try the call | |
560 | again. */ | |
561 | if (errno == EIO) | |
562 | have_ptrace_getsetevrregs = 0; | |
563 | else | |
564 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 565 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
566 | } |
567 | } | |
568 | } | |
569 | ||
6ced10dd JB |
570 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
571 | If REGNO is -1, write the values of all the SPE-specific | |
572 | registers. */ | |
01904826 | 573 | static void |
56be3814 | 574 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 JB |
575 | { |
576 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
577 | struct gdb_evrregset_t evrregs; | |
578 | ||
6ced10dd JB |
579 | gdb_assert (sizeof (evrregs.evr[0]) |
580 | == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum)); | |
581 | gdb_assert (sizeof (evrregs.acc) | |
582 | == register_size (current_gdbarch, tdep->ppc_acc_regnum)); | |
583 | gdb_assert (sizeof (evrregs.spefscr) | |
584 | == register_size (current_gdbarch, tdep->ppc_spefscr_regnum)); | |
01904826 | 585 | |
6ced10dd JB |
586 | if (regno == -1) |
587 | /* Since we're going to write out every register, the code below | |
588 | should store to every field of evrregs; if that doesn't happen, | |
589 | make it obvious by initializing it with suspicious values. */ | |
590 | memset (&evrregs, 42, sizeof (evrregs)); | |
591 | else | |
592 | /* We can only read and write the entire EVR register set at a | |
593 | time, so to write just a single register, we do a | |
594 | read-modify-write maneuver. */ | |
595 | get_spe_registers (tid, &evrregs); | |
596 | ||
597 | if (regno == -1) | |
01904826 | 598 | { |
6ced10dd JB |
599 | int i; |
600 | ||
601 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 602 | regcache_raw_collect (regcache, |
6ced10dd JB |
603 | tdep->ppc_ev0_upper_regnum + i, |
604 | &evrregs.evr[i]); | |
01904826 | 605 | } |
6ced10dd JB |
606 | else if (tdep->ppc_ev0_upper_regnum <= regno |
607 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 608 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
609 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
610 | ||
611 | if (regno == -1 | |
612 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 613 | regcache_raw_collect (regcache, |
6ced10dd JB |
614 | tdep->ppc_acc_regnum, |
615 | &evrregs.acc); | |
616 | ||
617 | if (regno == -1 | |
618 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 619 | regcache_raw_collect (regcache, |
6ced10dd JB |
620 | tdep->ppc_spefscr_regnum, |
621 | &evrregs.spefscr); | |
01904826 JB |
622 | |
623 | /* Write back the modified register set. */ | |
624 | set_spe_registers (tid, &evrregs); | |
625 | } | |
626 | ||
45229ea4 | 627 | static void |
56be3814 | 628 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 629 | { |
366f009f | 630 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 EZ |
631 | /* This isn't really an address. But ptrace thinks of it as one. */ |
632 | CORE_ADDR regaddr = ppc_register_u_addr (regno); | |
52f0bd74 | 633 | int i; |
4a19ea35 | 634 | size_t bytes_to_transfer; |
d9d9c31f | 635 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 636 | |
9abe5450 | 637 | if (altivec_register_p (regno)) |
45229ea4 | 638 | { |
56be3814 | 639 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
640 | return; |
641 | } | |
01904826 JB |
642 | else if (spe_register_p (regno)) |
643 | { | |
56be3814 | 644 | store_spe_register (regcache, tid, regno); |
01904826 JB |
645 | return; |
646 | } | |
45229ea4 | 647 | |
9abe5450 EZ |
648 | if (regaddr == -1) |
649 | return; | |
650 | ||
4a19ea35 JB |
651 | /* First collect the register. Keep in mind that the regcache's |
652 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 653 | (long). */ |
56d0d96a | 654 | memset (buf, 0, sizeof buf); |
4a19ea35 | 655 | bytes_to_transfer = align_up (register_size (current_gdbarch, regno), |
411cb3f9 | 656 | sizeof (long)); |
4c6b5505 | 657 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
658 | { |
659 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 660 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 661 | } |
4c6b5505 | 662 | else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
663 | { |
664 | /* Big-endian values sit at the right end of the buffer. */ | |
665 | size_t padding = (bytes_to_transfer | |
666 | - register_size (current_gdbarch, regno)); | |
56be3814 | 667 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
668 | } |
669 | ||
411cb3f9 | 670 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 EZ |
671 | { |
672 | errno = 0; | |
411cb3f9 PG |
673 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, |
674 | *(long *) &buf[i]); | |
675 | regaddr += sizeof (long); | |
e3f36dbd KB |
676 | |
677 | if (errno == EIO | |
383f0f5b | 678 | && regno == tdep->ppc_fpscr_regnum) |
e3f36dbd KB |
679 | { |
680 | /* Some older kernel versions don't allow fpscr to be written. */ | |
681 | continue; | |
682 | } | |
683 | ||
45229ea4 EZ |
684 | if (errno != 0) |
685 | { | |
bc97b3ba JB |
686 | char message[128]; |
687 | sprintf (message, "writing register %s (#%d)", | |
45229ea4 | 688 | REGISTER_NAME (regno), regno); |
bc97b3ba | 689 | perror_with_name (message); |
45229ea4 EZ |
690 | } |
691 | } | |
692 | } | |
693 | ||
9abe5450 | 694 | static void |
56be3814 | 695 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
696 | { |
697 | int i; | |
698 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
699 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; | |
3acba339 AC |
700 | int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); |
701 | int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
702 | |
703 | for (i = 0; i < num_of_vrregs; i++) | |
704 | { | |
705 | /* The last 2 registers of this set are only 32 bit long, not | |
706 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
707 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 708 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 709 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 710 | else |
56be3814 | 711 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 712 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
713 | } |
714 | } | |
715 | ||
716 | static void | |
56be3814 | 717 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
718 | { |
719 | int ret; | |
720 | gdb_vrregset_t regs; | |
721 | ||
0897f59b | 722 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
723 | if (ret < 0) |
724 | { | |
725 | if (errno == EIO) | |
726 | { | |
727 | have_ptrace_getvrregs = 0; | |
728 | return; | |
729 | } | |
e2e0b3e5 | 730 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
731 | } |
732 | ||
56be3814 | 733 | fill_vrregset (regcache, ®s); |
9abe5450 | 734 | |
0897f59b | 735 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 736 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
737 | } |
738 | ||
45229ea4 | 739 | static void |
56be3814 | 740 | store_ppc_registers (const struct regcache *regcache, int tid) |
45229ea4 EZ |
741 | { |
742 | int i; | |
9abe5450 | 743 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 | 744 | |
6ced10dd | 745 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 746 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
32b99774 JB |
747 | if (tdep->ppc_fp0_regnum >= 0) |
748 | for (i = 0; i < ppc_num_fprs; i++) | |
56be3814 UW |
749 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
750 | store_register (regcache, tid, PC_REGNUM); | |
32b99774 | 751 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 752 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 753 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 754 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 755 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 756 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 757 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 758 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 759 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 760 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 761 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 762 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 763 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 764 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
765 | if (have_ptrace_getvrregs) |
766 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 767 | store_altivec_registers (regcache, tid); |
6ced10dd | 768 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 769 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
770 | } |
771 | ||
e0d24f8d WZ |
772 | static int |
773 | ppc_linux_check_watch_resources (int type, int cnt, int ot) | |
774 | { | |
775 | int tid; | |
776 | ptid_t ptid = inferior_ptid; | |
777 | ||
778 | /* DABR (data address breakpoint register) is optional for PPC variants. | |
779 | Some variants have one DABR, others have none. So CNT can't be larger | |
780 | than 1. */ | |
781 | if (cnt > 1) | |
782 | return 0; | |
783 | ||
784 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether | |
785 | the target has DABR. If either answer is no, the ptrace call will | |
786 | return -1. Fail in that case. */ | |
787 | tid = TIDGET (ptid); | |
788 | if (tid == 0) | |
789 | tid = PIDGET (ptid); | |
790 | ||
791 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
792 | return 0; | |
793 | return 1; | |
794 | } | |
795 | ||
796 | static int | |
797 | ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
798 | { | |
799 | /* Handle sub-8-byte quantities. */ | |
800 | if (len <= 0) | |
801 | return 0; | |
802 | ||
803 | /* addr+len must fall in the 8 byte watchable region. */ | |
804 | if ((addr + len) > (addr & ~7) + 8) | |
805 | return 0; | |
806 | ||
807 | return 1; | |
808 | } | |
809 | ||
810 | /* Set a watchpoint of type TYPE at address ADDR. */ | |
2c387241 | 811 | static int |
e0d24f8d WZ |
812 | ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw) |
813 | { | |
814 | int tid; | |
815 | long dabr_value; | |
816 | ptid_t ptid = inferior_ptid; | |
817 | ||
818 | dabr_value = addr & ~7; | |
819 | switch (rw) | |
820 | { | |
821 | case hw_read: | |
822 | /* Set read and translate bits. */ | |
823 | dabr_value |= 5; | |
824 | break; | |
825 | case hw_write: | |
826 | /* Set write and translate bits. */ | |
827 | dabr_value |= 6; | |
828 | break; | |
829 | case hw_access: | |
830 | /* Set read, write and translate bits. */ | |
831 | dabr_value |= 7; | |
832 | break; | |
833 | } | |
834 | ||
835 | tid = TIDGET (ptid); | |
836 | if (tid == 0) | |
837 | tid = PIDGET (ptid); | |
838 | ||
839 | return ptrace (PTRACE_SET_DEBUGREG, tid, 0, dabr_value); | |
840 | } | |
841 | ||
2c387241 AM |
842 | static int |
843 | ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw) | |
e0d24f8d WZ |
844 | { |
845 | int tid; | |
846 | ptid_t ptid = inferior_ptid; | |
847 | ||
848 | tid = TIDGET (ptid); | |
849 | if (tid == 0) | |
850 | tid = PIDGET (ptid); | |
851 | ||
852 | return ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0); | |
853 | } | |
854 | ||
855 | static int | |
856 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
857 | { | |
858 | if (last_stopped_data_address) | |
859 | { | |
860 | *addr_p = last_stopped_data_address; | |
861 | last_stopped_data_address = 0; | |
862 | return 1; | |
863 | } | |
864 | return 0; | |
865 | } | |
866 | ||
867 | static int | |
868 | ppc_linux_stopped_by_watchpoint (void) | |
869 | { | |
870 | int tid; | |
871 | struct siginfo siginfo; | |
872 | ptid_t ptid = inferior_ptid; | |
873 | CORE_ADDR *addr_p; | |
874 | ||
875 | tid = TIDGET(ptid); | |
876 | if (tid == 0) | |
877 | tid = PIDGET (ptid); | |
878 | ||
879 | errno = 0; | |
880 | ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo); | |
881 | ||
882 | if (errno != 0 || siginfo.si_signo != SIGTRAP || | |
883 | (siginfo.si_code & 0xffff) != 0x0004) | |
884 | return 0; | |
885 | ||
411cb3f9 | 886 | last_stopped_data_address = (uintptr_t) siginfo.si_addr; |
e0d24f8d WZ |
887 | return 1; |
888 | } | |
889 | ||
10d6c8cd | 890 | static void |
56be3814 | 891 | ppc_linux_store_inferior_registers (struct regcache *regcache, int regno) |
45229ea4 | 892 | { |
05f13b9c EZ |
893 | /* Overload thread id onto process id */ |
894 | int tid = TIDGET (inferior_ptid); | |
895 | ||
896 | /* No thread id, just use process id */ | |
897 | if (tid == 0) | |
898 | tid = PIDGET (inferior_ptid); | |
899 | ||
45229ea4 | 900 | if (regno >= 0) |
56be3814 | 901 | store_register (regcache, tid, regno); |
45229ea4 | 902 | else |
56be3814 | 903 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
904 | } |
905 | ||
50c9bd31 | 906 | void |
7f7fe91e | 907 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 908 | { |
f9be684a AC |
909 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
910 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 911 | int wordsize = sizeof (long); |
7f7fe91e | 912 | ppc_linux_supply_gregset (regcache, -1, gregsetp, |
f9be684a AC |
913 | sizeof (gdb_gregset_t), wordsize); |
914 | } | |
915 | ||
916 | static void | |
7f7fe91e | 917 | right_fill_reg (const struct regcache *regcache, int regnum, void *reg) |
f9be684a AC |
918 | { |
919 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace | |
920 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 921 | int wordsize = sizeof (long); |
f9be684a | 922 | /* Right fill the register. */ |
7f7fe91e | 923 | regcache_raw_collect (regcache, regnum, |
f9be684a AC |
924 | ((bfd_byte *) reg |
925 | + wordsize | |
926 | - register_size (current_gdbarch, regnum))); | |
c877c8e6 KB |
927 | } |
928 | ||
fdb28ac4 | 929 | void |
7f7fe91e UW |
930 | fill_gregset (const struct regcache *regcache, |
931 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 KB |
932 | { |
933 | int regi; | |
2ac44c70 | 934 | elf_greg_t *regp = (elf_greg_t *) gregsetp; |
dc5cfeb6 | 935 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
f9be684a AC |
936 | const int elf_ngreg = 48; |
937 | ||
938 | ||
939 | /* Start with zeros. */ | |
940 | memset (regp, 0, elf_ngreg * sizeof (*regp)); | |
fdb28ac4 | 941 | |
063715bf | 942 | for (regi = 0; regi < ppc_num_gprs; regi++) |
fdb28ac4 | 943 | { |
cdf2c5f5 | 944 | if ((regno == -1) || regno == tdep->ppc_gp0_regnum + regi) |
7f7fe91e UW |
945 | right_fill_reg (regcache, tdep->ppc_gp0_regnum + regi, |
946 | (regp + PT_R0 + regi)); | |
fdb28ac4 KB |
947 | } |
948 | ||
16333c4f | 949 | if ((regno == -1) || regno == PC_REGNUM) |
7f7fe91e | 950 | right_fill_reg (regcache, PC_REGNUM, regp + PT_NIP); |
05f13b9c | 951 | if ((regno == -1) || regno == tdep->ppc_lr_regnum) |
7f7fe91e | 952 | right_fill_reg (regcache, tdep->ppc_lr_regnum, regp + PT_LNK); |
05f13b9c | 953 | if ((regno == -1) || regno == tdep->ppc_cr_regnum) |
7f7fe91e | 954 | regcache_raw_collect (regcache, tdep->ppc_cr_regnum, |
822c9732 | 955 | regp + PT_CCR); |
05f13b9c | 956 | if ((regno == -1) || regno == tdep->ppc_xer_regnum) |
7f7fe91e | 957 | regcache_raw_collect (regcache, tdep->ppc_xer_regnum, |
822c9732 | 958 | regp + PT_XER); |
05f13b9c | 959 | if ((regno == -1) || regno == tdep->ppc_ctr_regnum) |
56be3814 | 960 | right_fill_reg (regcache, tdep->ppc_ctr_regnum, regp + PT_CTR); |
f8c59253 | 961 | #ifdef PT_MQ |
e3f36dbd KB |
962 | if (((regno == -1) || regno == tdep->ppc_mq_regnum) |
963 | && (tdep->ppc_mq_regnum != -1)) | |
7f7fe91e | 964 | right_fill_reg (regcache, tdep->ppc_mq_regnum, regp + PT_MQ); |
f8c59253 | 965 | #endif |
05f13b9c | 966 | if ((regno == -1) || regno == tdep->ppc_ps_regnum) |
7f7fe91e | 967 | right_fill_reg (regcache, tdep->ppc_ps_regnum, regp + PT_MSR); |
fdb28ac4 KB |
968 | } |
969 | ||
50c9bd31 | 970 | void |
7f7fe91e | 971 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 972 | { |
7f7fe91e | 973 | ppc_linux_supply_fpregset (NULL, regcache, -1, fpregsetp, |
f9be684a | 974 | sizeof (gdb_fpregset_t)); |
c877c8e6 | 975 | } |
fdb28ac4 | 976 | |
9abe5450 EZ |
977 | /* Given a pointer to a floating point register set in /proc format |
978 | (fpregset_t *), update the register specified by REGNO from gdb's | |
979 | idea of the current floating point register set. If REGNO is -1, | |
980 | update them all. */ | |
fdb28ac4 | 981 | void |
7f7fe91e UW |
982 | fill_fpregset (const struct regcache *regcache, |
983 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 KB |
984 | { |
985 | int regi; | |
e3f36dbd | 986 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
f9be684a | 987 | bfd_byte *fpp = (void *) fpregsetp; |
fdb28ac4 | 988 | |
383f0f5b | 989 | if (ppc_floating_point_unit_p (current_gdbarch)) |
fdb28ac4 | 990 | { |
383f0f5b JB |
991 | for (regi = 0; regi < ppc_num_fprs; regi++) |
992 | { | |
993 | if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi)) | |
7f7fe91e | 994 | regcache_raw_collect (regcache, tdep->ppc_fp0_regnum + regi, |
822c9732 | 995 | fpp + 8 * regi); |
383f0f5b JB |
996 | } |
997 | if (regno == -1 || regno == tdep->ppc_fpscr_regnum) | |
56be3814 | 998 | right_fill_reg (regcache, tdep->ppc_fpscr_regnum, (fpp + 8 * 32)); |
fdb28ac4 KB |
999 | } |
1000 | } | |
10d6c8cd DJ |
1001 | |
1002 | void _initialize_ppc_linux_nat (void); | |
1003 | ||
1004 | void | |
1005 | _initialize_ppc_linux_nat (void) | |
1006 | { | |
1007 | struct target_ops *t; | |
1008 | ||
1009 | /* Fill in the generic GNU/Linux methods. */ | |
1010 | t = linux_target (); | |
1011 | ||
1012 | /* Add our register access methods. */ | |
1013 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; | |
1014 | t->to_store_registers = ppc_linux_store_inferior_registers; | |
1015 | ||
e0d24f8d WZ |
1016 | /* Add our watchpoint methods. */ |
1017 | t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources; | |
1018 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; | |
1019 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; | |
1020 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; | |
1021 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; | |
1022 | t->to_stopped_data_address = ppc_linux_stopped_data_address; | |
1023 | ||
10d6c8cd | 1024 | /* Register the target. */ |
f973ed9c | 1025 | linux_nat_add_target (t); |
10d6c8cd | 1026 | } |