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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003, |
4 | 2004, 2005, 2006, 2007 Free Software Foundation, Inc. | |
c877c8e6 KB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
20 | |
21 | #include "defs.h" | |
e162d11b | 22 | #include "gdb_string.h" |
c877c8e6 KB |
23 | #include "frame.h" |
24 | #include "inferior.h" | |
25 | #include "gdbcore.h" | |
4e052eda | 26 | #include "regcache.h" |
383f0f5b | 27 | #include "gdb_assert.h" |
10d6c8cd DJ |
28 | #include "target.h" |
29 | #include "linux-nat.h" | |
c877c8e6 | 30 | |
411cb3f9 | 31 | #include <stdint.h> |
c877c8e6 KB |
32 | #include <sys/types.h> |
33 | #include <sys/param.h> | |
34 | #include <signal.h> | |
35 | #include <sys/user.h> | |
36 | #include <sys/ioctl.h> | |
2555fe1a | 37 | #include "gdb_wait.h" |
c877c8e6 KB |
38 | #include <fcntl.h> |
39 | #include <sys/procfs.h> | |
45229ea4 | 40 | #include <sys/ptrace.h> |
c877c8e6 | 41 | |
c60c0f5f MS |
42 | /* Prototypes for supply_gregset etc. */ |
43 | #include "gregset.h" | |
16333c4f | 44 | #include "ppc-tdep.h" |
c60c0f5f | 45 | |
9abe5450 EZ |
46 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
47 | configure time check. Some older glibc's (for instance 2.2.1) | |
48 | don't have a specific powerpc version of ptrace.h, and fall back on | |
49 | a generic one. In such cases, sys/ptrace.h defines | |
50 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
51 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
52 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
53 | much useless. */ | |
54 | ||
55 | /* These definitions should really come from the glibc header files, | |
56 | but Glibc doesn't know about the vrregs yet. */ | |
57 | #ifndef PTRACE_GETVRREGS | |
58 | #define PTRACE_GETVRREGS 18 | |
59 | #define PTRACE_SETVRREGS 19 | |
60 | #endif | |
61 | ||
01904826 JB |
62 | |
63 | /* Similarly for the ptrace requests for getting / setting the SPE | |
64 | registers (ev0 -- ev31, acc, and spefscr). See the description of | |
65 | gdb_evrregset_t for details. */ | |
66 | #ifndef PTRACE_GETEVRREGS | |
67 | #define PTRACE_GETEVRREGS 20 | |
68 | #define PTRACE_SETEVRREGS 21 | |
69 | #endif | |
70 | ||
e0d24f8d WZ |
71 | /* Similarly for the hardware watchpoint support. */ |
72 | #ifndef PTRACE_GET_DEBUGREG | |
73 | #define PTRACE_GET_DEBUGREG 25 | |
74 | #endif | |
75 | #ifndef PTRACE_SET_DEBUGREG | |
76 | #define PTRACE_SET_DEBUGREG 26 | |
77 | #endif | |
78 | #ifndef PTRACE_GETSIGINFO | |
79 | #define PTRACE_GETSIGINFO 0x4202 | |
80 | #endif | |
01904826 | 81 | |
9abe5450 EZ |
82 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
83 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
84 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
85 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
86 | flat array of chars, so that it is easier to manipulate for gdb. | |
87 | ||
88 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
89 | which is only 4 bytes long, but is fetched as a 16 bytes | |
90 | quantity. Up to here we have the elf_vrregset_t structure. | |
91 | Appended to this there is space for the VRSAVE register: 4 bytes. | |
92 | Even though this vrsave register is not included in the regset | |
93 | typedef, it is handled by the ptrace requests. | |
94 | ||
95 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
96 | therefore the offset at which the real value of the VSCR register | |
97 | is located will be always 12 bytes. | |
98 | ||
99 | The layout is like this (where x is the actual value of the vscr reg): */ | |
100 | ||
101 | /* *INDENT-OFF* */ | |
102 | /* | |
103 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
104 | <-------> <-------><-------><-> | |
105 | VR0 VR31 VSCR VRSAVE | |
106 | */ | |
107 | /* *INDENT-ON* */ | |
108 | ||
109 | #define SIZEOF_VRREGS 33*16+4 | |
110 | ||
111 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
112 | ||
01904826 JB |
113 | |
114 | /* On PPC processors that support the the Signal Processing Extension | |
115 | (SPE) APU, the general-purpose registers are 64 bits long. | |
411cb3f9 PG |
116 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
117 | ptrace calls only access the lower half of each register, to allow | |
118 | them to behave the same way they do on non-SPE systems. There's a | |
119 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
120 | read and write the top halves of all the general-purpose registers | |
121 | at once, along with some SPE-specific registers. | |
01904826 JB |
122 | |
123 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd JB |
124 | bits long. It has unnamed raw registers that hold the upper halves |
125 | of the gprs, and the the full 64-bit SIMD views of the registers, | |
126 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and | |
127 | bottom halves together. | |
01904826 JB |
128 | |
129 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
130 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
131 | struct gdb_evrregset_t | |
132 | { | |
133 | unsigned long evr[32]; | |
134 | unsigned long long acc; | |
135 | unsigned long spefscr; | |
136 | }; | |
137 | ||
138 | ||
139 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
140 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
141 | registers. Zero if we've tried one of them and gotten an | |
142 | error. */ | |
9abe5450 EZ |
143 | int have_ptrace_getvrregs = 1; |
144 | ||
e0d24f8d | 145 | static CORE_ADDR last_stopped_data_address = 0; |
01904826 JB |
146 | |
147 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and | |
148 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
149 | registers. Zero if we've tried one of them and gotten an | |
150 | error. */ | |
151 | int have_ptrace_getsetevrregs = 1; | |
152 | ||
16333c4f EZ |
153 | /* *INDENT-OFF* */ |
154 | /* registers layout, as presented by the ptrace interface: | |
155 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
156 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
157 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
158 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
159 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
160 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
161 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
162 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
163 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ | |
164 | /* *INDENT_ON * */ | |
c877c8e6 | 165 | |
45229ea4 EZ |
166 | static int |
167 | ppc_register_u_addr (int regno) | |
c877c8e6 | 168 | { |
16333c4f | 169 | int u_addr = -1; |
dc5cfeb6 | 170 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
56d0d96a AC |
171 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
172 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 173 | int wordsize = sizeof (long); |
16333c4f EZ |
174 | |
175 | /* General purpose registers occupy 1 slot each in the buffer */ | |
8bf659e8 JB |
176 | if (regno >= tdep->ppc_gp0_regnum |
177 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 178 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 179 | |
49ff75ad JB |
180 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
181 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
182 | slot each in 64-bit interface. */ | |
383f0f5b JB |
183 | if (tdep->ppc_fp0_regnum >= 0 |
184 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
185 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
186 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f EZ |
187 | |
188 | /* UISA special purpose registers: 1 slot each */ | |
3e8c568d | 189 | if (regno == gdbarch_pc_regnum (current_gdbarch)) |
49ff75ad | 190 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 191 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 192 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 193 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 194 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 195 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 196 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 197 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 198 | u_addr = PT_CTR * wordsize; |
f8c59253 | 199 | #ifdef PT_MQ |
dc5cfeb6 | 200 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 201 | u_addr = PT_MQ * wordsize; |
f8c59253 | 202 | #endif |
dc5cfeb6 | 203 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 204 | u_addr = PT_MSR * wordsize; |
383f0f5b JB |
205 | if (tdep->ppc_fpscr_regnum >= 0 |
206 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
207 | { |
208 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
209 | kernel headers incorrectly contained the 32-bit definition of | |
210 | PT_FPSCR. For the 32-bit definition, floating-point | |
211 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
212 | the secondhalf of such a slot-pair (hence +1). For 64-bit, | |
213 | the FPSCR instead occupies the full 64-bit 2-word-slot and | |
214 | hence no adjustment is necessary. Hack around this. */ | |
215 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
216 | u_addr = (48 + 32) * wordsize; | |
217 | else | |
218 | u_addr = PT_FPSCR * wordsize; | |
219 | } | |
16333c4f | 220 | return u_addr; |
c877c8e6 KB |
221 | } |
222 | ||
9abe5450 EZ |
223 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
224 | registers set mechanism, as opposed to the interface for all the | |
225 | other registers, that stores/fetches each register individually. */ | |
226 | static void | |
56be3814 | 227 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
228 | { |
229 | int ret; | |
230 | int offset = 0; | |
231 | gdb_vrregset_t regs; | |
232 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3acba339 | 233 | int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); |
9abe5450 EZ |
234 | |
235 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
236 | if (ret < 0) | |
237 | { | |
238 | if (errno == EIO) | |
239 | { | |
240 | have_ptrace_getvrregs = 0; | |
241 | return; | |
242 | } | |
e2e0b3e5 | 243 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
244 | } |
245 | ||
246 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
247 | long on the hardware. We deal only with the lower 4 bytes of the | |
248 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
249 | there is no need to define an offset for it. */ | |
250 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
3acba339 | 251 | offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 252 | |
56be3814 | 253 | regcache_raw_supply (regcache, regno, |
23a6d369 | 254 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
255 | } |
256 | ||
01904826 JB |
257 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
258 | SPE-specific registers, and place the results in EVRREGSET. If we | |
259 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
260 | zeros. | |
261 | ||
262 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
263 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
264 | set_spe_registers. */ | |
265 | static void | |
266 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
267 | { | |
268 | if (have_ptrace_getsetevrregs) | |
269 | { | |
270 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
271 | return; | |
272 | else | |
273 | { | |
274 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
275 | we just return zeros. */ | |
276 | if (errno == EIO) | |
277 | have_ptrace_getsetevrregs = 0; | |
278 | else | |
279 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 280 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
281 | } |
282 | } | |
283 | ||
284 | memset (evrregset, 0, sizeof (*evrregset)); | |
285 | } | |
286 | ||
6ced10dd JB |
287 | /* Supply values from TID for SPE-specific raw registers: the upper |
288 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
289 | be the number of an upper half register, acc, spefscr, or -1 to | |
290 | supply the values of all registers. */ | |
01904826 | 291 | static void |
56be3814 | 292 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 JB |
293 | { |
294 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
295 | struct gdb_evrregset_t evrregs; | |
296 | ||
6ced10dd JB |
297 | gdb_assert (sizeof (evrregs.evr[0]) |
298 | == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum)); | |
299 | gdb_assert (sizeof (evrregs.acc) | |
300 | == register_size (current_gdbarch, tdep->ppc_acc_regnum)); | |
301 | gdb_assert (sizeof (evrregs.spefscr) | |
302 | == register_size (current_gdbarch, tdep->ppc_spefscr_regnum)); | |
303 | ||
01904826 JB |
304 | get_spe_registers (tid, &evrregs); |
305 | ||
6ced10dd | 306 | if (regno == -1) |
01904826 | 307 | { |
6ced10dd JB |
308 | int i; |
309 | ||
310 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 311 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 312 | &evrregs.evr[i]); |
01904826 | 313 | } |
6ced10dd JB |
314 | else if (tdep->ppc_ev0_upper_regnum <= regno |
315 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 316 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
317 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
318 | ||
319 | if (regno == -1 | |
320 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 321 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
322 | |
323 | if (regno == -1 | |
324 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 325 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 326 | &evrregs.spefscr); |
01904826 JB |
327 | } |
328 | ||
45229ea4 | 329 | static void |
56be3814 | 330 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 331 | { |
366f009f | 332 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 | 333 | /* This isn't really an address. But ptrace thinks of it as one. */ |
0397dee1 | 334 | CORE_ADDR regaddr = ppc_register_u_addr (regno); |
4a19ea35 | 335 | int bytes_transferred; |
45229ea4 | 336 | unsigned int offset; /* Offset of registers within the u area. */ |
d9d9c31f | 337 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 338 | |
9abe5450 EZ |
339 | if (altivec_register_p (regno)) |
340 | { | |
341 | /* If this is the first time through, or if it is not the first | |
342 | time through, and we have comfirmed that there is kernel | |
343 | support for such a ptrace request, then go and fetch the | |
344 | register. */ | |
345 | if (have_ptrace_getvrregs) | |
346 | { | |
56be3814 | 347 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
348 | return; |
349 | } | |
350 | /* If we have discovered that there is no ptrace support for | |
351 | AltiVec registers, fall through and return zeroes, because | |
352 | regaddr will be -1 in this case. */ | |
353 | } | |
01904826 JB |
354 | else if (spe_register_p (regno)) |
355 | { | |
56be3814 | 356 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
357 | return; |
358 | } | |
9abe5450 | 359 | |
45229ea4 EZ |
360 | if (regaddr == -1) |
361 | { | |
3acba339 | 362 | memset (buf, '\0', register_size (current_gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 363 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
364 | return; |
365 | } | |
366 | ||
411cb3f9 | 367 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
368 | 32-bit platform, 64-bit floating-point registers will require two |
369 | transfers. */ | |
4a19ea35 | 370 | for (bytes_transferred = 0; |
8327ccee | 371 | bytes_transferred < register_size (current_gdbarch, regno); |
411cb3f9 | 372 | bytes_transferred += sizeof (long)) |
45229ea4 EZ |
373 | { |
374 | errno = 0; | |
411cb3f9 PG |
375 | *(long *) &buf[bytes_transferred] |
376 | = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); | |
377 | regaddr += sizeof (long); | |
45229ea4 EZ |
378 | if (errno != 0) |
379 | { | |
bc97b3ba JB |
380 | char message[128]; |
381 | sprintf (message, "reading register %s (#%d)", | |
c9f4d572 | 382 | gdbarch_register_name (current_gdbarch, regno), regno); |
bc97b3ba | 383 | perror_with_name (message); |
45229ea4 EZ |
384 | } |
385 | } | |
56d0d96a | 386 | |
4a19ea35 JB |
387 | /* Now supply the register. Keep in mind that the regcache's idea |
388 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 389 | (long). */ |
4a19ea35 JB |
390 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
391 | { | |
392 | /* Little-endian values are always found at the left end of the | |
393 | bytes transferred. */ | |
56be3814 | 394 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 JB |
395 | } |
396 | else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) | |
397 | { | |
398 | /* Big-endian values are found at the right end of the bytes | |
399 | transferred. */ | |
400 | size_t padding = (bytes_transferred | |
401 | - register_size (current_gdbarch, regno)); | |
56be3814 | 402 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
403 | } |
404 | else | |
a44bddec | 405 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 406 | _("fetch_register: unexpected byte order: %d"), |
a44bddec | 407 | gdbarch_byte_order (current_gdbarch)); |
45229ea4 EZ |
408 | } |
409 | ||
9abe5450 | 410 | static void |
56be3814 | 411 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
412 | { |
413 | int i; | |
414 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
415 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; | |
3acba339 AC |
416 | int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); |
417 | int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
418 | |
419 | for (i = 0; i < num_of_vrregs; i++) | |
420 | { | |
421 | /* The last 2 registers of this set are only 32 bit long, not | |
422 | 128. However an offset is necessary only for VSCR because it | |
423 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
424 | slot. */ | |
425 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 426 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 427 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 428 | else |
56be3814 | 429 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 430 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
431 | } |
432 | } | |
433 | ||
434 | static void | |
56be3814 | 435 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
436 | { |
437 | int ret; | |
438 | gdb_vrregset_t regs; | |
439 | ||
440 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
441 | if (ret < 0) | |
442 | { | |
443 | if (errno == EIO) | |
444 | { | |
445 | have_ptrace_getvrregs = 0; | |
446 | return; | |
447 | } | |
e2e0b3e5 | 448 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 449 | } |
56be3814 | 450 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
451 | } |
452 | ||
45229ea4 | 453 | static void |
56be3814 | 454 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
455 | { |
456 | int i; | |
9abe5450 EZ |
457 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
458 | ||
6ced10dd | 459 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 460 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
32b99774 JB |
461 | if (tdep->ppc_fp0_regnum >= 0) |
462 | for (i = 0; i < ppc_num_fprs; i++) | |
56be3814 | 463 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
3e8c568d | 464 | fetch_register (regcache, tid, gdbarch_pc_regnum (current_gdbarch)); |
32b99774 | 465 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 466 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 467 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 468 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 469 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 470 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 471 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 472 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 473 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 474 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 475 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 476 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 477 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 478 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
479 | if (have_ptrace_getvrregs) |
480 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 481 | fetch_altivec_registers (regcache, tid); |
6ced10dd | 482 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 483 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
484 | } |
485 | ||
486 | /* Fetch registers from the child process. Fetch all registers if | |
487 | regno == -1, otherwise fetch all general registers or all floating | |
488 | point registers depending upon the value of regno. */ | |
10d6c8cd | 489 | static void |
56be3814 | 490 | ppc_linux_fetch_inferior_registers (struct regcache *regcache, int regno) |
45229ea4 | 491 | { |
9abe5450 | 492 | /* Overload thread id onto process id */ |
05f13b9c EZ |
493 | int tid = TIDGET (inferior_ptid); |
494 | ||
495 | /* No thread id, just use process id */ | |
496 | if (tid == 0) | |
497 | tid = PIDGET (inferior_ptid); | |
498 | ||
9abe5450 | 499 | if (regno == -1) |
56be3814 | 500 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 501 | else |
56be3814 | 502 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
503 | } |
504 | ||
505 | /* Store one register. */ | |
9abe5450 | 506 | static void |
56be3814 | 507 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
508 | { |
509 | int ret; | |
510 | int offset = 0; | |
511 | gdb_vrregset_t regs; | |
512 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3acba339 | 513 | int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); |
9abe5450 EZ |
514 | |
515 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
516 | if (ret < 0) | |
517 | { | |
518 | if (errno == EIO) | |
519 | { | |
520 | have_ptrace_getvrregs = 0; | |
521 | return; | |
522 | } | |
e2e0b3e5 | 523 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
524 | } |
525 | ||
526 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
527 | long on the hardware. */ | |
528 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
3acba339 | 529 | offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 530 | |
56be3814 | 531 | regcache_raw_collect (regcache, regno, |
822c9732 | 532 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
533 | |
534 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
535 | if (ret < 0) | |
e2e0b3e5 | 536 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
537 | } |
538 | ||
01904826 JB |
539 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
540 | general-purpose registers and its SPE-specific registers to the | |
541 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
542 | nothing. | |
543 | ||
544 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
545 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
546 | get_spe_registers. */ | |
547 | static void | |
548 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
549 | { | |
550 | if (have_ptrace_getsetevrregs) | |
551 | { | |
552 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
553 | return; | |
554 | else | |
555 | { | |
556 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
557 | supported; we fail silently, and don't try the call | |
558 | again. */ | |
559 | if (errno == EIO) | |
560 | have_ptrace_getsetevrregs = 0; | |
561 | else | |
562 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 563 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
564 | } |
565 | } | |
566 | } | |
567 | ||
6ced10dd JB |
568 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
569 | If REGNO is -1, write the values of all the SPE-specific | |
570 | registers. */ | |
01904826 | 571 | static void |
56be3814 | 572 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 JB |
573 | { |
574 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
575 | struct gdb_evrregset_t evrregs; | |
576 | ||
6ced10dd JB |
577 | gdb_assert (sizeof (evrregs.evr[0]) |
578 | == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum)); | |
579 | gdb_assert (sizeof (evrregs.acc) | |
580 | == register_size (current_gdbarch, tdep->ppc_acc_regnum)); | |
581 | gdb_assert (sizeof (evrregs.spefscr) | |
582 | == register_size (current_gdbarch, tdep->ppc_spefscr_regnum)); | |
01904826 | 583 | |
6ced10dd JB |
584 | if (regno == -1) |
585 | /* Since we're going to write out every register, the code below | |
586 | should store to every field of evrregs; if that doesn't happen, | |
587 | make it obvious by initializing it with suspicious values. */ | |
588 | memset (&evrregs, 42, sizeof (evrregs)); | |
589 | else | |
590 | /* We can only read and write the entire EVR register set at a | |
591 | time, so to write just a single register, we do a | |
592 | read-modify-write maneuver. */ | |
593 | get_spe_registers (tid, &evrregs); | |
594 | ||
595 | if (regno == -1) | |
01904826 | 596 | { |
6ced10dd JB |
597 | int i; |
598 | ||
599 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 600 | regcache_raw_collect (regcache, |
6ced10dd JB |
601 | tdep->ppc_ev0_upper_regnum + i, |
602 | &evrregs.evr[i]); | |
01904826 | 603 | } |
6ced10dd JB |
604 | else if (tdep->ppc_ev0_upper_regnum <= regno |
605 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 606 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
607 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
608 | ||
609 | if (regno == -1 | |
610 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 611 | regcache_raw_collect (regcache, |
6ced10dd JB |
612 | tdep->ppc_acc_regnum, |
613 | &evrregs.acc); | |
614 | ||
615 | if (regno == -1 | |
616 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 617 | regcache_raw_collect (regcache, |
6ced10dd JB |
618 | tdep->ppc_spefscr_regnum, |
619 | &evrregs.spefscr); | |
01904826 JB |
620 | |
621 | /* Write back the modified register set. */ | |
622 | set_spe_registers (tid, &evrregs); | |
623 | } | |
624 | ||
45229ea4 | 625 | static void |
56be3814 | 626 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 627 | { |
366f009f | 628 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 EZ |
629 | /* This isn't really an address. But ptrace thinks of it as one. */ |
630 | CORE_ADDR regaddr = ppc_register_u_addr (regno); | |
52f0bd74 | 631 | int i; |
4a19ea35 | 632 | size_t bytes_to_transfer; |
d9d9c31f | 633 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 634 | |
9abe5450 | 635 | if (altivec_register_p (regno)) |
45229ea4 | 636 | { |
56be3814 | 637 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
638 | return; |
639 | } | |
01904826 JB |
640 | else if (spe_register_p (regno)) |
641 | { | |
56be3814 | 642 | store_spe_register (regcache, tid, regno); |
01904826 JB |
643 | return; |
644 | } | |
45229ea4 | 645 | |
9abe5450 EZ |
646 | if (regaddr == -1) |
647 | return; | |
648 | ||
4a19ea35 JB |
649 | /* First collect the register. Keep in mind that the regcache's |
650 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 651 | (long). */ |
56d0d96a | 652 | memset (buf, 0, sizeof buf); |
4a19ea35 | 653 | bytes_to_transfer = align_up (register_size (current_gdbarch, regno), |
411cb3f9 | 654 | sizeof (long)); |
4c6b5505 | 655 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
656 | { |
657 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 658 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 659 | } |
4c6b5505 | 660 | else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
661 | { |
662 | /* Big-endian values sit at the right end of the buffer. */ | |
663 | size_t padding = (bytes_to_transfer | |
664 | - register_size (current_gdbarch, regno)); | |
56be3814 | 665 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
666 | } |
667 | ||
411cb3f9 | 668 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 EZ |
669 | { |
670 | errno = 0; | |
411cb3f9 PG |
671 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, |
672 | *(long *) &buf[i]); | |
673 | regaddr += sizeof (long); | |
e3f36dbd KB |
674 | |
675 | if (errno == EIO | |
383f0f5b | 676 | && regno == tdep->ppc_fpscr_regnum) |
e3f36dbd KB |
677 | { |
678 | /* Some older kernel versions don't allow fpscr to be written. */ | |
679 | continue; | |
680 | } | |
681 | ||
45229ea4 EZ |
682 | if (errno != 0) |
683 | { | |
bc97b3ba JB |
684 | char message[128]; |
685 | sprintf (message, "writing register %s (#%d)", | |
c9f4d572 | 686 | gdbarch_register_name (current_gdbarch, regno), regno); |
bc97b3ba | 687 | perror_with_name (message); |
45229ea4 EZ |
688 | } |
689 | } | |
690 | } | |
691 | ||
9abe5450 | 692 | static void |
56be3814 | 693 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
694 | { |
695 | int i; | |
696 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
697 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; | |
3acba339 AC |
698 | int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); |
699 | int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
700 | |
701 | for (i = 0; i < num_of_vrregs; i++) | |
702 | { | |
703 | /* The last 2 registers of this set are only 32 bit long, not | |
704 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
705 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 706 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 707 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 708 | else |
56be3814 | 709 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 710 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
711 | } |
712 | } | |
713 | ||
714 | static void | |
56be3814 | 715 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
716 | { |
717 | int ret; | |
718 | gdb_vrregset_t regs; | |
719 | ||
0897f59b | 720 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
721 | if (ret < 0) |
722 | { | |
723 | if (errno == EIO) | |
724 | { | |
725 | have_ptrace_getvrregs = 0; | |
726 | return; | |
727 | } | |
e2e0b3e5 | 728 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
729 | } |
730 | ||
56be3814 | 731 | fill_vrregset (regcache, ®s); |
9abe5450 | 732 | |
0897f59b | 733 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 734 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
735 | } |
736 | ||
45229ea4 | 737 | static void |
56be3814 | 738 | store_ppc_registers (const struct regcache *regcache, int tid) |
45229ea4 EZ |
739 | { |
740 | int i; | |
9abe5450 | 741 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 | 742 | |
6ced10dd | 743 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 744 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
32b99774 JB |
745 | if (tdep->ppc_fp0_regnum >= 0) |
746 | for (i = 0; i < ppc_num_fprs; i++) | |
56be3814 | 747 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
3e8c568d | 748 | store_register (regcache, tid, gdbarch_pc_regnum (current_gdbarch)); |
32b99774 | 749 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 750 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 751 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 752 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 753 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 754 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 755 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 756 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 757 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 758 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 759 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 760 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 761 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 762 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
763 | if (have_ptrace_getvrregs) |
764 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 765 | store_altivec_registers (regcache, tid); |
6ced10dd | 766 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 767 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
768 | } |
769 | ||
e0d24f8d WZ |
770 | static int |
771 | ppc_linux_check_watch_resources (int type, int cnt, int ot) | |
772 | { | |
773 | int tid; | |
774 | ptid_t ptid = inferior_ptid; | |
775 | ||
776 | /* DABR (data address breakpoint register) is optional for PPC variants. | |
777 | Some variants have one DABR, others have none. So CNT can't be larger | |
778 | than 1. */ | |
779 | if (cnt > 1) | |
780 | return 0; | |
781 | ||
782 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether | |
783 | the target has DABR. If either answer is no, the ptrace call will | |
784 | return -1. Fail in that case. */ | |
785 | tid = TIDGET (ptid); | |
786 | if (tid == 0) | |
787 | tid = PIDGET (ptid); | |
788 | ||
789 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
790 | return 0; | |
791 | return 1; | |
792 | } | |
793 | ||
794 | static int | |
795 | ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
796 | { | |
797 | /* Handle sub-8-byte quantities. */ | |
798 | if (len <= 0) | |
799 | return 0; | |
800 | ||
801 | /* addr+len must fall in the 8 byte watchable region. */ | |
802 | if ((addr + len) > (addr & ~7) + 8) | |
803 | return 0; | |
804 | ||
805 | return 1; | |
806 | } | |
807 | ||
808 | /* Set a watchpoint of type TYPE at address ADDR. */ | |
2c387241 | 809 | static int |
e0d24f8d WZ |
810 | ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw) |
811 | { | |
812 | int tid; | |
813 | long dabr_value; | |
814 | ptid_t ptid = inferior_ptid; | |
815 | ||
816 | dabr_value = addr & ~7; | |
817 | switch (rw) | |
818 | { | |
819 | case hw_read: | |
820 | /* Set read and translate bits. */ | |
821 | dabr_value |= 5; | |
822 | break; | |
823 | case hw_write: | |
824 | /* Set write and translate bits. */ | |
825 | dabr_value |= 6; | |
826 | break; | |
827 | case hw_access: | |
828 | /* Set read, write and translate bits. */ | |
829 | dabr_value |= 7; | |
830 | break; | |
831 | } | |
832 | ||
833 | tid = TIDGET (ptid); | |
834 | if (tid == 0) | |
835 | tid = PIDGET (ptid); | |
836 | ||
837 | return ptrace (PTRACE_SET_DEBUGREG, tid, 0, dabr_value); | |
838 | } | |
839 | ||
2c387241 AM |
840 | static int |
841 | ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw) | |
e0d24f8d WZ |
842 | { |
843 | int tid; | |
844 | ptid_t ptid = inferior_ptid; | |
845 | ||
846 | tid = TIDGET (ptid); | |
847 | if (tid == 0) | |
848 | tid = PIDGET (ptid); | |
849 | ||
850 | return ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0); | |
851 | } | |
852 | ||
853 | static int | |
854 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
855 | { | |
856 | if (last_stopped_data_address) | |
857 | { | |
858 | *addr_p = last_stopped_data_address; | |
859 | last_stopped_data_address = 0; | |
860 | return 1; | |
861 | } | |
862 | return 0; | |
863 | } | |
864 | ||
865 | static int | |
866 | ppc_linux_stopped_by_watchpoint (void) | |
867 | { | |
868 | int tid; | |
869 | struct siginfo siginfo; | |
870 | ptid_t ptid = inferior_ptid; | |
871 | CORE_ADDR *addr_p; | |
872 | ||
873 | tid = TIDGET(ptid); | |
874 | if (tid == 0) | |
875 | tid = PIDGET (ptid); | |
876 | ||
877 | errno = 0; | |
878 | ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo); | |
879 | ||
880 | if (errno != 0 || siginfo.si_signo != SIGTRAP || | |
881 | (siginfo.si_code & 0xffff) != 0x0004) | |
882 | return 0; | |
883 | ||
411cb3f9 | 884 | last_stopped_data_address = (uintptr_t) siginfo.si_addr; |
e0d24f8d WZ |
885 | return 1; |
886 | } | |
887 | ||
10d6c8cd | 888 | static void |
56be3814 | 889 | ppc_linux_store_inferior_registers (struct regcache *regcache, int regno) |
45229ea4 | 890 | { |
05f13b9c EZ |
891 | /* Overload thread id onto process id */ |
892 | int tid = TIDGET (inferior_ptid); | |
893 | ||
894 | /* No thread id, just use process id */ | |
895 | if (tid == 0) | |
896 | tid = PIDGET (inferior_ptid); | |
897 | ||
45229ea4 | 898 | if (regno >= 0) |
56be3814 | 899 | store_register (regcache, tid, regno); |
45229ea4 | 900 | else |
56be3814 | 901 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
902 | } |
903 | ||
f2db237a AM |
904 | /* Functions for transferring registers between a gregset_t or fpregset_t |
905 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
906 | by the ptrace interface, not the current program's ABI. eg. If a | |
907 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we | |
908 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
909 | ||
50c9bd31 | 910 | void |
7f7fe91e | 911 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 912 | { |
f2db237a | 913 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 914 | |
f2db237a | 915 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
916 | } |
917 | ||
fdb28ac4 | 918 | void |
7f7fe91e UW |
919 | fill_gregset (const struct regcache *regcache, |
920 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 921 | { |
f2db237a | 922 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 923 | |
f2db237a AM |
924 | if (regno == -1) |
925 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
926 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
927 | } |
928 | ||
50c9bd31 | 929 | void |
7f7fe91e | 930 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 931 | { |
f2db237a AM |
932 | const struct regset *regset = ppc_linux_fpregset (); |
933 | ||
934 | ppc_supply_fpregset (regset, regcache, -1, | |
935 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 936 | } |
fdb28ac4 | 937 | |
fdb28ac4 | 938 | void |
7f7fe91e UW |
939 | fill_fpregset (const struct regcache *regcache, |
940 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 941 | { |
f2db237a AM |
942 | const struct regset *regset = ppc_linux_fpregset (); |
943 | ||
944 | ppc_collect_fpregset (regset, regcache, regno, | |
945 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 946 | } |
10d6c8cd DJ |
947 | |
948 | void _initialize_ppc_linux_nat (void); | |
949 | ||
950 | void | |
951 | _initialize_ppc_linux_nat (void) | |
952 | { | |
953 | struct target_ops *t; | |
954 | ||
955 | /* Fill in the generic GNU/Linux methods. */ | |
956 | t = linux_target (); | |
957 | ||
958 | /* Add our register access methods. */ | |
959 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; | |
960 | t->to_store_registers = ppc_linux_store_inferior_registers; | |
961 | ||
e0d24f8d WZ |
962 | /* Add our watchpoint methods. */ |
963 | t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources; | |
964 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; | |
965 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; | |
966 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; | |
967 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; | |
968 | t->to_stopped_data_address = ppc_linux_stopped_data_address; | |
969 | ||
10d6c8cd | 970 | /* Register the target. */ |
f973ed9c | 971 | linux_nat_add_target (t); |
10d6c8cd | 972 | } |