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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
ecd75fc8 | 3 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
c877c8e6 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
19 | |
20 | #include "defs.h" | |
0e9f083f | 21 | #include <string.h> |
6ffbb7ab | 22 | #include "observer.h" |
c877c8e6 KB |
23 | #include "frame.h" |
24 | #include "inferior.h" | |
6ffbb7ab | 25 | #include "gdbthread.h" |
c877c8e6 | 26 | #include "gdbcore.h" |
4e052eda | 27 | #include "regcache.h" |
383f0f5b | 28 | #include "gdb_assert.h" |
10d6c8cd DJ |
29 | #include "target.h" |
30 | #include "linux-nat.h" | |
c877c8e6 | 31 | |
411cb3f9 | 32 | #include <stdint.h> |
c877c8e6 | 33 | #include <sys/types.h> |
c877c8e6 KB |
34 | #include <signal.h> |
35 | #include <sys/user.h> | |
36 | #include <sys/ioctl.h> | |
2555fe1a | 37 | #include "gdb_wait.h" |
c877c8e6 KB |
38 | #include <fcntl.h> |
39 | #include <sys/procfs.h> | |
45229ea4 | 40 | #include <sys/ptrace.h> |
c877c8e6 | 41 | |
0df8b418 | 42 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 43 | #include "gregset.h" |
16333c4f | 44 | #include "ppc-tdep.h" |
7284e1be UW |
45 | #include "ppc-linux-tdep.h" |
46 | ||
b7622095 LM |
47 | /* Required when using the AUXV. */ |
48 | #include "elf/common.h" | |
49 | #include "auxv.h" | |
50 | ||
7284e1be UW |
51 | /* This sometimes isn't defined. */ |
52 | #ifndef PT_ORIG_R3 | |
53 | #define PT_ORIG_R3 34 | |
54 | #endif | |
55 | #ifndef PT_TRAP | |
56 | #define PT_TRAP 40 | |
57 | #endif | |
c60c0f5f | 58 | |
69abc51c TJB |
59 | /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>. |
60 | If they aren't, we can provide them ourselves (their values are fixed | |
61 | because they are part of the kernel ABI). They are used in the AT_HWCAP | |
62 | entry of the AUXV. */ | |
f4d9bade UW |
63 | #ifndef PPC_FEATURE_CELL |
64 | #define PPC_FEATURE_CELL 0x00010000 | |
65 | #endif | |
b7622095 LM |
66 | #ifndef PPC_FEATURE_BOOKE |
67 | #define PPC_FEATURE_BOOKE 0x00008000 | |
68 | #endif | |
f04c6d38 TJB |
69 | #ifndef PPC_FEATURE_HAS_DFP |
70 | #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */ | |
69abc51c | 71 | #endif |
b7622095 | 72 | |
9abe5450 EZ |
73 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
74 | configure time check. Some older glibc's (for instance 2.2.1) | |
75 | don't have a specific powerpc version of ptrace.h, and fall back on | |
76 | a generic one. In such cases, sys/ptrace.h defines | |
77 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
78 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
79 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
80 | much useless. */ | |
81 | ||
82 | /* These definitions should really come from the glibc header files, | |
83 | but Glibc doesn't know about the vrregs yet. */ | |
84 | #ifndef PTRACE_GETVRREGS | |
85 | #define PTRACE_GETVRREGS 18 | |
86 | #define PTRACE_SETVRREGS 19 | |
87 | #endif | |
88 | ||
604c2f83 LM |
89 | /* PTRACE requests for POWER7 VSX registers. */ |
90 | #ifndef PTRACE_GETVSXREGS | |
91 | #define PTRACE_GETVSXREGS 27 | |
92 | #define PTRACE_SETVSXREGS 28 | |
93 | #endif | |
01904826 JB |
94 | |
95 | /* Similarly for the ptrace requests for getting / setting the SPE | |
96 | registers (ev0 -- ev31, acc, and spefscr). See the description of | |
97 | gdb_evrregset_t for details. */ | |
98 | #ifndef PTRACE_GETEVRREGS | |
99 | #define PTRACE_GETEVRREGS 20 | |
100 | #define PTRACE_SETEVRREGS 21 | |
101 | #endif | |
102 | ||
6ffbb7ab | 103 | /* Similarly for the hardware watchpoint support. These requests are used |
926bf92d | 104 | when the PowerPC HWDEBUG ptrace interface is not available. */ |
e0d24f8d WZ |
105 | #ifndef PTRACE_GET_DEBUGREG |
106 | #define PTRACE_GET_DEBUGREG 25 | |
107 | #endif | |
108 | #ifndef PTRACE_SET_DEBUGREG | |
109 | #define PTRACE_SET_DEBUGREG 26 | |
110 | #endif | |
111 | #ifndef PTRACE_GETSIGINFO | |
112 | #define PTRACE_GETSIGINFO 0x4202 | |
113 | #endif | |
01904826 | 114 | |
926bf92d UW |
115 | /* These requests are used when the PowerPC HWDEBUG ptrace interface is |
116 | available. It exposes the debug facilities of PowerPC processors, as well | |
117 | as additional features of BookE processors, such as ranged breakpoints and | |
118 | watchpoints and hardware-accelerated condition evaluation. */ | |
6ffbb7ab TJB |
119 | #ifndef PPC_PTRACE_GETHWDBGINFO |
120 | ||
926bf92d UW |
121 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG |
122 | ptrace interface is not present in ptrace.h, so we'll have to pretty much | |
123 | include it all here so that the code at least compiles on older systems. */ | |
6ffbb7ab TJB |
124 | #define PPC_PTRACE_GETHWDBGINFO 0x89 |
125 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
126 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
127 | ||
128 | struct ppc_debug_info | |
129 | { | |
0df8b418 | 130 | uint32_t version; /* Only version 1 exists to date. */ |
6ffbb7ab TJB |
131 | uint32_t num_instruction_bps; |
132 | uint32_t num_data_bps; | |
133 | uint32_t num_condition_regs; | |
134 | uint32_t data_bp_alignment; | |
0df8b418 | 135 | uint32_t sizeof_condition; /* size of the DVC register. */ |
6ffbb7ab TJB |
136 | uint64_t features; |
137 | }; | |
138 | ||
139 | /* Features will have bits indicating whether there is support for: */ | |
140 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
141 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
142 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
143 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
144 | ||
145 | struct ppc_hw_breakpoint | |
146 | { | |
147 | uint32_t version; /* currently, version must be 1 */ | |
148 | uint32_t trigger_type; /* only some combinations allowed */ | |
149 | uint32_t addr_mode; /* address match mode */ | |
150 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
151 | uint64_t addr; /* break/watchpoint address */ | |
152 | uint64_t addr2; /* range end or mask */ | |
153 | uint64_t condition_value; /* contents of the DVC register */ | |
154 | }; | |
155 | ||
156 | /* Trigger type. */ | |
157 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
158 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
159 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
160 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
161 | ||
162 | /* Address mode. */ | |
163 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
164 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
165 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
166 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
167 | ||
168 | /* Condition mode. */ | |
169 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
170 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
171 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
172 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
173 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
174 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
175 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
176 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
177 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) | |
178 | #endif /* PPC_PTRACE_GETHWDBGINFO */ | |
179 | ||
e23b9d6e UW |
180 | /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider |
181 | watchpoint (up to 512 bytes). */ | |
182 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR | |
183 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | |
184 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */ | |
6ffbb7ab | 185 | |
1dfe79e8 SDJ |
186 | /* Similarly for the general-purpose (gp0 -- gp31) |
187 | and floating-point registers (fp0 -- fp31). */ | |
188 | #ifndef PTRACE_GETREGS | |
189 | #define PTRACE_GETREGS 12 | |
190 | #endif | |
191 | #ifndef PTRACE_SETREGS | |
192 | #define PTRACE_SETREGS 13 | |
193 | #endif | |
194 | #ifndef PTRACE_GETFPREGS | |
195 | #define PTRACE_GETFPREGS 14 | |
196 | #endif | |
197 | #ifndef PTRACE_SETFPREGS | |
198 | #define PTRACE_SETFPREGS 15 | |
199 | #endif | |
200 | ||
9abe5450 EZ |
201 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
202 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
203 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
204 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
205 | flat array of chars, so that it is easier to manipulate for gdb. | |
206 | ||
207 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
208 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 209 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
210 | Appended to this there is space for the VRSAVE register: 4 bytes. |
211 | Even though this vrsave register is not included in the regset | |
212 | typedef, it is handled by the ptrace requests. | |
213 | ||
214 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
215 | therefore the offset at which the real value of the VSCR register | |
216 | is located will be always 12 bytes. | |
217 | ||
218 | The layout is like this (where x is the actual value of the vscr reg): */ | |
219 | ||
220 | /* *INDENT-OFF* */ | |
221 | /* | |
222 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
223 | <-------> <-------><-------><-> | |
224 | VR0 VR31 VSCR VRSAVE | |
225 | */ | |
226 | /* *INDENT-ON* */ | |
227 | ||
228 | #define SIZEOF_VRREGS 33*16+4 | |
229 | ||
230 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
231 | ||
604c2f83 LM |
232 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
233 | with the existing FPR and VMX registers. | |
234 | ||
235 | VSR doubleword 0 VSR doubleword 1 | |
236 | ---------------------------------------------------------------- | |
237 | VSR[0] | FPR[0] | | | |
238 | ---------------------------------------------------------------- | |
239 | VSR[1] | FPR[1] | | | |
240 | ---------------------------------------------------------------- | |
241 | | ... | | | |
242 | | ... | | | |
243 | ---------------------------------------------------------------- | |
244 | VSR[30] | FPR[30] | | | |
245 | ---------------------------------------------------------------- | |
246 | VSR[31] | FPR[31] | | | |
247 | ---------------------------------------------------------------- | |
248 | VSR[32] | VR[0] | | |
249 | ---------------------------------------------------------------- | |
250 | VSR[33] | VR[1] | | |
251 | ---------------------------------------------------------------- | |
252 | | ... | | |
253 | | ... | | |
254 | ---------------------------------------------------------------- | |
255 | VSR[62] | VR[30] | | |
256 | ---------------------------------------------------------------- | |
257 | VSR[63] | VR[31] | | |
258 | ---------------------------------------------------------------- | |
259 | ||
260 | VSX has 64 128bit registers. The first 32 registers overlap with | |
261 | the FP registers (doubleword 0) and hence extend them with additional | |
262 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
263 | registers. */ | |
264 | #define SIZEOF_VSXREGS 32*8 | |
265 | ||
266 | typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; | |
01904826 | 267 | |
b021a221 | 268 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 269 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
270 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
271 | ptrace calls only access the lower half of each register, to allow | |
272 | them to behave the same way they do on non-SPE systems. There's a | |
273 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
274 | read and write the top halves of all the general-purpose registers | |
275 | at once, along with some SPE-specific registers. | |
01904826 JB |
276 | |
277 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 278 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 279 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
280 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
281 | bottom halves together. | |
01904826 JB |
282 | |
283 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
284 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
285 | struct gdb_evrregset_t | |
286 | { | |
287 | unsigned long evr[32]; | |
288 | unsigned long long acc; | |
289 | unsigned long spefscr; | |
290 | }; | |
291 | ||
604c2f83 LM |
292 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
293 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
294 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
295 | gotten an error. Note that VSX registers 32 through 63 overlap | |
296 | with VR registers 0 through 31. */ | |
297 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
298 | |
299 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
300 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
301 | registers. Zero if we've tried one of them and gotten an | |
302 | error. */ | |
9abe5450 EZ |
303 | int have_ptrace_getvrregs = 1; |
304 | ||
01904826 JB |
305 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
306 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
307 | registers. Zero if we've tried one of them and gotten an | |
308 | error. */ | |
309 | int have_ptrace_getsetevrregs = 1; | |
310 | ||
1dfe79e8 SDJ |
311 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
312 | PTRACE_SETREGS requests, for reading and writing the | |
313 | general-purpose registers. Zero if we've tried one of | |
314 | them and gotten an error. */ | |
315 | int have_ptrace_getsetregs = 1; | |
316 | ||
317 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
318 | PTRACE_SETFPREGS requests, for reading and writing the | |
319 | floating-pointers registers. Zero if we've tried one of | |
320 | them and gotten an error. */ | |
321 | int have_ptrace_getsetfpregs = 1; | |
322 | ||
16333c4f EZ |
323 | /* *INDENT-OFF* */ |
324 | /* registers layout, as presented by the ptrace interface: | |
325 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
326 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
327 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
328 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
329 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
330 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
331 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
332 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
333 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
334 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
335 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
336 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f EZ |
337 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
338 | /* *INDENT_ON * */ | |
c877c8e6 | 339 | |
45229ea4 | 340 | static int |
e101270f | 341 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 342 | { |
16333c4f | 343 | int u_addr = -1; |
e101270f | 344 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
345 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
346 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 347 | int wordsize = sizeof (long); |
16333c4f | 348 | |
0df8b418 | 349 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
350 | if (regno >= tdep->ppc_gp0_regnum |
351 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 352 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 353 | |
49ff75ad JB |
354 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
355 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
356 | slot each in 64-bit interface. */ | |
383f0f5b JB |
357 | if (tdep->ppc_fp0_regnum >= 0 |
358 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
359 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
360 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 361 | |
0df8b418 | 362 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 363 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 364 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 365 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 366 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 367 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 368 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 369 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 370 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 371 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 372 | u_addr = PT_CTR * wordsize; |
f8c59253 | 373 | #ifdef PT_MQ |
dc5cfeb6 | 374 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 375 | u_addr = PT_MQ * wordsize; |
f8c59253 | 376 | #endif |
dc5cfeb6 | 377 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 378 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
379 | if (regno == PPC_ORIG_R3_REGNUM) |
380 | u_addr = PT_ORIG_R3 * wordsize; | |
381 | if (regno == PPC_TRAP_REGNUM) | |
382 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
383 | if (tdep->ppc_fpscr_regnum >= 0 |
384 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
385 | { |
386 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
387 | kernel headers incorrectly contained the 32-bit definition of | |
388 | PT_FPSCR. For the 32-bit definition, floating-point | |
389 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 390 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
391 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
392 | hence no adjustment is necessary. Hack around this. */ | |
393 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
394 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
395 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
396 | slot and not just its second word. The PT_FPSCR supplied when | |
397 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
398 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
399 | && PT_FPSCR == (48 + 2*32 + 1)) | |
400 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
401 | else |
402 | u_addr = PT_FPSCR * wordsize; | |
403 | } | |
16333c4f | 404 | return u_addr; |
c877c8e6 KB |
405 | } |
406 | ||
604c2f83 LM |
407 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
408 | registers set mechanism, as opposed to the interface for all the | |
409 | other registers, that stores/fetches each register individually. */ | |
410 | static void | |
411 | fetch_vsx_register (struct regcache *regcache, int tid, int regno) | |
412 | { | |
413 | int ret; | |
414 | gdb_vsxregset_t regs; | |
415 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
416 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
417 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
418 | ||
419 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
420 | if (ret < 0) | |
421 | { | |
422 | if (errno == EIO) | |
423 | { | |
424 | have_ptrace_getsetvsxregs = 0; | |
425 | return; | |
426 | } | |
427 | perror_with_name (_("Unable to fetch VSX register")); | |
428 | } | |
429 | ||
430 | regcache_raw_supply (regcache, regno, | |
431 | regs + (regno - tdep->ppc_vsr0_upper_regnum) | |
432 | * vsxregsize); | |
433 | } | |
434 | ||
9abe5450 EZ |
435 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
436 | registers set mechanism, as opposed to the interface for all the | |
437 | other registers, that stores/fetches each register individually. */ | |
438 | static void | |
56be3814 | 439 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
440 | { |
441 | int ret; | |
442 | int offset = 0; | |
443 | gdb_vrregset_t regs; | |
40a6adc1 MD |
444 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
445 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
446 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
447 | |
448 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
449 | if (ret < 0) | |
450 | { | |
451 | if (errno == EIO) | |
452 | { | |
453 | have_ptrace_getvrregs = 0; | |
454 | return; | |
455 | } | |
e2e0b3e5 | 456 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
457 | } |
458 | ||
459 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
460 | long on the hardware. We deal only with the lower 4 bytes of the | |
461 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
462 | there is no need to define an offset for it. */ | |
463 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 464 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 465 | |
56be3814 | 466 | regcache_raw_supply (regcache, regno, |
0df8b418 MS |
467 | regs + (regno |
468 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
469 | } |
470 | ||
01904826 JB |
471 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
472 | SPE-specific registers, and place the results in EVRREGSET. If we | |
473 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
474 | zeros. | |
475 | ||
476 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
477 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
478 | set_spe_registers. */ | |
479 | static void | |
480 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
481 | { | |
482 | if (have_ptrace_getsetevrregs) | |
483 | { | |
484 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
485 | return; | |
486 | else | |
487 | { | |
488 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
489 | we just return zeros. */ | |
490 | if (errno == EIO) | |
491 | have_ptrace_getsetevrregs = 0; | |
492 | else | |
493 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 494 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
495 | } |
496 | } | |
497 | ||
498 | memset (evrregset, 0, sizeof (*evrregset)); | |
499 | } | |
500 | ||
6ced10dd JB |
501 | /* Supply values from TID for SPE-specific raw registers: the upper |
502 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
503 | be the number of an upper half register, acc, spefscr, or -1 to | |
504 | supply the values of all registers. */ | |
01904826 | 505 | static void |
56be3814 | 506 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 507 | { |
40a6adc1 MD |
508 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
509 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
510 | struct gdb_evrregset_t evrregs; |
511 | ||
6ced10dd | 512 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 513 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 514 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 515 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 516 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 517 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 518 | |
01904826 JB |
519 | get_spe_registers (tid, &evrregs); |
520 | ||
6ced10dd | 521 | if (regno == -1) |
01904826 | 522 | { |
6ced10dd JB |
523 | int i; |
524 | ||
525 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 526 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 527 | &evrregs.evr[i]); |
01904826 | 528 | } |
6ced10dd JB |
529 | else if (tdep->ppc_ev0_upper_regnum <= regno |
530 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 531 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
532 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
533 | ||
534 | if (regno == -1 | |
535 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 536 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
537 | |
538 | if (regno == -1 | |
539 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 540 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 541 | &evrregs.spefscr); |
01904826 JB |
542 | } |
543 | ||
45229ea4 | 544 | static void |
56be3814 | 545 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 546 | { |
40a6adc1 MD |
547 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
548 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 549 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 550 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 551 | int bytes_transferred; |
0df8b418 | 552 | unsigned int offset; /* Offset of registers within the u area. */ |
e362b510 | 553 | gdb_byte buf[MAX_REGISTER_SIZE]; |
45229ea4 | 554 | |
be8626e0 | 555 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
556 | { |
557 | /* If this is the first time through, or if it is not the first | |
558 | time through, and we have comfirmed that there is kernel | |
559 | support for such a ptrace request, then go and fetch the | |
560 | register. */ | |
561 | if (have_ptrace_getvrregs) | |
562 | { | |
56be3814 | 563 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
564 | return; |
565 | } | |
566 | /* If we have discovered that there is no ptrace support for | |
567 | AltiVec registers, fall through and return zeroes, because | |
568 | regaddr will be -1 in this case. */ | |
569 | } | |
604c2f83 LM |
570 | if (vsx_register_p (gdbarch, regno)) |
571 | { | |
572 | if (have_ptrace_getsetvsxregs) | |
573 | { | |
574 | fetch_vsx_register (regcache, tid, regno); | |
575 | return; | |
576 | } | |
577 | } | |
be8626e0 | 578 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 579 | { |
56be3814 | 580 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
581 | return; |
582 | } | |
9abe5450 | 583 | |
45229ea4 EZ |
584 | if (regaddr == -1) |
585 | { | |
40a6adc1 | 586 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 587 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
588 | return; |
589 | } | |
590 | ||
411cb3f9 | 591 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
592 | 32-bit platform, 64-bit floating-point registers will require two |
593 | transfers. */ | |
4a19ea35 | 594 | for (bytes_transferred = 0; |
40a6adc1 | 595 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 596 | bytes_transferred += sizeof (long)) |
45229ea4 | 597 | { |
11fde611 JK |
598 | long l; |
599 | ||
45229ea4 | 600 | errno = 0; |
11fde611 | 601 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 602 | regaddr += sizeof (long); |
45229ea4 EZ |
603 | if (errno != 0) |
604 | { | |
bc97b3ba | 605 | char message[128]; |
8c042590 PM |
606 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
607 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 608 | perror_with_name (message); |
45229ea4 | 609 | } |
11fde611 | 610 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 611 | } |
56d0d96a | 612 | |
4a19ea35 JB |
613 | /* Now supply the register. Keep in mind that the regcache's idea |
614 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 615 | (long). */ |
40a6adc1 | 616 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
617 | { |
618 | /* Little-endian values are always found at the left end of the | |
619 | bytes transferred. */ | |
56be3814 | 620 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 | 621 | } |
40a6adc1 | 622 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
623 | { |
624 | /* Big-endian values are found at the right end of the bytes | |
625 | transferred. */ | |
40a6adc1 | 626 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
56be3814 | 627 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
628 | } |
629 | else | |
a44bddec | 630 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 631 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 632 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
633 | } |
634 | ||
604c2f83 LM |
635 | static void |
636 | supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
637 | { | |
638 | int i; | |
639 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
640 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
641 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
642 | ||
643 | for (i = 0; i < ppc_num_vshrs; i++) | |
644 | { | |
645 | regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
646 | *vsxregsetp + i * vsxregsize); | |
647 | } | |
648 | } | |
649 | ||
9abe5450 | 650 | static void |
56be3814 | 651 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
652 | { |
653 | int i; | |
40a6adc1 MD |
654 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
655 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 656 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
657 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
658 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
659 | |
660 | for (i = 0; i < num_of_vrregs; i++) | |
661 | { | |
662 | /* The last 2 registers of this set are only 32 bit long, not | |
663 | 128. However an offset is necessary only for VSCR because it | |
664 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
665 | slot. */ | |
666 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 667 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 668 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 669 | else |
56be3814 | 670 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 671 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
672 | } |
673 | } | |
674 | ||
604c2f83 LM |
675 | static void |
676 | fetch_vsx_registers (struct regcache *regcache, int tid) | |
677 | { | |
678 | int ret; | |
679 | gdb_vsxregset_t regs; | |
680 | ||
681 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
682 | if (ret < 0) | |
683 | { | |
684 | if (errno == EIO) | |
685 | { | |
686 | have_ptrace_getsetvsxregs = 0; | |
687 | return; | |
688 | } | |
689 | perror_with_name (_("Unable to fetch VSX registers")); | |
690 | } | |
691 | supply_vsxregset (regcache, ®s); | |
692 | } | |
693 | ||
9abe5450 | 694 | static void |
56be3814 | 695 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
696 | { |
697 | int ret; | |
698 | gdb_vrregset_t regs; | |
699 | ||
700 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
701 | if (ret < 0) | |
702 | { | |
703 | if (errno == EIO) | |
704 | { | |
705 | have_ptrace_getvrregs = 0; | |
706 | return; | |
707 | } | |
e2e0b3e5 | 708 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 709 | } |
56be3814 | 710 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
711 | } |
712 | ||
1dfe79e8 SDJ |
713 | /* This function actually issues the request to ptrace, telling |
714 | it to get all general-purpose registers and put them into the | |
715 | specified regset. | |
716 | ||
717 | If the ptrace request does not exist, this function returns 0 | |
718 | and properly sets the have_ptrace_* flag. If the request fails, | |
719 | this function calls perror_with_name. Otherwise, if the request | |
720 | succeeds, then the regcache gets filled and 1 is returned. */ | |
721 | static int | |
722 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
723 | { | |
724 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
725 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
726 | gdb_gregset_t gregset; | |
727 | ||
728 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
729 | { | |
730 | if (errno == EIO) | |
731 | { | |
732 | have_ptrace_getsetregs = 0; | |
733 | return 0; | |
734 | } | |
735 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
736 | } | |
737 | ||
738 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
739 | ||
740 | return 1; | |
741 | } | |
742 | ||
743 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
744 | responsible for verifying if this target has the ptrace request | |
745 | that can be used to fetch all general-purpose registers at one | |
746 | shot. If it doesn't, then we should fetch them using the | |
747 | old-fashioned way, which is to iterate over the registers and | |
748 | request them one by one. */ | |
749 | static void | |
750 | fetch_gp_regs (struct regcache *regcache, int tid) | |
751 | { | |
752 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
753 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
754 | int i; | |
755 | ||
756 | if (have_ptrace_getsetregs) | |
757 | if (fetch_all_gp_regs (regcache, tid)) | |
758 | return; | |
759 | ||
760 | /* If we've hit this point, it doesn't really matter which | |
761 | architecture we are using. We just need to read the | |
762 | registers in the "old-fashioned way". */ | |
763 | for (i = 0; i < ppc_num_gprs; i++) | |
764 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
765 | } | |
766 | ||
767 | /* This function actually issues the request to ptrace, telling | |
768 | it to get all floating-point registers and put them into the | |
769 | specified regset. | |
770 | ||
771 | If the ptrace request does not exist, this function returns 0 | |
772 | and properly sets the have_ptrace_* flag. If the request fails, | |
773 | this function calls perror_with_name. Otherwise, if the request | |
774 | succeeds, then the regcache gets filled and 1 is returned. */ | |
775 | static int | |
776 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
777 | { | |
778 | gdb_fpregset_t fpregs; | |
779 | ||
780 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
781 | { | |
782 | if (errno == EIO) | |
783 | { | |
784 | have_ptrace_getsetfpregs = 0; | |
785 | return 0; | |
786 | } | |
787 | perror_with_name (_("Couldn't get floating-point registers.")); | |
788 | } | |
789 | ||
790 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
791 | ||
792 | return 1; | |
793 | } | |
794 | ||
795 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
796 | responsible for verifying if this target has the ptrace request | |
797 | that can be used to fetch all floating-point registers at one | |
798 | shot. If it doesn't, then we should fetch them using the | |
799 | old-fashioned way, which is to iterate over the registers and | |
800 | request them one by one. */ | |
801 | static void | |
802 | fetch_fp_regs (struct regcache *regcache, int tid) | |
803 | { | |
804 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
805 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
806 | int i; | |
807 | ||
808 | if (have_ptrace_getsetfpregs) | |
809 | if (fetch_all_fp_regs (regcache, tid)) | |
810 | return; | |
811 | ||
812 | /* If we've hit this point, it doesn't really matter which | |
813 | architecture we are using. We just need to read the | |
814 | registers in the "old-fashioned way". */ | |
815 | for (i = 0; i < ppc_num_fprs; i++) | |
816 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
817 | } | |
818 | ||
45229ea4 | 819 | static void |
56be3814 | 820 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
821 | { |
822 | int i; | |
40a6adc1 MD |
823 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
824 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 825 | |
1dfe79e8 | 826 | fetch_gp_regs (regcache, tid); |
32b99774 | 827 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 828 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 829 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 830 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 831 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 832 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 833 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 834 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 835 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 836 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 837 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 838 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 839 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 840 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 841 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
842 | if (ppc_linux_trap_reg_p (gdbarch)) |
843 | { | |
844 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
845 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
846 | } | |
32b99774 | 847 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 848 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
849 | if (have_ptrace_getvrregs) |
850 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 851 | fetch_altivec_registers (regcache, tid); |
604c2f83 LM |
852 | if (have_ptrace_getsetvsxregs) |
853 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
854 | fetch_vsx_registers (regcache, tid); | |
6ced10dd | 855 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 856 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
857 | } |
858 | ||
859 | /* Fetch registers from the child process. Fetch all registers if | |
860 | regno == -1, otherwise fetch all general registers or all floating | |
861 | point registers depending upon the value of regno. */ | |
10d6c8cd | 862 | static void |
28439f5e PA |
863 | ppc_linux_fetch_inferior_registers (struct target_ops *ops, |
864 | struct regcache *regcache, int regno) | |
45229ea4 | 865 | { |
0df8b418 | 866 | /* Overload thread id onto process id. */ |
dfd4cc63 | 867 | int tid = ptid_get_lwp (inferior_ptid); |
05f13b9c | 868 | |
0df8b418 | 869 | /* No thread id, just use process id. */ |
05f13b9c | 870 | if (tid == 0) |
dfd4cc63 | 871 | tid = ptid_get_pid (inferior_ptid); |
05f13b9c | 872 | |
9abe5450 | 873 | if (regno == -1) |
56be3814 | 874 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 875 | else |
56be3814 | 876 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
877 | } |
878 | ||
0df8b418 | 879 | /* Store one VSX register. */ |
604c2f83 LM |
880 | static void |
881 | store_vsx_register (const struct regcache *regcache, int tid, int regno) | |
882 | { | |
883 | int ret; | |
884 | gdb_vsxregset_t regs; | |
885 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
886 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
887 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
888 | ||
9fe70b4f | 889 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
890 | if (ret < 0) |
891 | { | |
892 | if (errno == EIO) | |
893 | { | |
894 | have_ptrace_getsetvsxregs = 0; | |
895 | return; | |
896 | } | |
897 | perror_with_name (_("Unable to fetch VSX register")); | |
898 | } | |
899 | ||
900 | regcache_raw_collect (regcache, regno, regs + | |
901 | (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); | |
902 | ||
903 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
904 | if (ret < 0) | |
905 | perror_with_name (_("Unable to store VSX register")); | |
906 | } | |
907 | ||
0df8b418 | 908 | /* Store one register. */ |
9abe5450 | 909 | static void |
56be3814 | 910 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
911 | { |
912 | int ret; | |
913 | int offset = 0; | |
914 | gdb_vrregset_t regs; | |
40a6adc1 MD |
915 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
916 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
917 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
918 | |
919 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
920 | if (ret < 0) | |
921 | { | |
922 | if (errno == EIO) | |
923 | { | |
924 | have_ptrace_getvrregs = 0; | |
925 | return; | |
926 | } | |
e2e0b3e5 | 927 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
928 | } |
929 | ||
930 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
931 | long on the hardware. */ | |
932 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 933 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 934 | |
56be3814 | 935 | regcache_raw_collect (regcache, regno, |
0df8b418 MS |
936 | regs + (regno |
937 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
938 | |
939 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
940 | if (ret < 0) | |
e2e0b3e5 | 941 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
942 | } |
943 | ||
01904826 JB |
944 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
945 | general-purpose registers and its SPE-specific registers to the | |
946 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
947 | nothing. | |
948 | ||
949 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
950 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
951 | get_spe_registers. */ | |
952 | static void | |
953 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
954 | { | |
955 | if (have_ptrace_getsetevrregs) | |
956 | { | |
957 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
958 | return; | |
959 | else | |
960 | { | |
961 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
962 | supported; we fail silently, and don't try the call | |
963 | again. */ | |
964 | if (errno == EIO) | |
965 | have_ptrace_getsetevrregs = 0; | |
966 | else | |
967 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 968 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
969 | } |
970 | } | |
971 | } | |
972 | ||
6ced10dd JB |
973 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
974 | If REGNO is -1, write the values of all the SPE-specific | |
975 | registers. */ | |
01904826 | 976 | static void |
56be3814 | 977 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 978 | { |
40a6adc1 MD |
979 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
980 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
981 | struct gdb_evrregset_t evrregs; |
982 | ||
6ced10dd | 983 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 984 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 985 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 986 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 987 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 988 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 989 | |
6ced10dd JB |
990 | if (regno == -1) |
991 | /* Since we're going to write out every register, the code below | |
992 | should store to every field of evrregs; if that doesn't happen, | |
993 | make it obvious by initializing it with suspicious values. */ | |
994 | memset (&evrregs, 42, sizeof (evrregs)); | |
995 | else | |
996 | /* We can only read and write the entire EVR register set at a | |
997 | time, so to write just a single register, we do a | |
998 | read-modify-write maneuver. */ | |
999 | get_spe_registers (tid, &evrregs); | |
1000 | ||
1001 | if (regno == -1) | |
01904826 | 1002 | { |
6ced10dd JB |
1003 | int i; |
1004 | ||
1005 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 1006 | regcache_raw_collect (regcache, |
6ced10dd JB |
1007 | tdep->ppc_ev0_upper_regnum + i, |
1008 | &evrregs.evr[i]); | |
01904826 | 1009 | } |
6ced10dd JB |
1010 | else if (tdep->ppc_ev0_upper_regnum <= regno |
1011 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 1012 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
1013 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
1014 | ||
1015 | if (regno == -1 | |
1016 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 1017 | regcache_raw_collect (regcache, |
6ced10dd JB |
1018 | tdep->ppc_acc_regnum, |
1019 | &evrregs.acc); | |
1020 | ||
1021 | if (regno == -1 | |
1022 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 1023 | regcache_raw_collect (regcache, |
6ced10dd JB |
1024 | tdep->ppc_spefscr_regnum, |
1025 | &evrregs.spefscr); | |
01904826 JB |
1026 | |
1027 | /* Write back the modified register set. */ | |
1028 | set_spe_registers (tid, &evrregs); | |
1029 | } | |
1030 | ||
45229ea4 | 1031 | static void |
56be3814 | 1032 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1033 | { |
40a6adc1 MD |
1034 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1035 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 1036 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 1037 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 1038 | int i; |
4a19ea35 | 1039 | size_t bytes_to_transfer; |
e362b510 | 1040 | gdb_byte buf[MAX_REGISTER_SIZE]; |
45229ea4 | 1041 | |
be8626e0 | 1042 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 1043 | { |
56be3814 | 1044 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
1045 | return; |
1046 | } | |
604c2f83 LM |
1047 | if (vsx_register_p (gdbarch, regno)) |
1048 | { | |
1049 | store_vsx_register (regcache, tid, regno); | |
1050 | return; | |
1051 | } | |
be8626e0 | 1052 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 1053 | { |
56be3814 | 1054 | store_spe_register (regcache, tid, regno); |
01904826 JB |
1055 | return; |
1056 | } | |
45229ea4 | 1057 | |
9abe5450 EZ |
1058 | if (regaddr == -1) |
1059 | return; | |
1060 | ||
4a19ea35 JB |
1061 | /* First collect the register. Keep in mind that the regcache's |
1062 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1063 | (long). */ |
56d0d96a | 1064 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
1065 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
1066 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
1067 | { |
1068 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 1069 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 1070 | } |
40a6adc1 | 1071 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1072 | { |
1073 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 1074 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
56be3814 | 1075 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
1076 | } |
1077 | ||
411cb3f9 | 1078 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 1079 | { |
11fde611 JK |
1080 | long l; |
1081 | ||
1082 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 1083 | errno = 0; |
11fde611 | 1084 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 1085 | regaddr += sizeof (long); |
e3f36dbd KB |
1086 | |
1087 | if (errno == EIO | |
7284e1be UW |
1088 | && (regno == tdep->ppc_fpscr_regnum |
1089 | || regno == PPC_ORIG_R3_REGNUM | |
1090 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1091 | { |
7284e1be UW |
1092 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1093 | or trap to be written. */ | |
e3f36dbd KB |
1094 | continue; |
1095 | } | |
1096 | ||
45229ea4 EZ |
1097 | if (errno != 0) |
1098 | { | |
bc97b3ba | 1099 | char message[128]; |
8c042590 PM |
1100 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
1101 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 1102 | perror_with_name (message); |
45229ea4 EZ |
1103 | } |
1104 | } | |
1105 | } | |
1106 | ||
604c2f83 LM |
1107 | static void |
1108 | fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
1109 | { | |
1110 | int i; | |
1111 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1112 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1113 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
1114 | ||
1115 | for (i = 0; i < ppc_num_vshrs; i++) | |
1116 | regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
1117 | *vsxregsetp + i * vsxregsize); | |
1118 | } | |
1119 | ||
9abe5450 | 1120 | static void |
56be3814 | 1121 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
1122 | { |
1123 | int i; | |
40a6adc1 MD |
1124 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1125 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 1126 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
1127 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
1128 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
1129 | |
1130 | for (i = 0; i < num_of_vrregs; i++) | |
1131 | { | |
1132 | /* The last 2 registers of this set are only 32 bit long, not | |
1133 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
1134 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 1135 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1136 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 1137 | else |
56be3814 | 1138 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1139 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
1140 | } |
1141 | } | |
1142 | ||
604c2f83 LM |
1143 | static void |
1144 | store_vsx_registers (const struct regcache *regcache, int tid) | |
1145 | { | |
1146 | int ret; | |
1147 | gdb_vsxregset_t regs; | |
1148 | ||
1149 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
1150 | if (ret < 0) | |
1151 | { | |
1152 | if (errno == EIO) | |
1153 | { | |
1154 | have_ptrace_getsetvsxregs = 0; | |
1155 | return; | |
1156 | } | |
1157 | perror_with_name (_("Couldn't get VSX registers")); | |
1158 | } | |
1159 | ||
1160 | fill_vsxregset (regcache, ®s); | |
1161 | ||
1162 | if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) | |
1163 | perror_with_name (_("Couldn't write VSX registers")); | |
1164 | } | |
1165 | ||
9abe5450 | 1166 | static void |
56be3814 | 1167 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
1168 | { |
1169 | int ret; | |
1170 | gdb_vrregset_t regs; | |
1171 | ||
0897f59b | 1172 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
1173 | if (ret < 0) |
1174 | { | |
1175 | if (errno == EIO) | |
1176 | { | |
1177 | have_ptrace_getvrregs = 0; | |
1178 | return; | |
1179 | } | |
e2e0b3e5 | 1180 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
1181 | } |
1182 | ||
56be3814 | 1183 | fill_vrregset (regcache, ®s); |
9abe5450 | 1184 | |
0897f59b | 1185 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 1186 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
1187 | } |
1188 | ||
1dfe79e8 SDJ |
1189 | /* This function actually issues the request to ptrace, telling |
1190 | it to store all general-purpose registers present in the specified | |
1191 | regset. | |
1192 | ||
1193 | If the ptrace request does not exist, this function returns 0 | |
1194 | and properly sets the have_ptrace_* flag. If the request fails, | |
1195 | this function calls perror_with_name. Otherwise, if the request | |
1196 | succeeds, then the regcache is stored and 1 is returned. */ | |
1197 | static int | |
1198 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1199 | { | |
1200 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1201 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1202 | gdb_gregset_t gregset; | |
1203 | ||
1204 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1205 | { | |
1206 | if (errno == EIO) | |
1207 | { | |
1208 | have_ptrace_getsetregs = 0; | |
1209 | return 0; | |
1210 | } | |
1211 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1212 | } | |
1213 | ||
1214 | fill_gregset (regcache, &gregset, regno); | |
1215 | ||
1216 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1217 | { | |
1218 | if (errno == EIO) | |
1219 | { | |
1220 | have_ptrace_getsetregs = 0; | |
1221 | return 0; | |
1222 | } | |
1223 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1224 | } | |
1225 | ||
1226 | return 1; | |
1227 | } | |
1228 | ||
1229 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1230 | responsible for verifying if this target has the ptrace request | |
1231 | that can be used to store all general-purpose registers at one | |
1232 | shot. If it doesn't, then we should store them using the | |
1233 | old-fashioned way, which is to iterate over the registers and | |
1234 | store them one by one. */ | |
45229ea4 | 1235 | static void |
1dfe79e8 | 1236 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1237 | { |
40a6adc1 MD |
1238 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1239 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dfe79e8 SDJ |
1240 | int i; |
1241 | ||
1242 | if (have_ptrace_getsetregs) | |
1243 | if (store_all_gp_regs (regcache, tid, regno)) | |
1244 | return; | |
1245 | ||
1246 | /* If we hit this point, it doesn't really matter which | |
1247 | architecture we are using. We just need to store the | |
1248 | registers in the "old-fashioned way". */ | |
6ced10dd | 1249 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1250 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1251 | } |
1252 | ||
1253 | /* This function actually issues the request to ptrace, telling | |
1254 | it to store all floating-point registers present in the specified | |
1255 | regset. | |
1256 | ||
1257 | If the ptrace request does not exist, this function returns 0 | |
1258 | and properly sets the have_ptrace_* flag. If the request fails, | |
1259 | this function calls perror_with_name. Otherwise, if the request | |
1260 | succeeds, then the regcache is stored and 1 is returned. */ | |
1261 | static int | |
1262 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1263 | { | |
1264 | gdb_fpregset_t fpregs; | |
1265 | ||
1266 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1267 | { | |
1268 | if (errno == EIO) | |
1269 | { | |
1270 | have_ptrace_getsetfpregs = 0; | |
1271 | return 0; | |
1272 | } | |
1273 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1274 | } | |
1275 | ||
1276 | fill_fpregset (regcache, &fpregs, regno); | |
1277 | ||
1278 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1279 | { | |
1280 | if (errno == EIO) | |
1281 | { | |
1282 | have_ptrace_getsetfpregs = 0; | |
1283 | return 0; | |
1284 | } | |
1285 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1286 | } | |
1287 | ||
1288 | return 1; | |
1289 | } | |
1290 | ||
1291 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1292 | responsible for verifying if this target has the ptrace request | |
1293 | that can be used to store all floating-point registers at one | |
1294 | shot. If it doesn't, then we should store them using the | |
1295 | old-fashioned way, which is to iterate over the registers and | |
1296 | store them one by one. */ | |
1297 | static void | |
1298 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1299 | { | |
1300 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1301 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1302 | int i; | |
1303 | ||
1304 | if (have_ptrace_getsetfpregs) | |
1305 | if (store_all_fp_regs (regcache, tid, regno)) | |
1306 | return; | |
1307 | ||
1308 | /* If we hit this point, it doesn't really matter which | |
1309 | architecture we are using. We just need to store the | |
1310 | registers in the "old-fashioned way". */ | |
1311 | for (i = 0; i < ppc_num_fprs; i++) | |
1312 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1313 | } | |
1314 | ||
1315 | static void | |
1316 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1317 | { | |
1318 | int i; | |
1319 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1320 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1321 | ||
1322 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1323 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1324 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1325 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1326 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1327 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1328 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1329 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1330 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1331 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1332 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1333 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1334 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1335 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1336 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1337 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1338 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1339 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1340 | if (ppc_linux_trap_reg_p (gdbarch)) |
1341 | { | |
1342 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1343 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1344 | } | |
9abe5450 EZ |
1345 | if (have_ptrace_getvrregs) |
1346 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 1347 | store_altivec_registers (regcache, tid); |
604c2f83 LM |
1348 | if (have_ptrace_getsetvsxregs) |
1349 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
1350 | store_vsx_registers (regcache, tid); | |
6ced10dd | 1351 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1352 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
1353 | } |
1354 | ||
6ffbb7ab | 1355 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
b261e0c5 UW |
1356 | static unsigned long |
1357 | ppc_linux_get_hwcap (void) | |
6ffbb7ab TJB |
1358 | { |
1359 | CORE_ADDR field; | |
1360 | ||
1361 | if (target_auxv_search (¤t_target, AT_HWCAP, &field)) | |
1362 | return (unsigned long) field; | |
1363 | ||
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | /* The cached DABR value, to install in new threads. | |
926bf92d UW |
1368 | This variable is used when the PowerPC HWDEBUG ptrace |
1369 | interface is not available. */ | |
6ffbb7ab TJB |
1370 | static long saved_dabr_value; |
1371 | ||
1372 | /* Global structure that will store information about the available | |
926bf92d UW |
1373 | features provided by the PowerPC HWDEBUG ptrace interface. */ |
1374 | static struct ppc_debug_info hwdebug_info; | |
6ffbb7ab TJB |
1375 | |
1376 | /* Global variable that holds the maximum number of slots that the | |
926bf92d UW |
1377 | kernel will use. This is only used when PowerPC HWDEBUG ptrace interface |
1378 | is available. */ | |
6ffbb7ab TJB |
1379 | static size_t max_slots_number = 0; |
1380 | ||
1381 | struct hw_break_tuple | |
1382 | { | |
1383 | long slot; | |
1384 | struct ppc_hw_breakpoint *hw_break; | |
1385 | }; | |
1386 | ||
1387 | /* This is an internal VEC created to store information about *points inserted | |
926bf92d UW |
1388 | for each thread. This is used when PowerPC HWDEBUG ptrace interface is |
1389 | available. */ | |
6ffbb7ab TJB |
1390 | typedef struct thread_points |
1391 | { | |
1392 | /* The TID to which this *point relates. */ | |
1393 | int tid; | |
1394 | /* Information about the *point, such as its address, type, etc. | |
1395 | ||
1396 | Each element inside this vector corresponds to a hardware | |
1397 | breakpoint or watchpoint in the thread represented by TID. The maximum | |
1398 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of | |
1399 | the tuple is NULL, then the position in the vector is free. */ | |
1400 | struct hw_break_tuple *hw_breaks; | |
1401 | } *thread_points_p; | |
1402 | DEF_VEC_P (thread_points_p); | |
1403 | ||
1404 | VEC(thread_points_p) *ppc_threads = NULL; | |
1405 | ||
926bf92d UW |
1406 | /* The version of the PowerPC HWDEBUG kernel interface that we will use, if |
1407 | available. */ | |
6ffbb7ab TJB |
1408 | #define PPC_DEBUG_CURRENT_VERSION 1 |
1409 | ||
926bf92d | 1410 | /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */ |
e0d24f8d | 1411 | static int |
926bf92d | 1412 | have_ptrace_hwdebug_interface (void) |
e0d24f8d | 1413 | { |
926bf92d | 1414 | static int have_ptrace_hwdebug_interface = -1; |
e0d24f8d | 1415 | |
926bf92d | 1416 | if (have_ptrace_hwdebug_interface == -1) |
6ffbb7ab TJB |
1417 | { |
1418 | int tid; | |
e0d24f8d | 1419 | |
dfd4cc63 | 1420 | tid = ptid_get_lwp (inferior_ptid); |
6ffbb7ab | 1421 | if (tid == 0) |
dfd4cc63 | 1422 | tid = ptid_get_pid (inferior_ptid); |
e0d24f8d | 1423 | |
926bf92d UW |
1424 | /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ |
1425 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) | |
6ffbb7ab | 1426 | { |
926bf92d | 1427 | /* Check whether PowerPC HWDEBUG ptrace interface is functional and |
0c56f59b | 1428 | provides any supported feature. */ |
926bf92d | 1429 | if (hwdebug_info.features != 0) |
0c56f59b | 1430 | { |
926bf92d UW |
1431 | have_ptrace_hwdebug_interface = 1; |
1432 | max_slots_number = hwdebug_info.num_instruction_bps | |
1433 | + hwdebug_info.num_data_bps | |
1434 | + hwdebug_info.num_condition_regs; | |
1435 | return have_ptrace_hwdebug_interface; | |
0c56f59b | 1436 | } |
6ffbb7ab | 1437 | } |
926bf92d UW |
1438 | /* Old school interface and no PowerPC HWDEBUG ptrace support. */ |
1439 | have_ptrace_hwdebug_interface = 0; | |
1440 | memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info)); | |
6ffbb7ab TJB |
1441 | } |
1442 | ||
926bf92d | 1443 | return have_ptrace_hwdebug_interface; |
e0d24f8d WZ |
1444 | } |
1445 | ||
6ffbb7ab | 1446 | static int |
5461485a TT |
1447 | ppc_linux_can_use_hw_breakpoint (struct target_ops *self, |
1448 | int type, int cnt, int ot) | |
b7622095 | 1449 | { |
6ffbb7ab | 1450 | int total_hw_wp, total_hw_bp; |
b7622095 | 1451 | |
926bf92d | 1452 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab | 1453 | { |
926bf92d UW |
1454 | /* When PowerPC HWDEBUG ptrace interface is available, the number of |
1455 | available hardware watchpoints and breakpoints is stored at the | |
1456 | hwdebug_info struct. */ | |
1457 | total_hw_bp = hwdebug_info.num_instruction_bps; | |
1458 | total_hw_wp = hwdebug_info.num_data_bps; | |
6ffbb7ab TJB |
1459 | } |
1460 | else | |
1461 | { | |
926bf92d UW |
1462 | /* When we do not have PowerPC HWDEBUG ptrace interface, we should |
1463 | consider having 1 hardware watchpoint and no hardware breakpoints. */ | |
6ffbb7ab TJB |
1464 | total_hw_bp = 0; |
1465 | total_hw_wp = 1; | |
1466 | } | |
b7622095 | 1467 | |
6ffbb7ab TJB |
1468 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
1469 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
1470 | { | |
bb08bdbd | 1471 | if (cnt + ot > total_hw_wp) |
6ffbb7ab TJB |
1472 | return -1; |
1473 | } | |
1474 | else if (type == bp_hardware_breakpoint) | |
1475 | { | |
1476 | if (cnt > total_hw_bp) | |
1477 | return -1; | |
1478 | } | |
1479 | ||
926bf92d | 1480 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1481 | { |
1482 | int tid; | |
1483 | ptid_t ptid = inferior_ptid; | |
1484 | ||
0df8b418 MS |
1485 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
1486 | and whether the target has DABR. If either answer is no, the | |
1487 | ptrace call will return -1. Fail in that case. */ | |
dfd4cc63 | 1488 | tid = ptid_get_lwp (ptid); |
6ffbb7ab | 1489 | if (tid == 0) |
dfd4cc63 | 1490 | tid = ptid_get_pid (ptid); |
6ffbb7ab TJB |
1491 | |
1492 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1493 | return 0; | |
1494 | } | |
1495 | ||
1496 | return 1; | |
b7622095 LM |
1497 | } |
1498 | ||
e0d24f8d | 1499 | static int |
31568a15 TT |
1500 | ppc_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1501 | CORE_ADDR addr, int len) | |
e0d24f8d WZ |
1502 | { |
1503 | /* Handle sub-8-byte quantities. */ | |
1504 | if (len <= 0) | |
1505 | return 0; | |
1506 | ||
926bf92d UW |
1507 | /* The PowerPC HWDEBUG ptrace interface tells if there are alignment |
1508 | restrictions for watchpoints in the processors. In that case, we use that | |
1509 | information to determine the hardcoded watchable region for | |
1510 | watchpoints. */ | |
1511 | if (have_ptrace_hwdebug_interface ()) | |
6ffbb7ab | 1512 | { |
e23b9d6e | 1513 | int region_size; |
4feebbdd EBM |
1514 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
1515 | watchpoints and can watch any access within an arbitrary memory | |
1516 | region. This is useful to watch arrays and structs, for instance. It | |
1517 | takes two hardware watchpoints though. */ | |
e09342b5 | 1518 | if (len > 1 |
926bf92d | 1519 | && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
4feebbdd | 1520 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
e09342b5 | 1521 | return 2; |
e23b9d6e UW |
1522 | /* Check if the processor provides DAWR interface. */ |
1523 | if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) | |
1524 | /* DAWR interface allows to watch up to 512 byte wide ranges which | |
1525 | can't cross a 512 byte boundary. */ | |
1526 | region_size = 512; | |
1527 | else | |
1528 | region_size = hwdebug_info.data_bp_alignment; | |
4feebbdd EBM |
1529 | /* Server processors provide one hardware watchpoint and addr+len should |
1530 | fall in the watchable region provided by the ptrace interface. */ | |
e23b9d6e UW |
1531 | if (region_size |
1532 | && (addr + len > (addr & ~(region_size - 1)) + region_size)) | |
0cf6dd15 | 1533 | return 0; |
6ffbb7ab | 1534 | } |
b7622095 | 1535 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
926bf92d UW |
1536 | processors (i.e., server processors). Without the new PowerPC HWDEBUG |
1537 | ptrace interface, DAC-based processors (i.e., embedded processors) will | |
1538 | use addresses aligned to 4-bytes due to the way the read/write flags are | |
6ffbb7ab TJB |
1539 | passed in the old ptrace interface. */ |
1540 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1541 | && (addr + len) > (addr & ~3) + 4) | |
1542 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1543 | return 0; |
1544 | ||
1545 | return 1; | |
1546 | } | |
1547 | ||
6ffbb7ab | 1548 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
e4166a49 | 1549 | static int |
926bf92d | 1550 | hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
6ffbb7ab | 1551 | { |
ad422571 TJB |
1552 | return (a->trigger_type == b->trigger_type |
1553 | && a->addr_mode == b->addr_mode | |
1554 | && a->condition_mode == b->condition_mode | |
1555 | && a->addr == b->addr | |
1556 | && a->addr2 == b->addr2 | |
6ffbb7ab TJB |
1557 | && a->condition_value == b->condition_value); |
1558 | } | |
1559 | ||
1560 | /* This function can be used to retrieve a thread_points by the TID of the | |
1561 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, | |
1562 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the | |
1563 | provided TID will be created and returned. */ | |
1564 | static struct thread_points * | |
926bf92d | 1565 | hwdebug_find_thread_points_by_tid (int tid, int alloc_new) |
6ffbb7ab TJB |
1566 | { |
1567 | int i; | |
1568 | struct thread_points *t; | |
1569 | ||
1570 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) | |
1571 | if (t->tid == tid) | |
1572 | return t; | |
1573 | ||
1574 | t = NULL; | |
1575 | ||
1576 | /* Do we need to allocate a new point_item | |
1577 | if the wanted one does not exist? */ | |
1578 | if (alloc_new) | |
1579 | { | |
1580 | t = xmalloc (sizeof (struct thread_points)); | |
0df8b418 MS |
1581 | t->hw_breaks |
1582 | = xzalloc (max_slots_number * sizeof (struct hw_break_tuple)); | |
6ffbb7ab TJB |
1583 | t->tid = tid; |
1584 | VEC_safe_push (thread_points_p, ppc_threads, t); | |
1585 | } | |
1586 | ||
1587 | return t; | |
1588 | } | |
1589 | ||
1590 | /* This function is a generic wrapper that is responsible for inserting a | |
1591 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1592 | kernel) and registering it internally in GDB. */ | |
1593 | static void | |
926bf92d | 1594 | hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1595 | { |
1596 | int i; | |
1597 | long slot; | |
1598 | struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint)); | |
1599 | struct hw_break_tuple *hw_breaks; | |
1600 | struct cleanup *c = make_cleanup (xfree, p); | |
1601 | struct thread_points *t; | |
1602 | struct hw_break_tuple *tuple; | |
1603 | ||
1604 | memcpy (p, b, sizeof (struct ppc_hw_breakpoint)); | |
1605 | ||
1606 | errno = 0; | |
1607 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p); | |
1608 | if (slot < 0) | |
1609 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); | |
1610 | ||
1611 | /* Everything went fine, so we have to register this *point. */ | |
926bf92d | 1612 | t = hwdebug_find_thread_points_by_tid (tid, 1); |
6ffbb7ab TJB |
1613 | gdb_assert (t != NULL); |
1614 | hw_breaks = t->hw_breaks; | |
1615 | ||
1616 | /* Find a free element in the hw_breaks vector. */ | |
1617 | for (i = 0; i < max_slots_number; i++) | |
1618 | if (hw_breaks[i].hw_break == NULL) | |
1619 | { | |
1620 | hw_breaks[i].slot = slot; | |
1621 | hw_breaks[i].hw_break = p; | |
1622 | break; | |
1623 | } | |
1624 | ||
1625 | gdb_assert (i != max_slots_number); | |
1626 | ||
1627 | discard_cleanups (c); | |
1628 | } | |
1629 | ||
1630 | /* This function is a generic wrapper that is responsible for removing a | |
1631 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1632 | kernel), and unregistering it internally at GDB. */ | |
1633 | static void | |
926bf92d | 1634 | hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1635 | { |
1636 | int i; | |
1637 | struct hw_break_tuple *hw_breaks; | |
1638 | struct thread_points *t; | |
1639 | ||
926bf92d | 1640 | t = hwdebug_find_thread_points_by_tid (tid, 0); |
6ffbb7ab TJB |
1641 | gdb_assert (t != NULL); |
1642 | hw_breaks = t->hw_breaks; | |
1643 | ||
1644 | for (i = 0; i < max_slots_number; i++) | |
926bf92d | 1645 | if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b)) |
6ffbb7ab TJB |
1646 | break; |
1647 | ||
1648 | gdb_assert (i != max_slots_number); | |
1649 | ||
1650 | /* We have to ignore ENOENT errors because the kernel implements hardware | |
1651 | breakpoints/watchpoints as "one-shot", that is, they are automatically | |
1652 | deleted when hit. */ | |
1653 | errno = 0; | |
1654 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) | |
1655 | if (errno != ENOENT) | |
0df8b418 MS |
1656 | perror_with_name (_("Unexpected error deleting " |
1657 | "breakpoint or watchpoint")); | |
6ffbb7ab TJB |
1658 | |
1659 | xfree (hw_breaks[i].hw_break); | |
1660 | hw_breaks[i].hw_break = NULL; | |
1661 | } | |
9f0bdab8 | 1662 | |
f1310107 TJB |
1663 | /* Return the number of registers needed for a ranged breakpoint. */ |
1664 | ||
1665 | static int | |
1666 | ppc_linux_ranged_break_num_registers (struct target_ops *target) | |
1667 | { | |
926bf92d UW |
1668 | return ((have_ptrace_hwdebug_interface () |
1669 | && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? | |
f1310107 TJB |
1670 | 2 : -1); |
1671 | } | |
1672 | ||
1673 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for | |
1674 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ | |
1675 | ||
2c387241 | 1676 | static int |
23a26771 TT |
1677 | ppc_linux_insert_hw_breakpoint (struct target_ops *self, |
1678 | struct gdbarch *gdbarch, | |
6ffbb7ab | 1679 | struct bp_target_info *bp_tgt) |
e0d24f8d | 1680 | { |
9f0bdab8 | 1681 | struct lwp_info *lp; |
6ffbb7ab TJB |
1682 | struct ppc_hw_breakpoint p; |
1683 | ||
926bf92d | 1684 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1685 | return -1; |
1686 | ||
ad422571 TJB |
1687 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1688 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1689 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1690 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1691 | p.condition_value = 0; |
1692 | ||
f1310107 TJB |
1693 | if (bp_tgt->length) |
1694 | { | |
1695 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1696 | ||
1697 | /* The breakpoint will trigger if the address of the instruction is | |
1698 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
1699 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1700 | } | |
1701 | else | |
1702 | { | |
1703 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1704 | p.addr2 = 0; | |
1705 | } | |
1706 | ||
4c38200f | 1707 | ALL_LWPS (lp) |
dfd4cc63 | 1708 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
1709 | |
1710 | return 0; | |
1711 | } | |
1712 | ||
1713 | static int | |
a64dc96c TT |
1714 | ppc_linux_remove_hw_breakpoint (struct target_ops *self, |
1715 | struct gdbarch *gdbarch, | |
6ffbb7ab TJB |
1716 | struct bp_target_info *bp_tgt) |
1717 | { | |
6ffbb7ab TJB |
1718 | struct lwp_info *lp; |
1719 | struct ppc_hw_breakpoint p; | |
b7622095 | 1720 | |
926bf92d | 1721 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1722 | return -1; |
1723 | ||
ad422571 TJB |
1724 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1725 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1726 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1727 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1728 | p.condition_value = 0; |
1729 | ||
f1310107 TJB |
1730 | if (bp_tgt->length) |
1731 | { | |
1732 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1733 | ||
1734 | /* The breakpoint will trigger if the address of the instruction is within | |
1735 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
1736 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1737 | } | |
1738 | else | |
1739 | { | |
1740 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1741 | p.addr2 = 0; | |
1742 | } | |
1743 | ||
4c38200f | 1744 | ALL_LWPS (lp) |
dfd4cc63 | 1745 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
1746 | |
1747 | return 0; | |
1748 | } | |
1749 | ||
1750 | static int | |
1751 | get_trigger_type (int rw) | |
1752 | { | |
1753 | int t; | |
1754 | ||
1755 | if (rw == hw_read) | |
1756 | t = PPC_BREAKPOINT_TRIGGER_READ; | |
1757 | else if (rw == hw_write) | |
1758 | t = PPC_BREAKPOINT_TRIGGER_WRITE; | |
b7622095 | 1759 | else |
6ffbb7ab TJB |
1760 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
1761 | ||
1762 | return t; | |
1763 | } | |
1764 | ||
9c06b0b4 TJB |
1765 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
1766 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1767 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1768 | an error on failure. */ | |
1769 | ||
1770 | static int | |
1771 | ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, | |
1772 | CORE_ADDR mask, int rw) | |
1773 | { | |
9c06b0b4 TJB |
1774 | struct lwp_info *lp; |
1775 | struct ppc_hw_breakpoint p; | |
1776 | ||
926bf92d | 1777 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1778 | |
1779 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1780 | p.trigger_type = get_trigger_type (rw); | |
1781 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1782 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1783 | p.addr = addr; | |
1784 | p.addr2 = mask; | |
1785 | p.condition_value = 0; | |
1786 | ||
4c38200f | 1787 | ALL_LWPS (lp) |
dfd4cc63 | 1788 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
9c06b0b4 TJB |
1789 | |
1790 | return 0; | |
1791 | } | |
1792 | ||
1793 | /* Remove a masked watchpoint at ADDR with the mask MASK. | |
1794 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1795 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1796 | an error on failure. */ | |
1797 | ||
1798 | static int | |
1799 | ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, | |
1800 | CORE_ADDR mask, int rw) | |
1801 | { | |
9c06b0b4 TJB |
1802 | struct lwp_info *lp; |
1803 | struct ppc_hw_breakpoint p; | |
1804 | ||
926bf92d | 1805 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1806 | |
1807 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1808 | p.trigger_type = get_trigger_type (rw); | |
1809 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1810 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1811 | p.addr = addr; | |
1812 | p.addr2 = mask; | |
1813 | p.condition_value = 0; | |
1814 | ||
4c38200f | 1815 | ALL_LWPS (lp) |
dfd4cc63 | 1816 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
9c06b0b4 TJB |
1817 | |
1818 | return 0; | |
1819 | } | |
1820 | ||
0cf6dd15 TJB |
1821 | /* Check whether we have at least one free DVC register. */ |
1822 | static int | |
1823 | can_use_watchpoint_cond_accel (void) | |
1824 | { | |
1825 | struct thread_points *p; | |
dfd4cc63 | 1826 | int tid = ptid_get_lwp (inferior_ptid); |
926bf92d | 1827 | int cnt = hwdebug_info.num_condition_regs, i; |
0cf6dd15 TJB |
1828 | CORE_ADDR tmp_value; |
1829 | ||
926bf92d | 1830 | if (!have_ptrace_hwdebug_interface () || cnt == 0) |
0cf6dd15 TJB |
1831 | return 0; |
1832 | ||
926bf92d | 1833 | p = hwdebug_find_thread_points_by_tid (tid, 0); |
0cf6dd15 TJB |
1834 | |
1835 | if (p) | |
1836 | { | |
1837 | for (i = 0; i < max_slots_number; i++) | |
1838 | if (p->hw_breaks[i].hw_break != NULL | |
1839 | && (p->hw_breaks[i].hw_break->condition_mode | |
1840 | != PPC_BREAKPOINT_CONDITION_NONE)) | |
1841 | cnt--; | |
1842 | ||
1843 | /* There are no available slots now. */ | |
1844 | if (cnt <= 0) | |
1845 | return 0; | |
1846 | } | |
1847 | ||
1848 | return 1; | |
1849 | } | |
1850 | ||
1851 | /* Calculate the enable bits and the contents of the Data Value Compare | |
1852 | debug register present in BookE processors. | |
1853 | ||
1854 | ADDR is the address to be watched, LEN is the length of watched data | |
1855 | and DATA_VALUE is the value which will trigger the watchpoint. | |
1856 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
1857 | CONDITION_VALUE will hold the value which should be put in the | |
1858 | DVC register. */ | |
1859 | static void | |
1860 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, | |
1861 | uint32_t *condition_mode, uint64_t *condition_value) | |
1862 | { | |
1863 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, | |
1864 | rightmost_enabled_byte; | |
1865 | CORE_ADDR addr_end_data, addr_end_dvc; | |
1866 | ||
1867 | /* The DVC register compares bytes within fixed-length windows which | |
1868 | are word-aligned, with length equal to that of the DVC register. | |
1869 | We need to calculate where our watch region is relative to that | |
1870 | window and enable comparison of the bytes which fall within it. */ | |
1871 | ||
926bf92d | 1872 | align_offset = addr % hwdebug_info.sizeof_condition; |
0cf6dd15 TJB |
1873 | addr_end_data = addr + len; |
1874 | addr_end_dvc = (addr - align_offset | |
926bf92d | 1875 | + hwdebug_info.sizeof_condition); |
0cf6dd15 TJB |
1876 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? |
1877 | addr_end_data - addr_end_dvc : 0; | |
1878 | num_byte_enable = len - num_bytes_off_dvc; | |
1879 | /* Here, bytes are numbered from right to left. */ | |
1880 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
1881 | addr_end_dvc - addr_end_data : 0; | |
1882 | ||
1883 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
1884 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
1885 | *condition_mode |
1886 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
1887 | |
1888 | /* Now we need to match the position within the DVC of the comparison | |
1889 | value with where the watch region is relative to the window | |
1890 | (i.e., the ALIGN_OFFSET). */ | |
1891 | ||
1892 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
1893 | << rightmost_enabled_byte * 8); | |
1894 | } | |
1895 | ||
1896 | /* Return the number of memory locations that need to be accessed to | |
1897 | evaluate the expression which generated the given value chain. | |
1898 | Returns -1 if there's any register access involved, or if there are | |
1899 | other kinds of values which are not acceptable in a condition | |
1900 | expression (e.g., lval_computed or lval_internalvar). */ | |
1901 | static int | |
1902 | num_memory_accesses (struct value *v) | |
1903 | { | |
1904 | int found_memory_cnt = 0; | |
1905 | struct value *head = v; | |
1906 | ||
1907 | /* The idea here is that evaluating an expression generates a series | |
1908 | of values, one holding the value of every subexpression. (The | |
1909 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
1910 | a*b+c.) GDB's values hold almost enough information to establish | |
1911 | the criteria given above --- they identify memory lvalues, | |
1912 | register lvalues, computed values, etcetera. So we can evaluate | |
1913 | the expression, and then scan the chain of values that leaves | |
1914 | behind to determine the memory locations involved in the evaluation | |
1915 | of an expression. | |
1916 | ||
1917 | However, I don't think that the values returned by inferior | |
1918 | function calls are special in any way. So this function may not | |
1919 | notice that an expression contains an inferior function call. | |
1920 | FIXME. */ | |
1921 | ||
1922 | for (; v; v = value_next (v)) | |
1923 | { | |
1924 | /* Constants and values from the history are fine. */ | |
1925 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) | |
1926 | continue; | |
1927 | else if (VALUE_LVAL (v) == lval_memory) | |
1928 | { | |
1929 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
1930 | we either just used its address (e.g., `a' in `a.b') or | |
1931 | we never needed it at all (e.g., `a' in `a,b'). */ | |
1932 | if (!value_lazy (v)) | |
1933 | found_memory_cnt++; | |
1934 | } | |
0df8b418 | 1935 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
1936 | else |
1937 | return -1; | |
1938 | } | |
1939 | ||
1940 | return found_memory_cnt; | |
1941 | } | |
1942 | ||
1943 | /* Verifies whether the expression COND can be implemented using the | |
1944 | DVC (Data Value Compare) register in BookE processors. The expression | |
1945 | must test the watch value for equality with a constant expression. | |
1946 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
1947 | which the watch value should be compared and LEN will contain the size |
1948 | of the constant. */ | |
0cf6dd15 TJB |
1949 | static int |
1950 | check_condition (CORE_ADDR watch_addr, struct expression *cond, | |
e7db58ea | 1951 | CORE_ADDR *data_value, int *len) |
0cf6dd15 TJB |
1952 | { |
1953 | int pc = 1, num_accesses_left, num_accesses_right; | |
1954 | struct value *left_val, *right_val, *left_chain, *right_chain; | |
1955 | ||
1956 | if (cond->elts[0].opcode != BINOP_EQUAL) | |
1957 | return 0; | |
1958 | ||
3a1115a0 | 1959 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0); |
0cf6dd15 TJB |
1960 | num_accesses_left = num_memory_accesses (left_chain); |
1961 | ||
1962 | if (left_val == NULL || num_accesses_left < 0) | |
1963 | { | |
1964 | free_value_chain (left_chain); | |
1965 | ||
1966 | return 0; | |
1967 | } | |
1968 | ||
3a1115a0 | 1969 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0); |
0cf6dd15 TJB |
1970 | num_accesses_right = num_memory_accesses (right_chain); |
1971 | ||
1972 | if (right_val == NULL || num_accesses_right < 0) | |
1973 | { | |
1974 | free_value_chain (left_chain); | |
1975 | free_value_chain (right_chain); | |
1976 | ||
1977 | return 0; | |
1978 | } | |
1979 | ||
1980 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
1981 | && VALUE_LVAL (left_val) == lval_memory | |
1982 | && value_address (left_val) == watch_addr) | |
e7db58ea TJB |
1983 | { |
1984 | *data_value = value_as_long (right_val); | |
1985 | ||
1986 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
1987 | the same type as the memory region referenced by LEFT_VAL. */ | |
1988 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); | |
1989 | } | |
0cf6dd15 TJB |
1990 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
1991 | && VALUE_LVAL (right_val) == lval_memory | |
1992 | && value_address (right_val) == watch_addr) | |
e7db58ea TJB |
1993 | { |
1994 | *data_value = value_as_long (left_val); | |
1995 | ||
1996 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
1997 | the same type as the memory region referenced by RIGHT_VAL. */ | |
1998 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); | |
1999 | } | |
0cf6dd15 TJB |
2000 | else |
2001 | { | |
2002 | free_value_chain (left_chain); | |
2003 | free_value_chain (right_chain); | |
2004 | ||
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | free_value_chain (left_chain); | |
2009 | free_value_chain (right_chain); | |
2010 | ||
2011 | return 1; | |
2012 | } | |
2013 | ||
2014 | /* Return non-zero if the target is capable of using hardware to evaluate | |
2015 | the condition expression, thus only triggering the watchpoint when it is | |
2016 | true. */ | |
2017 | static int | |
c3a5ff89 TT |
2018 | ppc_linux_can_accel_watchpoint_condition (struct target_ops *self, |
2019 | CORE_ADDR addr, int len, int rw, | |
0cf6dd15 TJB |
2020 | struct expression *cond) |
2021 | { | |
2022 | CORE_ADDR data_value; | |
2023 | ||
926bf92d UW |
2024 | return (have_ptrace_hwdebug_interface () |
2025 | && hwdebug_info.num_condition_regs > 0 | |
e7db58ea | 2026 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
2027 | } |
2028 | ||
e09342b5 TJB |
2029 | /* Set up P with the parameters necessary to request a watchpoint covering |
2030 | LEN bytes starting at ADDR and if possible with condition expression COND | |
2031 | evaluated by hardware. INSERT tells if we are creating a request for | |
2032 | inserting or removing the watchpoint. */ | |
2033 | ||
2034 | static void | |
2035 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, | |
2036 | int len, int rw, struct expression *cond, | |
2037 | int insert) | |
2038 | { | |
f16c4e8b | 2039 | if (len == 1 |
926bf92d | 2040 | || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) |
e09342b5 TJB |
2041 | { |
2042 | int use_condition; | |
2043 | CORE_ADDR data_value; | |
2044 | ||
2045 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
926bf92d | 2046 | : hwdebug_info.num_condition_regs > 0); |
e7db58ea TJB |
2047 | if (cond && use_condition && check_condition (addr, cond, |
2048 | &data_value, &len)) | |
e09342b5 TJB |
2049 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
2050 | &p->condition_value); | |
2051 | else | |
2052 | { | |
2053 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2054 | p->condition_value = 0; | |
2055 | } | |
2056 | ||
2057 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2058 | p->addr2 = 0; | |
2059 | } | |
2060 | else | |
2061 | { | |
2062 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2063 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2064 | p->condition_value = 0; | |
2065 | ||
2066 | /* The watchpoint will trigger if the address of the memory access is | |
2067 | within the defined range, as follows: p->addr <= address < p->addr2. | |
2068 | ||
2069 | Note that the above sentence just documents how ptrace interprets | |
2070 | its arguments; the watchpoint is set to watch the range defined by | |
2071 | the user _inclusively_, as specified by the user interface. */ | |
2072 | p->addr2 = (uint64_t) addr + len; | |
2073 | } | |
2074 | ||
2075 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
2076 | p->trigger_type = get_trigger_type (rw); | |
2077 | p->addr = (uint64_t) addr; | |
2078 | } | |
2079 | ||
6ffbb7ab | 2080 | static int |
7bb99c53 TT |
2081 | ppc_linux_insert_watchpoint (struct target_ops *self, |
2082 | CORE_ADDR addr, int len, int rw, | |
0cf6dd15 | 2083 | struct expression *cond) |
6ffbb7ab TJB |
2084 | { |
2085 | struct lwp_info *lp; | |
6ffbb7ab TJB |
2086 | int ret = -1; |
2087 | ||
926bf92d | 2088 | if (have_ptrace_hwdebug_interface ()) |
e0d24f8d | 2089 | { |
6ffbb7ab TJB |
2090 | struct ppc_hw_breakpoint p; |
2091 | ||
e09342b5 | 2092 | create_watchpoint_request (&p, addr, len, rw, cond, 1); |
6ffbb7ab | 2093 | |
4c38200f | 2094 | ALL_LWPS (lp) |
dfd4cc63 | 2095 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
2096 | |
2097 | ret = 0; | |
e0d24f8d | 2098 | } |
6ffbb7ab TJB |
2099 | else |
2100 | { | |
2101 | long dabr_value; | |
2102 | long read_mode, write_mode; | |
e0d24f8d | 2103 | |
6ffbb7ab TJB |
2104 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2105 | { | |
2106 | /* PowerPC 440 requires only the read/write flags to be passed | |
2107 | to the kernel. */ | |
ad422571 | 2108 | read_mode = 1; |
6ffbb7ab TJB |
2109 | write_mode = 2; |
2110 | } | |
2111 | else | |
2112 | { | |
2113 | /* PowerPC 970 and other DABR-based processors are required to pass | |
2114 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 2115 | read_mode = 5; |
6ffbb7ab TJB |
2116 | write_mode = 6; |
2117 | } | |
1c86e440 | 2118 | |
6ffbb7ab TJB |
2119 | dabr_value = addr & ~(read_mode | write_mode); |
2120 | switch (rw) | |
2121 | { | |
2122 | case hw_read: | |
2123 | /* Set read and translate bits. */ | |
2124 | dabr_value |= read_mode; | |
2125 | break; | |
2126 | case hw_write: | |
2127 | /* Set write and translate bits. */ | |
2128 | dabr_value |= write_mode; | |
2129 | break; | |
2130 | case hw_access: | |
2131 | /* Set read, write and translate bits. */ | |
2132 | dabr_value |= read_mode | write_mode; | |
2133 | break; | |
2134 | } | |
1c86e440 | 2135 | |
6ffbb7ab TJB |
2136 | saved_dabr_value = dabr_value; |
2137 | ||
4c38200f | 2138 | ALL_LWPS (lp) |
dfd4cc63 | 2139 | if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, |
0cf6dd15 | 2140 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2141 | return -1; |
2142 | ||
2143 | ret = 0; | |
2144 | } | |
2145 | ||
2146 | return ret; | |
e0d24f8d WZ |
2147 | } |
2148 | ||
2c387241 | 2149 | static int |
11b5219a TT |
2150 | ppc_linux_remove_watchpoint (struct target_ops *self, |
2151 | CORE_ADDR addr, int len, int rw, | |
0cf6dd15 | 2152 | struct expression *cond) |
e0d24f8d | 2153 | { |
9f0bdab8 | 2154 | struct lwp_info *lp; |
6ffbb7ab | 2155 | int ret = -1; |
9f0bdab8 | 2156 | |
926bf92d | 2157 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2158 | { |
2159 | struct ppc_hw_breakpoint p; | |
2160 | ||
e09342b5 | 2161 | create_watchpoint_request (&p, addr, len, rw, cond, 0); |
6ffbb7ab | 2162 | |
4c38200f | 2163 | ALL_LWPS (lp) |
dfd4cc63 | 2164 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
2165 | |
2166 | ret = 0; | |
2167 | } | |
2168 | else | |
2169 | { | |
2170 | saved_dabr_value = 0; | |
4c38200f | 2171 | ALL_LWPS (lp) |
dfd4cc63 | 2172 | if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, |
0cf6dd15 | 2173 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2174 | return -1; |
2175 | ||
2176 | ret = 0; | |
2177 | } | |
2178 | ||
2179 | return ret; | |
e0d24f8d WZ |
2180 | } |
2181 | ||
9f0bdab8 | 2182 | static void |
7b50312a | 2183 | ppc_linux_new_thread (struct lwp_info *lp) |
e0d24f8d | 2184 | { |
dfd4cc63 | 2185 | int tid = ptid_get_lwp (lp->ptid); |
6ffbb7ab | 2186 | |
926bf92d | 2187 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2188 | { |
2189 | int i; | |
2190 | struct thread_points *p; | |
2191 | struct hw_break_tuple *hw_breaks; | |
2192 | ||
2193 | if (VEC_empty (thread_points_p, ppc_threads)) | |
2194 | return; | |
2195 | ||
0df8b418 | 2196 | /* Get a list of breakpoints from any thread. */ |
6ffbb7ab TJB |
2197 | p = VEC_last (thread_points_p, ppc_threads); |
2198 | hw_breaks = p->hw_breaks; | |
2199 | ||
0df8b418 | 2200 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
6ffbb7ab TJB |
2201 | for (i = 0; i < max_slots_number; i++) |
2202 | if (hw_breaks[i].hw_break) | |
aacbb8a5 LM |
2203 | { |
2204 | /* Older kernels did not make new threads inherit their parent | |
2205 | thread's debug state, so we always clear the slot and replicate | |
2206 | the debug state ourselves, ensuring compatibility with all | |
2207 | kernels. */ | |
2208 | ||
2209 | /* The ppc debug resource accounting is done through "slots". | |
2210 | Ask the kernel the deallocate this specific *point's slot. */ | |
2211 | ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot); | |
2212 | ||
926bf92d | 2213 | hwdebug_insert_point (hw_breaks[i].hw_break, tid); |
aacbb8a5 | 2214 | } |
6ffbb7ab TJB |
2215 | } |
2216 | else | |
2217 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); | |
2218 | } | |
2219 | ||
2220 | static void | |
2221 | ppc_linux_thread_exit (struct thread_info *tp, int silent) | |
2222 | { | |
2223 | int i; | |
dfd4cc63 | 2224 | int tid = ptid_get_lwp (tp->ptid); |
6ffbb7ab TJB |
2225 | struct hw_break_tuple *hw_breaks; |
2226 | struct thread_points *t = NULL, *p; | |
2227 | ||
926bf92d | 2228 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2229 | return; |
2230 | ||
2231 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) | |
2232 | if (p->tid == tid) | |
2233 | { | |
2234 | t = p; | |
2235 | break; | |
2236 | } | |
2237 | ||
2238 | if (t == NULL) | |
2239 | return; | |
2240 | ||
2241 | VEC_unordered_remove (thread_points_p, ppc_threads, i); | |
2242 | ||
2243 | hw_breaks = t->hw_breaks; | |
2244 | ||
2245 | for (i = 0; i < max_slots_number; i++) | |
2246 | if (hw_breaks[i].hw_break) | |
2247 | xfree (hw_breaks[i].hw_break); | |
2248 | ||
2249 | xfree (t->hw_breaks); | |
2250 | xfree (t); | |
e0d24f8d WZ |
2251 | } |
2252 | ||
2253 | static int | |
9f0bdab8 | 2254 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) |
e0d24f8d | 2255 | { |
f865ee35 | 2256 | siginfo_t siginfo; |
e0d24f8d | 2257 | |
f865ee35 JK |
2258 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
2259 | return 0; | |
e0d24f8d | 2260 | |
f865ee35 JK |
2261 | if (siginfo.si_signo != SIGTRAP |
2262 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e0d24f8d WZ |
2263 | return 0; |
2264 | ||
926bf92d | 2265 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2266 | { |
2267 | int i; | |
2268 | struct thread_points *t; | |
2269 | struct hw_break_tuple *hw_breaks; | |
2270 | /* The index (or slot) of the *point is passed in the si_errno field. */ | |
f865ee35 | 2271 | int slot = siginfo.si_errno; |
6ffbb7ab | 2272 | |
dfd4cc63 | 2273 | t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0); |
6ffbb7ab TJB |
2274 | |
2275 | /* Find out if this *point is a hardware breakpoint. | |
2276 | If so, we should return 0. */ | |
2277 | if (t) | |
2278 | { | |
2279 | hw_breaks = t->hw_breaks; | |
2280 | for (i = 0; i < max_slots_number; i++) | |
2281 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot | |
2282 | && hw_breaks[i].hw_break->trigger_type | |
2283 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) | |
2284 | return 0; | |
2285 | } | |
2286 | } | |
2287 | ||
f865ee35 | 2288 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e0d24f8d WZ |
2289 | return 1; |
2290 | } | |
2291 | ||
9f0bdab8 | 2292 | static int |
6a109b6b | 2293 | ppc_linux_stopped_by_watchpoint (struct target_ops *ops) |
9f0bdab8 DJ |
2294 | { |
2295 | CORE_ADDR addr; | |
6a109b6b | 2296 | return ppc_linux_stopped_data_address (ops, &addr); |
9f0bdab8 DJ |
2297 | } |
2298 | ||
5009afc5 AS |
2299 | static int |
2300 | ppc_linux_watchpoint_addr_within_range (struct target_ops *target, | |
2301 | CORE_ADDR addr, | |
2302 | CORE_ADDR start, int length) | |
2303 | { | |
b7622095 LM |
2304 | int mask; |
2305 | ||
926bf92d | 2306 | if (have_ptrace_hwdebug_interface () |
6ffbb7ab TJB |
2307 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2308 | return start <= addr && start + length >= addr; | |
2309 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
b7622095 LM |
2310 | mask = 3; |
2311 | else | |
2312 | mask = 7; | |
2313 | ||
2314 | addr &= ~mask; | |
2315 | ||
0df8b418 | 2316 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 2317 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
2318 | } |
2319 | ||
9c06b0b4 TJB |
2320 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
2321 | ||
2322 | static int | |
2323 | ppc_linux_masked_watch_num_registers (struct target_ops *target, | |
2324 | CORE_ADDR addr, CORE_ADDR mask) | |
2325 | { | |
926bf92d UW |
2326 | if (!have_ptrace_hwdebug_interface () |
2327 | || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
9c06b0b4 TJB |
2328 | return -1; |
2329 | else if ((mask & 0xC0000000) != 0xC0000000) | |
2330 | { | |
2331 | warning (_("The given mask covers kernel address space " | |
2332 | "and cannot be used.\n")); | |
2333 | ||
2334 | return -2; | |
2335 | } | |
2336 | else | |
2337 | return 2; | |
2338 | } | |
2339 | ||
10d6c8cd | 2340 | static void |
28439f5e PA |
2341 | ppc_linux_store_inferior_registers (struct target_ops *ops, |
2342 | struct regcache *regcache, int regno) | |
45229ea4 | 2343 | { |
0df8b418 | 2344 | /* Overload thread id onto process id. */ |
dfd4cc63 | 2345 | int tid = ptid_get_lwp (inferior_ptid); |
05f13b9c | 2346 | |
0df8b418 | 2347 | /* No thread id, just use process id. */ |
05f13b9c | 2348 | if (tid == 0) |
dfd4cc63 | 2349 | tid = ptid_get_pid (inferior_ptid); |
05f13b9c | 2350 | |
45229ea4 | 2351 | if (regno >= 0) |
56be3814 | 2352 | store_register (regcache, tid, regno); |
45229ea4 | 2353 | else |
56be3814 | 2354 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
2355 | } |
2356 | ||
f2db237a AM |
2357 | /* Functions for transferring registers between a gregset_t or fpregset_t |
2358 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
0df8b418 | 2359 | by the ptrace interface, not the current program's ABI. Eg. if a |
f2db237a AM |
2360 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
2361 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
2362 | ||
50c9bd31 | 2363 | void |
7f7fe91e | 2364 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 2365 | { |
f2db237a | 2366 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2367 | |
f2db237a | 2368 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
2369 | } |
2370 | ||
fdb28ac4 | 2371 | void |
7f7fe91e UW |
2372 | fill_gregset (const struct regcache *regcache, |
2373 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 2374 | { |
f2db237a | 2375 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2376 | |
f2db237a AM |
2377 | if (regno == -1) |
2378 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
2379 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
2380 | } |
2381 | ||
50c9bd31 | 2382 | void |
7f7fe91e | 2383 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 2384 | { |
f2db237a AM |
2385 | const struct regset *regset = ppc_linux_fpregset (); |
2386 | ||
2387 | ppc_supply_fpregset (regset, regcache, -1, | |
2388 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 2389 | } |
fdb28ac4 | 2390 | |
fdb28ac4 | 2391 | void |
7f7fe91e UW |
2392 | fill_fpregset (const struct regcache *regcache, |
2393 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 2394 | { |
f2db237a AM |
2395 | const struct regset *regset = ppc_linux_fpregset (); |
2396 | ||
2397 | ppc_collect_fpregset (regset, regcache, regno, | |
2398 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 2399 | } |
10d6c8cd | 2400 | |
409c383c UW |
2401 | static int |
2402 | ppc_linux_target_wordsize (void) | |
2403 | { | |
2404 | int wordsize = 4; | |
2405 | ||
2406 | /* Check for 64-bit inferior process. This is the case when the host is | |
2407 | 64-bit, and in addition the top bit of the MSR register is set. */ | |
2408 | #ifdef __powerpc64__ | |
2409 | long msr; | |
2410 | ||
dfd4cc63 | 2411 | int tid = ptid_get_lwp (inferior_ptid); |
409c383c | 2412 | if (tid == 0) |
dfd4cc63 | 2413 | tid = ptid_get_pid (inferior_ptid); |
409c383c UW |
2414 | |
2415 | errno = 0; | |
2416 | msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); | |
2417 | if (errno == 0 && msr < 0) | |
2418 | wordsize = 8; | |
2419 | #endif | |
2420 | ||
2421 | return wordsize; | |
2422 | } | |
2423 | ||
2424 | static int | |
2425 | ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr, | |
2426 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
2427 | { | |
2428 | int sizeof_auxv_field = ppc_linux_target_wordsize (); | |
f5656ead | 2429 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
409c383c UW |
2430 | gdb_byte *ptr = *readptr; |
2431 | ||
2432 | if (endptr == ptr) | |
2433 | return 0; | |
2434 | ||
2435 | if (endptr - ptr < sizeof_auxv_field * 2) | |
2436 | return -1; | |
2437 | ||
e17a4113 | 2438 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c | 2439 | ptr += sizeof_auxv_field; |
e17a4113 | 2440 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c UW |
2441 | ptr += sizeof_auxv_field; |
2442 | ||
2443 | *readptr = ptr; | |
2444 | return 1; | |
2445 | } | |
2446 | ||
310a98e1 DJ |
2447 | static const struct target_desc * |
2448 | ppc_linux_read_description (struct target_ops *ops) | |
2449 | { | |
7284e1be | 2450 | int altivec = 0; |
604c2f83 | 2451 | int vsx = 0; |
69abc51c | 2452 | int isa205 = 0; |
f4d9bade | 2453 | int cell = 0; |
7284e1be | 2454 | |
dfd4cc63 | 2455 | int tid = ptid_get_lwp (inferior_ptid); |
7284e1be | 2456 | if (tid == 0) |
dfd4cc63 | 2457 | tid = ptid_get_pid (inferior_ptid); |
7284e1be | 2458 | |
310a98e1 DJ |
2459 | if (have_ptrace_getsetevrregs) |
2460 | { | |
2461 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
2462 | |
2463 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
2464 | return tdesc_powerpc_e500l; |
2465 | ||
2466 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
2467 | Anything else needs to be reported. */ | |
2468 | else if (errno != EIO) | |
2469 | perror_with_name (_("Unable to fetch SPE registers")); | |
2470 | } | |
2471 | ||
604c2f83 LM |
2472 | if (have_ptrace_getsetvsxregs) |
2473 | { | |
2474 | gdb_vsxregset_t vsxregset; | |
2475 | ||
2476 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
2477 | vsx = 1; | |
2478 | ||
2479 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
2480 | Anything else needs to be reported. */ | |
2481 | else if (errno != EIO) | |
2482 | perror_with_name (_("Unable to fetch VSX registers")); | |
2483 | } | |
2484 | ||
7284e1be UW |
2485 | if (have_ptrace_getvrregs) |
2486 | { | |
2487 | gdb_vrregset_t vrregset; | |
2488 | ||
2489 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
2490 | altivec = 1; | |
2491 | ||
2492 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
2493 | Anything else needs to be reported. */ | |
2494 | else if (errno != EIO) | |
2495 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
2496 | } |
2497 | ||
f04c6d38 | 2498 | /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases |
0df8b418 | 2499 | the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this |
f04c6d38 TJB |
2500 | ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only |
2501 | PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher | |
2502 | half of the register are for Decimal Floating Point, we check if that | |
2503 | feature is available to decide the size of the FPSCR. */ | |
2504 | if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP) | |
69abc51c TJB |
2505 | isa205 = 1; |
2506 | ||
f4d9bade UW |
2507 | if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL) |
2508 | cell = 1; | |
2509 | ||
409c383c UW |
2510 | if (ppc_linux_target_wordsize () == 8) |
2511 | { | |
f4d9bade UW |
2512 | if (cell) |
2513 | return tdesc_powerpc_cell64l; | |
2514 | else if (vsx) | |
409c383c UW |
2515 | return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; |
2516 | else if (altivec) | |
0df8b418 MS |
2517 | return isa205 |
2518 | ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; | |
409c383c UW |
2519 | |
2520 | return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; | |
2521 | } | |
7284e1be | 2522 | |
f4d9bade UW |
2523 | if (cell) |
2524 | return tdesc_powerpc_cell32l; | |
2525 | else if (vsx) | |
69abc51c | 2526 | return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; |
604c2f83 | 2527 | else if (altivec) |
69abc51c | 2528 | return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; |
604c2f83 | 2529 | |
69abc51c | 2530 | return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; |
310a98e1 DJ |
2531 | } |
2532 | ||
10d6c8cd DJ |
2533 | void _initialize_ppc_linux_nat (void); |
2534 | ||
2535 | void | |
2536 | _initialize_ppc_linux_nat (void) | |
2537 | { | |
2538 | struct target_ops *t; | |
2539 | ||
2540 | /* Fill in the generic GNU/Linux methods. */ | |
2541 | t = linux_target (); | |
2542 | ||
2543 | /* Add our register access methods. */ | |
2544 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; | |
2545 | t->to_store_registers = ppc_linux_store_inferior_registers; | |
2546 | ||
6ffbb7ab TJB |
2547 | /* Add our breakpoint/watchpoint methods. */ |
2548 | t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint; | |
2549 | t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint; | |
2550 | t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint; | |
e0d24f8d WZ |
2551 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; |
2552 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; | |
2553 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; | |
9c06b0b4 TJB |
2554 | t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint; |
2555 | t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint; | |
e0d24f8d WZ |
2556 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; |
2557 | t->to_stopped_data_address = ppc_linux_stopped_data_address; | |
5009afc5 | 2558 | t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; |
0df8b418 MS |
2559 | t->to_can_accel_watchpoint_condition |
2560 | = ppc_linux_can_accel_watchpoint_condition; | |
9c06b0b4 | 2561 | t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers; |
f1310107 | 2562 | t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers; |
e0d24f8d | 2563 | |
310a98e1 | 2564 | t->to_read_description = ppc_linux_read_description; |
409c383c | 2565 | t->to_auxv_parse = ppc_linux_auxv_parse; |
310a98e1 | 2566 | |
6ffbb7ab TJB |
2567 | observer_attach_thread_exit (ppc_linux_thread_exit); |
2568 | ||
10d6c8cd | 2569 | /* Register the target. */ |
f973ed9c | 2570 | linux_nat_add_target (t); |
9f0bdab8 | 2571 | linux_nat_set_new_thread (t, ppc_linux_new_thread); |
10d6c8cd | 2572 | } |