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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
e2882c85 | 3 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
c877c8e6 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
19 | |
20 | #include "defs.h" | |
76727919 | 21 | #include "observable.h" |
c877c8e6 KB |
22 | #include "frame.h" |
23 | #include "inferior.h" | |
6ffbb7ab | 24 | #include "gdbthread.h" |
c877c8e6 | 25 | #include "gdbcore.h" |
4e052eda | 26 | #include "regcache.h" |
10d6c8cd DJ |
27 | #include "target.h" |
28 | #include "linux-nat.h" | |
c877c8e6 | 29 | #include <sys/types.h> |
c877c8e6 KB |
30 | #include <signal.h> |
31 | #include <sys/user.h> | |
32 | #include <sys/ioctl.h> | |
2555fe1a | 33 | #include "gdb_wait.h" |
c877c8e6 KB |
34 | #include <fcntl.h> |
35 | #include <sys/procfs.h> | |
5826e159 | 36 | #include "nat/gdb_ptrace.h" |
bcc0c096 | 37 | #include "inf-ptrace.h" |
c877c8e6 | 38 | |
0df8b418 | 39 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 40 | #include "gregset.h" |
16333c4f | 41 | #include "ppc-tdep.h" |
7284e1be UW |
42 | #include "ppc-linux-tdep.h" |
43 | ||
b7622095 LM |
44 | /* Required when using the AUXV. */ |
45 | #include "elf/common.h" | |
46 | #include "auxv.h" | |
47 | ||
bd64614e PFC |
48 | #include "arch/ppc-linux-common.h" |
49 | #include "arch/ppc-linux-tdesc.h" | |
514c5338 | 50 | #include "nat/ppc-linux.h" |
01904826 | 51 | |
6ffbb7ab | 52 | /* Similarly for the hardware watchpoint support. These requests are used |
926bf92d | 53 | when the PowerPC HWDEBUG ptrace interface is not available. */ |
e0d24f8d WZ |
54 | #ifndef PTRACE_GET_DEBUGREG |
55 | #define PTRACE_GET_DEBUGREG 25 | |
56 | #endif | |
57 | #ifndef PTRACE_SET_DEBUGREG | |
58 | #define PTRACE_SET_DEBUGREG 26 | |
59 | #endif | |
60 | #ifndef PTRACE_GETSIGINFO | |
61 | #define PTRACE_GETSIGINFO 0x4202 | |
62 | #endif | |
01904826 | 63 | |
926bf92d UW |
64 | /* These requests are used when the PowerPC HWDEBUG ptrace interface is |
65 | available. It exposes the debug facilities of PowerPC processors, as well | |
66 | as additional features of BookE processors, such as ranged breakpoints and | |
67 | watchpoints and hardware-accelerated condition evaluation. */ | |
6ffbb7ab TJB |
68 | #ifndef PPC_PTRACE_GETHWDBGINFO |
69 | ||
926bf92d UW |
70 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG |
71 | ptrace interface is not present in ptrace.h, so we'll have to pretty much | |
72 | include it all here so that the code at least compiles on older systems. */ | |
6ffbb7ab TJB |
73 | #define PPC_PTRACE_GETHWDBGINFO 0x89 |
74 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
75 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
76 | ||
77 | struct ppc_debug_info | |
78 | { | |
0df8b418 | 79 | uint32_t version; /* Only version 1 exists to date. */ |
6ffbb7ab TJB |
80 | uint32_t num_instruction_bps; |
81 | uint32_t num_data_bps; | |
82 | uint32_t num_condition_regs; | |
83 | uint32_t data_bp_alignment; | |
0df8b418 | 84 | uint32_t sizeof_condition; /* size of the DVC register. */ |
6ffbb7ab TJB |
85 | uint64_t features; |
86 | }; | |
87 | ||
88 | /* Features will have bits indicating whether there is support for: */ | |
89 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
90 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
91 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
92 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
93 | ||
94 | struct ppc_hw_breakpoint | |
95 | { | |
96 | uint32_t version; /* currently, version must be 1 */ | |
97 | uint32_t trigger_type; /* only some combinations allowed */ | |
98 | uint32_t addr_mode; /* address match mode */ | |
99 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
100 | uint64_t addr; /* break/watchpoint address */ | |
101 | uint64_t addr2; /* range end or mask */ | |
102 | uint64_t condition_value; /* contents of the DVC register */ | |
103 | }; | |
104 | ||
105 | /* Trigger type. */ | |
106 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
107 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
108 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
109 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
110 | ||
111 | /* Address mode. */ | |
112 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
113 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
114 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
115 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
116 | ||
117 | /* Condition mode. */ | |
118 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
119 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
120 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
121 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
122 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
123 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
124 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
125 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
126 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) | |
127 | #endif /* PPC_PTRACE_GETHWDBGINFO */ | |
128 | ||
e23b9d6e UW |
129 | /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider |
130 | watchpoint (up to 512 bytes). */ | |
131 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR | |
132 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | |
133 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */ | |
6ffbb7ab | 134 | |
1dfe79e8 SDJ |
135 | /* Similarly for the general-purpose (gp0 -- gp31) |
136 | and floating-point registers (fp0 -- fp31). */ | |
137 | #ifndef PTRACE_GETREGS | |
138 | #define PTRACE_GETREGS 12 | |
139 | #endif | |
140 | #ifndef PTRACE_SETREGS | |
141 | #define PTRACE_SETREGS 13 | |
142 | #endif | |
143 | #ifndef PTRACE_GETFPREGS | |
144 | #define PTRACE_GETFPREGS 14 | |
145 | #endif | |
146 | #ifndef PTRACE_SETFPREGS | |
147 | #define PTRACE_SETFPREGS 15 | |
148 | #endif | |
149 | ||
9abe5450 EZ |
150 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
151 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
152 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
153 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
154 | flat array of chars, so that it is easier to manipulate for gdb. | |
155 | ||
156 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
157 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 158 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
159 | Appended to this there is space for the VRSAVE register: 4 bytes. |
160 | Even though this vrsave register is not included in the regset | |
161 | typedef, it is handled by the ptrace requests. | |
162 | ||
163 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
164 | therefore the offset at which the real value of the VSCR register | |
165 | is located will be always 12 bytes. | |
166 | ||
167 | The layout is like this (where x is the actual value of the vscr reg): */ | |
168 | ||
169 | /* *INDENT-OFF* */ | |
170 | /* | |
171 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
172 | <-------> <-------><-------><-> | |
173 | VR0 VR31 VSCR VRSAVE | |
174 | */ | |
175 | /* *INDENT-ON* */ | |
176 | ||
177 | #define SIZEOF_VRREGS 33*16+4 | |
178 | ||
179 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
180 | ||
604c2f83 LM |
181 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
182 | with the existing FPR and VMX registers. | |
183 | ||
184 | VSR doubleword 0 VSR doubleword 1 | |
185 | ---------------------------------------------------------------- | |
186 | VSR[0] | FPR[0] | | | |
187 | ---------------------------------------------------------------- | |
188 | VSR[1] | FPR[1] | | | |
189 | ---------------------------------------------------------------- | |
190 | | ... | | | |
191 | | ... | | | |
192 | ---------------------------------------------------------------- | |
193 | VSR[30] | FPR[30] | | | |
194 | ---------------------------------------------------------------- | |
195 | VSR[31] | FPR[31] | | | |
196 | ---------------------------------------------------------------- | |
197 | VSR[32] | VR[0] | | |
198 | ---------------------------------------------------------------- | |
199 | VSR[33] | VR[1] | | |
200 | ---------------------------------------------------------------- | |
201 | | ... | | |
202 | | ... | | |
203 | ---------------------------------------------------------------- | |
204 | VSR[62] | VR[30] | | |
205 | ---------------------------------------------------------------- | |
206 | VSR[63] | VR[31] | | |
207 | ---------------------------------------------------------------- | |
208 | ||
209 | VSX has 64 128bit registers. The first 32 registers overlap with | |
210 | the FP registers (doubleword 0) and hence extend them with additional | |
211 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
212 | registers. */ | |
213 | #define SIZEOF_VSXREGS 32*8 | |
214 | ||
215 | typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; | |
01904826 | 216 | |
b021a221 | 217 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 218 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
219 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
220 | ptrace calls only access the lower half of each register, to allow | |
221 | them to behave the same way they do on non-SPE systems. There's a | |
222 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
223 | read and write the top halves of all the general-purpose registers | |
224 | at once, along with some SPE-specific registers. | |
01904826 JB |
225 | |
226 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 227 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 228 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
229 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
230 | bottom halves together. | |
01904826 JB |
231 | |
232 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
233 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
234 | struct gdb_evrregset_t | |
235 | { | |
236 | unsigned long evr[32]; | |
237 | unsigned long long acc; | |
238 | unsigned long spefscr; | |
239 | }; | |
240 | ||
604c2f83 LM |
241 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
242 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
243 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
244 | gotten an error. Note that VSX registers 32 through 63 overlap | |
245 | with VR registers 0 through 31. */ | |
246 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
247 | |
248 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
249 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
250 | registers. Zero if we've tried one of them and gotten an | |
251 | error. */ | |
9abe5450 EZ |
252 | int have_ptrace_getvrregs = 1; |
253 | ||
01904826 JB |
254 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
255 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
256 | registers. Zero if we've tried one of them and gotten an | |
257 | error. */ | |
258 | int have_ptrace_getsetevrregs = 1; | |
259 | ||
1dfe79e8 SDJ |
260 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
261 | PTRACE_SETREGS requests, for reading and writing the | |
262 | general-purpose registers. Zero if we've tried one of | |
263 | them and gotten an error. */ | |
264 | int have_ptrace_getsetregs = 1; | |
265 | ||
266 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
267 | PTRACE_SETFPREGS requests, for reading and writing the | |
268 | floating-pointers registers. Zero if we've tried one of | |
269 | them and gotten an error. */ | |
270 | int have_ptrace_getsetfpregs = 1; | |
271 | ||
f6ac5f3d PA |
272 | struct ppc_linux_nat_target final : public linux_nat_target |
273 | { | |
274 | /* Add our register access methods. */ | |
275 | void fetch_registers (struct regcache *, int) override; | |
276 | void store_registers (struct regcache *, int) override; | |
277 | ||
278 | /* Add our breakpoint/watchpoint methods. */ | |
279 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
280 | ||
281 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
282 | override; | |
283 | ||
284 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
285 | override; | |
286 | ||
287 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
288 | ||
289 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
290 | struct expression *) override; | |
291 | ||
292 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
293 | struct expression *) override; | |
294 | ||
295 | int insert_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
296 | override; | |
297 | ||
298 | int remove_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
299 | override; | |
300 | ||
57810aa7 | 301 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 302 | |
57810aa7 | 303 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 304 | |
57810aa7 | 305 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d | 306 | |
57810aa7 | 307 | bool can_accel_watchpoint_condition (CORE_ADDR, int, int, struct expression *) |
f6ac5f3d PA |
308 | override; |
309 | ||
310 | int masked_watch_num_registers (CORE_ADDR, CORE_ADDR) override; | |
311 | ||
312 | int ranged_break_num_registers () override; | |
313 | ||
314 | const struct target_desc *read_description () override; | |
315 | ||
316 | int auxv_parse (gdb_byte **readptr, | |
317 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
318 | override; | |
135340af PA |
319 | |
320 | /* Override linux_nat_target low methods. */ | |
321 | void low_new_thread (struct lwp_info *lp) override; | |
f6ac5f3d PA |
322 | }; |
323 | ||
324 | static ppc_linux_nat_target the_ppc_linux_nat_target; | |
325 | ||
16333c4f EZ |
326 | /* *INDENT-OFF* */ |
327 | /* registers layout, as presented by the ptrace interface: | |
328 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
329 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
330 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
331 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
332 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
333 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
334 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
335 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
336 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
337 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
338 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
339 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f EZ |
340 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
341 | /* *INDENT_ON * */ | |
c877c8e6 | 342 | |
45229ea4 | 343 | static int |
e101270f | 344 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 345 | { |
16333c4f | 346 | int u_addr = -1; |
e101270f | 347 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
348 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
349 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 350 | int wordsize = sizeof (long); |
16333c4f | 351 | |
0df8b418 | 352 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
353 | if (regno >= tdep->ppc_gp0_regnum |
354 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 355 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 356 | |
49ff75ad JB |
357 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
358 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
359 | slot each in 64-bit interface. */ | |
383f0f5b JB |
360 | if (tdep->ppc_fp0_regnum >= 0 |
361 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
362 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
363 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 364 | |
0df8b418 | 365 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 366 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 367 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 368 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 369 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 370 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 371 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 372 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 373 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 374 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 375 | u_addr = PT_CTR * wordsize; |
f8c59253 | 376 | #ifdef PT_MQ |
dc5cfeb6 | 377 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 378 | u_addr = PT_MQ * wordsize; |
f8c59253 | 379 | #endif |
dc5cfeb6 | 380 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 381 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
382 | if (regno == PPC_ORIG_R3_REGNUM) |
383 | u_addr = PT_ORIG_R3 * wordsize; | |
384 | if (regno == PPC_TRAP_REGNUM) | |
385 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
386 | if (tdep->ppc_fpscr_regnum >= 0 |
387 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
388 | { |
389 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
390 | kernel headers incorrectly contained the 32-bit definition of | |
391 | PT_FPSCR. For the 32-bit definition, floating-point | |
392 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 393 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
394 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
395 | hence no adjustment is necessary. Hack around this. */ | |
396 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
397 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
398 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
399 | slot and not just its second word. The PT_FPSCR supplied when | |
400 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
401 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
402 | && PT_FPSCR == (48 + 2*32 + 1)) | |
403 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
404 | else |
405 | u_addr = PT_FPSCR * wordsize; | |
406 | } | |
16333c4f | 407 | return u_addr; |
c877c8e6 KB |
408 | } |
409 | ||
604c2f83 LM |
410 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
411 | registers set mechanism, as opposed to the interface for all the | |
412 | other registers, that stores/fetches each register individually. */ | |
413 | static void | |
414 | fetch_vsx_register (struct regcache *regcache, int tid, int regno) | |
415 | { | |
416 | int ret; | |
417 | gdb_vsxregset_t regs; | |
ac7936df | 418 | struct gdbarch *gdbarch = regcache->arch (); |
604c2f83 LM |
419 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
420 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
421 | ||
422 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
423 | if (ret < 0) | |
424 | { | |
425 | if (errno == EIO) | |
426 | { | |
427 | have_ptrace_getsetvsxregs = 0; | |
428 | return; | |
429 | } | |
430 | perror_with_name (_("Unable to fetch VSX register")); | |
431 | } | |
432 | ||
433 | regcache_raw_supply (regcache, regno, | |
434 | regs + (regno - tdep->ppc_vsr0_upper_regnum) | |
435 | * vsxregsize); | |
436 | } | |
437 | ||
9abe5450 EZ |
438 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
439 | registers set mechanism, as opposed to the interface for all the | |
440 | other registers, that stores/fetches each register individually. */ | |
441 | static void | |
56be3814 | 442 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
443 | { |
444 | int ret; | |
445 | int offset = 0; | |
446 | gdb_vrregset_t regs; | |
ac7936df | 447 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 MD |
448 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
449 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
450 | |
451 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
452 | if (ret < 0) | |
453 | { | |
454 | if (errno == EIO) | |
455 | { | |
456 | have_ptrace_getvrregs = 0; | |
457 | return; | |
458 | } | |
e2e0b3e5 | 459 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
460 | } |
461 | ||
462 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
463 | long on the hardware. We deal only with the lower 4 bytes of the | |
464 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
465 | there is no need to define an offset for it. */ | |
466 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 467 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 468 | |
56be3814 | 469 | regcache_raw_supply (regcache, regno, |
0df8b418 MS |
470 | regs + (regno |
471 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
472 | } |
473 | ||
01904826 JB |
474 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
475 | SPE-specific registers, and place the results in EVRREGSET. If we | |
476 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
477 | zeros. | |
478 | ||
479 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
480 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
481 | set_spe_registers. */ | |
482 | static void | |
483 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
484 | { | |
485 | if (have_ptrace_getsetevrregs) | |
486 | { | |
487 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
488 | return; | |
489 | else | |
490 | { | |
491 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
492 | we just return zeros. */ | |
493 | if (errno == EIO) | |
494 | have_ptrace_getsetevrregs = 0; | |
495 | else | |
496 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 497 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
498 | } |
499 | } | |
500 | ||
501 | memset (evrregset, 0, sizeof (*evrregset)); | |
502 | } | |
503 | ||
6ced10dd JB |
504 | /* Supply values from TID for SPE-specific raw registers: the upper |
505 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
506 | be the number of an upper half register, acc, spefscr, or -1 to | |
507 | supply the values of all registers. */ | |
01904826 | 508 | static void |
56be3814 | 509 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 510 | { |
ac7936df | 511 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 512 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
513 | struct gdb_evrregset_t evrregs; |
514 | ||
6ced10dd | 515 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 516 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 517 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 518 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 519 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 520 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 521 | |
01904826 JB |
522 | get_spe_registers (tid, &evrregs); |
523 | ||
6ced10dd | 524 | if (regno == -1) |
01904826 | 525 | { |
6ced10dd JB |
526 | int i; |
527 | ||
528 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 529 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 530 | &evrregs.evr[i]); |
01904826 | 531 | } |
6ced10dd JB |
532 | else if (tdep->ppc_ev0_upper_regnum <= regno |
533 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 534 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
535 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
536 | ||
537 | if (regno == -1 | |
538 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 539 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
540 | |
541 | if (regno == -1 | |
542 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 543 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 544 | &evrregs.spefscr); |
01904826 JB |
545 | } |
546 | ||
45229ea4 | 547 | static void |
56be3814 | 548 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 549 | { |
ac7936df | 550 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 551 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
45229ea4 | 552 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 553 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 554 | int bytes_transferred; |
0df8b418 | 555 | unsigned int offset; /* Offset of registers within the u area. */ |
0f068fb5 | 556 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 557 | |
be8626e0 | 558 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
559 | { |
560 | /* If this is the first time through, or if it is not the first | |
561 | time through, and we have comfirmed that there is kernel | |
562 | support for such a ptrace request, then go and fetch the | |
563 | register. */ | |
564 | if (have_ptrace_getvrregs) | |
565 | { | |
56be3814 | 566 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
567 | return; |
568 | } | |
569 | /* If we have discovered that there is no ptrace support for | |
570 | AltiVec registers, fall through and return zeroes, because | |
571 | regaddr will be -1 in this case. */ | |
572 | } | |
604c2f83 LM |
573 | if (vsx_register_p (gdbarch, regno)) |
574 | { | |
575 | if (have_ptrace_getsetvsxregs) | |
576 | { | |
577 | fetch_vsx_register (regcache, tid, regno); | |
578 | return; | |
579 | } | |
580 | } | |
be8626e0 | 581 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 582 | { |
56be3814 | 583 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
584 | return; |
585 | } | |
9abe5450 | 586 | |
45229ea4 EZ |
587 | if (regaddr == -1) |
588 | { | |
40a6adc1 | 589 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 590 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
591 | return; |
592 | } | |
593 | ||
411cb3f9 | 594 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
595 | 32-bit platform, 64-bit floating-point registers will require two |
596 | transfers. */ | |
4a19ea35 | 597 | for (bytes_transferred = 0; |
40a6adc1 | 598 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 599 | bytes_transferred += sizeof (long)) |
45229ea4 | 600 | { |
11fde611 JK |
601 | long l; |
602 | ||
45229ea4 | 603 | errno = 0; |
11fde611 | 604 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 605 | regaddr += sizeof (long); |
45229ea4 EZ |
606 | if (errno != 0) |
607 | { | |
bc97b3ba | 608 | char message[128]; |
8c042590 PM |
609 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
610 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 611 | perror_with_name (message); |
45229ea4 | 612 | } |
11fde611 | 613 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 614 | } |
56d0d96a | 615 | |
4a19ea35 JB |
616 | /* Now supply the register. Keep in mind that the regcache's idea |
617 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 618 | (long). */ |
40a6adc1 | 619 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
620 | { |
621 | /* Little-endian values are always found at the left end of the | |
622 | bytes transferred. */ | |
56be3814 | 623 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 | 624 | } |
40a6adc1 | 625 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
626 | { |
627 | /* Big-endian values are found at the right end of the bytes | |
628 | transferred. */ | |
40a6adc1 | 629 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
56be3814 | 630 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
631 | } |
632 | else | |
a44bddec | 633 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 634 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 635 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
636 | } |
637 | ||
604c2f83 LM |
638 | static void |
639 | supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
640 | { | |
641 | int i; | |
ac7936df | 642 | struct gdbarch *gdbarch = regcache->arch (); |
604c2f83 LM |
643 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
644 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
645 | ||
646 | for (i = 0; i < ppc_num_vshrs; i++) | |
647 | { | |
648 | regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
649 | *vsxregsetp + i * vsxregsize); | |
650 | } | |
651 | } | |
652 | ||
9abe5450 | 653 | static void |
56be3814 | 654 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
655 | { |
656 | int i; | |
ac7936df | 657 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 658 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9abe5450 | 659 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
660 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
661 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
662 | |
663 | for (i = 0; i < num_of_vrregs; i++) | |
664 | { | |
665 | /* The last 2 registers of this set are only 32 bit long, not | |
666 | 128. However an offset is necessary only for VSCR because it | |
667 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
668 | slot. */ | |
669 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 670 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 671 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 672 | else |
56be3814 | 673 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 674 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
675 | } |
676 | } | |
677 | ||
604c2f83 LM |
678 | static void |
679 | fetch_vsx_registers (struct regcache *regcache, int tid) | |
680 | { | |
681 | int ret; | |
682 | gdb_vsxregset_t regs; | |
683 | ||
684 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
685 | if (ret < 0) | |
686 | { | |
687 | if (errno == EIO) | |
688 | { | |
689 | have_ptrace_getsetvsxregs = 0; | |
690 | return; | |
691 | } | |
692 | perror_with_name (_("Unable to fetch VSX registers")); | |
693 | } | |
694 | supply_vsxregset (regcache, ®s); | |
695 | } | |
696 | ||
9abe5450 | 697 | static void |
56be3814 | 698 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
699 | { |
700 | int ret; | |
701 | gdb_vrregset_t regs; | |
702 | ||
703 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
704 | if (ret < 0) | |
705 | { | |
706 | if (errno == EIO) | |
707 | { | |
708 | have_ptrace_getvrregs = 0; | |
709 | return; | |
710 | } | |
e2e0b3e5 | 711 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 712 | } |
56be3814 | 713 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
714 | } |
715 | ||
1dfe79e8 SDJ |
716 | /* This function actually issues the request to ptrace, telling |
717 | it to get all general-purpose registers and put them into the | |
718 | specified regset. | |
719 | ||
720 | If the ptrace request does not exist, this function returns 0 | |
721 | and properly sets the have_ptrace_* flag. If the request fails, | |
722 | this function calls perror_with_name. Otherwise, if the request | |
723 | succeeds, then the regcache gets filled and 1 is returned. */ | |
724 | static int | |
725 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
726 | { | |
ac7936df | 727 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
728 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
729 | gdb_gregset_t gregset; | |
730 | ||
731 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
732 | { | |
733 | if (errno == EIO) | |
734 | { | |
735 | have_ptrace_getsetregs = 0; | |
736 | return 0; | |
737 | } | |
738 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
739 | } | |
740 | ||
741 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
742 | ||
743 | return 1; | |
744 | } | |
745 | ||
746 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
747 | responsible for verifying if this target has the ptrace request | |
748 | that can be used to fetch all general-purpose registers at one | |
749 | shot. If it doesn't, then we should fetch them using the | |
750 | old-fashioned way, which is to iterate over the registers and | |
751 | request them one by one. */ | |
752 | static void | |
753 | fetch_gp_regs (struct regcache *regcache, int tid) | |
754 | { | |
ac7936df | 755 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
756 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
757 | int i; | |
758 | ||
759 | if (have_ptrace_getsetregs) | |
760 | if (fetch_all_gp_regs (regcache, tid)) | |
761 | return; | |
762 | ||
763 | /* If we've hit this point, it doesn't really matter which | |
764 | architecture we are using. We just need to read the | |
765 | registers in the "old-fashioned way". */ | |
766 | for (i = 0; i < ppc_num_gprs; i++) | |
767 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
768 | } | |
769 | ||
770 | /* This function actually issues the request to ptrace, telling | |
771 | it to get all floating-point registers and put them into the | |
772 | specified regset. | |
773 | ||
774 | If the ptrace request does not exist, this function returns 0 | |
775 | and properly sets the have_ptrace_* flag. If the request fails, | |
776 | this function calls perror_with_name. Otherwise, if the request | |
777 | succeeds, then the regcache gets filled and 1 is returned. */ | |
778 | static int | |
779 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
780 | { | |
781 | gdb_fpregset_t fpregs; | |
782 | ||
783 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
784 | { | |
785 | if (errno == EIO) | |
786 | { | |
787 | have_ptrace_getsetfpregs = 0; | |
788 | return 0; | |
789 | } | |
790 | perror_with_name (_("Couldn't get floating-point registers.")); | |
791 | } | |
792 | ||
793 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
794 | ||
795 | return 1; | |
796 | } | |
797 | ||
798 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
799 | responsible for verifying if this target has the ptrace request | |
800 | that can be used to fetch all floating-point registers at one | |
801 | shot. If it doesn't, then we should fetch them using the | |
802 | old-fashioned way, which is to iterate over the registers and | |
803 | request them one by one. */ | |
804 | static void | |
805 | fetch_fp_regs (struct regcache *regcache, int tid) | |
806 | { | |
ac7936df | 807 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
808 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
809 | int i; | |
810 | ||
811 | if (have_ptrace_getsetfpregs) | |
812 | if (fetch_all_fp_regs (regcache, tid)) | |
813 | return; | |
814 | ||
815 | /* If we've hit this point, it doesn't really matter which | |
816 | architecture we are using. We just need to read the | |
817 | registers in the "old-fashioned way". */ | |
818 | for (i = 0; i < ppc_num_fprs; i++) | |
819 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
820 | } | |
821 | ||
45229ea4 | 822 | static void |
56be3814 | 823 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
824 | { |
825 | int i; | |
ac7936df | 826 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 827 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9abe5450 | 828 | |
1dfe79e8 | 829 | fetch_gp_regs (regcache, tid); |
32b99774 | 830 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 831 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 832 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 833 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 834 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 835 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 836 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 837 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 838 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 839 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 840 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 841 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 842 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 843 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 844 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
845 | if (ppc_linux_trap_reg_p (gdbarch)) |
846 | { | |
847 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
848 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
849 | } | |
32b99774 | 850 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 851 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
852 | if (have_ptrace_getvrregs) |
853 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 854 | fetch_altivec_registers (regcache, tid); |
604c2f83 LM |
855 | if (have_ptrace_getsetvsxregs) |
856 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
857 | fetch_vsx_registers (regcache, tid); | |
6ced10dd | 858 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 859 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
860 | } |
861 | ||
862 | /* Fetch registers from the child process. Fetch all registers if | |
863 | regno == -1, otherwise fetch all general registers or all floating | |
864 | point registers depending upon the value of regno. */ | |
f6ac5f3d PA |
865 | void |
866 | ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
45229ea4 | 867 | { |
bcc0c096 | 868 | pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache)); |
05f13b9c | 869 | |
9abe5450 | 870 | if (regno == -1) |
56be3814 | 871 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 872 | else |
56be3814 | 873 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
874 | } |
875 | ||
0df8b418 | 876 | /* Store one VSX register. */ |
604c2f83 LM |
877 | static void |
878 | store_vsx_register (const struct regcache *regcache, int tid, int regno) | |
879 | { | |
880 | int ret; | |
881 | gdb_vsxregset_t regs; | |
ac7936df | 882 | struct gdbarch *gdbarch = regcache->arch (); |
604c2f83 LM |
883 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
884 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
885 | ||
9fe70b4f | 886 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
887 | if (ret < 0) |
888 | { | |
889 | if (errno == EIO) | |
890 | { | |
891 | have_ptrace_getsetvsxregs = 0; | |
892 | return; | |
893 | } | |
894 | perror_with_name (_("Unable to fetch VSX register")); | |
895 | } | |
896 | ||
897 | regcache_raw_collect (regcache, regno, regs + | |
898 | (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); | |
899 | ||
900 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
901 | if (ret < 0) | |
902 | perror_with_name (_("Unable to store VSX register")); | |
903 | } | |
904 | ||
0df8b418 | 905 | /* Store one register. */ |
9abe5450 | 906 | static void |
56be3814 | 907 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
908 | { |
909 | int ret; | |
910 | int offset = 0; | |
911 | gdb_vrregset_t regs; | |
ac7936df | 912 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 MD |
913 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
914 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
915 | |
916 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
917 | if (ret < 0) | |
918 | { | |
919 | if (errno == EIO) | |
920 | { | |
921 | have_ptrace_getvrregs = 0; | |
922 | return; | |
923 | } | |
e2e0b3e5 | 924 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
925 | } |
926 | ||
927 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
928 | long on the hardware. */ | |
929 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 930 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 931 | |
56be3814 | 932 | regcache_raw_collect (regcache, regno, |
0df8b418 MS |
933 | regs + (regno |
934 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
935 | |
936 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
937 | if (ret < 0) | |
e2e0b3e5 | 938 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
939 | } |
940 | ||
01904826 JB |
941 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
942 | general-purpose registers and its SPE-specific registers to the | |
943 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
944 | nothing. | |
945 | ||
946 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
947 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
948 | get_spe_registers. */ | |
949 | static void | |
950 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
951 | { | |
952 | if (have_ptrace_getsetevrregs) | |
953 | { | |
954 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
955 | return; | |
956 | else | |
957 | { | |
958 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
959 | supported; we fail silently, and don't try the call | |
960 | again. */ | |
961 | if (errno == EIO) | |
962 | have_ptrace_getsetevrregs = 0; | |
963 | else | |
964 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 965 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
966 | } |
967 | } | |
968 | } | |
969 | ||
6ced10dd JB |
970 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
971 | If REGNO is -1, write the values of all the SPE-specific | |
972 | registers. */ | |
01904826 | 973 | static void |
56be3814 | 974 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 975 | { |
ac7936df | 976 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 977 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
978 | struct gdb_evrregset_t evrregs; |
979 | ||
6ced10dd | 980 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 981 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 982 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 983 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 984 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 985 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 986 | |
6ced10dd JB |
987 | if (regno == -1) |
988 | /* Since we're going to write out every register, the code below | |
989 | should store to every field of evrregs; if that doesn't happen, | |
990 | make it obvious by initializing it with suspicious values. */ | |
991 | memset (&evrregs, 42, sizeof (evrregs)); | |
992 | else | |
993 | /* We can only read and write the entire EVR register set at a | |
994 | time, so to write just a single register, we do a | |
995 | read-modify-write maneuver. */ | |
996 | get_spe_registers (tid, &evrregs); | |
997 | ||
998 | if (regno == -1) | |
01904826 | 999 | { |
6ced10dd JB |
1000 | int i; |
1001 | ||
1002 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 1003 | regcache_raw_collect (regcache, |
6ced10dd JB |
1004 | tdep->ppc_ev0_upper_regnum + i, |
1005 | &evrregs.evr[i]); | |
01904826 | 1006 | } |
6ced10dd JB |
1007 | else if (tdep->ppc_ev0_upper_regnum <= regno |
1008 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 1009 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
1010 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
1011 | ||
1012 | if (regno == -1 | |
1013 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 1014 | regcache_raw_collect (regcache, |
6ced10dd JB |
1015 | tdep->ppc_acc_regnum, |
1016 | &evrregs.acc); | |
1017 | ||
1018 | if (regno == -1 | |
1019 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 1020 | regcache_raw_collect (regcache, |
6ced10dd JB |
1021 | tdep->ppc_spefscr_regnum, |
1022 | &evrregs.spefscr); | |
01904826 JB |
1023 | |
1024 | /* Write back the modified register set. */ | |
1025 | set_spe_registers (tid, &evrregs); | |
1026 | } | |
1027 | ||
45229ea4 | 1028 | static void |
56be3814 | 1029 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1030 | { |
ac7936df | 1031 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1032 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
45229ea4 | 1033 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 1034 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 1035 | int i; |
4a19ea35 | 1036 | size_t bytes_to_transfer; |
0f068fb5 | 1037 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 1038 | |
be8626e0 | 1039 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 1040 | { |
56be3814 | 1041 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
1042 | return; |
1043 | } | |
604c2f83 LM |
1044 | if (vsx_register_p (gdbarch, regno)) |
1045 | { | |
1046 | store_vsx_register (regcache, tid, regno); | |
1047 | return; | |
1048 | } | |
be8626e0 | 1049 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 1050 | { |
56be3814 | 1051 | store_spe_register (regcache, tid, regno); |
01904826 JB |
1052 | return; |
1053 | } | |
45229ea4 | 1054 | |
9abe5450 EZ |
1055 | if (regaddr == -1) |
1056 | return; | |
1057 | ||
4a19ea35 JB |
1058 | /* First collect the register. Keep in mind that the regcache's |
1059 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1060 | (long). */ |
56d0d96a | 1061 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
1062 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
1063 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
1064 | { |
1065 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 1066 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 1067 | } |
40a6adc1 | 1068 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1069 | { |
1070 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 1071 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
56be3814 | 1072 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
1073 | } |
1074 | ||
411cb3f9 | 1075 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 1076 | { |
11fde611 JK |
1077 | long l; |
1078 | ||
1079 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 1080 | errno = 0; |
11fde611 | 1081 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 1082 | regaddr += sizeof (long); |
e3f36dbd KB |
1083 | |
1084 | if (errno == EIO | |
7284e1be UW |
1085 | && (regno == tdep->ppc_fpscr_regnum |
1086 | || regno == PPC_ORIG_R3_REGNUM | |
1087 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1088 | { |
7284e1be UW |
1089 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1090 | or trap to be written. */ | |
e3f36dbd KB |
1091 | continue; |
1092 | } | |
1093 | ||
45229ea4 EZ |
1094 | if (errno != 0) |
1095 | { | |
bc97b3ba | 1096 | char message[128]; |
8c042590 PM |
1097 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
1098 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 1099 | perror_with_name (message); |
45229ea4 EZ |
1100 | } |
1101 | } | |
1102 | } | |
1103 | ||
604c2f83 LM |
1104 | static void |
1105 | fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
1106 | { | |
1107 | int i; | |
ac7936df | 1108 | struct gdbarch *gdbarch = regcache->arch (); |
604c2f83 LM |
1109 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1110 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
1111 | ||
1112 | for (i = 0; i < ppc_num_vshrs; i++) | |
1113 | regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
1114 | *vsxregsetp + i * vsxregsize); | |
1115 | } | |
1116 | ||
9abe5450 | 1117 | static void |
56be3814 | 1118 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
1119 | { |
1120 | int i; | |
ac7936df | 1121 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1122 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9abe5450 | 1123 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
1124 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
1125 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
1126 | |
1127 | for (i = 0; i < num_of_vrregs; i++) | |
1128 | { | |
1129 | /* The last 2 registers of this set are only 32 bit long, not | |
1130 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
1131 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 1132 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1133 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 1134 | else |
56be3814 | 1135 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1136 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
1137 | } |
1138 | } | |
1139 | ||
604c2f83 LM |
1140 | static void |
1141 | store_vsx_registers (const struct regcache *regcache, int tid) | |
1142 | { | |
1143 | int ret; | |
1144 | gdb_vsxregset_t regs; | |
1145 | ||
1146 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
1147 | if (ret < 0) | |
1148 | { | |
1149 | if (errno == EIO) | |
1150 | { | |
1151 | have_ptrace_getsetvsxregs = 0; | |
1152 | return; | |
1153 | } | |
1154 | perror_with_name (_("Couldn't get VSX registers")); | |
1155 | } | |
1156 | ||
1157 | fill_vsxregset (regcache, ®s); | |
1158 | ||
1159 | if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) | |
1160 | perror_with_name (_("Couldn't write VSX registers")); | |
1161 | } | |
1162 | ||
9abe5450 | 1163 | static void |
56be3814 | 1164 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
1165 | { |
1166 | int ret; | |
1167 | gdb_vrregset_t regs; | |
1168 | ||
0897f59b | 1169 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
1170 | if (ret < 0) |
1171 | { | |
1172 | if (errno == EIO) | |
1173 | { | |
1174 | have_ptrace_getvrregs = 0; | |
1175 | return; | |
1176 | } | |
e2e0b3e5 | 1177 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
1178 | } |
1179 | ||
56be3814 | 1180 | fill_vrregset (regcache, ®s); |
9abe5450 | 1181 | |
0897f59b | 1182 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 1183 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
1184 | } |
1185 | ||
1dfe79e8 SDJ |
1186 | /* This function actually issues the request to ptrace, telling |
1187 | it to store all general-purpose registers present in the specified | |
1188 | regset. | |
1189 | ||
1190 | If the ptrace request does not exist, this function returns 0 | |
1191 | and properly sets the have_ptrace_* flag. If the request fails, | |
1192 | this function calls perror_with_name. Otherwise, if the request | |
1193 | succeeds, then the regcache is stored and 1 is returned. */ | |
1194 | static int | |
1195 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1196 | { | |
ac7936df | 1197 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1198 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1199 | gdb_gregset_t gregset; | |
1200 | ||
1201 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1202 | { | |
1203 | if (errno == EIO) | |
1204 | { | |
1205 | have_ptrace_getsetregs = 0; | |
1206 | return 0; | |
1207 | } | |
1208 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1209 | } | |
1210 | ||
1211 | fill_gregset (regcache, &gregset, regno); | |
1212 | ||
1213 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1214 | { | |
1215 | if (errno == EIO) | |
1216 | { | |
1217 | have_ptrace_getsetregs = 0; | |
1218 | return 0; | |
1219 | } | |
1220 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1221 | } | |
1222 | ||
1223 | return 1; | |
1224 | } | |
1225 | ||
1226 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1227 | responsible for verifying if this target has the ptrace request | |
1228 | that can be used to store all general-purpose registers at one | |
1229 | shot. If it doesn't, then we should store them using the | |
1230 | old-fashioned way, which is to iterate over the registers and | |
1231 | store them one by one. */ | |
45229ea4 | 1232 | static void |
1dfe79e8 | 1233 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1234 | { |
ac7936df | 1235 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dfe79e8 SDJ |
1237 | int i; |
1238 | ||
1239 | if (have_ptrace_getsetregs) | |
1240 | if (store_all_gp_regs (regcache, tid, regno)) | |
1241 | return; | |
1242 | ||
1243 | /* If we hit this point, it doesn't really matter which | |
1244 | architecture we are using. We just need to store the | |
1245 | registers in the "old-fashioned way". */ | |
6ced10dd | 1246 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1247 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1248 | } |
1249 | ||
1250 | /* This function actually issues the request to ptrace, telling | |
1251 | it to store all floating-point registers present in the specified | |
1252 | regset. | |
1253 | ||
1254 | If the ptrace request does not exist, this function returns 0 | |
1255 | and properly sets the have_ptrace_* flag. If the request fails, | |
1256 | this function calls perror_with_name. Otherwise, if the request | |
1257 | succeeds, then the regcache is stored and 1 is returned. */ | |
1258 | static int | |
1259 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1260 | { | |
1261 | gdb_fpregset_t fpregs; | |
1262 | ||
1263 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1264 | { | |
1265 | if (errno == EIO) | |
1266 | { | |
1267 | have_ptrace_getsetfpregs = 0; | |
1268 | return 0; | |
1269 | } | |
1270 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1271 | } | |
1272 | ||
1273 | fill_fpregset (regcache, &fpregs, regno); | |
1274 | ||
1275 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1276 | { | |
1277 | if (errno == EIO) | |
1278 | { | |
1279 | have_ptrace_getsetfpregs = 0; | |
1280 | return 0; | |
1281 | } | |
1282 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1283 | } | |
1284 | ||
1285 | return 1; | |
1286 | } | |
1287 | ||
1288 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1289 | responsible for verifying if this target has the ptrace request | |
1290 | that can be used to store all floating-point registers at one | |
1291 | shot. If it doesn't, then we should store them using the | |
1292 | old-fashioned way, which is to iterate over the registers and | |
1293 | store them one by one. */ | |
1294 | static void | |
1295 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1296 | { | |
ac7936df | 1297 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1298 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1299 | int i; | |
1300 | ||
1301 | if (have_ptrace_getsetfpregs) | |
1302 | if (store_all_fp_regs (regcache, tid, regno)) | |
1303 | return; | |
1304 | ||
1305 | /* If we hit this point, it doesn't really matter which | |
1306 | architecture we are using. We just need to store the | |
1307 | registers in the "old-fashioned way". */ | |
1308 | for (i = 0; i < ppc_num_fprs; i++) | |
1309 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1310 | } | |
1311 | ||
1312 | static void | |
1313 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1314 | { | |
1315 | int i; | |
ac7936df | 1316 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1317 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1318 | ||
1319 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1320 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1321 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1322 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1323 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1324 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1325 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1326 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1327 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1328 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1329 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1330 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1331 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1332 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1333 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1334 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1335 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1336 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1337 | if (ppc_linux_trap_reg_p (gdbarch)) |
1338 | { | |
1339 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1340 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1341 | } | |
9abe5450 EZ |
1342 | if (have_ptrace_getvrregs) |
1343 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 1344 | store_altivec_registers (regcache, tid); |
604c2f83 LM |
1345 | if (have_ptrace_getsetvsxregs) |
1346 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
1347 | store_vsx_registers (regcache, tid); | |
6ced10dd | 1348 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1349 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
1350 | } |
1351 | ||
6ffbb7ab | 1352 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
b261e0c5 UW |
1353 | static unsigned long |
1354 | ppc_linux_get_hwcap (void) | |
6ffbb7ab TJB |
1355 | { |
1356 | CORE_ADDR field; | |
1357 | ||
f6ac5f3d | 1358 | if (target_auxv_search (target_stack, AT_HWCAP, &field)) |
6ffbb7ab TJB |
1359 | return (unsigned long) field; |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
1364 | /* The cached DABR value, to install in new threads. | |
926bf92d UW |
1365 | This variable is used when the PowerPC HWDEBUG ptrace |
1366 | interface is not available. */ | |
6ffbb7ab TJB |
1367 | static long saved_dabr_value; |
1368 | ||
1369 | /* Global structure that will store information about the available | |
926bf92d UW |
1370 | features provided by the PowerPC HWDEBUG ptrace interface. */ |
1371 | static struct ppc_debug_info hwdebug_info; | |
6ffbb7ab TJB |
1372 | |
1373 | /* Global variable that holds the maximum number of slots that the | |
926bf92d UW |
1374 | kernel will use. This is only used when PowerPC HWDEBUG ptrace interface |
1375 | is available. */ | |
6ffbb7ab TJB |
1376 | static size_t max_slots_number = 0; |
1377 | ||
1378 | struct hw_break_tuple | |
1379 | { | |
1380 | long slot; | |
1381 | struct ppc_hw_breakpoint *hw_break; | |
1382 | }; | |
1383 | ||
1384 | /* This is an internal VEC created to store information about *points inserted | |
926bf92d UW |
1385 | for each thread. This is used when PowerPC HWDEBUG ptrace interface is |
1386 | available. */ | |
6ffbb7ab TJB |
1387 | typedef struct thread_points |
1388 | { | |
1389 | /* The TID to which this *point relates. */ | |
1390 | int tid; | |
1391 | /* Information about the *point, such as its address, type, etc. | |
1392 | ||
1393 | Each element inside this vector corresponds to a hardware | |
1394 | breakpoint or watchpoint in the thread represented by TID. The maximum | |
1395 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of | |
1396 | the tuple is NULL, then the position in the vector is free. */ | |
1397 | struct hw_break_tuple *hw_breaks; | |
1398 | } *thread_points_p; | |
1399 | DEF_VEC_P (thread_points_p); | |
1400 | ||
1401 | VEC(thread_points_p) *ppc_threads = NULL; | |
1402 | ||
926bf92d UW |
1403 | /* The version of the PowerPC HWDEBUG kernel interface that we will use, if |
1404 | available. */ | |
6ffbb7ab TJB |
1405 | #define PPC_DEBUG_CURRENT_VERSION 1 |
1406 | ||
926bf92d | 1407 | /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */ |
e0d24f8d | 1408 | static int |
926bf92d | 1409 | have_ptrace_hwdebug_interface (void) |
e0d24f8d | 1410 | { |
926bf92d | 1411 | static int have_ptrace_hwdebug_interface = -1; |
e0d24f8d | 1412 | |
926bf92d | 1413 | if (have_ptrace_hwdebug_interface == -1) |
6ffbb7ab TJB |
1414 | { |
1415 | int tid; | |
e0d24f8d | 1416 | |
dfd4cc63 | 1417 | tid = ptid_get_lwp (inferior_ptid); |
6ffbb7ab | 1418 | if (tid == 0) |
dfd4cc63 | 1419 | tid = ptid_get_pid (inferior_ptid); |
e0d24f8d | 1420 | |
926bf92d UW |
1421 | /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ |
1422 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) | |
6ffbb7ab | 1423 | { |
926bf92d | 1424 | /* Check whether PowerPC HWDEBUG ptrace interface is functional and |
0c56f59b | 1425 | provides any supported feature. */ |
926bf92d | 1426 | if (hwdebug_info.features != 0) |
0c56f59b | 1427 | { |
926bf92d UW |
1428 | have_ptrace_hwdebug_interface = 1; |
1429 | max_slots_number = hwdebug_info.num_instruction_bps | |
1430 | + hwdebug_info.num_data_bps | |
1431 | + hwdebug_info.num_condition_regs; | |
1432 | return have_ptrace_hwdebug_interface; | |
0c56f59b | 1433 | } |
6ffbb7ab | 1434 | } |
926bf92d UW |
1435 | /* Old school interface and no PowerPC HWDEBUG ptrace support. */ |
1436 | have_ptrace_hwdebug_interface = 0; | |
1437 | memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info)); | |
6ffbb7ab TJB |
1438 | } |
1439 | ||
926bf92d | 1440 | return have_ptrace_hwdebug_interface; |
e0d24f8d WZ |
1441 | } |
1442 | ||
f6ac5f3d PA |
1443 | int |
1444 | ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, int ot) | |
b7622095 | 1445 | { |
6ffbb7ab | 1446 | int total_hw_wp, total_hw_bp; |
b7622095 | 1447 | |
926bf92d | 1448 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab | 1449 | { |
926bf92d UW |
1450 | /* When PowerPC HWDEBUG ptrace interface is available, the number of |
1451 | available hardware watchpoints and breakpoints is stored at the | |
1452 | hwdebug_info struct. */ | |
1453 | total_hw_bp = hwdebug_info.num_instruction_bps; | |
1454 | total_hw_wp = hwdebug_info.num_data_bps; | |
6ffbb7ab TJB |
1455 | } |
1456 | else | |
1457 | { | |
926bf92d UW |
1458 | /* When we do not have PowerPC HWDEBUG ptrace interface, we should |
1459 | consider having 1 hardware watchpoint and no hardware breakpoints. */ | |
6ffbb7ab TJB |
1460 | total_hw_bp = 0; |
1461 | total_hw_wp = 1; | |
1462 | } | |
b7622095 | 1463 | |
6ffbb7ab TJB |
1464 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
1465 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
1466 | { | |
bb08bdbd | 1467 | if (cnt + ot > total_hw_wp) |
6ffbb7ab TJB |
1468 | return -1; |
1469 | } | |
1470 | else if (type == bp_hardware_breakpoint) | |
1471 | { | |
572f6555 EBM |
1472 | if (total_hw_bp == 0) |
1473 | { | |
1474 | /* No hardware breakpoint support. */ | |
1475 | return 0; | |
1476 | } | |
6ffbb7ab TJB |
1477 | if (cnt > total_hw_bp) |
1478 | return -1; | |
1479 | } | |
1480 | ||
926bf92d | 1481 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1482 | { |
1483 | int tid; | |
1484 | ptid_t ptid = inferior_ptid; | |
1485 | ||
0df8b418 MS |
1486 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
1487 | and whether the target has DABR. If either answer is no, the | |
1488 | ptrace call will return -1. Fail in that case. */ | |
dfd4cc63 | 1489 | tid = ptid_get_lwp (ptid); |
6ffbb7ab | 1490 | if (tid == 0) |
dfd4cc63 | 1491 | tid = ptid_get_pid (ptid); |
6ffbb7ab TJB |
1492 | |
1493 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1494 | return 0; | |
1495 | } | |
1496 | ||
1497 | return 1; | |
b7622095 LM |
1498 | } |
1499 | ||
f6ac5f3d PA |
1500 | int |
1501 | ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e0d24f8d WZ |
1502 | { |
1503 | /* Handle sub-8-byte quantities. */ | |
1504 | if (len <= 0) | |
1505 | return 0; | |
1506 | ||
926bf92d UW |
1507 | /* The PowerPC HWDEBUG ptrace interface tells if there are alignment |
1508 | restrictions for watchpoints in the processors. In that case, we use that | |
1509 | information to determine the hardcoded watchable region for | |
1510 | watchpoints. */ | |
1511 | if (have_ptrace_hwdebug_interface ()) | |
6ffbb7ab | 1512 | { |
e23b9d6e | 1513 | int region_size; |
4feebbdd EBM |
1514 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
1515 | watchpoints and can watch any access within an arbitrary memory | |
1516 | region. This is useful to watch arrays and structs, for instance. It | |
1517 | takes two hardware watchpoints though. */ | |
e09342b5 | 1518 | if (len > 1 |
926bf92d | 1519 | && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
4feebbdd | 1520 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
e09342b5 | 1521 | return 2; |
e23b9d6e UW |
1522 | /* Check if the processor provides DAWR interface. */ |
1523 | if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) | |
1524 | /* DAWR interface allows to watch up to 512 byte wide ranges which | |
1525 | can't cross a 512 byte boundary. */ | |
1526 | region_size = 512; | |
1527 | else | |
1528 | region_size = hwdebug_info.data_bp_alignment; | |
4feebbdd EBM |
1529 | /* Server processors provide one hardware watchpoint and addr+len should |
1530 | fall in the watchable region provided by the ptrace interface. */ | |
e23b9d6e UW |
1531 | if (region_size |
1532 | && (addr + len > (addr & ~(region_size - 1)) + region_size)) | |
0cf6dd15 | 1533 | return 0; |
6ffbb7ab | 1534 | } |
b7622095 | 1535 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
926bf92d UW |
1536 | processors (i.e., server processors). Without the new PowerPC HWDEBUG |
1537 | ptrace interface, DAC-based processors (i.e., embedded processors) will | |
1538 | use addresses aligned to 4-bytes due to the way the read/write flags are | |
6ffbb7ab TJB |
1539 | passed in the old ptrace interface. */ |
1540 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1541 | && (addr + len) > (addr & ~3) + 4) | |
1542 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1543 | return 0; |
1544 | ||
1545 | return 1; | |
1546 | } | |
1547 | ||
6ffbb7ab | 1548 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
e4166a49 | 1549 | static int |
926bf92d | 1550 | hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
6ffbb7ab | 1551 | { |
ad422571 TJB |
1552 | return (a->trigger_type == b->trigger_type |
1553 | && a->addr_mode == b->addr_mode | |
1554 | && a->condition_mode == b->condition_mode | |
1555 | && a->addr == b->addr | |
1556 | && a->addr2 == b->addr2 | |
6ffbb7ab TJB |
1557 | && a->condition_value == b->condition_value); |
1558 | } | |
1559 | ||
1560 | /* This function can be used to retrieve a thread_points by the TID of the | |
1561 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, | |
1562 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the | |
1563 | provided TID will be created and returned. */ | |
1564 | static struct thread_points * | |
926bf92d | 1565 | hwdebug_find_thread_points_by_tid (int tid, int alloc_new) |
6ffbb7ab TJB |
1566 | { |
1567 | int i; | |
1568 | struct thread_points *t; | |
1569 | ||
1570 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) | |
1571 | if (t->tid == tid) | |
1572 | return t; | |
1573 | ||
1574 | t = NULL; | |
1575 | ||
1576 | /* Do we need to allocate a new point_item | |
1577 | if the wanted one does not exist? */ | |
1578 | if (alloc_new) | |
1579 | { | |
8d749320 SM |
1580 | t = XNEW (struct thread_points); |
1581 | t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number); | |
6ffbb7ab TJB |
1582 | t->tid = tid; |
1583 | VEC_safe_push (thread_points_p, ppc_threads, t); | |
1584 | } | |
1585 | ||
1586 | return t; | |
1587 | } | |
1588 | ||
1589 | /* This function is a generic wrapper that is responsible for inserting a | |
1590 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1591 | kernel) and registering it internally in GDB. */ | |
1592 | static void | |
926bf92d | 1593 | hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1594 | { |
1595 | int i; | |
1596 | long slot; | |
a90ecff8 | 1597 | gdb::unique_xmalloc_ptr<ppc_hw_breakpoint> p (XDUP (ppc_hw_breakpoint, b)); |
6ffbb7ab | 1598 | struct hw_break_tuple *hw_breaks; |
6ffbb7ab TJB |
1599 | struct thread_points *t; |
1600 | struct hw_break_tuple *tuple; | |
1601 | ||
6ffbb7ab | 1602 | errno = 0; |
a90ecff8 | 1603 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ()); |
6ffbb7ab TJB |
1604 | if (slot < 0) |
1605 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); | |
1606 | ||
1607 | /* Everything went fine, so we have to register this *point. */ | |
926bf92d | 1608 | t = hwdebug_find_thread_points_by_tid (tid, 1); |
6ffbb7ab TJB |
1609 | gdb_assert (t != NULL); |
1610 | hw_breaks = t->hw_breaks; | |
1611 | ||
1612 | /* Find a free element in the hw_breaks vector. */ | |
1613 | for (i = 0; i < max_slots_number; i++) | |
1614 | if (hw_breaks[i].hw_break == NULL) | |
1615 | { | |
1616 | hw_breaks[i].slot = slot; | |
a90ecff8 | 1617 | hw_breaks[i].hw_break = p.release (); |
6ffbb7ab TJB |
1618 | break; |
1619 | } | |
1620 | ||
1621 | gdb_assert (i != max_slots_number); | |
6ffbb7ab TJB |
1622 | } |
1623 | ||
1624 | /* This function is a generic wrapper that is responsible for removing a | |
1625 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1626 | kernel), and unregistering it internally at GDB. */ | |
1627 | static void | |
926bf92d | 1628 | hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1629 | { |
1630 | int i; | |
1631 | struct hw_break_tuple *hw_breaks; | |
1632 | struct thread_points *t; | |
1633 | ||
926bf92d | 1634 | t = hwdebug_find_thread_points_by_tid (tid, 0); |
6ffbb7ab TJB |
1635 | gdb_assert (t != NULL); |
1636 | hw_breaks = t->hw_breaks; | |
1637 | ||
1638 | for (i = 0; i < max_slots_number; i++) | |
926bf92d | 1639 | if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b)) |
6ffbb7ab TJB |
1640 | break; |
1641 | ||
1642 | gdb_assert (i != max_slots_number); | |
1643 | ||
1644 | /* We have to ignore ENOENT errors because the kernel implements hardware | |
1645 | breakpoints/watchpoints as "one-shot", that is, they are automatically | |
1646 | deleted when hit. */ | |
1647 | errno = 0; | |
1648 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) | |
1649 | if (errno != ENOENT) | |
0df8b418 MS |
1650 | perror_with_name (_("Unexpected error deleting " |
1651 | "breakpoint or watchpoint")); | |
6ffbb7ab TJB |
1652 | |
1653 | xfree (hw_breaks[i].hw_break); | |
1654 | hw_breaks[i].hw_break = NULL; | |
1655 | } | |
9f0bdab8 | 1656 | |
f1310107 TJB |
1657 | /* Return the number of registers needed for a ranged breakpoint. */ |
1658 | ||
f6ac5f3d PA |
1659 | int |
1660 | ppc_linux_nat_target::ranged_break_num_registers () | |
f1310107 | 1661 | { |
926bf92d UW |
1662 | return ((have_ptrace_hwdebug_interface () |
1663 | && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? | |
f1310107 TJB |
1664 | 2 : -1); |
1665 | } | |
1666 | ||
1667 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for | |
1668 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ | |
1669 | ||
f6ac5f3d PA |
1670 | int |
1671 | ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1672 | struct bp_target_info *bp_tgt) | |
e0d24f8d | 1673 | { |
9f0bdab8 | 1674 | struct lwp_info *lp; |
6ffbb7ab TJB |
1675 | struct ppc_hw_breakpoint p; |
1676 | ||
926bf92d | 1677 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1678 | return -1; |
1679 | ||
ad422571 TJB |
1680 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1681 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 | 1682 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
0d5ed153 | 1683 | p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address); |
6ffbb7ab TJB |
1684 | p.condition_value = 0; |
1685 | ||
f1310107 TJB |
1686 | if (bp_tgt->length) |
1687 | { | |
1688 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1689 | ||
1690 | /* The breakpoint will trigger if the address of the instruction is | |
1691 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
1692 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1693 | } | |
1694 | else | |
1695 | { | |
1696 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1697 | p.addr2 = 0; | |
1698 | } | |
1699 | ||
4c38200f | 1700 | ALL_LWPS (lp) |
dfd4cc63 | 1701 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
1702 | |
1703 | return 0; | |
1704 | } | |
1705 | ||
f6ac5f3d PA |
1706 | int |
1707 | ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1708 | struct bp_target_info *bp_tgt) | |
6ffbb7ab | 1709 | { |
6ffbb7ab TJB |
1710 | struct lwp_info *lp; |
1711 | struct ppc_hw_breakpoint p; | |
b7622095 | 1712 | |
926bf92d | 1713 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1714 | return -1; |
1715 | ||
ad422571 TJB |
1716 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1717 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1718 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1719 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1720 | p.condition_value = 0; |
1721 | ||
f1310107 TJB |
1722 | if (bp_tgt->length) |
1723 | { | |
1724 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1725 | ||
1726 | /* The breakpoint will trigger if the address of the instruction is within | |
1727 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
1728 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1729 | } | |
1730 | else | |
1731 | { | |
1732 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1733 | p.addr2 = 0; | |
1734 | } | |
1735 | ||
4c38200f | 1736 | ALL_LWPS (lp) |
dfd4cc63 | 1737 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
1738 | |
1739 | return 0; | |
1740 | } | |
1741 | ||
1742 | static int | |
e76460db | 1743 | get_trigger_type (enum target_hw_bp_type type) |
6ffbb7ab TJB |
1744 | { |
1745 | int t; | |
1746 | ||
e76460db | 1747 | if (type == hw_read) |
6ffbb7ab | 1748 | t = PPC_BREAKPOINT_TRIGGER_READ; |
e76460db | 1749 | else if (type == hw_write) |
6ffbb7ab | 1750 | t = PPC_BREAKPOINT_TRIGGER_WRITE; |
b7622095 | 1751 | else |
6ffbb7ab TJB |
1752 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
1753 | ||
1754 | return t; | |
1755 | } | |
1756 | ||
9c06b0b4 TJB |
1757 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
1758 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1759 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1760 | an error on failure. */ | |
1761 | ||
f6ac5f3d PA |
1762 | int |
1763 | ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
1764 | target_hw_bp_type rw) | |
9c06b0b4 | 1765 | { |
9c06b0b4 TJB |
1766 | struct lwp_info *lp; |
1767 | struct ppc_hw_breakpoint p; | |
1768 | ||
926bf92d | 1769 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1770 | |
1771 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1772 | p.trigger_type = get_trigger_type (rw); | |
1773 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1774 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1775 | p.addr = addr; | |
1776 | p.addr2 = mask; | |
1777 | p.condition_value = 0; | |
1778 | ||
4c38200f | 1779 | ALL_LWPS (lp) |
dfd4cc63 | 1780 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
9c06b0b4 TJB |
1781 | |
1782 | return 0; | |
1783 | } | |
1784 | ||
1785 | /* Remove a masked watchpoint at ADDR with the mask MASK. | |
1786 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1787 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1788 | an error on failure. */ | |
1789 | ||
f6ac5f3d PA |
1790 | int |
1791 | ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
1792 | target_hw_bp_type rw) | |
9c06b0b4 | 1793 | { |
9c06b0b4 TJB |
1794 | struct lwp_info *lp; |
1795 | struct ppc_hw_breakpoint p; | |
1796 | ||
926bf92d | 1797 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1798 | |
1799 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1800 | p.trigger_type = get_trigger_type (rw); | |
1801 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1802 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1803 | p.addr = addr; | |
1804 | p.addr2 = mask; | |
1805 | p.condition_value = 0; | |
1806 | ||
4c38200f | 1807 | ALL_LWPS (lp) |
dfd4cc63 | 1808 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
9c06b0b4 TJB |
1809 | |
1810 | return 0; | |
1811 | } | |
1812 | ||
0cf6dd15 TJB |
1813 | /* Check whether we have at least one free DVC register. */ |
1814 | static int | |
1815 | can_use_watchpoint_cond_accel (void) | |
1816 | { | |
1817 | struct thread_points *p; | |
dfd4cc63 | 1818 | int tid = ptid_get_lwp (inferior_ptid); |
926bf92d | 1819 | int cnt = hwdebug_info.num_condition_regs, i; |
0cf6dd15 TJB |
1820 | CORE_ADDR tmp_value; |
1821 | ||
926bf92d | 1822 | if (!have_ptrace_hwdebug_interface () || cnt == 0) |
0cf6dd15 TJB |
1823 | return 0; |
1824 | ||
926bf92d | 1825 | p = hwdebug_find_thread_points_by_tid (tid, 0); |
0cf6dd15 TJB |
1826 | |
1827 | if (p) | |
1828 | { | |
1829 | for (i = 0; i < max_slots_number; i++) | |
1830 | if (p->hw_breaks[i].hw_break != NULL | |
1831 | && (p->hw_breaks[i].hw_break->condition_mode | |
1832 | != PPC_BREAKPOINT_CONDITION_NONE)) | |
1833 | cnt--; | |
1834 | ||
1835 | /* There are no available slots now. */ | |
1836 | if (cnt <= 0) | |
1837 | return 0; | |
1838 | } | |
1839 | ||
1840 | return 1; | |
1841 | } | |
1842 | ||
1843 | /* Calculate the enable bits and the contents of the Data Value Compare | |
1844 | debug register present in BookE processors. | |
1845 | ||
1846 | ADDR is the address to be watched, LEN is the length of watched data | |
1847 | and DATA_VALUE is the value which will trigger the watchpoint. | |
1848 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
1849 | CONDITION_VALUE will hold the value which should be put in the | |
1850 | DVC register. */ | |
1851 | static void | |
1852 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, | |
1853 | uint32_t *condition_mode, uint64_t *condition_value) | |
1854 | { | |
1855 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, | |
1856 | rightmost_enabled_byte; | |
1857 | CORE_ADDR addr_end_data, addr_end_dvc; | |
1858 | ||
1859 | /* The DVC register compares bytes within fixed-length windows which | |
1860 | are word-aligned, with length equal to that of the DVC register. | |
1861 | We need to calculate where our watch region is relative to that | |
1862 | window and enable comparison of the bytes which fall within it. */ | |
1863 | ||
926bf92d | 1864 | align_offset = addr % hwdebug_info.sizeof_condition; |
0cf6dd15 TJB |
1865 | addr_end_data = addr + len; |
1866 | addr_end_dvc = (addr - align_offset | |
926bf92d | 1867 | + hwdebug_info.sizeof_condition); |
0cf6dd15 TJB |
1868 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? |
1869 | addr_end_data - addr_end_dvc : 0; | |
1870 | num_byte_enable = len - num_bytes_off_dvc; | |
1871 | /* Here, bytes are numbered from right to left. */ | |
1872 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
1873 | addr_end_dvc - addr_end_data : 0; | |
1874 | ||
1875 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
1876 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
1877 | *condition_mode |
1878 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
1879 | |
1880 | /* Now we need to match the position within the DVC of the comparison | |
1881 | value with where the watch region is relative to the window | |
1882 | (i.e., the ALIGN_OFFSET). */ | |
1883 | ||
1884 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
1885 | << rightmost_enabled_byte * 8); | |
1886 | } | |
1887 | ||
1888 | /* Return the number of memory locations that need to be accessed to | |
1889 | evaluate the expression which generated the given value chain. | |
1890 | Returns -1 if there's any register access involved, or if there are | |
1891 | other kinds of values which are not acceptable in a condition | |
1892 | expression (e.g., lval_computed or lval_internalvar). */ | |
1893 | static int | |
a6535de1 | 1894 | num_memory_accesses (const std::vector<value_ref_ptr> &chain) |
0cf6dd15 TJB |
1895 | { |
1896 | int found_memory_cnt = 0; | |
0cf6dd15 TJB |
1897 | |
1898 | /* The idea here is that evaluating an expression generates a series | |
1899 | of values, one holding the value of every subexpression. (The | |
1900 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
1901 | a*b+c.) GDB's values hold almost enough information to establish | |
1902 | the criteria given above --- they identify memory lvalues, | |
1903 | register lvalues, computed values, etcetera. So we can evaluate | |
1904 | the expression, and then scan the chain of values that leaves | |
1905 | behind to determine the memory locations involved in the evaluation | |
1906 | of an expression. | |
1907 | ||
1908 | However, I don't think that the values returned by inferior | |
1909 | function calls are special in any way. So this function may not | |
1910 | notice that an expression contains an inferior function call. | |
1911 | FIXME. */ | |
1912 | ||
a6535de1 | 1913 | for (const value_ref_ptr &iter : chain) |
0cf6dd15 | 1914 | { |
a6535de1 TT |
1915 | struct value *v = iter.get (); |
1916 | ||
0cf6dd15 TJB |
1917 | /* Constants and values from the history are fine. */ |
1918 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) | |
1919 | continue; | |
1920 | else if (VALUE_LVAL (v) == lval_memory) | |
1921 | { | |
1922 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
1923 | we either just used its address (e.g., `a' in `a.b') or | |
1924 | we never needed it at all (e.g., `a' in `a,b'). */ | |
1925 | if (!value_lazy (v)) | |
1926 | found_memory_cnt++; | |
1927 | } | |
0df8b418 | 1928 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
1929 | else |
1930 | return -1; | |
1931 | } | |
1932 | ||
1933 | return found_memory_cnt; | |
1934 | } | |
1935 | ||
1936 | /* Verifies whether the expression COND can be implemented using the | |
1937 | DVC (Data Value Compare) register in BookE processors. The expression | |
1938 | must test the watch value for equality with a constant expression. | |
1939 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
1940 | which the watch value should be compared and LEN will contain the size |
1941 | of the constant. */ | |
0cf6dd15 TJB |
1942 | static int |
1943 | check_condition (CORE_ADDR watch_addr, struct expression *cond, | |
e7db58ea | 1944 | CORE_ADDR *data_value, int *len) |
0cf6dd15 TJB |
1945 | { |
1946 | int pc = 1, num_accesses_left, num_accesses_right; | |
a6535de1 TT |
1947 | struct value *left_val, *right_val; |
1948 | std::vector<value_ref_ptr> left_chain, right_chain; | |
0cf6dd15 TJB |
1949 | |
1950 | if (cond->elts[0].opcode != BINOP_EQUAL) | |
1951 | return 0; | |
1952 | ||
3a1115a0 | 1953 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0); |
0cf6dd15 TJB |
1954 | num_accesses_left = num_memory_accesses (left_chain); |
1955 | ||
1956 | if (left_val == NULL || num_accesses_left < 0) | |
a6535de1 | 1957 | return 0; |
0cf6dd15 | 1958 | |
3a1115a0 | 1959 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0); |
0cf6dd15 TJB |
1960 | num_accesses_right = num_memory_accesses (right_chain); |
1961 | ||
1962 | if (right_val == NULL || num_accesses_right < 0) | |
a6535de1 | 1963 | return 0; |
0cf6dd15 TJB |
1964 | |
1965 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
1966 | && VALUE_LVAL (left_val) == lval_memory | |
1967 | && value_address (left_val) == watch_addr) | |
e7db58ea TJB |
1968 | { |
1969 | *data_value = value_as_long (right_val); | |
1970 | ||
1971 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
1972 | the same type as the memory region referenced by LEFT_VAL. */ | |
1973 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); | |
1974 | } | |
0cf6dd15 TJB |
1975 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
1976 | && VALUE_LVAL (right_val) == lval_memory | |
1977 | && value_address (right_val) == watch_addr) | |
e7db58ea TJB |
1978 | { |
1979 | *data_value = value_as_long (left_val); | |
1980 | ||
1981 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
1982 | the same type as the memory region referenced by RIGHT_VAL. */ | |
1983 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); | |
1984 | } | |
0cf6dd15 | 1985 | else |
a6535de1 | 1986 | return 0; |
0cf6dd15 TJB |
1987 | |
1988 | return 1; | |
1989 | } | |
1990 | ||
1991 | /* Return non-zero if the target is capable of using hardware to evaluate | |
1992 | the condition expression, thus only triggering the watchpoint when it is | |
1993 | true. */ | |
57810aa7 | 1994 | bool |
f6ac5f3d PA |
1995 | ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, int len, |
1996 | int rw, | |
1997 | struct expression *cond) | |
0cf6dd15 TJB |
1998 | { |
1999 | CORE_ADDR data_value; | |
2000 | ||
926bf92d UW |
2001 | return (have_ptrace_hwdebug_interface () |
2002 | && hwdebug_info.num_condition_regs > 0 | |
e7db58ea | 2003 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
2004 | } |
2005 | ||
e09342b5 TJB |
2006 | /* Set up P with the parameters necessary to request a watchpoint covering |
2007 | LEN bytes starting at ADDR and if possible with condition expression COND | |
2008 | evaluated by hardware. INSERT tells if we are creating a request for | |
2009 | inserting or removing the watchpoint. */ | |
2010 | ||
2011 | static void | |
2012 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, | |
e76460db PA |
2013 | int len, enum target_hw_bp_type type, |
2014 | struct expression *cond, int insert) | |
e09342b5 | 2015 | { |
f16c4e8b | 2016 | if (len == 1 |
926bf92d | 2017 | || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) |
e09342b5 TJB |
2018 | { |
2019 | int use_condition; | |
2020 | CORE_ADDR data_value; | |
2021 | ||
2022 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
926bf92d | 2023 | : hwdebug_info.num_condition_regs > 0); |
e7db58ea TJB |
2024 | if (cond && use_condition && check_condition (addr, cond, |
2025 | &data_value, &len)) | |
e09342b5 TJB |
2026 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
2027 | &p->condition_value); | |
2028 | else | |
2029 | { | |
2030 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2031 | p->condition_value = 0; | |
2032 | } | |
2033 | ||
2034 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2035 | p->addr2 = 0; | |
2036 | } | |
2037 | else | |
2038 | { | |
2039 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2040 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2041 | p->condition_value = 0; | |
2042 | ||
2043 | /* The watchpoint will trigger if the address of the memory access is | |
2044 | within the defined range, as follows: p->addr <= address < p->addr2. | |
2045 | ||
2046 | Note that the above sentence just documents how ptrace interprets | |
2047 | its arguments; the watchpoint is set to watch the range defined by | |
2048 | the user _inclusively_, as specified by the user interface. */ | |
2049 | p->addr2 = (uint64_t) addr + len; | |
2050 | } | |
2051 | ||
2052 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
e76460db | 2053 | p->trigger_type = get_trigger_type (type); |
e09342b5 TJB |
2054 | p->addr = (uint64_t) addr; |
2055 | } | |
2056 | ||
f6ac5f3d PA |
2057 | int |
2058 | ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
2059 | enum target_hw_bp_type type, | |
2060 | struct expression *cond) | |
6ffbb7ab TJB |
2061 | { |
2062 | struct lwp_info *lp; | |
6ffbb7ab TJB |
2063 | int ret = -1; |
2064 | ||
926bf92d | 2065 | if (have_ptrace_hwdebug_interface ()) |
e0d24f8d | 2066 | { |
6ffbb7ab TJB |
2067 | struct ppc_hw_breakpoint p; |
2068 | ||
e76460db | 2069 | create_watchpoint_request (&p, addr, len, type, cond, 1); |
6ffbb7ab | 2070 | |
4c38200f | 2071 | ALL_LWPS (lp) |
dfd4cc63 | 2072 | hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
2073 | |
2074 | ret = 0; | |
e0d24f8d | 2075 | } |
6ffbb7ab TJB |
2076 | else |
2077 | { | |
2078 | long dabr_value; | |
2079 | long read_mode, write_mode; | |
e0d24f8d | 2080 | |
6ffbb7ab TJB |
2081 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2082 | { | |
2083 | /* PowerPC 440 requires only the read/write flags to be passed | |
2084 | to the kernel. */ | |
ad422571 | 2085 | read_mode = 1; |
6ffbb7ab TJB |
2086 | write_mode = 2; |
2087 | } | |
2088 | else | |
2089 | { | |
2090 | /* PowerPC 970 and other DABR-based processors are required to pass | |
2091 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 2092 | read_mode = 5; |
6ffbb7ab TJB |
2093 | write_mode = 6; |
2094 | } | |
1c86e440 | 2095 | |
6ffbb7ab | 2096 | dabr_value = addr & ~(read_mode | write_mode); |
e76460db | 2097 | switch (type) |
6ffbb7ab TJB |
2098 | { |
2099 | case hw_read: | |
2100 | /* Set read and translate bits. */ | |
2101 | dabr_value |= read_mode; | |
2102 | break; | |
2103 | case hw_write: | |
2104 | /* Set write and translate bits. */ | |
2105 | dabr_value |= write_mode; | |
2106 | break; | |
2107 | case hw_access: | |
2108 | /* Set read, write and translate bits. */ | |
2109 | dabr_value |= read_mode | write_mode; | |
2110 | break; | |
2111 | } | |
1c86e440 | 2112 | |
6ffbb7ab TJB |
2113 | saved_dabr_value = dabr_value; |
2114 | ||
4c38200f | 2115 | ALL_LWPS (lp) |
dfd4cc63 | 2116 | if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, |
0cf6dd15 | 2117 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2118 | return -1; |
2119 | ||
2120 | ret = 0; | |
2121 | } | |
2122 | ||
2123 | return ret; | |
e0d24f8d WZ |
2124 | } |
2125 | ||
f6ac5f3d PA |
2126 | int |
2127 | ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
2128 | enum target_hw_bp_type type, | |
2129 | struct expression *cond) | |
e0d24f8d | 2130 | { |
9f0bdab8 | 2131 | struct lwp_info *lp; |
6ffbb7ab | 2132 | int ret = -1; |
9f0bdab8 | 2133 | |
926bf92d | 2134 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2135 | { |
2136 | struct ppc_hw_breakpoint p; | |
2137 | ||
e76460db | 2138 | create_watchpoint_request (&p, addr, len, type, cond, 0); |
6ffbb7ab | 2139 | |
4c38200f | 2140 | ALL_LWPS (lp) |
dfd4cc63 | 2141 | hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); |
6ffbb7ab TJB |
2142 | |
2143 | ret = 0; | |
2144 | } | |
2145 | else | |
2146 | { | |
2147 | saved_dabr_value = 0; | |
4c38200f | 2148 | ALL_LWPS (lp) |
dfd4cc63 | 2149 | if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, |
0cf6dd15 | 2150 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2151 | return -1; |
2152 | ||
2153 | ret = 0; | |
2154 | } | |
2155 | ||
2156 | return ret; | |
e0d24f8d WZ |
2157 | } |
2158 | ||
135340af PA |
2159 | void |
2160 | ppc_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e0d24f8d | 2161 | { |
dfd4cc63 | 2162 | int tid = ptid_get_lwp (lp->ptid); |
6ffbb7ab | 2163 | |
926bf92d | 2164 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2165 | { |
2166 | int i; | |
2167 | struct thread_points *p; | |
2168 | struct hw_break_tuple *hw_breaks; | |
2169 | ||
2170 | if (VEC_empty (thread_points_p, ppc_threads)) | |
2171 | return; | |
2172 | ||
0df8b418 | 2173 | /* Get a list of breakpoints from any thread. */ |
6ffbb7ab TJB |
2174 | p = VEC_last (thread_points_p, ppc_threads); |
2175 | hw_breaks = p->hw_breaks; | |
2176 | ||
0df8b418 | 2177 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
6ffbb7ab TJB |
2178 | for (i = 0; i < max_slots_number; i++) |
2179 | if (hw_breaks[i].hw_break) | |
aacbb8a5 LM |
2180 | { |
2181 | /* Older kernels did not make new threads inherit their parent | |
2182 | thread's debug state, so we always clear the slot and replicate | |
2183 | the debug state ourselves, ensuring compatibility with all | |
2184 | kernels. */ | |
2185 | ||
2186 | /* The ppc debug resource accounting is done through "slots". | |
2187 | Ask the kernel the deallocate this specific *point's slot. */ | |
2188 | ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot); | |
2189 | ||
926bf92d | 2190 | hwdebug_insert_point (hw_breaks[i].hw_break, tid); |
aacbb8a5 | 2191 | } |
6ffbb7ab TJB |
2192 | } |
2193 | else | |
2194 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); | |
2195 | } | |
2196 | ||
2197 | static void | |
2198 | ppc_linux_thread_exit (struct thread_info *tp, int silent) | |
2199 | { | |
2200 | int i; | |
dfd4cc63 | 2201 | int tid = ptid_get_lwp (tp->ptid); |
6ffbb7ab TJB |
2202 | struct hw_break_tuple *hw_breaks; |
2203 | struct thread_points *t = NULL, *p; | |
2204 | ||
926bf92d | 2205 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2206 | return; |
2207 | ||
2208 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) | |
2209 | if (p->tid == tid) | |
2210 | { | |
2211 | t = p; | |
2212 | break; | |
2213 | } | |
2214 | ||
2215 | if (t == NULL) | |
2216 | return; | |
2217 | ||
2218 | VEC_unordered_remove (thread_points_p, ppc_threads, i); | |
2219 | ||
2220 | hw_breaks = t->hw_breaks; | |
2221 | ||
2222 | for (i = 0; i < max_slots_number; i++) | |
2223 | if (hw_breaks[i].hw_break) | |
2224 | xfree (hw_breaks[i].hw_break); | |
2225 | ||
2226 | xfree (t->hw_breaks); | |
2227 | xfree (t); | |
e0d24f8d WZ |
2228 | } |
2229 | ||
57810aa7 | 2230 | bool |
f6ac5f3d | 2231 | ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e0d24f8d | 2232 | { |
f865ee35 | 2233 | siginfo_t siginfo; |
e0d24f8d | 2234 | |
f865ee35 | 2235 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
57810aa7 | 2236 | return false; |
e0d24f8d | 2237 | |
f865ee35 JK |
2238 | if (siginfo.si_signo != SIGTRAP |
2239 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 2240 | return false; |
e0d24f8d | 2241 | |
926bf92d | 2242 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2243 | { |
2244 | int i; | |
2245 | struct thread_points *t; | |
2246 | struct hw_break_tuple *hw_breaks; | |
2247 | /* The index (or slot) of the *point is passed in the si_errno field. */ | |
f865ee35 | 2248 | int slot = siginfo.si_errno; |
6ffbb7ab | 2249 | |
dfd4cc63 | 2250 | t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0); |
6ffbb7ab TJB |
2251 | |
2252 | /* Find out if this *point is a hardware breakpoint. | |
2253 | If so, we should return 0. */ | |
2254 | if (t) | |
2255 | { | |
2256 | hw_breaks = t->hw_breaks; | |
2257 | for (i = 0; i < max_slots_number; i++) | |
2258 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot | |
2259 | && hw_breaks[i].hw_break->trigger_type | |
2260 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) | |
57810aa7 | 2261 | return false; |
6ffbb7ab TJB |
2262 | } |
2263 | } | |
2264 | ||
f865ee35 | 2265 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 2266 | return true; |
e0d24f8d WZ |
2267 | } |
2268 | ||
57810aa7 | 2269 | bool |
f6ac5f3d | 2270 | ppc_linux_nat_target::stopped_by_watchpoint () |
9f0bdab8 DJ |
2271 | { |
2272 | CORE_ADDR addr; | |
f6ac5f3d | 2273 | return stopped_data_address (&addr); |
9f0bdab8 DJ |
2274 | } |
2275 | ||
57810aa7 | 2276 | bool |
f6ac5f3d PA |
2277 | ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
2278 | CORE_ADDR start, | |
2279 | int length) | |
5009afc5 | 2280 | { |
b7622095 LM |
2281 | int mask; |
2282 | ||
926bf92d | 2283 | if (have_ptrace_hwdebug_interface () |
6ffbb7ab TJB |
2284 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2285 | return start <= addr && start + length >= addr; | |
2286 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
b7622095 LM |
2287 | mask = 3; |
2288 | else | |
2289 | mask = 7; | |
2290 | ||
2291 | addr &= ~mask; | |
2292 | ||
0df8b418 | 2293 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 2294 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
2295 | } |
2296 | ||
9c06b0b4 TJB |
2297 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
2298 | ||
f6ac5f3d PA |
2299 | int |
2300 | ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, CORE_ADDR mask) | |
9c06b0b4 | 2301 | { |
926bf92d UW |
2302 | if (!have_ptrace_hwdebug_interface () |
2303 | || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
9c06b0b4 TJB |
2304 | return -1; |
2305 | else if ((mask & 0xC0000000) != 0xC0000000) | |
2306 | { | |
2307 | warning (_("The given mask covers kernel address space " | |
2308 | "and cannot be used.\n")); | |
2309 | ||
2310 | return -2; | |
2311 | } | |
2312 | else | |
2313 | return 2; | |
2314 | } | |
2315 | ||
f6ac5f3d PA |
2316 | void |
2317 | ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
45229ea4 | 2318 | { |
bcc0c096 | 2319 | pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache)); |
05f13b9c | 2320 | |
45229ea4 | 2321 | if (regno >= 0) |
56be3814 | 2322 | store_register (regcache, tid, regno); |
45229ea4 | 2323 | else |
56be3814 | 2324 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
2325 | } |
2326 | ||
f2db237a AM |
2327 | /* Functions for transferring registers between a gregset_t or fpregset_t |
2328 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
0df8b418 | 2329 | by the ptrace interface, not the current program's ABI. Eg. if a |
f2db237a AM |
2330 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
2331 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
2332 | ||
50c9bd31 | 2333 | void |
7f7fe91e | 2334 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 2335 | { |
f2db237a | 2336 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2337 | |
f2db237a | 2338 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
2339 | } |
2340 | ||
fdb28ac4 | 2341 | void |
7f7fe91e UW |
2342 | fill_gregset (const struct regcache *regcache, |
2343 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 2344 | { |
f2db237a | 2345 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2346 | |
f2db237a AM |
2347 | if (regno == -1) |
2348 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
2349 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
2350 | } |
2351 | ||
50c9bd31 | 2352 | void |
7f7fe91e | 2353 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 2354 | { |
f2db237a AM |
2355 | const struct regset *regset = ppc_linux_fpregset (); |
2356 | ||
2357 | ppc_supply_fpregset (regset, regcache, -1, | |
2358 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 2359 | } |
fdb28ac4 | 2360 | |
fdb28ac4 | 2361 | void |
7f7fe91e UW |
2362 | fill_fpregset (const struct regcache *regcache, |
2363 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 2364 | { |
f2db237a AM |
2365 | const struct regset *regset = ppc_linux_fpregset (); |
2366 | ||
2367 | ppc_collect_fpregset (regset, regcache, regno, | |
2368 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 2369 | } |
10d6c8cd | 2370 | |
2e077f5e PFC |
2371 | int |
2372 | ppc_linux_nat_target::auxv_parse (gdb_byte **readptr, | |
2373 | gdb_byte *endptr, CORE_ADDR *typep, | |
2374 | CORE_ADDR *valp) | |
409c383c | 2375 | { |
dfd4cc63 | 2376 | int tid = ptid_get_lwp (inferior_ptid); |
409c383c | 2377 | if (tid == 0) |
dfd4cc63 | 2378 | tid = ptid_get_pid (inferior_ptid); |
409c383c | 2379 | |
2e077f5e | 2380 | int sizeof_auxv_field = ppc_linux_target_wordsize (tid); |
409c383c | 2381 | |
f5656ead | 2382 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
409c383c UW |
2383 | gdb_byte *ptr = *readptr; |
2384 | ||
2385 | if (endptr == ptr) | |
2386 | return 0; | |
2387 | ||
2388 | if (endptr - ptr < sizeof_auxv_field * 2) | |
2389 | return -1; | |
2390 | ||
e17a4113 | 2391 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c | 2392 | ptr += sizeof_auxv_field; |
e17a4113 | 2393 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c UW |
2394 | ptr += sizeof_auxv_field; |
2395 | ||
2396 | *readptr = ptr; | |
2397 | return 1; | |
2398 | } | |
2399 | ||
f6ac5f3d PA |
2400 | const struct target_desc * |
2401 | ppc_linux_nat_target::read_description () | |
310a98e1 | 2402 | { |
dfd4cc63 | 2403 | int tid = ptid_get_lwp (inferior_ptid); |
7284e1be | 2404 | if (tid == 0) |
dfd4cc63 | 2405 | tid = ptid_get_pid (inferior_ptid); |
7284e1be | 2406 | |
310a98e1 DJ |
2407 | if (have_ptrace_getsetevrregs) |
2408 | { | |
2409 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
2410 | |
2411 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
2412 | return tdesc_powerpc_e500l; |
2413 | ||
2414 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
2415 | Anything else needs to be reported. */ | |
2416 | else if (errno != EIO) | |
2417 | perror_with_name (_("Unable to fetch SPE registers")); | |
2418 | } | |
2419 | ||
bd64614e PFC |
2420 | struct ppc_linux_features features = ppc_linux_no_features; |
2421 | ||
2e077f5e | 2422 | features.wordsize = ppc_linux_target_wordsize (tid); |
bd64614e PFC |
2423 | |
2424 | unsigned long hwcap = ppc_linux_get_hwcap (); | |
2425 | ||
0154d990 | 2426 | if (have_ptrace_getsetvsxregs |
bd64614e | 2427 | && (hwcap & PPC_FEATURE_HAS_VSX)) |
604c2f83 LM |
2428 | { |
2429 | gdb_vsxregset_t vsxregset; | |
2430 | ||
2431 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
bd64614e | 2432 | features.vsx = true; |
604c2f83 LM |
2433 | |
2434 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
2435 | Anything else needs to be reported. */ | |
2436 | else if (errno != EIO) | |
2437 | perror_with_name (_("Unable to fetch VSX registers")); | |
2438 | } | |
2439 | ||
0154d990 | 2440 | if (have_ptrace_getvrregs |
bd64614e | 2441 | && (hwcap & PPC_FEATURE_HAS_ALTIVEC)) |
7284e1be UW |
2442 | { |
2443 | gdb_vrregset_t vrregset; | |
2444 | ||
2445 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
bd64614e | 2446 | features.altivec = true; |
7284e1be UW |
2447 | |
2448 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
2449 | Anything else needs to be reported. */ | |
2450 | else if (errno != EIO) | |
2451 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
2452 | } |
2453 | ||
bd64614e PFC |
2454 | if (hwcap & PPC_FEATURE_CELL) |
2455 | features.cell = true; | |
7284e1be | 2456 | |
bd64614e | 2457 | features.isa205 = ppc_linux_has_isa205 (hwcap); |
604c2f83 | 2458 | |
bd64614e | 2459 | return ppc_linux_match_description (features); |
310a98e1 DJ |
2460 | } |
2461 | ||
10d6c8cd DJ |
2462 | void |
2463 | _initialize_ppc_linux_nat (void) | |
2464 | { | |
f6ac5f3d | 2465 | linux_target = &the_ppc_linux_nat_target; |
310a98e1 | 2466 | |
76727919 | 2467 | gdb::observers::thread_exit.attach (ppc_linux_thread_exit); |
6ffbb7ab | 2468 | |
10d6c8cd | 2469 | /* Register the target. */ |
d9f719f1 | 2470 | add_inf_child_target (linux_target); |
10d6c8cd | 2471 | } |