Commit | Line | Data |
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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a AC |
2 | |
3 | Copyright 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, | |
4 | 2003 Free Software Foundation, Inc. | |
c877c8e6 KB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
05f13b9c EZ |
20 | Foundation, Inc., 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
c877c8e6 KB |
22 | |
23 | #include "defs.h" | |
e162d11b | 24 | #include "gdb_string.h" |
c877c8e6 KB |
25 | #include "frame.h" |
26 | #include "inferior.h" | |
27 | #include "gdbcore.h" | |
4e052eda | 28 | #include "regcache.h" |
383f0f5b | 29 | #include "gdb_assert.h" |
c877c8e6 KB |
30 | |
31 | #include <sys/types.h> | |
32 | #include <sys/param.h> | |
33 | #include <signal.h> | |
34 | #include <sys/user.h> | |
35 | #include <sys/ioctl.h> | |
2555fe1a | 36 | #include "gdb_wait.h" |
c877c8e6 KB |
37 | #include <fcntl.h> |
38 | #include <sys/procfs.h> | |
45229ea4 | 39 | #include <sys/ptrace.h> |
c877c8e6 | 40 | |
c60c0f5f MS |
41 | /* Prototypes for supply_gregset etc. */ |
42 | #include "gregset.h" | |
16333c4f | 43 | #include "ppc-tdep.h" |
c60c0f5f | 44 | |
45229ea4 EZ |
45 | #ifndef PT_READ_U |
46 | #define PT_READ_U PTRACE_PEEKUSR | |
47 | #endif | |
48 | #ifndef PT_WRITE_U | |
49 | #define PT_WRITE_U PTRACE_POKEUSR | |
50 | #endif | |
51 | ||
52 | /* Default the type of the ptrace transfer to int. */ | |
53 | #ifndef PTRACE_XFER_TYPE | |
54 | #define PTRACE_XFER_TYPE int | |
55 | #endif | |
56 | ||
9abe5450 EZ |
57 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
58 | configure time check. Some older glibc's (for instance 2.2.1) | |
59 | don't have a specific powerpc version of ptrace.h, and fall back on | |
60 | a generic one. In such cases, sys/ptrace.h defines | |
61 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
62 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
63 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
64 | much useless. */ | |
65 | ||
66 | /* These definitions should really come from the glibc header files, | |
67 | but Glibc doesn't know about the vrregs yet. */ | |
68 | #ifndef PTRACE_GETVRREGS | |
69 | #define PTRACE_GETVRREGS 18 | |
70 | #define PTRACE_SETVRREGS 19 | |
71 | #endif | |
72 | ||
73 | /* This oddity is because the Linux kernel defines elf_vrregset_t as | |
74 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
75 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
76 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
77 | flat array of chars, so that it is easier to manipulate for gdb. | |
78 | ||
79 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
80 | which is only 4 bytes long, but is fetched as a 16 bytes | |
81 | quantity. Up to here we have the elf_vrregset_t structure. | |
82 | Appended to this there is space for the VRSAVE register: 4 bytes. | |
83 | Even though this vrsave register is not included in the regset | |
84 | typedef, it is handled by the ptrace requests. | |
85 | ||
86 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
87 | therefore the offset at which the real value of the VSCR register | |
88 | is located will be always 12 bytes. | |
89 | ||
90 | The layout is like this (where x is the actual value of the vscr reg): */ | |
91 | ||
92 | /* *INDENT-OFF* */ | |
93 | /* | |
94 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
95 | <-------> <-------><-------><-> | |
96 | VR0 VR31 VSCR VRSAVE | |
97 | */ | |
98 | /* *INDENT-ON* */ | |
99 | ||
100 | #define SIZEOF_VRREGS 33*16+4 | |
101 | ||
102 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
103 | ||
104 | /* For runtime check of ptrace support for VRREGS. */ | |
105 | int have_ptrace_getvrregs = 1; | |
106 | ||
c877c8e6 | 107 | int |
fba45db2 | 108 | kernel_u_size (void) |
c877c8e6 KB |
109 | { |
110 | return (sizeof (struct user)); | |
111 | } | |
112 | ||
16333c4f EZ |
113 | /* *INDENT-OFF* */ |
114 | /* registers layout, as presented by the ptrace interface: | |
115 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
116 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
117 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
118 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
119 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
120 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
121 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
122 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
123 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ | |
124 | /* *INDENT_ON * */ | |
c877c8e6 | 125 | |
45229ea4 EZ |
126 | static int |
127 | ppc_register_u_addr (int regno) | |
c877c8e6 | 128 | { |
16333c4f | 129 | int u_addr = -1; |
dc5cfeb6 | 130 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
56d0d96a AC |
131 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
132 | interface, and not the wordsize of the program's ABI. */ | |
133 | int wordsize = sizeof (PTRACE_XFER_TYPE); | |
16333c4f EZ |
134 | |
135 | /* General purpose registers occupy 1 slot each in the buffer */ | |
8bf659e8 JB |
136 | if (regno >= tdep->ppc_gp0_regnum |
137 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 138 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 139 | |
49ff75ad JB |
140 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
141 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
142 | slot each in 64-bit interface. */ | |
383f0f5b JB |
143 | if (tdep->ppc_fp0_regnum >= 0 |
144 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
145 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
146 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f EZ |
147 | |
148 | /* UISA special purpose registers: 1 slot each */ | |
149 | if (regno == PC_REGNUM) | |
49ff75ad | 150 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 151 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 152 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 153 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 154 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 155 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 156 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 157 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 158 | u_addr = PT_CTR * wordsize; |
f8c59253 | 159 | #ifdef PT_MQ |
dc5cfeb6 | 160 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 161 | u_addr = PT_MQ * wordsize; |
f8c59253 | 162 | #endif |
dc5cfeb6 | 163 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 164 | u_addr = PT_MSR * wordsize; |
383f0f5b JB |
165 | if (tdep->ppc_fpscr_regnum >= 0 |
166 | && regno == tdep->ppc_fpscr_regnum) | |
49ff75ad | 167 | u_addr = PT_FPSCR * wordsize; |
16333c4f EZ |
168 | |
169 | return u_addr; | |
c877c8e6 KB |
170 | } |
171 | ||
9abe5450 EZ |
172 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
173 | registers set mechanism, as opposed to the interface for all the | |
174 | other registers, that stores/fetches each register individually. */ | |
175 | static void | |
176 | fetch_altivec_register (int tid, int regno) | |
177 | { | |
178 | int ret; | |
179 | int offset = 0; | |
180 | gdb_vrregset_t regs; | |
181 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
12c266ea | 182 | int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
9abe5450 EZ |
183 | |
184 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
185 | if (ret < 0) | |
186 | { | |
187 | if (errno == EIO) | |
188 | { | |
189 | have_ptrace_getvrregs = 0; | |
190 | return; | |
191 | } | |
192 | perror_with_name ("Unable to fetch AltiVec register"); | |
193 | } | |
194 | ||
195 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
196 | long on the hardware. We deal only with the lower 4 bytes of the | |
197 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
198 | there is no need to define an offset for it. */ | |
199 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
12c266ea | 200 | offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); |
9abe5450 EZ |
201 | |
202 | supply_register (regno, | |
203 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
204 | } | |
205 | ||
45229ea4 | 206 | static void |
05f13b9c | 207 | fetch_register (int tid, int regno) |
45229ea4 | 208 | { |
366f009f | 209 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 EZ |
210 | /* This isn't really an address. But ptrace thinks of it as one. */ |
211 | char mess[128]; /* For messages */ | |
52f0bd74 | 212 | int i; |
45229ea4 | 213 | unsigned int offset; /* Offset of registers within the u area. */ |
d9d9c31f | 214 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 EZ |
215 | CORE_ADDR regaddr = ppc_register_u_addr (regno); |
216 | ||
9abe5450 EZ |
217 | if (altivec_register_p (regno)) |
218 | { | |
219 | /* If this is the first time through, or if it is not the first | |
220 | time through, and we have comfirmed that there is kernel | |
221 | support for such a ptrace request, then go and fetch the | |
222 | register. */ | |
223 | if (have_ptrace_getvrregs) | |
224 | { | |
225 | fetch_altivec_register (tid, regno); | |
226 | return; | |
227 | } | |
228 | /* If we have discovered that there is no ptrace support for | |
229 | AltiVec registers, fall through and return zeroes, because | |
230 | regaddr will be -1 in this case. */ | |
231 | } | |
232 | ||
45229ea4 EZ |
233 | if (regaddr == -1) |
234 | { | |
12c266ea | 235 | memset (buf, '\0', DEPRECATED_REGISTER_RAW_SIZE (regno)); /* Supply zeroes */ |
45229ea4 EZ |
236 | supply_register (regno, buf); |
237 | return; | |
238 | } | |
239 | ||
383f0f5b JB |
240 | /* If the current architecture has no floating-point registers, we |
241 | should never reach this point: ppc_register_u_addr should have | |
242 | returned -1, and we should have caught that above. */ | |
243 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
244 | ||
56d0d96a AC |
245 | /* Read the raw register using PTRACE_XFER_TYPE sized chunks. On a |
246 | 32-bit platform, 64-bit floating-point registers will require two | |
247 | transfers. */ | |
12c266ea | 248 | for (i = 0; i < DEPRECATED_REGISTER_RAW_SIZE (regno); i += sizeof (PTRACE_XFER_TYPE)) |
45229ea4 EZ |
249 | { |
250 | errno = 0; | |
251 | *(PTRACE_XFER_TYPE *) & buf[i] = ptrace (PT_READ_U, tid, | |
252 | (PTRACE_ARG3_TYPE) regaddr, 0); | |
253 | regaddr += sizeof (PTRACE_XFER_TYPE); | |
254 | if (errno != 0) | |
255 | { | |
256 | sprintf (mess, "reading register %s (#%d)", | |
257 | REGISTER_NAME (regno), regno); | |
258 | perror_with_name (mess); | |
259 | } | |
260 | } | |
56d0d96a AC |
261 | |
262 | /* Now supply the register. Be careful to map between ptrace's and | |
263 | the current_regcache's idea of the current wordsize. */ | |
366f009f JB |
264 | if ((regno >= tdep->ppc_fp0_regnum |
265 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) | |
56d0d96a AC |
266 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
267 | /* FPs are always 64 bits. Little endian values are always found | |
268 | at the left-hand end of the register. */ | |
269 | regcache_raw_supply (current_regcache, regno, buf); | |
270 | else | |
271 | /* Big endian register, need to fetch the right-hand end. */ | |
272 | regcache_raw_supply (current_regcache, regno, | |
273 | (buf + sizeof (PTRACE_XFER_TYPE) | |
274 | - register_size (current_gdbarch, regno))); | |
45229ea4 EZ |
275 | } |
276 | ||
9abe5450 EZ |
277 | static void |
278 | supply_vrregset (gdb_vrregset_t *vrregsetp) | |
279 | { | |
280 | int i; | |
281 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
282 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; | |
12c266ea AC |
283 | int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
284 | int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
285 | |
286 | for (i = 0; i < num_of_vrregs; i++) | |
287 | { | |
288 | /* The last 2 registers of this set are only 32 bit long, not | |
289 | 128. However an offset is necessary only for VSCR because it | |
290 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
291 | slot. */ | |
292 | if (i == (num_of_vrregs - 2)) | |
293 | supply_register (tdep->ppc_vr0_regnum + i, | |
294 | *vrregsetp + i * vrregsize + offset); | |
295 | else | |
296 | supply_register (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize); | |
297 | } | |
298 | } | |
299 | ||
300 | static void | |
301 | fetch_altivec_registers (int tid) | |
302 | { | |
303 | int ret; | |
304 | gdb_vrregset_t regs; | |
305 | ||
306 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
307 | if (ret < 0) | |
308 | { | |
309 | if (errno == EIO) | |
310 | { | |
311 | have_ptrace_getvrregs = 0; | |
312 | return; | |
313 | } | |
314 | perror_with_name ("Unable to fetch AltiVec registers"); | |
315 | } | |
316 | supply_vrregset (®s); | |
317 | } | |
318 | ||
45229ea4 | 319 | static void |
05f13b9c | 320 | fetch_ppc_registers (int tid) |
45229ea4 EZ |
321 | { |
322 | int i; | |
9abe5450 EZ |
323 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
324 | ||
32b99774 JB |
325 | for (i = 0; i < ppc_num_gprs; i++) |
326 | fetch_register (tid, tdep->ppc_gp0_regnum + i); | |
327 | if (tdep->ppc_fp0_regnum >= 0) | |
328 | for (i = 0; i < ppc_num_fprs; i++) | |
329 | fetch_register (tid, tdep->ppc_fp0_regnum + i); | |
330 | fetch_register (tid, PC_REGNUM); | |
331 | if (tdep->ppc_ps_regnum != -1) | |
332 | fetch_register (tid, tdep->ppc_ps_regnum); | |
333 | if (tdep->ppc_cr_regnum != -1) | |
334 | fetch_register (tid, tdep->ppc_cr_regnum); | |
335 | if (tdep->ppc_lr_regnum != -1) | |
336 | fetch_register (tid, tdep->ppc_lr_regnum); | |
337 | if (tdep->ppc_ctr_regnum != -1) | |
338 | fetch_register (tid, tdep->ppc_ctr_regnum); | |
339 | if (tdep->ppc_xer_regnum != -1) | |
340 | fetch_register (tid, tdep->ppc_xer_regnum); | |
e3f36dbd KB |
341 | if (tdep->ppc_mq_regnum != -1) |
342 | fetch_register (tid, tdep->ppc_mq_regnum); | |
32b99774 JB |
343 | if (tdep->ppc_fpscr_regnum != -1) |
344 | fetch_register (tid, tdep->ppc_fpscr_regnum); | |
9abe5450 EZ |
345 | if (have_ptrace_getvrregs) |
346 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
347 | fetch_altivec_registers (tid); | |
45229ea4 EZ |
348 | } |
349 | ||
350 | /* Fetch registers from the child process. Fetch all registers if | |
351 | regno == -1, otherwise fetch all general registers or all floating | |
352 | point registers depending upon the value of regno. */ | |
353 | void | |
354 | fetch_inferior_registers (int regno) | |
355 | { | |
9abe5450 | 356 | /* Overload thread id onto process id */ |
05f13b9c EZ |
357 | int tid = TIDGET (inferior_ptid); |
358 | ||
359 | /* No thread id, just use process id */ | |
360 | if (tid == 0) | |
361 | tid = PIDGET (inferior_ptid); | |
362 | ||
9abe5450 | 363 | if (regno == -1) |
05f13b9c | 364 | fetch_ppc_registers (tid); |
45229ea4 | 365 | else |
05f13b9c | 366 | fetch_register (tid, regno); |
45229ea4 EZ |
367 | } |
368 | ||
369 | /* Store one register. */ | |
9abe5450 EZ |
370 | static void |
371 | store_altivec_register (int tid, int regno) | |
372 | { | |
373 | int ret; | |
374 | int offset = 0; | |
375 | gdb_vrregset_t regs; | |
376 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
12c266ea | 377 | int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
9abe5450 EZ |
378 | |
379 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
380 | if (ret < 0) | |
381 | { | |
382 | if (errno == EIO) | |
383 | { | |
384 | have_ptrace_getvrregs = 0; | |
385 | return; | |
386 | } | |
387 | perror_with_name ("Unable to fetch AltiVec register"); | |
388 | } | |
389 | ||
390 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
391 | long on the hardware. */ | |
392 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
12c266ea | 393 | offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); |
9abe5450 EZ |
394 | |
395 | regcache_collect (regno, | |
396 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
397 | ||
398 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
399 | if (ret < 0) | |
400 | perror_with_name ("Unable to store AltiVec register"); | |
401 | } | |
402 | ||
45229ea4 | 403 | static void |
05f13b9c | 404 | store_register (int tid, int regno) |
45229ea4 | 405 | { |
366f009f | 406 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 EZ |
407 | /* This isn't really an address. But ptrace thinks of it as one. */ |
408 | CORE_ADDR regaddr = ppc_register_u_addr (regno); | |
409 | char mess[128]; /* For messages */ | |
52f0bd74 | 410 | int i; |
45229ea4 | 411 | unsigned int offset; /* Offset of registers within the u area. */ |
d9d9c31f | 412 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 413 | |
9abe5450 | 414 | if (altivec_register_p (regno)) |
45229ea4 | 415 | { |
9abe5450 | 416 | store_altivec_register (tid, regno); |
45229ea4 EZ |
417 | return; |
418 | } | |
419 | ||
9abe5450 EZ |
420 | if (regaddr == -1) |
421 | return; | |
422 | ||
383f0f5b JB |
423 | /* If the current architecture has no floating-point registers, we |
424 | should never reach this point: ppc_register_u_addr should have | |
425 | returned -1, and we should have caught that above. */ | |
426 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
427 | ||
56d0d96a AC |
428 | /* First collect the register value from the regcache. Be careful |
429 | to to convert the regcache's wordsize into ptrace's wordsize. */ | |
430 | memset (buf, 0, sizeof buf); | |
366f009f JB |
431 | if ((regno >= tdep->ppc_fp0_regnum |
432 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) | |
56d0d96a AC |
433 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) |
434 | /* Floats are always 64-bit. Little endian registers are always | |
435 | at the left-hand end of the register cache. */ | |
436 | regcache_raw_collect (current_regcache, regno, buf); | |
437 | else | |
438 | /* Big-endian registers belong at the right-hand end of the | |
439 | buffer. */ | |
440 | regcache_raw_collect (current_regcache, regno, | |
441 | (buf + sizeof (PTRACE_XFER_TYPE) | |
442 | - register_size (current_gdbarch, regno))); | |
443 | ||
12c266ea | 444 | for (i = 0; i < DEPRECATED_REGISTER_RAW_SIZE (regno); i += sizeof (PTRACE_XFER_TYPE)) |
45229ea4 EZ |
445 | { |
446 | errno = 0; | |
447 | ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) regaddr, | |
448 | *(PTRACE_XFER_TYPE *) & buf[i]); | |
449 | regaddr += sizeof (PTRACE_XFER_TYPE); | |
e3f36dbd KB |
450 | |
451 | if (errno == EIO | |
383f0f5b | 452 | && regno == tdep->ppc_fpscr_regnum) |
e3f36dbd KB |
453 | { |
454 | /* Some older kernel versions don't allow fpscr to be written. */ | |
455 | continue; | |
456 | } | |
457 | ||
45229ea4 EZ |
458 | if (errno != 0) |
459 | { | |
460 | sprintf (mess, "writing register %s (#%d)", | |
461 | REGISTER_NAME (regno), regno); | |
462 | perror_with_name (mess); | |
463 | } | |
464 | } | |
465 | } | |
466 | ||
9abe5450 EZ |
467 | static void |
468 | fill_vrregset (gdb_vrregset_t *vrregsetp) | |
469 | { | |
470 | int i; | |
471 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
472 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; | |
12c266ea AC |
473 | int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
474 | int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
475 | |
476 | for (i = 0; i < num_of_vrregs; i++) | |
477 | { | |
478 | /* The last 2 registers of this set are only 32 bit long, not | |
479 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
480 | if (i == (num_of_vrregs - 2)) | |
481 | regcache_collect (tdep->ppc_vr0_regnum + i, | |
482 | *vrregsetp + i * vrregsize + offset); | |
483 | else | |
484 | regcache_collect (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize); | |
485 | } | |
486 | } | |
487 | ||
488 | static void | |
489 | store_altivec_registers (int tid) | |
490 | { | |
491 | int ret; | |
492 | gdb_vrregset_t regs; | |
493 | ||
0897f59b | 494 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
495 | if (ret < 0) |
496 | { | |
497 | if (errno == EIO) | |
498 | { | |
499 | have_ptrace_getvrregs = 0; | |
500 | return; | |
501 | } | |
502 | perror_with_name ("Couldn't get AltiVec registers"); | |
503 | } | |
504 | ||
505 | fill_vrregset (®s); | |
506 | ||
0897f59b | 507 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
9abe5450 EZ |
508 | perror_with_name ("Couldn't write AltiVec registers"); |
509 | } | |
510 | ||
45229ea4 | 511 | static void |
05f13b9c | 512 | store_ppc_registers (int tid) |
45229ea4 EZ |
513 | { |
514 | int i; | |
9abe5450 | 515 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 | 516 | |
32b99774 JB |
517 | for (i = 0; i < ppc_num_gprs; i++) |
518 | store_register (tid, tdep->ppc_gp0_regnum + i); | |
519 | if (tdep->ppc_fp0_regnum >= 0) | |
520 | for (i = 0; i < ppc_num_fprs; i++) | |
521 | store_register (tid, tdep->ppc_fp0_regnum + i); | |
522 | store_register (tid, PC_REGNUM); | |
523 | if (tdep->ppc_ps_regnum != -1) | |
524 | store_register (tid, tdep->ppc_ps_regnum); | |
525 | if (tdep->ppc_cr_regnum != -1) | |
526 | store_register (tid, tdep->ppc_cr_regnum); | |
527 | if (tdep->ppc_lr_regnum != -1) | |
528 | store_register (tid, tdep->ppc_lr_regnum); | |
529 | if (tdep->ppc_ctr_regnum != -1) | |
530 | store_register (tid, tdep->ppc_ctr_regnum); | |
531 | if (tdep->ppc_xer_regnum != -1) | |
532 | store_register (tid, tdep->ppc_xer_regnum); | |
e3f36dbd KB |
533 | if (tdep->ppc_mq_regnum != -1) |
534 | store_register (tid, tdep->ppc_mq_regnum); | |
32b99774 JB |
535 | if (tdep->ppc_fpscr_regnum != -1) |
536 | store_register (tid, tdep->ppc_fpscr_regnum); | |
9abe5450 EZ |
537 | if (have_ptrace_getvrregs) |
538 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
539 | store_altivec_registers (tid); | |
45229ea4 EZ |
540 | } |
541 | ||
542 | void | |
543 | store_inferior_registers (int regno) | |
544 | { | |
05f13b9c EZ |
545 | /* Overload thread id onto process id */ |
546 | int tid = TIDGET (inferior_ptid); | |
547 | ||
548 | /* No thread id, just use process id */ | |
549 | if (tid == 0) | |
550 | tid = PIDGET (inferior_ptid); | |
551 | ||
45229ea4 | 552 | if (regno >= 0) |
05f13b9c | 553 | store_register (tid, regno); |
45229ea4 | 554 | else |
05f13b9c | 555 | store_ppc_registers (tid); |
45229ea4 EZ |
556 | } |
557 | ||
50c9bd31 | 558 | void |
8ae45c11 | 559 | supply_gregset (gdb_gregset_t *gregsetp) |
c877c8e6 | 560 | { |
f9be684a AC |
561 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
562 | interface, and not the wordsize of the program's ABI. */ | |
563 | int wordsize = sizeof (PTRACE_XFER_TYPE); | |
564 | ppc_linux_supply_gregset (current_regcache, -1, gregsetp, | |
565 | sizeof (gdb_gregset_t), wordsize); | |
566 | } | |
567 | ||
568 | static void | |
569 | right_fill_reg (int regnum, void *reg) | |
570 | { | |
571 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace | |
572 | interface, and not the wordsize of the program's ABI. */ | |
573 | int wordsize = sizeof (PTRACE_XFER_TYPE); | |
574 | /* Right fill the register. */ | |
575 | regcache_raw_collect (current_regcache, regnum, | |
576 | ((bfd_byte *) reg | |
577 | + wordsize | |
578 | - register_size (current_gdbarch, regnum))); | |
c877c8e6 KB |
579 | } |
580 | ||
fdb28ac4 | 581 | void |
8ae45c11 | 582 | fill_gregset (gdb_gregset_t *gregsetp, int regno) |
fdb28ac4 KB |
583 | { |
584 | int regi; | |
2ac44c70 | 585 | elf_greg_t *regp = (elf_greg_t *) gregsetp; |
dc5cfeb6 | 586 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
f9be684a AC |
587 | const int elf_ngreg = 48; |
588 | ||
589 | ||
590 | /* Start with zeros. */ | |
591 | memset (regp, 0, elf_ngreg * sizeof (*regp)); | |
fdb28ac4 | 592 | |
fdb28ac4 KB |
593 | for (regi = 0; regi < 32; regi++) |
594 | { | |
16333c4f | 595 | if ((regno == -1) || regno == regi) |
f9be684a | 596 | right_fill_reg (regi, (regp + PT_R0 + regi)); |
fdb28ac4 KB |
597 | } |
598 | ||
16333c4f | 599 | if ((regno == -1) || regno == PC_REGNUM) |
f9be684a | 600 | right_fill_reg (PC_REGNUM, regp + PT_NIP); |
05f13b9c | 601 | if ((regno == -1) || regno == tdep->ppc_lr_regnum) |
f9be684a | 602 | right_fill_reg (tdep->ppc_lr_regnum, regp + PT_LNK); |
05f13b9c | 603 | if ((regno == -1) || regno == tdep->ppc_cr_regnum) |
dc5cfeb6 | 604 | regcache_collect (tdep->ppc_cr_regnum, regp + PT_CCR); |
05f13b9c | 605 | if ((regno == -1) || regno == tdep->ppc_xer_regnum) |
dc5cfeb6 | 606 | regcache_collect (tdep->ppc_xer_regnum, regp + PT_XER); |
05f13b9c | 607 | if ((regno == -1) || regno == tdep->ppc_ctr_regnum) |
f9be684a | 608 | right_fill_reg (tdep->ppc_ctr_regnum, regp + PT_CTR); |
f8c59253 | 609 | #ifdef PT_MQ |
e3f36dbd KB |
610 | if (((regno == -1) || regno == tdep->ppc_mq_regnum) |
611 | && (tdep->ppc_mq_regnum != -1)) | |
f9be684a | 612 | right_fill_reg (tdep->ppc_mq_regnum, regp + PT_MQ); |
f8c59253 | 613 | #endif |
05f13b9c | 614 | if ((regno == -1) || regno == tdep->ppc_ps_regnum) |
f9be684a | 615 | right_fill_reg (tdep->ppc_ps_regnum, regp + PT_MSR); |
fdb28ac4 KB |
616 | } |
617 | ||
50c9bd31 | 618 | void |
8ae45c11 | 619 | supply_fpregset (gdb_fpregset_t * fpregsetp) |
c877c8e6 | 620 | { |
f9be684a AC |
621 | ppc_linux_supply_fpregset (NULL, current_regcache, -1, fpregsetp, |
622 | sizeof (gdb_fpregset_t)); | |
c877c8e6 | 623 | } |
fdb28ac4 | 624 | |
9abe5450 EZ |
625 | /* Given a pointer to a floating point register set in /proc format |
626 | (fpregset_t *), update the register specified by REGNO from gdb's | |
627 | idea of the current floating point register set. If REGNO is -1, | |
628 | update them all. */ | |
fdb28ac4 | 629 | void |
8ae45c11 | 630 | fill_fpregset (gdb_fpregset_t *fpregsetp, int regno) |
fdb28ac4 KB |
631 | { |
632 | int regi; | |
e3f36dbd | 633 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
f9be684a | 634 | bfd_byte *fpp = (void *) fpregsetp; |
fdb28ac4 | 635 | |
383f0f5b | 636 | if (ppc_floating_point_unit_p (current_gdbarch)) |
fdb28ac4 | 637 | { |
383f0f5b JB |
638 | for (regi = 0; regi < ppc_num_fprs; regi++) |
639 | { | |
640 | if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi)) | |
641 | regcache_collect (tdep->ppc_fp0_regnum + regi, fpp + 8 * regi); | |
642 | } | |
643 | if (regno == -1 || regno == tdep->ppc_fpscr_regnum) | |
644 | right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32)); | |
fdb28ac4 KB |
645 | } |
646 | } |