[deliverable/binutils-gdb.git] / gdb / ppc-tdep.h

/* Target-dependent code for GDB, the GNU debugger.

   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef PPC_TDEP_H
#define PPC_TDEP_H

struct gdbarch;
struct frame_info;
struct value;
struct regcache;
struct type;

/* From ppc-sysv-tdep.c ... */
enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
							struct type *func_type,
							struct type *valtype,
							struct regcache *regcache,
							gdb_byte *readbuf,
							const gdb_byte *writebuf);
enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
							       struct type *func_type,
							       struct type *valtype,
							       struct regcache *regcache,
							       gdb_byte *readbuf,
							       const gdb_byte *writebuf);
CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					struct value *function,
					struct regcache *regcache,
					CORE_ADDR bp_addr, int nargs,
					struct value **args, CORE_ADDR sp,
					int struct_return,
					CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					  struct value *function,
					  struct regcache *regcache,
					  CORE_ADDR bp_addr, int nargs,
					  struct value **args, CORE_ADDR sp,
					  int struct_return,
					  CORE_ADDR struct_addr);
enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
							  struct type *func_type,
							  struct type *valtype,
							  struct regcache *regcache,
							  gdb_byte *readbuf,
							  const gdb_byte *writebuf);

/* From rs6000-tdep.c... */
int altivec_register_p (struct gdbarch *gdbarch, int regno);
int spe_register_p (struct gdbarch *gdbarch, int regno);

/* Return non-zero if the architecture described by GDBARCH has
   floating-point registers (f0 --- f31 and fpscr).  */
int ppc_floating_point_unit_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   Altivec registers (vr0 --- vr31, vrsave and vscr).  */
int ppc_altivec_support_p (struct gdbarch *gdbarch);

int ppc_deal_with_atomic_sequence (struct frame_info *frame);


/* Register set description.  */

struct ppc_reg_offsets
{
  /* General-purpose registers.  */
  int r0_offset;
  int gpr_size; /* size for r0-31, pc, ps, lr, ctr.  */
  int xr_size;  /* size for cr, xer, mq.  */
  int pc_offset;
  int ps_offset;
  int cr_offset;
  int lr_offset;
  int ctr_offset;
  int xer_offset;
  int mq_offset;

  /* Floating-point registers.  */
  int f0_offset;
  int fpscr_offset;
  int fpscr_size;

  /* AltiVec registers.  */
  int vr0_offset;
  int vscr_offset;
  int vrsave_offset;
};

extern void ppc_supply_reg (struct regcache *regcache, int regnum,
			    const gdb_byte *regs, size_t offset, int regsize);

extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
			     gdb_byte *regs, size_t offset, int regsize);

/* Supply register REGNUM in the general-purpose register set REGSET
   from the buffer specified by GREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_gregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t len);

/* Supply register REGNUM in the floating-point register set REGSET
   from the buffer specified by FPREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_fpregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *fpregs, size_t len);

/* Supply register REGNUM in the Altivec register set REGSET
   from the buffer specified by VRREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vrregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vrregs, size_t len);

/* Collect register REGNUM in the general-purpose register set
   REGSET. from register cache REGCACHE into the buffer specified by
   GREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_gregset (const struct regset *regset,
				 const struct regcache *regcache,
				 int regnum, void *gregs, size_t len);

/* Collect register REGNUM in the floating-point register set
   REGSET. from register cache REGCACHE into the buffer specified by
   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_fpregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *fpregs, size_t len);

/* Collect register REGNUM in the Altivec register set
   REGSET from register cache REGCACHE into the buffer specified by
   VRREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vrregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vrregs, size_t len);

/* Private data that this module attaches to struct gdbarch. */

/* Vector ABI used by the inferior.  */
enum powerpc_vector_abi
{
  POWERPC_VEC_AUTO,
  POWERPC_VEC_GENERIC,
  POWERPC_VEC_ALTIVEC,
  POWERPC_VEC_SPE,
  POWERPC_VEC_LAST
};

struct gdbarch_tdep
  {
    int wordsize;		/* Size in bytes of fixed-point word.  */
    int soft_float;		/* Avoid FP registers for arguments?  */

    /* How to pass vector arguments.  Never set to AUTO or LAST.  */
    enum powerpc_vector_abi vector_abi;

    int ppc_gp0_regnum;		/* GPR register 0 */
    int ppc_toc_regnum;		/* TOC register */
    int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
    int ppc_cr_regnum;		/* Condition register */
    int ppc_lr_regnum;		/* Link register */
    int ppc_ctr_regnum;		/* Count register */
    int ppc_xer_regnum;		/* Integer exception register */

    /* Not all PPC and RS6000 variants will have the registers
       represented below.  A -1 is used to indicate that the register
       is not present in this variant.  */

    /* Floating-point registers.  */
    int ppc_fp0_regnum;         /* floating-point register 0 */
    int ppc_fpscr_regnum;	/* fp status and condition register */

    /* Multiplier-Quotient Register (older POWER architectures only).  */
    int ppc_mq_regnum;

    /* Altivec registers.  */
    int ppc_vr0_regnum;		/* First AltiVec register */
    int ppc_vrsave_regnum;	/* Last AltiVec register */

    /* SPE registers.  */
    int ppc_ev0_upper_regnum;   /* First GPR upper half register */
    int ppc_ev0_regnum;         /* First ev register */
    int ppc_acc_regnum;         /* SPE 'acc' register */
    int ppc_spefscr_regnum;     /* SPE 'spefscr' register */

    /* Decimal 128 registers.  */
    int ppc_dl0_regnum;		/* First Decimal128 argument register pair.  */

    /* Offset to ABI specific location where link register is saved.  */
    int lr_frame_offset;	

    /* An array of integers, such that sim_regno[I] is the simulator
       register number for GDB register number I, or -1 if the
       simulator does not implement that register.  */
    int *sim_regno;

    /* ISA-specific types.  */
    struct type *ppc_builtin_type_vec64;
};


/* Constants for register set sizes.  */
enum
  {
    ppc_num_gprs = 32,          /* 32 general-purpose registers */
    ppc_num_fprs = 32,          /* 32 floating-point registers */
    ppc_num_srs = 16,           /* 16 segment registers */
    ppc_num_vrs = 32            /* 32 Altivec vector registers */
  };


/* Register number constants.  These are GDB internal register
   numbers; they are not used for the simulator or remote targets.
   Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
   numbers above PPC_NUM_REGS.  So are segment registers and other
   target-defined registers.  */
enum {
  PPC_R0_REGNUM = 0,
  PPC_F0_REGNUM = 32,
  PPC_PC_REGNUM = 64,
  PPC_MSR_REGNUM = 65,
  PPC_CR_REGNUM = 66,
  PPC_LR_REGNUM = 67,
  PPC_CTR_REGNUM = 68,
  PPC_XER_REGNUM = 69,
  PPC_FPSCR_REGNUM = 70,
  PPC_MQ_REGNUM = 71,
  PPC_SPE_UPPER_GP0_REGNUM = 72,
  PPC_SPE_ACC_REGNUM = 104,
  PPC_SPE_FSCR_REGNUM = 105,
  PPC_VR0_REGNUM = 106,
  PPC_VSCR_REGNUM = 138,
  PPC_VRSAVE_REGNUM = 139,
  PPC_NUM_REGS
};


/* Instruction size.  */
#define PPC_INSN_SIZE 4

/* Estimate for the maximum number of instrctions in a function epilogue.  */
#define PPC_MAX_EPILOGUE_INSTRUCTIONS  52

#endif /* ppc-tdep.h */
Commit	Line	Data
9aa1e687	1	/* Target-dependent code for GDB, the GNU debugger.
f9be684a	2
9b254dd1	3	Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
a0c75879	4	Free Software Foundation, Inc.
9aa1e687 KB	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
a9762ec7	10	the Free Software Foundation; either version 3 of the License, or
9aa1e687 KB	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
a9762ec7	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9aa1e687	20
3a1c5313 AC	21	#ifndef PPC_TDEP_H
	22	#define PPC_TDEP_H
	23
da3331ec	24	struct gdbarch;
3a1c5313 AC	25	struct frame_info;
3a1c5313 AC	26	struct value;
4a4b3fed	27	struct regcache;
221c12ff	28	struct type;
3a1c5313	29
7284e1be	30	/* From ppc-sysv-tdep.c ... */
05580c65	31	enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
c055b101	32	struct type *func_type,
05580c65 AC	33	struct type *valtype,
05580c65 AC	34	struct regcache *regcache,
50fd1280 AC	35	gdb_byte *readbuf,
50fd1280 AC	36	const gdb_byte *writebuf);
05580c65	37	enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
c055b101	38	struct type *func_type,
05580c65 AC	39	struct type *valtype,
05580c65 AC	40	struct regcache *regcache,
50fd1280 AC	41	gdb_byte *readbuf,
50fd1280 AC	42	const gdb_byte *writebuf);
77b2b6d4	43	CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	44	struct value *function,
77b2b6d4 AC	45	struct regcache *regcache,
	46	CORE_ADDR bp_addr, int nargs,
	47	struct value **args, CORE_ADDR sp,
	48	int struct_return,
	49	CORE_ADDR struct_addr);
8be9034a	50	CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	51	struct value *function,
8be9034a AC	52	struct regcache *regcache,
	53	CORE_ADDR bp_addr, int nargs,
	54	struct value **args, CORE_ADDR sp,
	55	int struct_return,
	56	CORE_ADDR struct_addr);
05580c65	57	enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
c055b101	58	struct type *func_type,
05580c65 AC	59	struct type *valtype,
05580c65 AC	60	struct regcache *regcache,
50fd1280 AC	61	gdb_byte *readbuf,
50fd1280 AC	62	const gdb_byte *writebuf);
9aa1e687 KB	63
9aa1e687 KB	64	/* From rs6000-tdep.c... */
be8626e0 MD	65	int altivec_register_p (struct gdbarch *gdbarch, int regno);
be8626e0 MD	66	int spe_register_p (struct gdbarch *gdbarch, int regno);
9aa1e687	67
383f0f5b JB	68	/* Return non-zero if the architecture described by GDBARCH has
383f0f5b JB	69	floating-point registers (f0 --- f31 and fpscr). */
0a613259 AC	70	int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
0a613259 AC	71
06caf7d2 CES	72	/* Return non-zero if the architecture described by GDBARCH has
	73	Altivec registers (vr0 --- vr31, vrsave and vscr). */
	74	int ppc_altivec_support_p (struct gdbarch *gdbarch);
	75
4a7622d1 UW	76	int ppc_deal_with_atomic_sequence (struct frame_info *frame);
	77
	78
d195bc9f MK	79	/* Register set description. */
	80
	81	struct ppc_reg_offsets
	82	{
	83	/* General-purpose registers. */
	84	int r0_offset;
f2db237a AM	85	int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
f2db237a AM	86	int xr_size; /* size for cr, xer, mq. */
d195bc9f MK	87	int pc_offset;
	88	int ps_offset;
	89	int cr_offset;
	90	int lr_offset;
	91	int ctr_offset;
	92	int xer_offset;
	93	int mq_offset;
	94
	95	/* Floating-point registers. */
	96	int f0_offset;
	97	int fpscr_offset;
f2db237a	98	int fpscr_size;
d195bc9f MK	99
	100	/* AltiVec registers. */
	101	int vr0_offset;
	102	int vscr_offset;
	103	int vrsave_offset;
	104	};
	105
7284e1be UW	106	extern void ppc_supply_reg (struct regcache *regcache, int regnum,
	107	const gdb_byte *regs, size_t offset, int regsize);
	108
	109	extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
	110	gdb_byte *regs, size_t offset, int regsize);
	111
d195bc9f MK	112	/* Supply register REGNUM in the general-purpose register set REGSET
	113	from the buffer specified by GREGS and LEN to register cache
	114	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	115
	116	extern void ppc_supply_gregset (const struct regset *regset,
	117	struct regcache *regcache,
	118	int regnum, const void *gregs, size_t len);
	119
	120	/* Supply register REGNUM in the floating-point register set REGSET
	121	from the buffer specified by FPREGS and LEN to register cache
	122	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	123
	124	extern void ppc_supply_fpregset (const struct regset *regset,
	125	struct regcache *regcache,
	126	int regnum, const void *fpregs, size_t len);
	127
06caf7d2 CES	128	/* Supply register REGNUM in the Altivec register set REGSET
	129	from the buffer specified by VRREGS and LEN to register cache
	130	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	131
	132	extern void ppc_supply_vrregset (const struct regset *regset,
	133	struct regcache *regcache,
	134	int regnum, const void *vrregs, size_t len);
	135
d195bc9f MK	136	/* Collect register REGNUM in the general-purpose register set
	137	REGSET. from register cache REGCACHE into the buffer specified by
	138	GREGS and LEN. If REGNUM is -1, do this for all registers in
	139	REGSET. */
	140
	141	extern void ppc_collect_gregset (const struct regset *regset,
	142	const struct regcache *regcache,
	143	int regnum, void *gregs, size_t len);
	144
	145	/* Collect register REGNUM in the floating-point register set
	146	REGSET. from register cache REGCACHE into the buffer specified by
	147	FPREGS and LEN. If REGNUM is -1, do this for all registers in
	148	REGSET. */
	149
	150	extern void ppc_collect_fpregset (const struct regset *regset,
	151	const struct regcache *regcache,
	152	int regnum, void *fpregs, size_t len);
	153
06caf7d2 CES	154	/* Collect register REGNUM in the Altivec register set
	155	REGSET from register cache REGCACHE into the buffer specified by
	156	VRREGS and LEN. If REGNUM is -1, do this for all registers in
	157	REGSET. */
	158
	159	extern void ppc_collect_vrregset (const struct regset *regset,
	160	const struct regcache *regcache,
	161	int regnum, void *vrregs, size_t len);
	162
2188cbdd EZ	163	/* Private data that this module attaches to struct gdbarch. */
2188cbdd EZ	164
55eddb0f DJ	165	/* Vector ABI used by the inferior. */
	166	enum powerpc_vector_abi
	167	{
	168	POWERPC_VEC_AUTO,
	169	POWERPC_VEC_GENERIC,
	170	POWERPC_VEC_ALTIVEC,
	171	POWERPC_VEC_SPE,
	172	POWERPC_VEC_LAST
	173	};
	174
2188cbdd EZ	175	struct gdbarch_tdep
2188cbdd EZ	176	{
55eddb0f DJ	177	int wordsize; /* Size in bytes of fixed-point word. */
	178	int soft_float; /* Avoid FP registers for arguments? */
	179
	180	/* How to pass vector arguments. Never set to AUTO or LAST. */
	181	enum powerpc_vector_abi vector_abi;
	182
2188cbdd	183	int ppc_gp0_regnum; /* GPR register 0 */
2188cbdd EZ	184	int ppc_toc_regnum; /* TOC register */
	185	int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
	186	int ppc_cr_regnum; /* Condition register */
	187	int ppc_lr_regnum; /* Link register */
	188	int ppc_ctr_regnum; /* Count register */
	189	int ppc_xer_regnum; /* Integer exception register */
383f0f5b	190
826d5376 PG	191	/* Not all PPC and RS6000 variants will have the registers
	192	represented below. A -1 is used to indicate that the register
	193	is not present in this variant. */
	194
	195	/* Floating-point registers. */
366f009f	196	int ppc_fp0_regnum; /* floating-point register 0 */
826d5376 PG	197	int ppc_fpscr_regnum; /* fp status and condition register */
826d5376 PG	198
826d5376 PG	199	/* Multiplier-Quotient Register (older POWER architectures only). */
826d5376 PG	200	int ppc_mq_regnum;
f86a7158	201
826d5376	202	/* Altivec registers. */
1fcc0bb8 EZ	203	int ppc_vr0_regnum; /* First AltiVec register */
1fcc0bb8 EZ	204	int ppc_vrsave_regnum; /* Last AltiVec register */
826d5376 PG	205
826d5376 PG	206	/* SPE registers. */
6ced10dd	207	int ppc_ev0_upper_regnum; /* First GPR upper half register */
c8001721	208	int ppc_ev0_regnum; /* First ev register */
867e2dc5 JB	209	int ppc_acc_regnum; /* SPE 'acc' register */
867e2dc5 JB	210	int ppc_spefscr_regnum; /* SPE 'spefscr' register */
826d5376	211
f949c649 TJB	212	/* Decimal 128 registers. */
	213	int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
	214
826d5376 PG	215	/* Offset to ABI specific location where link register is saved. */
826d5376 PG	216	int lr_frame_offset;
9f643768 JB	217
	218	/* An array of integers, such that sim_regno[I] is the simulator
	219	register number for GDB register number I, or -1 if the
	220	simulator does not implement that register. */
	221	int *sim_regno;
6f7f3f0d	222
794ac428 UW	223	/* ISA-specific types. */
794ac428 UW	224	struct type *ppc_builtin_type_vec64;
2188cbdd	225	};
3a1c5313	226
b967e06f JB	227
	228	/* Constants for register set sizes. */
	229	enum
	230	{
8bf659e8	231	ppc_num_gprs = 32, /* 32 general-purpose registers */
cc98b5cc	232	ppc_num_fprs = 32, /* 32 floating-point registers */
8f088af7	233	ppc_num_srs = 16, /* 16 segment registers */
cc98b5cc	234	ppc_num_vrs = 32 /* 32 Altivec vector registers */
b967e06f JB	235	};
b967e06f JB	236
0ea0ec5f	237
7cc46491 DJ	238	/* Register number constants. These are GDB internal register
	239	numbers; they are not used for the simulator or remote targets.
	240	Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
	241	numbers above PPC_NUM_REGS. So are segment registers and other
	242	target-defined registers. */
	243	enum {
	244	PPC_R0_REGNUM = 0,
	245	PPC_F0_REGNUM = 32,
	246	PPC_PC_REGNUM = 64,
	247	PPC_MSR_REGNUM = 65,
	248	PPC_CR_REGNUM = 66,
	249	PPC_LR_REGNUM = 67,
	250	PPC_CTR_REGNUM = 68,
	251	PPC_XER_REGNUM = 69,
	252	PPC_FPSCR_REGNUM = 70,
	253	PPC_MQ_REGNUM = 71,
	254	PPC_SPE_UPPER_GP0_REGNUM = 72,
	255	PPC_SPE_ACC_REGNUM = 104,
	256	PPC_SPE_FSCR_REGNUM = 105,
	257	PPC_VR0_REGNUM = 106,
	258	PPC_VSCR_REGNUM = 138,
	259	PPC_VRSAVE_REGNUM = 139,
	260	PPC_NUM_REGS
	261	};
0ea0ec5f	262
0ea0ec5f	263
a0c75879 MK	264	/* Instruction size. */
	265	#define PPC_INSN_SIZE 4
	266
0d1243d9 PG	267	/* Estimate for the maximum number of instrctions in a function epilogue. */
	268	#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
	269
a0c75879	270	#endif /* ppc-tdep.h */