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9aa1e687 | 1 | /* Target-dependent code for GDB, the GNU debugger. |
f9be684a | 2 | |
42a4f53d | 3 | Copyright (C) 2000-2019 Free Software Foundation, Inc. |
9aa1e687 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
9aa1e687 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
9aa1e687 | 19 | |
3a1c5313 AC |
20 | #ifndef PPC_TDEP_H |
21 | #define PPC_TDEP_H | |
22 | ||
da3331ec | 23 | struct gdbarch; |
3a1c5313 AC |
24 | struct frame_info; |
25 | struct value; | |
4a4b3fed | 26 | struct regcache; |
221c12ff | 27 | struct type; |
3a1c5313 | 28 | |
0df8b418 | 29 | /* From ppc-sysv-tdep.c ... */ |
05580c65 | 30 | enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch, |
6a3a010b | 31 | struct value *function, |
05580c65 AC |
32 | struct type *valtype, |
33 | struct regcache *regcache, | |
50fd1280 AC |
34 | gdb_byte *readbuf, |
35 | const gdb_byte *writebuf); | |
05580c65 | 36 | enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch, |
6a3a010b | 37 | struct value *function, |
05580c65 AC |
38 | struct type *valtype, |
39 | struct regcache *regcache, | |
50fd1280 AC |
40 | gdb_byte *readbuf, |
41 | const gdb_byte *writebuf); | |
cf84fa6b AH |
42 | |
43 | CORE_ADDR ppc_sysv_abi_push_dummy_call | |
44 | (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, | |
45 | CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, | |
46 | function_call_return_method return_method, CORE_ADDR struct_addr); | |
47 | ||
48 | CORE_ADDR ppc64_sysv_abi_push_dummy_call | |
49 | (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, | |
50 | CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, | |
51 | function_call_return_method return_method, CORE_ADDR struct_addr); | |
52 | ||
05580c65 | 53 | enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch, |
6a3a010b | 54 | struct value *function, |
05580c65 AC |
55 | struct type *valtype, |
56 | struct regcache *regcache, | |
50fd1280 AC |
57 | gdb_byte *readbuf, |
58 | const gdb_byte *writebuf); | |
9aa1e687 | 59 | |
0df8b418 | 60 | /* From rs6000-tdep.c... */ |
be8626e0 | 61 | int altivec_register_p (struct gdbarch *gdbarch, int regno); |
604c2f83 | 62 | int vsx_register_p (struct gdbarch *gdbarch, int regno); |
be8626e0 | 63 | int spe_register_p (struct gdbarch *gdbarch, int regno); |
9aa1e687 | 64 | |
383f0f5b JB |
65 | /* Return non-zero if the architecture described by GDBARCH has |
66 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
67 | int ppc_floating_point_unit_p (struct gdbarch *gdbarch); |
68 | ||
06caf7d2 CES |
69 | /* Return non-zero if the architecture described by GDBARCH has |
70 | Altivec registers (vr0 --- vr31, vrsave and vscr). */ | |
71 | int ppc_altivec_support_p (struct gdbarch *gdbarch); | |
72 | ||
604c2f83 LM |
73 | /* Return non-zero if the architecture described by GDBARCH has |
74 | VSX registers (vsr0 --- vsr63). */ | |
75 | int vsx_support_p (struct gdbarch *gdbarch); | |
a0ff9e1a SM |
76 | std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence |
77 | (struct regcache *regcache); | |
4a7622d1 UW |
78 | |
79 | ||
d195bc9f MK |
80 | /* Register set description. */ |
81 | ||
82 | struct ppc_reg_offsets | |
83 | { | |
84 | /* General-purpose registers. */ | |
85 | int r0_offset; | |
f2db237a AM |
86 | int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */ |
87 | int xr_size; /* size for cr, xer, mq. */ | |
d195bc9f MK |
88 | int pc_offset; |
89 | int ps_offset; | |
90 | int cr_offset; | |
91 | int lr_offset; | |
92 | int ctr_offset; | |
93 | int xer_offset; | |
94 | int mq_offset; | |
95 | ||
96 | /* Floating-point registers. */ | |
97 | int f0_offset; | |
98 | int fpscr_offset; | |
f2db237a | 99 | int fpscr_size; |
d195bc9f MK |
100 | }; |
101 | ||
7284e1be UW |
102 | extern void ppc_supply_reg (struct regcache *regcache, int regnum, |
103 | const gdb_byte *regs, size_t offset, int regsize); | |
104 | ||
105 | extern void ppc_collect_reg (const struct regcache *regcache, int regnum, | |
106 | gdb_byte *regs, size_t offset, int regsize); | |
107 | ||
d195bc9f MK |
108 | /* Supply register REGNUM in the general-purpose register set REGSET |
109 | from the buffer specified by GREGS and LEN to register cache | |
110 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
111 | ||
112 | extern void ppc_supply_gregset (const struct regset *regset, | |
113 | struct regcache *regcache, | |
114 | int regnum, const void *gregs, size_t len); | |
115 | ||
116 | /* Supply register REGNUM in the floating-point register set REGSET | |
117 | from the buffer specified by FPREGS and LEN to register cache | |
118 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
119 | ||
120 | extern void ppc_supply_fpregset (const struct regset *regset, | |
121 | struct regcache *regcache, | |
122 | int regnum, const void *fpregs, size_t len); | |
123 | ||
06caf7d2 CES |
124 | /* Supply register REGNUM in the Altivec register set REGSET |
125 | from the buffer specified by VRREGS and LEN to register cache | |
126 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
127 | ||
128 | extern void ppc_supply_vrregset (const struct regset *regset, | |
129 | struct regcache *regcache, | |
130 | int regnum, const void *vrregs, size_t len); | |
131 | ||
604c2f83 LM |
132 | /* Supply register REGNUM in the VSX register set REGSET |
133 | from the buffer specified by VSXREGS and LEN to register cache | |
134 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
135 | ||
136 | extern void ppc_supply_vsxregset (const struct regset *regset, | |
137 | struct regcache *regcache, | |
138 | int regnum, const void *vsxregs, size_t len); | |
139 | ||
d195bc9f | 140 | /* Collect register REGNUM in the general-purpose register set |
0df8b418 | 141 | REGSET, from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
142 | GREGS and LEN. If REGNUM is -1, do this for all registers in |
143 | REGSET. */ | |
144 | ||
145 | extern void ppc_collect_gregset (const struct regset *regset, | |
146 | const struct regcache *regcache, | |
147 | int regnum, void *gregs, size_t len); | |
148 | ||
149 | /* Collect register REGNUM in the floating-point register set | |
0df8b418 | 150 | REGSET, from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
151 | FPREGS and LEN. If REGNUM is -1, do this for all registers in |
152 | REGSET. */ | |
153 | ||
154 | extern void ppc_collect_fpregset (const struct regset *regset, | |
155 | const struct regcache *regcache, | |
156 | int regnum, void *fpregs, size_t len); | |
157 | ||
06caf7d2 CES |
158 | /* Collect register REGNUM in the Altivec register set |
159 | REGSET from register cache REGCACHE into the buffer specified by | |
160 | VRREGS and LEN. If REGNUM is -1, do this for all registers in | |
161 | REGSET. */ | |
162 | ||
163 | extern void ppc_collect_vrregset (const struct regset *regset, | |
164 | const struct regcache *regcache, | |
165 | int regnum, void *vrregs, size_t len); | |
166 | ||
604c2f83 LM |
167 | /* Collect register REGNUM in the VSX register set |
168 | REGSET from register cache REGCACHE into the buffer specified by | |
169 | VSXREGS and LEN. If REGNUM is -1, do this for all registers in | |
170 | REGSET. */ | |
171 | ||
172 | extern void ppc_collect_vsxregset (const struct regset *regset, | |
173 | const struct regcache *regcache, | |
174 | int regnum, void *vsxregs, size_t len); | |
175 | ||
0df8b418 | 176 | /* Private data that this module attaches to struct gdbarch. */ |
2188cbdd | 177 | |
cd453cd0 UW |
178 | /* ELF ABI version used by the inferior. */ |
179 | enum powerpc_elf_abi | |
180 | { | |
181 | POWERPC_ELF_AUTO, | |
182 | POWERPC_ELF_V1, | |
183 | POWERPC_ELF_V2, | |
184 | POWERPC_ELF_LAST | |
185 | }; | |
186 | ||
55eddb0f DJ |
187 | /* Vector ABI used by the inferior. */ |
188 | enum powerpc_vector_abi | |
189 | { | |
190 | POWERPC_VEC_AUTO, | |
191 | POWERPC_VEC_GENERIC, | |
192 | POWERPC_VEC_ALTIVEC, | |
193 | POWERPC_VEC_SPE, | |
194 | POWERPC_VEC_LAST | |
195 | }; | |
196 | ||
ed0f4273 UW |
197 | /* long double ABI version used by the inferior. */ |
198 | enum powerpc_long_double_abi | |
199 | { | |
200 | POWERPC_LONG_DOUBLE_AUTO, | |
201 | POWERPC_LONG_DOUBLE_IBM128, | |
202 | POWERPC_LONG_DOUBLE_IEEE128, | |
203 | POWERPC_LONG_DOUBLE_LAST | |
204 | }; | |
205 | ||
2188cbdd EZ |
206 | struct gdbarch_tdep |
207 | { | |
55eddb0f DJ |
208 | int wordsize; /* Size in bytes of fixed-point word. */ |
209 | int soft_float; /* Avoid FP registers for arguments? */ | |
210 | ||
cd453cd0 UW |
211 | enum powerpc_elf_abi elf_abi; /* ELF ABI version. */ |
212 | ||
ed0f4273 UW |
213 | /* Format to use for the "long double" data type. */ |
214 | enum powerpc_long_double_abi long_double_abi; | |
215 | ||
55eddb0f DJ |
216 | /* How to pass vector arguments. Never set to AUTO or LAST. */ |
217 | enum powerpc_vector_abi vector_abi; | |
218 | ||
2188cbdd | 219 | int ppc_gp0_regnum; /* GPR register 0 */ |
2188cbdd EZ |
220 | int ppc_toc_regnum; /* TOC register */ |
221 | int ppc_ps_regnum; /* Processor (or machine) status (%msr) */ | |
222 | int ppc_cr_regnum; /* Condition register */ | |
223 | int ppc_lr_regnum; /* Link register */ | |
224 | int ppc_ctr_regnum; /* Count register */ | |
225 | int ppc_xer_regnum; /* Integer exception register */ | |
383f0f5b | 226 | |
826d5376 PG |
227 | /* Not all PPC and RS6000 variants will have the registers |
228 | represented below. A -1 is used to indicate that the register | |
229 | is not present in this variant. */ | |
230 | ||
231 | /* Floating-point registers. */ | |
0df8b418 MS |
232 | int ppc_fp0_regnum; /* Floating-point register 0. */ |
233 | int ppc_fpscr_regnum; /* fp status and condition register. */ | |
826d5376 | 234 | |
826d5376 PG |
235 | /* Multiplier-Quotient Register (older POWER architectures only). */ |
236 | int ppc_mq_regnum; | |
f86a7158 | 237 | |
604c2f83 LM |
238 | /* POWER7 VSX registers. */ |
239 | int ppc_vsr0_regnum; /* First VSX register. */ | |
240 | int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */ | |
241 | int ppc_efpr0_regnum; /* First Extended FP register. */ | |
242 | ||
826d5376 | 243 | /* Altivec registers. */ |
0df8b418 MS |
244 | int ppc_vr0_regnum; /* First AltiVec register. */ |
245 | int ppc_vrsave_regnum; /* Last AltiVec register. */ | |
826d5376 | 246 | |
6f072a10 PFC |
247 | /* Altivec pseudo-register vX aliases for the raw vrX |
248 | registers. */ | |
249 | int ppc_v0_alias_regnum; | |
250 | ||
826d5376 | 251 | /* SPE registers. */ |
0df8b418 MS |
252 | int ppc_ev0_upper_regnum; /* First GPR upper half register. */ |
253 | int ppc_ev0_regnum; /* First ev register. */ | |
254 | int ppc_acc_regnum; /* SPE 'acc' register. */ | |
255 | int ppc_spefscr_regnum; /* SPE 'spefscr' register. */ | |
826d5376 | 256 | |
7ca18ed6 EBM |
257 | /* Program Priority Register. */ |
258 | int ppc_ppr_regnum; | |
259 | ||
260 | /* Data Stream Control Register. */ | |
261 | int ppc_dscr_regnum; | |
262 | ||
f2cf6173 EBM |
263 | /* Target Address Register. */ |
264 | int ppc_tar_regnum; | |
265 | ||
f949c649 TJB |
266 | /* Decimal 128 registers. */ |
267 | int ppc_dl0_regnum; /* First Decimal128 argument register pair. */ | |
268 | ||
232bfb86 EBM |
269 | int have_ebb; |
270 | ||
271 | /* PMU registers. */ | |
272 | int ppc_mmcr0_regnum; | |
273 | int ppc_mmcr2_regnum; | |
274 | int ppc_siar_regnum; | |
275 | int ppc_sdar_regnum; | |
276 | int ppc_sier_regnum; | |
277 | ||
8d619c01 EBM |
278 | /* Hardware Transactional Memory registers. */ |
279 | int have_htm_spr; | |
280 | int have_htm_core; | |
281 | int have_htm_fpu; | |
282 | int have_htm_altivec; | |
283 | int have_htm_vsx; | |
284 | int ppc_cppr_regnum; | |
285 | int ppc_cdscr_regnum; | |
286 | int ppc_ctar_regnum; | |
287 | ||
288 | /* HTM pseudo registers. */ | |
289 | int ppc_cdl0_regnum; | |
290 | int ppc_cvsr0_regnum; | |
291 | int ppc_cefpr0_regnum; | |
292 | ||
826d5376 PG |
293 | /* Offset to ABI specific location where link register is saved. */ |
294 | int lr_frame_offset; | |
9f643768 JB |
295 | |
296 | /* An array of integers, such that sim_regno[I] is the simulator | |
297 | register number for GDB register number I, or -1 if the | |
298 | simulator does not implement that register. */ | |
299 | int *sim_regno; | |
6f7f3f0d | 300 | |
794ac428 UW |
301 | /* ISA-specific types. */ |
302 | struct type *ppc_builtin_type_vec64; | |
604c2f83 | 303 | struct type *ppc_builtin_type_vec128; |
b4cdae6f WW |
304 | |
305 | int (*ppc_syscall_record) (struct regcache *regcache); | |
2188cbdd | 306 | }; |
3a1c5313 | 307 | |
b967e06f JB |
308 | |
309 | /* Constants for register set sizes. */ | |
310 | enum | |
311 | { | |
604c2f83 LM |
312 | ppc_num_gprs = 32, /* 32 general-purpose registers. */ |
313 | ppc_num_fprs = 32, /* 32 floating-point registers. */ | |
314 | ppc_num_srs = 16, /* 16 segment registers. */ | |
315 | ppc_num_vrs = 32, /* 32 Altivec vector registers. */ | |
316 | ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */ | |
317 | ppc_num_vsrs = 64, /* 64 VSX vector registers. */ | |
318 | ppc_num_efprs = 32 /* 32 Extended FP registers. */ | |
b967e06f JB |
319 | }; |
320 | ||
0ea0ec5f | 321 | |
7cc46491 DJ |
322 | /* Register number constants. These are GDB internal register |
323 | numbers; they are not used for the simulator or remote targets. | |
324 | Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given | |
325 | numbers above PPC_NUM_REGS. So are segment registers and other | |
326 | target-defined registers. */ | |
327 | enum { | |
328 | PPC_R0_REGNUM = 0, | |
329 | PPC_F0_REGNUM = 32, | |
330 | PPC_PC_REGNUM = 64, | |
331 | PPC_MSR_REGNUM = 65, | |
332 | PPC_CR_REGNUM = 66, | |
333 | PPC_LR_REGNUM = 67, | |
334 | PPC_CTR_REGNUM = 68, | |
335 | PPC_XER_REGNUM = 69, | |
336 | PPC_FPSCR_REGNUM = 70, | |
337 | PPC_MQ_REGNUM = 71, | |
338 | PPC_SPE_UPPER_GP0_REGNUM = 72, | |
339 | PPC_SPE_ACC_REGNUM = 104, | |
340 | PPC_SPE_FSCR_REGNUM = 105, | |
341 | PPC_VR0_REGNUM = 106, | |
342 | PPC_VSCR_REGNUM = 138, | |
343 | PPC_VRSAVE_REGNUM = 139, | |
604c2f83 LM |
344 | PPC_VSR0_UPPER_REGNUM = 140, |
345 | PPC_VSR31_UPPER_REGNUM = 171, | |
7ca18ed6 EBM |
346 | PPC_PPR_REGNUM = 172, |
347 | PPC_DSCR_REGNUM = 173, | |
f2cf6173 | 348 | PPC_TAR_REGNUM = 174, |
232bfb86 EBM |
349 | |
350 | /* EBB registers. */ | |
351 | PPC_BESCR_REGNUM = 175, | |
352 | PPC_EBBHR_REGNUM = 176, | |
353 | PPC_EBBRR_REGNUM = 177, | |
354 | ||
355 | /* PMU registers. */ | |
356 | PPC_MMCR0_REGNUM = 178, | |
357 | PPC_MMCR2_REGNUM = 179, | |
358 | PPC_SIAR_REGNUM = 180, | |
359 | PPC_SDAR_REGNUM = 181, | |
360 | PPC_SIER_REGNUM = 182, | |
361 | ||
8d619c01 EBM |
362 | /* Hardware transactional memory registers. */ |
363 | PPC_TFHAR_REGNUM = 183, | |
364 | PPC_TEXASR_REGNUM = 184, | |
365 | PPC_TFIAR_REGNUM = 185, | |
366 | ||
367 | PPC_CR0_REGNUM = 186, | |
368 | PPC_CCR_REGNUM = 218, | |
369 | PPC_CXER_REGNUM = 219, | |
370 | PPC_CLR_REGNUM = 220, | |
371 | PPC_CCTR_REGNUM = 221, | |
372 | ||
373 | PPC_CF0_REGNUM = 222, | |
374 | PPC_CFPSCR_REGNUM = 254, | |
375 | ||
376 | PPC_CVR0_REGNUM = 255, | |
377 | PPC_CVSCR_REGNUM = 287, | |
378 | PPC_CVRSAVE_REGNUM = 288, | |
379 | ||
380 | PPC_CVSR0_UPPER_REGNUM = 289, | |
381 | ||
382 | PPC_CPPR_REGNUM = 321, | |
383 | PPC_CDSCR_REGNUM = 322, | |
384 | PPC_CTAR_REGNUM = 323, | |
7cc46491 DJ |
385 | PPC_NUM_REGS |
386 | }; | |
0ea0ec5f | 387 | |
0f068fb5 AH |
388 | /* Big enough to hold the size of the largest register in bytes. */ |
389 | #define PPC_MAX_REGISTER_SIZE 64 | |
390 | ||
232bfb86 EBM |
391 | #define PPC_IS_EBB_REGNUM(i) \ |
392 | ((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM) | |
393 | ||
394 | #define PPC_IS_PMU_REGNUM(i) \ | |
395 | ((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM) | |
396 | ||
8d619c01 EBM |
397 | #define PPC_IS_TMSPR_REGNUM(i) \ |
398 | ((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM) | |
399 | ||
400 | #define PPC_IS_CKPTGP_REGNUM(i) \ | |
401 | ((i) >= PPC_CR0_REGNUM && (i) <= PPC_CCTR_REGNUM) | |
402 | ||
403 | #define PPC_IS_CKPTFP_REGNUM(i) \ | |
404 | ((i) >= PPC_CF0_REGNUM && (i) <= PPC_CFPSCR_REGNUM) | |
405 | ||
406 | #define PPC_IS_CKPTVMX_REGNUM(i) \ | |
407 | ((i) >= PPC_CVR0_REGNUM && (i) <= PPC_CVRSAVE_REGNUM) | |
408 | ||
409 | #define PPC_IS_CKPTVSX_REGNUM(i) \ | |
410 | ((i) >= PPC_CVSR0_UPPER_REGNUM && (i) < (PPC_CVSR0_UPPER_REGNUM + 32)) | |
411 | ||
d78489bf AT |
412 | /* An instruction to match. */ |
413 | ||
414 | struct ppc_insn_pattern | |
415 | { | |
416 | unsigned int mask; /* mask the insn with this... */ | |
417 | unsigned int data; /* ...and see if it matches this. */ | |
418 | int optional; /* If non-zero, this insn may be absent. */ | |
419 | }; | |
420 | ||
845d4708 | 421 | extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc, |
7433498b | 422 | const struct ppc_insn_pattern *pattern, |
845d4708 | 423 | unsigned int *insns); |
d78489bf AT |
424 | extern CORE_ADDR ppc_insn_d_field (unsigned int insn); |
425 | ||
426 | extern CORE_ADDR ppc_insn_ds_field (unsigned int insn); | |
0ea0ec5f | 427 | |
b4cdae6f WW |
428 | extern int ppc_process_record (struct gdbarch *gdbarch, |
429 | struct regcache *regcache, CORE_ADDR addr); | |
430 | ||
a0c75879 MK |
431 | /* Instruction size. */ |
432 | #define PPC_INSN_SIZE 4 | |
433 | ||
0d1243d9 PG |
434 | /* Estimate for the maximum number of instrctions in a function epilogue. */ |
435 | #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52 | |
436 | ||
a0c75879 | 437 | #endif /* ppc-tdep.h */ |