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9aa1e687 | 1 | /* Target-dependent code for GDB, the GNU debugger. |
f9be684a | 2 | |
e2882c85 | 3 | Copyright (C) 2000-2018 Free Software Foundation, Inc. |
9aa1e687 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
9aa1e687 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
9aa1e687 | 19 | |
3a1c5313 AC |
20 | #ifndef PPC_TDEP_H |
21 | #define PPC_TDEP_H | |
22 | ||
da3331ec | 23 | struct gdbarch; |
3a1c5313 AC |
24 | struct frame_info; |
25 | struct value; | |
4a4b3fed | 26 | struct regcache; |
221c12ff | 27 | struct type; |
3a1c5313 | 28 | |
0df8b418 | 29 | /* From ppc-sysv-tdep.c ... */ |
05580c65 | 30 | enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch, |
6a3a010b | 31 | struct value *function, |
05580c65 AC |
32 | struct type *valtype, |
33 | struct regcache *regcache, | |
50fd1280 AC |
34 | gdb_byte *readbuf, |
35 | const gdb_byte *writebuf); | |
05580c65 | 36 | enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch, |
6a3a010b | 37 | struct value *function, |
05580c65 AC |
38 | struct type *valtype, |
39 | struct regcache *regcache, | |
50fd1280 AC |
40 | gdb_byte *readbuf, |
41 | const gdb_byte *writebuf); | |
77b2b6d4 | 42 | CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, |
7d9b040b | 43 | struct value *function, |
77b2b6d4 AC |
44 | struct regcache *regcache, |
45 | CORE_ADDR bp_addr, int nargs, | |
46 | struct value **args, CORE_ADDR sp, | |
47 | int struct_return, | |
48 | CORE_ADDR struct_addr); | |
8be9034a | 49 | CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, |
7d9b040b | 50 | struct value *function, |
8be9034a AC |
51 | struct regcache *regcache, |
52 | CORE_ADDR bp_addr, int nargs, | |
53 | struct value **args, CORE_ADDR sp, | |
54 | int struct_return, | |
55 | CORE_ADDR struct_addr); | |
05580c65 | 56 | enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch, |
6a3a010b | 57 | struct value *function, |
05580c65 AC |
58 | struct type *valtype, |
59 | struct regcache *regcache, | |
50fd1280 AC |
60 | gdb_byte *readbuf, |
61 | const gdb_byte *writebuf); | |
9aa1e687 | 62 | |
0df8b418 | 63 | /* From rs6000-tdep.c... */ |
be8626e0 | 64 | int altivec_register_p (struct gdbarch *gdbarch, int regno); |
604c2f83 | 65 | int vsx_register_p (struct gdbarch *gdbarch, int regno); |
be8626e0 | 66 | int spe_register_p (struct gdbarch *gdbarch, int regno); |
9aa1e687 | 67 | |
383f0f5b JB |
68 | /* Return non-zero if the architecture described by GDBARCH has |
69 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
70 | int ppc_floating_point_unit_p (struct gdbarch *gdbarch); |
71 | ||
06caf7d2 CES |
72 | /* Return non-zero if the architecture described by GDBARCH has |
73 | Altivec registers (vr0 --- vr31, vrsave and vscr). */ | |
74 | int ppc_altivec_support_p (struct gdbarch *gdbarch); | |
75 | ||
604c2f83 LM |
76 | /* Return non-zero if the architecture described by GDBARCH has |
77 | VSX registers (vsr0 --- vsr63). */ | |
78 | int vsx_support_p (struct gdbarch *gdbarch); | |
a0ff9e1a SM |
79 | std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence |
80 | (struct regcache *regcache); | |
4a7622d1 UW |
81 | |
82 | ||
d195bc9f MK |
83 | /* Register set description. */ |
84 | ||
85 | struct ppc_reg_offsets | |
86 | { | |
87 | /* General-purpose registers. */ | |
88 | int r0_offset; | |
f2db237a AM |
89 | int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */ |
90 | int xr_size; /* size for cr, xer, mq. */ | |
d195bc9f MK |
91 | int pc_offset; |
92 | int ps_offset; | |
93 | int cr_offset; | |
94 | int lr_offset; | |
95 | int ctr_offset; | |
96 | int xer_offset; | |
97 | int mq_offset; | |
98 | ||
99 | /* Floating-point registers. */ | |
100 | int f0_offset; | |
101 | int fpscr_offset; | |
f2db237a | 102 | int fpscr_size; |
d195bc9f MK |
103 | }; |
104 | ||
7284e1be UW |
105 | extern void ppc_supply_reg (struct regcache *regcache, int regnum, |
106 | const gdb_byte *regs, size_t offset, int regsize); | |
107 | ||
108 | extern void ppc_collect_reg (const struct regcache *regcache, int regnum, | |
109 | gdb_byte *regs, size_t offset, int regsize); | |
110 | ||
d195bc9f MK |
111 | /* Supply register REGNUM in the general-purpose register set REGSET |
112 | from the buffer specified by GREGS and LEN to register cache | |
113 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
114 | ||
115 | extern void ppc_supply_gregset (const struct regset *regset, | |
116 | struct regcache *regcache, | |
117 | int regnum, const void *gregs, size_t len); | |
118 | ||
119 | /* Supply register REGNUM in the floating-point register set REGSET | |
120 | from the buffer specified by FPREGS and LEN to register cache | |
121 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
122 | ||
123 | extern void ppc_supply_fpregset (const struct regset *regset, | |
124 | struct regcache *regcache, | |
125 | int regnum, const void *fpregs, size_t len); | |
126 | ||
06caf7d2 CES |
127 | /* Supply register REGNUM in the Altivec register set REGSET |
128 | from the buffer specified by VRREGS and LEN to register cache | |
129 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
130 | ||
131 | extern void ppc_supply_vrregset (const struct regset *regset, | |
132 | struct regcache *regcache, | |
133 | int regnum, const void *vrregs, size_t len); | |
134 | ||
604c2f83 LM |
135 | /* Supply register REGNUM in the VSX register set REGSET |
136 | from the buffer specified by VSXREGS and LEN to register cache | |
137 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
138 | ||
139 | extern void ppc_supply_vsxregset (const struct regset *regset, | |
140 | struct regcache *regcache, | |
141 | int regnum, const void *vsxregs, size_t len); | |
142 | ||
d195bc9f | 143 | /* Collect register REGNUM in the general-purpose register set |
0df8b418 | 144 | REGSET, from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
145 | GREGS and LEN. If REGNUM is -1, do this for all registers in |
146 | REGSET. */ | |
147 | ||
148 | extern void ppc_collect_gregset (const struct regset *regset, | |
149 | const struct regcache *regcache, | |
150 | int regnum, void *gregs, size_t len); | |
151 | ||
152 | /* Collect register REGNUM in the floating-point register set | |
0df8b418 | 153 | REGSET, from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
154 | FPREGS and LEN. If REGNUM is -1, do this for all registers in |
155 | REGSET. */ | |
156 | ||
157 | extern void ppc_collect_fpregset (const struct regset *regset, | |
158 | const struct regcache *regcache, | |
159 | int regnum, void *fpregs, size_t len); | |
160 | ||
06caf7d2 CES |
161 | /* Collect register REGNUM in the Altivec register set |
162 | REGSET from register cache REGCACHE into the buffer specified by | |
163 | VRREGS and LEN. If REGNUM is -1, do this for all registers in | |
164 | REGSET. */ | |
165 | ||
166 | extern void ppc_collect_vrregset (const struct regset *regset, | |
167 | const struct regcache *regcache, | |
168 | int regnum, void *vrregs, size_t len); | |
169 | ||
604c2f83 LM |
170 | /* Collect register REGNUM in the VSX register set |
171 | REGSET from register cache REGCACHE into the buffer specified by | |
172 | VSXREGS and LEN. If REGNUM is -1, do this for all registers in | |
173 | REGSET. */ | |
174 | ||
175 | extern void ppc_collect_vsxregset (const struct regset *regset, | |
176 | const struct regcache *regcache, | |
177 | int regnum, void *vsxregs, size_t len); | |
178 | ||
0df8b418 | 179 | /* Private data that this module attaches to struct gdbarch. */ |
2188cbdd | 180 | |
cd453cd0 UW |
181 | /* ELF ABI version used by the inferior. */ |
182 | enum powerpc_elf_abi | |
183 | { | |
184 | POWERPC_ELF_AUTO, | |
185 | POWERPC_ELF_V1, | |
186 | POWERPC_ELF_V2, | |
187 | POWERPC_ELF_LAST | |
188 | }; | |
189 | ||
55eddb0f DJ |
190 | /* Vector ABI used by the inferior. */ |
191 | enum powerpc_vector_abi | |
192 | { | |
193 | POWERPC_VEC_AUTO, | |
194 | POWERPC_VEC_GENERIC, | |
195 | POWERPC_VEC_ALTIVEC, | |
196 | POWERPC_VEC_SPE, | |
197 | POWERPC_VEC_LAST | |
198 | }; | |
199 | ||
ed0f4273 UW |
200 | /* long double ABI version used by the inferior. */ |
201 | enum powerpc_long_double_abi | |
202 | { | |
203 | POWERPC_LONG_DOUBLE_AUTO, | |
204 | POWERPC_LONG_DOUBLE_IBM128, | |
205 | POWERPC_LONG_DOUBLE_IEEE128, | |
206 | POWERPC_LONG_DOUBLE_LAST | |
207 | }; | |
208 | ||
2188cbdd EZ |
209 | struct gdbarch_tdep |
210 | { | |
55eddb0f DJ |
211 | int wordsize; /* Size in bytes of fixed-point word. */ |
212 | int soft_float; /* Avoid FP registers for arguments? */ | |
213 | ||
cd453cd0 UW |
214 | enum powerpc_elf_abi elf_abi; /* ELF ABI version. */ |
215 | ||
ed0f4273 UW |
216 | /* Format to use for the "long double" data type. */ |
217 | enum powerpc_long_double_abi long_double_abi; | |
218 | ||
55eddb0f DJ |
219 | /* How to pass vector arguments. Never set to AUTO or LAST. */ |
220 | enum powerpc_vector_abi vector_abi; | |
221 | ||
2188cbdd | 222 | int ppc_gp0_regnum; /* GPR register 0 */ |
2188cbdd EZ |
223 | int ppc_toc_regnum; /* TOC register */ |
224 | int ppc_ps_regnum; /* Processor (or machine) status (%msr) */ | |
225 | int ppc_cr_regnum; /* Condition register */ | |
226 | int ppc_lr_regnum; /* Link register */ | |
227 | int ppc_ctr_regnum; /* Count register */ | |
228 | int ppc_xer_regnum; /* Integer exception register */ | |
383f0f5b | 229 | |
826d5376 PG |
230 | /* Not all PPC and RS6000 variants will have the registers |
231 | represented below. A -1 is used to indicate that the register | |
232 | is not present in this variant. */ | |
233 | ||
234 | /* Floating-point registers. */ | |
0df8b418 MS |
235 | int ppc_fp0_regnum; /* Floating-point register 0. */ |
236 | int ppc_fpscr_regnum; /* fp status and condition register. */ | |
826d5376 | 237 | |
826d5376 PG |
238 | /* Multiplier-Quotient Register (older POWER architectures only). */ |
239 | int ppc_mq_regnum; | |
f86a7158 | 240 | |
604c2f83 LM |
241 | /* POWER7 VSX registers. */ |
242 | int ppc_vsr0_regnum; /* First VSX register. */ | |
243 | int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */ | |
244 | int ppc_efpr0_regnum; /* First Extended FP register. */ | |
245 | ||
826d5376 | 246 | /* Altivec registers. */ |
0df8b418 MS |
247 | int ppc_vr0_regnum; /* First AltiVec register. */ |
248 | int ppc_vrsave_regnum; /* Last AltiVec register. */ | |
826d5376 PG |
249 | |
250 | /* SPE registers. */ | |
0df8b418 MS |
251 | int ppc_ev0_upper_regnum; /* First GPR upper half register. */ |
252 | int ppc_ev0_regnum; /* First ev register. */ | |
253 | int ppc_acc_regnum; /* SPE 'acc' register. */ | |
254 | int ppc_spefscr_regnum; /* SPE 'spefscr' register. */ | |
826d5376 | 255 | |
f949c649 TJB |
256 | /* Decimal 128 registers. */ |
257 | int ppc_dl0_regnum; /* First Decimal128 argument register pair. */ | |
258 | ||
826d5376 PG |
259 | /* Offset to ABI specific location where link register is saved. */ |
260 | int lr_frame_offset; | |
9f643768 JB |
261 | |
262 | /* An array of integers, such that sim_regno[I] is the simulator | |
263 | register number for GDB register number I, or -1 if the | |
264 | simulator does not implement that register. */ | |
265 | int *sim_regno; | |
6f7f3f0d | 266 | |
794ac428 UW |
267 | /* ISA-specific types. */ |
268 | struct type *ppc_builtin_type_vec64; | |
604c2f83 | 269 | struct type *ppc_builtin_type_vec128; |
b4cdae6f WW |
270 | |
271 | int (*ppc_syscall_record) (struct regcache *regcache); | |
2188cbdd | 272 | }; |
3a1c5313 | 273 | |
b967e06f JB |
274 | |
275 | /* Constants for register set sizes. */ | |
276 | enum | |
277 | { | |
604c2f83 LM |
278 | ppc_num_gprs = 32, /* 32 general-purpose registers. */ |
279 | ppc_num_fprs = 32, /* 32 floating-point registers. */ | |
280 | ppc_num_srs = 16, /* 16 segment registers. */ | |
281 | ppc_num_vrs = 32, /* 32 Altivec vector registers. */ | |
282 | ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */ | |
283 | ppc_num_vsrs = 64, /* 64 VSX vector registers. */ | |
284 | ppc_num_efprs = 32 /* 32 Extended FP registers. */ | |
b967e06f JB |
285 | }; |
286 | ||
0ea0ec5f | 287 | |
7cc46491 DJ |
288 | /* Register number constants. These are GDB internal register |
289 | numbers; they are not used for the simulator or remote targets. | |
290 | Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given | |
291 | numbers above PPC_NUM_REGS. So are segment registers and other | |
292 | target-defined registers. */ | |
293 | enum { | |
294 | PPC_R0_REGNUM = 0, | |
295 | PPC_F0_REGNUM = 32, | |
296 | PPC_PC_REGNUM = 64, | |
297 | PPC_MSR_REGNUM = 65, | |
298 | PPC_CR_REGNUM = 66, | |
299 | PPC_LR_REGNUM = 67, | |
300 | PPC_CTR_REGNUM = 68, | |
301 | PPC_XER_REGNUM = 69, | |
302 | PPC_FPSCR_REGNUM = 70, | |
303 | PPC_MQ_REGNUM = 71, | |
304 | PPC_SPE_UPPER_GP0_REGNUM = 72, | |
305 | PPC_SPE_ACC_REGNUM = 104, | |
306 | PPC_SPE_FSCR_REGNUM = 105, | |
307 | PPC_VR0_REGNUM = 106, | |
308 | PPC_VSCR_REGNUM = 138, | |
309 | PPC_VRSAVE_REGNUM = 139, | |
604c2f83 LM |
310 | PPC_VSR0_UPPER_REGNUM = 140, |
311 | PPC_VSR31_UPPER_REGNUM = 171, | |
7cc46491 DJ |
312 | PPC_NUM_REGS |
313 | }; | |
0ea0ec5f | 314 | |
0f068fb5 AH |
315 | /* Big enough to hold the size of the largest register in bytes. */ |
316 | #define PPC_MAX_REGISTER_SIZE 64 | |
317 | ||
d78489bf AT |
318 | /* An instruction to match. */ |
319 | ||
320 | struct ppc_insn_pattern | |
321 | { | |
322 | unsigned int mask; /* mask the insn with this... */ | |
323 | unsigned int data; /* ...and see if it matches this. */ | |
324 | int optional; /* If non-zero, this insn may be absent. */ | |
325 | }; | |
326 | ||
845d4708 | 327 | extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc, |
7433498b | 328 | const struct ppc_insn_pattern *pattern, |
845d4708 | 329 | unsigned int *insns); |
d78489bf AT |
330 | extern CORE_ADDR ppc_insn_d_field (unsigned int insn); |
331 | ||
332 | extern CORE_ADDR ppc_insn_ds_field (unsigned int insn); | |
0ea0ec5f | 333 | |
b4cdae6f WW |
334 | extern int ppc_process_record (struct gdbarch *gdbarch, |
335 | struct regcache *regcache, CORE_ADDR addr); | |
336 | ||
a0c75879 MK |
337 | /* Instruction size. */ |
338 | #define PPC_INSN_SIZE 4 | |
339 | ||
0d1243d9 PG |
340 | /* Estimate for the maximum number of instrctions in a function epilogue. */ |
341 | #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52 | |
342 | ||
a0c75879 | 343 | #endif /* ppc-tdep.h */ |