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dbbb1059 AB |
1 | /* Target-dependent code for the RISC-V architecture, for GDB. |
2 | ||
3 | Copyright (C) 2018 Free Software Foundation, Inc. | |
4 | ||
dbbb1059 AB |
5 | This file is part of GDB. |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
23 | #include "symtab.h" | |
24 | #include "value.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "language.h" | |
27 | #include "gdbcore.h" | |
28 | #include "symfile.h" | |
29 | #include "objfiles.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "target.h" | |
32 | #include "arch-utils.h" | |
33 | #include "regcache.h" | |
34 | #include "osabi.h" | |
35 | #include "riscv-tdep.h" | |
36 | #include "block.h" | |
37 | #include "reggroups.h" | |
38 | #include "opcode/riscv.h" | |
39 | #include "elf/riscv.h" | |
40 | #include "elf-bfd.h" | |
41 | #include "symcat.h" | |
42 | #include "dis-asm.h" | |
43 | #include "frame-unwind.h" | |
44 | #include "frame-base.h" | |
45 | #include "trad-frame.h" | |
46 | #include "infcall.h" | |
47 | #include "floatformat.h" | |
48 | #include "remote.h" | |
49 | #include "target-descriptions.h" | |
50 | #include "dwarf2-frame.h" | |
51 | #include "user-regs.h" | |
52 | #include "valprint.h" | |
53 | #include "common-defs.h" | |
54 | #include "opcode/riscv-opc.h" | |
55 | #include "cli/cli-decode.h" | |
56 | #include "observer.h" | |
57 | ||
58 | /* The stack must be 16-byte aligned. */ | |
59 | #define SP_ALIGNMENT 16 | |
60 | ||
61 | /* Forward declarations. */ | |
62 | static bool riscv_has_feature (struct gdbarch *gdbarch, char feature); | |
63 | struct riscv_inferior_data; | |
64 | struct riscv_inferior_data * riscv_inferior_data (struct inferior *const inf); | |
65 | ||
66 | /* Define a series of is_XXX_insn functions to check if the value INSN | |
67 | is an instance of instruction XXX. */ | |
68 | #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ | |
69 | static inline bool is_ ## INSN_NAME ## _insn (long insn) \ | |
70 | { \ | |
71 | return (insn & INSN_MASK) == INSN_MATCH; \ | |
72 | } | |
73 | #include "opcode/riscv-opc.h" | |
74 | #undef DECLARE_INSN | |
75 | ||
76 | /* Per inferior information for RiscV. */ | |
77 | ||
78 | struct riscv_inferior_data | |
79 | { | |
80 | /* True when MISA_VALUE is valid, otherwise false. */ | |
81 | bool misa_read; | |
82 | ||
83 | /* If MISA_READ is true then MISA_VALUE holds the value of the MISA | |
84 | register read from the target. */ | |
85 | uint32_t misa_value; | |
86 | }; | |
87 | ||
88 | /* Key created when the RiscV per-inferior data is registered. */ | |
89 | ||
90 | static const struct inferior_data *riscv_inferior_data_reg; | |
91 | ||
92 | /* Architectural name for core registers. */ | |
93 | ||
94 | static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] = | |
95 | { | |
96 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
97 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
98 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
99 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", | |
100 | "pc", | |
101 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
102 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
103 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
104 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
105 | }; | |
106 | ||
107 | /* Maps "pretty" register names onto their GDB register number. */ | |
108 | ||
109 | struct register_alias | |
110 | { | |
111 | /* The register alias. Usually more descriptive than the | |
112 | architectural name of the register. */ | |
113 | const char *name; | |
114 | ||
115 | /* The GDB register number. */ | |
116 | int regnum; | |
117 | }; | |
118 | ||
119 | /* Table of register aliases. */ | |
120 | ||
121 | static const struct register_alias riscv_register_aliases[] = | |
122 | { | |
123 | { "zero", 0 }, | |
124 | { "ra", 1 }, | |
125 | { "sp", 2 }, | |
126 | { "gp", 3 }, | |
127 | { "tp", 4 }, | |
128 | { "t0", 5 }, | |
129 | { "t1", 6 }, | |
130 | { "t2", 7 }, | |
131 | { "fp", 8 }, | |
132 | { "s0", 8 }, | |
133 | { "s1", 9 }, | |
134 | { "a0", 10 }, | |
135 | { "a1", 11 }, | |
136 | { "a2", 12 }, | |
137 | { "a3", 13 }, | |
138 | { "a4", 14 }, | |
139 | { "a5", 15 }, | |
140 | { "a6", 16 }, | |
141 | { "a7", 17 }, | |
142 | { "s2", 18 }, | |
143 | { "s3", 19 }, | |
144 | { "s4", 20 }, | |
145 | { "s5", 21 }, | |
146 | { "s6", 22 }, | |
147 | { "s7", 23 }, | |
148 | { "s8", 24 }, | |
149 | { "s9", 25 }, | |
150 | { "s10", 26 }, | |
151 | { "s11", 27 }, | |
152 | { "t3", 28 }, | |
153 | { "t4", 29 }, | |
154 | { "t5", 30 }, | |
155 | { "t6", 31 }, | |
156 | /* pc is 32. */ | |
157 | { "ft0", 33 }, | |
158 | { "ft1", 34 }, | |
159 | { "ft2", 35 }, | |
160 | { "ft3", 36 }, | |
161 | { "ft4", 37 }, | |
162 | { "ft5", 38 }, | |
163 | { "ft6", 39 }, | |
164 | { "ft7", 40 }, | |
165 | { "fs0", 41 }, | |
166 | { "fs1", 42 }, | |
167 | { "fa0", 43 }, | |
168 | { "fa1", 44 }, | |
169 | { "fa2", 45 }, | |
170 | { "fa3", 46 }, | |
171 | { "fa4", 47 }, | |
172 | { "fa5", 48 }, | |
173 | { "fa6", 49 }, | |
174 | { "fa7", 50 }, | |
175 | { "fs2", 51 }, | |
176 | { "fs3", 52 }, | |
177 | { "fs4", 53 }, | |
178 | { "fs5", 54 }, | |
179 | { "fs6", 55 }, | |
180 | { "fs7", 56 }, | |
181 | { "fs8", 57 }, | |
182 | { "fs9", 58 }, | |
183 | { "fs10", 59 }, | |
184 | { "fs11", 60 }, | |
185 | { "ft8", 61 }, | |
186 | { "ft9", 62 }, | |
187 | { "ft10", 63 }, | |
188 | { "ft11", 64 }, | |
189 | #define DECLARE_CSR(name, num) { #name, (num) + 65 }, | |
190 | #include "opcode/riscv-opc.h" | |
191 | #undef DECLARE_CSR | |
192 | }; | |
193 | ||
194 | /* Controls whether we place compressed breakpoints or not. When in auto | |
195 | mode GDB tries to determine if the target supports compressed | |
196 | breakpoints, and uses them if it does. */ | |
197 | ||
198 | static enum auto_boolean use_compressed_breakpoints; | |
199 | ||
200 | /* The show callback for 'show riscv use-compressed-breakpoints'. */ | |
201 | ||
202 | static void | |
203 | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, | |
204 | struct cmd_list_element *c, | |
205 | const char *value) | |
206 | { | |
207 | const char *additional_info; | |
208 | struct gdbarch *gdbarch = target_gdbarch (); | |
209 | ||
210 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) | |
211 | if (riscv_has_feature (gdbarch, 'C')) | |
212 | additional_info = _(" (currently on)"); | |
213 | else | |
214 | additional_info = _(" (currently off)"); | |
215 | else | |
216 | additional_info = ""; | |
217 | ||
218 | fprintf_filtered (file, | |
219 | _("Debugger's use of compressed breakpoints is set " | |
220 | "to %s%s.\n"), value, additional_info); | |
221 | } | |
222 | ||
223 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
224 | ||
225 | static struct cmd_list_element *setriscvcmdlist = NULL; | |
226 | static struct cmd_list_element *showriscvcmdlist = NULL; | |
227 | ||
228 | /* The show callback for the 'show riscv' prefix command. */ | |
229 | ||
230 | static void | |
231 | show_riscv_command (const char *args, int from_tty) | |
232 | { | |
233 | help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout); | |
234 | } | |
235 | ||
236 | /* The set callback for the 'set riscv' prefix command. */ | |
237 | ||
238 | static void | |
239 | set_riscv_command (const char *args, int from_tty) | |
240 | { | |
241 | printf_unfiltered | |
242 | (_("\"set riscv\" must be followed by an appropriate subcommand.\n")); | |
243 | help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout); | |
244 | } | |
245 | ||
246 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
247 | ||
248 | static struct cmd_list_element *setdebugriscvcmdlist = NULL; | |
249 | static struct cmd_list_element *showdebugriscvcmdlist = NULL; | |
250 | ||
251 | /* The show callback for the 'show debug riscv' prefix command. */ | |
252 | ||
253 | static void | |
254 | show_debug_riscv_command (const char *args, int from_tty) | |
255 | { | |
256 | help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout); | |
257 | } | |
258 | ||
259 | /* The set callback for the 'set debug riscv' prefix command. */ | |
260 | ||
261 | static void | |
262 | set_debug_riscv_command (const char *args, int from_tty) | |
263 | { | |
264 | printf_unfiltered | |
265 | (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n")); | |
266 | help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout); | |
267 | } | |
268 | ||
269 | /* The show callback for all 'show debug riscv VARNAME' variables. */ | |
270 | ||
271 | static void | |
272 | show_riscv_debug_variable (struct ui_file *file, int from_tty, | |
273 | struct cmd_list_element *c, | |
274 | const char *value) | |
275 | { | |
276 | fprintf_filtered (file, | |
277 | _("RiscV debug variable `%s' is set to: %s\n"), | |
278 | c->name, value); | |
279 | } | |
280 | ||
281 | /* When this is set to non-zero debugging information about inferior calls | |
282 | will be printed. */ | |
283 | ||
284 | static unsigned int riscv_debug_infcall = 0; | |
285 | ||
286 | /* Read the MISA register from the target. The register will only be read | |
287 | once, and the value read will be cached. If the register can't be read | |
288 | from the target then a default value (0) will be returned. If the | |
289 | pointer READ_P is not null, then the bool pointed to is updated to | |
290 | indicate if the value returned was read from the target (true) or is the | |
291 | default (false). */ | |
292 | ||
293 | static uint32_t | |
294 | riscv_read_misa_reg (bool *read_p) | |
295 | { | |
296 | struct riscv_inferior_data *inf_data | |
297 | = riscv_inferior_data (current_inferior ()); | |
298 | ||
299 | if (!inf_data->misa_read && target_has_registers) | |
300 | { | |
301 | uint32_t value = 0; | |
302 | struct frame_info *frame = get_current_frame (); | |
303 | ||
304 | TRY | |
305 | { | |
306 | value = get_frame_register_unsigned (frame, RISCV_CSR_MISA_REGNUM); | |
307 | } | |
308 | CATCH (ex, RETURN_MASK_ERROR) | |
309 | { | |
310 | /* Old cores might have MISA located at a different offset. */ | |
311 | value = get_frame_register_unsigned (frame, | |
312 | RISCV_CSR_LEGACY_MISA_REGNUM); | |
313 | } | |
314 | END_CATCH | |
315 | ||
316 | inf_data->misa_read = true; | |
317 | inf_data->misa_value = value; | |
318 | } | |
319 | ||
320 | if (read_p != nullptr) | |
321 | *read_p = inf_data->misa_read; | |
322 | ||
323 | return inf_data->misa_value; | |
324 | } | |
325 | ||
326 | /* Return true if FEATURE is available for the architecture GDBARCH. The | |
327 | FEATURE should be one of the single character feature codes described in | |
328 | the RiscV ISA manual, these are between 'A' and 'Z'. */ | |
329 | ||
330 | static bool | |
331 | riscv_has_feature (struct gdbarch *gdbarch, char feature) | |
332 | { | |
333 | bool have_read_misa = false; | |
334 | uint32_t misa; | |
335 | ||
336 | gdb_assert (feature >= 'A' && feature <= 'Z'); | |
337 | ||
338 | /* It would be nice to always check with the real target where possible, | |
339 | however, for compressed instructions this is a bad idea. | |
340 | ||
341 | The call to `set_gdbarch_decr_pc_after_break' is made just once per | |
342 | GDBARCH and we decide at that point if we should decrement by 2 or 4 | |
343 | bytes based on whether the BFD has compressed instruction support or | |
344 | not. | |
345 | ||
346 | If the BFD was not compiled with compressed instruction support, but we | |
347 | are running on a target with compressed instructions then we might | |
348 | place a 4-byte breakpoint, then decrement the $pc by 2 bytes leading to | |
349 | confusion. | |
350 | ||
351 | It's safer if we just make decisions about compressed instruction | |
352 | support based on the BFD. */ | |
353 | if (feature != 'C') | |
354 | misa = riscv_read_misa_reg (&have_read_misa); | |
355 | if (!have_read_misa || misa == 0) | |
356 | misa = gdbarch_tdep (gdbarch)->core_features; | |
357 | ||
358 | return (misa & (1 << (feature - 'A'))) != 0; | |
359 | } | |
360 | ||
361 | /* Return the width in bytes of the general purpose registers for GDBARCH. | |
362 | Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or | |
363 | RV128. */ | |
364 | ||
365 | static int | |
366 | riscv_isa_xlen (struct gdbarch *gdbarch) | |
367 | { | |
368 | switch (gdbarch_tdep (gdbarch)->abi.fields.base_len) | |
369 | { | |
370 | default: | |
371 | warning (_("unknown xlen size, assuming 4 bytes")); | |
372 | case 1: | |
373 | return 4; | |
374 | case 2: | |
375 | return 8; | |
376 | case 3: | |
377 | return 16; | |
378 | } | |
379 | } | |
380 | ||
381 | /* Return the width in bytes of the floating point registers for GDBARCH. | |
382 | If this architecture has no floating point registers, then return 0. | |
383 | Possible values are 4, 8, or 16 for depending on which of single, double | |
384 | or quad floating point support is available. */ | |
385 | ||
386 | static int | |
387 | riscv_isa_flen (struct gdbarch *gdbarch) | |
388 | { | |
389 | if (riscv_has_feature (gdbarch, 'Q')) | |
390 | return 16; | |
391 | else if (riscv_has_feature (gdbarch, 'D')) | |
392 | return 8; | |
393 | else if (riscv_has_feature (gdbarch, 'F')) | |
394 | return 4; | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | /* Return true if the target for GDBARCH has floating point hardware. */ | |
400 | ||
401 | static bool | |
402 | riscv_has_fp_regs (struct gdbarch *gdbarch) | |
403 | { | |
404 | return (riscv_isa_flen (gdbarch) > 0); | |
405 | } | |
406 | ||
407 | /* Return true if GDBARCH is using any of the floating point hardware ABIs. */ | |
408 | ||
409 | static bool | |
410 | riscv_has_fp_abi (struct gdbarch *gdbarch) | |
411 | { | |
412 | return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0); | |
413 | } | |
414 | ||
415 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ | |
416 | ||
417 | static int | |
418 | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
419 | { | |
420 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) | |
421 | { | |
422 | if (riscv_has_feature (gdbarch, 'C')) | |
423 | return 2; | |
424 | else | |
425 | return 4; | |
426 | } | |
427 | else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) | |
428 | return 2; | |
429 | else | |
430 | return 4; | |
431 | } | |
432 | ||
433 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ | |
434 | ||
435 | static const gdb_byte * | |
436 | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
437 | { | |
438 | static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, }; | |
439 | static const gdb_byte c_ebreak[] = { 0x02, 0x90 }; | |
440 | ||
441 | *size = kind; | |
442 | switch (kind) | |
443 | { | |
444 | case 2: | |
445 | return c_ebreak; | |
446 | case 4: | |
447 | return ebreak; | |
448 | default: | |
449 | gdb_assert_not_reached ("unhandled breakpoint kind"); | |
450 | } | |
451 | } | |
452 | ||
453 | /* Callback function for user_reg_add. */ | |
454 | ||
455 | static struct value * | |
456 | value_of_riscv_user_reg (struct frame_info *frame, const void *baton) | |
457 | { | |
458 | const int *reg_p = (const int *) baton; | |
459 | return value_of_register (*reg_p, frame); | |
460 | } | |
461 | ||
462 | /* Implement the register_name gdbarch method. */ | |
463 | ||
464 | static const char * | |
465 | riscv_register_name (struct gdbarch *gdbarch, int regnum) | |
466 | { | |
dbbb1059 AB |
467 | /* Prefer to use the alias. */ |
468 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM) | |
469 | { | |
470 | int i; | |
471 | ||
472 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) | |
473 | if (regnum == riscv_register_aliases[i].regnum) | |
474 | return riscv_register_aliases[i].name; | |
475 | } | |
476 | ||
477 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) | |
478 | return riscv_gdb_reg_names[regnum]; | |
479 | ||
480 | if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM) | |
481 | { | |
482 | static char buf[20]; | |
483 | ||
484 | sprintf (buf, "csr%d", regnum - RISCV_FIRST_CSR_REGNUM); | |
485 | return buf; | |
486 | } | |
487 | ||
488 | if (regnum == RISCV_PRIV_REGNUM) | |
489 | return "priv"; | |
490 | ||
491 | return NULL; | |
492 | } | |
493 | ||
dbbb1059 AB |
494 | /* Implement the register_type gdbarch method. */ |
495 | ||
496 | static struct type * | |
497 | riscv_register_type (struct gdbarch *gdbarch, int regnum) | |
498 | { | |
499 | int regsize; | |
500 | ||
501 | if (regnum < RISCV_FIRST_FP_REGNUM) | |
502 | { | |
503 | if (regnum == gdbarch_pc_regnum (gdbarch) | |
504 | || regnum == RISCV_RA_REGNUM) | |
505 | return builtin_type (gdbarch)->builtin_func_ptr; | |
506 | ||
507 | if (regnum == RISCV_FP_REGNUM | |
508 | || regnum == RISCV_SP_REGNUM | |
509 | || regnum == RISCV_GP_REGNUM | |
510 | || regnum == RISCV_TP_REGNUM) | |
511 | return builtin_type (gdbarch)->builtin_data_ptr; | |
512 | ||
513 | /* Remaining GPRs vary in size based on the current ISA. */ | |
514 | regsize = riscv_isa_xlen (gdbarch); | |
515 | switch (regsize) | |
516 | { | |
517 | case 4: | |
518 | return builtin_type (gdbarch)->builtin_uint32; | |
519 | case 8: | |
520 | return builtin_type (gdbarch)->builtin_uint64; | |
521 | case 16: | |
522 | return builtin_type (gdbarch)->builtin_uint128; | |
523 | default: | |
524 | internal_error (__FILE__, __LINE__, | |
525 | _("unknown isa regsize %i"), regsize); | |
526 | } | |
527 | } | |
528 | else if (regnum <= RISCV_LAST_FP_REGNUM) | |
529 | { | |
530 | regsize = riscv_isa_xlen (gdbarch); | |
531 | switch (regsize) | |
532 | { | |
533 | case 4: | |
534 | return builtin_type (gdbarch)->builtin_float; | |
535 | case 8: | |
536 | return builtin_type (gdbarch)->builtin_double; | |
537 | case 16: | |
538 | return builtin_type (gdbarch)->builtin_long_double; | |
539 | default: | |
540 | internal_error (__FILE__, __LINE__, | |
541 | _("unknown isa regsize %i"), regsize); | |
542 | } | |
543 | } | |
544 | else if (regnum == RISCV_PRIV_REGNUM) | |
545 | return builtin_type (gdbarch)->builtin_int8; | |
546 | else | |
547 | { | |
548 | if (regnum == RISCV_CSR_FFLAGS_REGNUM | |
549 | || regnum == RISCV_CSR_FRM_REGNUM | |
550 | || regnum == RISCV_CSR_FCSR_REGNUM) | |
551 | return builtin_type (gdbarch)->builtin_int32; | |
552 | ||
553 | regsize = riscv_isa_xlen (gdbarch); | |
554 | switch (regsize) | |
555 | { | |
556 | case 4: | |
557 | return builtin_type (gdbarch)->builtin_int32; | |
558 | case 8: | |
559 | return builtin_type (gdbarch)->builtin_int64; | |
560 | case 16: | |
561 | return builtin_type (gdbarch)->builtin_int128; | |
562 | default: | |
563 | internal_error (__FILE__, __LINE__, | |
564 | _("unknown isa regsize %i"), regsize); | |
565 | } | |
566 | } | |
567 | } | |
568 | ||
569 | /* Helper for riscv_print_registers_info, prints info for a single register | |
570 | REGNUM. */ | |
571 | ||
572 | static void | |
573 | riscv_print_one_register_info (struct gdbarch *gdbarch, | |
574 | struct ui_file *file, | |
575 | struct frame_info *frame, | |
576 | int regnum) | |
577 | { | |
578 | const char *name = gdbarch_register_name (gdbarch, regnum); | |
579 | struct value *val = value_of_register (regnum, frame); | |
580 | struct type *regtype = value_type (val); | |
581 | int print_raw_format; | |
582 | enum tab_stops { value_column_1 = 15 }; | |
583 | ||
584 | fputs_filtered (name, file); | |
585 | print_spaces_filtered (value_column_1 - strlen (name), file); | |
586 | ||
587 | print_raw_format = (value_entirely_available (val) | |
588 | && !value_optimized_out (val)); | |
589 | ||
590 | if (TYPE_CODE (regtype) == TYPE_CODE_FLT) | |
591 | { | |
592 | struct value_print_options opts; | |
593 | const gdb_byte *valaddr = value_contents_for_printing (val); | |
594 | enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype)); | |
595 | ||
596 | get_user_print_options (&opts); | |
597 | opts.deref_ref = 1; | |
598 | ||
599 | val_print (regtype, | |
600 | value_embedded_offset (val), 0, | |
601 | file, 0, val, &opts, current_language); | |
602 | ||
603 | if (print_raw_format) | |
604 | { | |
605 | fprintf_filtered (file, "\t(raw "); | |
606 | print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order, | |
607 | true); | |
608 | fprintf_filtered (file, ")"); | |
609 | } | |
610 | } | |
611 | else | |
612 | { | |
613 | struct value_print_options opts; | |
614 | ||
615 | /* Print the register in hex. */ | |
616 | get_formatted_print_options (&opts, 'x'); | |
617 | opts.deref_ref = 1; | |
618 | val_print (regtype, | |
619 | value_embedded_offset (val), 0, | |
620 | file, 0, val, &opts, current_language); | |
621 | ||
622 | if (print_raw_format) | |
623 | { | |
624 | if (regnum == RISCV_CSR_MSTATUS_REGNUM) | |
625 | { | |
626 | LONGEST d; | |
627 | int size = register_size (gdbarch, regnum); | |
628 | unsigned xlen; | |
629 | ||
630 | d = value_as_long (val); | |
631 | xlen = size * 4; | |
632 | fprintf_filtered (file, | |
633 | "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " | |
634 | "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " | |
635 | "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X", | |
636 | (int) ((d >> (xlen - 1)) & 0x1), | |
637 | (int) ((d >> 24) & 0x1f), | |
638 | (int) ((d >> 19) & 0x1), | |
639 | (int) ((d >> 18) & 0x1), | |
640 | (int) ((d >> 17) & 0x1), | |
641 | (int) ((d >> 15) & 0x3), | |
642 | (int) ((d >> 13) & 0x3), | |
643 | (int) ((d >> 11) & 0x3), | |
644 | (int) ((d >> 9) & 0x3), | |
645 | (int) ((d >> 8) & 0x1), | |
646 | (int) ((d >> 7) & 0x1), | |
647 | (int) ((d >> 6) & 0x1), | |
648 | (int) ((d >> 5) & 0x1), | |
649 | (int) ((d >> 4) & 0x1), | |
650 | (int) ((d >> 3) & 0x1), | |
651 | (int) ((d >> 2) & 0x1), | |
652 | (int) ((d >> 1) & 0x1), | |
653 | (int) ((d >> 0) & 0x1)); | |
654 | } | |
655 | else if (regnum == RISCV_CSR_MISA_REGNUM) | |
656 | { | |
657 | int base; | |
658 | unsigned xlen, i; | |
659 | LONGEST d; | |
660 | ||
661 | d = value_as_long (val); | |
662 | base = d >> 30; | |
663 | xlen = 16; | |
664 | ||
665 | for (; base > 0; base--) | |
666 | xlen *= 2; | |
667 | fprintf_filtered (file, "\tRV%d", xlen); | |
668 | ||
669 | for (i = 0; i < 26; i++) | |
670 | { | |
671 | if (d & (1 << i)) | |
672 | fprintf_filtered (file, "%c", 'A' + i); | |
673 | } | |
674 | } | |
675 | else if (regnum == RISCV_CSR_FCSR_REGNUM | |
676 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
677 | || regnum == RISCV_CSR_FRM_REGNUM) | |
678 | { | |
679 | LONGEST d; | |
680 | ||
681 | d = value_as_long (val); | |
682 | ||
683 | fprintf_filtered (file, "\t"); | |
684 | if (regnum != RISCV_CSR_FRM_REGNUM) | |
685 | fprintf_filtered (file, | |
686 | "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d", | |
687 | (int) ((d >> 5) & 0x7), | |
688 | (int) ((d >> 4) & 0x1), | |
689 | (int) ((d >> 3) & 0x1), | |
690 | (int) ((d >> 2) & 0x1), | |
691 | (int) ((d >> 1) & 0x1), | |
692 | (int) ((d >> 0) & 0x1)); | |
693 | ||
694 | if (regnum != RISCV_CSR_FFLAGS_REGNUM) | |
695 | { | |
696 | static const char * const sfrm[] = | |
697 | { | |
698 | "RNE (round to nearest; ties to even)", | |
699 | "RTZ (Round towards zero)", | |
700 | "RDN (Round down towards -INF)", | |
701 | "RUP (Round up towards +INF)", | |
702 | "RMM (Round to nearest; ties to max magnitude)", | |
703 | "INVALID[5]", | |
704 | "INVALID[6]", | |
705 | "dynamic rounding mode", | |
706 | }; | |
707 | int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) | |
708 | ? (d >> 5) : d) & 0x3; | |
709 | ||
710 | fprintf_filtered (file, "%sFRM:%i [%s]", | |
711 | (regnum == RISCV_CSR_FCSR_REGNUM | |
712 | ? " " : ""), | |
713 | frm, sfrm[frm]); | |
714 | } | |
715 | } | |
716 | else if (regnum == RISCV_PRIV_REGNUM) | |
717 | { | |
718 | LONGEST d; | |
719 | uint8_t priv; | |
720 | ||
721 | d = value_as_long (val); | |
722 | priv = d & 0xff; | |
723 | ||
724 | if (priv < 4) | |
725 | { | |
726 | static const char * const sprv[] = | |
727 | { | |
728 | "User/Application", | |
729 | "Supervisor", | |
730 | "Hypervisor", | |
731 | "Machine" | |
732 | }; | |
733 | fprintf_filtered (file, "\tprv:%d [%s]", | |
734 | priv, sprv[priv]); | |
735 | } | |
736 | else | |
737 | fprintf_filtered (file, "\tprv:%d [INVALID]", priv); | |
738 | } | |
739 | else | |
740 | { | |
741 | /* If not a vector register, print it also according to its | |
742 | natural format. */ | |
743 | if (TYPE_VECTOR (regtype) == 0) | |
744 | { | |
745 | get_user_print_options (&opts); | |
746 | opts.deref_ref = 1; | |
747 | fprintf_filtered (file, "\t"); | |
748 | val_print (regtype, | |
749 | value_embedded_offset (val), 0, | |
750 | file, 0, val, &opts, current_language); | |
751 | } | |
752 | } | |
753 | } | |
754 | } | |
755 | fprintf_filtered (file, "\n"); | |
756 | } | |
757 | ||
758 | /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member | |
759 | of REGGROUP? */ | |
760 | ||
761 | static int | |
762 | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
763 | struct reggroup *reggroup) | |
764 | { | |
765 | int float_p; | |
766 | int raw_p; | |
767 | unsigned int i; | |
768 | ||
769 | /* Used by 'info registers' and 'info registers <groupname>'. */ | |
770 | ||
771 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
772 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
773 | return 0; | |
774 | ||
775 | if (reggroup == all_reggroup) | |
776 | { | |
777 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM) | |
778 | return 1; | |
779 | /* Only include CSRs that have aliases. */ | |
780 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) | |
781 | { | |
782 | if (regnum == riscv_register_aliases[i].regnum) | |
783 | return 1; | |
784 | } | |
785 | return 0; | |
786 | } | |
787 | else if (reggroup == float_reggroup) | |
788 | return ((regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) | |
789 | || (regnum == RISCV_CSR_FCSR_REGNUM | |
790 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
791 | || regnum == RISCV_CSR_FRM_REGNUM)); | |
792 | else if (reggroup == general_reggroup) | |
793 | return regnum < RISCV_FIRST_FP_REGNUM; | |
794 | else if (reggroup == restore_reggroup || reggroup == save_reggroup) | |
795 | { | |
796 | if (riscv_has_fp_regs (gdbarch)) | |
797 | return regnum <= RISCV_LAST_FP_REGNUM; | |
798 | else | |
799 | return regnum < RISCV_FIRST_FP_REGNUM; | |
800 | } | |
801 | else if (reggroup == system_reggroup) | |
802 | { | |
803 | if (regnum == RISCV_PRIV_REGNUM) | |
804 | return 1; | |
805 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM) | |
806 | return 0; | |
807 | /* Only include CSRs that have aliases. */ | |
808 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) | |
809 | { | |
810 | if (regnum == riscv_register_aliases[i].regnum) | |
811 | return 1; | |
812 | } | |
813 | return 0; | |
814 | } | |
815 | else if (reggroup == vector_reggroup) | |
816 | return 0; | |
817 | else | |
818 | return 0; | |
819 | } | |
820 | ||
821 | /* Implement the print_registers_info gdbarch method. This is used by | |
822 | 'info registers' and 'info all-registers'. */ | |
823 | ||
824 | static void | |
825 | riscv_print_registers_info (struct gdbarch *gdbarch, | |
826 | struct ui_file *file, | |
827 | struct frame_info *frame, | |
828 | int regnum, int print_all) | |
829 | { | |
830 | if (regnum != -1) | |
831 | { | |
832 | /* Print one specified register. */ | |
833 | gdb_assert (regnum <= RISCV_LAST_REGNUM); | |
834 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
835 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
836 | error (_("Not a valid register for the current processor type")); | |
837 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
838 | } | |
839 | else | |
840 | { | |
841 | struct reggroup *reggroup; | |
842 | ||
843 | if (print_all) | |
844 | reggroup = all_reggroup; | |
845 | else | |
846 | reggroup = general_reggroup; | |
847 | ||
848 | for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum) | |
849 | { | |
850 | /* Zero never changes, so might as well hide by default. */ | |
851 | if (regnum == RISCV_ZERO_REGNUM && !print_all) | |
852 | continue; | |
853 | ||
854 | /* Registers with no name are not valid on this ISA. */ | |
855 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
856 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
857 | continue; | |
858 | ||
859 | /* Is the register in the group we're interested in? */ | |
860 | if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup)) | |
861 | continue; | |
862 | ||
863 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
864 | } | |
865 | } | |
866 | } | |
867 | ||
868 | /* Class that handles one decoded RiscV instruction. */ | |
869 | ||
870 | class riscv_insn | |
871 | { | |
872 | public: | |
873 | ||
874 | /* Enum of all the opcodes that GDB cares about during the prologue scan. */ | |
875 | enum opcode | |
876 | { | |
877 | /* Unknown value is used at initialisation time. */ | |
878 | UNKNOWN = 0, | |
879 | ||
880 | /* These instructions are all the ones we are interested in during the | |
881 | prologue scan. */ | |
882 | ADD, | |
883 | ADDI, | |
884 | ADDIW, | |
885 | ADDW, | |
886 | AUIPC, | |
887 | LUI, | |
888 | SD, | |
889 | SW, | |
890 | ||
891 | /* Other instructions are not interesting during the prologue scan, and | |
892 | are ignored. */ | |
893 | OTHER | |
894 | }; | |
895 | ||
896 | riscv_insn () | |
897 | : m_length (0), | |
898 | m_opcode (OTHER), | |
899 | m_rd (0), | |
900 | m_rs1 (0), | |
901 | m_rs2 (0) | |
902 | { | |
903 | /* Nothing. */ | |
904 | } | |
905 | ||
906 | void decode (struct gdbarch *gdbarch, CORE_ADDR pc); | |
907 | ||
908 | /* Get the length of the instruction in bytes. */ | |
909 | int length () const | |
910 | { return m_length; } | |
911 | ||
912 | /* Get the opcode for this instruction. */ | |
913 | enum opcode opcode () const | |
914 | { return m_opcode; } | |
915 | ||
916 | /* Get destination register field for this instruction. This is only | |
917 | valid if the OPCODE implies there is such a field for this | |
918 | instruction. */ | |
919 | int rd () const | |
920 | { return m_rd; } | |
921 | ||
922 | /* Get the RS1 register field for this instruction. This is only valid | |
923 | if the OPCODE implies there is such a field for this instruction. */ | |
924 | int rs1 () const | |
925 | { return m_rs1; } | |
926 | ||
927 | /* Get the RS2 register field for this instruction. This is only valid | |
928 | if the OPCODE implies there is such a field for this instruction. */ | |
929 | int rs2 () const | |
930 | { return m_rs2; } | |
931 | ||
932 | /* Get the immediate for this instruction in signed form. This is only | |
933 | valid if the OPCODE implies there is such a field for this | |
934 | instruction. */ | |
935 | int imm_signed () const | |
936 | { return m_imm.s; } | |
937 | ||
938 | private: | |
939 | ||
940 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ | |
941 | int decode_register_index (unsigned long opcode, int offset) | |
942 | { | |
943 | return (opcode >> offset) & 0x1F; | |
944 | } | |
945 | ||
946 | /* Helper for DECODE, decode 32-bit R-type instruction. */ | |
947 | void decode_r_type_insn (enum opcode opcode, ULONGEST ival) | |
948 | { | |
949 | m_opcode = opcode; | |
950 | m_rd = decode_register_index (ival, OP_SH_RD); | |
951 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
952 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
953 | } | |
954 | ||
955 | /* Helper for DECODE, decode 16-bit compressed R-type instruction. */ | |
956 | void decode_cr_type_insn (enum opcode opcode, ULONGEST ival) | |
957 | { | |
958 | m_opcode = opcode; | |
959 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
960 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
961 | } | |
962 | ||
963 | /* Helper for DECODE, decode 32-bit I-type instruction. */ | |
964 | void decode_i_type_insn (enum opcode opcode, ULONGEST ival) | |
965 | { | |
966 | m_opcode = opcode; | |
967 | m_rd = decode_register_index (ival, OP_SH_RD); | |
968 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
969 | m_imm.s = EXTRACT_ITYPE_IMM (ival); | |
970 | } | |
971 | ||
972 | /* Helper for DECODE, decode 16-bit compressed I-type instruction. */ | |
973 | void decode_ci_type_insn (enum opcode opcode, ULONGEST ival) | |
974 | { | |
975 | m_opcode = opcode; | |
976 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
977 | m_imm.s = EXTRACT_RVC_IMM (ival); | |
978 | } | |
979 | ||
980 | /* Helper for DECODE, decode 32-bit S-type instruction. */ | |
981 | void decode_s_type_insn (enum opcode opcode, ULONGEST ival) | |
982 | { | |
983 | m_opcode = opcode; | |
984 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
985 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
986 | m_imm.s = EXTRACT_STYPE_IMM (ival); | |
987 | } | |
988 | ||
989 | /* Helper for DECODE, decode 32-bit U-type instruction. */ | |
990 | void decode_u_type_insn (enum opcode opcode, ULONGEST ival) | |
991 | { | |
992 | m_opcode = opcode; | |
993 | m_rd = decode_register_index (ival, OP_SH_RD); | |
994 | m_imm.s = EXTRACT_UTYPE_IMM (ival); | |
995 | } | |
996 | ||
997 | /* Fetch instruction from target memory at ADDR, return the content of | |
998 | the instruction, and update LEN with the instruction length. */ | |
999 | static ULONGEST fetch_instruction (struct gdbarch *gdbarch, | |
1000 | CORE_ADDR addr, int *len); | |
1001 | ||
1002 | /* The length of the instruction in bytes. Should be 2 or 4. */ | |
1003 | int m_length; | |
1004 | ||
1005 | /* The instruction opcode. */ | |
1006 | enum opcode m_opcode; | |
1007 | ||
1008 | /* The three possible registers an instruction might reference. Not | |
1009 | every instruction fills in all of these registers. Which fields are | |
1010 | valid depends on the opcode. The naming of these fields matches the | |
1011 | naming in the riscv isa manual. */ | |
1012 | int m_rd; | |
1013 | int m_rs1; | |
1014 | int m_rs2; | |
1015 | ||
1016 | /* Possible instruction immediate. This is only valid if the instruction | |
1017 | format contains an immediate, not all instruction, whether this is | |
1018 | valid depends on the opcode. Despite only having one format for now | |
1019 | the immediate is packed into a union, later instructions might require | |
1020 | an unsigned formatted immediate, having the union in place now will | |
1021 | reduce the need for code churn later. */ | |
1022 | union riscv_insn_immediate | |
1023 | { | |
1024 | riscv_insn_immediate () | |
1025 | : s (0) | |
1026 | { | |
1027 | /* Nothing. */ | |
1028 | } | |
1029 | ||
1030 | int s; | |
1031 | } m_imm; | |
1032 | }; | |
1033 | ||
1034 | /* Fetch instruction from target memory at ADDR, return the content of the | |
1035 | instruction, and update LEN with the instruction length. */ | |
1036 | ||
1037 | ULONGEST | |
1038 | riscv_insn::fetch_instruction (struct gdbarch *gdbarch, | |
1039 | CORE_ADDR addr, int *len) | |
1040 | { | |
1041 | enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); | |
1042 | gdb_byte buf[8]; | |
1043 | int instlen, status; | |
1044 | ||
1045 | /* All insns are at least 16 bits. */ | |
1046 | status = target_read_memory (addr, buf, 2); | |
1047 | if (status) | |
1048 | memory_error (TARGET_XFER_E_IO, addr); | |
1049 | ||
1050 | /* If we need more, grab it now. */ | |
1051 | instlen = riscv_insn_length (buf[0]); | |
1052 | *len = instlen; | |
1053 | if (instlen > sizeof (buf)) | |
1054 | internal_error (__FILE__, __LINE__, | |
1055 | _("%s: riscv_insn_length returned %i"), | |
1056 | __func__, instlen); | |
1057 | else if (instlen > 2) | |
1058 | { | |
1059 | status = target_read_memory (addr + 2, buf + 2, instlen - 2); | |
1060 | if (status) | |
1061 | memory_error (TARGET_XFER_E_IO, addr + 2); | |
1062 | } | |
1063 | ||
1064 | return extract_unsigned_integer (buf, instlen, byte_order); | |
1065 | } | |
1066 | ||
1067 | /* Fetch from target memory an instruction at PC and decode it. */ | |
1068 | ||
1069 | void | |
1070 | riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1071 | { | |
1072 | ULONGEST ival; | |
1073 | ||
1074 | /* Fetch the instruction, and the instructions length. */ | |
1075 | ival = fetch_instruction (gdbarch, pc, &m_length); | |
1076 | ||
1077 | if (m_length == 4) | |
1078 | { | |
1079 | if (is_add_insn (ival)) | |
1080 | decode_r_type_insn (ADD, ival); | |
1081 | else if (is_addw_insn (ival)) | |
1082 | decode_r_type_insn (ADDW, ival); | |
1083 | else if (is_addi_insn (ival)) | |
1084 | decode_i_type_insn (ADDI, ival); | |
1085 | else if (is_addiw_insn (ival)) | |
1086 | decode_i_type_insn (ADDIW, ival); | |
1087 | else if (is_auipc_insn (ival)) | |
1088 | decode_u_type_insn (AUIPC, ival); | |
1089 | else if (is_lui_insn (ival)) | |
1090 | decode_u_type_insn (LUI, ival); | |
1091 | else if (is_sd_insn (ival)) | |
1092 | decode_s_type_insn (SD, ival); | |
1093 | else if (is_sw_insn (ival)) | |
1094 | decode_s_type_insn (SW, ival); | |
1095 | else | |
1096 | /* None of the other fields are valid in this case. */ | |
1097 | m_opcode = OTHER; | |
1098 | } | |
1099 | else if (m_length == 2) | |
1100 | { | |
1101 | if (is_c_add_insn (ival)) | |
1102 | decode_cr_type_insn (ADD, ival); | |
1103 | else if (is_c_addw_insn (ival)) | |
1104 | decode_cr_type_insn (ADDW, ival); | |
1105 | else if (is_c_addi_insn (ival)) | |
1106 | decode_ci_type_insn (ADDI, ival); | |
1107 | else if (is_c_addiw_insn (ival)) | |
1108 | decode_ci_type_insn (ADDIW, ival); | |
1109 | else if (is_c_addi16sp_insn (ival)) | |
1110 | { | |
1111 | m_opcode = ADDI; | |
1112 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); | |
1113 | m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); | |
1114 | } | |
1115 | else if (is_lui_insn (ival)) | |
1116 | m_opcode = OTHER; | |
1117 | else if (is_c_sd_insn (ival)) | |
1118 | m_opcode = OTHER; | |
1119 | else if (is_sw_insn (ival)) | |
1120 | m_opcode = OTHER; | |
1121 | else | |
1122 | /* None of the other fields of INSN are valid in this case. */ | |
1123 | m_opcode = OTHER; | |
1124 | } | |
1125 | else | |
1126 | internal_error (__FILE__, __LINE__, | |
1127 | _("unable to decode %d byte instructions in " | |
1128 | "prologue at %s"), m_length, | |
1129 | core_addr_to_string (pc)); | |
1130 | } | |
1131 | ||
1132 | /* The prologue scanner. This is currently only used for skipping the | |
1133 | prologue of a function when the DWARF information is not sufficient. | |
1134 | However, it is written with filling of the frame cache in mind, which | |
1135 | is why different groups of stack setup instructions are split apart | |
1136 | during the core of the inner loop. In the future, the intention is to | |
1137 | extend this function to fully support building up a frame cache that | |
1138 | can unwind register values when there is no DWARF information. */ | |
1139 | ||
1140 | static CORE_ADDR | |
1141 | riscv_scan_prologue (struct gdbarch *gdbarch, | |
1142 | CORE_ADDR start_pc, CORE_ADDR limit_pc) | |
1143 | { | |
1144 | CORE_ADDR cur_pc, next_pc; | |
1145 | long frame_offset = 0; | |
1146 | CORE_ADDR end_prologue_addr = 0; | |
1147 | ||
1148 | if (limit_pc > start_pc + 200) | |
1149 | limit_pc = start_pc + 200; | |
1150 | ||
1151 | for (next_pc = cur_pc = start_pc; cur_pc < limit_pc; cur_pc = next_pc) | |
1152 | { | |
1153 | struct riscv_insn insn; | |
1154 | ||
1155 | /* Decode the current instruction, and decide where the next | |
1156 | instruction lives based on the size of this instruction. */ | |
1157 | insn.decode (gdbarch, cur_pc); | |
1158 | gdb_assert (insn.length () > 0); | |
1159 | next_pc = cur_pc + insn.length (); | |
1160 | ||
1161 | /* Look for common stack adjustment insns. */ | |
1162 | if ((insn.opcode () == riscv_insn::ADDI | |
1163 | || insn.opcode () == riscv_insn::ADDIW) | |
1164 | && insn.rd () == RISCV_SP_REGNUM | |
1165 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1166 | { | |
1167 | /* Handle: addi sp, sp, -i | |
1168 | or: addiw sp, sp, -i */ | |
1169 | if (insn.imm_signed () < 0) | |
1170 | frame_offset += insn.imm_signed (); | |
1171 | else | |
1172 | break; | |
1173 | } | |
1174 | else if ((insn.opcode () == riscv_insn::SW | |
1175 | || insn.opcode () == riscv_insn::SD) | |
1176 | && (insn.rs1 () == RISCV_SP_REGNUM | |
1177 | || insn.rs1 () == RISCV_FP_REGNUM)) | |
1178 | { | |
1179 | /* Handle: sw reg, offset(sp) | |
1180 | or: sd reg, offset(sp) | |
1181 | or: sw reg, offset(s0) | |
1182 | or: sd reg, offset(s0) */ | |
1183 | /* Instruction storing a register onto the stack. */ | |
1184 | } | |
1185 | else if (insn.opcode () == riscv_insn::ADDI | |
1186 | && insn.rd () == RISCV_FP_REGNUM | |
1187 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1188 | { | |
1189 | /* Handle: addi s0, sp, size */ | |
1190 | /* Instructions setting up the frame pointer. */ | |
1191 | } | |
1192 | else if ((insn.opcode () == riscv_insn::ADD | |
1193 | || insn.opcode () == riscv_insn::ADDW) | |
1194 | && insn.rd () == RISCV_FP_REGNUM | |
1195 | && insn.rs1 () == RISCV_SP_REGNUM | |
1196 | && insn.rs2 () == RISCV_ZERO_REGNUM) | |
1197 | { | |
1198 | /* Handle: add s0, sp, 0 | |
1199 | or: addw s0, sp, 0 */ | |
1200 | /* Instructions setting up the frame pointer. */ | |
1201 | } | |
1202 | else if ((insn.rd () == RISCV_GP_REGNUM | |
1203 | && (insn.opcode () == riscv_insn::AUIPC | |
1204 | || insn.opcode () == riscv_insn::LUI | |
1205 | || (insn.opcode () == riscv_insn::ADDI | |
1206 | && insn.rs1 () == RISCV_GP_REGNUM) | |
1207 | || (insn.opcode () == riscv_insn::ADD | |
1208 | && (insn.rs1 () == RISCV_GP_REGNUM | |
1209 | || insn.rs2 () == RISCV_GP_REGNUM)))) | |
1210 | || (insn.opcode () == riscv_insn::ADDI | |
1211 | && insn.rd () == RISCV_ZERO_REGNUM | |
1212 | && insn.rs1 () == RISCV_ZERO_REGNUM | |
1213 | && insn.imm_signed () == 0)) | |
1214 | { | |
1215 | /* Handle: auipc gp, n | |
1216 | or: addi gp, gp, n | |
1217 | or: add gp, gp, reg | |
1218 | or: add gp, reg, gp | |
1219 | or: lui gp, n | |
1220 | or: add x0, x0, 0 (NOP) */ | |
1221 | /* These instructions are part of the prologue, but we don't need | |
1222 | to do anything special to handle them. */ | |
1223 | } | |
1224 | else | |
1225 | { | |
1226 | if (end_prologue_addr == 0) | |
1227 | end_prologue_addr = cur_pc; | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | if (end_prologue_addr == 0) | |
1232 | end_prologue_addr = cur_pc; | |
1233 | ||
1234 | return end_prologue_addr; | |
1235 | } | |
1236 | ||
1237 | /* Implement the riscv_skip_prologue gdbarch method. */ | |
1238 | ||
1239 | static CORE_ADDR | |
1240 | riscv_skip_prologue (struct gdbarch *gdbarch, | |
1241 | CORE_ADDR pc) | |
1242 | { | |
1243 | CORE_ADDR limit_pc; | |
1244 | CORE_ADDR func_addr; | |
1245 | ||
1246 | /* See if we can determine the end of the prologue via the symbol | |
1247 | table. If so, then return either PC, or the PC after the | |
1248 | prologue, whichever is greater. */ | |
1249 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
1250 | { | |
1251 | CORE_ADDR post_prologue_pc | |
1252 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1253 | ||
1254 | if (post_prologue_pc != 0) | |
1255 | return std::max (pc, post_prologue_pc); | |
1256 | } | |
1257 | ||
1258 | /* Can't determine prologue from the symbol table, need to examine | |
1259 | instructions. */ | |
1260 | ||
1261 | /* Find an upper limit on the function prologue using the debug | |
1262 | information. If the debug information could not be used to provide | |
1263 | that bound, then use an arbitrary large number as the upper bound. */ | |
1264 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
1265 | if (limit_pc == 0) | |
1266 | limit_pc = pc + 100; /* MAGIC! */ | |
1267 | ||
1268 | return riscv_scan_prologue (gdbarch, pc, limit_pc); | |
1269 | } | |
1270 | ||
1271 | /* Implement the gdbarch push dummy code callback. */ | |
1272 | ||
1273 | static CORE_ADDR | |
1274 | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
1275 | CORE_ADDR funaddr, struct value **args, int nargs, | |
1276 | struct type *value_type, CORE_ADDR *real_pc, | |
1277 | CORE_ADDR *bp_addr, struct regcache *regcache) | |
1278 | { | |
1279 | /* Allocate space for a breakpoint, and keep the stack correctly | |
1280 | aligned. */ | |
1281 | sp -= 16; | |
1282 | *bp_addr = sp; | |
1283 | *real_pc = funaddr; | |
1284 | return sp; | |
1285 | } | |
1286 | ||
1287 | /* Compute the alignment of the type T. Used while setting up the | |
1288 | arguments for a dummy call. */ | |
1289 | ||
1290 | static int | |
1291 | riscv_type_alignment (struct type *t) | |
1292 | { | |
1293 | t = check_typedef (t); | |
1294 | switch (TYPE_CODE (t)) | |
1295 | { | |
1296 | default: | |
1297 | error (_("Could not compute alignment of type")); | |
1298 | ||
1299 | case TYPE_CODE_RVALUE_REF: | |
1300 | case TYPE_CODE_PTR: | |
1301 | case TYPE_CODE_ENUM: | |
1302 | case TYPE_CODE_INT: | |
1303 | case TYPE_CODE_FLT: | |
1304 | case TYPE_CODE_REF: | |
1305 | case TYPE_CODE_CHAR: | |
1306 | case TYPE_CODE_BOOL: | |
1307 | return TYPE_LENGTH (t); | |
1308 | ||
1309 | case TYPE_CODE_ARRAY: | |
1310 | case TYPE_CODE_COMPLEX: | |
1311 | return riscv_type_alignment (TYPE_TARGET_TYPE (t)); | |
1312 | ||
1313 | case TYPE_CODE_STRUCT: | |
1314 | case TYPE_CODE_UNION: | |
1315 | { | |
1316 | int i; | |
1317 | int align = 1; | |
1318 | ||
1319 | for (i = 0; i < TYPE_NFIELDS (t); ++i) | |
1320 | { | |
1321 | if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS) | |
1322 | { | |
1323 | int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i)); | |
1324 | if (a > align) | |
1325 | align = a; | |
1326 | } | |
1327 | } | |
1328 | return align; | |
1329 | } | |
1330 | } | |
1331 | } | |
1332 | ||
1333 | /* Holds information about a single argument either being passed to an | |
1334 | inferior function, or returned from an inferior function. This includes | |
1335 | information about the size, type, etc of the argument, and also | |
1336 | information about how the argument will be passed (or returned). */ | |
1337 | ||
1338 | struct riscv_arg_info | |
1339 | { | |
1340 | /* Contents of the argument. */ | |
1341 | const gdb_byte *contents; | |
1342 | ||
1343 | /* Length of argument. */ | |
1344 | int length; | |
1345 | ||
1346 | /* Alignment required for an argument of this type. */ | |
1347 | int align; | |
1348 | ||
1349 | /* The type for this argument. */ | |
1350 | struct type *type; | |
1351 | ||
1352 | /* Each argument can have either 1 or 2 locations assigned to it. Each | |
1353 | location describes where part of the argument will be placed. The | |
1354 | second location is valid based on the LOC_TYPE and C_LENGTH fields | |
1355 | of the first location (which is always valid). */ | |
1356 | struct location | |
1357 | { | |
1358 | /* What type of location this is. */ | |
1359 | enum location_type | |
1360 | { | |
1361 | /* Argument passed in a register. */ | |
1362 | in_reg, | |
1363 | ||
1364 | /* Argument passed as an on stack argument. */ | |
1365 | on_stack, | |
1366 | ||
1367 | /* Argument passed by reference. The second location is always | |
1368 | valid for a BY_REF argument, and describes where the address | |
1369 | of the BY_REF argument should be placed. */ | |
1370 | by_ref | |
1371 | } loc_type; | |
1372 | ||
1373 | /* Information that depends on the location type. */ | |
1374 | union | |
1375 | { | |
1376 | /* Which register number to use. */ | |
1377 | int regno; | |
1378 | ||
1379 | /* The offset into the stack region. */ | |
1380 | int offset; | |
1381 | } loc_data; | |
1382 | ||
1383 | /* The length of contents covered by this location. If this is less | |
1384 | than the total length of the argument, then the second location | |
1385 | will be valid, and will describe where the rest of the argument | |
1386 | will go. */ | |
1387 | int c_length; | |
1388 | ||
1389 | /* The offset within CONTENTS for this part of the argument. Will | |
1390 | always be 0 for the first part. For the second part of the | |
1391 | argument, this might be the C_LENGTH value of the first part, | |
1392 | however, if we are passing a structure in two registers, and there's | |
1393 | is padding between the first and second field, then this offset | |
1394 | might be greater than the length of the first argument part. When | |
1395 | the second argument location is not holding part of the argument | |
1396 | value, but is instead holding the address of a reference argument, | |
1397 | then this offset will be set to 0. */ | |
1398 | int c_offset; | |
1399 | } argloc[2]; | |
1400 | }; | |
1401 | ||
1402 | /* Information about a set of registers being used for passing arguments as | |
1403 | part of a function call. The register set must be numerically | |
1404 | sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be | |
1405 | disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */ | |
1406 | ||
1407 | struct riscv_arg_reg | |
1408 | { | |
1409 | riscv_arg_reg (int first, int last) | |
1410 | : next_regnum (first), | |
1411 | last_regnum (last) | |
1412 | { | |
1413 | /* Nothing. */ | |
1414 | } | |
1415 | ||
1416 | /* The GDB register number to use in this set. */ | |
1417 | int next_regnum; | |
1418 | ||
1419 | /* The last GDB register number to use in this set. */ | |
1420 | int last_regnum; | |
1421 | }; | |
1422 | ||
1423 | /* Arguments can be passed as on stack arguments, or by reference. The | |
1424 | on stack arguments must be in a continuous region starting from $sp, | |
1425 | while the by reference arguments can be anywhere, but we'll put them | |
1426 | on the stack after (at higher address) the on stack arguments. | |
1427 | ||
1428 | This might not be the right approach to take. The ABI is clear that | |
1429 | an argument passed by reference can be modified by the callee, which | |
1430 | us placing the argument (temporarily) onto the stack will not achieve | |
1431 | (changes will be lost). There's also the possibility that very large | |
1432 | arguments could overflow the stack. | |
1433 | ||
1434 | This struct is used to track offset into these two areas for where | |
1435 | arguments are to be placed. */ | |
1436 | struct riscv_memory_offsets | |
1437 | { | |
1438 | riscv_memory_offsets () | |
1439 | : arg_offset (0), | |
1440 | ref_offset (0) | |
1441 | { | |
1442 | /* Nothing. */ | |
1443 | } | |
1444 | ||
1445 | /* Offset into on stack argument area. */ | |
1446 | int arg_offset; | |
1447 | ||
1448 | /* Offset into the pass by reference area. */ | |
1449 | int ref_offset; | |
1450 | }; | |
1451 | ||
1452 | /* Holds information about where arguments to a call will be placed. This | |
1453 | is updated as arguments are added onto the call, and can be used to | |
1454 | figure out where the next argument should be placed. */ | |
1455 | ||
1456 | struct riscv_call_info | |
1457 | { | |
1458 | riscv_call_info (struct gdbarch *gdbarch) | |
1459 | : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7), | |
1460 | float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7) | |
1461 | { | |
1462 | xlen = riscv_isa_xlen (gdbarch); | |
1463 | flen = riscv_isa_flen (gdbarch); | |
1464 | ||
1465 | /* Disable use of floating point registers if needed. */ | |
1466 | if (!riscv_has_fp_abi (gdbarch)) | |
1467 | float_regs.next_regnum = float_regs.last_regnum + 1; | |
1468 | } | |
1469 | ||
1470 | /* Track the memory areas used for holding in-memory arguments to a | |
1471 | call. */ | |
1472 | struct riscv_memory_offsets memory; | |
1473 | ||
1474 | /* Holds information about the next integer register to use for passing | |
1475 | an argument. */ | |
1476 | struct riscv_arg_reg int_regs; | |
1477 | ||
1478 | /* Holds information about the next floating point register to use for | |
1479 | passing an argument. */ | |
1480 | struct riscv_arg_reg float_regs; | |
1481 | ||
1482 | /* The XLEN and FLEN are copied in to this structure for convenience, and | |
1483 | are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */ | |
1484 | int xlen; | |
1485 | int flen; | |
1486 | }; | |
1487 | ||
1488 | /* Return the number of registers available for use as parameters in the | |
1489 | register set REG. Returned value can be 0 or more. */ | |
1490 | ||
1491 | static int | |
1492 | riscv_arg_regs_available (struct riscv_arg_reg *reg) | |
1493 | { | |
1494 | if (reg->next_regnum > reg->last_regnum) | |
1495 | return 0; | |
1496 | ||
1497 | return (reg->last_regnum - reg->next_regnum + 1); | |
1498 | } | |
1499 | ||
1500 | /* If there is at least one register available in the register set REG then | |
1501 | the next register from REG is assigned to LOC and the length field of | |
1502 | LOC is updated to LENGTH. The register set REG is updated to indicate | |
1503 | that the assigned register is no longer available and the function | |
1504 | returns true. | |
1505 | ||
1506 | If there are no registers available in REG then the function returns | |
1507 | false, and LOC and REG are unchanged. */ | |
1508 | ||
1509 | static bool | |
1510 | riscv_assign_reg_location (struct riscv_arg_info::location *loc, | |
1511 | struct riscv_arg_reg *reg, | |
1512 | int length, int offset) | |
1513 | { | |
1514 | if (reg->next_regnum <= reg->last_regnum) | |
1515 | { | |
1516 | loc->loc_type = riscv_arg_info::location::in_reg; | |
1517 | loc->loc_data.regno = reg->next_regnum; | |
1518 | reg->next_regnum++; | |
1519 | loc->c_length = length; | |
1520 | loc->c_offset = offset; | |
1521 | return true; | |
1522 | } | |
1523 | ||
1524 | return false; | |
1525 | } | |
1526 | ||
1527 | /* Assign LOC a location as the next stack parameter, and update MEMORY to | |
1528 | record that an area of stack has been used to hold the parameter | |
1529 | described by LOC. | |
1530 | ||
1531 | The length field of LOC is updated to LENGTH, the length of the | |
1532 | parameter being stored, and ALIGN is the alignment required by the | |
1533 | parameter, which will affect how memory is allocated out of MEMORY. */ | |
1534 | ||
1535 | static void | |
1536 | riscv_assign_stack_location (struct riscv_arg_info::location *loc, | |
1537 | struct riscv_memory_offsets *memory, | |
1538 | int length, int align) | |
1539 | { | |
1540 | loc->loc_type = riscv_arg_info::location::on_stack; | |
1541 | memory->arg_offset | |
1542 | = align_up (memory->arg_offset, align); | |
1543 | loc->loc_data.offset = memory->arg_offset; | |
1544 | memory->arg_offset += length; | |
1545 | loc->c_length = length; | |
1546 | ||
1547 | /* Offset is always 0, either we're the first location part, in which | |
1548 | case we're reading content from the start of the argument, or we're | |
1549 | passing the address of a reference argument, so 0. */ | |
1550 | loc->c_offset = 0; | |
1551 | } | |
1552 | ||
1553 | /* Update AINFO, which describes an argument that should be passed or | |
1554 | returned using the integer ABI. The argloc fields within AINFO are | |
1555 | updated to describe the location in which the argument will be passed to | |
1556 | a function, or returned from a function. | |
1557 | ||
1558 | The CINFO structure contains the ongoing call information, the holds | |
1559 | information such as which argument registers are remaining to be | |
1560 | assigned to parameter, and how much memory has been used by parameters | |
1561 | so far. | |
1562 | ||
1563 | By examining the state of CINFO a suitable location can be selected, | |
1564 | and assigned to AINFO. */ | |
1565 | ||
1566 | static void | |
1567 | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, | |
1568 | struct riscv_call_info *cinfo) | |
1569 | { | |
1570 | if (ainfo->length > (2 * cinfo->xlen)) | |
1571 | { | |
1572 | /* Argument is going to be passed by reference. */ | |
1573 | ainfo->argloc[0].loc_type | |
1574 | = riscv_arg_info::location::by_ref; | |
1575 | cinfo->memory.ref_offset | |
1576 | = align_up (cinfo->memory.ref_offset, ainfo->align); | |
1577 | ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset; | |
1578 | cinfo->memory.ref_offset += ainfo->length; | |
1579 | ainfo->argloc[0].c_length = ainfo->length; | |
1580 | ||
1581 | /* The second location for this argument is given over to holding the | |
1582 | address of the by-reference data. Pass 0 for the offset as this | |
1583 | is not part of the actual argument value. */ | |
1584 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1585 | &cinfo->int_regs, | |
1586 | cinfo->xlen, 0)) | |
1587 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1588 | &cinfo->memory, cinfo->xlen, | |
1589 | cinfo->xlen); | |
1590 | } | |
1591 | else | |
1592 | { | |
1593 | int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length; | |
1594 | ||
1595 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1596 | &cinfo->int_regs, len, 0)) | |
1597 | riscv_assign_stack_location (&ainfo->argloc[0], | |
1598 | &cinfo->memory, len, ainfo->align); | |
1599 | ||
1600 | if (len < ainfo->length) | |
1601 | { | |
1602 | len = ainfo->length - len; | |
1603 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1604 | &cinfo->int_regs, len, | |
1605 | cinfo->xlen)) | |
1606 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1607 | &cinfo->memory, len, cinfo->xlen); | |
1608 | } | |
1609 | } | |
1610 | } | |
1611 | ||
1612 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1613 | is being passed with the floating point ABI. */ | |
1614 | ||
1615 | static void | |
1616 | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, | |
1617 | struct riscv_call_info *cinfo) | |
1618 | { | |
1619 | if (ainfo->length > cinfo->flen) | |
1620 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1621 | else | |
1622 | { | |
1623 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1624 | &cinfo->float_regs, | |
1625 | ainfo->length, 0)) | |
1626 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1627 | } | |
1628 | } | |
1629 | ||
1630 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1631 | is a complex floating point argument, and is therefore handled | |
1632 | differently to other argument types. */ | |
1633 | ||
1634 | static void | |
1635 | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, | |
1636 | struct riscv_call_info *cinfo) | |
1637 | { | |
1638 | if (ainfo->length <= (2 * cinfo->flen) | |
1639 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
1640 | { | |
1641 | bool result; | |
1642 | int len = ainfo->length / 2; | |
1643 | ||
1644 | result = riscv_assign_reg_location (&ainfo->argloc[0], | |
1645 | &cinfo->float_regs, len, len); | |
1646 | gdb_assert (result); | |
1647 | ||
1648 | result = riscv_assign_reg_location (&ainfo->argloc[1], | |
1649 | &cinfo->float_regs, len, len); | |
1650 | gdb_assert (result); | |
1651 | } | |
1652 | else | |
1653 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1654 | } | |
1655 | ||
1656 | /* A structure used for holding information about a structure type within | |
1657 | the inferior program. The RiscV ABI has special rules for handling some | |
1658 | structures with a single field or with two fields. The counting of | |
1659 | fields here is done after flattening out all nested structures. */ | |
1660 | ||
1661 | class riscv_struct_info | |
1662 | { | |
1663 | public: | |
1664 | riscv_struct_info () | |
1665 | : m_number_of_fields (0), | |
1666 | m_types { nullptr, nullptr } | |
1667 | { | |
1668 | /* Nothing. */ | |
1669 | } | |
1670 | ||
1671 | /* Analyse TYPE descending into nested structures, count the number of | |
1672 | scalar fields and record the types of the first two fields found. */ | |
1673 | void analyse (struct type *type); | |
1674 | ||
1675 | /* The number of scalar fields found in the analysed type. This is | |
1676 | currently only accurate if the value returned is 0, 1, or 2 as the | |
1677 | analysis stops counting when the number of fields is 3. This is | |
1678 | because the RiscV ABI only has special cases for 1 or 2 fields, | |
1679 | anything else we just don't care about. */ | |
1680 | int number_of_fields () const | |
1681 | { return m_number_of_fields; } | |
1682 | ||
1683 | /* Return the type for scalar field INDEX within the analysed type. Will | |
1684 | return nullptr if there is no field at that index. Only INDEX values | |
1685 | 0 and 1 can be requested as the RiscV ABI only has special cases for | |
1686 | structures with 1 or 2 fields. */ | |
1687 | struct type *field_type (int index) const | |
1688 | { | |
1689 | gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0]))); | |
1690 | return m_types[index]; | |
1691 | } | |
1692 | ||
1693 | private: | |
1694 | /* The number of scalar fields found within the structure after recursing | |
1695 | into nested structures. */ | |
1696 | int m_number_of_fields; | |
1697 | ||
1698 | /* The types of the first two scalar fields found within the structure | |
1699 | after recursing into nested structures. */ | |
1700 | struct type *m_types[2]; | |
1701 | }; | |
1702 | ||
1703 | /* Analyse TYPE descending into nested structures, count the number of | |
1704 | scalar fields and record the types of the first two fields found. */ | |
1705 | ||
1706 | void | |
1707 | riscv_struct_info::analyse (struct type *type) | |
1708 | { | |
1709 | unsigned int count = TYPE_NFIELDS (type); | |
1710 | unsigned int i; | |
1711 | ||
1712 | for (i = 0; i < count; ++i) | |
1713 | { | |
1714 | if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS) | |
1715 | continue; | |
1716 | ||
1717 | struct type *field_type = TYPE_FIELD_TYPE (type, i); | |
1718 | field_type = check_typedef (field_type); | |
1719 | ||
1720 | switch (TYPE_CODE (field_type)) | |
1721 | { | |
1722 | case TYPE_CODE_STRUCT: | |
1723 | analyse (field_type); | |
1724 | break; | |
1725 | ||
1726 | default: | |
1727 | /* RiscV only flattens out structures. Anything else does not | |
1728 | need to be flattened, we just record the type, and when we | |
1729 | look at the analysis results we'll realise this is not a | |
1730 | structure we can special case, and pass the structure in | |
1731 | memory. */ | |
1732 | if (m_number_of_fields < 2) | |
1733 | m_types[m_number_of_fields] = field_type; | |
1734 | m_number_of_fields++; | |
1735 | break; | |
1736 | } | |
1737 | ||
1738 | /* RiscV only has special handling for structures with 1 or 2 scalar | |
1739 | fields, any more than that and the structure is just passed in | |
1740 | memory. We can safely drop out early when we find 3 or more | |
1741 | fields then. */ | |
1742 | ||
1743 | if (m_number_of_fields > 2) | |
1744 | return; | |
1745 | } | |
1746 | } | |
1747 | ||
1748 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1749 | is a structure. Small structures on RiscV have some special case | |
1750 | handling in order that the structure might be passed in register. | |
1751 | Larger structures are passed in memory. After assigning location | |
1752 | information to AINFO, CINFO will have been updated. */ | |
1753 | ||
1754 | static void | |
1755 | riscv_call_arg_struct (struct riscv_arg_info *ainfo, | |
1756 | struct riscv_call_info *cinfo) | |
1757 | { | |
1758 | if (riscv_arg_regs_available (&cinfo->float_regs) >= 1) | |
1759 | { | |
1760 | struct riscv_struct_info sinfo; | |
1761 | ||
1762 | sinfo.analyse (ainfo->type); | |
1763 | if (sinfo.number_of_fields () == 1 | |
1764 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX) | |
1765 | { | |
1766 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1767 | == TYPE_LENGTH (sinfo.field_type (0))); | |
1768 | return riscv_call_arg_complex_float (ainfo, cinfo); | |
1769 | } | |
1770 | ||
1771 | if (sinfo.number_of_fields () == 1 | |
1772 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT) | |
1773 | { | |
1774 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1775 | == TYPE_LENGTH (sinfo.field_type (0))); | |
1776 | return riscv_call_arg_scalar_float (ainfo, cinfo); | |
1777 | } | |
1778 | ||
1779 | if (sinfo.number_of_fields () == 2 | |
1780 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
1781 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
1782 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
1783 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen | |
1784 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
1785 | { | |
1786 | int len0, len1, offset; | |
1787 | ||
1788 | gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen)); | |
1789 | ||
1790 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
1791 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1792 | &cinfo->float_regs, len0, 0)) | |
1793 | error (_("failed during argument setup")); | |
1794 | ||
1795 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
1796 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
1797 | gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type) | |
1798 | - TYPE_LENGTH (sinfo.field_type (0)))); | |
1799 | ||
1800 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1801 | &cinfo->float_regs, | |
1802 | len1, offset)) | |
1803 | error (_("failed during argument setup")); | |
1804 | return; | |
1805 | } | |
1806 | ||
1807 | if (sinfo.number_of_fields () == 2 | |
1808 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
1809 | && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
1810 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
1811 | && is_integral_type (sinfo.field_type (1)) | |
1812 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen)) | |
1813 | { | |
1814 | int len0, len1, offset; | |
1815 | ||
1816 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1817 | <= (cinfo->flen + cinfo->xlen)); | |
1818 | ||
1819 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
1820 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1821 | &cinfo->float_regs, len0, 0)) | |
1822 | error (_("failed during argument setup")); | |
1823 | ||
1824 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
1825 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
1826 | gdb_assert (len1 <= cinfo->xlen); | |
1827 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1828 | &cinfo->int_regs, len1, offset)) | |
1829 | error (_("failed during argument setup")); | |
1830 | return; | |
1831 | } | |
1832 | ||
1833 | if (sinfo.number_of_fields () == 2 | |
1834 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
1835 | && (is_integral_type (sinfo.field_type (0)) | |
1836 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen | |
1837 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
1838 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen)) | |
1839 | { | |
1840 | int len0, len1, offset; | |
1841 | ||
1842 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1843 | <= (cinfo->flen + cinfo->xlen)); | |
1844 | ||
1845 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
1846 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
1847 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
1848 | ||
1849 | gdb_assert (len0 <= cinfo->xlen); | |
1850 | gdb_assert (len1 <= cinfo->flen); | |
1851 | ||
1852 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1853 | &cinfo->int_regs, len0, 0)) | |
1854 | error (_("failed during argument setup")); | |
1855 | ||
1856 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1857 | &cinfo->float_regs, | |
1858 | len1, offset)) | |
1859 | error (_("failed during argument setup")); | |
1860 | ||
1861 | return; | |
1862 | } | |
1863 | } | |
1864 | ||
1865 | /* Non of the structure flattening cases apply, so we just pass using | |
1866 | the integer ABI. */ | |
1867 | ainfo->length = align_up (ainfo->length, cinfo->xlen); | |
1868 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
1869 | } | |
1870 | ||
1871 | /* Assign a location to call (or return) argument AINFO, the location is | |
1872 | selected from CINFO which holds information about what call argument | |
1873 | locations are available for use next. The TYPE is the type of the | |
1874 | argument being passed, this information is recorded into AINFO (along | |
1875 | with some additional information derived from the type). | |
1876 | ||
1877 | After assigning a location to AINFO, CINFO will have been updated. */ | |
1878 | ||
1879 | static void | |
1880 | riscv_arg_location (struct gdbarch *gdbarch, | |
1881 | struct riscv_arg_info *ainfo, | |
1882 | struct riscv_call_info *cinfo, | |
1883 | struct type *type) | |
1884 | { | |
1885 | ainfo->type = type; | |
1886 | ainfo->length = TYPE_LENGTH (ainfo->type); | |
1887 | ainfo->align = riscv_type_alignment (ainfo->type); | |
1888 | ainfo->contents = nullptr; | |
1889 | ||
1890 | switch (TYPE_CODE (ainfo->type)) | |
1891 | { | |
1892 | case TYPE_CODE_INT: | |
1893 | case TYPE_CODE_BOOL: | |
1894 | case TYPE_CODE_CHAR: | |
1895 | case TYPE_CODE_RANGE: | |
1896 | case TYPE_CODE_ENUM: | |
1897 | case TYPE_CODE_PTR: | |
1898 | if (ainfo->length <= cinfo->xlen) | |
1899 | { | |
1900 | ainfo->type = builtin_type (gdbarch)->builtin_long; | |
1901 | ainfo->length = cinfo->xlen; | |
1902 | } | |
1903 | else if (ainfo->length <= (2 * cinfo->xlen)) | |
1904 | { | |
1905 | ainfo->type = builtin_type (gdbarch)->builtin_long_long; | |
1906 | ainfo->length = 2 * cinfo->xlen; | |
1907 | } | |
1908 | ||
1909 | /* Recalculate the alignment requirement. */ | |
1910 | ainfo->align = riscv_type_alignment (ainfo->type); | |
1911 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
1912 | break; | |
1913 | ||
1914 | case TYPE_CODE_FLT: | |
1915 | riscv_call_arg_scalar_float (ainfo, cinfo); | |
1916 | break; | |
1917 | ||
1918 | case TYPE_CODE_COMPLEX: | |
1919 | riscv_call_arg_complex_float (ainfo, cinfo); | |
1920 | break; | |
1921 | ||
1922 | case TYPE_CODE_STRUCT: | |
1923 | riscv_call_arg_struct (ainfo, cinfo); | |
1924 | break; | |
1925 | ||
1926 | default: | |
1927 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
1928 | break; | |
1929 | } | |
1930 | } | |
1931 | ||
cab5bb9d AB |
1932 | /* Used for printing debug information about the call argument location in |
1933 | INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base | |
1934 | addresses for the location of pass-by-reference and | |
1935 | arguments-on-the-stack memory areas. */ | |
1936 | ||
dbbb1059 | 1937 | static void |
cab5bb9d | 1938 | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, |
dbbb1059 AB |
1939 | struct riscv_arg_info *info, |
1940 | CORE_ADDR sp_refs, CORE_ADDR sp_args) | |
1941 | { | |
1942 | const char* type_name = TYPE_NAME (info->type); | |
1943 | if (type_name == nullptr) | |
1944 | type_name = "???"; | |
1945 | ||
cab5bb9d AB |
1946 | fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x", |
1947 | type_name, info->length, info->align); | |
dbbb1059 AB |
1948 | switch (info->argloc[0].loc_type) |
1949 | { | |
1950 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
1951 | fprintf_unfiltered |
1952 | (stream, ", register %s", | |
1953 | gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno)); | |
dbbb1059 AB |
1954 | if (info->argloc[0].c_length < info->length) |
1955 | { | |
1956 | switch (info->argloc[1].loc_type) | |
1957 | { | |
1958 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
1959 | fprintf_unfiltered |
1960 | (stream, ", register %s", | |
1961 | gdbarch_register_name (gdbarch, | |
1962 | info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
1963 | break; |
1964 | ||
1965 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
1966 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
1967 | info->argloc[1].loc_data.offset); | |
dbbb1059 AB |
1968 | break; |
1969 | ||
1970 | case riscv_arg_info::location::by_ref: | |
1971 | default: | |
1972 | /* The second location should never be a reference, any | |
1973 | argument being passed by reference just places its address | |
1974 | in the first location and is done. */ | |
1975 | error (_("invalid argument location")); | |
1976 | break; | |
1977 | } | |
1978 | ||
1979 | if (info->argloc[1].c_offset > info->argloc[0].c_length) | |
cab5bb9d AB |
1980 | fprintf_unfiltered (stream, " (offset 0x%x)", |
1981 | info->argloc[1].c_offset); | |
dbbb1059 AB |
1982 | } |
1983 | break; | |
1984 | ||
1985 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
1986 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
1987 | info->argloc[0].loc_data.offset); | |
dbbb1059 AB |
1988 | break; |
1989 | ||
1990 | case riscv_arg_info::location::by_ref: | |
cab5bb9d AB |
1991 | fprintf_unfiltered |
1992 | (stream, ", by reference, data at offset 0x%x (%s)", | |
1993 | info->argloc[0].loc_data.offset, | |
1994 | core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset)); | |
dbbb1059 AB |
1995 | if (info->argloc[1].loc_type |
1996 | == riscv_arg_info::location::in_reg) | |
cab5bb9d AB |
1997 | fprintf_unfiltered |
1998 | (stream, ", address in register %s", | |
1999 | gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2000 | else |
2001 | { | |
2002 | gdb_assert (info->argloc[1].loc_type | |
2003 | == riscv_arg_info::location::on_stack); | |
cab5bb9d AB |
2004 | fprintf_unfiltered |
2005 | (stream, ", address on stack at offset 0x%x (%s)", | |
2006 | info->argloc[1].loc_data.offset, | |
2007 | core_addr_to_string (sp_args + info->argloc[1].loc_data.offset)); | |
dbbb1059 AB |
2008 | } |
2009 | break; | |
2010 | ||
2011 | default: | |
2012 | error ("unknown argument location type"); | |
2013 | } | |
2014 | } | |
2015 | ||
2016 | /* Implement the push dummy call gdbarch callback. */ | |
2017 | ||
2018 | static CORE_ADDR | |
2019 | riscv_push_dummy_call (struct gdbarch *gdbarch, | |
2020 | struct value *function, | |
2021 | struct regcache *regcache, | |
2022 | CORE_ADDR bp_addr, | |
2023 | int nargs, | |
2024 | struct value **args, | |
2025 | CORE_ADDR sp, | |
2026 | int struct_return, | |
2027 | CORE_ADDR struct_addr) | |
2028 | { | |
2029 | int i; | |
2030 | CORE_ADDR sp_args, sp_refs; | |
2031 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2032 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2033 | ||
2034 | struct riscv_arg_info *arg_info = | |
2035 | (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info)); | |
2036 | struct riscv_arg_info *info; | |
2037 | ||
2038 | struct riscv_call_info call_info (gdbarch); | |
2039 | ||
2040 | CORE_ADDR osp = sp; | |
2041 | ||
2042 | /* We'll use register $a0 if we're returning a struct. */ | |
2043 | if (struct_return) | |
2044 | ++call_info.int_regs.next_regnum; | |
2045 | ||
2046 | for (i = 0, info = &arg_info[0]; | |
2047 | i < nargs; | |
2048 | ++i, ++info) | |
2049 | { | |
2050 | struct value *arg_value; | |
2051 | struct type *arg_type; | |
2052 | ||
2053 | arg_value = args[i]; | |
2054 | arg_type = check_typedef (value_type (arg_value)); | |
2055 | ||
2056 | riscv_arg_location (gdbarch, info, &call_info, arg_type); | |
2057 | ||
2058 | if (info->type != arg_type) | |
2059 | arg_value = value_cast (info->type, arg_value); | |
2060 | info->contents = value_contents (arg_value); | |
2061 | } | |
2062 | ||
2063 | /* Adjust the stack pointer and align it. */ | |
2064 | sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT); | |
2065 | sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT); | |
2066 | ||
2067 | if (riscv_debug_infcall > 0) | |
2068 | { | |
2069 | fprintf_unfiltered (gdb_stdlog, "dummy call args:\n"); | |
2070 | fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n", | |
2071 | (riscv_has_fp_abi (gdbarch) ? "is" : "is not")); | |
2072 | fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n", | |
2073 | call_info.xlen, call_info.flen); | |
2074 | if (struct_return) | |
2075 | fprintf_unfiltered (gdb_stdlog, | |
2076 | "[*] struct return pointer in register $A0\n"); | |
2077 | for (i = 0; i < nargs; ++i) | |
2078 | { | |
2079 | struct riscv_arg_info *info = &arg_info [i]; | |
2080 | ||
2081 | fprintf_unfiltered (gdb_stdlog, "[%2d] ", i); | |
cab5bb9d | 2082 | riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args); |
dbbb1059 AB |
2083 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2084 | } | |
2085 | if (call_info.memory.arg_offset > 0 | |
2086 | || call_info.memory.ref_offset > 0) | |
2087 | { | |
cab5bb9d AB |
2088 | fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n", |
2089 | core_addr_to_string (osp)); | |
dbbb1059 | 2090 | fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n", |
cab5bb9d | 2091 | call_info.memory.arg_offset); |
dbbb1059 | 2092 | fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n", |
cab5bb9d | 2093 | call_info.memory.ref_offset); |
fb294655 AB |
2094 | fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n", |
2095 | core_addr_to_string_nz (osp - sp)); | |
dbbb1059 AB |
2096 | } |
2097 | } | |
2098 | ||
2099 | /* Now load the argument into registers, or onto the stack. */ | |
2100 | ||
2101 | if (struct_return) | |
2102 | { | |
2103 | gdb_byte buf[sizeof (LONGEST)]; | |
2104 | ||
2105 | store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr); | |
2106 | regcache_cooked_write (regcache, RISCV_A0_REGNUM, buf); | |
2107 | } | |
2108 | ||
2109 | for (i = 0; i < nargs; ++i) | |
2110 | { | |
2111 | CORE_ADDR dst; | |
2112 | int second_arg_length = 0; | |
2113 | const gdb_byte *second_arg_data; | |
2114 | struct riscv_arg_info *info = &arg_info [i]; | |
2115 | ||
2116 | gdb_assert (info->length > 0); | |
2117 | ||
2118 | switch (info->argloc[0].loc_type) | |
2119 | { | |
2120 | case riscv_arg_info::location::in_reg: | |
2121 | { | |
2122 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2123 | ||
2124 | gdb_assert (info->argloc[0].c_length <= info->length); | |
2125 | memset (tmp, 0, sizeof (tmp)); | |
2126 | memcpy (tmp, info->contents, info->argloc[0].c_length); | |
2127 | regcache_cooked_write (regcache, | |
2128 | info->argloc[0].loc_data.regno, | |
2129 | tmp); | |
2130 | second_arg_length = | |
2131 | ((info->argloc[0].c_length < info->length) | |
2132 | ? info->argloc[1].c_length : 0); | |
2133 | second_arg_data = info->contents + info->argloc[1].c_offset; | |
2134 | } | |
2135 | break; | |
2136 | ||
2137 | case riscv_arg_info::location::on_stack: | |
2138 | dst = sp_args + info->argloc[0].loc_data.offset; | |
2139 | write_memory (dst, info->contents, info->length); | |
2140 | second_arg_length = 0; | |
2141 | break; | |
2142 | ||
2143 | case riscv_arg_info::location::by_ref: | |
2144 | dst = sp_refs + info->argloc[0].loc_data.offset; | |
2145 | write_memory (dst, info->contents, info->length); | |
2146 | ||
2147 | second_arg_length = call_info.xlen; | |
2148 | second_arg_data = (gdb_byte *) &dst; | |
2149 | break; | |
2150 | ||
2151 | default: | |
2152 | error ("unknown argument location type"); | |
2153 | } | |
2154 | ||
2155 | if (second_arg_length > 0) | |
2156 | { | |
2157 | switch (info->argloc[1].loc_type) | |
2158 | { | |
2159 | case riscv_arg_info::location::in_reg: | |
2160 | { | |
2161 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2162 | ||
2163 | gdb_assert (second_arg_length <= call_info.xlen); | |
2164 | memset (tmp, 0, sizeof (tmp)); | |
2165 | memcpy (tmp, second_arg_data, second_arg_length); | |
2166 | regcache_cooked_write (regcache, | |
2167 | info->argloc[1].loc_data.regno, | |
2168 | tmp); | |
2169 | } | |
2170 | break; | |
2171 | ||
2172 | case riscv_arg_info::location::on_stack: | |
2173 | { | |
2174 | CORE_ADDR arg_addr; | |
2175 | ||
2176 | arg_addr = sp_args + info->argloc[1].loc_data.offset; | |
2177 | write_memory (arg_addr, second_arg_data, second_arg_length); | |
2178 | break; | |
2179 | } | |
2180 | ||
2181 | case riscv_arg_info::location::by_ref: | |
2182 | default: | |
2183 | /* The second location should never be a reference, any | |
2184 | argument being passed by reference just places its address | |
2185 | in the first location and is done. */ | |
2186 | error (_("invalid argument location")); | |
2187 | break; | |
2188 | } | |
2189 | } | |
2190 | } | |
2191 | ||
2192 | /* Set the dummy return value to bp_addr. | |
2193 | A dummy breakpoint will be setup to execute the call. */ | |
2194 | ||
2195 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2196 | fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n", |
2197 | core_addr_to_string (bp_addr)); | |
dbbb1059 AB |
2198 | regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr); |
2199 | ||
2200 | /* Finally, update the stack pointer. */ | |
2201 | ||
2202 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2203 | fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n", |
2204 | core_addr_to_string (sp)); | |
dbbb1059 AB |
2205 | regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp); |
2206 | ||
2207 | return sp; | |
2208 | } | |
2209 | ||
2210 | /* Implement the return_value gdbarch method. */ | |
2211 | ||
2212 | static enum return_value_convention | |
2213 | riscv_return_value (struct gdbarch *gdbarch, | |
2214 | struct value *function, | |
2215 | struct type *type, | |
2216 | struct regcache *regcache, | |
2217 | gdb_byte *readbuf, | |
2218 | const gdb_byte *writebuf) | |
2219 | { | |
2220 | enum type_code rv_type = TYPE_CODE (type); | |
2221 | unsigned int rv_size = TYPE_LENGTH (type); | |
2222 | int fp, regnum, flen; | |
2223 | ULONGEST tmp; | |
2224 | struct riscv_call_info call_info (gdbarch); | |
2225 | struct riscv_arg_info info; | |
2226 | struct type *arg_type; | |
2227 | ||
2228 | arg_type = check_typedef (type); | |
2229 | riscv_arg_location (gdbarch, &info, &call_info, arg_type); | |
2230 | ||
2231 | if (riscv_debug_infcall > 0) | |
2232 | { | |
2233 | fprintf_unfiltered (gdb_stdlog, "riscv return value:\n"); | |
2234 | fprintf_unfiltered (gdb_stdlog, "[R] "); | |
cab5bb9d | 2235 | riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0); |
dbbb1059 AB |
2236 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2237 | } | |
2238 | ||
2239 | if (readbuf != nullptr || writebuf != nullptr) | |
2240 | { | |
2241 | int regnum; | |
2242 | ||
2243 | switch (info.argloc[0].loc_type) | |
2244 | { | |
2245 | /* Return value in register(s). */ | |
2246 | case riscv_arg_info::location::in_reg: | |
2247 | { | |
2248 | regnum = info.argloc[0].loc_data.regno; | |
2249 | ||
2250 | if (readbuf) | |
2251 | regcache_cooked_read (regcache, regnum, readbuf); | |
2252 | ||
2253 | if (writebuf) | |
2254 | regcache_cooked_write (regcache, regnum, writebuf); | |
2255 | ||
2256 | /* A return value in register can have a second part in a | |
2257 | second register. */ | |
2258 | if (info.argloc[0].c_length < info.length) | |
2259 | { | |
2260 | switch (info.argloc[1].loc_type) | |
2261 | { | |
2262 | case riscv_arg_info::location::in_reg: | |
2263 | regnum = info.argloc[1].loc_data.regno; | |
2264 | ||
2265 | if (readbuf) | |
2266 | { | |
2267 | readbuf += info.argloc[1].c_offset; | |
2268 | regcache_cooked_read (regcache, regnum, readbuf); | |
2269 | } | |
2270 | ||
2271 | if (writebuf) | |
2272 | { | |
2273 | writebuf += info.argloc[1].c_offset; | |
2274 | regcache_cooked_write (regcache, regnum, writebuf); | |
2275 | } | |
2276 | break; | |
2277 | ||
2278 | case riscv_arg_info::location::by_ref: | |
2279 | case riscv_arg_info::location::on_stack: | |
2280 | default: | |
2281 | error (_("invalid argument location")); | |
2282 | break; | |
2283 | } | |
2284 | } | |
2285 | } | |
2286 | break; | |
2287 | ||
2288 | /* Return value by reference will have its address in A0. */ | |
2289 | case riscv_arg_info::location::by_ref: | |
2290 | { | |
b2970c23 | 2291 | ULONGEST addr; |
dbbb1059 AB |
2292 | |
2293 | regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, | |
2294 | &addr); | |
2295 | if (readbuf != nullptr) | |
2296 | read_memory (addr, readbuf, info.length); | |
2297 | if (writebuf != nullptr) | |
2298 | write_memory (addr, writebuf, info.length); | |
2299 | } | |
2300 | break; | |
2301 | ||
2302 | case riscv_arg_info::location::on_stack: | |
2303 | default: | |
2304 | error (_("invalid argument location")); | |
2305 | break; | |
2306 | } | |
2307 | } | |
2308 | ||
2309 | switch (info.argloc[0].loc_type) | |
2310 | { | |
2311 | case riscv_arg_info::location::in_reg: | |
2312 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2313 | case riscv_arg_info::location::by_ref: | |
2314 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2315 | case riscv_arg_info::location::on_stack: | |
2316 | default: | |
2317 | error (_("invalid argument location")); | |
2318 | } | |
2319 | } | |
2320 | ||
2321 | /* Implement the frame_align gdbarch method. */ | |
2322 | ||
2323 | static CORE_ADDR | |
2324 | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2325 | { | |
2326 | return align_down (addr, 16); | |
2327 | } | |
2328 | ||
2329 | /* Implement the unwind_pc gdbarch method. */ | |
2330 | ||
2331 | static CORE_ADDR | |
2332 | riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2333 | { | |
2334 | return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM); | |
2335 | } | |
2336 | ||
2337 | /* Implement the unwind_sp gdbarch method. */ | |
2338 | ||
2339 | static CORE_ADDR | |
2340 | riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2341 | { | |
2342 | return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM); | |
2343 | } | |
2344 | ||
2345 | /* Implement the dummy_id gdbarch method. */ | |
2346 | ||
2347 | static struct frame_id | |
2348 | riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
2349 | { | |
2350 | return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM), | |
2351 | get_frame_pc (this_frame)); | |
2352 | } | |
2353 | ||
2354 | /* Generate, or return the cached frame cache for the RiscV frame | |
2355 | unwinder. */ | |
2356 | ||
2357 | static struct trad_frame_cache * | |
2358 | riscv_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2359 | { | |
2360 | CORE_ADDR pc; | |
2361 | CORE_ADDR start_addr; | |
2362 | CORE_ADDR stack_addr; | |
2363 | struct trad_frame_cache *this_trad_cache; | |
2364 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2365 | ||
2366 | if ((*this_cache) != NULL) | |
2367 | return (struct trad_frame_cache *) *this_cache; | |
2368 | this_trad_cache = trad_frame_cache_zalloc (this_frame); | |
2369 | (*this_cache) = this_trad_cache; | |
2370 | ||
2371 | trad_frame_set_reg_realreg (this_trad_cache, gdbarch_pc_regnum (gdbarch), | |
2372 | RISCV_RA_REGNUM); | |
2373 | ||
2374 | pc = get_frame_pc (this_frame); | |
2375 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2376 | stack_addr = get_frame_register_signed (this_frame, RISCV_SP_REGNUM); | |
2377 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); | |
2378 | ||
2379 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
2380 | ||
2381 | return this_trad_cache; | |
2382 | } | |
2383 | ||
2384 | /* Implement the this_id callback for RiscV frame unwinder. */ | |
2385 | ||
2386 | static void | |
2387 | riscv_frame_this_id (struct frame_info *this_frame, | |
2388 | void **prologue_cache, | |
2389 | struct frame_id *this_id) | |
2390 | { | |
2391 | struct trad_frame_cache *info; | |
2392 | ||
2393 | info = riscv_frame_cache (this_frame, prologue_cache); | |
2394 | trad_frame_get_id (info, this_id); | |
2395 | } | |
2396 | ||
2397 | /* Implement the prev_register callback for RiscV frame unwinder. */ | |
2398 | ||
2399 | static struct value * | |
2400 | riscv_frame_prev_register (struct frame_info *this_frame, | |
2401 | void **prologue_cache, | |
2402 | int regnum) | |
2403 | { | |
2404 | struct trad_frame_cache *info; | |
2405 | ||
2406 | info = riscv_frame_cache (this_frame, prologue_cache); | |
2407 | return trad_frame_get_register (info, this_frame, regnum); | |
2408 | } | |
2409 | ||
2410 | /* Structure defining the RiscV normal frame unwind functions. Since we | |
2411 | are the fallback unwinder (DWARF unwinder is used first), we use the | |
2412 | default frame sniffer, which always accepts the frame. */ | |
2413 | ||
2414 | static const struct frame_unwind riscv_frame_unwind = | |
2415 | { | |
2416 | /*.type =*/ NORMAL_FRAME, | |
2417 | /*.stop_reason =*/ default_frame_unwind_stop_reason, | |
2418 | /*.this_id =*/ riscv_frame_this_id, | |
2419 | /*.prev_register =*/ riscv_frame_prev_register, | |
2420 | /*.unwind_data =*/ NULL, | |
2421 | /*.sniffer =*/ default_frame_sniffer, | |
2422 | /*.dealloc_cache =*/ NULL, | |
2423 | /*.prev_arch =*/ NULL, | |
2424 | }; | |
2425 | ||
2426 | /* Initialize the current architecture based on INFO. If possible, | |
2427 | re-use an architecture from ARCHES, which is a list of | |
2428 | architectures already created during this debugging session. | |
2429 | ||
2430 | Called e.g. at program startup, when reading a core file, and when | |
2431 | reading a binary file. */ | |
2432 | ||
2433 | static struct gdbarch * | |
2434 | riscv_gdbarch_init (struct gdbarch_info info, | |
2435 | struct gdbarch_list *arches) | |
2436 | { | |
2437 | struct gdbarch *gdbarch; | |
2438 | struct gdbarch_tdep *tdep; | |
2439 | struct gdbarch_tdep tmp_tdep; | |
2440 | bool has_compressed_isa = false; | |
2441 | int i; | |
2442 | ||
2443 | /* Ideally, we'd like to get as much information from the target for | |
2444 | things like register size, and whether the target has floating point | |
2445 | hardware. However, there are some things that the target can't tell | |
2446 | us, like, what ABI is being used. | |
2447 | ||
2448 | So, for now, we take as much information as possible from the ELF, | |
2449 | including things like register size, and FP hardware support, along | |
2450 | with information about the ABI. | |
2451 | ||
2452 | Information about this target is built up in TMP_TDEP, and then we | |
2453 | look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no | |
2454 | match is found we'll create a new gdbarch and copy TMP_TDEP over. */ | |
2455 | memset (&tmp_tdep, 0, sizeof (tmp_tdep)); | |
2456 | ||
2457 | if (info.abfd != NULL | |
2458 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
2459 | { | |
2460 | unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS]; | |
2461 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
2462 | ||
2463 | if (eclass == ELFCLASS32) | |
2464 | tmp_tdep.abi.fields.base_len = 1; | |
2465 | else if (eclass == ELFCLASS64) | |
2466 | tmp_tdep.abi.fields.base_len = 2; | |
2467 | else | |
2468 | internal_error (__FILE__, __LINE__, | |
2469 | _("unknown ELF header class %d"), eclass); | |
2470 | ||
2471 | if (e_flags & EF_RISCV_RVC) | |
2472 | { | |
2473 | has_compressed_isa = true; | |
2474 | tmp_tdep.core_features |= (1 << ('C' - 'A')); | |
2475 | } | |
2476 | ||
2477 | if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE) | |
2478 | { | |
2479 | tmp_tdep.abi.fields.float_abi = 2; | |
2480 | tmp_tdep.core_features |= (1 << ('D' - 'A')); | |
2481 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2482 | } | |
2483 | else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) | |
2484 | { | |
2485 | tmp_tdep.abi.fields.float_abi = 1; | |
2486 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2487 | } | |
2488 | } | |
2489 | else | |
2490 | { | |
2491 | const struct bfd_arch_info *binfo = info.bfd_arch_info; | |
2492 | ||
2493 | if (binfo->bits_per_word == 32) | |
2494 | tmp_tdep.abi.fields.base_len = 1; | |
2495 | else if (binfo->bits_per_word == 64) | |
2496 | tmp_tdep.abi.fields.base_len = 2; | |
2497 | else | |
2498 | internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"), | |
2499 | binfo->bits_per_word); | |
2500 | } | |
2501 | ||
2502 | /* Find a candidate among the list of pre-declared architectures. */ | |
2503 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2504 | arches != NULL; | |
2505 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2506 | if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value) | |
2507 | return arches->gdbarch; | |
2508 | ||
2509 | /* None found, so create a new architecture from the information provided. */ | |
2510 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep); | |
2511 | gdbarch = gdbarch_alloc (&info, tdep); | |
2512 | memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep)); | |
2513 | ||
2514 | /* Target data types. */ | |
2515 | set_gdbarch_short_bit (gdbarch, 16); | |
2516 | set_gdbarch_int_bit (gdbarch, 32); | |
2517 | set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2518 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2519 | set_gdbarch_float_bit (gdbarch, 32); | |
2520 | set_gdbarch_double_bit (gdbarch, 64); | |
2521 | set_gdbarch_long_double_bit (gdbarch, 128); | |
2522 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
2523 | set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2524 | set_gdbarch_char_signed (gdbarch, 0); | |
2525 | ||
2526 | /* Information about the target architecture. */ | |
2527 | set_gdbarch_return_value (gdbarch, riscv_return_value); | |
2528 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc); | |
2529 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind); | |
2530 | ||
2531 | /* Register architecture. */ | |
dbbb1059 | 2532 | set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1); |
dbbb1059 AB |
2533 | set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM); |
2534 | set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM); | |
2535 | set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM); | |
2536 | set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM); | |
2537 | ||
2538 | /* Functions to supply register information. */ | |
2539 | set_gdbarch_register_name (gdbarch, riscv_register_name); | |
2540 | set_gdbarch_register_type (gdbarch, riscv_register_type); | |
2541 | set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info); | |
2542 | set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p); | |
2543 | ||
2544 | /* Functions to analyze frames. */ | |
2545 | set_gdbarch_decr_pc_after_break (gdbarch, (has_compressed_isa ? 2 : 4)); | |
2546 | set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue); | |
2547 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2548 | set_gdbarch_frame_align (gdbarch, riscv_frame_align); | |
2549 | ||
2550 | /* Functions to access frame data. */ | |
2551 | set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc); | |
2552 | set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp); | |
2553 | ||
2554 | /* Functions handling dummy frames. */ | |
2555 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
2556 | set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code); | |
2557 | set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call); | |
2558 | set_gdbarch_dummy_id (gdbarch, riscv_dummy_id); | |
2559 | ||
2560 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our own | |
2561 | unwinder. */ | |
2562 | dwarf2_append_unwinders (gdbarch); | |
2563 | frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind); | |
2564 | ||
dbbb1059 AB |
2565 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) |
2566 | user_reg_add (gdbarch, riscv_register_aliases[i].name, | |
2567 | value_of_riscv_user_reg, &riscv_register_aliases[i].regnum); | |
2568 | ||
2569 | return gdbarch; | |
2570 | } | |
2571 | ||
2572 | ||
2573 | /* Allocate new riscv_inferior_data object. */ | |
2574 | ||
2575 | static struct riscv_inferior_data * | |
2576 | riscv_new_inferior_data (void) | |
2577 | { | |
2578 | struct riscv_inferior_data *inf_data | |
2579 | = new (struct riscv_inferior_data); | |
2580 | inf_data->misa_read = false; | |
2581 | return inf_data; | |
2582 | } | |
2583 | ||
2584 | /* Free inferior data. */ | |
2585 | ||
2586 | static void | |
2587 | riscv_inferior_data_cleanup (struct inferior *inf, void *data) | |
2588 | { | |
2589 | struct riscv_inferior_data *inf_data = | |
2590 | static_cast <struct riscv_inferior_data *> (data); | |
2591 | delete (inf_data); | |
2592 | } | |
2593 | ||
2594 | /* Return riscv_inferior_data for the given INFERIOR. If not yet created, | |
2595 | construct it. */ | |
2596 | ||
2597 | struct riscv_inferior_data * | |
2598 | riscv_inferior_data (struct inferior *const inf) | |
2599 | { | |
2600 | struct riscv_inferior_data *inf_data; | |
2601 | ||
2602 | gdb_assert (inf != NULL); | |
2603 | ||
2604 | inf_data | |
2605 | = (struct riscv_inferior_data *) inferior_data (inf, riscv_inferior_data_reg); | |
2606 | if (inf_data == NULL) | |
2607 | { | |
2608 | inf_data = riscv_new_inferior_data (); | |
2609 | set_inferior_data (inf, riscv_inferior_data_reg, inf_data); | |
2610 | } | |
2611 | ||
2612 | return inf_data; | |
2613 | } | |
2614 | ||
2615 | /* Free the inferior data when an inferior exits. */ | |
2616 | ||
2617 | static void | |
2618 | riscv_invalidate_inferior_data (struct inferior *inf) | |
2619 | { | |
2620 | struct riscv_inferior_data *inf_data; | |
2621 | ||
2622 | gdb_assert (inf != NULL); | |
2623 | ||
2624 | /* Don't call RISCV_INFERIOR_DATA as we don't want to create the data if | |
2625 | we've not already created it by this point. */ | |
2626 | inf_data | |
2627 | = (struct riscv_inferior_data *) inferior_data (inf, riscv_inferior_data_reg); | |
2628 | if (inf_data != NULL) | |
2629 | { | |
2630 | delete (inf_data); | |
2631 | set_inferior_data (inf, riscv_inferior_data_reg, NULL); | |
2632 | } | |
2633 | } | |
2634 | ||
2635 | void | |
2636 | _initialize_riscv_tdep (void) | |
2637 | { | |
2638 | gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL); | |
2639 | ||
2640 | /* Register per-inferior data. */ | |
2641 | riscv_inferior_data_reg | |
2642 | = register_inferior_data_with_cleanup (NULL, riscv_inferior_data_cleanup); | |
2643 | ||
2644 | /* Observers used to invalidate the inferior data when needed. */ | |
2645 | observer_attach_inferior_exit (riscv_invalidate_inferior_data); | |
2646 | observer_attach_inferior_appeared (riscv_invalidate_inferior_data); | |
2647 | ||
2648 | /* Add root prefix command for all "set debug riscv" and "show debug | |
2649 | riscv" commands. */ | |
2650 | add_prefix_cmd ("riscv", no_class, set_debug_riscv_command, | |
2651 | _("RISC-V specific debug commands."), | |
2652 | &setdebugriscvcmdlist, "set debug riscv ", 0, | |
2653 | &setdebuglist); | |
2654 | ||
2655 | add_prefix_cmd ("riscv", no_class, show_debug_riscv_command, | |
2656 | _("RISC-V specific debug commands."), | |
2657 | &showdebugriscvcmdlist, "show debug riscv ", 0, | |
2658 | &showdebuglist); | |
2659 | ||
2660 | add_setshow_zuinteger_cmd ("infcall", class_maintenance, | |
2661 | &riscv_debug_infcall, _("\ | |
2662 | Set riscv inferior call debugging."), _("\ | |
2663 | Show riscv inferior call debugging."), _("\ | |
2664 | When non-zero, print debugging information for the riscv specific parts\n\ | |
2665 | of the inferior call mechanism."), | |
2666 | NULL, | |
2667 | show_riscv_debug_variable, | |
2668 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
2669 | ||
2670 | /* Add root prefix command for all "set riscv" and "show riscv" commands. */ | |
2671 | add_prefix_cmd ("riscv", no_class, set_riscv_command, | |
2672 | _("RISC-V specific commands."), | |
2673 | &setriscvcmdlist, "set riscv ", 0, &setlist); | |
2674 | ||
2675 | add_prefix_cmd ("riscv", no_class, show_riscv_command, | |
2676 | _("RISC-V specific commands."), | |
2677 | &showriscvcmdlist, "show riscv ", 0, &showlist); | |
2678 | ||
2679 | ||
2680 | use_compressed_breakpoints = AUTO_BOOLEAN_AUTO; | |
2681 | add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class, | |
2682 | &use_compressed_breakpoints, | |
2683 | _("\ | |
2684 | Set debugger's use of compressed breakpoints."), _(" \ | |
2685 | Show debugger's use of compressed breakpoints."), _("\ | |
2686 | Debugging compressed code requires compressed breakpoints to be used. If\n \ | |
2687 | left to 'auto' then gdb will use them if $misa indicates the C extension\n \ | |
2688 | is supported. If that doesn't give the correct behavior, then this option\n\ | |
2689 | can be used."), | |
2690 | NULL, | |
2691 | show_use_compressed_breakpoints, | |
2692 | &setriscvcmdlist, | |
2693 | &showriscvcmdlist); | |
2694 | } |