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dbbb1059 AB |
1 | /* Target-dependent code for the RISC-V architecture, for GDB. |
2 | ||
3 | Copyright (C) 2018 Free Software Foundation, Inc. | |
4 | ||
dbbb1059 AB |
5 | This file is part of GDB. |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
23 | #include "symtab.h" | |
24 | #include "value.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "language.h" | |
27 | #include "gdbcore.h" | |
28 | #include "symfile.h" | |
29 | #include "objfiles.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "target.h" | |
32 | #include "arch-utils.h" | |
33 | #include "regcache.h" | |
34 | #include "osabi.h" | |
35 | #include "riscv-tdep.h" | |
36 | #include "block.h" | |
37 | #include "reggroups.h" | |
38 | #include "opcode/riscv.h" | |
39 | #include "elf/riscv.h" | |
40 | #include "elf-bfd.h" | |
41 | #include "symcat.h" | |
42 | #include "dis-asm.h" | |
43 | #include "frame-unwind.h" | |
44 | #include "frame-base.h" | |
45 | #include "trad-frame.h" | |
46 | #include "infcall.h" | |
47 | #include "floatformat.h" | |
48 | #include "remote.h" | |
49 | #include "target-descriptions.h" | |
50 | #include "dwarf2-frame.h" | |
51 | #include "user-regs.h" | |
52 | #include "valprint.h" | |
53 | #include "common-defs.h" | |
54 | #include "opcode/riscv-opc.h" | |
55 | #include "cli/cli-decode.h" | |
76727919 | 56 | #include "observable.h" |
78a3b0fa | 57 | #include "prologue-value.h" |
dbbb1059 AB |
58 | |
59 | /* The stack must be 16-byte aligned. */ | |
60 | #define SP_ALIGNMENT 16 | |
61 | ||
62 | /* Forward declarations. */ | |
63 | static bool riscv_has_feature (struct gdbarch *gdbarch, char feature); | |
dbbb1059 AB |
64 | |
65 | /* Define a series of is_XXX_insn functions to check if the value INSN | |
66 | is an instance of instruction XXX. */ | |
67 | #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ | |
68 | static inline bool is_ ## INSN_NAME ## _insn (long insn) \ | |
69 | { \ | |
70 | return (insn & INSN_MASK) == INSN_MATCH; \ | |
71 | } | |
72 | #include "opcode/riscv-opc.h" | |
73 | #undef DECLARE_INSN | |
74 | ||
78a3b0fa AB |
75 | /* Cached information about a frame. */ |
76 | ||
77 | struct riscv_unwind_cache | |
78 | { | |
79 | /* The register from which we can calculate the frame base. This is | |
80 | usually $sp or $fp. */ | |
81 | int frame_base_reg; | |
82 | ||
83 | /* The offset from the current value in register FRAME_BASE_REG to the | |
84 | actual frame base address. */ | |
85 | int frame_base_offset; | |
86 | ||
87 | /* Information about previous register values. */ | |
88 | struct trad_frame_saved_reg *regs; | |
89 | ||
90 | /* The id for this frame. */ | |
91 | struct frame_id this_id; | |
92 | ||
93 | /* The base (stack) address for this frame. This is the stack pointer | |
94 | value on entry to this frame before any adjustments are made. */ | |
95 | CORE_ADDR frame_base; | |
96 | }; | |
97 | ||
dbbb1059 AB |
98 | /* Architectural name for core registers. */ |
99 | ||
100 | static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] = | |
101 | { | |
102 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
103 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
104 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
105 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", | |
106 | "pc", | |
107 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
108 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
109 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
110 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
111 | }; | |
112 | ||
113 | /* Maps "pretty" register names onto their GDB register number. */ | |
114 | ||
115 | struct register_alias | |
116 | { | |
117 | /* The register alias. Usually more descriptive than the | |
118 | architectural name of the register. */ | |
119 | const char *name; | |
120 | ||
121 | /* The GDB register number. */ | |
122 | int regnum; | |
123 | }; | |
124 | ||
125 | /* Table of register aliases. */ | |
126 | ||
127 | static const struct register_alias riscv_register_aliases[] = | |
128 | { | |
129 | { "zero", 0 }, | |
130 | { "ra", 1 }, | |
131 | { "sp", 2 }, | |
132 | { "gp", 3 }, | |
133 | { "tp", 4 }, | |
134 | { "t0", 5 }, | |
135 | { "t1", 6 }, | |
136 | { "t2", 7 }, | |
dbbb1059 | 137 | { "s0", 8 }, |
41823f29 | 138 | { "fp", 8 }, |
dbbb1059 AB |
139 | { "s1", 9 }, |
140 | { "a0", 10 }, | |
141 | { "a1", 11 }, | |
142 | { "a2", 12 }, | |
143 | { "a3", 13 }, | |
144 | { "a4", 14 }, | |
145 | { "a5", 15 }, | |
146 | { "a6", 16 }, | |
147 | { "a7", 17 }, | |
148 | { "s2", 18 }, | |
149 | { "s3", 19 }, | |
150 | { "s4", 20 }, | |
151 | { "s5", 21 }, | |
152 | { "s6", 22 }, | |
153 | { "s7", 23 }, | |
154 | { "s8", 24 }, | |
155 | { "s9", 25 }, | |
156 | { "s10", 26 }, | |
157 | { "s11", 27 }, | |
158 | { "t3", 28 }, | |
159 | { "t4", 29 }, | |
160 | { "t5", 30 }, | |
161 | { "t6", 31 }, | |
162 | /* pc is 32. */ | |
163 | { "ft0", 33 }, | |
164 | { "ft1", 34 }, | |
165 | { "ft2", 35 }, | |
166 | { "ft3", 36 }, | |
167 | { "ft4", 37 }, | |
168 | { "ft5", 38 }, | |
169 | { "ft6", 39 }, | |
170 | { "ft7", 40 }, | |
171 | { "fs0", 41 }, | |
172 | { "fs1", 42 }, | |
173 | { "fa0", 43 }, | |
174 | { "fa1", 44 }, | |
175 | { "fa2", 45 }, | |
176 | { "fa3", 46 }, | |
177 | { "fa4", 47 }, | |
178 | { "fa5", 48 }, | |
179 | { "fa6", 49 }, | |
180 | { "fa7", 50 }, | |
181 | { "fs2", 51 }, | |
182 | { "fs3", 52 }, | |
183 | { "fs4", 53 }, | |
184 | { "fs5", 54 }, | |
185 | { "fs6", 55 }, | |
186 | { "fs7", 56 }, | |
187 | { "fs8", 57 }, | |
188 | { "fs9", 58 }, | |
189 | { "fs10", 59 }, | |
190 | { "fs11", 60 }, | |
191 | { "ft8", 61 }, | |
192 | { "ft9", 62 }, | |
193 | { "ft10", 63 }, | |
194 | { "ft11", 64 }, | |
195 | #define DECLARE_CSR(name, num) { #name, (num) + 65 }, | |
196 | #include "opcode/riscv-opc.h" | |
197 | #undef DECLARE_CSR | |
198 | }; | |
199 | ||
200 | /* Controls whether we place compressed breakpoints or not. When in auto | |
201 | mode GDB tries to determine if the target supports compressed | |
202 | breakpoints, and uses them if it does. */ | |
203 | ||
204 | static enum auto_boolean use_compressed_breakpoints; | |
205 | ||
206 | /* The show callback for 'show riscv use-compressed-breakpoints'. */ | |
207 | ||
208 | static void | |
209 | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, | |
210 | struct cmd_list_element *c, | |
211 | const char *value) | |
212 | { | |
dbbb1059 AB |
213 | fprintf_filtered (file, |
214 | _("Debugger's use of compressed breakpoints is set " | |
f37bc8b1 | 215 | "to %s.\n"), value); |
dbbb1059 AB |
216 | } |
217 | ||
218 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
219 | ||
220 | static struct cmd_list_element *setriscvcmdlist = NULL; | |
221 | static struct cmd_list_element *showriscvcmdlist = NULL; | |
222 | ||
223 | /* The show callback for the 'show riscv' prefix command. */ | |
224 | ||
225 | static void | |
226 | show_riscv_command (const char *args, int from_tty) | |
227 | { | |
228 | help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout); | |
229 | } | |
230 | ||
231 | /* The set callback for the 'set riscv' prefix command. */ | |
232 | ||
233 | static void | |
234 | set_riscv_command (const char *args, int from_tty) | |
235 | { | |
236 | printf_unfiltered | |
237 | (_("\"set riscv\" must be followed by an appropriate subcommand.\n")); | |
238 | help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout); | |
239 | } | |
240 | ||
241 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
242 | ||
243 | static struct cmd_list_element *setdebugriscvcmdlist = NULL; | |
244 | static struct cmd_list_element *showdebugriscvcmdlist = NULL; | |
245 | ||
246 | /* The show callback for the 'show debug riscv' prefix command. */ | |
247 | ||
248 | static void | |
249 | show_debug_riscv_command (const char *args, int from_tty) | |
250 | { | |
251 | help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout); | |
252 | } | |
253 | ||
254 | /* The set callback for the 'set debug riscv' prefix command. */ | |
255 | ||
256 | static void | |
257 | set_debug_riscv_command (const char *args, int from_tty) | |
258 | { | |
259 | printf_unfiltered | |
260 | (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n")); | |
261 | help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout); | |
262 | } | |
263 | ||
264 | /* The show callback for all 'show debug riscv VARNAME' variables. */ | |
265 | ||
266 | static void | |
267 | show_riscv_debug_variable (struct ui_file *file, int from_tty, | |
268 | struct cmd_list_element *c, | |
269 | const char *value) | |
270 | { | |
271 | fprintf_filtered (file, | |
272 | _("RiscV debug variable `%s' is set to: %s\n"), | |
273 | c->name, value); | |
274 | } | |
275 | ||
f37bc8b1 JB |
276 | /* When this is set to non-zero debugging information about breakpoint |
277 | kinds will be printed. */ | |
278 | ||
279 | static unsigned int riscv_debug_breakpoints = 0; | |
280 | ||
dbbb1059 AB |
281 | /* When this is set to non-zero debugging information about inferior calls |
282 | will be printed. */ | |
283 | ||
284 | static unsigned int riscv_debug_infcall = 0; | |
285 | ||
78a3b0fa AB |
286 | /* When this is set to non-zero debugging information about stack unwinding |
287 | will be printed. */ | |
288 | ||
289 | static unsigned int riscv_debug_unwinder = 0; | |
290 | ||
dbbb1059 AB |
291 | /* Read the MISA register from the target. The register will only be read |
292 | once, and the value read will be cached. If the register can't be read | |
293 | from the target then a default value (0) will be returned. If the | |
294 | pointer READ_P is not null, then the bool pointed to is updated to | |
295 | indicate if the value returned was read from the target (true) or is the | |
296 | default (false). */ | |
297 | ||
298 | static uint32_t | |
299 | riscv_read_misa_reg (bool *read_p) | |
300 | { | |
0b3f9efc | 301 | uint32_t value = 0; |
dbbb1059 | 302 | |
0b3f9efc | 303 | if (target_has_registers) |
dbbb1059 | 304 | { |
dbbb1059 AB |
305 | struct frame_info *frame = get_current_frame (); |
306 | ||
307 | TRY | |
308 | { | |
0b3f9efc AB |
309 | value = get_frame_register_unsigned (frame, |
310 | RISCV_CSR_MISA_REGNUM); | |
dbbb1059 AB |
311 | } |
312 | CATCH (ex, RETURN_MASK_ERROR) | |
313 | { | |
314 | /* Old cores might have MISA located at a different offset. */ | |
315 | value = get_frame_register_unsigned (frame, | |
316 | RISCV_CSR_LEGACY_MISA_REGNUM); | |
317 | } | |
318 | END_CATCH | |
dbbb1059 AB |
319 | } |
320 | ||
0b3f9efc | 321 | return value; |
dbbb1059 AB |
322 | } |
323 | ||
324 | /* Return true if FEATURE is available for the architecture GDBARCH. The | |
325 | FEATURE should be one of the single character feature codes described in | |
326 | the RiscV ISA manual, these are between 'A' and 'Z'. */ | |
327 | ||
328 | static bool | |
329 | riscv_has_feature (struct gdbarch *gdbarch, char feature) | |
330 | { | |
331 | bool have_read_misa = false; | |
332 | uint32_t misa; | |
333 | ||
334 | gdb_assert (feature >= 'A' && feature <= 'Z'); | |
335 | ||
27724bad | 336 | misa = riscv_read_misa_reg (&have_read_misa); |
dbbb1059 AB |
337 | if (!have_read_misa || misa == 0) |
338 | misa = gdbarch_tdep (gdbarch)->core_features; | |
339 | ||
340 | return (misa & (1 << (feature - 'A'))) != 0; | |
341 | } | |
342 | ||
343 | /* Return the width in bytes of the general purpose registers for GDBARCH. | |
344 | Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or | |
345 | RV128. */ | |
346 | ||
411baa47 | 347 | int |
dbbb1059 AB |
348 | riscv_isa_xlen (struct gdbarch *gdbarch) |
349 | { | |
350 | switch (gdbarch_tdep (gdbarch)->abi.fields.base_len) | |
351 | { | |
352 | default: | |
353 | warning (_("unknown xlen size, assuming 4 bytes")); | |
565e0eda | 354 | /* Fall through. */ |
dbbb1059 AB |
355 | case 1: |
356 | return 4; | |
357 | case 2: | |
358 | return 8; | |
359 | case 3: | |
360 | return 16; | |
361 | } | |
362 | } | |
363 | ||
364 | /* Return the width in bytes of the floating point registers for GDBARCH. | |
365 | If this architecture has no floating point registers, then return 0. | |
366 | Possible values are 4, 8, or 16 for depending on which of single, double | |
367 | or quad floating point support is available. */ | |
368 | ||
369 | static int | |
370 | riscv_isa_flen (struct gdbarch *gdbarch) | |
371 | { | |
372 | if (riscv_has_feature (gdbarch, 'Q')) | |
373 | return 16; | |
374 | else if (riscv_has_feature (gdbarch, 'D')) | |
375 | return 8; | |
376 | else if (riscv_has_feature (gdbarch, 'F')) | |
377 | return 4; | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | /* Return true if the target for GDBARCH has floating point hardware. */ | |
383 | ||
384 | static bool | |
385 | riscv_has_fp_regs (struct gdbarch *gdbarch) | |
386 | { | |
387 | return (riscv_isa_flen (gdbarch) > 0); | |
388 | } | |
389 | ||
390 | /* Return true if GDBARCH is using any of the floating point hardware ABIs. */ | |
391 | ||
392 | static bool | |
393 | riscv_has_fp_abi (struct gdbarch *gdbarch) | |
394 | { | |
395 | return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0); | |
396 | } | |
397 | ||
8c49aa89 AB |
398 | /* Return true if REGNO is a floating pointer register. */ |
399 | ||
400 | static bool | |
401 | riscv_is_fp_regno_p (int regno) | |
402 | { | |
403 | return (regno >= RISCV_FIRST_FP_REGNUM | |
404 | && regno <= RISCV_LAST_FP_REGNUM); | |
405 | } | |
406 | ||
dbbb1059 AB |
407 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
408 | ||
409 | static int | |
410 | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
411 | { | |
412 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) | |
413 | { | |
f37bc8b1 JB |
414 | gdb_byte buf[1]; |
415 | ||
416 | /* Read the opcode byte to determine the instruction length. */ | |
417 | read_code (*pcptr, buf, 1); | |
418 | ||
419 | if (riscv_debug_breakpoints) | |
420 | fprintf_unfiltered | |
421 | (gdb_stdlog, | |
422 | "Using %s for breakpoint at %s (instruction length %d)\n", | |
423 | riscv_insn_length (buf[0]) == 2 ? "C.EBREAK" : "EBREAK", | |
424 | paddress (gdbarch, *pcptr), riscv_insn_length (buf[0])); | |
425 | if (riscv_insn_length (buf[0]) == 2) | |
dbbb1059 AB |
426 | return 2; |
427 | else | |
428 | return 4; | |
429 | } | |
430 | else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) | |
431 | return 2; | |
432 | else | |
433 | return 4; | |
434 | } | |
435 | ||
436 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ | |
437 | ||
438 | static const gdb_byte * | |
439 | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
440 | { | |
441 | static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, }; | |
442 | static const gdb_byte c_ebreak[] = { 0x02, 0x90 }; | |
443 | ||
444 | *size = kind; | |
445 | switch (kind) | |
446 | { | |
447 | case 2: | |
448 | return c_ebreak; | |
449 | case 4: | |
450 | return ebreak; | |
451 | default: | |
89a3b63e | 452 | gdb_assert_not_reached (_("unhandled breakpoint kind")); |
dbbb1059 AB |
453 | } |
454 | } | |
455 | ||
456 | /* Callback function for user_reg_add. */ | |
457 | ||
458 | static struct value * | |
459 | value_of_riscv_user_reg (struct frame_info *frame, const void *baton) | |
460 | { | |
461 | const int *reg_p = (const int *) baton; | |
462 | return value_of_register (*reg_p, frame); | |
463 | } | |
464 | ||
465 | /* Implement the register_name gdbarch method. */ | |
466 | ||
467 | static const char * | |
468 | riscv_register_name (struct gdbarch *gdbarch, int regnum) | |
469 | { | |
dbbb1059 AB |
470 | /* Prefer to use the alias. */ |
471 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM) | |
472 | { | |
473 | int i; | |
474 | ||
475 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) | |
476 | if (regnum == riscv_register_aliases[i].regnum) | |
477 | return riscv_register_aliases[i].name; | |
478 | } | |
479 | ||
480 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) | |
481 | return riscv_gdb_reg_names[regnum]; | |
482 | ||
483 | if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM) | |
484 | { | |
485 | static char buf[20]; | |
486 | ||
89a3b63e AB |
487 | xsnprintf (buf, sizeof (buf), "csr%d", |
488 | regnum - RISCV_FIRST_CSR_REGNUM); | |
dbbb1059 AB |
489 | return buf; |
490 | } | |
491 | ||
492 | if (regnum == RISCV_PRIV_REGNUM) | |
493 | return "priv"; | |
494 | ||
495 | return NULL; | |
496 | } | |
497 | ||
dbbb1059 AB |
498 | /* Implement the register_type gdbarch method. */ |
499 | ||
500 | static struct type * | |
501 | riscv_register_type (struct gdbarch *gdbarch, int regnum) | |
502 | { | |
503 | int regsize; | |
504 | ||
505 | if (regnum < RISCV_FIRST_FP_REGNUM) | |
506 | { | |
507 | if (regnum == gdbarch_pc_regnum (gdbarch) | |
508 | || regnum == RISCV_RA_REGNUM) | |
509 | return builtin_type (gdbarch)->builtin_func_ptr; | |
510 | ||
511 | if (regnum == RISCV_FP_REGNUM | |
512 | || regnum == RISCV_SP_REGNUM | |
513 | || regnum == RISCV_GP_REGNUM | |
514 | || regnum == RISCV_TP_REGNUM) | |
515 | return builtin_type (gdbarch)->builtin_data_ptr; | |
516 | ||
517 | /* Remaining GPRs vary in size based on the current ISA. */ | |
518 | regsize = riscv_isa_xlen (gdbarch); | |
519 | switch (regsize) | |
520 | { | |
521 | case 4: | |
522 | return builtin_type (gdbarch)->builtin_uint32; | |
523 | case 8: | |
524 | return builtin_type (gdbarch)->builtin_uint64; | |
525 | case 16: | |
526 | return builtin_type (gdbarch)->builtin_uint128; | |
527 | default: | |
528 | internal_error (__FILE__, __LINE__, | |
529 | _("unknown isa regsize %i"), regsize); | |
530 | } | |
531 | } | |
532 | else if (regnum <= RISCV_LAST_FP_REGNUM) | |
533 | { | |
534 | regsize = riscv_isa_xlen (gdbarch); | |
535 | switch (regsize) | |
536 | { | |
537 | case 4: | |
538 | return builtin_type (gdbarch)->builtin_float; | |
539 | case 8: | |
540 | return builtin_type (gdbarch)->builtin_double; | |
541 | case 16: | |
542 | return builtin_type (gdbarch)->builtin_long_double; | |
543 | default: | |
544 | internal_error (__FILE__, __LINE__, | |
545 | _("unknown isa regsize %i"), regsize); | |
546 | } | |
547 | } | |
548 | else if (regnum == RISCV_PRIV_REGNUM) | |
549 | return builtin_type (gdbarch)->builtin_int8; | |
550 | else | |
551 | { | |
552 | if (regnum == RISCV_CSR_FFLAGS_REGNUM | |
553 | || regnum == RISCV_CSR_FRM_REGNUM | |
554 | || regnum == RISCV_CSR_FCSR_REGNUM) | |
555 | return builtin_type (gdbarch)->builtin_int32; | |
556 | ||
557 | regsize = riscv_isa_xlen (gdbarch); | |
558 | switch (regsize) | |
559 | { | |
560 | case 4: | |
561 | return builtin_type (gdbarch)->builtin_int32; | |
562 | case 8: | |
563 | return builtin_type (gdbarch)->builtin_int64; | |
564 | case 16: | |
565 | return builtin_type (gdbarch)->builtin_int128; | |
566 | default: | |
567 | internal_error (__FILE__, __LINE__, | |
568 | _("unknown isa regsize %i"), regsize); | |
569 | } | |
570 | } | |
571 | } | |
572 | ||
573 | /* Helper for riscv_print_registers_info, prints info for a single register | |
574 | REGNUM. */ | |
575 | ||
576 | static void | |
577 | riscv_print_one_register_info (struct gdbarch *gdbarch, | |
578 | struct ui_file *file, | |
579 | struct frame_info *frame, | |
580 | int regnum) | |
581 | { | |
582 | const char *name = gdbarch_register_name (gdbarch, regnum); | |
583 | struct value *val = value_of_register (regnum, frame); | |
584 | struct type *regtype = value_type (val); | |
585 | int print_raw_format; | |
586 | enum tab_stops { value_column_1 = 15 }; | |
587 | ||
588 | fputs_filtered (name, file); | |
589 | print_spaces_filtered (value_column_1 - strlen (name), file); | |
590 | ||
591 | print_raw_format = (value_entirely_available (val) | |
592 | && !value_optimized_out (val)); | |
593 | ||
594 | if (TYPE_CODE (regtype) == TYPE_CODE_FLT) | |
595 | { | |
596 | struct value_print_options opts; | |
597 | const gdb_byte *valaddr = value_contents_for_printing (val); | |
598 | enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype)); | |
599 | ||
600 | get_user_print_options (&opts); | |
601 | opts.deref_ref = 1; | |
602 | ||
603 | val_print (regtype, | |
604 | value_embedded_offset (val), 0, | |
605 | file, 0, val, &opts, current_language); | |
606 | ||
607 | if (print_raw_format) | |
608 | { | |
609 | fprintf_filtered (file, "\t(raw "); | |
610 | print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order, | |
611 | true); | |
612 | fprintf_filtered (file, ")"); | |
613 | } | |
614 | } | |
615 | else | |
616 | { | |
617 | struct value_print_options opts; | |
618 | ||
619 | /* Print the register in hex. */ | |
620 | get_formatted_print_options (&opts, 'x'); | |
621 | opts.deref_ref = 1; | |
622 | val_print (regtype, | |
623 | value_embedded_offset (val), 0, | |
624 | file, 0, val, &opts, current_language); | |
625 | ||
626 | if (print_raw_format) | |
627 | { | |
628 | if (regnum == RISCV_CSR_MSTATUS_REGNUM) | |
629 | { | |
630 | LONGEST d; | |
631 | int size = register_size (gdbarch, regnum); | |
632 | unsigned xlen; | |
633 | ||
634 | d = value_as_long (val); | |
635 | xlen = size * 4; | |
636 | fprintf_filtered (file, | |
637 | "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " | |
638 | "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " | |
639 | "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X", | |
640 | (int) ((d >> (xlen - 1)) & 0x1), | |
641 | (int) ((d >> 24) & 0x1f), | |
642 | (int) ((d >> 19) & 0x1), | |
643 | (int) ((d >> 18) & 0x1), | |
644 | (int) ((d >> 17) & 0x1), | |
645 | (int) ((d >> 15) & 0x3), | |
646 | (int) ((d >> 13) & 0x3), | |
647 | (int) ((d >> 11) & 0x3), | |
648 | (int) ((d >> 9) & 0x3), | |
649 | (int) ((d >> 8) & 0x1), | |
650 | (int) ((d >> 7) & 0x1), | |
651 | (int) ((d >> 6) & 0x1), | |
652 | (int) ((d >> 5) & 0x1), | |
653 | (int) ((d >> 4) & 0x1), | |
654 | (int) ((d >> 3) & 0x1), | |
655 | (int) ((d >> 2) & 0x1), | |
656 | (int) ((d >> 1) & 0x1), | |
657 | (int) ((d >> 0) & 0x1)); | |
658 | } | |
659 | else if (regnum == RISCV_CSR_MISA_REGNUM) | |
660 | { | |
661 | int base; | |
662 | unsigned xlen, i; | |
663 | LONGEST d; | |
664 | ||
665 | d = value_as_long (val); | |
666 | base = d >> 30; | |
667 | xlen = 16; | |
668 | ||
669 | for (; base > 0; base--) | |
670 | xlen *= 2; | |
671 | fprintf_filtered (file, "\tRV%d", xlen); | |
672 | ||
673 | for (i = 0; i < 26; i++) | |
674 | { | |
675 | if (d & (1 << i)) | |
676 | fprintf_filtered (file, "%c", 'A' + i); | |
677 | } | |
678 | } | |
679 | else if (regnum == RISCV_CSR_FCSR_REGNUM | |
680 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
681 | || regnum == RISCV_CSR_FRM_REGNUM) | |
682 | { | |
683 | LONGEST d; | |
684 | ||
685 | d = value_as_long (val); | |
686 | ||
687 | fprintf_filtered (file, "\t"); | |
688 | if (regnum != RISCV_CSR_FRM_REGNUM) | |
689 | fprintf_filtered (file, | |
690 | "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d", | |
691 | (int) ((d >> 5) & 0x7), | |
692 | (int) ((d >> 4) & 0x1), | |
693 | (int) ((d >> 3) & 0x1), | |
694 | (int) ((d >> 2) & 0x1), | |
695 | (int) ((d >> 1) & 0x1), | |
696 | (int) ((d >> 0) & 0x1)); | |
697 | ||
698 | if (regnum != RISCV_CSR_FFLAGS_REGNUM) | |
699 | { | |
700 | static const char * const sfrm[] = | |
701 | { | |
702 | "RNE (round to nearest; ties to even)", | |
703 | "RTZ (Round towards zero)", | |
704 | "RDN (Round down towards -INF)", | |
705 | "RUP (Round up towards +INF)", | |
706 | "RMM (Round to nearest; ties to max magnitude)", | |
707 | "INVALID[5]", | |
708 | "INVALID[6]", | |
709 | "dynamic rounding mode", | |
710 | }; | |
711 | int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) | |
712 | ? (d >> 5) : d) & 0x3; | |
713 | ||
714 | fprintf_filtered (file, "%sFRM:%i [%s]", | |
715 | (regnum == RISCV_CSR_FCSR_REGNUM | |
716 | ? " " : ""), | |
717 | frm, sfrm[frm]); | |
718 | } | |
719 | } | |
720 | else if (regnum == RISCV_PRIV_REGNUM) | |
721 | { | |
722 | LONGEST d; | |
723 | uint8_t priv; | |
724 | ||
725 | d = value_as_long (val); | |
726 | priv = d & 0xff; | |
727 | ||
728 | if (priv < 4) | |
729 | { | |
730 | static const char * const sprv[] = | |
731 | { | |
732 | "User/Application", | |
733 | "Supervisor", | |
734 | "Hypervisor", | |
735 | "Machine" | |
736 | }; | |
737 | fprintf_filtered (file, "\tprv:%d [%s]", | |
738 | priv, sprv[priv]); | |
739 | } | |
740 | else | |
741 | fprintf_filtered (file, "\tprv:%d [INVALID]", priv); | |
742 | } | |
743 | else | |
744 | { | |
745 | /* If not a vector register, print it also according to its | |
746 | natural format. */ | |
747 | if (TYPE_VECTOR (regtype) == 0) | |
748 | { | |
749 | get_user_print_options (&opts); | |
750 | opts.deref_ref = 1; | |
751 | fprintf_filtered (file, "\t"); | |
752 | val_print (regtype, | |
753 | value_embedded_offset (val), 0, | |
754 | file, 0, val, &opts, current_language); | |
755 | } | |
756 | } | |
757 | } | |
758 | } | |
759 | fprintf_filtered (file, "\n"); | |
760 | } | |
761 | ||
762 | /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member | |
763 | of REGGROUP? */ | |
764 | ||
765 | static int | |
766 | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
767 | struct reggroup *reggroup) | |
768 | { | |
dbbb1059 AB |
769 | unsigned int i; |
770 | ||
771 | /* Used by 'info registers' and 'info registers <groupname>'. */ | |
772 | ||
773 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
774 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
775 | return 0; | |
776 | ||
777 | if (reggroup == all_reggroup) | |
778 | { | |
779 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM) | |
780 | return 1; | |
781 | /* Only include CSRs that have aliases. */ | |
782 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) | |
783 | { | |
784 | if (regnum == riscv_register_aliases[i].regnum) | |
785 | return 1; | |
786 | } | |
787 | return 0; | |
788 | } | |
789 | else if (reggroup == float_reggroup) | |
8c49aa89 AB |
790 | return (riscv_is_fp_regno_p (regnum) |
791 | || regnum == RISCV_CSR_FCSR_REGNUM | |
792 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
793 | || regnum == RISCV_CSR_FRM_REGNUM); | |
dbbb1059 AB |
794 | else if (reggroup == general_reggroup) |
795 | return regnum < RISCV_FIRST_FP_REGNUM; | |
796 | else if (reggroup == restore_reggroup || reggroup == save_reggroup) | |
797 | { | |
798 | if (riscv_has_fp_regs (gdbarch)) | |
799 | return regnum <= RISCV_LAST_FP_REGNUM; | |
800 | else | |
801 | return regnum < RISCV_FIRST_FP_REGNUM; | |
802 | } | |
803 | else if (reggroup == system_reggroup) | |
804 | { | |
805 | if (regnum == RISCV_PRIV_REGNUM) | |
806 | return 1; | |
807 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM) | |
808 | return 0; | |
809 | /* Only include CSRs that have aliases. */ | |
810 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) | |
811 | { | |
812 | if (regnum == riscv_register_aliases[i].regnum) | |
813 | return 1; | |
814 | } | |
815 | return 0; | |
816 | } | |
817 | else if (reggroup == vector_reggroup) | |
818 | return 0; | |
819 | else | |
820 | return 0; | |
821 | } | |
822 | ||
823 | /* Implement the print_registers_info gdbarch method. This is used by | |
824 | 'info registers' and 'info all-registers'. */ | |
825 | ||
826 | static void | |
827 | riscv_print_registers_info (struct gdbarch *gdbarch, | |
828 | struct ui_file *file, | |
829 | struct frame_info *frame, | |
830 | int regnum, int print_all) | |
831 | { | |
832 | if (regnum != -1) | |
833 | { | |
834 | /* Print one specified register. */ | |
835 | gdb_assert (regnum <= RISCV_LAST_REGNUM); | |
836 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
837 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
838 | error (_("Not a valid register for the current processor type")); | |
839 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
840 | } | |
841 | else | |
842 | { | |
843 | struct reggroup *reggroup; | |
844 | ||
845 | if (print_all) | |
846 | reggroup = all_reggroup; | |
847 | else | |
848 | reggroup = general_reggroup; | |
849 | ||
850 | for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum) | |
851 | { | |
852 | /* Zero never changes, so might as well hide by default. */ | |
853 | if (regnum == RISCV_ZERO_REGNUM && !print_all) | |
854 | continue; | |
855 | ||
856 | /* Registers with no name are not valid on this ISA. */ | |
857 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
858 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
859 | continue; | |
860 | ||
861 | /* Is the register in the group we're interested in? */ | |
862 | if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup)) | |
863 | continue; | |
864 | ||
865 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
866 | } | |
867 | } | |
868 | } | |
869 | ||
870 | /* Class that handles one decoded RiscV instruction. */ | |
871 | ||
872 | class riscv_insn | |
873 | { | |
874 | public: | |
875 | ||
876 | /* Enum of all the opcodes that GDB cares about during the prologue scan. */ | |
877 | enum opcode | |
878 | { | |
879 | /* Unknown value is used at initialisation time. */ | |
880 | UNKNOWN = 0, | |
881 | ||
882 | /* These instructions are all the ones we are interested in during the | |
883 | prologue scan. */ | |
884 | ADD, | |
885 | ADDI, | |
886 | ADDIW, | |
887 | ADDW, | |
888 | AUIPC, | |
889 | LUI, | |
890 | SD, | |
891 | SW, | |
5c720ed8 JW |
892 | /* These are needed for software breakopint support. */ |
893 | JAL, | |
894 | JALR, | |
895 | BEQ, | |
896 | BNE, | |
897 | BLT, | |
898 | BGE, | |
899 | BLTU, | |
900 | BGEU, | |
901 | /* These are needed for stepping over atomic sequences. */ | |
902 | LR, | |
903 | SC, | |
dbbb1059 AB |
904 | |
905 | /* Other instructions are not interesting during the prologue scan, and | |
906 | are ignored. */ | |
907 | OTHER | |
908 | }; | |
909 | ||
910 | riscv_insn () | |
911 | : m_length (0), | |
912 | m_opcode (OTHER), | |
913 | m_rd (0), | |
914 | m_rs1 (0), | |
915 | m_rs2 (0) | |
916 | { | |
917 | /* Nothing. */ | |
918 | } | |
919 | ||
920 | void decode (struct gdbarch *gdbarch, CORE_ADDR pc); | |
921 | ||
922 | /* Get the length of the instruction in bytes. */ | |
923 | int length () const | |
924 | { return m_length; } | |
925 | ||
926 | /* Get the opcode for this instruction. */ | |
927 | enum opcode opcode () const | |
928 | { return m_opcode; } | |
929 | ||
930 | /* Get destination register field for this instruction. This is only | |
931 | valid if the OPCODE implies there is such a field for this | |
932 | instruction. */ | |
933 | int rd () const | |
934 | { return m_rd; } | |
935 | ||
936 | /* Get the RS1 register field for this instruction. This is only valid | |
937 | if the OPCODE implies there is such a field for this instruction. */ | |
938 | int rs1 () const | |
939 | { return m_rs1; } | |
940 | ||
941 | /* Get the RS2 register field for this instruction. This is only valid | |
942 | if the OPCODE implies there is such a field for this instruction. */ | |
943 | int rs2 () const | |
944 | { return m_rs2; } | |
945 | ||
946 | /* Get the immediate for this instruction in signed form. This is only | |
947 | valid if the OPCODE implies there is such a field for this | |
948 | instruction. */ | |
949 | int imm_signed () const | |
950 | { return m_imm.s; } | |
951 | ||
952 | private: | |
953 | ||
954 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ | |
955 | int decode_register_index (unsigned long opcode, int offset) | |
956 | { | |
957 | return (opcode >> offset) & 0x1F; | |
958 | } | |
959 | ||
5c720ed8 JW |
960 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ |
961 | int decode_register_index_short (unsigned long opcode, int offset) | |
962 | { | |
963 | return ((opcode >> offset) & 0x7) + 8; | |
964 | } | |
965 | ||
dbbb1059 AB |
966 | /* Helper for DECODE, decode 32-bit R-type instruction. */ |
967 | void decode_r_type_insn (enum opcode opcode, ULONGEST ival) | |
968 | { | |
969 | m_opcode = opcode; | |
970 | m_rd = decode_register_index (ival, OP_SH_RD); | |
971 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
972 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
973 | } | |
974 | ||
975 | /* Helper for DECODE, decode 16-bit compressed R-type instruction. */ | |
976 | void decode_cr_type_insn (enum opcode opcode, ULONGEST ival) | |
977 | { | |
978 | m_opcode = opcode; | |
979 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
980 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
981 | } | |
982 | ||
983 | /* Helper for DECODE, decode 32-bit I-type instruction. */ | |
984 | void decode_i_type_insn (enum opcode opcode, ULONGEST ival) | |
985 | { | |
986 | m_opcode = opcode; | |
987 | m_rd = decode_register_index (ival, OP_SH_RD); | |
988 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
989 | m_imm.s = EXTRACT_ITYPE_IMM (ival); | |
990 | } | |
991 | ||
992 | /* Helper for DECODE, decode 16-bit compressed I-type instruction. */ | |
993 | void decode_ci_type_insn (enum opcode opcode, ULONGEST ival) | |
994 | { | |
995 | m_opcode = opcode; | |
996 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
997 | m_imm.s = EXTRACT_RVC_IMM (ival); | |
998 | } | |
999 | ||
1000 | /* Helper for DECODE, decode 32-bit S-type instruction. */ | |
1001 | void decode_s_type_insn (enum opcode opcode, ULONGEST ival) | |
1002 | { | |
1003 | m_opcode = opcode; | |
1004 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1005 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1006 | m_imm.s = EXTRACT_STYPE_IMM (ival); | |
1007 | } | |
1008 | ||
ff3a05b3 AB |
1009 | /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate |
1010 | encoding is different for each CS format instruction, so extracting | |
1011 | the immediate is left up to the caller, who should pass the extracted | |
1012 | immediate value through in IMM. */ | |
1013 | void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1014 | { | |
1015 | m_opcode = opcode; | |
1016 | m_imm.s = imm; | |
1017 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1018 | m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S); | |
1019 | } | |
1020 | ||
1021 | /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate | |
1022 | encoding is different for each CSS format instruction, so extracting | |
1023 | the immediate is left up to the caller, who should pass the extracted | |
1024 | immediate value through in IMM. */ | |
1025 | void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1026 | { | |
1027 | m_opcode = opcode; | |
1028 | m_imm.s = imm; | |
1029 | m_rs1 = RISCV_SP_REGNUM; | |
1030 | /* Not a compressed register number in this case. */ | |
1031 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
1032 | } | |
1033 | ||
dbbb1059 AB |
1034 | /* Helper for DECODE, decode 32-bit U-type instruction. */ |
1035 | void decode_u_type_insn (enum opcode opcode, ULONGEST ival) | |
1036 | { | |
1037 | m_opcode = opcode; | |
1038 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1039 | m_imm.s = EXTRACT_UTYPE_IMM (ival); | |
1040 | } | |
1041 | ||
5c720ed8 JW |
1042 | /* Helper for DECODE, decode 32-bit J-type instruction. */ |
1043 | void decode_j_type_insn (enum opcode opcode, ULONGEST ival) | |
1044 | { | |
1045 | m_opcode = opcode; | |
1046 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1047 | m_imm.s = EXTRACT_UJTYPE_IMM (ival); | |
1048 | } | |
1049 | ||
1050 | /* Helper for DECODE, decode 32-bit J-type instruction. */ | |
1051 | void decode_cj_type_insn (enum opcode opcode, ULONGEST ival) | |
1052 | { | |
1053 | m_opcode = opcode; | |
1054 | m_imm.s = EXTRACT_RVC_J_IMM (ival); | |
1055 | } | |
1056 | ||
1057 | void decode_b_type_insn (enum opcode opcode, ULONGEST ival) | |
1058 | { | |
1059 | m_opcode = opcode; | |
1060 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1061 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1062 | m_imm.s = EXTRACT_SBTYPE_IMM (ival); | |
1063 | } | |
1064 | ||
1065 | void decode_cb_type_insn (enum opcode opcode, ULONGEST ival) | |
1066 | { | |
1067 | m_opcode = opcode; | |
1068 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1069 | m_imm.s = EXTRACT_RVC_B_IMM (ival); | |
1070 | } | |
1071 | ||
dbbb1059 AB |
1072 | /* Fetch instruction from target memory at ADDR, return the content of |
1073 | the instruction, and update LEN with the instruction length. */ | |
1074 | static ULONGEST fetch_instruction (struct gdbarch *gdbarch, | |
1075 | CORE_ADDR addr, int *len); | |
1076 | ||
1077 | /* The length of the instruction in bytes. Should be 2 or 4. */ | |
1078 | int m_length; | |
1079 | ||
1080 | /* The instruction opcode. */ | |
1081 | enum opcode m_opcode; | |
1082 | ||
1083 | /* The three possible registers an instruction might reference. Not | |
1084 | every instruction fills in all of these registers. Which fields are | |
1085 | valid depends on the opcode. The naming of these fields matches the | |
1086 | naming in the riscv isa manual. */ | |
1087 | int m_rd; | |
1088 | int m_rs1; | |
1089 | int m_rs2; | |
1090 | ||
1091 | /* Possible instruction immediate. This is only valid if the instruction | |
1092 | format contains an immediate, not all instruction, whether this is | |
1093 | valid depends on the opcode. Despite only having one format for now | |
1094 | the immediate is packed into a union, later instructions might require | |
1095 | an unsigned formatted immediate, having the union in place now will | |
1096 | reduce the need for code churn later. */ | |
1097 | union riscv_insn_immediate | |
1098 | { | |
1099 | riscv_insn_immediate () | |
1100 | : s (0) | |
1101 | { | |
1102 | /* Nothing. */ | |
1103 | } | |
1104 | ||
1105 | int s; | |
1106 | } m_imm; | |
1107 | }; | |
1108 | ||
1109 | /* Fetch instruction from target memory at ADDR, return the content of the | |
1110 | instruction, and update LEN with the instruction length. */ | |
1111 | ||
1112 | ULONGEST | |
1113 | riscv_insn::fetch_instruction (struct gdbarch *gdbarch, | |
1114 | CORE_ADDR addr, int *len) | |
1115 | { | |
1116 | enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); | |
1117 | gdb_byte buf[8]; | |
1118 | int instlen, status; | |
1119 | ||
1120 | /* All insns are at least 16 bits. */ | |
1121 | status = target_read_memory (addr, buf, 2); | |
1122 | if (status) | |
1123 | memory_error (TARGET_XFER_E_IO, addr); | |
1124 | ||
1125 | /* If we need more, grab it now. */ | |
1126 | instlen = riscv_insn_length (buf[0]); | |
89a3b63e | 1127 | gdb_assert (instlen <= sizeof (buf)); |
dbbb1059 | 1128 | *len = instlen; |
89a3b63e AB |
1129 | |
1130 | if (instlen > 2) | |
dbbb1059 AB |
1131 | { |
1132 | status = target_read_memory (addr + 2, buf + 2, instlen - 2); | |
1133 | if (status) | |
1134 | memory_error (TARGET_XFER_E_IO, addr + 2); | |
1135 | } | |
1136 | ||
1137 | return extract_unsigned_integer (buf, instlen, byte_order); | |
1138 | } | |
1139 | ||
1140 | /* Fetch from target memory an instruction at PC and decode it. */ | |
1141 | ||
1142 | void | |
1143 | riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1144 | { | |
1145 | ULONGEST ival; | |
1146 | ||
1147 | /* Fetch the instruction, and the instructions length. */ | |
1148 | ival = fetch_instruction (gdbarch, pc, &m_length); | |
1149 | ||
1150 | if (m_length == 4) | |
1151 | { | |
1152 | if (is_add_insn (ival)) | |
1153 | decode_r_type_insn (ADD, ival); | |
1154 | else if (is_addw_insn (ival)) | |
1155 | decode_r_type_insn (ADDW, ival); | |
1156 | else if (is_addi_insn (ival)) | |
1157 | decode_i_type_insn (ADDI, ival); | |
1158 | else if (is_addiw_insn (ival)) | |
1159 | decode_i_type_insn (ADDIW, ival); | |
1160 | else if (is_auipc_insn (ival)) | |
1161 | decode_u_type_insn (AUIPC, ival); | |
1162 | else if (is_lui_insn (ival)) | |
1163 | decode_u_type_insn (LUI, ival); | |
1164 | else if (is_sd_insn (ival)) | |
1165 | decode_s_type_insn (SD, ival); | |
1166 | else if (is_sw_insn (ival)) | |
1167 | decode_s_type_insn (SW, ival); | |
5c720ed8 JW |
1168 | else if (is_jal_insn (ival)) |
1169 | decode_j_type_insn (JAL, ival); | |
1170 | else if (is_jalr_insn (ival)) | |
1171 | decode_i_type_insn (JALR, ival); | |
1172 | else if (is_beq_insn (ival)) | |
1173 | decode_b_type_insn (BEQ, ival); | |
1174 | else if (is_bne_insn (ival)) | |
1175 | decode_b_type_insn (BNE, ival); | |
1176 | else if (is_blt_insn (ival)) | |
1177 | decode_b_type_insn (BLT, ival); | |
1178 | else if (is_bge_insn (ival)) | |
1179 | decode_b_type_insn (BGE, ival); | |
1180 | else if (is_bltu_insn (ival)) | |
1181 | decode_b_type_insn (BLTU, ival); | |
1182 | else if (is_bgeu_insn (ival)) | |
1183 | decode_b_type_insn (BGEU, ival); | |
1184 | else if (is_lr_w_insn (ival)) | |
1185 | decode_r_type_insn (LR, ival); | |
1186 | else if (is_lr_d_insn (ival)) | |
1187 | decode_r_type_insn (LR, ival); | |
1188 | else if (is_sc_w_insn (ival)) | |
1189 | decode_r_type_insn (SC, ival); | |
1190 | else if (is_sc_d_insn (ival)) | |
1191 | decode_r_type_insn (SC, ival); | |
dbbb1059 AB |
1192 | else |
1193 | /* None of the other fields are valid in this case. */ | |
1194 | m_opcode = OTHER; | |
1195 | } | |
1196 | else if (m_length == 2) | |
1197 | { | |
5c720ed8 JW |
1198 | int xlen = riscv_isa_xlen (gdbarch); |
1199 | ||
1200 | /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a | |
1201 | C_JALR. So must try to match C_JALR first as it has more bits in | |
1202 | mask. */ | |
1203 | if (is_c_jalr_insn (ival)) | |
1204 | decode_cr_type_insn (JALR, ival); | |
1205 | else if (is_c_add_insn (ival)) | |
dbbb1059 | 1206 | decode_cr_type_insn (ADD, ival); |
5c720ed8 JW |
1207 | /* C_ADDW is RV64 and RV128 only. */ |
1208 | else if (xlen != 4 && is_c_addw_insn (ival)) | |
dbbb1059 AB |
1209 | decode_cr_type_insn (ADDW, ival); |
1210 | else if (is_c_addi_insn (ival)) | |
1211 | decode_ci_type_insn (ADDI, ival); | |
5c720ed8 JW |
1212 | /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128 |
1213 | only and C_JAL is RV32 only. */ | |
1214 | else if (xlen != 4 && is_c_addiw_insn (ival)) | |
dbbb1059 | 1215 | decode_ci_type_insn (ADDIW, ival); |
5c720ed8 JW |
1216 | else if (xlen == 4 && is_c_jal_insn (ival)) |
1217 | decode_cj_type_insn (JAL, ival); | |
1218 | /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a | |
1219 | C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits | |
1220 | in mask. */ | |
dbbb1059 AB |
1221 | else if (is_c_addi16sp_insn (ival)) |
1222 | { | |
1223 | m_opcode = ADDI; | |
1224 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); | |
1225 | m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); | |
1226 | } | |
ff3a05b3 AB |
1227 | else if (is_c_addi4spn_insn (ival)) |
1228 | { | |
1229 | m_opcode = ADDI; | |
1230 | m_rd = decode_register_index_short (ival, OP_SH_CRS2S); | |
1231 | m_rs1 = RISCV_SP_REGNUM; | |
1232 | m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival); | |
1233 | } | |
5c720ed8 | 1234 | else if (is_c_lui_insn (ival)) |
d354055e AB |
1235 | { |
1236 | m_opcode = LUI; | |
1237 | m_rd = decode_register_index (ival, OP_SH_CRS1S); | |
1238 | m_imm.s = EXTRACT_RVC_LUI_IMM (ival); | |
1239 | } | |
5c720ed8 JW |
1240 | /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, |
1241 | and C_FSW is RV32 only. */ | |
1242 | else if (xlen != 4 && is_c_sd_insn (ival)) | |
ff3a05b3 | 1243 | decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival)); |
5c720ed8 | 1244 | else if (is_c_sw_insn (ival)) |
ff3a05b3 AB |
1245 | decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival)); |
1246 | else if (is_c_swsp_insn (ival)) | |
1247 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival)); | |
1248 | else if (xlen != 4 && is_c_sdsp_insn (ival)) | |
1249 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival)); | |
5c720ed8 JW |
1250 | /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. |
1251 | So must try to match C_JR first as it ahs more bits in mask. */ | |
1252 | else if (is_c_jr_insn (ival)) | |
1253 | decode_cr_type_insn (JALR, ival); | |
1254 | else if (is_c_j_insn (ival)) | |
1255 | decode_cj_type_insn (JAL, ival); | |
1256 | else if (is_c_beqz_insn (ival)) | |
1257 | decode_cb_type_insn (BEQ, ival); | |
1258 | else if (is_c_bnez_insn (ival)) | |
1259 | decode_cb_type_insn (BNE, ival); | |
dbbb1059 AB |
1260 | else |
1261 | /* None of the other fields of INSN are valid in this case. */ | |
1262 | m_opcode = OTHER; | |
1263 | } | |
1264 | else | |
1265 | internal_error (__FILE__, __LINE__, | |
1266 | _("unable to decode %d byte instructions in " | |
1267 | "prologue at %s"), m_length, | |
1268 | core_addr_to_string (pc)); | |
1269 | } | |
1270 | ||
1271 | /* The prologue scanner. This is currently only used for skipping the | |
1272 | prologue of a function when the DWARF information is not sufficient. | |
1273 | However, it is written with filling of the frame cache in mind, which | |
1274 | is why different groups of stack setup instructions are split apart | |
1275 | during the core of the inner loop. In the future, the intention is to | |
1276 | extend this function to fully support building up a frame cache that | |
1277 | can unwind register values when there is no DWARF information. */ | |
1278 | ||
1279 | static CORE_ADDR | |
1280 | riscv_scan_prologue (struct gdbarch *gdbarch, | |
78a3b0fa AB |
1281 | CORE_ADDR start_pc, CORE_ADDR end_pc, |
1282 | struct riscv_unwind_cache *cache) | |
dbbb1059 | 1283 | { |
78a3b0fa | 1284 | CORE_ADDR cur_pc, next_pc, after_prologue_pc; |
dbbb1059 AB |
1285 | CORE_ADDR end_prologue_addr = 0; |
1286 | ||
78a3b0fa AB |
1287 | /* Find an upper limit on the function prologue using the debug |
1288 | information. If the debug information could not be used to provide | |
1289 | that bound, then use an arbitrary large number as the upper bound. */ | |
1290 | after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc); | |
1291 | if (after_prologue_pc == 0) | |
1292 | after_prologue_pc = start_pc + 100; /* Arbitrary large number. */ | |
1293 | if (after_prologue_pc < end_pc) | |
1294 | end_pc = after_prologue_pc; | |
1295 | ||
1296 | pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */ | |
1297 | for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++) | |
1298 | regs[regno] = pv_register (regno, 0); | |
1299 | pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch)); | |
1300 | ||
1301 | if (riscv_debug_unwinder) | |
1302 | fprintf_unfiltered | |
1303 | (gdb_stdlog, | |
1304 | "Prologue scan for function starting at %s (limit %s)\n", | |
1305 | core_addr_to_string (start_pc), | |
1306 | core_addr_to_string (end_pc)); | |
1307 | ||
1308 | for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc) | |
dbbb1059 AB |
1309 | { |
1310 | struct riscv_insn insn; | |
1311 | ||
1312 | /* Decode the current instruction, and decide where the next | |
1313 | instruction lives based on the size of this instruction. */ | |
1314 | insn.decode (gdbarch, cur_pc); | |
1315 | gdb_assert (insn.length () > 0); | |
1316 | next_pc = cur_pc + insn.length (); | |
1317 | ||
1318 | /* Look for common stack adjustment insns. */ | |
1319 | if ((insn.opcode () == riscv_insn::ADDI | |
1320 | || insn.opcode () == riscv_insn::ADDIW) | |
1321 | && insn.rd () == RISCV_SP_REGNUM | |
1322 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1323 | { | |
1324 | /* Handle: addi sp, sp, -i | |
1325 | or: addiw sp, sp, -i */ | |
78a3b0fa AB |
1326 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1327 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1328 | regs[insn.rd ()] | |
1329 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1330 | } |
1331 | else if ((insn.opcode () == riscv_insn::SW | |
1332 | || insn.opcode () == riscv_insn::SD) | |
1333 | && (insn.rs1 () == RISCV_SP_REGNUM | |
1334 | || insn.rs1 () == RISCV_FP_REGNUM)) | |
1335 | { | |
1336 | /* Handle: sw reg, offset(sp) | |
1337 | or: sd reg, offset(sp) | |
1338 | or: sw reg, offset(s0) | |
1339 | or: sd reg, offset(s0) */ | |
1340 | /* Instruction storing a register onto the stack. */ | |
78a3b0fa AB |
1341 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
1342 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1343 | stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()), | |
1344 | (insn.opcode () == riscv_insn::SW ? 4 : 8), | |
1345 | regs[insn.rs2 ()]); | |
dbbb1059 AB |
1346 | } |
1347 | else if (insn.opcode () == riscv_insn::ADDI | |
1348 | && insn.rd () == RISCV_FP_REGNUM | |
1349 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1350 | { | |
1351 | /* Handle: addi s0, sp, size */ | |
1352 | /* Instructions setting up the frame pointer. */ | |
78a3b0fa AB |
1353 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1354 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1355 | regs[insn.rd ()] | |
1356 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1357 | } |
1358 | else if ((insn.opcode () == riscv_insn::ADD | |
1359 | || insn.opcode () == riscv_insn::ADDW) | |
1360 | && insn.rd () == RISCV_FP_REGNUM | |
1361 | && insn.rs1 () == RISCV_SP_REGNUM | |
1362 | && insn.rs2 () == RISCV_ZERO_REGNUM) | |
1363 | { | |
1364 | /* Handle: add s0, sp, 0 | |
1365 | or: addw s0, sp, 0 */ | |
1366 | /* Instructions setting up the frame pointer. */ | |
78a3b0fa AB |
1367 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1368 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1369 | regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0); | |
dbbb1059 | 1370 | } |
d354055e AB |
1371 | else if ((insn.opcode () == riscv_insn::ADDI |
1372 | && insn.rd () == RISCV_ZERO_REGNUM | |
1373 | && insn.rs1 () == RISCV_ZERO_REGNUM | |
1374 | && insn.imm_signed () == 0)) | |
dbbb1059 | 1375 | { |
d354055e | 1376 | /* Handle: add x0, x0, 0 (NOP) */ |
dbbb1059 | 1377 | } |
d354055e AB |
1378 | else if (insn.opcode () == riscv_insn::AUIPC) |
1379 | { | |
1380 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1381 | regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ()); | |
1382 | } | |
1383 | else if (insn.opcode () == riscv_insn::LUI) | |
1384 | { | |
1385 | /* Handle: lui REG, n | |
1386 | Where REG is not gp register. */ | |
1387 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1388 | regs[insn.rd ()] = pv_constant (insn.imm_signed ()); | |
1389 | } | |
1390 | else if (insn.opcode () == riscv_insn::ADDI) | |
1391 | { | |
1392 | /* Handle: addi REG1, REG2, IMM */ | |
1393 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1394 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1395 | regs[insn.rd ()] | |
1396 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
1397 | } | |
1398 | else if (insn.opcode () == riscv_insn::ADD) | |
1399 | { | |
1400 | /* Handle: addi REG1, REG2, IMM */ | |
1401 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1402 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1403 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1404 | regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]); | |
1405 | } | |
dbbb1059 AB |
1406 | else |
1407 | { | |
78a3b0fa AB |
1408 | end_prologue_addr = cur_pc; |
1409 | break; | |
dbbb1059 AB |
1410 | } |
1411 | } | |
1412 | ||
1413 | if (end_prologue_addr == 0) | |
1414 | end_prologue_addr = cur_pc; | |
1415 | ||
78a3b0fa AB |
1416 | if (riscv_debug_unwinder) |
1417 | fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n", | |
1418 | core_addr_to_string (end_prologue_addr)); | |
1419 | ||
1420 | if (cache != NULL) | |
1421 | { | |
1422 | /* Figure out if it is a frame pointer or just a stack pointer. Also | |
1423 | the offset held in the pv_t is from the original register value to | |
1424 | the current value, which for a grows down stack means a negative | |
1425 | value. The FRAME_BASE_OFFSET is the negation of this, how to get | |
1426 | from the current value to the original value. */ | |
1427 | if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM)) | |
1428 | { | |
1429 | cache->frame_base_reg = RISCV_FP_REGNUM; | |
1430 | cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k; | |
1431 | } | |
1432 | else | |
1433 | { | |
1434 | cache->frame_base_reg = RISCV_SP_REGNUM; | |
1435 | cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k; | |
1436 | } | |
1437 | ||
1438 | /* Assign offset from old SP to all saved registers. As we don't | |
1439 | have the previous value for the frame base register at this | |
1440 | point, we store the offset as the address in the trad_frame, and | |
1441 | then convert this to an actual address later. */ | |
1442 | for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++) | |
1443 | { | |
1444 | CORE_ADDR offset; | |
1445 | if (stack.find_reg (gdbarch, i, &offset)) | |
1446 | { | |
1447 | if (riscv_debug_unwinder) | |
1448 | fprintf_unfiltered (gdb_stdlog, | |
1449 | "Register $%s at stack offset %ld\n", | |
1450 | gdbarch_register_name (gdbarch, i), | |
1451 | offset); | |
1452 | trad_frame_set_addr (cache->regs, i, offset); | |
1453 | } | |
1454 | } | |
1455 | } | |
1456 | ||
dbbb1059 AB |
1457 | return end_prologue_addr; |
1458 | } | |
1459 | ||
1460 | /* Implement the riscv_skip_prologue gdbarch method. */ | |
1461 | ||
1462 | static CORE_ADDR | |
78a3b0fa | 1463 | riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
dbbb1059 | 1464 | { |
dbbb1059 AB |
1465 | CORE_ADDR func_addr; |
1466 | ||
1467 | /* See if we can determine the end of the prologue via the symbol | |
1468 | table. If so, then return either PC, or the PC after the | |
1469 | prologue, whichever is greater. */ | |
1470 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
1471 | { | |
1472 | CORE_ADDR post_prologue_pc | |
1473 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1474 | ||
1475 | if (post_prologue_pc != 0) | |
1476 | return std::max (pc, post_prologue_pc); | |
1477 | } | |
1478 | ||
1479 | /* Can't determine prologue from the symbol table, need to examine | |
78a3b0fa AB |
1480 | instructions. Pass -1 for the end address to indicate the prologue |
1481 | scanner can scan as far as it needs to find the end of the prologue. */ | |
1482 | return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL); | |
dbbb1059 AB |
1483 | } |
1484 | ||
1485 | /* Implement the gdbarch push dummy code callback. */ | |
1486 | ||
1487 | static CORE_ADDR | |
1488 | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
1489 | CORE_ADDR funaddr, struct value **args, int nargs, | |
1490 | struct type *value_type, CORE_ADDR *real_pc, | |
1491 | CORE_ADDR *bp_addr, struct regcache *regcache) | |
1492 | { | |
1493 | /* Allocate space for a breakpoint, and keep the stack correctly | |
1494 | aligned. */ | |
1495 | sp -= 16; | |
1496 | *bp_addr = sp; | |
1497 | *real_pc = funaddr; | |
1498 | return sp; | |
1499 | } | |
1500 | ||
1501 | /* Compute the alignment of the type T. Used while setting up the | |
1502 | arguments for a dummy call. */ | |
1503 | ||
1504 | static int | |
1505 | riscv_type_alignment (struct type *t) | |
1506 | { | |
1507 | t = check_typedef (t); | |
1508 | switch (TYPE_CODE (t)) | |
1509 | { | |
1510 | default: | |
1511 | error (_("Could not compute alignment of type")); | |
1512 | ||
1513 | case TYPE_CODE_RVALUE_REF: | |
1514 | case TYPE_CODE_PTR: | |
1515 | case TYPE_CODE_ENUM: | |
1516 | case TYPE_CODE_INT: | |
1517 | case TYPE_CODE_FLT: | |
1518 | case TYPE_CODE_REF: | |
1519 | case TYPE_CODE_CHAR: | |
1520 | case TYPE_CODE_BOOL: | |
1521 | return TYPE_LENGTH (t); | |
1522 | ||
1523 | case TYPE_CODE_ARRAY: | |
1524 | case TYPE_CODE_COMPLEX: | |
1525 | return riscv_type_alignment (TYPE_TARGET_TYPE (t)); | |
1526 | ||
1527 | case TYPE_CODE_STRUCT: | |
1528 | case TYPE_CODE_UNION: | |
1529 | { | |
1530 | int i; | |
1531 | int align = 1; | |
1532 | ||
1533 | for (i = 0; i < TYPE_NFIELDS (t); ++i) | |
1534 | { | |
1535 | if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS) | |
1536 | { | |
1537 | int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i)); | |
1538 | if (a > align) | |
1539 | align = a; | |
1540 | } | |
1541 | } | |
1542 | return align; | |
1543 | } | |
1544 | } | |
1545 | } | |
1546 | ||
1547 | /* Holds information about a single argument either being passed to an | |
1548 | inferior function, or returned from an inferior function. This includes | |
1549 | information about the size, type, etc of the argument, and also | |
1550 | information about how the argument will be passed (or returned). */ | |
1551 | ||
1552 | struct riscv_arg_info | |
1553 | { | |
1554 | /* Contents of the argument. */ | |
1555 | const gdb_byte *contents; | |
1556 | ||
1557 | /* Length of argument. */ | |
1558 | int length; | |
1559 | ||
1560 | /* Alignment required for an argument of this type. */ | |
1561 | int align; | |
1562 | ||
1563 | /* The type for this argument. */ | |
1564 | struct type *type; | |
1565 | ||
1566 | /* Each argument can have either 1 or 2 locations assigned to it. Each | |
1567 | location describes where part of the argument will be placed. The | |
1568 | second location is valid based on the LOC_TYPE and C_LENGTH fields | |
1569 | of the first location (which is always valid). */ | |
1570 | struct location | |
1571 | { | |
1572 | /* What type of location this is. */ | |
1573 | enum location_type | |
1574 | { | |
1575 | /* Argument passed in a register. */ | |
1576 | in_reg, | |
1577 | ||
1578 | /* Argument passed as an on stack argument. */ | |
1579 | on_stack, | |
1580 | ||
1581 | /* Argument passed by reference. The second location is always | |
1582 | valid for a BY_REF argument, and describes where the address | |
1583 | of the BY_REF argument should be placed. */ | |
1584 | by_ref | |
1585 | } loc_type; | |
1586 | ||
1587 | /* Information that depends on the location type. */ | |
1588 | union | |
1589 | { | |
1590 | /* Which register number to use. */ | |
1591 | int regno; | |
1592 | ||
1593 | /* The offset into the stack region. */ | |
1594 | int offset; | |
1595 | } loc_data; | |
1596 | ||
1597 | /* The length of contents covered by this location. If this is less | |
1598 | than the total length of the argument, then the second location | |
1599 | will be valid, and will describe where the rest of the argument | |
1600 | will go. */ | |
1601 | int c_length; | |
1602 | ||
1603 | /* The offset within CONTENTS for this part of the argument. Will | |
1604 | always be 0 for the first part. For the second part of the | |
1605 | argument, this might be the C_LENGTH value of the first part, | |
1606 | however, if we are passing a structure in two registers, and there's | |
1607 | is padding between the first and second field, then this offset | |
1608 | might be greater than the length of the first argument part. When | |
1609 | the second argument location is not holding part of the argument | |
1610 | value, but is instead holding the address of a reference argument, | |
1611 | then this offset will be set to 0. */ | |
1612 | int c_offset; | |
1613 | } argloc[2]; | |
1614 | }; | |
1615 | ||
1616 | /* Information about a set of registers being used for passing arguments as | |
1617 | part of a function call. The register set must be numerically | |
1618 | sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be | |
1619 | disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */ | |
1620 | ||
1621 | struct riscv_arg_reg | |
1622 | { | |
1623 | riscv_arg_reg (int first, int last) | |
1624 | : next_regnum (first), | |
1625 | last_regnum (last) | |
1626 | { | |
1627 | /* Nothing. */ | |
1628 | } | |
1629 | ||
1630 | /* The GDB register number to use in this set. */ | |
1631 | int next_regnum; | |
1632 | ||
1633 | /* The last GDB register number to use in this set. */ | |
1634 | int last_regnum; | |
1635 | }; | |
1636 | ||
1637 | /* Arguments can be passed as on stack arguments, or by reference. The | |
1638 | on stack arguments must be in a continuous region starting from $sp, | |
1639 | while the by reference arguments can be anywhere, but we'll put them | |
1640 | on the stack after (at higher address) the on stack arguments. | |
1641 | ||
1642 | This might not be the right approach to take. The ABI is clear that | |
1643 | an argument passed by reference can be modified by the callee, which | |
1644 | us placing the argument (temporarily) onto the stack will not achieve | |
1645 | (changes will be lost). There's also the possibility that very large | |
1646 | arguments could overflow the stack. | |
1647 | ||
1648 | This struct is used to track offset into these two areas for where | |
1649 | arguments are to be placed. */ | |
1650 | struct riscv_memory_offsets | |
1651 | { | |
1652 | riscv_memory_offsets () | |
1653 | : arg_offset (0), | |
1654 | ref_offset (0) | |
1655 | { | |
1656 | /* Nothing. */ | |
1657 | } | |
1658 | ||
1659 | /* Offset into on stack argument area. */ | |
1660 | int arg_offset; | |
1661 | ||
1662 | /* Offset into the pass by reference area. */ | |
1663 | int ref_offset; | |
1664 | }; | |
1665 | ||
1666 | /* Holds information about where arguments to a call will be placed. This | |
1667 | is updated as arguments are added onto the call, and can be used to | |
1668 | figure out where the next argument should be placed. */ | |
1669 | ||
1670 | struct riscv_call_info | |
1671 | { | |
1672 | riscv_call_info (struct gdbarch *gdbarch) | |
1673 | : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7), | |
1674 | float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7) | |
1675 | { | |
1676 | xlen = riscv_isa_xlen (gdbarch); | |
1677 | flen = riscv_isa_flen (gdbarch); | |
1678 | ||
1679 | /* Disable use of floating point registers if needed. */ | |
1680 | if (!riscv_has_fp_abi (gdbarch)) | |
1681 | float_regs.next_regnum = float_regs.last_regnum + 1; | |
1682 | } | |
1683 | ||
1684 | /* Track the memory areas used for holding in-memory arguments to a | |
1685 | call. */ | |
1686 | struct riscv_memory_offsets memory; | |
1687 | ||
1688 | /* Holds information about the next integer register to use for passing | |
1689 | an argument. */ | |
1690 | struct riscv_arg_reg int_regs; | |
1691 | ||
1692 | /* Holds information about the next floating point register to use for | |
1693 | passing an argument. */ | |
1694 | struct riscv_arg_reg float_regs; | |
1695 | ||
1696 | /* The XLEN and FLEN are copied in to this structure for convenience, and | |
1697 | are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */ | |
1698 | int xlen; | |
1699 | int flen; | |
1700 | }; | |
1701 | ||
1702 | /* Return the number of registers available for use as parameters in the | |
1703 | register set REG. Returned value can be 0 or more. */ | |
1704 | ||
1705 | static int | |
1706 | riscv_arg_regs_available (struct riscv_arg_reg *reg) | |
1707 | { | |
1708 | if (reg->next_regnum > reg->last_regnum) | |
1709 | return 0; | |
1710 | ||
1711 | return (reg->last_regnum - reg->next_regnum + 1); | |
1712 | } | |
1713 | ||
1714 | /* If there is at least one register available in the register set REG then | |
1715 | the next register from REG is assigned to LOC and the length field of | |
1716 | LOC is updated to LENGTH. The register set REG is updated to indicate | |
1717 | that the assigned register is no longer available and the function | |
1718 | returns true. | |
1719 | ||
1720 | If there are no registers available in REG then the function returns | |
1721 | false, and LOC and REG are unchanged. */ | |
1722 | ||
1723 | static bool | |
1724 | riscv_assign_reg_location (struct riscv_arg_info::location *loc, | |
1725 | struct riscv_arg_reg *reg, | |
1726 | int length, int offset) | |
1727 | { | |
1728 | if (reg->next_regnum <= reg->last_regnum) | |
1729 | { | |
1730 | loc->loc_type = riscv_arg_info::location::in_reg; | |
1731 | loc->loc_data.regno = reg->next_regnum; | |
1732 | reg->next_regnum++; | |
1733 | loc->c_length = length; | |
1734 | loc->c_offset = offset; | |
1735 | return true; | |
1736 | } | |
1737 | ||
1738 | return false; | |
1739 | } | |
1740 | ||
1741 | /* Assign LOC a location as the next stack parameter, and update MEMORY to | |
1742 | record that an area of stack has been used to hold the parameter | |
1743 | described by LOC. | |
1744 | ||
1745 | The length field of LOC is updated to LENGTH, the length of the | |
1746 | parameter being stored, and ALIGN is the alignment required by the | |
1747 | parameter, which will affect how memory is allocated out of MEMORY. */ | |
1748 | ||
1749 | static void | |
1750 | riscv_assign_stack_location (struct riscv_arg_info::location *loc, | |
1751 | struct riscv_memory_offsets *memory, | |
1752 | int length, int align) | |
1753 | { | |
1754 | loc->loc_type = riscv_arg_info::location::on_stack; | |
1755 | memory->arg_offset | |
1756 | = align_up (memory->arg_offset, align); | |
1757 | loc->loc_data.offset = memory->arg_offset; | |
1758 | memory->arg_offset += length; | |
1759 | loc->c_length = length; | |
1760 | ||
1761 | /* Offset is always 0, either we're the first location part, in which | |
1762 | case we're reading content from the start of the argument, or we're | |
1763 | passing the address of a reference argument, so 0. */ | |
1764 | loc->c_offset = 0; | |
1765 | } | |
1766 | ||
1767 | /* Update AINFO, which describes an argument that should be passed or | |
1768 | returned using the integer ABI. The argloc fields within AINFO are | |
1769 | updated to describe the location in which the argument will be passed to | |
1770 | a function, or returned from a function. | |
1771 | ||
1772 | The CINFO structure contains the ongoing call information, the holds | |
1773 | information such as which argument registers are remaining to be | |
1774 | assigned to parameter, and how much memory has been used by parameters | |
1775 | so far. | |
1776 | ||
1777 | By examining the state of CINFO a suitable location can be selected, | |
1778 | and assigned to AINFO. */ | |
1779 | ||
1780 | static void | |
1781 | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, | |
1782 | struct riscv_call_info *cinfo) | |
1783 | { | |
1784 | if (ainfo->length > (2 * cinfo->xlen)) | |
1785 | { | |
1786 | /* Argument is going to be passed by reference. */ | |
1787 | ainfo->argloc[0].loc_type | |
1788 | = riscv_arg_info::location::by_ref; | |
1789 | cinfo->memory.ref_offset | |
1790 | = align_up (cinfo->memory.ref_offset, ainfo->align); | |
1791 | ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset; | |
1792 | cinfo->memory.ref_offset += ainfo->length; | |
1793 | ainfo->argloc[0].c_length = ainfo->length; | |
1794 | ||
1795 | /* The second location for this argument is given over to holding the | |
1796 | address of the by-reference data. Pass 0 for the offset as this | |
1797 | is not part of the actual argument value. */ | |
1798 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1799 | &cinfo->int_regs, | |
1800 | cinfo->xlen, 0)) | |
1801 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1802 | &cinfo->memory, cinfo->xlen, | |
1803 | cinfo->xlen); | |
1804 | } | |
1805 | else | |
1806 | { | |
1807 | int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length; | |
1808 | ||
1809 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1810 | &cinfo->int_regs, len, 0)) | |
1811 | riscv_assign_stack_location (&ainfo->argloc[0], | |
1812 | &cinfo->memory, len, ainfo->align); | |
1813 | ||
1814 | if (len < ainfo->length) | |
1815 | { | |
1816 | len = ainfo->length - len; | |
1817 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1818 | &cinfo->int_regs, len, | |
1819 | cinfo->xlen)) | |
1820 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1821 | &cinfo->memory, len, cinfo->xlen); | |
1822 | } | |
1823 | } | |
1824 | } | |
1825 | ||
1826 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1827 | is being passed with the floating point ABI. */ | |
1828 | ||
1829 | static void | |
1830 | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, | |
1831 | struct riscv_call_info *cinfo) | |
1832 | { | |
1833 | if (ainfo->length > cinfo->flen) | |
1834 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1835 | else | |
1836 | { | |
1837 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1838 | &cinfo->float_regs, | |
1839 | ainfo->length, 0)) | |
1840 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1841 | } | |
1842 | } | |
1843 | ||
1844 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1845 | is a complex floating point argument, and is therefore handled | |
1846 | differently to other argument types. */ | |
1847 | ||
1848 | static void | |
1849 | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, | |
1850 | struct riscv_call_info *cinfo) | |
1851 | { | |
1852 | if (ainfo->length <= (2 * cinfo->flen) | |
1853 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
1854 | { | |
1855 | bool result; | |
1856 | int len = ainfo->length / 2; | |
1857 | ||
1858 | result = riscv_assign_reg_location (&ainfo->argloc[0], | |
1859 | &cinfo->float_regs, len, len); | |
1860 | gdb_assert (result); | |
1861 | ||
1862 | result = riscv_assign_reg_location (&ainfo->argloc[1], | |
1863 | &cinfo->float_regs, len, len); | |
1864 | gdb_assert (result); | |
1865 | } | |
1866 | else | |
1867 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1868 | } | |
1869 | ||
1870 | /* A structure used for holding information about a structure type within | |
1871 | the inferior program. The RiscV ABI has special rules for handling some | |
1872 | structures with a single field or with two fields. The counting of | |
1873 | fields here is done after flattening out all nested structures. */ | |
1874 | ||
1875 | class riscv_struct_info | |
1876 | { | |
1877 | public: | |
1878 | riscv_struct_info () | |
1879 | : m_number_of_fields (0), | |
1880 | m_types { nullptr, nullptr } | |
1881 | { | |
1882 | /* Nothing. */ | |
1883 | } | |
1884 | ||
1885 | /* Analyse TYPE descending into nested structures, count the number of | |
1886 | scalar fields and record the types of the first two fields found. */ | |
1887 | void analyse (struct type *type); | |
1888 | ||
1889 | /* The number of scalar fields found in the analysed type. This is | |
1890 | currently only accurate if the value returned is 0, 1, or 2 as the | |
1891 | analysis stops counting when the number of fields is 3. This is | |
1892 | because the RiscV ABI only has special cases for 1 or 2 fields, | |
1893 | anything else we just don't care about. */ | |
1894 | int number_of_fields () const | |
1895 | { return m_number_of_fields; } | |
1896 | ||
1897 | /* Return the type for scalar field INDEX within the analysed type. Will | |
1898 | return nullptr if there is no field at that index. Only INDEX values | |
1899 | 0 and 1 can be requested as the RiscV ABI only has special cases for | |
1900 | structures with 1 or 2 fields. */ | |
1901 | struct type *field_type (int index) const | |
1902 | { | |
1903 | gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0]))); | |
1904 | return m_types[index]; | |
1905 | } | |
1906 | ||
1907 | private: | |
1908 | /* The number of scalar fields found within the structure after recursing | |
1909 | into nested structures. */ | |
1910 | int m_number_of_fields; | |
1911 | ||
1912 | /* The types of the first two scalar fields found within the structure | |
1913 | after recursing into nested structures. */ | |
1914 | struct type *m_types[2]; | |
1915 | }; | |
1916 | ||
1917 | /* Analyse TYPE descending into nested structures, count the number of | |
1918 | scalar fields and record the types of the first two fields found. */ | |
1919 | ||
1920 | void | |
1921 | riscv_struct_info::analyse (struct type *type) | |
1922 | { | |
1923 | unsigned int count = TYPE_NFIELDS (type); | |
1924 | unsigned int i; | |
1925 | ||
1926 | for (i = 0; i < count; ++i) | |
1927 | { | |
1928 | if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS) | |
1929 | continue; | |
1930 | ||
1931 | struct type *field_type = TYPE_FIELD_TYPE (type, i); | |
1932 | field_type = check_typedef (field_type); | |
1933 | ||
1934 | switch (TYPE_CODE (field_type)) | |
1935 | { | |
1936 | case TYPE_CODE_STRUCT: | |
1937 | analyse (field_type); | |
1938 | break; | |
1939 | ||
1940 | default: | |
1941 | /* RiscV only flattens out structures. Anything else does not | |
1942 | need to be flattened, we just record the type, and when we | |
1943 | look at the analysis results we'll realise this is not a | |
1944 | structure we can special case, and pass the structure in | |
1945 | memory. */ | |
1946 | if (m_number_of_fields < 2) | |
1947 | m_types[m_number_of_fields] = field_type; | |
1948 | m_number_of_fields++; | |
1949 | break; | |
1950 | } | |
1951 | ||
1952 | /* RiscV only has special handling for structures with 1 or 2 scalar | |
1953 | fields, any more than that and the structure is just passed in | |
1954 | memory. We can safely drop out early when we find 3 or more | |
1955 | fields then. */ | |
1956 | ||
1957 | if (m_number_of_fields > 2) | |
1958 | return; | |
1959 | } | |
1960 | } | |
1961 | ||
1962 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1963 | is a structure. Small structures on RiscV have some special case | |
1964 | handling in order that the structure might be passed in register. | |
1965 | Larger structures are passed in memory. After assigning location | |
1966 | information to AINFO, CINFO will have been updated. */ | |
1967 | ||
1968 | static void | |
1969 | riscv_call_arg_struct (struct riscv_arg_info *ainfo, | |
1970 | struct riscv_call_info *cinfo) | |
1971 | { | |
1972 | if (riscv_arg_regs_available (&cinfo->float_regs) >= 1) | |
1973 | { | |
1974 | struct riscv_struct_info sinfo; | |
1975 | ||
1976 | sinfo.analyse (ainfo->type); | |
1977 | if (sinfo.number_of_fields () == 1 | |
1978 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX) | |
1979 | { | |
1980 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1981 | == TYPE_LENGTH (sinfo.field_type (0))); | |
1982 | return riscv_call_arg_complex_float (ainfo, cinfo); | |
1983 | } | |
1984 | ||
1985 | if (sinfo.number_of_fields () == 1 | |
1986 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT) | |
1987 | { | |
1988 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1989 | == TYPE_LENGTH (sinfo.field_type (0))); | |
1990 | return riscv_call_arg_scalar_float (ainfo, cinfo); | |
1991 | } | |
1992 | ||
1993 | if (sinfo.number_of_fields () == 2 | |
1994 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
1995 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
1996 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
1997 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen | |
1998 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
1999 | { | |
2000 | int len0, len1, offset; | |
2001 | ||
2002 | gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen)); | |
2003 | ||
2004 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
2005 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2006 | &cinfo->float_regs, len0, 0)) | |
2007 | error (_("failed during argument setup")); | |
2008 | ||
2009 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
2010 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
2011 | gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type) | |
2012 | - TYPE_LENGTH (sinfo.field_type (0)))); | |
2013 | ||
2014 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2015 | &cinfo->float_regs, | |
2016 | len1, offset)) | |
2017 | error (_("failed during argument setup")); | |
2018 | return; | |
2019 | } | |
2020 | ||
2021 | if (sinfo.number_of_fields () == 2 | |
2022 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
2023 | && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
2024 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
2025 | && is_integral_type (sinfo.field_type (1)) | |
2026 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen)) | |
2027 | { | |
2028 | int len0, len1, offset; | |
2029 | ||
2030 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2031 | <= (cinfo->flen + cinfo->xlen)); | |
2032 | ||
2033 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
2034 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2035 | &cinfo->float_regs, len0, 0)) | |
2036 | error (_("failed during argument setup")); | |
2037 | ||
2038 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
2039 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
2040 | gdb_assert (len1 <= cinfo->xlen); | |
2041 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2042 | &cinfo->int_regs, len1, offset)) | |
2043 | error (_("failed during argument setup")); | |
2044 | return; | |
2045 | } | |
2046 | ||
2047 | if (sinfo.number_of_fields () == 2 | |
2048 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
2049 | && (is_integral_type (sinfo.field_type (0)) | |
2050 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen | |
2051 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
2052 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen)) | |
2053 | { | |
2054 | int len0, len1, offset; | |
2055 | ||
2056 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2057 | <= (cinfo->flen + cinfo->xlen)); | |
2058 | ||
2059 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
2060 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
2061 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
2062 | ||
2063 | gdb_assert (len0 <= cinfo->xlen); | |
2064 | gdb_assert (len1 <= cinfo->flen); | |
2065 | ||
2066 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2067 | &cinfo->int_regs, len0, 0)) | |
2068 | error (_("failed during argument setup")); | |
2069 | ||
2070 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2071 | &cinfo->float_regs, | |
2072 | len1, offset)) | |
2073 | error (_("failed during argument setup")); | |
2074 | ||
2075 | return; | |
2076 | } | |
2077 | } | |
2078 | ||
2079 | /* Non of the structure flattening cases apply, so we just pass using | |
2080 | the integer ABI. */ | |
2081 | ainfo->length = align_up (ainfo->length, cinfo->xlen); | |
2082 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2083 | } | |
2084 | ||
2085 | /* Assign a location to call (or return) argument AINFO, the location is | |
2086 | selected from CINFO which holds information about what call argument | |
2087 | locations are available for use next. The TYPE is the type of the | |
2088 | argument being passed, this information is recorded into AINFO (along | |
2089 | with some additional information derived from the type). | |
2090 | ||
2091 | After assigning a location to AINFO, CINFO will have been updated. */ | |
2092 | ||
2093 | static void | |
2094 | riscv_arg_location (struct gdbarch *gdbarch, | |
2095 | struct riscv_arg_info *ainfo, | |
2096 | struct riscv_call_info *cinfo, | |
2097 | struct type *type) | |
2098 | { | |
2099 | ainfo->type = type; | |
2100 | ainfo->length = TYPE_LENGTH (ainfo->type); | |
2101 | ainfo->align = riscv_type_alignment (ainfo->type); | |
2102 | ainfo->contents = nullptr; | |
2103 | ||
2104 | switch (TYPE_CODE (ainfo->type)) | |
2105 | { | |
2106 | case TYPE_CODE_INT: | |
2107 | case TYPE_CODE_BOOL: | |
2108 | case TYPE_CODE_CHAR: | |
2109 | case TYPE_CODE_RANGE: | |
2110 | case TYPE_CODE_ENUM: | |
2111 | case TYPE_CODE_PTR: | |
2112 | if (ainfo->length <= cinfo->xlen) | |
2113 | { | |
2114 | ainfo->type = builtin_type (gdbarch)->builtin_long; | |
2115 | ainfo->length = cinfo->xlen; | |
2116 | } | |
2117 | else if (ainfo->length <= (2 * cinfo->xlen)) | |
2118 | { | |
2119 | ainfo->type = builtin_type (gdbarch)->builtin_long_long; | |
2120 | ainfo->length = 2 * cinfo->xlen; | |
2121 | } | |
2122 | ||
2123 | /* Recalculate the alignment requirement. */ | |
2124 | ainfo->align = riscv_type_alignment (ainfo->type); | |
2125 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2126 | break; | |
2127 | ||
2128 | case TYPE_CODE_FLT: | |
2129 | riscv_call_arg_scalar_float (ainfo, cinfo); | |
2130 | break; | |
2131 | ||
2132 | case TYPE_CODE_COMPLEX: | |
2133 | riscv_call_arg_complex_float (ainfo, cinfo); | |
2134 | break; | |
2135 | ||
2136 | case TYPE_CODE_STRUCT: | |
2137 | riscv_call_arg_struct (ainfo, cinfo); | |
2138 | break; | |
2139 | ||
2140 | default: | |
2141 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2142 | break; | |
2143 | } | |
2144 | } | |
2145 | ||
cab5bb9d AB |
2146 | /* Used for printing debug information about the call argument location in |
2147 | INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base | |
2148 | addresses for the location of pass-by-reference and | |
2149 | arguments-on-the-stack memory areas. */ | |
2150 | ||
dbbb1059 | 2151 | static void |
cab5bb9d | 2152 | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, |
dbbb1059 AB |
2153 | struct riscv_arg_info *info, |
2154 | CORE_ADDR sp_refs, CORE_ADDR sp_args) | |
2155 | { | |
cab5bb9d | 2156 | fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x", |
42ecac17 | 2157 | TYPE_SAFE_NAME (info->type), info->length, info->align); |
dbbb1059 AB |
2158 | switch (info->argloc[0].loc_type) |
2159 | { | |
2160 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2161 | fprintf_unfiltered |
2162 | (stream, ", register %s", | |
2163 | gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno)); | |
dbbb1059 AB |
2164 | if (info->argloc[0].c_length < info->length) |
2165 | { | |
2166 | switch (info->argloc[1].loc_type) | |
2167 | { | |
2168 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2169 | fprintf_unfiltered |
2170 | (stream, ", register %s", | |
2171 | gdbarch_register_name (gdbarch, | |
2172 | info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2173 | break; |
2174 | ||
2175 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2176 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2177 | info->argloc[1].loc_data.offset); | |
dbbb1059 AB |
2178 | break; |
2179 | ||
2180 | case riscv_arg_info::location::by_ref: | |
2181 | default: | |
2182 | /* The second location should never be a reference, any | |
2183 | argument being passed by reference just places its address | |
2184 | in the first location and is done. */ | |
2185 | error (_("invalid argument location")); | |
2186 | break; | |
2187 | } | |
2188 | ||
2189 | if (info->argloc[1].c_offset > info->argloc[0].c_length) | |
cab5bb9d AB |
2190 | fprintf_unfiltered (stream, " (offset 0x%x)", |
2191 | info->argloc[1].c_offset); | |
dbbb1059 AB |
2192 | } |
2193 | break; | |
2194 | ||
2195 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2196 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2197 | info->argloc[0].loc_data.offset); | |
dbbb1059 AB |
2198 | break; |
2199 | ||
2200 | case riscv_arg_info::location::by_ref: | |
cab5bb9d AB |
2201 | fprintf_unfiltered |
2202 | (stream, ", by reference, data at offset 0x%x (%s)", | |
2203 | info->argloc[0].loc_data.offset, | |
2204 | core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset)); | |
dbbb1059 AB |
2205 | if (info->argloc[1].loc_type |
2206 | == riscv_arg_info::location::in_reg) | |
cab5bb9d AB |
2207 | fprintf_unfiltered |
2208 | (stream, ", address in register %s", | |
2209 | gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2210 | else |
2211 | { | |
2212 | gdb_assert (info->argloc[1].loc_type | |
2213 | == riscv_arg_info::location::on_stack); | |
cab5bb9d AB |
2214 | fprintf_unfiltered |
2215 | (stream, ", address on stack at offset 0x%x (%s)", | |
2216 | info->argloc[1].loc_data.offset, | |
2217 | core_addr_to_string (sp_args + info->argloc[1].loc_data.offset)); | |
dbbb1059 AB |
2218 | } |
2219 | break; | |
2220 | ||
2221 | default: | |
89a3b63e | 2222 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2223 | } |
2224 | } | |
2225 | ||
2226 | /* Implement the push dummy call gdbarch callback. */ | |
2227 | ||
2228 | static CORE_ADDR | |
2229 | riscv_push_dummy_call (struct gdbarch *gdbarch, | |
2230 | struct value *function, | |
2231 | struct regcache *regcache, | |
2232 | CORE_ADDR bp_addr, | |
2233 | int nargs, | |
2234 | struct value **args, | |
2235 | CORE_ADDR sp, | |
2236 | int struct_return, | |
2237 | CORE_ADDR struct_addr) | |
2238 | { | |
2239 | int i; | |
2240 | CORE_ADDR sp_args, sp_refs; | |
2241 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
dbbb1059 AB |
2242 | |
2243 | struct riscv_arg_info *arg_info = | |
2244 | (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info)); | |
dbbb1059 AB |
2245 | |
2246 | struct riscv_call_info call_info (gdbarch); | |
2247 | ||
2248 | CORE_ADDR osp = sp; | |
2249 | ||
2250 | /* We'll use register $a0 if we're returning a struct. */ | |
2251 | if (struct_return) | |
2252 | ++call_info.int_regs.next_regnum; | |
2253 | ||
b926417a | 2254 | for (i = 0; i < nargs; ++i) |
dbbb1059 AB |
2255 | { |
2256 | struct value *arg_value; | |
2257 | struct type *arg_type; | |
b926417a | 2258 | struct riscv_arg_info *info = &arg_info[i]; |
dbbb1059 AB |
2259 | |
2260 | arg_value = args[i]; | |
2261 | arg_type = check_typedef (value_type (arg_value)); | |
2262 | ||
2263 | riscv_arg_location (gdbarch, info, &call_info, arg_type); | |
2264 | ||
2265 | if (info->type != arg_type) | |
2266 | arg_value = value_cast (info->type, arg_value); | |
2267 | info->contents = value_contents (arg_value); | |
2268 | } | |
2269 | ||
2270 | /* Adjust the stack pointer and align it. */ | |
2271 | sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT); | |
2272 | sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT); | |
2273 | ||
2274 | if (riscv_debug_infcall > 0) | |
2275 | { | |
2276 | fprintf_unfiltered (gdb_stdlog, "dummy call args:\n"); | |
2277 | fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n", | |
2278 | (riscv_has_fp_abi (gdbarch) ? "is" : "is not")); | |
2279 | fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n", | |
2280 | call_info.xlen, call_info.flen); | |
2281 | if (struct_return) | |
2282 | fprintf_unfiltered (gdb_stdlog, | |
2283 | "[*] struct return pointer in register $A0\n"); | |
2284 | for (i = 0; i < nargs; ++i) | |
2285 | { | |
2286 | struct riscv_arg_info *info = &arg_info [i]; | |
2287 | ||
2288 | fprintf_unfiltered (gdb_stdlog, "[%2d] ", i); | |
cab5bb9d | 2289 | riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args); |
dbbb1059 AB |
2290 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2291 | } | |
2292 | if (call_info.memory.arg_offset > 0 | |
2293 | || call_info.memory.ref_offset > 0) | |
2294 | { | |
cab5bb9d AB |
2295 | fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n", |
2296 | core_addr_to_string (osp)); | |
dbbb1059 | 2297 | fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n", |
cab5bb9d | 2298 | call_info.memory.arg_offset); |
dbbb1059 | 2299 | fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n", |
cab5bb9d | 2300 | call_info.memory.ref_offset); |
fb294655 AB |
2301 | fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n", |
2302 | core_addr_to_string_nz (osp - sp)); | |
dbbb1059 AB |
2303 | } |
2304 | } | |
2305 | ||
2306 | /* Now load the argument into registers, or onto the stack. */ | |
2307 | ||
2308 | if (struct_return) | |
2309 | { | |
2310 | gdb_byte buf[sizeof (LONGEST)]; | |
2311 | ||
2312 | store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr); | |
b66f5587 | 2313 | regcache->cooked_write (RISCV_A0_REGNUM, buf); |
dbbb1059 AB |
2314 | } |
2315 | ||
2316 | for (i = 0; i < nargs; ++i) | |
2317 | { | |
2318 | CORE_ADDR dst; | |
2319 | int second_arg_length = 0; | |
2320 | const gdb_byte *second_arg_data; | |
2321 | struct riscv_arg_info *info = &arg_info [i]; | |
2322 | ||
2323 | gdb_assert (info->length > 0); | |
2324 | ||
2325 | switch (info->argloc[0].loc_type) | |
2326 | { | |
2327 | case riscv_arg_info::location::in_reg: | |
2328 | { | |
2329 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2330 | ||
2331 | gdb_assert (info->argloc[0].c_length <= info->length); | |
2332 | memset (tmp, 0, sizeof (tmp)); | |
2333 | memcpy (tmp, info->contents, info->argloc[0].c_length); | |
b66f5587 | 2334 | regcache->cooked_write (info->argloc[0].loc_data.regno, tmp); |
dbbb1059 AB |
2335 | second_arg_length = |
2336 | ((info->argloc[0].c_length < info->length) | |
2337 | ? info->argloc[1].c_length : 0); | |
2338 | second_arg_data = info->contents + info->argloc[1].c_offset; | |
2339 | } | |
2340 | break; | |
2341 | ||
2342 | case riscv_arg_info::location::on_stack: | |
2343 | dst = sp_args + info->argloc[0].loc_data.offset; | |
2344 | write_memory (dst, info->contents, info->length); | |
2345 | second_arg_length = 0; | |
2346 | break; | |
2347 | ||
2348 | case riscv_arg_info::location::by_ref: | |
2349 | dst = sp_refs + info->argloc[0].loc_data.offset; | |
2350 | write_memory (dst, info->contents, info->length); | |
2351 | ||
2352 | second_arg_length = call_info.xlen; | |
2353 | second_arg_data = (gdb_byte *) &dst; | |
2354 | break; | |
2355 | ||
2356 | default: | |
89a3b63e | 2357 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2358 | } |
2359 | ||
2360 | if (second_arg_length > 0) | |
2361 | { | |
2362 | switch (info->argloc[1].loc_type) | |
2363 | { | |
2364 | case riscv_arg_info::location::in_reg: | |
2365 | { | |
2366 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2367 | ||
8c49aa89 AB |
2368 | gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) |
2369 | && second_arg_length <= call_info.flen) | |
2370 | || second_arg_length <= call_info.xlen); | |
dbbb1059 AB |
2371 | memset (tmp, 0, sizeof (tmp)); |
2372 | memcpy (tmp, second_arg_data, second_arg_length); | |
b66f5587 | 2373 | regcache->cooked_write (info->argloc[1].loc_data.regno, tmp); |
dbbb1059 AB |
2374 | } |
2375 | break; | |
2376 | ||
2377 | case riscv_arg_info::location::on_stack: | |
2378 | { | |
2379 | CORE_ADDR arg_addr; | |
2380 | ||
2381 | arg_addr = sp_args + info->argloc[1].loc_data.offset; | |
2382 | write_memory (arg_addr, second_arg_data, second_arg_length); | |
2383 | break; | |
2384 | } | |
2385 | ||
2386 | case riscv_arg_info::location::by_ref: | |
2387 | default: | |
2388 | /* The second location should never be a reference, any | |
2389 | argument being passed by reference just places its address | |
2390 | in the first location and is done. */ | |
2391 | error (_("invalid argument location")); | |
2392 | break; | |
2393 | } | |
2394 | } | |
2395 | } | |
2396 | ||
2397 | /* Set the dummy return value to bp_addr. | |
2398 | A dummy breakpoint will be setup to execute the call. */ | |
2399 | ||
2400 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2401 | fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n", |
2402 | core_addr_to_string (bp_addr)); | |
dbbb1059 AB |
2403 | regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr); |
2404 | ||
2405 | /* Finally, update the stack pointer. */ | |
2406 | ||
2407 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2408 | fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n", |
2409 | core_addr_to_string (sp)); | |
dbbb1059 AB |
2410 | regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp); |
2411 | ||
2412 | return sp; | |
2413 | } | |
2414 | ||
2415 | /* Implement the return_value gdbarch method. */ | |
2416 | ||
2417 | static enum return_value_convention | |
2418 | riscv_return_value (struct gdbarch *gdbarch, | |
2419 | struct value *function, | |
2420 | struct type *type, | |
2421 | struct regcache *regcache, | |
2422 | gdb_byte *readbuf, | |
2423 | const gdb_byte *writebuf) | |
2424 | { | |
dbbb1059 AB |
2425 | struct riscv_call_info call_info (gdbarch); |
2426 | struct riscv_arg_info info; | |
2427 | struct type *arg_type; | |
2428 | ||
2429 | arg_type = check_typedef (type); | |
2430 | riscv_arg_location (gdbarch, &info, &call_info, arg_type); | |
2431 | ||
2432 | if (riscv_debug_infcall > 0) | |
2433 | { | |
2434 | fprintf_unfiltered (gdb_stdlog, "riscv return value:\n"); | |
2435 | fprintf_unfiltered (gdb_stdlog, "[R] "); | |
cab5bb9d | 2436 | riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0); |
dbbb1059 AB |
2437 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2438 | } | |
2439 | ||
2440 | if (readbuf != nullptr || writebuf != nullptr) | |
2441 | { | |
2442 | int regnum; | |
2443 | ||
2444 | switch (info.argloc[0].loc_type) | |
2445 | { | |
2446 | /* Return value in register(s). */ | |
2447 | case riscv_arg_info::location::in_reg: | |
2448 | { | |
2449 | regnum = info.argloc[0].loc_data.regno; | |
2450 | ||
2451 | if (readbuf) | |
dca08e1f | 2452 | regcache->cooked_read (regnum, readbuf); |
dbbb1059 AB |
2453 | |
2454 | if (writebuf) | |
b66f5587 | 2455 | regcache->cooked_write (regnum, writebuf); |
dbbb1059 AB |
2456 | |
2457 | /* A return value in register can have a second part in a | |
2458 | second register. */ | |
2459 | if (info.argloc[0].c_length < info.length) | |
2460 | { | |
2461 | switch (info.argloc[1].loc_type) | |
2462 | { | |
2463 | case riscv_arg_info::location::in_reg: | |
2464 | regnum = info.argloc[1].loc_data.regno; | |
2465 | ||
2466 | if (readbuf) | |
2467 | { | |
2468 | readbuf += info.argloc[1].c_offset; | |
dca08e1f | 2469 | regcache->cooked_read (regnum, readbuf); |
dbbb1059 AB |
2470 | } |
2471 | ||
2472 | if (writebuf) | |
2473 | { | |
2474 | writebuf += info.argloc[1].c_offset; | |
b66f5587 | 2475 | regcache->cooked_write (regnum, writebuf); |
dbbb1059 AB |
2476 | } |
2477 | break; | |
2478 | ||
2479 | case riscv_arg_info::location::by_ref: | |
2480 | case riscv_arg_info::location::on_stack: | |
2481 | default: | |
2482 | error (_("invalid argument location")); | |
2483 | break; | |
2484 | } | |
2485 | } | |
2486 | } | |
2487 | break; | |
2488 | ||
2489 | /* Return value by reference will have its address in A0. */ | |
2490 | case riscv_arg_info::location::by_ref: | |
2491 | { | |
b2970c23 | 2492 | ULONGEST addr; |
dbbb1059 AB |
2493 | |
2494 | regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, | |
2495 | &addr); | |
2496 | if (readbuf != nullptr) | |
2497 | read_memory (addr, readbuf, info.length); | |
2498 | if (writebuf != nullptr) | |
2499 | write_memory (addr, writebuf, info.length); | |
2500 | } | |
2501 | break; | |
2502 | ||
2503 | case riscv_arg_info::location::on_stack: | |
2504 | default: | |
2505 | error (_("invalid argument location")); | |
2506 | break; | |
2507 | } | |
2508 | } | |
2509 | ||
2510 | switch (info.argloc[0].loc_type) | |
2511 | { | |
2512 | case riscv_arg_info::location::in_reg: | |
2513 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2514 | case riscv_arg_info::location::by_ref: | |
2515 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2516 | case riscv_arg_info::location::on_stack: | |
2517 | default: | |
2518 | error (_("invalid argument location")); | |
2519 | } | |
2520 | } | |
2521 | ||
2522 | /* Implement the frame_align gdbarch method. */ | |
2523 | ||
2524 | static CORE_ADDR | |
2525 | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2526 | { | |
2527 | return align_down (addr, 16); | |
2528 | } | |
2529 | ||
2530 | /* Implement the unwind_pc gdbarch method. */ | |
2531 | ||
2532 | static CORE_ADDR | |
2533 | riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2534 | { | |
2535 | return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM); | |
2536 | } | |
2537 | ||
2538 | /* Implement the unwind_sp gdbarch method. */ | |
2539 | ||
2540 | static CORE_ADDR | |
2541 | riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2542 | { | |
2543 | return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM); | |
2544 | } | |
2545 | ||
2546 | /* Implement the dummy_id gdbarch method. */ | |
2547 | ||
2548 | static struct frame_id | |
2549 | riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
2550 | { | |
2551 | return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM), | |
2552 | get_frame_pc (this_frame)); | |
2553 | } | |
2554 | ||
2555 | /* Generate, or return the cached frame cache for the RiscV frame | |
2556 | unwinder. */ | |
2557 | ||
78a3b0fa | 2558 | static struct riscv_unwind_cache * |
dbbb1059 AB |
2559 | riscv_frame_cache (struct frame_info *this_frame, void **this_cache) |
2560 | { | |
78a3b0fa AB |
2561 | CORE_ADDR pc, start_addr; |
2562 | struct riscv_unwind_cache *cache; | |
dbbb1059 | 2563 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
78a3b0fa | 2564 | int numregs, regno; |
dbbb1059 AB |
2565 | |
2566 | if ((*this_cache) != NULL) | |
78a3b0fa | 2567 | return (struct riscv_unwind_cache *) *this_cache; |
dbbb1059 | 2568 | |
78a3b0fa AB |
2569 | cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache); |
2570 | cache->regs = trad_frame_alloc_saved_regs (this_frame); | |
2571 | (*this_cache) = cache; | |
dbbb1059 | 2572 | |
78a3b0fa AB |
2573 | /* Scan the prologue, filling in the cache. */ |
2574 | start_addr = get_frame_func (this_frame); | |
dbbb1059 | 2575 | pc = get_frame_pc (this_frame); |
78a3b0fa AB |
2576 | riscv_scan_prologue (gdbarch, start_addr, pc, cache); |
2577 | ||
2578 | /* We can now calculate the frame base address. */ | |
2579 | cache->frame_base | |
6c9d681b AB |
2580 | = (get_frame_register_signed (this_frame, cache->frame_base_reg) |
2581 | + cache->frame_base_offset); | |
78a3b0fa AB |
2582 | if (riscv_debug_unwinder) |
2583 | fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n", | |
2584 | core_addr_to_string (cache->frame_base), | |
2585 | gdbarch_register_name (gdbarch, | |
2586 | cache->frame_base_reg), | |
2587 | cache->frame_base_offset); | |
2588 | ||
2589 | /* The prologue scanner sets the address of registers stored to the stack | |
2590 | as the offset of that register from the frame base. The prologue | |
2591 | scanner doesn't know the actual frame base value, and so is unable to | |
2592 | compute the exact address. We do now know the frame base value, so | |
2593 | update the address of registers stored to the stack. */ | |
2594 | numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | |
2595 | for (regno = 0; regno < numregs; ++regno) | |
2596 | { | |
2597 | if (trad_frame_addr_p (cache->regs, regno)) | |
2598 | cache->regs[regno].addr += cache->frame_base; | |
2599 | } | |
2600 | ||
2601 | /* The previous $pc can be found wherever the $ra value can be found. | |
2602 | The previous $ra value is gone, this would have been stored be the | |
2603 | previous frame if required. */ | |
2604 | cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM]; | |
2605 | trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM); | |
2606 | ||
2607 | /* Build the frame id. */ | |
2608 | cache->this_id = frame_id_build (cache->frame_base, start_addr); | |
dbbb1059 | 2609 | |
78a3b0fa AB |
2610 | /* The previous $sp value is the frame base value. */ |
2611 | trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch), | |
2612 | cache->frame_base); | |
dbbb1059 | 2613 | |
78a3b0fa | 2614 | return cache; |
dbbb1059 AB |
2615 | } |
2616 | ||
2617 | /* Implement the this_id callback for RiscV frame unwinder. */ | |
2618 | ||
2619 | static void | |
2620 | riscv_frame_this_id (struct frame_info *this_frame, | |
2621 | void **prologue_cache, | |
2622 | struct frame_id *this_id) | |
2623 | { | |
78a3b0fa | 2624 | struct riscv_unwind_cache *cache; |
dbbb1059 | 2625 | |
78a3b0fa AB |
2626 | cache = riscv_frame_cache (this_frame, prologue_cache); |
2627 | *this_id = cache->this_id; | |
dbbb1059 AB |
2628 | } |
2629 | ||
2630 | /* Implement the prev_register callback for RiscV frame unwinder. */ | |
2631 | ||
2632 | static struct value * | |
2633 | riscv_frame_prev_register (struct frame_info *this_frame, | |
2634 | void **prologue_cache, | |
2635 | int regnum) | |
2636 | { | |
78a3b0fa | 2637 | struct riscv_unwind_cache *cache; |
dbbb1059 | 2638 | |
78a3b0fa AB |
2639 | cache = riscv_frame_cache (this_frame, prologue_cache); |
2640 | return trad_frame_get_prev_register (this_frame, cache->regs, regnum); | |
dbbb1059 AB |
2641 | } |
2642 | ||
2643 | /* Structure defining the RiscV normal frame unwind functions. Since we | |
2644 | are the fallback unwinder (DWARF unwinder is used first), we use the | |
2645 | default frame sniffer, which always accepts the frame. */ | |
2646 | ||
2647 | static const struct frame_unwind riscv_frame_unwind = | |
2648 | { | |
2649 | /*.type =*/ NORMAL_FRAME, | |
2650 | /*.stop_reason =*/ default_frame_unwind_stop_reason, | |
2651 | /*.this_id =*/ riscv_frame_this_id, | |
2652 | /*.prev_register =*/ riscv_frame_prev_register, | |
2653 | /*.unwind_data =*/ NULL, | |
2654 | /*.sniffer =*/ default_frame_sniffer, | |
2655 | /*.dealloc_cache =*/ NULL, | |
2656 | /*.prev_arch =*/ NULL, | |
2657 | }; | |
2658 | ||
2659 | /* Initialize the current architecture based on INFO. If possible, | |
2660 | re-use an architecture from ARCHES, which is a list of | |
2661 | architectures already created during this debugging session. | |
2662 | ||
2663 | Called e.g. at program startup, when reading a core file, and when | |
2664 | reading a binary file. */ | |
2665 | ||
2666 | static struct gdbarch * | |
2667 | riscv_gdbarch_init (struct gdbarch_info info, | |
2668 | struct gdbarch_list *arches) | |
2669 | { | |
2670 | struct gdbarch *gdbarch; | |
2671 | struct gdbarch_tdep *tdep; | |
2672 | struct gdbarch_tdep tmp_tdep; | |
dbbb1059 AB |
2673 | int i; |
2674 | ||
2675 | /* Ideally, we'd like to get as much information from the target for | |
2676 | things like register size, and whether the target has floating point | |
2677 | hardware. However, there are some things that the target can't tell | |
2678 | us, like, what ABI is being used. | |
2679 | ||
2680 | So, for now, we take as much information as possible from the ELF, | |
2681 | including things like register size, and FP hardware support, along | |
2682 | with information about the ABI. | |
2683 | ||
2684 | Information about this target is built up in TMP_TDEP, and then we | |
2685 | look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no | |
2686 | match is found we'll create a new gdbarch and copy TMP_TDEP over. */ | |
2687 | memset (&tmp_tdep, 0, sizeof (tmp_tdep)); | |
2688 | ||
2689 | if (info.abfd != NULL | |
2690 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
2691 | { | |
2692 | unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS]; | |
2693 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
2694 | ||
2695 | if (eclass == ELFCLASS32) | |
2696 | tmp_tdep.abi.fields.base_len = 1; | |
2697 | else if (eclass == ELFCLASS64) | |
2698 | tmp_tdep.abi.fields.base_len = 2; | |
2699 | else | |
2700 | internal_error (__FILE__, __LINE__, | |
2701 | _("unknown ELF header class %d"), eclass); | |
2702 | ||
2703 | if (e_flags & EF_RISCV_RVC) | |
27724bad | 2704 | tmp_tdep.core_features |= (1 << ('C' - 'A')); |
dbbb1059 AB |
2705 | |
2706 | if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE) | |
2707 | { | |
2708 | tmp_tdep.abi.fields.float_abi = 2; | |
2709 | tmp_tdep.core_features |= (1 << ('D' - 'A')); | |
2710 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2711 | } | |
2712 | else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) | |
2713 | { | |
2714 | tmp_tdep.abi.fields.float_abi = 1; | |
2715 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2716 | } | |
2717 | } | |
2718 | else | |
2719 | { | |
2720 | const struct bfd_arch_info *binfo = info.bfd_arch_info; | |
2721 | ||
2722 | if (binfo->bits_per_word == 32) | |
2723 | tmp_tdep.abi.fields.base_len = 1; | |
2724 | else if (binfo->bits_per_word == 64) | |
2725 | tmp_tdep.abi.fields.base_len = 2; | |
2726 | else | |
2727 | internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"), | |
2728 | binfo->bits_per_word); | |
2729 | } | |
2730 | ||
2731 | /* Find a candidate among the list of pre-declared architectures. */ | |
2732 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2733 | arches != NULL; | |
2734 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2735 | if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value) | |
2736 | return arches->gdbarch; | |
2737 | ||
2738 | /* None found, so create a new architecture from the information provided. */ | |
2739 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep); | |
2740 | gdbarch = gdbarch_alloc (&info, tdep); | |
2741 | memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep)); | |
2742 | ||
2743 | /* Target data types. */ | |
2744 | set_gdbarch_short_bit (gdbarch, 16); | |
2745 | set_gdbarch_int_bit (gdbarch, 32); | |
2746 | set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2747 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2748 | set_gdbarch_float_bit (gdbarch, 32); | |
2749 | set_gdbarch_double_bit (gdbarch, 64); | |
2750 | set_gdbarch_long_double_bit (gdbarch, 128); | |
2751 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
2752 | set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2753 | set_gdbarch_char_signed (gdbarch, 0); | |
2754 | ||
2755 | /* Information about the target architecture. */ | |
2756 | set_gdbarch_return_value (gdbarch, riscv_return_value); | |
2757 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc); | |
2758 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind); | |
2759 | ||
2760 | /* Register architecture. */ | |
dbbb1059 | 2761 | set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1); |
dbbb1059 AB |
2762 | set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM); |
2763 | set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM); | |
2764 | set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM); | |
2765 | set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM); | |
2766 | ||
2767 | /* Functions to supply register information. */ | |
2768 | set_gdbarch_register_name (gdbarch, riscv_register_name); | |
2769 | set_gdbarch_register_type (gdbarch, riscv_register_type); | |
2770 | set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info); | |
2771 | set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p); | |
2772 | ||
2773 | /* Functions to analyze frames. */ | |
dbbb1059 AB |
2774 | set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue); |
2775 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2776 | set_gdbarch_frame_align (gdbarch, riscv_frame_align); | |
2777 | ||
2778 | /* Functions to access frame data. */ | |
2779 | set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc); | |
2780 | set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp); | |
2781 | ||
2782 | /* Functions handling dummy frames. */ | |
2783 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
2784 | set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code); | |
2785 | set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call); | |
2786 | set_gdbarch_dummy_id (gdbarch, riscv_dummy_id); | |
2787 | ||
2788 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our own | |
2789 | unwinder. */ | |
2790 | dwarf2_append_unwinders (gdbarch); | |
2791 | frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind); | |
2792 | ||
dbbb1059 AB |
2793 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) |
2794 | user_reg_add (gdbarch, riscv_register_aliases[i].name, | |
2795 | value_of_riscv_user_reg, &riscv_register_aliases[i].regnum); | |
2796 | ||
117a0e99 JW |
2797 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
2798 | gdbarch_init_osabi (info, gdbarch); | |
2799 | ||
dbbb1059 AB |
2800 | return gdbarch; |
2801 | } | |
2802 | ||
5c720ed8 JW |
2803 | /* This decodes the current instruction and determines the address of the |
2804 | next instruction. */ | |
2805 | ||
2806 | static CORE_ADDR | |
2807 | riscv_next_pc (struct regcache *regcache, CORE_ADDR pc) | |
2808 | { | |
2809 | struct gdbarch *gdbarch = regcache->arch (); | |
2810 | struct riscv_insn insn; | |
2811 | CORE_ADDR next_pc; | |
2812 | ||
2813 | insn.decode (gdbarch, pc); | |
2814 | next_pc = pc + insn.length (); | |
2815 | ||
2816 | if (insn.opcode () == riscv_insn::JAL) | |
2817 | next_pc = pc + insn.imm_signed (); | |
2818 | else if (insn.opcode () == riscv_insn::JALR) | |
2819 | { | |
2820 | LONGEST source; | |
2821 | regcache->cooked_read (insn.rs1 (), &source); | |
2822 | next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1; | |
2823 | } | |
2824 | else if (insn.opcode () == riscv_insn::BEQ) | |
2825 | { | |
2826 | LONGEST src1, src2; | |
2827 | regcache->cooked_read (insn.rs1 (), &src1); | |
2828 | regcache->cooked_read (insn.rs2 (), &src2); | |
2829 | if (src1 == src2) | |
2830 | next_pc = pc + insn.imm_signed (); | |
2831 | } | |
2832 | else if (insn.opcode () == riscv_insn::BNE) | |
2833 | { | |
2834 | LONGEST src1, src2; | |
2835 | regcache->cooked_read (insn.rs1 (), &src1); | |
2836 | regcache->cooked_read (insn.rs2 (), &src2); | |
2837 | if (src1 != src2) | |
2838 | next_pc = pc + insn.imm_signed (); | |
2839 | } | |
2840 | else if (insn.opcode () == riscv_insn::BLT) | |
2841 | { | |
2842 | LONGEST src1, src2; | |
2843 | regcache->cooked_read (insn.rs1 (), &src1); | |
2844 | regcache->cooked_read (insn.rs2 (), &src2); | |
2845 | if (src1 < src2) | |
2846 | next_pc = pc + insn.imm_signed (); | |
2847 | } | |
2848 | else if (insn.opcode () == riscv_insn::BGE) | |
2849 | { | |
2850 | LONGEST src1, src2; | |
2851 | regcache->cooked_read (insn.rs1 (), &src1); | |
2852 | regcache->cooked_read (insn.rs2 (), &src2); | |
2853 | if (src1 >= src2) | |
2854 | next_pc = pc + insn.imm_signed (); | |
2855 | } | |
2856 | else if (insn.opcode () == riscv_insn::BLTU) | |
2857 | { | |
2858 | ULONGEST src1, src2; | |
2859 | regcache->cooked_read (insn.rs1 (), &src1); | |
2860 | regcache->cooked_read (insn.rs2 (), &src2); | |
2861 | if (src1 < src2) | |
2862 | next_pc = pc + insn.imm_signed (); | |
2863 | } | |
2864 | else if (insn.opcode () == riscv_insn::BGEU) | |
2865 | { | |
2866 | ULONGEST src1, src2; | |
2867 | regcache->cooked_read (insn.rs1 (), &src1); | |
2868 | regcache->cooked_read (insn.rs2 (), &src2); | |
2869 | if (src1 >= src2) | |
2870 | next_pc = pc + insn.imm_signed (); | |
2871 | } | |
2872 | ||
2873 | return next_pc; | |
2874 | } | |
2875 | ||
2876 | /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look | |
2877 | for the end of the sequence and put the breakpoint there. */ | |
2878 | ||
2879 | static bool | |
2880 | riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc, | |
2881 | CORE_ADDR *next_pc) | |
2882 | { | |
2883 | struct gdbarch *gdbarch = regcache->arch (); | |
2884 | struct riscv_insn insn; | |
2885 | CORE_ADDR cur_step_pc = pc; | |
2886 | CORE_ADDR last_addr = 0; | |
2887 | ||
2888 | /* First instruction has to be a load reserved. */ | |
2889 | insn.decode (gdbarch, cur_step_pc); | |
2890 | if (insn.opcode () != riscv_insn::LR) | |
2891 | return false; | |
2892 | cur_step_pc = cur_step_pc + insn.length (); | |
2893 | ||
2894 | /* Next instruction should be branch to exit. */ | |
2895 | insn.decode (gdbarch, cur_step_pc); | |
2896 | if (insn.opcode () != riscv_insn::BNE) | |
2897 | return false; | |
2898 | last_addr = cur_step_pc + insn.imm_signed (); | |
2899 | cur_step_pc = cur_step_pc + insn.length (); | |
2900 | ||
2901 | /* Next instruction should be store conditional. */ | |
2902 | insn.decode (gdbarch, cur_step_pc); | |
2903 | if (insn.opcode () != riscv_insn::SC) | |
2904 | return false; | |
2905 | cur_step_pc = cur_step_pc + insn.length (); | |
2906 | ||
2907 | /* Next instruction should be branch to start. */ | |
2908 | insn.decode (gdbarch, cur_step_pc); | |
2909 | if (insn.opcode () != riscv_insn::BNE) | |
2910 | return false; | |
2911 | if (pc != (cur_step_pc + insn.imm_signed ())) | |
2912 | return false; | |
2913 | cur_step_pc = cur_step_pc + insn.length (); | |
2914 | ||
2915 | /* We should now be at the end of the sequence. */ | |
2916 | if (cur_step_pc != last_addr) | |
2917 | return false; | |
2918 | ||
2919 | *next_pc = cur_step_pc; | |
2920 | return true; | |
2921 | } | |
2922 | ||
2923 | /* This is called just before we want to resume the inferior, if we want to | |
2924 | single-step it but there is no hardware or kernel single-step support. We | |
2925 | find the target of the coming instruction and breakpoint it. */ | |
2926 | ||
2927 | std::vector<CORE_ADDR> | |
2928 | riscv_software_single_step (struct regcache *regcache) | |
2929 | { | |
2930 | CORE_ADDR pc, next_pc; | |
2931 | ||
2932 | pc = regcache_read_pc (regcache); | |
2933 | ||
2934 | if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc)) | |
2935 | return {next_pc}; | |
2936 | ||
2937 | next_pc = riscv_next_pc (regcache, pc); | |
2938 | ||
2939 | return {next_pc}; | |
2940 | } | |
2941 | ||
dbbb1059 AB |
2942 | void |
2943 | _initialize_riscv_tdep (void) | |
2944 | { | |
2945 | gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL); | |
2946 | ||
dbbb1059 AB |
2947 | /* Add root prefix command for all "set debug riscv" and "show debug |
2948 | riscv" commands. */ | |
2949 | add_prefix_cmd ("riscv", no_class, set_debug_riscv_command, | |
2950 | _("RISC-V specific debug commands."), | |
2951 | &setdebugriscvcmdlist, "set debug riscv ", 0, | |
2952 | &setdebuglist); | |
2953 | ||
2954 | add_prefix_cmd ("riscv", no_class, show_debug_riscv_command, | |
2955 | _("RISC-V specific debug commands."), | |
2956 | &showdebugriscvcmdlist, "show debug riscv ", 0, | |
2957 | &showdebuglist); | |
2958 | ||
f37bc8b1 JB |
2959 | add_setshow_zuinteger_cmd ("breakpoints", class_maintenance, |
2960 | &riscv_debug_breakpoints, _("\ | |
2961 | Set riscv breakpoint debugging."), _("\ | |
2962 | Show riscv breakpoint debugging."), _("\ | |
2963 | When non-zero, print debugging information for the riscv specific parts\n\ | |
2964 | of the breakpoint mechanism."), | |
2965 | NULL, | |
2966 | show_riscv_debug_variable, | |
2967 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
2968 | ||
dbbb1059 AB |
2969 | add_setshow_zuinteger_cmd ("infcall", class_maintenance, |
2970 | &riscv_debug_infcall, _("\ | |
2971 | Set riscv inferior call debugging."), _("\ | |
2972 | Show riscv inferior call debugging."), _("\ | |
2973 | When non-zero, print debugging information for the riscv specific parts\n\ | |
2974 | of the inferior call mechanism."), | |
2975 | NULL, | |
2976 | show_riscv_debug_variable, | |
2977 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
78a3b0fa AB |
2978 | |
2979 | add_setshow_zuinteger_cmd ("unwinder", class_maintenance, | |
2980 | &riscv_debug_unwinder, _("\ | |
2981 | Set riscv stack unwinding debugging."), _("\ | |
2982 | Show riscv stack unwinding debugging."), _("\ | |
2983 | When non-zero, print debugging information for the riscv specific parts\n\ | |
2984 | of the stack unwinding mechanism."), | |
2985 | NULL, | |
2986 | show_riscv_debug_variable, | |
2987 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
dbbb1059 AB |
2988 | |
2989 | /* Add root prefix command for all "set riscv" and "show riscv" commands. */ | |
2990 | add_prefix_cmd ("riscv", no_class, set_riscv_command, | |
2991 | _("RISC-V specific commands."), | |
2992 | &setriscvcmdlist, "set riscv ", 0, &setlist); | |
2993 | ||
2994 | add_prefix_cmd ("riscv", no_class, show_riscv_command, | |
2995 | _("RISC-V specific commands."), | |
2996 | &showriscvcmdlist, "show riscv ", 0, &showlist); | |
2997 | ||
2998 | ||
2999 | use_compressed_breakpoints = AUTO_BOOLEAN_AUTO; | |
3000 | add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class, | |
3001 | &use_compressed_breakpoints, | |
3002 | _("\ | |
3003 | Set debugger's use of compressed breakpoints."), _(" \ | |
3004 | Show debugger's use of compressed breakpoints."), _("\ | |
f37bc8b1 JB |
3005 | Debugging compressed code requires compressed breakpoints to be used. If\n\ |
3006 | left to 'auto' then gdb will use them if the existing instruction is a\n\ | |
3007 | compressed instruction. If that doesn't give the correct behavior, then\n\ | |
3008 | this option can be used."), | |
dbbb1059 AB |
3009 | NULL, |
3010 | show_use_compressed_breakpoints, | |
3011 | &setriscvcmdlist, | |
3012 | &showriscvcmdlist); | |
3013 | } |