projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 06ab9219 TT |
1 | /* Target-dependent header for the RISC-V architecture, for GDB, the |
| 2 | GNU Debugger. | |
| dbbb1059 AB |
3 | |
| 4 | Copyright (C) 2018 Free Software Foundation, Inc. | |
| 5 | ||
| dbbb1059 AB |
6 | This file is part of GDB. |
| 7 | ||
| 8 | This program is free software; you can redistribute it and/or modify | |
| 9 | it under the terms of the GNU General Public License as published by | |
| 10 | the Free Software Foundation; either version 3 of the License, or | |
| 11 | (at your option) any later version. | |
| 12 | ||
| 13 | This program is distributed in the hope that it will be useful, | |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | GNU General Public License for more details. | |
| 17 | ||
| 18 | You should have received a copy of the GNU General Public License | |
| 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
| 20 | ||
| 21 | #ifndef RISCV_TDEP_H | |
| 22 | #define RISCV_TDEP_H | |
| 23 | ||
| 24 | /* RiscV register numbers. */ | |
| 25 | enum | |
| 26 | { | |
| 27 | RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */ | |
| 28 | RISCV_RA_REGNUM = 1, /* Return Address. */ | |
| 29 | RISCV_SP_REGNUM = 2, /* Stack Pointer. */ | |
| 30 | RISCV_GP_REGNUM = 3, /* Global Pointer. */ | |
| 31 | RISCV_TP_REGNUM = 4, /* Thread Pointer. */ | |
| 32 | RISCV_FP_REGNUM = 8, /* Frame Pointer. */ | |
| 33 | RISCV_A0_REGNUM = 10, /* First argument. */ | |
| 34 | RISCV_A1_REGNUM = 11, /* Second argument. */ | |
| 35 | RISCV_PC_REGNUM = 32, /* Program Counter. */ | |
| 36 | ||
| 37 | RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */ | |
| 38 | RISCV_FA0_REGNUM = 43, | |
| 39 | RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1, | |
| 40 | RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ | |
| 41 | ||
| 42 | RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ | |
| 06ab9219 TT |
43 | #define DECLARE_CSR(name, num) \ |
| 44 | RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num, | |
| dbbb1059 AB |
45 | #include "opcode/riscv-opc.h" |
| 46 | #undef DECLARE_CSR | |
| 47 | RISCV_LAST_CSR_REGNUM = 4160, | |
| ce73f310 | 48 | RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM, |
| dbbb1059 AB |
49 | |
| 50 | RISCV_PRIV_REGNUM = 4161, | |
| 51 | ||
| 52 | RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM | |
| 53 | }; | |
| 54 | ||
| 55 | /* RISC-V specific per-architecture information. */ | |
| 56 | struct gdbarch_tdep | |
| 57 | { | |
| 58 | union | |
| 59 | { | |
| 60 | /* Provide access to the whole ABI in one value. */ | |
| 61 | unsigned value; | |
| 62 | ||
| 63 | struct | |
| 64 | { | |
| 65 | /* Encode the base machine length following the same rules as in the | |
| 66 | MISA register. */ | |
| 67 | unsigned base_len : 2; | |
| 68 | ||
| 69 | /* Encode which floating point ABI is in use following the same rules | |
| 70 | as the ELF e_flags field. */ | |
| 71 | unsigned float_abi : 2; | |
| 72 | } fields; | |
| 73 | } abi; | |
| 74 | ||
| 75 | /* Only the least significant 26 bits are (possibly) valid, and indicate | |
| 76 | features that are supported on the target. These could be cached from | |
| 77 | the target, or read from the executable when available. */ | |
| 78 | unsigned core_features; | |
| 79 | }; | |
| 80 | ||
| 411baa47 JW |
81 | /* Return the width in bytes of the general purpose registers for GDBARCH. */ |
| 82 | extern int riscv_isa_xlen (struct gdbarch *gdbarch); | |
| 83 | ||
| 5c720ed8 | 84 | /* Single step based on where the current instruction will take us. */ |
| 06ab9219 TT |
85 | extern std::vector<CORE_ADDR> riscv_software_single_step |
| 86 | (struct regcache *regcache); | |
| 5c720ed8 | 87 | |
| dbbb1059 | 88 | #endif /* RISCV_TDEP_H */ |