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dbbb1059 AB |
1 | /* Target-dependent header for the RISC-V architecture, for GDB, the GNU Debugger. |
2 | ||
3 | Copyright (C) 2018 Free Software Foundation, Inc. | |
4 | ||
dbbb1059 AB |
5 | This file is part of GDB. |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifndef RISCV_TDEP_H | |
21 | #define RISCV_TDEP_H | |
22 | ||
23 | /* RiscV register numbers. */ | |
24 | enum | |
25 | { | |
26 | RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */ | |
27 | RISCV_RA_REGNUM = 1, /* Return Address. */ | |
28 | RISCV_SP_REGNUM = 2, /* Stack Pointer. */ | |
29 | RISCV_GP_REGNUM = 3, /* Global Pointer. */ | |
30 | RISCV_TP_REGNUM = 4, /* Thread Pointer. */ | |
31 | RISCV_FP_REGNUM = 8, /* Frame Pointer. */ | |
32 | RISCV_A0_REGNUM = 10, /* First argument. */ | |
33 | RISCV_A1_REGNUM = 11, /* Second argument. */ | |
34 | RISCV_PC_REGNUM = 32, /* Program Counter. */ | |
35 | ||
36 | RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */ | |
37 | RISCV_FA0_REGNUM = 43, | |
38 | RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1, | |
39 | RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ | |
40 | ||
41 | RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ | |
42 | #define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num, | |
43 | #include "opcode/riscv-opc.h" | |
44 | #undef DECLARE_CSR | |
45 | RISCV_LAST_CSR_REGNUM = 4160, | |
46 | RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10, | |
47 | ||
48 | RISCV_PRIV_REGNUM = 4161, | |
49 | ||
50 | RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM | |
51 | }; | |
52 | ||
53 | /* RISC-V specific per-architecture information. */ | |
54 | struct gdbarch_tdep | |
55 | { | |
56 | union | |
57 | { | |
58 | /* Provide access to the whole ABI in one value. */ | |
59 | unsigned value; | |
60 | ||
61 | struct | |
62 | { | |
63 | /* Encode the base machine length following the same rules as in the | |
64 | MISA register. */ | |
65 | unsigned base_len : 2; | |
66 | ||
67 | /* Encode which floating point ABI is in use following the same rules | |
68 | as the ELF e_flags field. */ | |
69 | unsigned float_abi : 2; | |
70 | } fields; | |
71 | } abi; | |
72 | ||
73 | /* Only the least significant 26 bits are (possibly) valid, and indicate | |
74 | features that are supported on the target. These could be cached from | |
75 | the target, or read from the executable when available. */ | |
76 | unsigned core_features; | |
77 | }; | |
78 | ||
79 | #endif /* RISCV_TDEP_H */ |