Commit | Line | Data |
---|---|---|
06ab9219 TT |
1 | /* Target-dependent header for the RISC-V architecture, for GDB, the |
2 | GNU Debugger. | |
dbbb1059 AB |
3 | |
4 | Copyright (C) 2018 Free Software Foundation, Inc. | |
5 | ||
dbbb1059 AB |
6 | This file is part of GDB. |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #ifndef RISCV_TDEP_H | |
22 | #define RISCV_TDEP_H | |
23 | ||
b5ffee31 AB |
24 | #include "arch/riscv.h" |
25 | ||
dbbb1059 AB |
26 | /* RiscV register numbers. */ |
27 | enum | |
28 | { | |
29 | RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */ | |
30 | RISCV_RA_REGNUM = 1, /* Return Address. */ | |
31 | RISCV_SP_REGNUM = 2, /* Stack Pointer. */ | |
32 | RISCV_GP_REGNUM = 3, /* Global Pointer. */ | |
33 | RISCV_TP_REGNUM = 4, /* Thread Pointer. */ | |
34 | RISCV_FP_REGNUM = 8, /* Frame Pointer. */ | |
35 | RISCV_A0_REGNUM = 10, /* First argument. */ | |
36 | RISCV_A1_REGNUM = 11, /* Second argument. */ | |
37 | RISCV_PC_REGNUM = 32, /* Program Counter. */ | |
38 | ||
78a3b0fa AB |
39 | RISCV_NUM_INTEGER_REGS = 32, |
40 | ||
dbbb1059 AB |
41 | RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */ |
42 | RISCV_FA0_REGNUM = 43, | |
43 | RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1, | |
44 | RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ | |
45 | ||
46 | RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ | |
06ab9219 TT |
47 | #define DECLARE_CSR(name, num) \ |
48 | RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num, | |
dbbb1059 AB |
49 | #include "opcode/riscv-opc.h" |
50 | #undef DECLARE_CSR | |
51 | RISCV_LAST_CSR_REGNUM = 4160, | |
ce73f310 | 52 | RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM, |
dbbb1059 AB |
53 | |
54 | RISCV_PRIV_REGNUM = 4161, | |
55 | ||
56 | RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM | |
57 | }; | |
58 | ||
fb44d95a AB |
59 | /* RiscV DWARF register numbers. */ |
60 | enum | |
61 | { | |
62 | RISCV_DWARF_REGNUM_X0 = 0, | |
63 | RISCV_DWARF_REGNUM_X31 = 31, | |
64 | RISCV_DWARF_REGNUM_F0 = 32, | |
65 | RISCV_DWARF_REGNUM_F31 = 63, | |
66 | }; | |
67 | ||
dbbb1059 AB |
68 | /* RISC-V specific per-architecture information. */ |
69 | struct gdbarch_tdep | |
70 | { | |
b5ffee31 AB |
71 | /* Features about the target that impact how the gdbarch is configured. |
72 | Two gdbarch instances are compatible only if this field matches. */ | |
73 | struct riscv_gdbarch_features features; | |
270b9329 JW |
74 | |
75 | /* ISA-specific data types. */ | |
b5ffee31 | 76 | struct type *riscv_fpreg_d_type = nullptr; |
dbbb1059 AB |
77 | }; |
78 | ||
8a613826 JW |
79 | |
80 | /* Return the width in bytes of the general purpose registers for GDBARCH. | |
81 | Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or | |
82 | RV128. */ | |
411baa47 JW |
83 | extern int riscv_isa_xlen (struct gdbarch *gdbarch); |
84 | ||
8a613826 JW |
85 | /* Return the width in bytes of the floating point registers for GDBARCH. |
86 | If this architecture has no floating point registers, then return 0. | |
87 | Possible values are 4, 8, or 16 for depending on which of single, double | |
88 | or quad floating point support is available. */ | |
89 | extern int riscv_isa_flen (struct gdbarch *gdbarch); | |
90 | ||
5c720ed8 | 91 | /* Single step based on where the current instruction will take us. */ |
06ab9219 TT |
92 | extern std::vector<CORE_ADDR> riscv_software_single_step |
93 | (struct regcache *regcache); | |
5c720ed8 | 94 | |
dbbb1059 | 95 | #endif /* RISCV_TDEP_H */ |