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2004-06-01 Andrew Cagney <cagney@gnu.org>
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6
AC		 2
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
5 Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
c906108c 13
c5aa993b
JM		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b
JM		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
c906108c
SS		 23
24#include "defs.h"
25#include "frame.h"
26#include "inferior.h"
27#include "symtab.h"
28#include "target.h"
29#include "gdbcore.h"
30#include "gdbcmd.h"
c906108c 31#include "objfiles.h"
7a78ae4e 32#include "arch-utils.h"
4e052eda 33#include "regcache.h"
d195bc9f 34#include "regset.h"
d16aafd8 35#include "doublest.h"
fd0407d6 36#include "value.h"
1fcc0bb8 37#include "parser-defs.h"
4be87837 38#include "osabi.h"
7a78ae4e 39
2fccf04a 40#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 41#include "coff/internal.h" /* for libcoff.h */
2fccf04a 42#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 43#include "coff/xcoff.h"
44#include "libxcoff.h"
7a78ae4e 45
9aa1e687 46#include "elf-bfd.h"
7a78ae4e 47
6ded7999 48#include "solib-svr4.h"
9aa1e687 49#include "ppc-tdep.h"
7a78ae4e 50
338ef23d 51#include "gdb_assert.h"
a89aa300 52#include "dis-asm.h"
338ef23d 53
61a65099
KB		 54#include "trad-frame.h"
55#include "frame-unwind.h"
56#include "frame-base.h"
57
7a78ae4e
ND		 58/* If the kernel has to deliver a signal, it pushes a sigcontext
59 structure on the stack and then calls the signal handler, passing
60 the address of the sigcontext in an argument register. Usually
61 the signal handler doesn't save this register, so we have to
62 access the sigcontext structure via an offset from the signal handler
63 frame.
64 The following constants were determined by experimentation on AIX 3.2. */
65#define SIG_FRAME_PC_OFFSET 96
66#define SIG_FRAME_LR_OFFSET 108
67#define SIG_FRAME_FP_OFFSET 284
68
7a78ae4e
ND		 69/* To be used by skip_prologue. */
70
71struct rs6000_framedata
72 {
73 int offset; /* total size of frame --- the distance
74 by which we decrement sp to allocate
75 the frame */
76 int saved_gpr; /* smallest # of saved gpr */
77 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 78 int saved_vr; /* smallest # of saved vr */
96ff0de4 79 int saved_ev; /* smallest # of saved ev */
7a78ae4e
ND		 80 int alloca_reg; /* alloca register number (frame ptr) */
81 char frameless; /* true if frameless functions. */
82 char nosavedpc; /* true if pc not saved. */
83 int gpr_offset; /* offset of saved gprs from prev sp */
84 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 85 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 86 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e
ND		 87 int lr_offset; /* offset of saved lr */
88 int cr_offset; /* offset of saved cr */
6be8bc0c 89 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 90 };
91
92/* Description of a single register. */
93
94struct reg
95 {
96 char *name; /* name of register */
97 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
98 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
99 unsigned char fpr; /* whether register is floating-point */
489461e2 100 unsigned char pseudo; /* whether register is pseudo */
7a78ae4e
ND		 101 };
102
c906108c
SS		 103/* Breakpoint shadows for the single step instructions will be kept here. */
104
c5aa993b
JM		 105static struct sstep_breaks
106 {
107 /* Address, or 0 if this is not in use. */
108 CORE_ADDR address;
109 /* Shadow contents. */
110 char data[4];
111 }
112stepBreaks[2];
c906108c
SS		 113
114/* Hook for determining the TOC address when calling functions in the
115 inferior under AIX. The initialization code in rs6000-nat.c sets
116 this hook to point to find_toc_address. */
117
7a78ae4e
ND		 118CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
119
120/* Hook to set the current architecture when starting a child process.
121 rs6000-nat.c sets this. */
122
123void (*rs6000_set_host_arch_hook) (int) = NULL;
c906108c
SS		 124
125/* Static function prototypes */
126
a14ed312
KB		 127static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
128 CORE_ADDR safety);
077276e8
KB		 129static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
130 struct rs6000_framedata *);
c906108c 131
64b84175
KB		 132/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
133int
134altivec_register_p (int regno)
135{
136 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
137 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
138 return 0;
139 else
140 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
141}
142
383f0f5b 143
867e2dc5
JB		 144/* Return true if REGNO is an SPE register, false otherwise. */
145int
146spe_register_p (int regno)
147{
148 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
149
150 /* Is it a reference to EV0 -- EV31, and do we have those? */
151 if (tdep->ppc_ev0_regnum >= 0
152 && tdep->ppc_ev31_regnum >= 0
153 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
154 return 1;
155
156 /* Is it a reference to the 64-bit accumulator, and do we have that? */
157 if (tdep->ppc_acc_regnum >= 0
158 && tdep->ppc_acc_regnum == regno)
159 return 1;
160
161 /* Is it a reference to the SPE floating-point status and control register,
162 and do we have that? */
163 if (tdep->ppc_spefscr_regnum >= 0
164 && tdep->ppc_spefscr_regnum == regno)
165 return 1;
166
167 return 0;
168}
169
170
383f0f5b
JB		 171/* Return non-zero if the architecture described by GDBARCH has
172 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 173int
174ppc_floating_point_unit_p (struct gdbarch *gdbarch)
175{
383f0f5b
JB		 176 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
177
178 return (tdep->ppc_fp0_regnum >= 0
179 && tdep->ppc_fpscr_regnum >= 0);
0a613259 180}
d195bc9f
MK		 181\f
182
183/* Register set support functions. */
184
185static void
186ppc_supply_reg (struct regcache *regcache, int regnum,
187 const char *regs, size_t offset)
188{
189 if (regnum != -1 && offset != -1)
190 regcache_raw_supply (regcache, regnum, regs + offset);
191}
192
193static void
194ppc_collect_reg (const struct regcache *regcache, int regnum,
195 char *regs, size_t offset)
196{
197 if (regnum != -1 && offset != -1)
198 regcache_raw_collect (regcache, regnum, regs + offset);
199}
200
201/* Supply register REGNUM in the general-purpose register set REGSET
202 from the buffer specified by GREGS and LEN to register cache
203 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
204
205void
206ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
207 int regnum, const void *gregs, size_t len)
208{
209 struct gdbarch *gdbarch = get_regcache_arch (regcache);
210 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
211 const struct ppc_reg_offsets *offsets = regset->descr;
212 size_t offset;
213 int i;
214
cdf2c5f5 215 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
063715bf 216 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
cdf2c5f5 217 i++, offset += 4)
d195bc9f
MK		 218 {
219 if (regnum == -1 || regnum == i)
220 ppc_supply_reg (regcache, i, gregs, offset);
221 }
222
223 if (regnum == -1 || regnum == PC_REGNUM)
224 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
225 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
226 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
227 gregs, offsets->ps_offset);
228 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
229 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
230 gregs, offsets->cr_offset);
231 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
232 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
233 gregs, offsets->lr_offset);
234 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
235 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
236 gregs, offsets->ctr_offset);
237 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
238 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
239 gregs, offsets->cr_offset);
240 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
241 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
242}
243
244/* Supply register REGNUM in the floating-point register set REGSET
245 from the buffer specified by FPREGS and LEN to register cache
246 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
247
248void
249ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
250 int regnum, const void *fpregs, size_t len)
251{
252 struct gdbarch *gdbarch = get_regcache_arch (regcache);
253 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
254 const struct ppc_reg_offsets *offsets = regset->descr;
255 size_t offset;
256 int i;
257
383f0f5b
JB		 258 gdb_assert (ppc_floating_point_unit_p (gdbarch));
259
d195bc9f 260 offset = offsets->f0_offset;
366f009f
JB		 261 for (i = tdep->ppc_fp0_regnum;
262 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
263 i++, offset += 4)
d195bc9f
MK		 264 {
265 if (regnum == -1 || regnum == i)
266 ppc_supply_reg (regcache, i, fpregs, offset);
267 }
268
269 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
270 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
271 fpregs, offsets->fpscr_offset);
272}
273
274/* Collect register REGNUM in the general-purpose register set
275 REGSET. from register cache REGCACHE into the buffer specified by
276 GREGS and LEN. If REGNUM is -1, do this for all registers in
277 REGSET. */
278
279void
280ppc_collect_gregset (const struct regset *regset,
281 const struct regcache *regcache,
282 int regnum, void *gregs, size_t len)
283{
284 struct gdbarch *gdbarch = get_regcache_arch (regcache);
285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
286 const struct ppc_reg_offsets *offsets = regset->descr;
287 size_t offset;
288 int i;
289
290 offset = offsets->r0_offset;
cdf2c5f5 291 for (i = tdep->ppc_gp0_regnum;
063715bf 292 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
cdf2c5f5 293 i++, offset += 4)
d195bc9f
MK		 294 {
295 if (regnum == -1 || regnum == i)
2e56e9c1 296 ppc_collect_reg (regcache, i, gregs, offset);
d195bc9f
MK		 297 }
298
299 if (regnum == -1 || regnum == PC_REGNUM)
300 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
301 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
302 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
303 gregs, offsets->ps_offset);
304 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
305 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
306 gregs, offsets->cr_offset);
307 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
308 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
309 gregs, offsets->lr_offset);
310 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
311 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
312 gregs, offsets->ctr_offset);
313 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
314 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
315 gregs, offsets->xer_offset);
316 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
317 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
318 gregs, offsets->mq_offset);
319}
320
321/* Collect register REGNUM in the floating-point register set
322 REGSET. from register cache REGCACHE into the buffer specified by
323 FPREGS and LEN. If REGNUM is -1, do this for all registers in
324 REGSET. */
325
326void
327ppc_collect_fpregset (const struct regset *regset,
328 const struct regcache *regcache,
329 int regnum, void *fpregs, size_t len)
330{
331 struct gdbarch *gdbarch = get_regcache_arch (regcache);
332 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
333 const struct ppc_reg_offsets *offsets = regset->descr;
334 size_t offset;
335 int i;
336
383f0f5b
JB		 337 gdb_assert (ppc_floating_point_unit_p (gdbarch));
338
d195bc9f 339 offset = offsets->f0_offset;
366f009f
JB		 340 for (i = tdep->ppc_fp0_regnum;
341 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
342 i++, offset += 4)
d195bc9f
MK		 343 {
344 if (regnum == -1 || regnum == i)
345 ppc_collect_reg (regcache, regnum, fpregs, offset);
346 }
347
348 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
349 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
350 fpregs, offsets->fpscr_offset);
351}
352\f
0a613259 353
7a78ae4e 354/* Read a LEN-byte address from debugged memory address MEMADDR. */
c906108c 355
7a78ae4e
ND		 356static CORE_ADDR
357read_memory_addr (CORE_ADDR memaddr, int len)
358{
359 return read_memory_unsigned_integer (memaddr, len);
360}
c906108c 361
7a78ae4e
ND		 362static CORE_ADDR
363rs6000_skip_prologue (CORE_ADDR pc)
b83266a0
SS		 364{
365 struct rs6000_framedata frame;
077276e8 366 pc = skip_prologue (pc, 0, &frame);
b83266a0
SS		 367 return pc;
368}
369
370
c906108c
SS		 371/* Fill in fi->saved_regs */
372
373struct frame_extra_info
374{
375 /* Functions calling alloca() change the value of the stack
376 pointer. We need to use initial stack pointer (which is saved in
377 r31 by gcc) in such cases. If a compiler emits traceback table,
378 then we should use the alloca register specified in traceback
379 table. FIXME. */
c5aa993b 380 CORE_ADDR initial_sp; /* initial stack pointer. */
c906108c
SS		 381};
382
143985b7 383/* Get the ith function argument for the current function. */
b9362cc7 384static CORE_ADDR
143985b7
AF		 385rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
386 struct type *type)
387{
388 CORE_ADDR addr;
7f5f525d 389 get_frame_register (frame, 3 + argi, &addr);
143985b7
AF		 390 return addr;
391}
392
c906108c
SS		 393/* Calculate the destination of a branch/jump. Return -1 if not a branch. */
394
395static CORE_ADDR
7a78ae4e 396branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
c906108c
SS		 397{
398 CORE_ADDR dest;
399 int immediate;
400 int absolute;
401 int ext_op;
402
403 absolute = (int) ((instr >> 1) & 1);
404
c5aa993b
JM		 405 switch (opcode)
406 {
407 case 18:
408 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
409 if (absolute)
410 dest = immediate;
411 else
412 dest = pc + immediate;
413 break;
414
415 case 16:
416 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
417 if (absolute)
418 dest = immediate;
419 else
420 dest = pc + immediate;
421 break;
422
423 case 19:
424 ext_op = (instr >> 1) & 0x3ff;
425
426 if (ext_op == 16) /* br conditional register */
427 {
2188cbdd 428 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
c5aa993b
JM		 429
430 /* If we are about to return from a signal handler, dest is
431 something like 0x3c90. The current frame is a signal handler
432 caller frame, upon completion of the sigreturn system call
433 execution will return to the saved PC in the frame. */
434 if (dest < TEXT_SEGMENT_BASE)
435 {
436 struct frame_info *fi;
437
438 fi = get_current_frame ();
439 if (fi != NULL)
8b36eed8 440 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
21283beb 441 gdbarch_tdep (current_gdbarch)->wordsize);
c5aa993b
JM		 442 }
443 }
444
445 else if (ext_op == 528) /* br cond to count reg */
446 {
2188cbdd 447 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
c5aa993b
JM		 448
449 /* If we are about to execute a system call, dest is something
450 like 0x22fc or 0x3b00. Upon completion the system call
451 will return to the address in the link register. */
452 if (dest < TEXT_SEGMENT_BASE)
2188cbdd 453 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
c5aa993b
JM		 454 }
455 else
456 return -1;
457 break;
c906108c 458
c5aa993b
JM		 459 default:
460 return -1;
461 }
c906108c
SS		 462 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
463}
464
465
466/* Sequence of bytes for breakpoint instruction. */
467
f4f9705a 468const static unsigned char *
7a78ae4e 469rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
c906108c 470{
aaab4dba
AC		 471 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
472 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 473 *bp_size = 4;
d7449b42 474 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
c906108c
SS		 475 return big_breakpoint;
476 else
477 return little_breakpoint;
478}
479
480
481/* AIX does not support PT_STEP. Simulate it. */
482
483void
379d08a1
AC		 484rs6000_software_single_step (enum target_signal signal,
485 int insert_breakpoints_p)
c906108c 486{
7c40d541
KB		 487 CORE_ADDR dummy;
488 int breakp_sz;
f4f9705a 489 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
c906108c
SS		 490 int ii, insn;
491 CORE_ADDR loc;
492 CORE_ADDR breaks[2];
493 int opcode;
494
c5aa993b
JM		 495 if (insert_breakpoints_p)
496 {
c906108c 497
c5aa993b 498 loc = read_pc ();
c906108c 499
c5aa993b 500 insn = read_memory_integer (loc, 4);
c906108c 501
7c40d541 502 breaks[0] = loc + breakp_sz;
c5aa993b
JM		 503 opcode = insn >> 26;
504 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
c906108c 505
c5aa993b
JM		 506 /* Don't put two breakpoints on the same address. */
507 if (breaks[1] == breaks[0])
508 breaks[1] = -1;
c906108c 509
c5aa993b 510 stepBreaks[1].address = 0;
c906108c 511
c5aa993b
JM		 512 for (ii = 0; ii < 2; ++ii)
513 {
c906108c 514
c5aa993b
JM		 515 /* ignore invalid breakpoint. */
516 if (breaks[ii] == -1)
517 continue;
7c40d541 518 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
c5aa993b
JM		 519 stepBreaks[ii].address = breaks[ii];
520 }
c906108c 521
c5aa993b
JM		 522 }
523 else
524 {
c906108c 525
c5aa993b
JM		 526 /* remove step breakpoints. */
527 for (ii = 0; ii < 2; ++ii)
528 if (stepBreaks[ii].address != 0)
7c40d541
KB		 529 target_remove_breakpoint (stepBreaks[ii].address,
530 stepBreaks[ii].data);
c5aa993b 531 }
c906108c 532 errno = 0; /* FIXME, don't ignore errors! */
c5aa993b 533 /* What errors? {read,write}_memory call error(). */
c906108c
SS		 534}
535
536
537/* return pc value after skipping a function prologue and also return
538 information about a function frame.
539
540 in struct rs6000_framedata fdata:
c5aa993b
JM		 541 - frameless is TRUE, if function does not have a frame.
542 - nosavedpc is TRUE, if function does not save %pc value in its frame.
543 - offset is the initial size of this stack frame --- the amount by
544 which we decrement the sp to allocate the frame.
545 - saved_gpr is the number of the first saved gpr.
546 - saved_fpr is the number of the first saved fpr.
6be8bc0c 547 - saved_vr is the number of the first saved vr.
96ff0de4 548 - saved_ev is the number of the first saved ev.
c5aa993b
JM		 549 - alloca_reg is the number of the register used for alloca() handling.
550 Otherwise -1.
551 - gpr_offset is the offset of the first saved gpr from the previous frame.
552 - fpr_offset is the offset of the first saved fpr from the previous frame.
6be8bc0c 553 - vr_offset is the offset of the first saved vr from the previous frame.
96ff0de4 554 - ev_offset is the offset of the first saved ev from the previous frame.
c5aa993b
JM		 555 - lr_offset is the offset of the saved lr
556 - cr_offset is the offset of the saved cr
6be8bc0c 557 - vrsave_offset is the offset of the saved vrsave register
c5aa993b 558 */
c906108c
SS		 559
560#define SIGNED_SHORT(x) \
561 ((sizeof (short) == 2) \
562 ? ((int)(short)(x)) \
563 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
564
565#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
566
55d05f3b
KB		 567/* Limit the number of skipped non-prologue instructions, as the examining
568 of the prologue is expensive. */
569static int max_skip_non_prologue_insns = 10;
570
571/* Given PC representing the starting address of a function, and
572 LIM_PC which is the (sloppy) limit to which to scan when looking
573 for a prologue, attempt to further refine this limit by using
574 the line data in the symbol table. If successful, a better guess
575 on where the prologue ends is returned, otherwise the previous
576 value of lim_pc is returned. */
634aa483
AC		 577
578/* FIXME: cagney/2004-02-14: This function and logic have largely been
579 superseded by skip_prologue_using_sal. */
580
55d05f3b
KB		 581static CORE_ADDR
582refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
583{
584 struct symtab_and_line prologue_sal;
585
586 prologue_sal = find_pc_line (pc, 0);
587 if (prologue_sal.line != 0)
588 {
589 int i;
590 CORE_ADDR addr = prologue_sal.end;
591
592 /* Handle the case in which compiler's optimizer/scheduler
593 has moved instructions into the prologue. We scan ahead
594 in the function looking for address ranges whose corresponding
595 line number is less than or equal to the first one that we
596 found for the function. (It can be less than when the
597 scheduler puts a body instruction before the first prologue
598 instruction.) */
599 for (i = 2 * max_skip_non_prologue_insns;
600 i > 0 && (lim_pc == 0 || addr < lim_pc);
601 i--)
602 {
603 struct symtab_and_line sal;
604
605 sal = find_pc_line (addr, 0);
606 if (sal.line == 0)
607 break;
608 if (sal.line <= prologue_sal.line
609 && sal.symtab == prologue_sal.symtab)
610 {
611 prologue_sal = sal;
612 }
613 addr = sal.end;
614 }
615
616 if (lim_pc == 0 || prologue_sal.end < lim_pc)
617 lim_pc = prologue_sal.end;
618 }
619 return lim_pc;
620}
621
773df3e5
JB		 622/* Return nonzero if the given instruction OP can be part of the prologue
623 of a function and saves a parameter on the stack. FRAMEP should be
624 set if one of the previous instructions in the function has set the
625 Frame Pointer. */
626
627static int
628store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
629{
630 /* Move parameters from argument registers to temporary register. */
631 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
632 {
633 /* Rx must be scratch register r0. */
634 const int rx_regno = (op >> 16) & 31;
635 /* Ry: Only r3 - r10 are used for parameter passing. */
636 const int ry_regno = GET_SRC_REG (op);
637
638 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
639 {
640 *r0_contains_arg = 1;
641 return 1;
642 }
643 else
644 return 0;
645 }
646
647 /* Save a General Purpose Register on stack. */
648
649 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
650 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
651 {
652 /* Rx: Only r3 - r10 are used for parameter passing. */
653 const int rx_regno = GET_SRC_REG (op);
654
655 return (rx_regno >= 3 && rx_regno <= 10);
656 }
657
658 /* Save a General Purpose Register on stack via the Frame Pointer. */
659
660 if (framep &&
661 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
662 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
663 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
664 {
665 /* Rx: Usually, only r3 - r10 are used for parameter passing.
666 However, the compiler sometimes uses r0 to hold an argument. */
667 const int rx_regno = GET_SRC_REG (op);
668
669 return ((rx_regno >= 3 && rx_regno <= 10)
670 || (rx_regno == 0 && *r0_contains_arg));
671 }
672
673 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
674 {
675 /* Only f2 - f8 are used for parameter passing. */
676 const int src_regno = GET_SRC_REG (op);
677
678 return (src_regno >= 2 && src_regno <= 8);
679 }
680
681 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
682 {
683 /* Only f2 - f8 are used for parameter passing. */
684 const int src_regno = GET_SRC_REG (op);
685
686 return (src_regno >= 2 && src_regno <= 8);
687 }
688
689 /* Not an insn that saves a parameter on stack. */
690 return 0;
691}
55d05f3b 692
7a78ae4e 693static CORE_ADDR
077276e8 694skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
c906108c
SS		 695{
696 CORE_ADDR orig_pc = pc;
55d05f3b 697 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 698 CORE_ADDR li_found_pc = 0;
c906108c
SS		 699 char buf[4];
700 unsigned long op;
701 long offset = 0;
6be8bc0c 702 long vr_saved_offset = 0;
482ca3f5
KB		 703 int lr_reg = -1;
704 int cr_reg = -1;
6be8bc0c 705 int vr_reg = -1;
96ff0de4
EZ		 706 int ev_reg = -1;
707 long ev_offset = 0;
6be8bc0c 708 int vrsave_reg = -1;
c906108c
SS		 709 int reg;
710 int framep = 0;
711 int minimal_toc_loaded = 0;
ddb20c56 712 int prev_insn_was_prologue_insn = 1;
55d05f3b 713 int num_skip_non_prologue_insns = 0;
773df3e5 714 int r0_contains_arg = 0;
96ff0de4 715 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
6f99cb26 716 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
96ff0de4 717
55d05f3b
KB		 718 /* Attempt to find the end of the prologue when no limit is specified.
719 Note that refine_prologue_limit() has been written so that it may
720 be used to "refine" the limits of non-zero PC values too, but this
721 is only safe if we 1) trust the line information provided by the
722 compiler and 2) iterate enough to actually find the end of the
723 prologue.
724
725 It may become a good idea at some point (for both performance and
726 accuracy) to unconditionally call refine_prologue_limit(). But,
727 until we can make a clear determination that this is beneficial,
728 we'll play it safe and only use it to obtain a limit when none
729 has been specified. */
730 if (lim_pc == 0)
731 lim_pc = refine_prologue_limit (pc, lim_pc);
c906108c 732
ddb20c56 733 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 734 fdata->saved_gpr = -1;
735 fdata->saved_fpr = -1;
6be8bc0c 736 fdata->saved_vr = -1;
96ff0de4 737 fdata->saved_ev = -1;
c906108c
SS		 738 fdata->alloca_reg = -1;
739 fdata->frameless = 1;
740 fdata->nosavedpc = 1;
741
55d05f3b 742 for (;; pc += 4)
c906108c 743 {
ddb20c56
KB		 744 /* Sometimes it isn't clear if an instruction is a prologue
745 instruction or not. When we encounter one of these ambiguous
746 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
747 Otherwise, we'll assume that it really is a prologue instruction. */
748 if (prev_insn_was_prologue_insn)
749 last_prologue_pc = pc;
55d05f3b
KB		 750
751 /* Stop scanning if we've hit the limit. */
752 if (lim_pc != 0 && pc >= lim_pc)
753 break;
754
ddb20c56
KB		 755 prev_insn_was_prologue_insn = 1;
756
55d05f3b 757 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 758 if (target_read_memory (pc, buf, 4))
759 break;
760 op = extract_signed_integer (buf, 4);
c906108c 761
c5aa993b
JM		 762 if ((op & 0xfc1fffff) == 0x7c0802a6)
763 { /* mflr Rx */
43b1ab88
AC		 764 /* Since shared library / PIC code, which needs to get its
765 address at runtime, can appear to save more than one link
766 register vis:
767
768 *INDENT-OFF*
769 stwu r1,-304(r1)
770 mflr r3
771 bl 0xff570d0 (blrl)
772 stw r30,296(r1)
773 mflr r30
774 stw r31,300(r1)
775 stw r3,308(r1);
776 ...
777 *INDENT-ON*
778
779 remember just the first one, but skip over additional
780 ones. */
781 if (lr_reg < 0)
782 lr_reg = (op & 0x03e00000);
773df3e5
JB		 783 if (lr_reg == 0)
784 r0_contains_arg = 0;
c5aa993b 785 continue;
c5aa993b
JM		 786 }
787 else if ((op & 0xfc1fffff) == 0x7c000026)
788 { /* mfcr Rx */
98f08d3d 789 cr_reg = (op & 0x03e00000);
773df3e5
JB		 790 if (cr_reg == 0)
791 r0_contains_arg = 0;
c5aa993b 792 continue;
c906108c 793
c906108c 794 }
c5aa993b
JM		 795 else if ((op & 0xfc1f0000) == 0xd8010000)
796 { /* stfd Rx,NUM(r1) */
797 reg = GET_SRC_REG (op);
798 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
799 {
800 fdata->saved_fpr = reg;
801 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
802 }
803 continue;
c906108c 804
c5aa993b
JM		 805 }
806 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 807 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
808 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
809 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 810 {
811
812 reg = GET_SRC_REG (op);
813 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
814 {
815 fdata->saved_gpr = reg;
7a78ae4e 816 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 817 op &= ~3UL;
c5aa993b
JM		 818 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
819 }
820 continue;
c906108c 821
ddb20c56
KB		 822 }
823 else if ((op & 0xffff0000) == 0x60000000)
824 {
96ff0de4 825 /* nop */
ddb20c56
KB		 826 /* Allow nops in the prologue, but do not consider them to
827 be part of the prologue unless followed by other prologue
828 instructions. */
829 prev_insn_was_prologue_insn = 0;
830 continue;
831
c906108c 832 }
c5aa993b
JM		 833 else if ((op & 0xffff0000) == 0x3c000000)
834 { /* addis 0,0,NUM, used
835 for >= 32k frames */
836 fdata->offset = (op & 0x0000ffff) << 16;
837 fdata->frameless = 0;
773df3e5 838 r0_contains_arg = 0;
c5aa993b
JM		 839 continue;
840
841 }
842 else if ((op & 0xffff0000) == 0x60000000)
843 { /* ori 0,0,NUM, 2nd ha
844 lf of >= 32k frames */
845 fdata->offset |= (op & 0x0000ffff);
846 fdata->frameless = 0;
773df3e5 847 r0_contains_arg = 0;
c5aa993b
JM		 848 continue;
849
850 }
98f08d3d
KB		 851 else if (lr_reg != -1 &&
852 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
853 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
854 /* stw Rx, NUM(r1) */
855 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
856 /* stwu Rx, NUM(r1) */
857 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
858 { /* where Rx == lr */
859 fdata->lr_offset = offset;
c5aa993b
JM		 860 fdata->nosavedpc = 0;
861 lr_reg = 0;
98f08d3d
KB		 862 if ((op & 0xfc000003) == 0xf8000000 || /* std */
863 (op & 0xfc000000) == 0x90000000) /* stw */
864 {
865 /* Does not update r1, so add displacement to lr_offset. */
866 fdata->lr_offset += SIGNED_SHORT (op);
867 }
c5aa993b
JM		 868 continue;
869
870 }
98f08d3d
KB		 871 else if (cr_reg != -1 &&
872 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
873 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
874 /* stw Rx, NUM(r1) */
875 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
876 /* stwu Rx, NUM(r1) */
877 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
878 { /* where Rx == cr */
879 fdata->cr_offset = offset;
c5aa993b 880 cr_reg = 0;
98f08d3d
KB		 881 if ((op & 0xfc000003) == 0xf8000000 ||
882 (op & 0xfc000000) == 0x90000000)
883 {
884 /* Does not update r1, so add displacement to cr_offset. */
885 fdata->cr_offset += SIGNED_SHORT (op);
886 }
c5aa993b
JM		 887 continue;
888
889 }
890 else if (op == 0x48000005)
891 { /* bl .+4 used in
892 -mrelocatable */
893 continue;
894
895 }
896 else if (op == 0x48000004)
897 { /* b .+4 (xlc) */
898 break;
899
c5aa993b 900 }
6be8bc0c
EZ		 901 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
902 in V.4 -mminimal-toc */
c5aa993b
JM		 903 (op & 0xffff0000) == 0x3bde0000)
904 { /* addi 30,30,foo@l */
905 continue;
c906108c 906
c5aa993b
JM		 907 }
908 else if ((op & 0xfc000001) == 0x48000001)
909 { /* bl foo,
910 to save fprs??? */
c906108c 911
c5aa993b 912 fdata->frameless = 0;
6be8bc0c
EZ		 913 /* Don't skip over the subroutine call if it is not within
914 the first three instructions of the prologue. */
c5aa993b
JM		 915 if ((pc - orig_pc) > 8)
916 break;
917
918 op = read_memory_integer (pc + 4, 4);
919
6be8bc0c
EZ		 920 /* At this point, make sure this is not a trampoline
921 function (a function that simply calls another functions,
922 and nothing else). If the next is not a nop, this branch
923 was part of the function prologue. */
c5aa993b
JM		 924
925 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
926 break; /* don't skip over
927 this branch */
928 continue;
929
c5aa993b 930 }
98f08d3d
KB		 931 /* update stack pointer */
932 else if ((op & 0xfc1f0000) == 0x94010000)
933 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 934 fdata->frameless = 0;
935 fdata->offset = SIGNED_SHORT (op);
936 offset = fdata->offset;
937 continue;
c5aa993b 938 }
98f08d3d
KB		 939 else if ((op & 0xfc1f016a) == 0x7c01016e)
940 { /* stwux rX,r1,rY */
941 /* no way to figure out what r1 is going to be */
942 fdata->frameless = 0;
943 offset = fdata->offset;
944 continue;
945 }
946 else if ((op & 0xfc1f0003) == 0xf8010001)
947 { /* stdu rX,NUM(r1) */
948 fdata->frameless = 0;
949 fdata->offset = SIGNED_SHORT (op & ~3UL);
950 offset = fdata->offset;
951 continue;
952 }
953 else if ((op & 0xfc1f016a) == 0x7c01016a)
954 { /* stdux rX,r1,rY */
955 /* no way to figure out what r1 is going to be */
c5aa993b
JM		 956 fdata->frameless = 0;
957 offset = fdata->offset;
958 continue;
c5aa993b 959 }
98f08d3d
KB		 960 /* Load up minimal toc pointer */
961 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
962 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
c5aa993b 963 && !minimal_toc_loaded)
98f08d3d 964 {
c5aa993b
JM		 965 minimal_toc_loaded = 1;
966 continue;
967
f6077098
KB		 968 /* move parameters from argument registers to local variable
969 registers */
970 }
971 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
972 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
973 (((op >> 21) & 31) <= 10) &&
96ff0de4 974 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 975 {
976 continue;
977
c5aa993b
JM		 978 /* store parameters in stack */
979 }
e802b915 980 /* Move parameters from argument registers to temporary register. */
773df3e5 981 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 982 {
c5aa993b
JM		 983 continue;
984
985 /* Set up frame pointer */
986 }
987 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
988 || op == 0x7c3f0b78)
989 { /* mr r31, r1 */
990 fdata->frameless = 0;
991 framep = 1;
6f99cb26 992 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 993 continue;
994
995 /* Another way to set up the frame pointer. */
996 }
997 else if ((op & 0xfc1fffff) == 0x38010000)
998 { /* addi rX, r1, 0x0 */
999 fdata->frameless = 0;
1000 framep = 1;
6f99cb26
AC		 1001 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1002 + ((op & ~0x38010000) >> 21));
c5aa993b 1003 continue;
c5aa993b 1004 }
6be8bc0c
EZ		 1005 /* AltiVec related instructions. */
1006 /* Store the vrsave register (spr 256) in another register for
1007 later manipulation, or load a register into the vrsave
1008 register. 2 instructions are used: mfvrsave and
1009 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1010 and mtspr SPR256, Rn. */
1011 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1012 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1013 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1014 {
1015 vrsave_reg = GET_SRC_REG (op);
1016 continue;
1017 }
1018 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1019 {
1020 continue;
1021 }
1022 /* Store the register where vrsave was saved to onto the stack:
1023 rS is the register where vrsave was stored in a previous
1024 instruction. */
1025 /* 100100 sssss 00001 dddddddd dddddddd */
1026 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1027 {
1028 if (vrsave_reg == GET_SRC_REG (op))
1029 {
1030 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1031 vrsave_reg = -1;
1032 }
1033 continue;
1034 }
1035 /* Compute the new value of vrsave, by modifying the register
1036 where vrsave was saved to. */
1037 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1038 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1039 {
1040 continue;
1041 }
1042 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1043 in a pair of insns to save the vector registers on the
1044 stack. */
1045 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1046 /* 001110 01110 00000 iiii iiii iiii iiii */
1047 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1048 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1049 {
773df3e5
JB		 1050 if ((op & 0xffff0000) == 0x38000000)
1051 r0_contains_arg = 0;
6be8bc0c
EZ		 1052 li_found_pc = pc;
1053 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1054
1055 /* This insn by itself is not part of the prologue, unless
1056 if part of the pair of insns mentioned above. So do not
1057 record this insn as part of the prologue yet. */
1058 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1059 }
1060 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1061 /* 011111 sssss 11111 00000 00111001110 */
1062 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1063 {
1064 if (pc == (li_found_pc + 4))
1065 {
1066 vr_reg = GET_SRC_REG (op);
1067 /* If this is the first vector reg to be saved, or if
1068 it has a lower number than others previously seen,
1069 reupdate the frame info. */
1070 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1071 {
1072 fdata->saved_vr = vr_reg;
1073 fdata->vr_offset = vr_saved_offset + offset;
1074 }
1075 vr_saved_offset = -1;
1076 vr_reg = -1;
1077 li_found_pc = 0;
1078 }
1079 }
1080 /* End AltiVec related instructions. */
96ff0de4
EZ		 1081
1082 /* Start BookE related instructions. */
1083 /* Store gen register S at (r31+uimm).
1084 Any register less than r13 is volatile, so we don't care. */
1085 /* 000100 sssss 11111 iiiii 01100100001 */
1086 else if (arch_info->mach == bfd_mach_ppc_e500
1087 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1088 {
1089 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1090 {
1091 unsigned int imm;
1092 ev_reg = GET_SRC_REG (op);
1093 imm = (op >> 11) & 0x1f;
1094 ev_offset = imm * 8;
1095 /* If this is the first vector reg to be saved, or if
1096 it has a lower number than others previously seen,
1097 reupdate the frame info. */
1098 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1099 {
1100 fdata->saved_ev = ev_reg;
1101 fdata->ev_offset = ev_offset + offset;
1102 }
1103 }
1104 continue;
1105 }
1106 /* Store gen register rS at (r1+rB). */
1107 /* 000100 sssss 00001 bbbbb 01100100000 */
1108 else if (arch_info->mach == bfd_mach_ppc_e500
1109 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1110 {
1111 if (pc == (li_found_pc + 4))
1112 {
1113 ev_reg = GET_SRC_REG (op);
1114 /* If this is the first vector reg to be saved, or if
1115 it has a lower number than others previously seen,
1116 reupdate the frame info. */
1117 /* We know the contents of rB from the previous instruction. */
1118 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1119 {
1120 fdata->saved_ev = ev_reg;
1121 fdata->ev_offset = vr_saved_offset + offset;
1122 }
1123 vr_saved_offset = -1;
1124 ev_reg = -1;
1125 li_found_pc = 0;
1126 }
1127 continue;
1128 }
1129 /* Store gen register r31 at (rA+uimm). */
1130 /* 000100 11111 aaaaa iiiii 01100100001 */
1131 else if (arch_info->mach == bfd_mach_ppc_e500
1132 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1133 {
1134 /* Wwe know that the source register is 31 already, but
1135 it can't hurt to compute it. */
1136 ev_reg = GET_SRC_REG (op);
1137 ev_offset = ((op >> 11) & 0x1f) * 8;
1138 /* If this is the first vector reg to be saved, or if
1139 it has a lower number than others previously seen,
1140 reupdate the frame info. */
1141 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1142 {
1143 fdata->saved_ev = ev_reg;
1144 fdata->ev_offset = ev_offset + offset;
1145 }
1146
1147 continue;
1148 }
1149 /* Store gen register S at (r31+r0).
1150 Store param on stack when offset from SP bigger than 4 bytes. */
1151 /* 000100 sssss 11111 00000 01100100000 */
1152 else if (arch_info->mach == bfd_mach_ppc_e500
1153 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1154 {
1155 if (pc == (li_found_pc + 4))
1156 {
1157 if ((op & 0x03e00000) >= 0x01a00000)
1158 {
1159 ev_reg = GET_SRC_REG (op);
1160 /* If this is the first vector reg to be saved, or if
1161 it has a lower number than others previously seen,
1162 reupdate the frame info. */
1163 /* We know the contents of r0 from the previous
1164 instruction. */
1165 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1166 {
1167 fdata->saved_ev = ev_reg;
1168 fdata->ev_offset = vr_saved_offset + offset;
1169 }
1170 ev_reg = -1;
1171 }
1172 vr_saved_offset = -1;
1173 li_found_pc = 0;
1174 continue;
1175 }
1176 }
1177 /* End BookE related instructions. */
1178
c5aa993b
JM		 1179 else
1180 {
55d05f3b
KB		 1181 /* Not a recognized prologue instruction.
1182 Handle optimizer code motions into the prologue by continuing
1183 the search if we have no valid frame yet or if the return
1184 address is not yet saved in the frame. */
1185 if (fdata->frameless == 0
1186 && (lr_reg == -1 || fdata->nosavedpc == 0))
1187 break;
1188
1189 if (op == 0x4e800020 /* blr */
1190 || op == 0x4e800420) /* bctr */
1191 /* Do not scan past epilogue in frameless functions or
1192 trampolines. */
1193 break;
1194 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 1195 /* Never skip branches. */
55d05f3b
KB		 1196 break;
1197
1198 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1199 /* Do not scan too many insns, scanning insns is expensive with
1200 remote targets. */
1201 break;
1202
1203 /* Continue scanning. */
1204 prev_insn_was_prologue_insn = 0;
1205 continue;
c5aa993b 1206 }
c906108c
SS		 1207 }
1208
1209#if 0
1210/* I have problems with skipping over __main() that I need to address
1211 * sometime. Previously, I used to use misc_function_vector which
1212 * didn't work as well as I wanted to be. -MGO */
1213
1214 /* If the first thing after skipping a prolog is a branch to a function,
1215 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 1216 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 1217 work before calling a function right after a prologue, thus we can
64366f1c 1218 single out such gcc2 behaviour. */
c906108c 1219
c906108c 1220
c5aa993b
JM		 1221 if ((op & 0xfc000001) == 0x48000001)
1222 { /* bl foo, an initializer function? */
1223 op = read_memory_integer (pc + 4, 4);
1224
1225 if (op == 0x4def7b82)
1226 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 1227
64366f1c
EZ		 1228 /* Check and see if we are in main. If so, skip over this
1229 initializer function as well. */
c906108c 1230
c5aa993b 1231 tmp = find_pc_misc_function (pc);
6314a349
AC		 1232 if (tmp >= 0
1233 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 1234 return pc + 8;
1235 }
c906108c 1236 }
c906108c 1237#endif /* 0 */
c5aa993b
JM		 1238
1239 fdata->offset = -fdata->offset;
ddb20c56 1240 return last_prologue_pc;
c906108c
SS		 1241}
1242
1243
1244/*************************************************************************
f6077098 1245 Support for creating pushing a dummy frame into the stack, and popping
c906108c
SS		 1246 frames, etc.
1247*************************************************************************/
1248
c906108c 1249
11269d7e
AC		 1250/* All the ABI's require 16 byte alignment. */
1251static CORE_ADDR
1252rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1253{
1254 return (addr & -16);
1255}
1256
7a78ae4e 1257/* Pass the arguments in either registers, or in the stack. In RS/6000,
c906108c
SS		 1258 the first eight words of the argument list (that might be less than
1259 eight parameters if some parameters occupy more than one word) are
7a78ae4e 1260 passed in r3..r10 registers. float and double parameters are
64366f1c
EZ		 1261 passed in fpr's, in addition to that. Rest of the parameters if any
1262 are passed in user stack. There might be cases in which half of the
c906108c
SS		 1263 parameter is copied into registers, the other half is pushed into
1264 stack.
1265
7a78ae4e
ND		 1266 Stack must be aligned on 64-bit boundaries when synthesizing
1267 function calls.
1268
c906108c
SS		 1269 If the function is returning a structure, then the return address is passed
1270 in r3, then the first 7 words of the parameters can be passed in registers,
64366f1c 1271 starting from r4. */
c906108c 1272
7a78ae4e 1273static CORE_ADDR
77b2b6d4
AC		 1274rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1275 struct regcache *regcache, CORE_ADDR bp_addr,
1276 int nargs, struct value **args, CORE_ADDR sp,
1277 int struct_return, CORE_ADDR struct_addr)
c906108c 1278{
7a41266b 1279 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c
SS		 1280 int ii;
1281 int len = 0;
c5aa993b
JM		 1282 int argno; /* current argument number */
1283 int argbytes; /* current argument byte */
1284 char tmp_buffer[50];
1285 int f_argno = 0; /* current floating point argno */
21283beb 1286 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
c906108c 1287
ea7c478f 1288 struct value *arg = 0;
c906108c
SS		 1289 struct type *type;
1290
1291 CORE_ADDR saved_sp;
1292
383f0f5b
JB		 1293 /* The calling convention this function implements assumes the
1294 processor has floating-point registers. We shouldn't be using it
1295 on PPC variants that lack them. */
1296 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1297
64366f1c 1298 /* The first eight words of ther arguments are passed in registers.
7a41266b
AC		 1299 Copy them appropriately. */
1300 ii = 0;
1301
1302 /* If the function is returning a `struct', then the first word
1303 (which will be passed in r3) is used for struct return address.
1304 In that case we should advance one word and start from r4
1305 register to copy parameters. */
1306 if (struct_return)
1307 {
1308 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1309 struct_addr);
1310 ii++;
1311 }
c906108c
SS		 1312
1313/*
c5aa993b
JM		 1314 effectively indirect call... gcc does...
1315
1316 return_val example( float, int);
1317
1318 eabi:
1319 float in fp0, int in r3
1320 offset of stack on overflow 8/16
1321 for varargs, must go by type.
1322 power open:
1323 float in r3&r4, int in r5
1324 offset of stack on overflow different
1325 both:
1326 return in r3 or f0. If no float, must study how gcc emulates floats;
1327 pay attention to arg promotion.
1328 User may have to cast\args to handle promotion correctly
1329 since gdb won't know if prototype supplied or not.
1330 */
c906108c 1331
c5aa993b
JM		 1332 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1333 {
12c266ea 1334 int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3);
c5aa993b
JM		 1335
1336 arg = args[argno];
1337 type = check_typedef (VALUE_TYPE (arg));
1338 len = TYPE_LENGTH (type);
1339
1340 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1341 {
1342
64366f1c 1343 /* Floating point arguments are passed in fpr's, as well as gpr's.
c5aa993b 1344 There are 13 fpr's reserved for passing parameters. At this point
64366f1c 1345 there is no way we would run out of them. */
c5aa993b
JM		 1346
1347 if (len > 8)
c2b6b4aa
JB		 1348 printf_unfiltered ("Fatal Error: a floating point parameter "
1349 "#%d with a size > 8 is found!\n", argno);
c5aa993b 1350
366f009f
JB		 1351 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE
1352 (tdep->ppc_fp0_regnum + 1 + f_argno)],
c5aa993b
JM		 1353 VALUE_CONTENTS (arg),
1354 len);
1355 ++f_argno;
1356 }
1357
f6077098 1358 if (len > reg_size)
c5aa993b
JM		 1359 {
1360
64366f1c 1361 /* Argument takes more than one register. */
c5aa993b
JM		 1362 while (argbytes < len)
1363 {
62700349 1364 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0,
524d7c18 1365 reg_size);
62700349 1366 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)],
c5aa993b 1367 ((char *) VALUE_CONTENTS (arg)) + argbytes,
f6077098
KB		 1368 (len - argbytes) > reg_size
1369 ? reg_size : len - argbytes);
1370 ++ii, argbytes += reg_size;
c5aa993b
JM		 1371
1372 if (ii >= 8)
1373 goto ran_out_of_registers_for_arguments;
1374 }
1375 argbytes = 0;
1376 --ii;
1377 }
1378 else
64366f1c
EZ		 1379 {
1380 /* Argument can fit in one register. No problem. */
d7449b42 1381 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
62700349
AC		 1382 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size);
1383 memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj,
f6077098 1384 VALUE_CONTENTS (arg), len);
c5aa993b
JM		 1385 }
1386 ++argno;
c906108c 1387 }
c906108c
SS		 1388
1389ran_out_of_registers_for_arguments:
1390
7a78ae4e 1391 saved_sp = read_sp ();
cc9836a8 1392
64366f1c 1393 /* Location for 8 parameters are always reserved. */
7a78ae4e 1394 sp -= wordsize * 8;
f6077098 1395
64366f1c 1396 /* Another six words for back chain, TOC register, link register, etc. */
7a78ae4e 1397 sp -= wordsize * 6;
f6077098 1398
64366f1c 1399 /* Stack pointer must be quadword aligned. */
7a78ae4e 1400 sp &= -16;
c906108c 1401
64366f1c
EZ		 1402 /* If there are more arguments, allocate space for them in
1403 the stack, then push them starting from the ninth one. */
c906108c 1404
c5aa993b
JM		 1405 if ((argno < nargs) || argbytes)
1406 {
1407 int space = 0, jj;
c906108c 1408
c5aa993b
JM		 1409 if (argbytes)
1410 {
1411 space += ((len - argbytes + 3) & -4);
1412 jj = argno + 1;
1413 }
1414 else
1415 jj = argno;
c906108c 1416
c5aa993b
JM		 1417 for (; jj < nargs; ++jj)
1418 {
ea7c478f 1419 struct value *val = args[jj];
c5aa993b
JM		 1420 space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
1421 }
c906108c 1422
64366f1c 1423 /* Add location required for the rest of the parameters. */
f6077098 1424 space = (space + 15) & -16;
c5aa993b 1425 sp -= space;
c906108c 1426
7aea86e6
AC		 1427 /* This is another instance we need to be concerned about
1428 securing our stack space. If we write anything underneath %sp
1429 (r1), we might conflict with the kernel who thinks he is free
1430 to use this area. So, update %sp first before doing anything
1431 else. */
1432
1433 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1434
64366f1c
EZ		 1435 /* If the last argument copied into the registers didn't fit there
1436 completely, push the rest of it into stack. */
c906108c 1437
c5aa993b
JM		 1438 if (argbytes)
1439 {
1440 write_memory (sp + 24 + (ii * 4),
1441 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1442 len - argbytes);
1443 ++argno;
1444 ii += ((len - argbytes + 3) & -4) / 4;
1445 }
c906108c 1446
64366f1c 1447 /* Push the rest of the arguments into stack. */
c5aa993b
JM		 1448 for (; argno < nargs; ++argno)
1449 {
c906108c 1450
c5aa993b
JM		 1451 arg = args[argno];
1452 type = check_typedef (VALUE_TYPE (arg));
1453 len = TYPE_LENGTH (type);
c906108c
SS		 1454
1455
64366f1c
EZ		 1456 /* Float types should be passed in fpr's, as well as in the
1457 stack. */
c5aa993b
JM		 1458 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1459 {
c906108c 1460
c5aa993b 1461 if (len > 8)
c2b6b4aa
JB		 1462 printf_unfiltered ("Fatal Error: a floating point parameter"
1463 " #%d with a size > 8 is found!\n", argno);
c906108c 1464
366f009f
JB		 1465 memcpy (&(deprecated_registers
1466 [DEPRECATED_REGISTER_BYTE
1467 (tdep->ppc_fp0_regnum + 1 + f_argno)]),
c5aa993b
JM		 1468 VALUE_CONTENTS (arg),
1469 len);
1470 ++f_argno;
1471 }
c906108c 1472
c2b6b4aa
JB		 1473 write_memory (sp + 24 + (ii * 4),
1474 (char *) VALUE_CONTENTS (arg),
1475 len);
c5aa993b
JM		 1476 ii += ((len + 3) & -4) / 4;
1477 }
c906108c 1478 }
c906108c 1479
69517000 1480 /* Set the stack pointer. According to the ABI, the SP is meant to
7aea86e6
AC		 1481 be set _before_ the corresponding stack space is used. On AIX,
1482 this even applies when the target has been completely stopped!
1483 Not doing this can lead to conflicts with the kernel which thinks
1484 that it still has control over this not-yet-allocated stack
1485 region. */
33a7c2fc
AC		 1486 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1487
7aea86e6
AC		 1488 /* Set back chain properly. */
1489 store_unsigned_integer (tmp_buffer, 4, saved_sp);
1490 write_memory (sp, tmp_buffer, 4);
1491
e56a0ecc
AC		 1492 /* Point the inferior function call's return address at the dummy's
1493 breakpoint. */
1494 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1495
794a477a
AC		 1496 /* Set the TOC register, get the value from the objfile reader
1497 which, in turn, gets it from the VMAP table. */
1498 if (rs6000_find_toc_address_hook != NULL)
1499 {
1500 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1501 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1502 }
1503
c906108c
SS		 1504 target_store_registers (-1);
1505 return sp;
1506}
c906108c 1507
b9ff3018
AC		 1508/* PowerOpen always puts structures in memory. Vectors, which were
1509 added later, do get returned in a register though. */
1510
1511static int
1512rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1513{
1514 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1515 && TYPE_VECTOR (value_type))
1516 return 0;
1517 return 1;
1518}
1519
7a78ae4e
ND		 1520static void
1521rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
c906108c
SS		 1522{
1523 int offset = 0;
ace1378a 1524 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c 1525
383f0f5b
JB		 1526 /* The calling convention this function implements assumes the
1527 processor has floating-point registers. We shouldn't be using it
1528 on PPC variants that lack them. */
1529 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1530
c5aa993b
JM		 1531 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1532 {
c906108c 1533
c5aa993b
JM		 1534 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1535 We need to truncate the return value into float size (4 byte) if
64366f1c 1536 necessary. */
c906108c 1537
65951cd9 1538 convert_typed_floating (&regbuf[DEPRECATED_REGISTER_BYTE
366f009f 1539 (tdep->ppc_fp0_regnum + 1)],
65951cd9
JG		 1540 builtin_type_double,
1541 valbuf,
1542 valtype);
c5aa993b 1543 }
ace1378a
EZ		 1544 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1545 && TYPE_LENGTH (valtype) == 16
1546 && TYPE_VECTOR (valtype))
1547 {
62700349 1548 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
ace1378a
EZ		 1549 TYPE_LENGTH (valtype));
1550 }
c5aa993b
JM		 1551 else
1552 {
1553 /* return value is copied starting from r3. */
d7449b42 1554 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
12c266ea
AC		 1555 && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3))
1556 offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype);
c5aa993b
JM		 1557
1558 memcpy (valbuf,
62700349 1559 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
c906108c 1560 TYPE_LENGTH (valtype));
c906108c 1561 }
c906108c
SS		 1562}
1563
977adac5
ND		 1564/* Return whether handle_inferior_event() should proceed through code
1565 starting at PC in function NAME when stepping.
1566
1567 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1568 handle memory references that are too distant to fit in instructions
1569 generated by the compiler. For example, if 'foo' in the following
1570 instruction:
1571
1572 lwz r9,foo(r2)
1573
1574 is greater than 32767, the linker might replace the lwz with a branch to
1575 somewhere in @FIX1 that does the load in 2 instructions and then branches
1576 back to where execution should continue.
1577
1578 GDB should silently step over @FIX code, just like AIX dbx does.
1579 Unfortunately, the linker uses the "b" instruction for the branches,
1580 meaning that the link register doesn't get set. Therefore, GDB's usual
1581 step_over_function() mechanism won't work.
1582
1583 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1584 in handle_inferior_event() to skip past @FIX code. */
1585
1586int
1587rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1588{
1589 return name && !strncmp (name, "@FIX", 4);
1590}
1591
1592/* Skip code that the user doesn't want to see when stepping:
1593
1594 1. Indirect function calls use a piece of trampoline code to do context
1595 switching, i.e. to set the new TOC table. Skip such code if we are on
1596 its first instruction (as when we have single-stepped to here).
1597
1598 2. Skip shared library trampoline code (which is different from
c906108c 1599 indirect function call trampolines).
977adac5
ND		 1600
1601 3. Skip bigtoc fixup code.
1602
c906108c 1603 Result is desired PC to step until, or NULL if we are not in
977adac5 1604 code that should be skipped. */
c906108c
SS		 1605
1606CORE_ADDR
7a78ae4e 1607rs6000_skip_trampoline_code (CORE_ADDR pc)
c906108c 1608{
52f0bd74 1609 unsigned int ii, op;
977adac5 1610 int rel;
c906108c 1611 CORE_ADDR solib_target_pc;
977adac5 1612 struct minimal_symbol *msymbol;
c906108c 1613
c5aa993b
JM		 1614 static unsigned trampoline_code[] =
1615 {
1616 0x800b0000, /* l r0,0x0(r11) */
1617 0x90410014, /* st r2,0x14(r1) */
1618 0x7c0903a6, /* mtctr r0 */
1619 0x804b0004, /* l r2,0x4(r11) */
1620 0x816b0008, /* l r11,0x8(r11) */
1621 0x4e800420, /* bctr */
1622 0x4e800020, /* br */
1623 0
c906108c
SS		 1624 };
1625
977adac5
ND		 1626 /* Check for bigtoc fixup code. */
1627 msymbol = lookup_minimal_symbol_by_pc (pc);
22abf04a 1628 if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol)))
977adac5
ND		 1629 {
1630 /* Double-check that the third instruction from PC is relative "b". */
1631 op = read_memory_integer (pc + 8, 4);
1632 if ((op & 0xfc000003) == 0x48000000)
1633 {
1634 /* Extract bits 6-29 as a signed 24-bit relative word address and
1635 add it to the containing PC. */
1636 rel = ((int)(op << 6) >> 6);
1637 return pc + 8 + rel;
1638 }
1639 }
1640
c906108c
SS		 1641 /* If pc is in a shared library trampoline, return its target. */
1642 solib_target_pc = find_solib_trampoline_target (pc);
1643 if (solib_target_pc)
1644 return solib_target_pc;
1645
c5aa993b
JM		 1646 for (ii = 0; trampoline_code[ii]; ++ii)
1647 {
1648 op = read_memory_integer (pc + (ii * 4), 4);
1649 if (op != trampoline_code[ii])
1650 return 0;
1651 }
1652 ii = read_register (11); /* r11 holds destination addr */
21283beb 1653 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
c906108c
SS		 1654 return pc;
1655}
1656
7a78ae4e 1657/* Return the size of register REG when words are WORDSIZE bytes long. If REG
64366f1c 1658 isn't available with that word size, return 0. */
7a78ae4e
ND		 1659
1660static int
1661regsize (const struct reg *reg, int wordsize)
1662{
1663 return wordsize == 8 ? reg->sz64 : reg->sz32;
1664}
1665
1666/* Return the name of register number N, or null if no such register exists
64366f1c 1667 in the current architecture. */
7a78ae4e 1668
fa88f677 1669static const char *
7a78ae4e
ND		 1670rs6000_register_name (int n)
1671{
21283beb 1672 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
7a78ae4e
ND		 1673 const struct reg *reg = tdep->regs + n;
1674
1675 if (!regsize (reg, tdep->wordsize))
1676 return NULL;
1677 return reg->name;
1678}
1679
7a78ae4e
ND		 1680/* Return the GDB type object for the "standard" data type
1681 of data in register N. */
1682
1683static struct type *
691d145a 1684rs6000_register_type (struct gdbarch *gdbarch, int n)
7a78ae4e 1685{
691d145a 1686 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e
ND		 1687 const struct reg *reg = tdep->regs + n;
1688
1fcc0bb8
EZ		 1689 if (reg->fpr)
1690 return builtin_type_double;
1691 else
1692 {
1693 int size = regsize (reg, tdep->wordsize);
1694 switch (size)
1695 {
449a5da4
AC		 1696 case 0:
1697 return builtin_type_int0;
1698 case 4:
ed6edd9b 1699 return builtin_type_uint32;
1fcc0bb8 1700 case 8:
c8001721
EZ		 1701 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1702 return builtin_type_vec64;
1703 else
ed6edd9b 1704 return builtin_type_uint64;
1fcc0bb8
EZ		 1705 break;
1706 case 16:
08cf96df 1707 return builtin_type_vec128;
1fcc0bb8
EZ		 1708 break;
1709 default:
449a5da4
AC		 1710 internal_error (__FILE__, __LINE__, "Register %d size %d unknown",
1711 n, size);
1fcc0bb8
EZ		 1712 }
1713 }
7a78ae4e
ND		 1714}
1715
691d145a 1716/* The register format for RS/6000 floating point registers is always
64366f1c 1717 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 1718
1719static int
691d145a 1720rs6000_convert_register_p (int regnum, struct type *type)
7a78ae4e 1721{
691d145a
JB		 1722 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1723
1724 return (reg->fpr
1725 && TYPE_CODE (type) == TYPE_CODE_FLT
1726 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
7a78ae4e
ND		 1727}
1728
7a78ae4e 1729static void
691d145a
JB		 1730rs6000_register_to_value (struct frame_info *frame,
1731 int regnum,
1732 struct type *type,
1733 void *to)
7a78ae4e 1734{
691d145a
JB		 1735 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1736 char from[MAX_REGISTER_SIZE];
1737
1738 gdb_assert (reg->fpr);
1739 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 1740
691d145a
JB		 1741 get_frame_register (frame, regnum, from);
1742 convert_typed_floating (from, builtin_type_double, to, type);
1743}
7a292a7a 1744
7a78ae4e 1745static void
691d145a
JB		 1746rs6000_value_to_register (struct frame_info *frame,
1747 int regnum,
1748 struct type *type,
1749 const void *from)
7a78ae4e 1750{
691d145a
JB		 1751 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1752 char to[MAX_REGISTER_SIZE];
1753
1754 gdb_assert (reg->fpr);
1755 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
1756
1757 convert_typed_floating (from, type, to, builtin_type_double);
1758 put_frame_register (frame, regnum, to);
7a78ae4e 1759}
c906108c 1760
c8001721
EZ		 1761static void
1762e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1763 int reg_nr, void *buffer)
1764{
1765 int base_regnum;
1766 int offset = 0;
d9d9c31f 1767 char temp_buffer[MAX_REGISTER_SIZE];
c8001721
EZ		 1768 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1769
1770 if (reg_nr >= tdep->ppc_gp0_regnum
8bf659e8 1771 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
c8001721
EZ		 1772 {
1773 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1774
1775 /* Build the value in the provided buffer. */
1776 /* Read the raw register of which this one is the lower portion. */
1777 regcache_raw_read (regcache, base_regnum, temp_buffer);
1778 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1779 offset = 4;
1780 memcpy ((char *) buffer, temp_buffer + offset, 4);
1781 }
1782}
1783
1784static void
1785e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1786 int reg_nr, const void *buffer)
1787{
1788 int base_regnum;
1789 int offset = 0;
d9d9c31f 1790 char temp_buffer[MAX_REGISTER_SIZE];
c8001721
EZ		 1791 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1792
1793 if (reg_nr >= tdep->ppc_gp0_regnum
8bf659e8 1794 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
c8001721
EZ		 1795 {
1796 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1797 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1798 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1799 offset = 4;
1800
1801 /* Let's read the value of the base register into a temporary
1802 buffer, so that overwriting the last four bytes with the new
1803 value of the pseudo will leave the upper 4 bytes unchanged. */
1804 regcache_raw_read (regcache, base_regnum, temp_buffer);
1805
1806 /* Write as an 8 byte quantity. */
1807 memcpy (temp_buffer + offset, (char *) buffer, 4);
1808 regcache_raw_write (regcache, base_regnum, temp_buffer);
1809 }
1810}
1811
18ed0c4e 1812/* Convert a DBX STABS register number to a GDB register number. */
c8001721 1813static int
18ed0c4e 1814rs6000_stab_reg_to_regnum (int num)
c8001721 1815{
9f744501 1816 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c8001721 1817
9f744501
JB		 1818 if (0 <= num && num <= 31)
1819 return tdep->ppc_gp0_regnum + num;
1820 else if (32 <= num && num <= 63)
383f0f5b
JB		 1821 /* FIXME: jimb/2004-05-05: What should we do when the debug info
1822 specifies registers the architecture doesn't have? Our
1823 callers don't check the value we return. */
366f009f 1824 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 1825 else if (77 <= num && num <= 108)
1826 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 1827 else if (1200 <= num && num < 1200 + 32)
1828 return tdep->ppc_ev0_regnum + (num - 1200);
1829 else
1830 switch (num)
1831 {
1832 case 64:
1833 return tdep->ppc_mq_regnum;
1834 case 65:
1835 return tdep->ppc_lr_regnum;
1836 case 66:
1837 return tdep->ppc_ctr_regnum;
1838 case 76:
1839 return tdep->ppc_xer_regnum;
1840 case 109:
1841 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 1842 case 110:
1843 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 1844 case 111:
18ed0c4e 1845 return tdep->ppc_acc_regnum;
867e2dc5 1846 case 112:
18ed0c4e 1847 return tdep->ppc_spefscr_regnum;
9f744501
JB		 1848 default:
1849 return num;
1850 }
18ed0c4e 1851}
9f744501 1852
9f744501 1853
18ed0c4e
JB		 1854/* Convert a Dwarf 2 register number to a GDB register number. */
1855static int
1856rs6000_dwarf2_reg_to_regnum (int num)
1857{
1858 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
9f744501 1859
18ed0c4e
JB		 1860 if (0 <= num && num <= 31)
1861 return tdep->ppc_gp0_regnum + num;
1862 else if (32 <= num && num <= 63)
1863 /* FIXME: jimb/2004-05-05: What should we do when the debug info
1864 specifies registers the architecture doesn't have? Our
1865 callers don't check the value we return. */
1866 return tdep->ppc_fp0_regnum + (num - 32);
1867 else if (1124 <= num && num < 1124 + 32)
1868 return tdep->ppc_vr0_regnum + (num - 1124);
1869 else if (1200 <= num && num < 1200 + 32)
1870 return tdep->ppc_ev0_regnum + (num - 1200);
1871 else
1872 switch (num)
1873 {
1874 case 67:
1875 return tdep->ppc_vrsave_regnum - 1; /* vscr */
1876 case 99:
1877 return tdep->ppc_acc_regnum;
1878 case 100:
1879 return tdep->ppc_mq_regnum;
1880 case 101:
1881 return tdep->ppc_xer_regnum;
1882 case 108:
1883 return tdep->ppc_lr_regnum;
1884 case 109:
1885 return tdep->ppc_ctr_regnum;
1886 case 356:
1887 return tdep->ppc_vrsave_regnum;
1888 case 612:
1889 return tdep->ppc_spefscr_regnum;
1890 default:
1891 return num;
1892 }
2188cbdd
EZ		 1893}
1894
18ed0c4e 1895
7a78ae4e
ND		 1896static void
1897rs6000_store_return_value (struct type *type, char *valbuf)
1898{
ace1378a
EZ		 1899 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1900
383f0f5b
JB		 1901 /* The calling convention this function implements assumes the
1902 processor has floating-point registers. We shouldn't be using it
1903 on PPC variants that lack them. */
1904 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1905
7a78ae4e
ND		 1906 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1907
1908 /* Floating point values are returned starting from FPR1 and up.
1909 Say a double_double_double type could be returned in
64366f1c 1910 FPR1/FPR2/FPR3 triple. */
7a78ae4e 1911
366f009f
JB		 1912 deprecated_write_register_bytes
1913 (DEPRECATED_REGISTER_BYTE (tdep->ppc_fp0_regnum + 1),
1914 valbuf,
1915 TYPE_LENGTH (type));
ace1378a
EZ		 1916 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1917 {
1918 if (TYPE_LENGTH (type) == 16
1919 && TYPE_VECTOR (type))
62700349 1920 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
73937e03 1921 valbuf, TYPE_LENGTH (type));
ace1378a 1922 }
7a78ae4e 1923 else
64366f1c 1924 /* Everything else is returned in GPR3 and up. */
62700349 1925 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3),
73937e03 1926 valbuf, TYPE_LENGTH (type));
7a78ae4e
ND		 1927}
1928
1929/* Extract from an array REGBUF containing the (raw) register state
1930 the address in which a function should return its structure value,
1931 as a CORE_ADDR (or an expression that can be used as one). */
1932
1933static CORE_ADDR
11269d7e
AC		 1934rs6000_extract_struct_value_address (struct regcache *regcache)
1935{
1936 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
1937 function call GDB knows the address of the struct return value
1938 and hence, should not need to call this function. Unfortunately,
e8a8712a
AC		 1939 the current call_function_by_hand() code only saves the most
1940 recent struct address leading to occasional calls. The code
1941 should instead maintain a stack of such addresses (in the dummy
1942 frame object). */
11269d7e
AC		 1943 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
1944 really got no idea where the return value is being stored. While
1945 r3, on function entry, contained the address it will have since
1946 been reused (scratch) and hence wouldn't be valid */
1947 return 0;
7a78ae4e
ND		 1948}
1949
64366f1c 1950/* Hook called when a new child process is started. */
7a78ae4e
ND		 1951
1952void
1953rs6000_create_inferior (int pid)
1954{
1955 if (rs6000_set_host_arch_hook)
1956 rs6000_set_host_arch_hook (pid);
c906108c
SS		 1957}
1958\f
e2d0e7eb 1959/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
7a78ae4e
ND		 1960
1961 Usually a function pointer's representation is simply the address
1962 of the function. On the RS/6000 however, a function pointer is
1963 represented by a pointer to a TOC entry. This TOC entry contains
1964 three words, the first word is the address of the function, the
1965 second word is the TOC pointer (r2), and the third word is the
1966 static chain value. Throughout GDB it is currently assumed that a
1967 function pointer contains the address of the function, which is not
1968 easy to fix. In addition, the conversion of a function address to
1969 a function pointer would require allocation of a TOC entry in the
1970 inferior's memory space, with all its drawbacks. To be able to
1971 call C++ virtual methods in the inferior (which are called via
f517ea4e 1972 function pointers), find_function_addr uses this function to get the
7a78ae4e
ND		 1973 function address from a function pointer. */
1974
f517ea4e
PS		 1975/* Return real function address if ADDR (a function pointer) is in the data
1976 space and is therefore a special function pointer. */
c906108c 1977
b9362cc7 1978static CORE_ADDR
e2d0e7eb
AC		 1979rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
1980 CORE_ADDR addr,
1981 struct target_ops *targ)
c906108c
SS		 1982{
1983 struct obj_section *s;
1984
1985 s = find_pc_section (addr);
1986 if (s && s->the_bfd_section->flags & SEC_CODE)
7a78ae4e 1987 return addr;
c906108c 1988
7a78ae4e 1989 /* ADDR is in the data space, so it's a special function pointer. */
21283beb 1990 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
c906108c 1991}
c906108c 1992\f
c5aa993b 1993
7a78ae4e 1994/* Handling the various POWER/PowerPC variants. */
c906108c
SS		 1995
1996
7a78ae4e
ND		 1997/* The arrays here called registers_MUMBLE hold information about available
1998 registers.
c906108c
SS		 1999
2000 For each family of PPC variants, I've tried to isolate out the
2001 common registers and put them up front, so that as long as you get
2002 the general family right, GDB will correctly identify the registers
2003 common to that family. The common register sets are:
2004
2005 For the 60x family: hid0 hid1 iabr dabr pir
2006
2007 For the 505 and 860 family: eie eid nri
2008
2009 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
c5aa993b
JM		 2010 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2011 pbu1 pbl2 pbu2
c906108c
SS		 2012
2013 Most of these register groups aren't anything formal. I arrived at
2014 them by looking at the registers that occurred in more than one
6f5987a6
KB		 2015 processor.
2016
2017 Note: kevinb/2002-04-30: Support for the fpscr register was added
2018 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2019 for Power. For PowerPC, slot 70 was unused and was already in the
2020 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2021 slot 70 was being used for "mq", so the next available slot (71)
2022 was chosen. It would have been nice to be able to make the
2023 register numbers the same across processor cores, but this wasn't
2024 possible without either 1) renumbering some registers for some
2025 processors or 2) assigning fpscr to a really high slot that's
2026 larger than any current register number. Doing (1) is bad because
2027 existing stubs would break. Doing (2) is undesirable because it
2028 would introduce a really large gap between fpscr and the rest of
2029 the registers for most processors. */
7a78ae4e 2030
64366f1c 2031/* Convenience macros for populating register arrays. */
7a78ae4e 2032
64366f1c 2033/* Within another macro, convert S to a string. */
7a78ae4e
ND		 2034
2035#define STR(s) #s
2036
2037/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
64366f1c 2038 and 64 bits on 64-bit systems. */
489461e2 2039#define R(name) { STR(name), 4, 8, 0, 0 }
7a78ae4e
ND		 2040
2041/* Return a struct reg defining register NAME that's 32 bits on all
64366f1c 2042 systems. */
489461e2 2043#define R4(name) { STR(name), 4, 4, 0, 0 }
7a78ae4e
ND		 2044
2045/* Return a struct reg defining register NAME that's 64 bits on all
64366f1c 2046 systems. */
489461e2 2047#define R8(name) { STR(name), 8, 8, 0, 0 }
7a78ae4e 2048
1fcc0bb8 2049/* Return a struct reg defining register NAME that's 128 bits on all
64366f1c 2050 systems. */
489461e2 2051#define R16(name) { STR(name), 16, 16, 0, 0 }
1fcc0bb8 2052
64366f1c 2053/* Return a struct reg defining floating-point register NAME. */
489461e2
EZ		 2054#define F(name) { STR(name), 8, 8, 1, 0 }
2055
64366f1c 2056/* Return a struct reg defining a pseudo register NAME. */
489461e2 2057#define P(name) { STR(name), 4, 8, 0, 1}
7a78ae4e
ND		 2058
2059/* Return a struct reg defining register NAME that's 32 bits on 32-bit
64366f1c 2060 systems and that doesn't exist on 64-bit systems. */
489461e2 2061#define R32(name) { STR(name), 4, 0, 0, 0 }
7a78ae4e
ND		 2062
2063/* Return a struct reg defining register NAME that's 64 bits on 64-bit
64366f1c 2064 systems and that doesn't exist on 32-bit systems. */
489461e2 2065#define R64(name) { STR(name), 0, 8, 0, 0 }
7a78ae4e 2066
64366f1c 2067/* Return a struct reg placeholder for a register that doesn't exist. */
489461e2 2068#define R0 { 0, 0, 0, 0, 0 }
7a78ae4e
ND		 2069
2070/* UISA registers common across all architectures, including POWER. */
2071
2072#define COMMON_UISA_REGS \
2073 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2074 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2075 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2076 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2077 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2078 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2079 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2080 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2081 /* 64 */ R(pc), R(ps)
2082
ebeac11a
EZ		 2083#define COMMON_UISA_NOFP_REGS \
2084 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2085 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2086 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2087 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2088 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2089 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2090 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2091 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2092 /* 64 */ R(pc), R(ps)
2093
7a78ae4e
ND		 2094/* UISA-level SPRs for PowerPC. */
2095#define PPC_UISA_SPRS \
e3f36dbd 2096 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
7a78ae4e 2097
c8001721
EZ		 2098/* UISA-level SPRs for PowerPC without floating point support. */
2099#define PPC_UISA_NOFP_SPRS \
2100 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
2101
7a78ae4e
ND		 2102/* Segment registers, for PowerPC. */
2103#define PPC_SEGMENT_REGS \
2104 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2105 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2106 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2107 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2108
2109/* OEA SPRs for PowerPC. */
2110#define PPC_OEA_SPRS \
2111 /* 87 */ R4(pvr), \
2112 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
2113 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
2114 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
2115 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
2116 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
2117 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
2118 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
2119 /* 116 */ R4(dec), R(dabr), R4(ear)
2120
64366f1c 2121/* AltiVec registers. */
1fcc0bb8
EZ		 2122#define PPC_ALTIVEC_REGS \
2123 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2124 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2125 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2126 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2127 /*151*/R4(vscr), R4(vrsave)
2128
c8001721
EZ		 2129/* Vectors of hi-lo general purpose registers. */
2130#define PPC_EV_REGS \
2131 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
2132 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
2133 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
2134 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
2135
2136/* Lower half of the EV registers. */
2137#define PPC_GPRS_PSEUDO_REGS \
2138 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
2139 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
2140 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
338ef23d 2141 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31)
c8001721 2142
7a78ae4e 2143/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
64366f1c 2144 user-level SPR's. */
7a78ae4e 2145static const struct reg registers_power[] =
c906108c 2146{
7a78ae4e 2147 COMMON_UISA_REGS,
e3f36dbd
KB		 2148 /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
2149 /* 71 */ R4(fpscr)
c906108c
SS		 2150};
2151
7a78ae4e 2152/* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
64366f1c 2153 view of the PowerPC. */
7a78ae4e 2154static const struct reg registers_powerpc[] =
c906108c 2155{
7a78ae4e 2156 COMMON_UISA_REGS,
1fcc0bb8
EZ		 2157 PPC_UISA_SPRS,
2158 PPC_ALTIVEC_REGS
c906108c
SS		 2159};
2160
ebeac11a
EZ		 2161/* PowerPC UISA - a PPC processor as viewed by user-level
2162 code, but without floating point registers. */
2163static const struct reg registers_powerpc_nofp[] =
2164{
2165 COMMON_UISA_NOFP_REGS,
2166 PPC_UISA_SPRS
2167};
2168
64366f1c 2169/* IBM PowerPC 403. */
7a78ae4e 2170static const struct reg registers_403[] =
c5aa993b 2171{
7a78ae4e
ND		 2172 COMMON_UISA_REGS,
2173 PPC_UISA_SPRS,
2174 PPC_SEGMENT_REGS,
2175 PPC_OEA_SPRS,
2176 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2177 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2178 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2179 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2180 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2181 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2)
c906108c
SS		 2182};
2183
64366f1c 2184/* IBM PowerPC 403GC. */
7a78ae4e 2185static const struct reg registers_403GC[] =
c5aa993b 2186{
7a78ae4e
ND		 2187 COMMON_UISA_REGS,
2188 PPC_UISA_SPRS,
2189 PPC_SEGMENT_REGS,
2190 PPC_OEA_SPRS,
2191 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2192 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2193 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2194 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2195 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2196 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2),
2197 /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr),
2198 /* 147 */ R(tbhu), R(tblu)
c906108c
SS		 2199};
2200
64366f1c 2201/* Motorola PowerPC 505. */
7a78ae4e 2202static const struct reg registers_505[] =
c5aa993b 2203{
7a78ae4e
ND		 2204 COMMON_UISA_REGS,
2205 PPC_UISA_SPRS,
2206 PPC_SEGMENT_REGS,
2207 PPC_OEA_SPRS,
2208 /* 119 */ R(eie), R(eid), R(nri)
c906108c
SS		 2209};
2210
64366f1c 2211/* Motorola PowerPC 860 or 850. */
7a78ae4e 2212static const struct reg registers_860[] =
c5aa993b 2213{
7a78ae4e
ND		 2214 COMMON_UISA_REGS,
2215 PPC_UISA_SPRS,
2216 PPC_SEGMENT_REGS,
2217 PPC_OEA_SPRS,
2218 /* 119 */ R(eie), R(eid), R(nri), R(cmpa),
2219 /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr),
2220 /* 127 */ R(der), R(counta), R(countb), R(cmpe),
2221 /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1),
2222 /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst),
2223 /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr),
2224 /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr),
2225 /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc),
2226 /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap),
2227 /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn),
2228 /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1),
2229 /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1)
c906108c
SS		 2230};
2231
7a78ae4e
ND		 2232/* Motorola PowerPC 601. Note that the 601 has different register numbers
2233 for reading and writing RTCU and RTCL. However, how one reads and writes a
c906108c 2234 register is the stub's problem. */
7a78ae4e 2235static const struct reg registers_601[] =
c5aa993b 2236{
7a78ae4e
ND		 2237 COMMON_UISA_REGS,
2238 PPC_UISA_SPRS,
2239 PPC_SEGMENT_REGS,
2240 PPC_OEA_SPRS,
2241 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2242 /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl)
c906108c
SS		 2243};
2244
64366f1c 2245/* Motorola PowerPC 602. */
7a78ae4e 2246static const struct reg registers_602[] =
c5aa993b 2247{
7a78ae4e
ND		 2248 COMMON_UISA_REGS,
2249 PPC_UISA_SPRS,
2250 PPC_SEGMENT_REGS,
2251 PPC_OEA_SPRS,
2252 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2253 /* 123 */ R0, R(tcr), R(ibr), R(esassr),
2254 /* 127 */ R(sebr), R(ser), R(sp), R(lt)
c906108c
SS		 2255};
2256
64366f1c 2257/* Motorola/IBM PowerPC 603 or 603e. */
7a78ae4e 2258static const struct reg registers_603[] =
c5aa993b 2259{
7a78ae4e
ND		 2260 COMMON_UISA_REGS,
2261 PPC_UISA_SPRS,
2262 PPC_SEGMENT_REGS,
2263 PPC_OEA_SPRS,
2264 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2265 /* 123 */ R0, R(dmiss), R(dcmp), R(hash1),
2266 /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa)
c906108c
SS		 2267};
2268
64366f1c 2269/* Motorola PowerPC 604 or 604e. */
7a78ae4e 2270static const struct reg registers_604[] =
c5aa993b 2271{
7a78ae4e
ND		 2272 COMMON_UISA_REGS,
2273 PPC_UISA_SPRS,
2274 PPC_SEGMENT_REGS,
2275 PPC_OEA_SPRS,
2276 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2277 /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2),
2278 /* 127 */ R(sia), R(sda)
c906108c
SS		 2279};
2280
64366f1c 2281/* Motorola/IBM PowerPC 750 or 740. */
7a78ae4e 2282static const struct reg registers_750[] =
c5aa993b 2283{
7a78ae4e
ND		 2284 COMMON_UISA_REGS,
2285 PPC_UISA_SPRS,
2286 PPC_SEGMENT_REGS,
2287 PPC_OEA_SPRS,
2288 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2289 /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2),
2290 /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4),
2291 /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia),
2292 /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr),
2293 /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3)
c906108c
SS		 2294};
2295
2296
64366f1c 2297/* Motorola PowerPC 7400. */
1fcc0bb8
EZ		 2298static const struct reg registers_7400[] =
2299{
2300 /* gpr0-gpr31, fpr0-fpr31 */
2301 COMMON_UISA_REGS,
13c7b1ca 2302 /* cr, lr, ctr, xer, fpscr */
1fcc0bb8
EZ		 2303 PPC_UISA_SPRS,
2304 /* sr0-sr15 */
2305 PPC_SEGMENT_REGS,
2306 PPC_OEA_SPRS,
2307 /* vr0-vr31, vrsave, vscr */
2308 PPC_ALTIVEC_REGS
2309 /* FIXME? Add more registers? */
2310};
2311
c8001721
EZ		 2312/* Motorola e500. */
2313static const struct reg registers_e500[] =
2314{
2315 R(pc), R(ps),
2316 /* cr, lr, ctr, xer, "" */
2317 PPC_UISA_NOFP_SPRS,
2318 /* 7...38 */
2319 PPC_EV_REGS,
338ef23d
AC		 2320 R8(acc), R(spefscr),
2321 /* NOTE: Add new registers here the end of the raw register
2322 list and just before the first pseudo register. */
13c7b1ca 2323 /* 41...72 */
c8001721
EZ		 2324 PPC_GPRS_PSEUDO_REGS
2325};
2326
c906108c 2327/* Information about a particular processor variant. */
7a78ae4e 2328
c906108c 2329struct variant
c5aa993b
JM		 2330 {
2331 /* Name of this variant. */
2332 char *name;
c906108c 2333
c5aa993b
JM		 2334 /* English description of the variant. */
2335 char *description;
c906108c 2336
64366f1c 2337 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2338 enum bfd_architecture arch;
2339
64366f1c 2340 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2341 unsigned long mach;
2342
489461e2
EZ		 2343 /* Number of real registers. */
2344 int nregs;
2345
2346 /* Number of pseudo registers. */
2347 int npregs;
2348
2349 /* Number of total registers (the sum of nregs and npregs). */
2350 int num_tot_regs;
2351
c5aa993b
JM		 2352 /* Table of register names; registers[R] is the name of the register
2353 number R. */
7a78ae4e 2354 const struct reg *regs;
c5aa993b 2355 };
c906108c 2356
489461e2
EZ		 2357#define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2358
2359static int
2360num_registers (const struct reg *reg_list, int num_tot_regs)
2361{
2362 int i;
2363 int nregs = 0;
2364
2365 for (i = 0; i < num_tot_regs; i++)
2366 if (!reg_list[i].pseudo)
2367 nregs++;
2368
2369 return nregs;
2370}
2371
2372static int
2373num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2374{
2375 int i;
2376 int npregs = 0;
2377
2378 for (i = 0; i < num_tot_regs; i++)
2379 if (reg_list[i].pseudo)
2380 npregs ++;
2381
2382 return npregs;
2383}
c906108c 2384
c906108c
SS		 2385/* Information in this table comes from the following web sites:
2386 IBM: http://www.chips.ibm.com:80/products/embedded/
2387 Motorola: http://www.mot.com/SPS/PowerPC/
2388
2389 I'm sure I've got some of the variant descriptions not quite right.
2390 Please report any inaccuracies you find to GDB's maintainer.
2391
2392 If you add entries to this table, please be sure to allow the new
2393 value as an argument to the --with-cpu flag, in configure.in. */
2394
489461e2 2395static struct variant variants[] =
c906108c 2396{
489461e2 2397
7a78ae4e 2398 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
489461e2
EZ		 2399 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2400 registers_powerpc},
7a78ae4e 2401 {"power", "POWER user-level", bfd_arch_rs6000,
489461e2
EZ		 2402 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2403 registers_power},
7a78ae4e 2404 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
489461e2
EZ		 2405 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2406 registers_403},
7a78ae4e 2407 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
489461e2
EZ		 2408 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2409 registers_601},
7a78ae4e 2410 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
489461e2
EZ		 2411 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2412 registers_602},
7a78ae4e 2413 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
489461e2
EZ		 2414 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2415 registers_603},
7a78ae4e 2416 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
489461e2
EZ		 2417 604, -1, -1, tot_num_registers (registers_604),
2418 registers_604},
7a78ae4e 2419 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
489461e2
EZ		 2420 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2421 registers_403GC},
7a78ae4e 2422 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
489461e2
EZ		 2423 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2424 registers_505},
7a78ae4e 2425 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
489461e2
EZ		 2426 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2427 registers_860},
7a78ae4e 2428 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
489461e2
EZ		 2429 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2430 registers_750},
1fcc0bb8 2431 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
489461e2
EZ		 2432 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2433 registers_7400},
c8001721
EZ		 2434 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2435 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2436 registers_e500},
7a78ae4e 2437
5d57ee30
KB		 2438 /* 64-bit */
2439 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
489461e2
EZ		 2440 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2441 registers_powerpc},
7a78ae4e 2442 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
489461e2
EZ		 2443 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2444 registers_powerpc},
5d57ee30 2445 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
489461e2
EZ		 2446 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2447 registers_powerpc},
7a78ae4e 2448 {"a35", "PowerPC A35", bfd_arch_powerpc,
489461e2
EZ		 2449 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2450 registers_powerpc},
5d57ee30 2451 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
489461e2
EZ		 2452 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2453 registers_powerpc},
5d57ee30 2454 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
489461e2
EZ		 2455 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2456 registers_powerpc},
5d57ee30 2457
64366f1c 2458 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 2459 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
489461e2
EZ		 2460 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2461 registers_power},
7a78ae4e 2462 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
489461e2
EZ		 2463 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2464 registers_power},
7a78ae4e 2465 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
489461e2
EZ		 2466 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2467 registers_power},
7a78ae4e 2468
489461e2 2469 {0, 0, 0, 0, 0, 0, 0, 0}
c906108c
SS		 2470};
2471
64366f1c 2472/* Initialize the number of registers and pseudo registers in each variant. */
489461e2
EZ		 2473
2474static void
2475init_variants (void)
2476{
2477 struct variant *v;
2478
2479 for (v = variants; v->name; v++)
2480 {
2481 if (v->nregs == -1)
2482 v->nregs = num_registers (v->regs, v->num_tot_regs);
2483 if (v->npregs == -1)
2484 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2485 }
2486}
c906108c 2487
7a78ae4e 2488/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 2489 MACH. If no such variant exists, return null. */
c906108c 2490
7a78ae4e
ND		 2491static const struct variant *
2492find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 2493{
7a78ae4e 2494 const struct variant *v;
c5aa993b 2495
7a78ae4e
ND		 2496 for (v = variants; v->name; v++)
2497 if (arch == v->arch && mach == v->mach)
2498 return v;
c906108c 2499
7a78ae4e 2500 return NULL;
c906108c 2501}
9364a0ef
EZ		 2502
2503static int
2504gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2505{
2506 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2507 return print_insn_big_powerpc (memaddr, info);
2508 else
2509 return print_insn_little_powerpc (memaddr, info);
2510}
7a78ae4e 2511\f
61a65099
KB		 2512static CORE_ADDR
2513rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2514{
2515 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2516}
2517
2518static struct frame_id
2519rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2520{
2521 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2522 SP_REGNUM),
2523 frame_pc_unwind (next_frame));
2524}
2525
2526struct rs6000_frame_cache
2527{
2528 CORE_ADDR base;
2529 CORE_ADDR initial_sp;
2530 struct trad_frame_saved_reg *saved_regs;
2531};
2532
2533static struct rs6000_frame_cache *
2534rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2535{
2536 struct rs6000_frame_cache *cache;
2537 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2538 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2539 struct rs6000_framedata fdata;
2540 int wordsize = tdep->wordsize;
2541
2542 if ((*this_cache) != NULL)
2543 return (*this_cache);
2544 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2545 (*this_cache) = cache;
2546 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2547
2548 skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame),
2549 &fdata);
2550
2551 /* If there were any saved registers, figure out parent's stack
2552 pointer. */
2553 /* The following is true only if the frame doesn't have a call to
2554 alloca(), FIXME. */
2555
2556 if (fdata.saved_fpr == 0
2557 && fdata.saved_gpr == 0
2558 && fdata.saved_vr == 0
2559 && fdata.saved_ev == 0
2560 && fdata.lr_offset == 0
2561 && fdata.cr_offset == 0
2562 && fdata.vr_offset == 0
2563 && fdata.ev_offset == 0)
2564 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2565 else
2566 {
2567 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2568 address of the current frame. Things might be easier if the
2569 ->frame pointed to the outer-most address of the frame. In
2570 the mean time, the address of the prev frame is used as the
2571 base address of this frame. */
2572 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2573 if (!fdata.frameless)
2574 /* Frameless really means stackless. */
2575 cache->base = read_memory_addr (cache->base, wordsize);
2576 }
2577 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
2578
2579 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2580 All fpr's from saved_fpr to fp31 are saved. */
2581
2582 if (fdata.saved_fpr >= 0)
2583 {
2584 int i;
2585 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 2586
2587 /* If skip_prologue says floating-point registers were saved,
2588 but the current architecture has no floating-point registers,
2589 then that's strange. But we have no indices to even record
2590 the addresses under, so we just ignore it. */
2591 if (ppc_floating_point_unit_p (gdbarch))
063715bf 2592 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 2593 {
2594 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2595 fpr_addr += 8;
2596 }
61a65099
KB		 2597 }
2598
2599 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2600 All gpr's from saved_gpr to gpr31 are saved. */
2601
2602 if (fdata.saved_gpr >= 0)
2603 {
2604 int i;
2605 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 2606 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099
KB		 2607 {
2608 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2609 gpr_addr += wordsize;
2610 }
2611 }
2612
2613 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2614 All vr's from saved_vr to vr31 are saved. */
2615 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2616 {
2617 if (fdata.saved_vr >= 0)
2618 {
2619 int i;
2620 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2621 for (i = fdata.saved_vr; i < 32; i++)
2622 {
2623 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2624 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2625 }
2626 }
2627 }
2628
2629 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2630 All vr's from saved_ev to ev31 are saved. ????? */
2631 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
2632 {
2633 if (fdata.saved_ev >= 0)
2634 {
2635 int i;
2636 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 2637 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 2638 {
2639 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2640 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2641 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2642 }
2643 }
2644 }
2645
2646 /* If != 0, fdata.cr_offset is the offset from the frame that
2647 holds the CR. */
2648 if (fdata.cr_offset != 0)
2649 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2650
2651 /* If != 0, fdata.lr_offset is the offset from the frame that
2652 holds the LR. */
2653 if (fdata.lr_offset != 0)
2654 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2655 /* The PC is found in the link register. */
2656 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
2657
2658 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2659 holds the VRSAVE. */
2660 if (fdata.vrsave_offset != 0)
2661 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2662
2663 if (fdata.alloca_reg < 0)
2664 /* If no alloca register used, then fi->frame is the value of the
2665 %sp for this frame, and it is good enough. */
2666 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2667 else
2668 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
2669 fdata.alloca_reg);
2670
2671 return cache;
2672}
2673
2674static void
2675rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
2676 struct frame_id *this_id)
2677{
2678 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2679 this_cache);
2680 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
2681}
2682
2683static void
2684rs6000_frame_prev_register (struct frame_info *next_frame,
2685 void **this_cache,
2686 int regnum, int *optimizedp,
2687 enum lval_type *lvalp, CORE_ADDR *addrp,
2688 int *realnump, void *valuep)
2689{
2690 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2691 this_cache);
2692 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
2693 optimizedp, lvalp, addrp, realnump, valuep);
2694}
2695
2696static const struct frame_unwind rs6000_frame_unwind =
2697{
2698 NORMAL_FRAME,
2699 rs6000_frame_this_id,
2700 rs6000_frame_prev_register
2701};
2702
2703static const struct frame_unwind *
2704rs6000_frame_sniffer (struct frame_info *next_frame)
2705{
2706 return &rs6000_frame_unwind;
2707}
2708
2709\f
2710
2711static CORE_ADDR
2712rs6000_frame_base_address (struct frame_info *next_frame,
2713 void **this_cache)
2714{
2715 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2716 this_cache);
2717 return info->initial_sp;
2718}
2719
2720static const struct frame_base rs6000_frame_base = {
2721 &rs6000_frame_unwind,
2722 rs6000_frame_base_address,
2723 rs6000_frame_base_address,
2724 rs6000_frame_base_address
2725};
2726
2727static const struct frame_base *
2728rs6000_frame_base_sniffer (struct frame_info *next_frame)
2729{
2730 return &rs6000_frame_base;
2731}
2732
7a78ae4e
ND		 2733/* Initialize the current architecture based on INFO. If possible, re-use an
2734 architecture from ARCHES, which is a list of architectures already created
2735 during this debugging session.
c906108c 2736
7a78ae4e 2737 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 2738 a binary file. */
c906108c 2739
7a78ae4e
ND		 2740static struct gdbarch *
2741rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2742{
2743 struct gdbarch *gdbarch;
2744 struct gdbarch_tdep *tdep;
9aa1e687 2745 int wordsize, from_xcoff_exec, from_elf_exec, power, i, off;
7a78ae4e
ND		 2746 struct reg *regs;
2747 const struct variant *v;
2748 enum bfd_architecture arch;
2749 unsigned long mach;
2750 bfd abfd;
7b112f9c 2751 int sysv_abi;
5bf1c677 2752 asection *sect;
7a78ae4e 2753
9aa1e687 2754 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 2755 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
2756
9aa1e687
KB		 2757 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
2758 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2759
2760 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2761
e712c1cf 2762 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 2763 that, else choose a likely default. */
9aa1e687 2764 if (from_xcoff_exec)
c906108c 2765 {
11ed25ac 2766 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 2767 wordsize = 8;
2768 else
2769 wordsize = 4;
c906108c 2770 }
9aa1e687
KB		 2771 else if (from_elf_exec)
2772 {
2773 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
2774 wordsize = 8;
2775 else
2776 wordsize = 4;
2777 }
c906108c 2778 else
7a78ae4e 2779 {
27b15785
KB		 2780 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
2781 wordsize = info.bfd_arch_info->bits_per_word /
2782 info.bfd_arch_info->bits_per_byte;
2783 else
2784 wordsize = 4;
7a78ae4e 2785 }
c906108c 2786
64366f1c 2787 /* Find a candidate among extant architectures. */
7a78ae4e
ND		 2788 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2789 arches != NULL;
2790 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2791 {
2792 /* Word size in the various PowerPC bfd_arch_info structs isn't
2793 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
64366f1c 2794 separate word size check. */
7a78ae4e 2795 tdep = gdbarch_tdep (arches->gdbarch);
4be87837 2796 if (tdep && tdep->wordsize == wordsize)
7a78ae4e
ND		 2797 return arches->gdbarch;
2798 }
c906108c 2799
7a78ae4e
ND		 2800 /* None found, create a new architecture from INFO, whose bfd_arch_info
2801 validity depends on the source:
2802 - executable useless
2803 - rs6000_host_arch() good
2804 - core file good
2805 - "set arch" trust blindly
2806 - GDB startup useless but harmless */
c906108c 2807
9aa1e687 2808 if (!from_xcoff_exec)
c906108c 2809 {
b732d07d 2810 arch = info.bfd_arch_info->arch;
7a78ae4e 2811 mach = info.bfd_arch_info->mach;
c906108c 2812 }
7a78ae4e 2813 else
c906108c 2814 {
7a78ae4e 2815 arch = bfd_arch_powerpc;
35cec841 2816 bfd_default_set_arch_mach (&abfd, arch, 0);
7a78ae4e 2817 info.bfd_arch_info = bfd_get_arch_info (&abfd);
35cec841 2818 mach = info.bfd_arch_info->mach;
7a78ae4e
ND		 2819 }
2820 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2821 tdep->wordsize = wordsize;
5bf1c677
EZ		 2822
2823 /* For e500 executables, the apuinfo section is of help here. Such
2824 section contains the identifier and revision number of each
2825 Application-specific Processing Unit that is present on the
2826 chip. The content of the section is determined by the assembler
2827 which looks at each instruction and determines which unit (and
2828 which version of it) can execute it. In our case we just look for
2829 the existance of the section. */
2830
2831 if (info.abfd)
2832 {
2833 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
2834 if (sect)
2835 {
2836 arch = info.bfd_arch_info->arch;
2837 mach = bfd_mach_ppc_e500;
2838 bfd_default_set_arch_mach (&abfd, arch, mach);
2839 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2840 }
2841 }
2842
7a78ae4e
ND		 2843 gdbarch = gdbarch_alloc (&info, tdep);
2844 power = arch == bfd_arch_rs6000;
2845
489461e2
EZ		 2846 /* Initialize the number of real and pseudo registers in each variant. */
2847 init_variants ();
2848
64366f1c 2849 /* Choose variant. */
7a78ae4e
ND		 2850 v = find_variant_by_arch (arch, mach);
2851 if (!v)
dd47e6fd
EZ		 2852 return NULL;
2853
7a78ae4e
ND		 2854 tdep->regs = v->regs;
2855
2188cbdd 2856 tdep->ppc_gp0_regnum = 0;
2188cbdd
EZ		 2857 tdep->ppc_toc_regnum = 2;
2858 tdep->ppc_ps_regnum = 65;
2859 tdep->ppc_cr_regnum = 66;
2860 tdep->ppc_lr_regnum = 67;
2861 tdep->ppc_ctr_regnum = 68;
2862 tdep->ppc_xer_regnum = 69;
2863 if (v->mach == bfd_mach_ppc_601)
2864 tdep->ppc_mq_regnum = 124;
e3f36dbd 2865 else if (power)
2188cbdd 2866 tdep->ppc_mq_regnum = 70;
e3f36dbd
KB		 2867 else
2868 tdep->ppc_mq_regnum = -1;
366f009f 2869 tdep->ppc_fp0_regnum = 32;
e3f36dbd 2870 tdep->ppc_fpscr_regnum = power ? 71 : 70;
baffbae0
JB		 2871 tdep->ppc_vr0_regnum = -1;
2872 tdep->ppc_vrsave_regnum = -1;
2873 tdep->ppc_ev0_regnum = -1;
2874 tdep->ppc_ev31_regnum = -1;
867e2dc5
JB		 2875 tdep->ppc_acc_regnum = -1;
2876 tdep->ppc_spefscr_regnum = -1;
2188cbdd 2877
c8001721
EZ		 2878 set_gdbarch_pc_regnum (gdbarch, 64);
2879 set_gdbarch_sp_regnum (gdbarch, 1);
0ba6dca9 2880 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
afd48b75 2881 if (sysv_abi && wordsize == 8)
05580c65 2882 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
e754ae69 2883 else if (sysv_abi && wordsize == 4)
05580c65 2884 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
afd48b75
AC		 2885 else
2886 {
2887 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
2888 set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value);
2889 }
c8001721 2890
baffbae0
JB		 2891 /* Set lr_frame_offset. */
2892 if (wordsize == 8)
2893 tdep->lr_frame_offset = 16;
2894 else if (sysv_abi)
2895 tdep->lr_frame_offset = 4;
2896 else
2897 tdep->lr_frame_offset = 8;
2898
2899 /* Calculate byte offsets in raw register array. */
2900 tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int));
2901 for (i = off = 0; i < v->num_tot_regs; i++)
2902 {
2903 tdep->regoff[i] = off;
2904 off += regsize (v->regs + i, wordsize);
2905 }
2906
1fcc0bb8
EZ		 2907 if (v->arch == bfd_arch_powerpc)
2908 switch (v->mach)
2909 {
2910 case bfd_mach_ppc:
2911 tdep->ppc_vr0_regnum = 71;
2912 tdep->ppc_vrsave_regnum = 104;
2913 break;
2914 case bfd_mach_ppc_7400:
2915 tdep->ppc_vr0_regnum = 119;
54c2a1e6 2916 tdep->ppc_vrsave_regnum = 152;
c8001721
EZ		 2917 break;
2918 case bfd_mach_ppc_e500:
338ef23d 2919 tdep->ppc_gp0_regnum = 41;
c8001721
EZ		 2920 tdep->ppc_toc_regnum = -1;
2921 tdep->ppc_ps_regnum = 1;
2922 tdep->ppc_cr_regnum = 2;
2923 tdep->ppc_lr_regnum = 3;
2924 tdep->ppc_ctr_regnum = 4;
2925 tdep->ppc_xer_regnum = 5;
2926 tdep->ppc_ev0_regnum = 7;
2927 tdep->ppc_ev31_regnum = 38;
383f0f5b
JB		 2928 tdep->ppc_fp0_regnum = -1;
2929 tdep->ppc_fpscr_regnum = -1;
867e2dc5
JB		 2930 tdep->ppc_acc_regnum = 39;
2931 tdep->ppc_spefscr_regnum = 40;
c8001721 2932 set_gdbarch_pc_regnum (gdbarch, 0);
338ef23d 2933 set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
0ba6dca9 2934 set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
c8001721
EZ		 2935 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
2936 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
1fcc0bb8 2937 break;
1fcc0bb8
EZ		 2938 }
2939
338ef23d
AC		 2940 /* Sanity check on registers. */
2941 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
2942
56a6dfb9
KB		 2943 /* Select instruction printer. */
2944 if (arch == power)
9364a0ef 2945 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 2946 else
9364a0ef 2947 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 2948
7a78ae4e 2949 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
7a78ae4e
ND		 2950
2951 set_gdbarch_num_regs (gdbarch, v->nregs);
c8001721 2952 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
7a78ae4e 2953 set_gdbarch_register_name (gdbarch, rs6000_register_name);
691d145a 2954 set_gdbarch_register_type (gdbarch, rs6000_register_type);
7a78ae4e
ND		 2955
2956 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2957 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2958 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2959 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2960 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2961 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2962 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
ab9fe00e
KB		 2963 if (sysv_abi)
2964 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
2965 else
2966 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4e409299 2967 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 2968
11269d7e 2969 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
8b148df9
AC		 2970 if (sysv_abi && wordsize == 8)
2971 /* PPC64 SYSV. */
2972 set_gdbarch_frame_red_zone_size (gdbarch, 288);
2973 else if (!sysv_abi && wordsize == 4)
5bffac25
AC		 2974 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
2975 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
2976 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
2977 224. */
2978 set_gdbarch_frame_red_zone_size (gdbarch, 224);
7a78ae4e 2979
691d145a
JB		 2980 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
2981 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
2982 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
2983
18ed0c4e
JB		 2984 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
2985 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
2ea5f656
KB		 2986 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
2987 is correct for the SysV ABI when the wordsize is 8, but I'm also
2988 fairly certain that ppc_sysv_abi_push_arguments() will give even
2989 worse results since it only works for 32-bit code. So, for the moment,
2990 we're better off calling rs6000_push_arguments() since it works for
2991 64-bit code. At some point in the future, this matter needs to be
2992 revisited. */
2993 if (sysv_abi && wordsize == 4)
77b2b6d4 2994 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
8be9034a
AC		 2995 else if (sysv_abi && wordsize == 8)
2996 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
9aa1e687 2997 else
77b2b6d4 2998 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
7a78ae4e 2999
74055713 3000 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
7a78ae4e
ND		 3001
3002 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3003 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 3004 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3005
6066c3de
AC		 3006 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3007 for the descriptor and ".FN" for the entry-point -- a user
3008 specifying "break FN" will unexpectedly end up with a breakpoint
3009 on the descriptor and not the function. This architecture method
3010 transforms any breakpoints on descriptors into breakpoints on the
3011 corresponding entry point. */
3012 if (sysv_abi && wordsize == 8)
3013 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3014
7a78ae4e
ND		 3015 /* Not sure on this. FIXMEmgo */
3016 set_gdbarch_frame_args_skip (gdbarch, 8);
3017
05580c65 3018 if (!sysv_abi)
7b112f9c 3019 set_gdbarch_use_struct_convention (gdbarch,
b9ff3018 3020 rs6000_use_struct_convention);
8e0662df 3021
15813d3f
AC		 3022 if (!sysv_abi)
3023 {
3024 /* Handle RS/6000 function pointers (which are really function
3025 descriptors). */
f517ea4e
PS		 3026 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3027 rs6000_convert_from_func_ptr_addr);
9aa1e687 3028 }
7a78ae4e 3029
143985b7
AF		 3030 /* Helpers for function argument information. */
3031 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3032
7b112f9c 3033 /* Hook in ABI-specific overrides, if they have been registered. */
4be87837 3034 gdbarch_init_osabi (info, gdbarch);
7b112f9c 3035
61a65099
KB		 3036 switch (info.osabi)
3037 {
3038 case GDB_OSABI_NETBSD_AOUT:
3039 case GDB_OSABI_NETBSD_ELF:
3040 case GDB_OSABI_UNKNOWN:
3041 case GDB_OSABI_LINUX:
3042 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3043 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3044 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3045 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3046 break;
3047 default:
61a65099 3048 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 3049
3050 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3051 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3052 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3053 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 3054 }
3055
ef5200c1
AC		 3056 if (from_xcoff_exec)
3057 {
3058 /* NOTE: jimix/2003-06-09: This test should really check for
3059 GDB_OSABI_AIX when that is defined and becomes
3060 available. (Actually, once things are properly split apart,
3061 the test goes away.) */
3062 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
3063 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
3064 }
3065
7a78ae4e 3066 return gdbarch;
c906108c
SS		 3067}
3068
7b112f9c
JT		 3069static void
3070rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3071{
3072 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3073
3074 if (tdep == NULL)
3075 return;
3076
4be87837 3077 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 3078}
3079
1fcc0bb8
EZ		 3080static struct cmd_list_element *info_powerpc_cmdlist = NULL;
3081
3082static void
3083rs6000_info_powerpc_command (char *args, int from_tty)
3084{
3085 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
3086}
3087
c906108c
SS		 3088/* Initialization code. */
3089
a78f21af 3090extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
b9362cc7 3091
c906108c 3092void
fba45db2 3093_initialize_rs6000_tdep (void)
c906108c 3094{
7b112f9c
JT		 3095 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3096 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
1fcc0bb8
EZ		 3097
3098 /* Add root prefix command for "info powerpc" commands */
3099 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
3100 "Various POWERPC info specific commands.",
3101 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);
c906108c 3102}
GDB Binutils - Deliverables
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