Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 AC |
2 | |
3 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, | |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software | |
5 | Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbcmd.h" | |
c906108c | 31 | #include "objfiles.h" |
7a78ae4e | 32 | #include "arch-utils.h" |
4e052eda | 33 | #include "regcache.h" |
d195bc9f | 34 | #include "regset.h" |
d16aafd8 | 35 | #include "doublest.h" |
fd0407d6 | 36 | #include "value.h" |
1fcc0bb8 | 37 | #include "parser-defs.h" |
4be87837 | 38 | #include "osabi.h" |
7a78ae4e | 39 | |
2fccf04a | 40 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 41 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 42 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
43 | #include "coff/xcoff.h" |
44 | #include "libxcoff.h" | |
7a78ae4e | 45 | |
9aa1e687 | 46 | #include "elf-bfd.h" |
7a78ae4e | 47 | |
6ded7999 | 48 | #include "solib-svr4.h" |
9aa1e687 | 49 | #include "ppc-tdep.h" |
7a78ae4e | 50 | |
338ef23d | 51 | #include "gdb_assert.h" |
a89aa300 | 52 | #include "dis-asm.h" |
338ef23d | 53 | |
61a65099 KB |
54 | #include "trad-frame.h" |
55 | #include "frame-unwind.h" | |
56 | #include "frame-base.h" | |
57 | ||
7a78ae4e ND |
58 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
59 | structure on the stack and then calls the signal handler, passing | |
60 | the address of the sigcontext in an argument register. Usually | |
61 | the signal handler doesn't save this register, so we have to | |
62 | access the sigcontext structure via an offset from the signal handler | |
63 | frame. | |
64 | The following constants were determined by experimentation on AIX 3.2. */ | |
65 | #define SIG_FRAME_PC_OFFSET 96 | |
66 | #define SIG_FRAME_LR_OFFSET 108 | |
67 | #define SIG_FRAME_FP_OFFSET 284 | |
68 | ||
7a78ae4e ND |
69 | /* To be used by skip_prologue. */ |
70 | ||
71 | struct rs6000_framedata | |
72 | { | |
73 | int offset; /* total size of frame --- the distance | |
74 | by which we decrement sp to allocate | |
75 | the frame */ | |
76 | int saved_gpr; /* smallest # of saved gpr */ | |
77 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 78 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 79 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
80 | int alloca_reg; /* alloca register number (frame ptr) */ |
81 | char frameless; /* true if frameless functions. */ | |
82 | char nosavedpc; /* true if pc not saved. */ | |
83 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
84 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 85 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 86 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
87 | int lr_offset; /* offset of saved lr */ |
88 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 89 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
90 | }; |
91 | ||
92 | /* Description of a single register. */ | |
93 | ||
94 | struct reg | |
95 | { | |
96 | char *name; /* name of register */ | |
97 | unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ | |
98 | unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ | |
99 | unsigned char fpr; /* whether register is floating-point */ | |
489461e2 | 100 | unsigned char pseudo; /* whether register is pseudo */ |
7a78ae4e ND |
101 | }; |
102 | ||
c906108c SS |
103 | /* Breakpoint shadows for the single step instructions will be kept here. */ |
104 | ||
c5aa993b JM |
105 | static struct sstep_breaks |
106 | { | |
107 | /* Address, or 0 if this is not in use. */ | |
108 | CORE_ADDR address; | |
109 | /* Shadow contents. */ | |
110 | char data[4]; | |
111 | } | |
112 | stepBreaks[2]; | |
c906108c SS |
113 | |
114 | /* Hook for determining the TOC address when calling functions in the | |
115 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
116 | this hook to point to find_toc_address. */ | |
117 | ||
7a78ae4e ND |
118 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
119 | ||
120 | /* Hook to set the current architecture when starting a child process. | |
121 | rs6000-nat.c sets this. */ | |
122 | ||
123 | void (*rs6000_set_host_arch_hook) (int) = NULL; | |
c906108c SS |
124 | |
125 | /* Static function prototypes */ | |
126 | ||
a14ed312 KB |
127 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
128 | CORE_ADDR safety); | |
077276e8 KB |
129 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
130 | struct rs6000_framedata *); | |
c906108c | 131 | |
64b84175 KB |
132 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
133 | int | |
134 | altivec_register_p (int regno) | |
135 | { | |
136 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
137 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
138 | return 0; | |
139 | else | |
140 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
141 | } | |
142 | ||
383f0f5b | 143 | |
867e2dc5 JB |
144 | /* Return true if REGNO is an SPE register, false otherwise. */ |
145 | int | |
146 | spe_register_p (int regno) | |
147 | { | |
148 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
149 | ||
150 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
151 | if (tdep->ppc_ev0_regnum >= 0 | |
152 | && tdep->ppc_ev31_regnum >= 0 | |
153 | && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) | |
154 | return 1; | |
155 | ||
156 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ | |
157 | if (tdep->ppc_acc_regnum >= 0 | |
158 | && tdep->ppc_acc_regnum == regno) | |
159 | return 1; | |
160 | ||
161 | /* Is it a reference to the SPE floating-point status and control register, | |
162 | and do we have that? */ | |
163 | if (tdep->ppc_spefscr_regnum >= 0 | |
164 | && tdep->ppc_spefscr_regnum == regno) | |
165 | return 1; | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | ||
383f0f5b JB |
171 | /* Return non-zero if the architecture described by GDBARCH has |
172 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
173 | int |
174 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
175 | { | |
383f0f5b JB |
176 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
177 | ||
178 | return (tdep->ppc_fp0_regnum >= 0 | |
179 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 180 | } |
d195bc9f MK |
181 | \f |
182 | ||
183 | /* Register set support functions. */ | |
184 | ||
185 | static void | |
186 | ppc_supply_reg (struct regcache *regcache, int regnum, | |
187 | const char *regs, size_t offset) | |
188 | { | |
189 | if (regnum != -1 && offset != -1) | |
190 | regcache_raw_supply (regcache, regnum, regs + offset); | |
191 | } | |
192 | ||
193 | static void | |
194 | ppc_collect_reg (const struct regcache *regcache, int regnum, | |
195 | char *regs, size_t offset) | |
196 | { | |
197 | if (regnum != -1 && offset != -1) | |
198 | regcache_raw_collect (regcache, regnum, regs + offset); | |
199 | } | |
200 | ||
201 | /* Supply register REGNUM in the general-purpose register set REGSET | |
202 | from the buffer specified by GREGS and LEN to register cache | |
203 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
204 | ||
205 | void | |
206 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
207 | int regnum, const void *gregs, size_t len) | |
208 | { | |
209 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
210 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
211 | const struct ppc_reg_offsets *offsets = regset->descr; | |
212 | size_t offset; | |
213 | int i; | |
214 | ||
cdf2c5f5 | 215 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; |
063715bf | 216 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 217 | i++, offset += 4) |
d195bc9f MK |
218 | { |
219 | if (regnum == -1 || regnum == i) | |
220 | ppc_supply_reg (regcache, i, gregs, offset); | |
221 | } | |
222 | ||
223 | if (regnum == -1 || regnum == PC_REGNUM) | |
224 | ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
225 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
226 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, | |
227 | gregs, offsets->ps_offset); | |
228 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
229 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, | |
230 | gregs, offsets->cr_offset); | |
231 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
232 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, | |
233 | gregs, offsets->lr_offset); | |
234 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
235 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, | |
236 | gregs, offsets->ctr_offset); | |
237 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
238 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, | |
239 | gregs, offsets->cr_offset); | |
240 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
241 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset); | |
242 | } | |
243 | ||
244 | /* Supply register REGNUM in the floating-point register set REGSET | |
245 | from the buffer specified by FPREGS and LEN to register cache | |
246 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
247 | ||
248 | void | |
249 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
250 | int regnum, const void *fpregs, size_t len) | |
251 | { | |
252 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
253 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
254 | const struct ppc_reg_offsets *offsets = regset->descr; | |
255 | size_t offset; | |
256 | int i; | |
257 | ||
383f0f5b JB |
258 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
259 | ||
d195bc9f | 260 | offset = offsets->f0_offset; |
366f009f JB |
261 | for (i = tdep->ppc_fp0_regnum; |
262 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
263 | i++, offset += 4) | |
d195bc9f MK |
264 | { |
265 | if (regnum == -1 || regnum == i) | |
266 | ppc_supply_reg (regcache, i, fpregs, offset); | |
267 | } | |
268 | ||
269 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
270 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
271 | fpregs, offsets->fpscr_offset); | |
272 | } | |
273 | ||
274 | /* Collect register REGNUM in the general-purpose register set | |
275 | REGSET. from register cache REGCACHE into the buffer specified by | |
276 | GREGS and LEN. If REGNUM is -1, do this for all registers in | |
277 | REGSET. */ | |
278 | ||
279 | void | |
280 | ppc_collect_gregset (const struct regset *regset, | |
281 | const struct regcache *regcache, | |
282 | int regnum, void *gregs, size_t len) | |
283 | { | |
284 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
285 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
286 | const struct ppc_reg_offsets *offsets = regset->descr; | |
287 | size_t offset; | |
288 | int i; | |
289 | ||
290 | offset = offsets->r0_offset; | |
cdf2c5f5 | 291 | for (i = tdep->ppc_gp0_regnum; |
063715bf | 292 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 293 | i++, offset += 4) |
d195bc9f MK |
294 | { |
295 | if (regnum == -1 || regnum == i) | |
2e56e9c1 | 296 | ppc_collect_reg (regcache, i, gregs, offset); |
d195bc9f MK |
297 | } |
298 | ||
299 | if (regnum == -1 || regnum == PC_REGNUM) | |
300 | ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
301 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
302 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, | |
303 | gregs, offsets->ps_offset); | |
304 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
305 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, | |
306 | gregs, offsets->cr_offset); | |
307 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
308 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, | |
309 | gregs, offsets->lr_offset); | |
310 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
311 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, | |
312 | gregs, offsets->ctr_offset); | |
313 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
314 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, | |
315 | gregs, offsets->xer_offset); | |
316 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
317 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, | |
318 | gregs, offsets->mq_offset); | |
319 | } | |
320 | ||
321 | /* Collect register REGNUM in the floating-point register set | |
322 | REGSET. from register cache REGCACHE into the buffer specified by | |
323 | FPREGS and LEN. If REGNUM is -1, do this for all registers in | |
324 | REGSET. */ | |
325 | ||
326 | void | |
327 | ppc_collect_fpregset (const struct regset *regset, | |
328 | const struct regcache *regcache, | |
329 | int regnum, void *fpregs, size_t len) | |
330 | { | |
331 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
332 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
333 | const struct ppc_reg_offsets *offsets = regset->descr; | |
334 | size_t offset; | |
335 | int i; | |
336 | ||
383f0f5b JB |
337 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
338 | ||
d195bc9f | 339 | offset = offsets->f0_offset; |
366f009f JB |
340 | for (i = tdep->ppc_fp0_regnum; |
341 | i <= tdep->ppc_fp0_regnum + ppc_num_fprs; | |
342 | i++, offset += 4) | |
d195bc9f MK |
343 | { |
344 | if (regnum == -1 || regnum == i) | |
345 | ppc_collect_reg (regcache, regnum, fpregs, offset); | |
346 | } | |
347 | ||
348 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
349 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
350 | fpregs, offsets->fpscr_offset); | |
351 | } | |
352 | \f | |
0a613259 | 353 | |
7a78ae4e | 354 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 355 | |
7a78ae4e ND |
356 | static CORE_ADDR |
357 | read_memory_addr (CORE_ADDR memaddr, int len) | |
358 | { | |
359 | return read_memory_unsigned_integer (memaddr, len); | |
360 | } | |
c906108c | 361 | |
7a78ae4e ND |
362 | static CORE_ADDR |
363 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
364 | { |
365 | struct rs6000_framedata frame; | |
077276e8 | 366 | pc = skip_prologue (pc, 0, &frame); |
b83266a0 SS |
367 | return pc; |
368 | } | |
369 | ||
370 | ||
c906108c SS |
371 | /* Fill in fi->saved_regs */ |
372 | ||
373 | struct frame_extra_info | |
374 | { | |
375 | /* Functions calling alloca() change the value of the stack | |
376 | pointer. We need to use initial stack pointer (which is saved in | |
377 | r31 by gcc) in such cases. If a compiler emits traceback table, | |
378 | then we should use the alloca register specified in traceback | |
379 | table. FIXME. */ | |
c5aa993b | 380 | CORE_ADDR initial_sp; /* initial stack pointer. */ |
c906108c SS |
381 | }; |
382 | ||
143985b7 | 383 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 384 | static CORE_ADDR |
143985b7 AF |
385 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
386 | struct type *type) | |
387 | { | |
388 | CORE_ADDR addr; | |
7f5f525d | 389 | get_frame_register (frame, 3 + argi, &addr); |
143985b7 AF |
390 | return addr; |
391 | } | |
392 | ||
c906108c SS |
393 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
394 | ||
395 | static CORE_ADDR | |
7a78ae4e | 396 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
c906108c SS |
397 | { |
398 | CORE_ADDR dest; | |
399 | int immediate; | |
400 | int absolute; | |
401 | int ext_op; | |
402 | ||
403 | absolute = (int) ((instr >> 1) & 1); | |
404 | ||
c5aa993b JM |
405 | switch (opcode) |
406 | { | |
407 | case 18: | |
408 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
409 | if (absolute) | |
410 | dest = immediate; | |
411 | else | |
412 | dest = pc + immediate; | |
413 | break; | |
414 | ||
415 | case 16: | |
416 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
417 | if (absolute) | |
418 | dest = immediate; | |
419 | else | |
420 | dest = pc + immediate; | |
421 | break; | |
422 | ||
423 | case 19: | |
424 | ext_op = (instr >> 1) & 0x3ff; | |
425 | ||
426 | if (ext_op == 16) /* br conditional register */ | |
427 | { | |
2188cbdd | 428 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
429 | |
430 | /* If we are about to return from a signal handler, dest is | |
431 | something like 0x3c90. The current frame is a signal handler | |
432 | caller frame, upon completion of the sigreturn system call | |
433 | execution will return to the saved PC in the frame. */ | |
434 | if (dest < TEXT_SEGMENT_BASE) | |
435 | { | |
436 | struct frame_info *fi; | |
437 | ||
438 | fi = get_current_frame (); | |
439 | if (fi != NULL) | |
8b36eed8 | 440 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
21283beb | 441 | gdbarch_tdep (current_gdbarch)->wordsize); |
c5aa993b JM |
442 | } |
443 | } | |
444 | ||
445 | else if (ext_op == 528) /* br cond to count reg */ | |
446 | { | |
2188cbdd | 447 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
448 | |
449 | /* If we are about to execute a system call, dest is something | |
450 | like 0x22fc or 0x3b00. Upon completion the system call | |
451 | will return to the address in the link register. */ | |
452 | if (dest < TEXT_SEGMENT_BASE) | |
2188cbdd | 453 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
454 | } |
455 | else | |
456 | return -1; | |
457 | break; | |
c906108c | 458 | |
c5aa993b JM |
459 | default: |
460 | return -1; | |
461 | } | |
c906108c SS |
462 | return (dest < TEXT_SEGMENT_BASE) ? safety : dest; |
463 | } | |
464 | ||
465 | ||
466 | /* Sequence of bytes for breakpoint instruction. */ | |
467 | ||
f4f9705a | 468 | const static unsigned char * |
7a78ae4e | 469 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 470 | { |
aaab4dba AC |
471 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
472 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 473 | *bp_size = 4; |
d7449b42 | 474 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
475 | return big_breakpoint; |
476 | else | |
477 | return little_breakpoint; | |
478 | } | |
479 | ||
480 | ||
481 | /* AIX does not support PT_STEP. Simulate it. */ | |
482 | ||
483 | void | |
379d08a1 AC |
484 | rs6000_software_single_step (enum target_signal signal, |
485 | int insert_breakpoints_p) | |
c906108c | 486 | { |
7c40d541 KB |
487 | CORE_ADDR dummy; |
488 | int breakp_sz; | |
f4f9705a | 489 | const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
490 | int ii, insn; |
491 | CORE_ADDR loc; | |
492 | CORE_ADDR breaks[2]; | |
493 | int opcode; | |
494 | ||
c5aa993b JM |
495 | if (insert_breakpoints_p) |
496 | { | |
c906108c | 497 | |
c5aa993b | 498 | loc = read_pc (); |
c906108c | 499 | |
c5aa993b | 500 | insn = read_memory_integer (loc, 4); |
c906108c | 501 | |
7c40d541 | 502 | breaks[0] = loc + breakp_sz; |
c5aa993b JM |
503 | opcode = insn >> 26; |
504 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); | |
c906108c | 505 | |
c5aa993b JM |
506 | /* Don't put two breakpoints on the same address. */ |
507 | if (breaks[1] == breaks[0]) | |
508 | breaks[1] = -1; | |
c906108c | 509 | |
c5aa993b | 510 | stepBreaks[1].address = 0; |
c906108c | 511 | |
c5aa993b JM |
512 | for (ii = 0; ii < 2; ++ii) |
513 | { | |
c906108c | 514 | |
c5aa993b JM |
515 | /* ignore invalid breakpoint. */ |
516 | if (breaks[ii] == -1) | |
517 | continue; | |
7c40d541 | 518 | target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); |
c5aa993b JM |
519 | stepBreaks[ii].address = breaks[ii]; |
520 | } | |
c906108c | 521 | |
c5aa993b JM |
522 | } |
523 | else | |
524 | { | |
c906108c | 525 | |
c5aa993b JM |
526 | /* remove step breakpoints. */ |
527 | for (ii = 0; ii < 2; ++ii) | |
528 | if (stepBreaks[ii].address != 0) | |
7c40d541 KB |
529 | target_remove_breakpoint (stepBreaks[ii].address, |
530 | stepBreaks[ii].data); | |
c5aa993b | 531 | } |
c906108c | 532 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 533 | /* What errors? {read,write}_memory call error(). */ |
c906108c SS |
534 | } |
535 | ||
536 | ||
537 | /* return pc value after skipping a function prologue and also return | |
538 | information about a function frame. | |
539 | ||
540 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
541 | - frameless is TRUE, if function does not have a frame. |
542 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
543 | - offset is the initial size of this stack frame --- the amount by | |
544 | which we decrement the sp to allocate the frame. | |
545 | - saved_gpr is the number of the first saved gpr. | |
546 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 547 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 548 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
549 | - alloca_reg is the number of the register used for alloca() handling. |
550 | Otherwise -1. | |
551 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
552 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 553 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 554 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
555 | - lr_offset is the offset of the saved lr |
556 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 557 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 558 | */ |
c906108c SS |
559 | |
560 | #define SIGNED_SHORT(x) \ | |
561 | ((sizeof (short) == 2) \ | |
562 | ? ((int)(short)(x)) \ | |
563 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
564 | ||
565 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
566 | ||
55d05f3b KB |
567 | /* Limit the number of skipped non-prologue instructions, as the examining |
568 | of the prologue is expensive. */ | |
569 | static int max_skip_non_prologue_insns = 10; | |
570 | ||
571 | /* Given PC representing the starting address of a function, and | |
572 | LIM_PC which is the (sloppy) limit to which to scan when looking | |
573 | for a prologue, attempt to further refine this limit by using | |
574 | the line data in the symbol table. If successful, a better guess | |
575 | on where the prologue ends is returned, otherwise the previous | |
576 | value of lim_pc is returned. */ | |
634aa483 AC |
577 | |
578 | /* FIXME: cagney/2004-02-14: This function and logic have largely been | |
579 | superseded by skip_prologue_using_sal. */ | |
580 | ||
55d05f3b KB |
581 | static CORE_ADDR |
582 | refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) | |
583 | { | |
584 | struct symtab_and_line prologue_sal; | |
585 | ||
586 | prologue_sal = find_pc_line (pc, 0); | |
587 | if (prologue_sal.line != 0) | |
588 | { | |
589 | int i; | |
590 | CORE_ADDR addr = prologue_sal.end; | |
591 | ||
592 | /* Handle the case in which compiler's optimizer/scheduler | |
593 | has moved instructions into the prologue. We scan ahead | |
594 | in the function looking for address ranges whose corresponding | |
595 | line number is less than or equal to the first one that we | |
596 | found for the function. (It can be less than when the | |
597 | scheduler puts a body instruction before the first prologue | |
598 | instruction.) */ | |
599 | for (i = 2 * max_skip_non_prologue_insns; | |
600 | i > 0 && (lim_pc == 0 || addr < lim_pc); | |
601 | i--) | |
602 | { | |
603 | struct symtab_and_line sal; | |
604 | ||
605 | sal = find_pc_line (addr, 0); | |
606 | if (sal.line == 0) | |
607 | break; | |
608 | if (sal.line <= prologue_sal.line | |
609 | && sal.symtab == prologue_sal.symtab) | |
610 | { | |
611 | prologue_sal = sal; | |
612 | } | |
613 | addr = sal.end; | |
614 | } | |
615 | ||
616 | if (lim_pc == 0 || prologue_sal.end < lim_pc) | |
617 | lim_pc = prologue_sal.end; | |
618 | } | |
619 | return lim_pc; | |
620 | } | |
621 | ||
773df3e5 JB |
622 | /* Return nonzero if the given instruction OP can be part of the prologue |
623 | of a function and saves a parameter on the stack. FRAMEP should be | |
624 | set if one of the previous instructions in the function has set the | |
625 | Frame Pointer. */ | |
626 | ||
627 | static int | |
628 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
629 | { | |
630 | /* Move parameters from argument registers to temporary register. */ | |
631 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
632 | { | |
633 | /* Rx must be scratch register r0. */ | |
634 | const int rx_regno = (op >> 16) & 31; | |
635 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
636 | const int ry_regno = GET_SRC_REG (op); | |
637 | ||
638 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
639 | { | |
640 | *r0_contains_arg = 1; | |
641 | return 1; | |
642 | } | |
643 | else | |
644 | return 0; | |
645 | } | |
646 | ||
647 | /* Save a General Purpose Register on stack. */ | |
648 | ||
649 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
650 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
651 | { | |
652 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
653 | const int rx_regno = GET_SRC_REG (op); | |
654 | ||
655 | return (rx_regno >= 3 && rx_regno <= 10); | |
656 | } | |
657 | ||
658 | /* Save a General Purpose Register on stack via the Frame Pointer. */ | |
659 | ||
660 | if (framep && | |
661 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
662 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
663 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
664 | { | |
665 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
666 | However, the compiler sometimes uses r0 to hold an argument. */ | |
667 | const int rx_regno = GET_SRC_REG (op); | |
668 | ||
669 | return ((rx_regno >= 3 && rx_regno <= 10) | |
670 | || (rx_regno == 0 && *r0_contains_arg)); | |
671 | } | |
672 | ||
673 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
674 | { | |
675 | /* Only f2 - f8 are used for parameter passing. */ | |
676 | const int src_regno = GET_SRC_REG (op); | |
677 | ||
678 | return (src_regno >= 2 && src_regno <= 8); | |
679 | } | |
680 | ||
681 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
682 | { | |
683 | /* Only f2 - f8 are used for parameter passing. */ | |
684 | const int src_regno = GET_SRC_REG (op); | |
685 | ||
686 | return (src_regno >= 2 && src_regno <= 8); | |
687 | } | |
688 | ||
689 | /* Not an insn that saves a parameter on stack. */ | |
690 | return 0; | |
691 | } | |
55d05f3b | 692 | |
7a78ae4e | 693 | static CORE_ADDR |
077276e8 | 694 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
695 | { |
696 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 697 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 698 | CORE_ADDR li_found_pc = 0; |
c906108c SS |
699 | char buf[4]; |
700 | unsigned long op; | |
701 | long offset = 0; | |
6be8bc0c | 702 | long vr_saved_offset = 0; |
482ca3f5 KB |
703 | int lr_reg = -1; |
704 | int cr_reg = -1; | |
6be8bc0c | 705 | int vr_reg = -1; |
96ff0de4 EZ |
706 | int ev_reg = -1; |
707 | long ev_offset = 0; | |
6be8bc0c | 708 | int vrsave_reg = -1; |
c906108c SS |
709 | int reg; |
710 | int framep = 0; | |
711 | int minimal_toc_loaded = 0; | |
ddb20c56 | 712 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 713 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 714 | int r0_contains_arg = 0; |
96ff0de4 | 715 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 716 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
96ff0de4 | 717 | |
55d05f3b KB |
718 | /* Attempt to find the end of the prologue when no limit is specified. |
719 | Note that refine_prologue_limit() has been written so that it may | |
720 | be used to "refine" the limits of non-zero PC values too, but this | |
721 | is only safe if we 1) trust the line information provided by the | |
722 | compiler and 2) iterate enough to actually find the end of the | |
723 | prologue. | |
724 | ||
725 | It may become a good idea at some point (for both performance and | |
726 | accuracy) to unconditionally call refine_prologue_limit(). But, | |
727 | until we can make a clear determination that this is beneficial, | |
728 | we'll play it safe and only use it to obtain a limit when none | |
729 | has been specified. */ | |
730 | if (lim_pc == 0) | |
731 | lim_pc = refine_prologue_limit (pc, lim_pc); | |
c906108c | 732 | |
ddb20c56 | 733 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
734 | fdata->saved_gpr = -1; |
735 | fdata->saved_fpr = -1; | |
6be8bc0c | 736 | fdata->saved_vr = -1; |
96ff0de4 | 737 | fdata->saved_ev = -1; |
c906108c SS |
738 | fdata->alloca_reg = -1; |
739 | fdata->frameless = 1; | |
740 | fdata->nosavedpc = 1; | |
741 | ||
55d05f3b | 742 | for (;; pc += 4) |
c906108c | 743 | { |
ddb20c56 KB |
744 | /* Sometimes it isn't clear if an instruction is a prologue |
745 | instruction or not. When we encounter one of these ambiguous | |
746 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
747 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
748 | if (prev_insn_was_prologue_insn) | |
749 | last_prologue_pc = pc; | |
55d05f3b KB |
750 | |
751 | /* Stop scanning if we've hit the limit. */ | |
752 | if (lim_pc != 0 && pc >= lim_pc) | |
753 | break; | |
754 | ||
ddb20c56 KB |
755 | prev_insn_was_prologue_insn = 1; |
756 | ||
55d05f3b | 757 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
758 | if (target_read_memory (pc, buf, 4)) |
759 | break; | |
760 | op = extract_signed_integer (buf, 4); | |
c906108c | 761 | |
c5aa993b JM |
762 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
763 | { /* mflr Rx */ | |
43b1ab88 AC |
764 | /* Since shared library / PIC code, which needs to get its |
765 | address at runtime, can appear to save more than one link | |
766 | register vis: | |
767 | ||
768 | *INDENT-OFF* | |
769 | stwu r1,-304(r1) | |
770 | mflr r3 | |
771 | bl 0xff570d0 (blrl) | |
772 | stw r30,296(r1) | |
773 | mflr r30 | |
774 | stw r31,300(r1) | |
775 | stw r3,308(r1); | |
776 | ... | |
777 | *INDENT-ON* | |
778 | ||
779 | remember just the first one, but skip over additional | |
780 | ones. */ | |
781 | if (lr_reg < 0) | |
782 | lr_reg = (op & 0x03e00000); | |
773df3e5 JB |
783 | if (lr_reg == 0) |
784 | r0_contains_arg = 0; | |
c5aa993b | 785 | continue; |
c5aa993b JM |
786 | } |
787 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
788 | { /* mfcr Rx */ | |
98f08d3d | 789 | cr_reg = (op & 0x03e00000); |
773df3e5 JB |
790 | if (cr_reg == 0) |
791 | r0_contains_arg = 0; | |
c5aa993b | 792 | continue; |
c906108c | 793 | |
c906108c | 794 | } |
c5aa993b JM |
795 | else if ((op & 0xfc1f0000) == 0xd8010000) |
796 | { /* stfd Rx,NUM(r1) */ | |
797 | reg = GET_SRC_REG (op); | |
798 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
799 | { | |
800 | fdata->saved_fpr = reg; | |
801 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
802 | } | |
803 | continue; | |
c906108c | 804 | |
c5aa993b JM |
805 | } |
806 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
807 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
808 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
809 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
810 | { |
811 | ||
812 | reg = GET_SRC_REG (op); | |
813 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
814 | { | |
815 | fdata->saved_gpr = reg; | |
7a78ae4e | 816 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 817 | op &= ~3UL; |
c5aa993b JM |
818 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
819 | } | |
820 | continue; | |
c906108c | 821 | |
ddb20c56 KB |
822 | } |
823 | else if ((op & 0xffff0000) == 0x60000000) | |
824 | { | |
96ff0de4 | 825 | /* nop */ |
ddb20c56 KB |
826 | /* Allow nops in the prologue, but do not consider them to |
827 | be part of the prologue unless followed by other prologue | |
828 | instructions. */ | |
829 | prev_insn_was_prologue_insn = 0; | |
830 | continue; | |
831 | ||
c906108c | 832 | } |
c5aa993b JM |
833 | else if ((op & 0xffff0000) == 0x3c000000) |
834 | { /* addis 0,0,NUM, used | |
835 | for >= 32k frames */ | |
836 | fdata->offset = (op & 0x0000ffff) << 16; | |
837 | fdata->frameless = 0; | |
773df3e5 | 838 | r0_contains_arg = 0; |
c5aa993b JM |
839 | continue; |
840 | ||
841 | } | |
842 | else if ((op & 0xffff0000) == 0x60000000) | |
843 | { /* ori 0,0,NUM, 2nd ha | |
844 | lf of >= 32k frames */ | |
845 | fdata->offset |= (op & 0x0000ffff); | |
846 | fdata->frameless = 0; | |
773df3e5 | 847 | r0_contains_arg = 0; |
c5aa993b JM |
848 | continue; |
849 | ||
850 | } | |
98f08d3d KB |
851 | else if (lr_reg != -1 && |
852 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
853 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
854 | /* stw Rx, NUM(r1) */ | |
855 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
856 | /* stwu Rx, NUM(r1) */ | |
857 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
858 | { /* where Rx == lr */ | |
859 | fdata->lr_offset = offset; | |
c5aa993b JM |
860 | fdata->nosavedpc = 0; |
861 | lr_reg = 0; | |
98f08d3d KB |
862 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
863 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
864 | { | |
865 | /* Does not update r1, so add displacement to lr_offset. */ | |
866 | fdata->lr_offset += SIGNED_SHORT (op); | |
867 | } | |
c5aa993b JM |
868 | continue; |
869 | ||
870 | } | |
98f08d3d KB |
871 | else if (cr_reg != -1 && |
872 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
873 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
874 | /* stw Rx, NUM(r1) */ | |
875 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
876 | /* stwu Rx, NUM(r1) */ | |
877 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
878 | { /* where Rx == cr */ | |
879 | fdata->cr_offset = offset; | |
c5aa993b | 880 | cr_reg = 0; |
98f08d3d KB |
881 | if ((op & 0xfc000003) == 0xf8000000 || |
882 | (op & 0xfc000000) == 0x90000000) | |
883 | { | |
884 | /* Does not update r1, so add displacement to cr_offset. */ | |
885 | fdata->cr_offset += SIGNED_SHORT (op); | |
886 | } | |
c5aa993b JM |
887 | continue; |
888 | ||
889 | } | |
890 | else if (op == 0x48000005) | |
891 | { /* bl .+4 used in | |
892 | -mrelocatable */ | |
893 | continue; | |
894 | ||
895 | } | |
896 | else if (op == 0x48000004) | |
897 | { /* b .+4 (xlc) */ | |
898 | break; | |
899 | ||
c5aa993b | 900 | } |
6be8bc0c EZ |
901 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
902 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
903 | (op & 0xffff0000) == 0x3bde0000) |
904 | { /* addi 30,30,foo@l */ | |
905 | continue; | |
c906108c | 906 | |
c5aa993b JM |
907 | } |
908 | else if ((op & 0xfc000001) == 0x48000001) | |
909 | { /* bl foo, | |
910 | to save fprs??? */ | |
c906108c | 911 | |
c5aa993b | 912 | fdata->frameless = 0; |
6be8bc0c EZ |
913 | /* Don't skip over the subroutine call if it is not within |
914 | the first three instructions of the prologue. */ | |
c5aa993b JM |
915 | if ((pc - orig_pc) > 8) |
916 | break; | |
917 | ||
918 | op = read_memory_integer (pc + 4, 4); | |
919 | ||
6be8bc0c EZ |
920 | /* At this point, make sure this is not a trampoline |
921 | function (a function that simply calls another functions, | |
922 | and nothing else). If the next is not a nop, this branch | |
923 | was part of the function prologue. */ | |
c5aa993b JM |
924 | |
925 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
926 | break; /* don't skip over | |
927 | this branch */ | |
928 | continue; | |
929 | ||
c5aa993b | 930 | } |
98f08d3d KB |
931 | /* update stack pointer */ |
932 | else if ((op & 0xfc1f0000) == 0x94010000) | |
933 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
934 | fdata->frameless = 0; |
935 | fdata->offset = SIGNED_SHORT (op); | |
936 | offset = fdata->offset; | |
937 | continue; | |
c5aa993b | 938 | } |
98f08d3d KB |
939 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
940 | { /* stwux rX,r1,rY */ | |
941 | /* no way to figure out what r1 is going to be */ | |
942 | fdata->frameless = 0; | |
943 | offset = fdata->offset; | |
944 | continue; | |
945 | } | |
946 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
947 | { /* stdu rX,NUM(r1) */ | |
948 | fdata->frameless = 0; | |
949 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
950 | offset = fdata->offset; | |
951 | continue; | |
952 | } | |
953 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
954 | { /* stdux rX,r1,rY */ | |
955 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
956 | fdata->frameless = 0; |
957 | offset = fdata->offset; | |
958 | continue; | |
c5aa993b | 959 | } |
98f08d3d KB |
960 | /* Load up minimal toc pointer */ |
961 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ | |
962 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
c5aa993b | 963 | && !minimal_toc_loaded) |
98f08d3d | 964 | { |
c5aa993b JM |
965 | minimal_toc_loaded = 1; |
966 | continue; | |
967 | ||
f6077098 KB |
968 | /* move parameters from argument registers to local variable |
969 | registers */ | |
970 | } | |
971 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
972 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
973 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 974 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
975 | { |
976 | continue; | |
977 | ||
c5aa993b JM |
978 | /* store parameters in stack */ |
979 | } | |
e802b915 | 980 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 981 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
e802b915 | 982 | { |
c5aa993b JM |
983 | continue; |
984 | ||
985 | /* Set up frame pointer */ | |
986 | } | |
987 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
988 | || op == 0x7c3f0b78) | |
989 | { /* mr r31, r1 */ | |
990 | fdata->frameless = 0; | |
991 | framep = 1; | |
6f99cb26 | 992 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
993 | continue; |
994 | ||
995 | /* Another way to set up the frame pointer. */ | |
996 | } | |
997 | else if ((op & 0xfc1fffff) == 0x38010000) | |
998 | { /* addi rX, r1, 0x0 */ | |
999 | fdata->frameless = 0; | |
1000 | framep = 1; | |
6f99cb26 AC |
1001 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1002 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 1003 | continue; |
c5aa993b | 1004 | } |
6be8bc0c EZ |
1005 | /* AltiVec related instructions. */ |
1006 | /* Store the vrsave register (spr 256) in another register for | |
1007 | later manipulation, or load a register into the vrsave | |
1008 | register. 2 instructions are used: mfvrsave and | |
1009 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1010 | and mtspr SPR256, Rn. */ | |
1011 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1012 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1013 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1014 | { | |
1015 | vrsave_reg = GET_SRC_REG (op); | |
1016 | continue; | |
1017 | } | |
1018 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
1019 | { | |
1020 | continue; | |
1021 | } | |
1022 | /* Store the register where vrsave was saved to onto the stack: | |
1023 | rS is the register where vrsave was stored in a previous | |
1024 | instruction. */ | |
1025 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1026 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
1027 | { | |
1028 | if (vrsave_reg == GET_SRC_REG (op)) | |
1029 | { | |
1030 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1031 | vrsave_reg = -1; | |
1032 | } | |
1033 | continue; | |
1034 | } | |
1035 | /* Compute the new value of vrsave, by modifying the register | |
1036 | where vrsave was saved to. */ | |
1037 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
1038 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1039 | { | |
1040 | continue; | |
1041 | } | |
1042 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1043 | in a pair of insns to save the vector registers on the | |
1044 | stack. */ | |
1045 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1046 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1047 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
1048 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c | 1049 | { |
773df3e5 JB |
1050 | if ((op & 0xffff0000) == 0x38000000) |
1051 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1052 | li_found_pc = pc; |
1053 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 JB |
1054 | |
1055 | /* This insn by itself is not part of the prologue, unless | |
1056 | if part of the pair of insns mentioned above. So do not | |
1057 | record this insn as part of the prologue yet. */ | |
1058 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
1059 | } |
1060 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
1061 | /* 011111 sssss 11111 00000 00111001110 */ | |
1062 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
1063 | { | |
1064 | if (pc == (li_found_pc + 4)) | |
1065 | { | |
1066 | vr_reg = GET_SRC_REG (op); | |
1067 | /* If this is the first vector reg to be saved, or if | |
1068 | it has a lower number than others previously seen, | |
1069 | reupdate the frame info. */ | |
1070 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
1071 | { | |
1072 | fdata->saved_vr = vr_reg; | |
1073 | fdata->vr_offset = vr_saved_offset + offset; | |
1074 | } | |
1075 | vr_saved_offset = -1; | |
1076 | vr_reg = -1; | |
1077 | li_found_pc = 0; | |
1078 | } | |
1079 | } | |
1080 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
1081 | |
1082 | /* Start BookE related instructions. */ | |
1083 | /* Store gen register S at (r31+uimm). | |
1084 | Any register less than r13 is volatile, so we don't care. */ | |
1085 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
1086 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1087 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
1088 | { | |
1089 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
1090 | { | |
1091 | unsigned int imm; | |
1092 | ev_reg = GET_SRC_REG (op); | |
1093 | imm = (op >> 11) & 0x1f; | |
1094 | ev_offset = imm * 8; | |
1095 | /* If this is the first vector reg to be saved, or if | |
1096 | it has a lower number than others previously seen, | |
1097 | reupdate the frame info. */ | |
1098 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1099 | { | |
1100 | fdata->saved_ev = ev_reg; | |
1101 | fdata->ev_offset = ev_offset + offset; | |
1102 | } | |
1103 | } | |
1104 | continue; | |
1105 | } | |
1106 | /* Store gen register rS at (r1+rB). */ | |
1107 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1108 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1109 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1110 | { | |
1111 | if (pc == (li_found_pc + 4)) | |
1112 | { | |
1113 | ev_reg = GET_SRC_REG (op); | |
1114 | /* If this is the first vector reg to be saved, or if | |
1115 | it has a lower number than others previously seen, | |
1116 | reupdate the frame info. */ | |
1117 | /* We know the contents of rB from the previous instruction. */ | |
1118 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1119 | { | |
1120 | fdata->saved_ev = ev_reg; | |
1121 | fdata->ev_offset = vr_saved_offset + offset; | |
1122 | } | |
1123 | vr_saved_offset = -1; | |
1124 | ev_reg = -1; | |
1125 | li_found_pc = 0; | |
1126 | } | |
1127 | continue; | |
1128 | } | |
1129 | /* Store gen register r31 at (rA+uimm). */ | |
1130 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1131 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1132 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
1133 | { | |
1134 | /* Wwe know that the source register is 31 already, but | |
1135 | it can't hurt to compute it. */ | |
1136 | ev_reg = GET_SRC_REG (op); | |
1137 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
1138 | /* If this is the first vector reg to be saved, or if | |
1139 | it has a lower number than others previously seen, | |
1140 | reupdate the frame info. */ | |
1141 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1142 | { | |
1143 | fdata->saved_ev = ev_reg; | |
1144 | fdata->ev_offset = ev_offset + offset; | |
1145 | } | |
1146 | ||
1147 | continue; | |
1148 | } | |
1149 | /* Store gen register S at (r31+r0). | |
1150 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
1151 | /* 000100 sssss 11111 00000 01100100000 */ | |
1152 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1153 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
1154 | { | |
1155 | if (pc == (li_found_pc + 4)) | |
1156 | { | |
1157 | if ((op & 0x03e00000) >= 0x01a00000) | |
1158 | { | |
1159 | ev_reg = GET_SRC_REG (op); | |
1160 | /* If this is the first vector reg to be saved, or if | |
1161 | it has a lower number than others previously seen, | |
1162 | reupdate the frame info. */ | |
1163 | /* We know the contents of r0 from the previous | |
1164 | instruction. */ | |
1165 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1166 | { | |
1167 | fdata->saved_ev = ev_reg; | |
1168 | fdata->ev_offset = vr_saved_offset + offset; | |
1169 | } | |
1170 | ev_reg = -1; | |
1171 | } | |
1172 | vr_saved_offset = -1; | |
1173 | li_found_pc = 0; | |
1174 | continue; | |
1175 | } | |
1176 | } | |
1177 | /* End BookE related instructions. */ | |
1178 | ||
c5aa993b JM |
1179 | else |
1180 | { | |
55d05f3b KB |
1181 | /* Not a recognized prologue instruction. |
1182 | Handle optimizer code motions into the prologue by continuing | |
1183 | the search if we have no valid frame yet or if the return | |
1184 | address is not yet saved in the frame. */ | |
1185 | if (fdata->frameless == 0 | |
1186 | && (lr_reg == -1 || fdata->nosavedpc == 0)) | |
1187 | break; | |
1188 | ||
1189 | if (op == 0x4e800020 /* blr */ | |
1190 | || op == 0x4e800420) /* bctr */ | |
1191 | /* Do not scan past epilogue in frameless functions or | |
1192 | trampolines. */ | |
1193 | break; | |
1194 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 1195 | /* Never skip branches. */ |
55d05f3b KB |
1196 | break; |
1197 | ||
1198 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
1199 | /* Do not scan too many insns, scanning insns is expensive with | |
1200 | remote targets. */ | |
1201 | break; | |
1202 | ||
1203 | /* Continue scanning. */ | |
1204 | prev_insn_was_prologue_insn = 0; | |
1205 | continue; | |
c5aa993b | 1206 | } |
c906108c SS |
1207 | } |
1208 | ||
1209 | #if 0 | |
1210 | /* I have problems with skipping over __main() that I need to address | |
1211 | * sometime. Previously, I used to use misc_function_vector which | |
1212 | * didn't work as well as I wanted to be. -MGO */ | |
1213 | ||
1214 | /* If the first thing after skipping a prolog is a branch to a function, | |
1215 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 1216 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 1217 | work before calling a function right after a prologue, thus we can |
64366f1c | 1218 | single out such gcc2 behaviour. */ |
c906108c | 1219 | |
c906108c | 1220 | |
c5aa993b JM |
1221 | if ((op & 0xfc000001) == 0x48000001) |
1222 | { /* bl foo, an initializer function? */ | |
1223 | op = read_memory_integer (pc + 4, 4); | |
1224 | ||
1225 | if (op == 0x4def7b82) | |
1226 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 1227 | |
64366f1c EZ |
1228 | /* Check and see if we are in main. If so, skip over this |
1229 | initializer function as well. */ | |
c906108c | 1230 | |
c5aa993b | 1231 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
1232 | if (tmp >= 0 |
1233 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
1234 | return pc + 8; |
1235 | } | |
c906108c | 1236 | } |
c906108c | 1237 | #endif /* 0 */ |
c5aa993b JM |
1238 | |
1239 | fdata->offset = -fdata->offset; | |
ddb20c56 | 1240 | return last_prologue_pc; |
c906108c SS |
1241 | } |
1242 | ||
1243 | ||
1244 | /************************************************************************* | |
f6077098 | 1245 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
1246 | frames, etc. |
1247 | *************************************************************************/ | |
1248 | ||
c906108c | 1249 | |
11269d7e AC |
1250 | /* All the ABI's require 16 byte alignment. */ |
1251 | static CORE_ADDR | |
1252 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1253 | { | |
1254 | return (addr & -16); | |
1255 | } | |
1256 | ||
7a78ae4e | 1257 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1258 | the first eight words of the argument list (that might be less than |
1259 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1260 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1261 | passed in fpr's, in addition to that. Rest of the parameters if any |
1262 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1263 | parameter is copied into registers, the other half is pushed into |
1264 | stack. | |
1265 | ||
7a78ae4e ND |
1266 | Stack must be aligned on 64-bit boundaries when synthesizing |
1267 | function calls. | |
1268 | ||
c906108c SS |
1269 | If the function is returning a structure, then the return address is passed |
1270 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1271 | starting from r4. */ |
c906108c | 1272 | |
7a78ae4e | 1273 | static CORE_ADDR |
77b2b6d4 AC |
1274 | rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1275 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1276 | int nargs, struct value **args, CORE_ADDR sp, | |
1277 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1278 | { |
7a41266b | 1279 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
1280 | int ii; |
1281 | int len = 0; | |
c5aa993b JM |
1282 | int argno; /* current argument number */ |
1283 | int argbytes; /* current argument byte */ | |
1284 | char tmp_buffer[50]; | |
1285 | int f_argno = 0; /* current floating point argno */ | |
21283beb | 1286 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c | 1287 | |
ea7c478f | 1288 | struct value *arg = 0; |
c906108c SS |
1289 | struct type *type; |
1290 | ||
1291 | CORE_ADDR saved_sp; | |
1292 | ||
383f0f5b JB |
1293 | /* The calling convention this function implements assumes the |
1294 | processor has floating-point registers. We shouldn't be using it | |
1295 | on PPC variants that lack them. */ | |
1296 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1297 | ||
64366f1c | 1298 | /* The first eight words of ther arguments are passed in registers. |
7a41266b AC |
1299 | Copy them appropriately. */ |
1300 | ii = 0; | |
1301 | ||
1302 | /* If the function is returning a `struct', then the first word | |
1303 | (which will be passed in r3) is used for struct return address. | |
1304 | In that case we should advance one word and start from r4 | |
1305 | register to copy parameters. */ | |
1306 | if (struct_return) | |
1307 | { | |
1308 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1309 | struct_addr); | |
1310 | ii++; | |
1311 | } | |
c906108c SS |
1312 | |
1313 | /* | |
c5aa993b JM |
1314 | effectively indirect call... gcc does... |
1315 | ||
1316 | return_val example( float, int); | |
1317 | ||
1318 | eabi: | |
1319 | float in fp0, int in r3 | |
1320 | offset of stack on overflow 8/16 | |
1321 | for varargs, must go by type. | |
1322 | power open: | |
1323 | float in r3&r4, int in r5 | |
1324 | offset of stack on overflow different | |
1325 | both: | |
1326 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1327 | pay attention to arg promotion. | |
1328 | User may have to cast\args to handle promotion correctly | |
1329 | since gdb won't know if prototype supplied or not. | |
1330 | */ | |
c906108c | 1331 | |
c5aa993b JM |
1332 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1333 | { | |
12c266ea | 1334 | int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3); |
c5aa993b JM |
1335 | |
1336 | arg = args[argno]; | |
1337 | type = check_typedef (VALUE_TYPE (arg)); | |
1338 | len = TYPE_LENGTH (type); | |
1339 | ||
1340 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1341 | { | |
1342 | ||
64366f1c | 1343 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1344 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1345 | there is no way we would run out of them. */ |
c5aa993b JM |
1346 | |
1347 | if (len > 8) | |
c2b6b4aa JB |
1348 | printf_unfiltered ("Fatal Error: a floating point parameter " |
1349 | "#%d with a size > 8 is found!\n", argno); | |
c5aa993b | 1350 | |
366f009f JB |
1351 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE |
1352 | (tdep->ppc_fp0_regnum + 1 + f_argno)], | |
c5aa993b JM |
1353 | VALUE_CONTENTS (arg), |
1354 | len); | |
1355 | ++f_argno; | |
1356 | } | |
1357 | ||
f6077098 | 1358 | if (len > reg_size) |
c5aa993b JM |
1359 | { |
1360 | ||
64366f1c | 1361 | /* Argument takes more than one register. */ |
c5aa993b JM |
1362 | while (argbytes < len) |
1363 | { | |
62700349 | 1364 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, |
524d7c18 | 1365 | reg_size); |
62700349 | 1366 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], |
c5aa993b | 1367 | ((char *) VALUE_CONTENTS (arg)) + argbytes, |
f6077098 KB |
1368 | (len - argbytes) > reg_size |
1369 | ? reg_size : len - argbytes); | |
1370 | ++ii, argbytes += reg_size; | |
c5aa993b JM |
1371 | |
1372 | if (ii >= 8) | |
1373 | goto ran_out_of_registers_for_arguments; | |
1374 | } | |
1375 | argbytes = 0; | |
1376 | --ii; | |
1377 | } | |
1378 | else | |
64366f1c EZ |
1379 | { |
1380 | /* Argument can fit in one register. No problem. */ | |
d7449b42 | 1381 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
62700349 AC |
1382 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size); |
1383 | memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj, | |
f6077098 | 1384 | VALUE_CONTENTS (arg), len); |
c5aa993b JM |
1385 | } |
1386 | ++argno; | |
c906108c | 1387 | } |
c906108c SS |
1388 | |
1389 | ran_out_of_registers_for_arguments: | |
1390 | ||
7a78ae4e | 1391 | saved_sp = read_sp (); |
cc9836a8 | 1392 | |
64366f1c | 1393 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1394 | sp -= wordsize * 8; |
f6077098 | 1395 | |
64366f1c | 1396 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1397 | sp -= wordsize * 6; |
f6077098 | 1398 | |
64366f1c | 1399 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1400 | sp &= -16; |
c906108c | 1401 | |
64366f1c EZ |
1402 | /* If there are more arguments, allocate space for them in |
1403 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1404 | |
c5aa993b JM |
1405 | if ((argno < nargs) || argbytes) |
1406 | { | |
1407 | int space = 0, jj; | |
c906108c | 1408 | |
c5aa993b JM |
1409 | if (argbytes) |
1410 | { | |
1411 | space += ((len - argbytes + 3) & -4); | |
1412 | jj = argno + 1; | |
1413 | } | |
1414 | else | |
1415 | jj = argno; | |
c906108c | 1416 | |
c5aa993b JM |
1417 | for (; jj < nargs; ++jj) |
1418 | { | |
ea7c478f | 1419 | struct value *val = args[jj]; |
c5aa993b JM |
1420 | space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; |
1421 | } | |
c906108c | 1422 | |
64366f1c | 1423 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1424 | space = (space + 15) & -16; |
c5aa993b | 1425 | sp -= space; |
c906108c | 1426 | |
7aea86e6 AC |
1427 | /* This is another instance we need to be concerned about |
1428 | securing our stack space. If we write anything underneath %sp | |
1429 | (r1), we might conflict with the kernel who thinks he is free | |
1430 | to use this area. So, update %sp first before doing anything | |
1431 | else. */ | |
1432 | ||
1433 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); | |
1434 | ||
64366f1c EZ |
1435 | /* If the last argument copied into the registers didn't fit there |
1436 | completely, push the rest of it into stack. */ | |
c906108c | 1437 | |
c5aa993b JM |
1438 | if (argbytes) |
1439 | { | |
1440 | write_memory (sp + 24 + (ii * 4), | |
1441 | ((char *) VALUE_CONTENTS (arg)) + argbytes, | |
1442 | len - argbytes); | |
1443 | ++argno; | |
1444 | ii += ((len - argbytes + 3) & -4) / 4; | |
1445 | } | |
c906108c | 1446 | |
64366f1c | 1447 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1448 | for (; argno < nargs; ++argno) |
1449 | { | |
c906108c | 1450 | |
c5aa993b JM |
1451 | arg = args[argno]; |
1452 | type = check_typedef (VALUE_TYPE (arg)); | |
1453 | len = TYPE_LENGTH (type); | |
c906108c SS |
1454 | |
1455 | ||
64366f1c EZ |
1456 | /* Float types should be passed in fpr's, as well as in the |
1457 | stack. */ | |
c5aa993b JM |
1458 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1459 | { | |
c906108c | 1460 | |
c5aa993b | 1461 | if (len > 8) |
c2b6b4aa JB |
1462 | printf_unfiltered ("Fatal Error: a floating point parameter" |
1463 | " #%d with a size > 8 is found!\n", argno); | |
c906108c | 1464 | |
366f009f JB |
1465 | memcpy (&(deprecated_registers |
1466 | [DEPRECATED_REGISTER_BYTE | |
1467 | (tdep->ppc_fp0_regnum + 1 + f_argno)]), | |
c5aa993b JM |
1468 | VALUE_CONTENTS (arg), |
1469 | len); | |
1470 | ++f_argno; | |
1471 | } | |
c906108c | 1472 | |
c2b6b4aa JB |
1473 | write_memory (sp + 24 + (ii * 4), |
1474 | (char *) VALUE_CONTENTS (arg), | |
1475 | len); | |
c5aa993b JM |
1476 | ii += ((len + 3) & -4) / 4; |
1477 | } | |
c906108c | 1478 | } |
c906108c | 1479 | |
69517000 | 1480 | /* Set the stack pointer. According to the ABI, the SP is meant to |
7aea86e6 AC |
1481 | be set _before_ the corresponding stack space is used. On AIX, |
1482 | this even applies when the target has been completely stopped! | |
1483 | Not doing this can lead to conflicts with the kernel which thinks | |
1484 | that it still has control over this not-yet-allocated stack | |
1485 | region. */ | |
33a7c2fc AC |
1486 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); |
1487 | ||
7aea86e6 AC |
1488 | /* Set back chain properly. */ |
1489 | store_unsigned_integer (tmp_buffer, 4, saved_sp); | |
1490 | write_memory (sp, tmp_buffer, 4); | |
1491 | ||
e56a0ecc AC |
1492 | /* Point the inferior function call's return address at the dummy's |
1493 | breakpoint. */ | |
1494 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); | |
1495 | ||
794a477a AC |
1496 | /* Set the TOC register, get the value from the objfile reader |
1497 | which, in turn, gets it from the VMAP table. */ | |
1498 | if (rs6000_find_toc_address_hook != NULL) | |
1499 | { | |
1500 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); | |
1501 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); | |
1502 | } | |
1503 | ||
c906108c SS |
1504 | target_store_registers (-1); |
1505 | return sp; | |
1506 | } | |
c906108c | 1507 | |
b9ff3018 AC |
1508 | /* PowerOpen always puts structures in memory. Vectors, which were |
1509 | added later, do get returned in a register though. */ | |
1510 | ||
1511 | static int | |
1512 | rs6000_use_struct_convention (int gcc_p, struct type *value_type) | |
1513 | { | |
1514 | if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8) | |
1515 | && TYPE_VECTOR (value_type)) | |
1516 | return 0; | |
1517 | return 1; | |
1518 | } | |
1519 | ||
7a78ae4e ND |
1520 | static void |
1521 | rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) | |
c906108c SS |
1522 | { |
1523 | int offset = 0; | |
ace1378a | 1524 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1525 | |
383f0f5b JB |
1526 | /* The calling convention this function implements assumes the |
1527 | processor has floating-point registers. We shouldn't be using it | |
1528 | on PPC variants that lack them. */ | |
1529 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1530 | ||
c5aa993b JM |
1531 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT) |
1532 | { | |
c906108c | 1533 | |
c5aa993b JM |
1534 | /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. |
1535 | We need to truncate the return value into float size (4 byte) if | |
64366f1c | 1536 | necessary. */ |
c906108c | 1537 | |
65951cd9 | 1538 | convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE |
366f009f | 1539 | (tdep->ppc_fp0_regnum + 1)], |
65951cd9 JG |
1540 | builtin_type_double, |
1541 | valbuf, | |
1542 | valtype); | |
c5aa993b | 1543 | } |
ace1378a EZ |
1544 | else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY |
1545 | && TYPE_LENGTH (valtype) == 16 | |
1546 | && TYPE_VECTOR (valtype)) | |
1547 | { | |
62700349 | 1548 | memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
ace1378a EZ |
1549 | TYPE_LENGTH (valtype)); |
1550 | } | |
c5aa993b JM |
1551 | else |
1552 | { | |
1553 | /* return value is copied starting from r3. */ | |
d7449b42 | 1554 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
12c266ea AC |
1555 | && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3)) |
1556 | offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype); | |
c5aa993b JM |
1557 | |
1558 | memcpy (valbuf, | |
62700349 | 1559 | regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, |
c906108c | 1560 | TYPE_LENGTH (valtype)); |
c906108c | 1561 | } |
c906108c SS |
1562 | } |
1563 | ||
977adac5 ND |
1564 | /* Return whether handle_inferior_event() should proceed through code |
1565 | starting at PC in function NAME when stepping. | |
1566 | ||
1567 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1568 | handle memory references that are too distant to fit in instructions | |
1569 | generated by the compiler. For example, if 'foo' in the following | |
1570 | instruction: | |
1571 | ||
1572 | lwz r9,foo(r2) | |
1573 | ||
1574 | is greater than 32767, the linker might replace the lwz with a branch to | |
1575 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1576 | back to where execution should continue. | |
1577 | ||
1578 | GDB should silently step over @FIX code, just like AIX dbx does. | |
1579 | Unfortunately, the linker uses the "b" instruction for the branches, | |
1580 | meaning that the link register doesn't get set. Therefore, GDB's usual | |
1581 | step_over_function() mechanism won't work. | |
1582 | ||
1583 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks | |
1584 | in handle_inferior_event() to skip past @FIX code. */ | |
1585 | ||
1586 | int | |
1587 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1588 | { | |
1589 | return name && !strncmp (name, "@FIX", 4); | |
1590 | } | |
1591 | ||
1592 | /* Skip code that the user doesn't want to see when stepping: | |
1593 | ||
1594 | 1. Indirect function calls use a piece of trampoline code to do context | |
1595 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1596 | its first instruction (as when we have single-stepped to here). | |
1597 | ||
1598 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1599 | indirect function call trampolines). |
977adac5 ND |
1600 | |
1601 | 3. Skip bigtoc fixup code. | |
1602 | ||
c906108c | 1603 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1604 | code that should be skipped. */ |
c906108c SS |
1605 | |
1606 | CORE_ADDR | |
7a78ae4e | 1607 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
c906108c | 1608 | { |
52f0bd74 | 1609 | unsigned int ii, op; |
977adac5 | 1610 | int rel; |
c906108c | 1611 | CORE_ADDR solib_target_pc; |
977adac5 | 1612 | struct minimal_symbol *msymbol; |
c906108c | 1613 | |
c5aa993b JM |
1614 | static unsigned trampoline_code[] = |
1615 | { | |
1616 | 0x800b0000, /* l r0,0x0(r11) */ | |
1617 | 0x90410014, /* st r2,0x14(r1) */ | |
1618 | 0x7c0903a6, /* mtctr r0 */ | |
1619 | 0x804b0004, /* l r2,0x4(r11) */ | |
1620 | 0x816b0008, /* l r11,0x8(r11) */ | |
1621 | 0x4e800420, /* bctr */ | |
1622 | 0x4e800020, /* br */ | |
1623 | 0 | |
c906108c SS |
1624 | }; |
1625 | ||
977adac5 ND |
1626 | /* Check for bigtoc fixup code. */ |
1627 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
22abf04a | 1628 | if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) |
977adac5 ND |
1629 | { |
1630 | /* Double-check that the third instruction from PC is relative "b". */ | |
1631 | op = read_memory_integer (pc + 8, 4); | |
1632 | if ((op & 0xfc000003) == 0x48000000) | |
1633 | { | |
1634 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
1635 | add it to the containing PC. */ | |
1636 | rel = ((int)(op << 6) >> 6); | |
1637 | return pc + 8 + rel; | |
1638 | } | |
1639 | } | |
1640 | ||
c906108c SS |
1641 | /* If pc is in a shared library trampoline, return its target. */ |
1642 | solib_target_pc = find_solib_trampoline_target (pc); | |
1643 | if (solib_target_pc) | |
1644 | return solib_target_pc; | |
1645 | ||
c5aa993b JM |
1646 | for (ii = 0; trampoline_code[ii]; ++ii) |
1647 | { | |
1648 | op = read_memory_integer (pc + (ii * 4), 4); | |
1649 | if (op != trampoline_code[ii]) | |
1650 | return 0; | |
1651 | } | |
1652 | ii = read_register (11); /* r11 holds destination addr */ | |
21283beb | 1653 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
1654 | return pc; |
1655 | } | |
1656 | ||
7a78ae4e | 1657 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG |
64366f1c | 1658 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
1659 | |
1660 | static int | |
1661 | regsize (const struct reg *reg, int wordsize) | |
1662 | { | |
1663 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
1664 | } | |
1665 | ||
1666 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 1667 | in the current architecture. */ |
7a78ae4e | 1668 | |
fa88f677 | 1669 | static const char * |
7a78ae4e ND |
1670 | rs6000_register_name (int n) |
1671 | { | |
21283beb | 1672 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1673 | const struct reg *reg = tdep->regs + n; |
1674 | ||
1675 | if (!regsize (reg, tdep->wordsize)) | |
1676 | return NULL; | |
1677 | return reg->name; | |
1678 | } | |
1679 | ||
1680 | /* Index within `registers' of the first byte of the space for | |
1681 | register N. */ | |
1682 | ||
1683 | static int | |
1684 | rs6000_register_byte (int n) | |
1685 | { | |
21283beb | 1686 | return gdbarch_tdep (current_gdbarch)->regoff[n]; |
7a78ae4e ND |
1687 | } |
1688 | ||
1689 | /* Return the number of bytes of storage in the actual machine representation | |
64366f1c | 1690 | for register N if that register is available, else return 0. */ |
7a78ae4e ND |
1691 | |
1692 | static int | |
1693 | rs6000_register_raw_size (int n) | |
1694 | { | |
21283beb | 1695 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1696 | const struct reg *reg = tdep->regs + n; |
1697 | return regsize (reg, tdep->wordsize); | |
1698 | } | |
1699 | ||
7a78ae4e ND |
1700 | /* Return the GDB type object for the "standard" data type |
1701 | of data in register N. */ | |
1702 | ||
1703 | static struct type * | |
fba45db2 | 1704 | rs6000_register_virtual_type (int n) |
7a78ae4e | 1705 | { |
21283beb | 1706 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1707 | const struct reg *reg = tdep->regs + n; |
1708 | ||
1fcc0bb8 EZ |
1709 | if (reg->fpr) |
1710 | return builtin_type_double; | |
1711 | else | |
1712 | { | |
1713 | int size = regsize (reg, tdep->wordsize); | |
1714 | switch (size) | |
1715 | { | |
449a5da4 AC |
1716 | case 0: |
1717 | return builtin_type_int0; | |
1718 | case 4: | |
ed6edd9b | 1719 | return builtin_type_uint32; |
1fcc0bb8 | 1720 | case 8: |
c8001721 EZ |
1721 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
1722 | return builtin_type_vec64; | |
1723 | else | |
ed6edd9b | 1724 | return builtin_type_uint64; |
1fcc0bb8 EZ |
1725 | break; |
1726 | case 16: | |
08cf96df | 1727 | return builtin_type_vec128; |
1fcc0bb8 EZ |
1728 | break; |
1729 | default: | |
449a5da4 AC |
1730 | internal_error (__FILE__, __LINE__, "Register %d size %d unknown", |
1731 | n, size); | |
1fcc0bb8 EZ |
1732 | } |
1733 | } | |
7a78ae4e ND |
1734 | } |
1735 | ||
7a78ae4e ND |
1736 | /* Return whether register N requires conversion when moving from raw format |
1737 | to virtual format. | |
1738 | ||
1739 | The register format for RS/6000 floating point registers is always | |
64366f1c | 1740 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
1741 | |
1742 | static int | |
1743 | rs6000_register_convertible (int n) | |
1744 | { | |
21283beb | 1745 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n; |
7a78ae4e ND |
1746 | return reg->fpr; |
1747 | } | |
1748 | ||
1749 | /* Convert data from raw format for register N in buffer FROM | |
64366f1c | 1750 | to virtual format with type TYPE in buffer TO. */ |
7a78ae4e ND |
1751 | |
1752 | static void | |
1753 | rs6000_register_convert_to_virtual (int n, struct type *type, | |
1754 | char *from, char *to) | |
1755 | { | |
12c266ea | 1756 | if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) |
7a292a7a | 1757 | { |
12c266ea | 1758 | double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
f1908289 | 1759 | deprecated_store_floating (to, TYPE_LENGTH (type), val); |
7a78ae4e ND |
1760 | } |
1761 | else | |
12c266ea | 1762 | memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
7a78ae4e ND |
1763 | } |
1764 | ||
1765 | /* Convert data from virtual format with type TYPE in buffer FROM | |
64366f1c | 1766 | to raw format for register N in buffer TO. */ |
7a292a7a | 1767 | |
7a78ae4e ND |
1768 | static void |
1769 | rs6000_register_convert_to_raw (struct type *type, int n, | |
781a750d | 1770 | const char *from, char *to) |
7a78ae4e | 1771 | { |
12c266ea | 1772 | if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) |
7a78ae4e | 1773 | { |
f1908289 | 1774 | double val = deprecated_extract_floating (from, TYPE_LENGTH (type)); |
12c266ea | 1775 | deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val); |
7a292a7a | 1776 | } |
7a78ae4e | 1777 | else |
12c266ea | 1778 | memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
7a78ae4e | 1779 | } |
c906108c | 1780 | |
c8001721 EZ |
1781 | static void |
1782 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
1783 | int reg_nr, void *buffer) | |
1784 | { | |
1785 | int base_regnum; | |
1786 | int offset = 0; | |
d9d9c31f | 1787 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1788 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1789 | ||
1790 | if (reg_nr >= tdep->ppc_gp0_regnum | |
8bf659e8 | 1791 | && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs) |
c8001721 EZ |
1792 | { |
1793 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1794 | ||
1795 | /* Build the value in the provided buffer. */ | |
1796 | /* Read the raw register of which this one is the lower portion. */ | |
1797 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1798 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1799 | offset = 4; | |
1800 | memcpy ((char *) buffer, temp_buffer + offset, 4); | |
1801 | } | |
1802 | } | |
1803 | ||
1804 | static void | |
1805 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
1806 | int reg_nr, const void *buffer) | |
1807 | { | |
1808 | int base_regnum; | |
1809 | int offset = 0; | |
d9d9c31f | 1810 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1811 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1812 | ||
1813 | if (reg_nr >= tdep->ppc_gp0_regnum | |
8bf659e8 | 1814 | && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs) |
c8001721 EZ |
1815 | { |
1816 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1817 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
1818 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1819 | offset = 4; | |
1820 | ||
1821 | /* Let's read the value of the base register into a temporary | |
1822 | buffer, so that overwriting the last four bytes with the new | |
1823 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
1824 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1825 | ||
1826 | /* Write as an 8 byte quantity. */ | |
1827 | memcpy (temp_buffer + offset, (char *) buffer, 4); | |
1828 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1829 | } | |
1830 | } | |
1831 | ||
9f744501 JB |
1832 | /* Convert a dbx stab or Dwarf 2 register number (from `r' |
1833 | declaration) to a gdb REGNUM. */ | |
c8001721 | 1834 | static int |
9f744501 | 1835 | rs6000_dwarf2_stab_reg_to_regnum (int num) |
c8001721 | 1836 | { |
9f744501 | 1837 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c8001721 | 1838 | |
9f744501 JB |
1839 | if (0 <= num && num <= 31) |
1840 | return tdep->ppc_gp0_regnum + num; | |
1841 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
1842 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
1843 | specifies registers the architecture doesn't have? Our | |
1844 | callers don't check the value we return. */ | |
366f009f | 1845 | return tdep->ppc_fp0_regnum + (num - 32); |
9f744501 JB |
1846 | else if (1200 <= num && num < 1200 + 32) |
1847 | return tdep->ppc_ev0_regnum + (num - 1200); | |
1848 | else | |
1849 | switch (num) | |
1850 | { | |
1851 | case 64: | |
1852 | return tdep->ppc_mq_regnum; | |
1853 | case 65: | |
1854 | return tdep->ppc_lr_regnum; | |
1855 | case 66: | |
1856 | return tdep->ppc_ctr_regnum; | |
1857 | case 76: | |
1858 | return tdep->ppc_xer_regnum; | |
1859 | case 109: | |
1860 | return tdep->ppc_vrsave_regnum; | |
867e2dc5 JB |
1861 | case 111: |
1862 | return gdbarch_tdep (current_gdbarch)->ppc_acc_regnum; | |
1863 | case 112: | |
1864 | return gdbarch_tdep (current_gdbarch)->ppc_spefscr_regnum; | |
9f744501 JB |
1865 | default: |
1866 | return num; | |
1867 | } | |
1868 | ||
1869 | /* FIXME: jimb/2004-03-28: Doesn't something need to be done here | |
1870 | for the Altivec registers, too? | |
1871 | ||
1872 | Looking at GCC, the headers in config/rs6000 never define a | |
1873 | DBX_REGISTER_NUMBER macro, so the debug info uses the same | |
1874 | numbers GCC does internally. Then, looking at the REGISTER_NAMES | |
1875 | macro defined in config/rs6000/rs6000.h, it seems that GCC gives | |
1876 | v0 -- v31 the numbers 77 -- 108. But we number them 119 -- 150. | |
1877 | ||
1878 | I don't have a way to test this ready to hand, but I noticed it | |
1879 | and thought I should include a note. */ | |
2188cbdd EZ |
1880 | } |
1881 | ||
7a78ae4e ND |
1882 | static void |
1883 | rs6000_store_return_value (struct type *type, char *valbuf) | |
1884 | { | |
ace1378a EZ |
1885 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1886 | ||
383f0f5b JB |
1887 | /* The calling convention this function implements assumes the |
1888 | processor has floating-point registers. We shouldn't be using it | |
1889 | on PPC variants that lack them. */ | |
1890 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1891 | ||
7a78ae4e ND |
1892 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
1893 | ||
1894 | /* Floating point values are returned starting from FPR1 and up. | |
1895 | Say a double_double_double type could be returned in | |
64366f1c | 1896 | FPR1/FPR2/FPR3 triple. */ |
7a78ae4e | 1897 | |
366f009f JB |
1898 | deprecated_write_register_bytes |
1899 | (DEPRECATED_REGISTER_BYTE (tdep->ppc_fp0_regnum + 1), | |
1900 | valbuf, | |
1901 | TYPE_LENGTH (type)); | |
ace1378a EZ |
1902 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
1903 | { | |
1904 | if (TYPE_LENGTH (type) == 16 | |
1905 | && TYPE_VECTOR (type)) | |
62700349 | 1906 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
73937e03 | 1907 | valbuf, TYPE_LENGTH (type)); |
ace1378a | 1908 | } |
7a78ae4e | 1909 | else |
64366f1c | 1910 | /* Everything else is returned in GPR3 and up. */ |
62700349 | 1911 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3), |
73937e03 | 1912 | valbuf, TYPE_LENGTH (type)); |
7a78ae4e ND |
1913 | } |
1914 | ||
1915 | /* Extract from an array REGBUF containing the (raw) register state | |
1916 | the address in which a function should return its structure value, | |
1917 | as a CORE_ADDR (or an expression that can be used as one). */ | |
1918 | ||
1919 | static CORE_ADDR | |
11269d7e AC |
1920 | rs6000_extract_struct_value_address (struct regcache *regcache) |
1921 | { | |
1922 | /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior | |
1923 | function call GDB knows the address of the struct return value | |
1924 | and hence, should not need to call this function. Unfortunately, | |
e8a8712a AC |
1925 | the current call_function_by_hand() code only saves the most |
1926 | recent struct address leading to occasional calls. The code | |
1927 | should instead maintain a stack of such addresses (in the dummy | |
1928 | frame object). */ | |
11269d7e AC |
1929 | /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've |
1930 | really got no idea where the return value is being stored. While | |
1931 | r3, on function entry, contained the address it will have since | |
1932 | been reused (scratch) and hence wouldn't be valid */ | |
1933 | return 0; | |
7a78ae4e ND |
1934 | } |
1935 | ||
64366f1c | 1936 | /* Hook called when a new child process is started. */ |
7a78ae4e ND |
1937 | |
1938 | void | |
1939 | rs6000_create_inferior (int pid) | |
1940 | { | |
1941 | if (rs6000_set_host_arch_hook) | |
1942 | rs6000_set_host_arch_hook (pid); | |
c906108c SS |
1943 | } |
1944 | \f | |
e2d0e7eb | 1945 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
7a78ae4e ND |
1946 | |
1947 | Usually a function pointer's representation is simply the address | |
1948 | of the function. On the RS/6000 however, a function pointer is | |
1949 | represented by a pointer to a TOC entry. This TOC entry contains | |
1950 | three words, the first word is the address of the function, the | |
1951 | second word is the TOC pointer (r2), and the third word is the | |
1952 | static chain value. Throughout GDB it is currently assumed that a | |
1953 | function pointer contains the address of the function, which is not | |
1954 | easy to fix. In addition, the conversion of a function address to | |
1955 | a function pointer would require allocation of a TOC entry in the | |
1956 | inferior's memory space, with all its drawbacks. To be able to | |
1957 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 1958 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
1959 | function address from a function pointer. */ |
1960 | ||
f517ea4e PS |
1961 | /* Return real function address if ADDR (a function pointer) is in the data |
1962 | space and is therefore a special function pointer. */ | |
c906108c | 1963 | |
b9362cc7 | 1964 | static CORE_ADDR |
e2d0e7eb AC |
1965 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
1966 | CORE_ADDR addr, | |
1967 | struct target_ops *targ) | |
c906108c SS |
1968 | { |
1969 | struct obj_section *s; | |
1970 | ||
1971 | s = find_pc_section (addr); | |
1972 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 1973 | return addr; |
c906108c | 1974 | |
7a78ae4e | 1975 | /* ADDR is in the data space, so it's a special function pointer. */ |
21283beb | 1976 | return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); |
c906108c | 1977 | } |
c906108c | 1978 | \f |
c5aa993b | 1979 | |
7a78ae4e | 1980 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
1981 | |
1982 | ||
7a78ae4e ND |
1983 | /* The arrays here called registers_MUMBLE hold information about available |
1984 | registers. | |
c906108c SS |
1985 | |
1986 | For each family of PPC variants, I've tried to isolate out the | |
1987 | common registers and put them up front, so that as long as you get | |
1988 | the general family right, GDB will correctly identify the registers | |
1989 | common to that family. The common register sets are: | |
1990 | ||
1991 | For the 60x family: hid0 hid1 iabr dabr pir | |
1992 | ||
1993 | For the 505 and 860 family: eie eid nri | |
1994 | ||
1995 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
1996 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
1997 | pbu1 pbl2 pbu2 | |
c906108c SS |
1998 | |
1999 | Most of these register groups aren't anything formal. I arrived at | |
2000 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
2001 | processor. |
2002 | ||
2003 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
2004 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
2005 | for Power. For PowerPC, slot 70 was unused and was already in the | |
2006 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
2007 | slot 70 was being used for "mq", so the next available slot (71) | |
2008 | was chosen. It would have been nice to be able to make the | |
2009 | register numbers the same across processor cores, but this wasn't | |
2010 | possible without either 1) renumbering some registers for some | |
2011 | processors or 2) assigning fpscr to a really high slot that's | |
2012 | larger than any current register number. Doing (1) is bad because | |
2013 | existing stubs would break. Doing (2) is undesirable because it | |
2014 | would introduce a really large gap between fpscr and the rest of | |
2015 | the registers for most processors. */ | |
7a78ae4e | 2016 | |
64366f1c | 2017 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 2018 | |
64366f1c | 2019 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
2020 | |
2021 | #define STR(s) #s | |
2022 | ||
2023 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 2024 | and 64 bits on 64-bit systems. */ |
489461e2 | 2025 | #define R(name) { STR(name), 4, 8, 0, 0 } |
7a78ae4e ND |
2026 | |
2027 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 2028 | systems. */ |
489461e2 | 2029 | #define R4(name) { STR(name), 4, 4, 0, 0 } |
7a78ae4e ND |
2030 | |
2031 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 2032 | systems. */ |
489461e2 | 2033 | #define R8(name) { STR(name), 8, 8, 0, 0 } |
7a78ae4e | 2034 | |
1fcc0bb8 | 2035 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 2036 | systems. */ |
489461e2 | 2037 | #define R16(name) { STR(name), 16, 16, 0, 0 } |
1fcc0bb8 | 2038 | |
64366f1c | 2039 | /* Return a struct reg defining floating-point register NAME. */ |
489461e2 EZ |
2040 | #define F(name) { STR(name), 8, 8, 1, 0 } |
2041 | ||
64366f1c | 2042 | /* Return a struct reg defining a pseudo register NAME. */ |
489461e2 | 2043 | #define P(name) { STR(name), 4, 8, 0, 1} |
7a78ae4e ND |
2044 | |
2045 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 2046 | systems and that doesn't exist on 64-bit systems. */ |
489461e2 | 2047 | #define R32(name) { STR(name), 4, 0, 0, 0 } |
7a78ae4e ND |
2048 | |
2049 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 2050 | systems and that doesn't exist on 32-bit systems. */ |
489461e2 | 2051 | #define R64(name) { STR(name), 0, 8, 0, 0 } |
7a78ae4e | 2052 | |
64366f1c | 2053 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
489461e2 | 2054 | #define R0 { 0, 0, 0, 0, 0 } |
7a78ae4e ND |
2055 | |
2056 | /* UISA registers common across all architectures, including POWER. */ | |
2057 | ||
2058 | #define COMMON_UISA_REGS \ | |
2059 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2060 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2061 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2062 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2063 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
2064 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
2065 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
2066 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
2067 | /* 64 */ R(pc), R(ps) | |
2068 | ||
ebeac11a EZ |
2069 | #define COMMON_UISA_NOFP_REGS \ |
2070 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2071 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2072 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2073 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2074 | /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2075 | /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2076 | /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2077 | /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2078 | /* 64 */ R(pc), R(ps) | |
2079 | ||
7a78ae4e ND |
2080 | /* UISA-level SPRs for PowerPC. */ |
2081 | #define PPC_UISA_SPRS \ | |
e3f36dbd | 2082 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr) |
7a78ae4e | 2083 | |
c8001721 EZ |
2084 | /* UISA-level SPRs for PowerPC without floating point support. */ |
2085 | #define PPC_UISA_NOFP_SPRS \ | |
2086 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0 | |
2087 | ||
7a78ae4e ND |
2088 | /* Segment registers, for PowerPC. */ |
2089 | #define PPC_SEGMENT_REGS \ | |
2090 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
2091 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
2092 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
2093 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
2094 | ||
2095 | /* OEA SPRs for PowerPC. */ | |
2096 | #define PPC_OEA_SPRS \ | |
2097 | /* 87 */ R4(pvr), \ | |
2098 | /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \ | |
2099 | /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \ | |
2100 | /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \ | |
2101 | /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \ | |
2102 | /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \ | |
2103 | /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \ | |
2104 | /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \ | |
2105 | /* 116 */ R4(dec), R(dabr), R4(ear) | |
2106 | ||
64366f1c | 2107 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
2108 | #define PPC_ALTIVEC_REGS \ |
2109 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
2110 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
2111 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
2112 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
2113 | /*151*/R4(vscr), R4(vrsave) | |
2114 | ||
c8001721 EZ |
2115 | /* Vectors of hi-lo general purpose registers. */ |
2116 | #define PPC_EV_REGS \ | |
2117 | /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \ | |
2118 | /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \ | |
2119 | /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \ | |
2120 | /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31) | |
2121 | ||
2122 | /* Lower half of the EV registers. */ | |
2123 | #define PPC_GPRS_PSEUDO_REGS \ | |
2124 | /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \ | |
2125 | /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \ | |
2126 | /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \ | |
338ef23d | 2127 | /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31) |
c8001721 | 2128 | |
7a78ae4e | 2129 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2130 | user-level SPR's. */ |
7a78ae4e | 2131 | static const struct reg registers_power[] = |
c906108c | 2132 | { |
7a78ae4e | 2133 | COMMON_UISA_REGS, |
e3f36dbd KB |
2134 | /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq), |
2135 | /* 71 */ R4(fpscr) | |
c906108c SS |
2136 | }; |
2137 | ||
7a78ae4e | 2138 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2139 | view of the PowerPC. */ |
7a78ae4e | 2140 | static const struct reg registers_powerpc[] = |
c906108c | 2141 | { |
7a78ae4e | 2142 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2143 | PPC_UISA_SPRS, |
2144 | PPC_ALTIVEC_REGS | |
c906108c SS |
2145 | }; |
2146 | ||
ebeac11a EZ |
2147 | /* PowerPC UISA - a PPC processor as viewed by user-level |
2148 | code, but without floating point registers. */ | |
2149 | static const struct reg registers_powerpc_nofp[] = | |
2150 | { | |
2151 | COMMON_UISA_NOFP_REGS, | |
2152 | PPC_UISA_SPRS | |
2153 | }; | |
2154 | ||
64366f1c | 2155 | /* IBM PowerPC 403. */ |
7a78ae4e | 2156 | static const struct reg registers_403[] = |
c5aa993b | 2157 | { |
7a78ae4e ND |
2158 | COMMON_UISA_REGS, |
2159 | PPC_UISA_SPRS, | |
2160 | PPC_SEGMENT_REGS, | |
2161 | PPC_OEA_SPRS, | |
2162 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2163 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2164 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2165 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2166 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2167 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2) | |
c906108c SS |
2168 | }; |
2169 | ||
64366f1c | 2170 | /* IBM PowerPC 403GC. */ |
7a78ae4e | 2171 | static const struct reg registers_403GC[] = |
c5aa993b | 2172 | { |
7a78ae4e ND |
2173 | COMMON_UISA_REGS, |
2174 | PPC_UISA_SPRS, | |
2175 | PPC_SEGMENT_REGS, | |
2176 | PPC_OEA_SPRS, | |
2177 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2178 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2179 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2180 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2181 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2182 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2), | |
2183 | /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr), | |
2184 | /* 147 */ R(tbhu), R(tblu) | |
c906108c SS |
2185 | }; |
2186 | ||
64366f1c | 2187 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2188 | static const struct reg registers_505[] = |
c5aa993b | 2189 | { |
7a78ae4e ND |
2190 | COMMON_UISA_REGS, |
2191 | PPC_UISA_SPRS, | |
2192 | PPC_SEGMENT_REGS, | |
2193 | PPC_OEA_SPRS, | |
2194 | /* 119 */ R(eie), R(eid), R(nri) | |
c906108c SS |
2195 | }; |
2196 | ||
64366f1c | 2197 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2198 | static const struct reg registers_860[] = |
c5aa993b | 2199 | { |
7a78ae4e ND |
2200 | COMMON_UISA_REGS, |
2201 | PPC_UISA_SPRS, | |
2202 | PPC_SEGMENT_REGS, | |
2203 | PPC_OEA_SPRS, | |
2204 | /* 119 */ R(eie), R(eid), R(nri), R(cmpa), | |
2205 | /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr), | |
2206 | /* 127 */ R(der), R(counta), R(countb), R(cmpe), | |
2207 | /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1), | |
2208 | /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst), | |
2209 | /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr), | |
2210 | /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr), | |
2211 | /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc), | |
2212 | /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap), | |
2213 | /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn), | |
2214 | /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1), | |
2215 | /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1) | |
c906108c SS |
2216 | }; |
2217 | ||
7a78ae4e ND |
2218 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2219 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2220 | register is the stub's problem. */ |
7a78ae4e | 2221 | static const struct reg registers_601[] = |
c5aa993b | 2222 | { |
7a78ae4e ND |
2223 | COMMON_UISA_REGS, |
2224 | PPC_UISA_SPRS, | |
2225 | PPC_SEGMENT_REGS, | |
2226 | PPC_OEA_SPRS, | |
2227 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2228 | /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl) | |
c906108c SS |
2229 | }; |
2230 | ||
64366f1c | 2231 | /* Motorola PowerPC 602. */ |
7a78ae4e | 2232 | static const struct reg registers_602[] = |
c5aa993b | 2233 | { |
7a78ae4e ND |
2234 | COMMON_UISA_REGS, |
2235 | PPC_UISA_SPRS, | |
2236 | PPC_SEGMENT_REGS, | |
2237 | PPC_OEA_SPRS, | |
2238 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2239 | /* 123 */ R0, R(tcr), R(ibr), R(esassr), | |
2240 | /* 127 */ R(sebr), R(ser), R(sp), R(lt) | |
c906108c SS |
2241 | }; |
2242 | ||
64366f1c | 2243 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2244 | static const struct reg registers_603[] = |
c5aa993b | 2245 | { |
7a78ae4e ND |
2246 | COMMON_UISA_REGS, |
2247 | PPC_UISA_SPRS, | |
2248 | PPC_SEGMENT_REGS, | |
2249 | PPC_OEA_SPRS, | |
2250 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2251 | /* 123 */ R0, R(dmiss), R(dcmp), R(hash1), | |
2252 | /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa) | |
c906108c SS |
2253 | }; |
2254 | ||
64366f1c | 2255 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2256 | static const struct reg registers_604[] = |
c5aa993b | 2257 | { |
7a78ae4e ND |
2258 | COMMON_UISA_REGS, |
2259 | PPC_UISA_SPRS, | |
2260 | PPC_SEGMENT_REGS, | |
2261 | PPC_OEA_SPRS, | |
2262 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2263 | /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2), | |
2264 | /* 127 */ R(sia), R(sda) | |
c906108c SS |
2265 | }; |
2266 | ||
64366f1c | 2267 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2268 | static const struct reg registers_750[] = |
c5aa993b | 2269 | { |
7a78ae4e ND |
2270 | COMMON_UISA_REGS, |
2271 | PPC_UISA_SPRS, | |
2272 | PPC_SEGMENT_REGS, | |
2273 | PPC_OEA_SPRS, | |
2274 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2275 | /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2), | |
2276 | /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4), | |
2277 | /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia), | |
2278 | /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr), | |
2279 | /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3) | |
c906108c SS |
2280 | }; |
2281 | ||
2282 | ||
64366f1c | 2283 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2284 | static const struct reg registers_7400[] = |
2285 | { | |
2286 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2287 | COMMON_UISA_REGS, | |
13c7b1ca | 2288 | /* cr, lr, ctr, xer, fpscr */ |
1fcc0bb8 EZ |
2289 | PPC_UISA_SPRS, |
2290 | /* sr0-sr15 */ | |
2291 | PPC_SEGMENT_REGS, | |
2292 | PPC_OEA_SPRS, | |
2293 | /* vr0-vr31, vrsave, vscr */ | |
2294 | PPC_ALTIVEC_REGS | |
2295 | /* FIXME? Add more registers? */ | |
2296 | }; | |
2297 | ||
c8001721 EZ |
2298 | /* Motorola e500. */ |
2299 | static const struct reg registers_e500[] = | |
2300 | { | |
2301 | R(pc), R(ps), | |
2302 | /* cr, lr, ctr, xer, "" */ | |
2303 | PPC_UISA_NOFP_SPRS, | |
2304 | /* 7...38 */ | |
2305 | PPC_EV_REGS, | |
338ef23d AC |
2306 | R8(acc), R(spefscr), |
2307 | /* NOTE: Add new registers here the end of the raw register | |
2308 | list and just before the first pseudo register. */ | |
13c7b1ca | 2309 | /* 41...72 */ |
c8001721 EZ |
2310 | PPC_GPRS_PSEUDO_REGS |
2311 | }; | |
2312 | ||
c906108c | 2313 | /* Information about a particular processor variant. */ |
7a78ae4e | 2314 | |
c906108c | 2315 | struct variant |
c5aa993b JM |
2316 | { |
2317 | /* Name of this variant. */ | |
2318 | char *name; | |
c906108c | 2319 | |
c5aa993b JM |
2320 | /* English description of the variant. */ |
2321 | char *description; | |
c906108c | 2322 | |
64366f1c | 2323 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2324 | enum bfd_architecture arch; |
2325 | ||
64366f1c | 2326 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2327 | unsigned long mach; |
2328 | ||
489461e2 EZ |
2329 | /* Number of real registers. */ |
2330 | int nregs; | |
2331 | ||
2332 | /* Number of pseudo registers. */ | |
2333 | int npregs; | |
2334 | ||
2335 | /* Number of total registers (the sum of nregs and npregs). */ | |
2336 | int num_tot_regs; | |
2337 | ||
c5aa993b JM |
2338 | /* Table of register names; registers[R] is the name of the register |
2339 | number R. */ | |
7a78ae4e | 2340 | const struct reg *regs; |
c5aa993b | 2341 | }; |
c906108c | 2342 | |
489461e2 EZ |
2343 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2344 | ||
2345 | static int | |
2346 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2347 | { | |
2348 | int i; | |
2349 | int nregs = 0; | |
2350 | ||
2351 | for (i = 0; i < num_tot_regs; i++) | |
2352 | if (!reg_list[i].pseudo) | |
2353 | nregs++; | |
2354 | ||
2355 | return nregs; | |
2356 | } | |
2357 | ||
2358 | static int | |
2359 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2360 | { | |
2361 | int i; | |
2362 | int npregs = 0; | |
2363 | ||
2364 | for (i = 0; i < num_tot_regs; i++) | |
2365 | if (reg_list[i].pseudo) | |
2366 | npregs ++; | |
2367 | ||
2368 | return npregs; | |
2369 | } | |
c906108c | 2370 | |
c906108c SS |
2371 | /* Information in this table comes from the following web sites: |
2372 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2373 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2374 | ||
2375 | I'm sure I've got some of the variant descriptions not quite right. | |
2376 | Please report any inaccuracies you find to GDB's maintainer. | |
2377 | ||
2378 | If you add entries to this table, please be sure to allow the new | |
2379 | value as an argument to the --with-cpu flag, in configure.in. */ | |
2380 | ||
489461e2 | 2381 | static struct variant variants[] = |
c906108c | 2382 | { |
489461e2 | 2383 | |
7a78ae4e | 2384 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
2385 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
2386 | registers_powerpc}, | |
7a78ae4e | 2387 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
2388 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
2389 | registers_power}, | |
7a78ae4e | 2390 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
2391 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
2392 | registers_403}, | |
7a78ae4e | 2393 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
2394 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
2395 | registers_601}, | |
7a78ae4e | 2396 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
2397 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
2398 | registers_602}, | |
7a78ae4e | 2399 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
2400 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
2401 | registers_603}, | |
7a78ae4e | 2402 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
2403 | 604, -1, -1, tot_num_registers (registers_604), |
2404 | registers_604}, | |
7a78ae4e | 2405 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
2406 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
2407 | registers_403GC}, | |
7a78ae4e | 2408 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
2409 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
2410 | registers_505}, | |
7a78ae4e | 2411 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
2412 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
2413 | registers_860}, | |
7a78ae4e | 2414 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
2415 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
2416 | registers_750}, | |
1fcc0bb8 | 2417 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
2418 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
2419 | registers_7400}, | |
c8001721 EZ |
2420 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
2421 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
2422 | registers_e500}, | |
7a78ae4e | 2423 | |
5d57ee30 KB |
2424 | /* 64-bit */ |
2425 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
2426 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
2427 | registers_powerpc}, | |
7a78ae4e | 2428 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
2429 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
2430 | registers_powerpc}, | |
5d57ee30 | 2431 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
2432 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
2433 | registers_powerpc}, | |
7a78ae4e | 2434 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
2435 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
2436 | registers_powerpc}, | |
5d57ee30 | 2437 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
2438 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
2439 | registers_powerpc}, | |
5d57ee30 | 2440 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
2441 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
2442 | registers_powerpc}, | |
5d57ee30 | 2443 | |
64366f1c | 2444 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2445 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
2446 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
2447 | registers_power}, | |
7a78ae4e | 2448 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
2449 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
2450 | registers_power}, | |
7a78ae4e | 2451 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
2452 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
2453 | registers_power}, | |
7a78ae4e | 2454 | |
489461e2 | 2455 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
2456 | }; |
2457 | ||
64366f1c | 2458 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
2459 | |
2460 | static void | |
2461 | init_variants (void) | |
2462 | { | |
2463 | struct variant *v; | |
2464 | ||
2465 | for (v = variants; v->name; v++) | |
2466 | { | |
2467 | if (v->nregs == -1) | |
2468 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
2469 | if (v->npregs == -1) | |
2470 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
2471 | } | |
2472 | } | |
c906108c | 2473 | |
7a78ae4e | 2474 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2475 | MACH. If no such variant exists, return null. */ |
c906108c | 2476 | |
7a78ae4e ND |
2477 | static const struct variant * |
2478 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2479 | { |
7a78ae4e | 2480 | const struct variant *v; |
c5aa993b | 2481 | |
7a78ae4e ND |
2482 | for (v = variants; v->name; v++) |
2483 | if (arch == v->arch && mach == v->mach) | |
2484 | return v; | |
c906108c | 2485 | |
7a78ae4e | 2486 | return NULL; |
c906108c | 2487 | } |
9364a0ef EZ |
2488 | |
2489 | static int | |
2490 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2491 | { | |
2492 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2493 | return print_insn_big_powerpc (memaddr, info); | |
2494 | else | |
2495 | return print_insn_little_powerpc (memaddr, info); | |
2496 | } | |
7a78ae4e | 2497 | \f |
61a65099 KB |
2498 | static CORE_ADDR |
2499 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2500 | { | |
2501 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
2502 | } | |
2503 | ||
2504 | static struct frame_id | |
2505 | rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2506 | { | |
2507 | return frame_id_build (frame_unwind_register_unsigned (next_frame, | |
2508 | SP_REGNUM), | |
2509 | frame_pc_unwind (next_frame)); | |
2510 | } | |
2511 | ||
2512 | struct rs6000_frame_cache | |
2513 | { | |
2514 | CORE_ADDR base; | |
2515 | CORE_ADDR initial_sp; | |
2516 | struct trad_frame_saved_reg *saved_regs; | |
2517 | }; | |
2518 | ||
2519 | static struct rs6000_frame_cache * | |
2520 | rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2521 | { | |
2522 | struct rs6000_frame_cache *cache; | |
2523 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2524 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2525 | struct rs6000_framedata fdata; | |
2526 | int wordsize = tdep->wordsize; | |
2527 | ||
2528 | if ((*this_cache) != NULL) | |
2529 | return (*this_cache); | |
2530 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
2531 | (*this_cache) = cache; | |
2532 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2533 | ||
2534 | skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame), | |
2535 | &fdata); | |
2536 | ||
2537 | /* If there were any saved registers, figure out parent's stack | |
2538 | pointer. */ | |
2539 | /* The following is true only if the frame doesn't have a call to | |
2540 | alloca(), FIXME. */ | |
2541 | ||
2542 | if (fdata.saved_fpr == 0 | |
2543 | && fdata.saved_gpr == 0 | |
2544 | && fdata.saved_vr == 0 | |
2545 | && fdata.saved_ev == 0 | |
2546 | && fdata.lr_offset == 0 | |
2547 | && fdata.cr_offset == 0 | |
2548 | && fdata.vr_offset == 0 | |
2549 | && fdata.ev_offset == 0) | |
2550 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2551 | else | |
2552 | { | |
2553 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
2554 | address of the current frame. Things might be easier if the | |
2555 | ->frame pointed to the outer-most address of the frame. In | |
2556 | the mean time, the address of the prev frame is used as the | |
2557 | base address of this frame. */ | |
2558 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2559 | if (!fdata.frameless) | |
2560 | /* Frameless really means stackless. */ | |
2561 | cache->base = read_memory_addr (cache->base, wordsize); | |
2562 | } | |
2563 | trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base); | |
2564 | ||
2565 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
2566 | All fpr's from saved_fpr to fp31 are saved. */ | |
2567 | ||
2568 | if (fdata.saved_fpr >= 0) | |
2569 | { | |
2570 | int i; | |
2571 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
2572 | |
2573 | /* If skip_prologue says floating-point registers were saved, | |
2574 | but the current architecture has no floating-point registers, | |
2575 | then that's strange. But we have no indices to even record | |
2576 | the addresses under, so we just ignore it. */ | |
2577 | if (ppc_floating_point_unit_p (gdbarch)) | |
063715bf | 2578 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
383f0f5b JB |
2579 | { |
2580 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
2581 | fpr_addr += 8; | |
2582 | } | |
61a65099 KB |
2583 | } |
2584 | ||
2585 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
2586 | All gpr's from saved_gpr to gpr31 are saved. */ | |
2587 | ||
2588 | if (fdata.saved_gpr >= 0) | |
2589 | { | |
2590 | int i; | |
2591 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 2592 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 KB |
2593 | { |
2594 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
2595 | gpr_addr += wordsize; | |
2596 | } | |
2597 | } | |
2598 | ||
2599 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
2600 | All vr's from saved_vr to vr31 are saved. */ | |
2601 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
2602 | { | |
2603 | if (fdata.saved_vr >= 0) | |
2604 | { | |
2605 | int i; | |
2606 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
2607 | for (i = fdata.saved_vr; i < 32; i++) | |
2608 | { | |
2609 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
2610 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
2611 | } | |
2612 | } | |
2613 | } | |
2614 | ||
2615 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
2616 | All vr's from saved_ev to ev31 are saved. ????? */ | |
2617 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
2618 | { | |
2619 | if (fdata.saved_ev >= 0) | |
2620 | { | |
2621 | int i; | |
2622 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
063715bf | 2623 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 KB |
2624 | { |
2625 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
2626 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; | |
2627 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); | |
2628 | } | |
2629 | } | |
2630 | } | |
2631 | ||
2632 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
2633 | holds the CR. */ | |
2634 | if (fdata.cr_offset != 0) | |
2635 | cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; | |
2636 | ||
2637 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
2638 | holds the LR. */ | |
2639 | if (fdata.lr_offset != 0) | |
2640 | cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; | |
2641 | /* The PC is found in the link register. */ | |
2642 | cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum]; | |
2643 | ||
2644 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
2645 | holds the VRSAVE. */ | |
2646 | if (fdata.vrsave_offset != 0) | |
2647 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; | |
2648 | ||
2649 | if (fdata.alloca_reg < 0) | |
2650 | /* If no alloca register used, then fi->frame is the value of the | |
2651 | %sp for this frame, and it is good enough. */ | |
2652 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2653 | else | |
2654 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, | |
2655 | fdata.alloca_reg); | |
2656 | ||
2657 | return cache; | |
2658 | } | |
2659 | ||
2660 | static void | |
2661 | rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2662 | struct frame_id *this_id) | |
2663 | { | |
2664 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2665 | this_cache); | |
2666 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
2667 | } | |
2668 | ||
2669 | static void | |
2670 | rs6000_frame_prev_register (struct frame_info *next_frame, | |
2671 | void **this_cache, | |
2672 | int regnum, int *optimizedp, | |
2673 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2674 | int *realnump, void *valuep) | |
2675 | { | |
2676 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2677 | this_cache); | |
2678 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
2679 | optimizedp, lvalp, addrp, realnump, valuep); | |
2680 | } | |
2681 | ||
2682 | static const struct frame_unwind rs6000_frame_unwind = | |
2683 | { | |
2684 | NORMAL_FRAME, | |
2685 | rs6000_frame_this_id, | |
2686 | rs6000_frame_prev_register | |
2687 | }; | |
2688 | ||
2689 | static const struct frame_unwind * | |
2690 | rs6000_frame_sniffer (struct frame_info *next_frame) | |
2691 | { | |
2692 | return &rs6000_frame_unwind; | |
2693 | } | |
2694 | ||
2695 | \f | |
2696 | ||
2697 | static CORE_ADDR | |
2698 | rs6000_frame_base_address (struct frame_info *next_frame, | |
2699 | void **this_cache) | |
2700 | { | |
2701 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2702 | this_cache); | |
2703 | return info->initial_sp; | |
2704 | } | |
2705 | ||
2706 | static const struct frame_base rs6000_frame_base = { | |
2707 | &rs6000_frame_unwind, | |
2708 | rs6000_frame_base_address, | |
2709 | rs6000_frame_base_address, | |
2710 | rs6000_frame_base_address | |
2711 | }; | |
2712 | ||
2713 | static const struct frame_base * | |
2714 | rs6000_frame_base_sniffer (struct frame_info *next_frame) | |
2715 | { | |
2716 | return &rs6000_frame_base; | |
2717 | } | |
2718 | ||
7a78ae4e ND |
2719 | /* Initialize the current architecture based on INFO. If possible, re-use an |
2720 | architecture from ARCHES, which is a list of architectures already created | |
2721 | during this debugging session. | |
c906108c | 2722 | |
7a78ae4e | 2723 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 2724 | a binary file. */ |
c906108c | 2725 | |
7a78ae4e ND |
2726 | static struct gdbarch * |
2727 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2728 | { | |
2729 | struct gdbarch *gdbarch; | |
2730 | struct gdbarch_tdep *tdep; | |
9aa1e687 | 2731 | int wordsize, from_xcoff_exec, from_elf_exec, power, i, off; |
7a78ae4e ND |
2732 | struct reg *regs; |
2733 | const struct variant *v; | |
2734 | enum bfd_architecture arch; | |
2735 | unsigned long mach; | |
2736 | bfd abfd; | |
7b112f9c | 2737 | int sysv_abi; |
5bf1c677 | 2738 | asection *sect; |
7a78ae4e | 2739 | |
9aa1e687 | 2740 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
2741 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
2742 | ||
9aa1e687 KB |
2743 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
2744 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2745 | ||
2746 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2747 | ||
e712c1cf | 2748 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 2749 | that, else choose a likely default. */ |
9aa1e687 | 2750 | if (from_xcoff_exec) |
c906108c | 2751 | { |
11ed25ac | 2752 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
2753 | wordsize = 8; |
2754 | else | |
2755 | wordsize = 4; | |
c906108c | 2756 | } |
9aa1e687 KB |
2757 | else if (from_elf_exec) |
2758 | { | |
2759 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
2760 | wordsize = 8; | |
2761 | else | |
2762 | wordsize = 4; | |
2763 | } | |
c906108c | 2764 | else |
7a78ae4e | 2765 | { |
27b15785 KB |
2766 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
2767 | wordsize = info.bfd_arch_info->bits_per_word / | |
2768 | info.bfd_arch_info->bits_per_byte; | |
2769 | else | |
2770 | wordsize = 4; | |
7a78ae4e | 2771 | } |
c906108c | 2772 | |
64366f1c | 2773 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
2774 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2775 | arches != NULL; | |
2776 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2777 | { | |
2778 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
2779 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 2780 | separate word size check. */ |
7a78ae4e | 2781 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 2782 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
2783 | return arches->gdbarch; |
2784 | } | |
c906108c | 2785 | |
7a78ae4e ND |
2786 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
2787 | validity depends on the source: | |
2788 | - executable useless | |
2789 | - rs6000_host_arch() good | |
2790 | - core file good | |
2791 | - "set arch" trust blindly | |
2792 | - GDB startup useless but harmless */ | |
c906108c | 2793 | |
9aa1e687 | 2794 | if (!from_xcoff_exec) |
c906108c | 2795 | { |
b732d07d | 2796 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 2797 | mach = info.bfd_arch_info->mach; |
c906108c | 2798 | } |
7a78ae4e | 2799 | else |
c906108c | 2800 | { |
7a78ae4e | 2801 | arch = bfd_arch_powerpc; |
35cec841 | 2802 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 2803 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 2804 | mach = info.bfd_arch_info->mach; |
7a78ae4e ND |
2805 | } |
2806 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2807 | tdep->wordsize = wordsize; | |
5bf1c677 EZ |
2808 | |
2809 | /* For e500 executables, the apuinfo section is of help here. Such | |
2810 | section contains the identifier and revision number of each | |
2811 | Application-specific Processing Unit that is present on the | |
2812 | chip. The content of the section is determined by the assembler | |
2813 | which looks at each instruction and determines which unit (and | |
2814 | which version of it) can execute it. In our case we just look for | |
2815 | the existance of the section. */ | |
2816 | ||
2817 | if (info.abfd) | |
2818 | { | |
2819 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
2820 | if (sect) | |
2821 | { | |
2822 | arch = info.bfd_arch_info->arch; | |
2823 | mach = bfd_mach_ppc_e500; | |
2824 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
2825 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
2826 | } | |
2827 | } | |
2828 | ||
7a78ae4e ND |
2829 | gdbarch = gdbarch_alloc (&info, tdep); |
2830 | power = arch == bfd_arch_rs6000; | |
2831 | ||
489461e2 EZ |
2832 | /* Initialize the number of real and pseudo registers in each variant. */ |
2833 | init_variants (); | |
2834 | ||
64366f1c | 2835 | /* Choose variant. */ |
7a78ae4e ND |
2836 | v = find_variant_by_arch (arch, mach); |
2837 | if (!v) | |
dd47e6fd EZ |
2838 | return NULL; |
2839 | ||
7a78ae4e ND |
2840 | tdep->regs = v->regs; |
2841 | ||
2188cbdd | 2842 | tdep->ppc_gp0_regnum = 0; |
2188cbdd EZ |
2843 | tdep->ppc_toc_regnum = 2; |
2844 | tdep->ppc_ps_regnum = 65; | |
2845 | tdep->ppc_cr_regnum = 66; | |
2846 | tdep->ppc_lr_regnum = 67; | |
2847 | tdep->ppc_ctr_regnum = 68; | |
2848 | tdep->ppc_xer_regnum = 69; | |
2849 | if (v->mach == bfd_mach_ppc_601) | |
2850 | tdep->ppc_mq_regnum = 124; | |
e3f36dbd | 2851 | else if (power) |
2188cbdd | 2852 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
2853 | else |
2854 | tdep->ppc_mq_regnum = -1; | |
366f009f | 2855 | tdep->ppc_fp0_regnum = 32; |
e3f36dbd | 2856 | tdep->ppc_fpscr_regnum = power ? 71 : 70; |
baffbae0 JB |
2857 | tdep->ppc_vr0_regnum = -1; |
2858 | tdep->ppc_vrsave_regnum = -1; | |
2859 | tdep->ppc_ev0_regnum = -1; | |
2860 | tdep->ppc_ev31_regnum = -1; | |
867e2dc5 JB |
2861 | tdep->ppc_acc_regnum = -1; |
2862 | tdep->ppc_spefscr_regnum = -1; | |
2188cbdd | 2863 | |
c8001721 EZ |
2864 | set_gdbarch_pc_regnum (gdbarch, 64); |
2865 | set_gdbarch_sp_regnum (gdbarch, 1); | |
0ba6dca9 | 2866 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
afd48b75 | 2867 | if (sysv_abi && wordsize == 8) |
05580c65 | 2868 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
e754ae69 | 2869 | else if (sysv_abi && wordsize == 4) |
05580c65 | 2870 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
afd48b75 AC |
2871 | else |
2872 | { | |
2873 | set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); | |
2874 | set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value); | |
2875 | } | |
c8001721 | 2876 | |
baffbae0 JB |
2877 | /* Set lr_frame_offset. */ |
2878 | if (wordsize == 8) | |
2879 | tdep->lr_frame_offset = 16; | |
2880 | else if (sysv_abi) | |
2881 | tdep->lr_frame_offset = 4; | |
2882 | else | |
2883 | tdep->lr_frame_offset = 8; | |
2884 | ||
2885 | /* Calculate byte offsets in raw register array. */ | |
2886 | tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int)); | |
2887 | for (i = off = 0; i < v->num_tot_regs; i++) | |
2888 | { | |
2889 | tdep->regoff[i] = off; | |
2890 | off += regsize (v->regs + i, wordsize); | |
2891 | } | |
2892 | ||
1fcc0bb8 EZ |
2893 | if (v->arch == bfd_arch_powerpc) |
2894 | switch (v->mach) | |
2895 | { | |
2896 | case bfd_mach_ppc: | |
2897 | tdep->ppc_vr0_regnum = 71; | |
2898 | tdep->ppc_vrsave_regnum = 104; | |
2899 | break; | |
2900 | case bfd_mach_ppc_7400: | |
2901 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 2902 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
2903 | break; |
2904 | case bfd_mach_ppc_e500: | |
338ef23d | 2905 | tdep->ppc_gp0_regnum = 41; |
c8001721 EZ |
2906 | tdep->ppc_toc_regnum = -1; |
2907 | tdep->ppc_ps_regnum = 1; | |
2908 | tdep->ppc_cr_regnum = 2; | |
2909 | tdep->ppc_lr_regnum = 3; | |
2910 | tdep->ppc_ctr_regnum = 4; | |
2911 | tdep->ppc_xer_regnum = 5; | |
2912 | tdep->ppc_ev0_regnum = 7; | |
2913 | tdep->ppc_ev31_regnum = 38; | |
383f0f5b JB |
2914 | tdep->ppc_fp0_regnum = -1; |
2915 | tdep->ppc_fpscr_regnum = -1; | |
867e2dc5 JB |
2916 | tdep->ppc_acc_regnum = 39; |
2917 | tdep->ppc_spefscr_regnum = 40; | |
c8001721 | 2918 | set_gdbarch_pc_regnum (gdbarch, 0); |
338ef23d | 2919 | set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
0ba6dca9 | 2920 | set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
c8001721 EZ |
2921 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); |
2922 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
1fcc0bb8 | 2923 | break; |
1fcc0bb8 EZ |
2924 | } |
2925 | ||
338ef23d AC |
2926 | /* Sanity check on registers. */ |
2927 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); | |
2928 | ||
56a6dfb9 KB |
2929 | /* Select instruction printer. */ |
2930 | if (arch == power) | |
9364a0ef | 2931 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 2932 | else |
9364a0ef | 2933 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 2934 | |
7a78ae4e | 2935 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
7a78ae4e ND |
2936 | |
2937 | set_gdbarch_num_regs (gdbarch, v->nregs); | |
c8001721 | 2938 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e | 2939 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
b1e29e33 | 2940 | set_gdbarch_deprecated_register_size (gdbarch, wordsize); |
b8b527c5 | 2941 | set_gdbarch_deprecated_register_bytes (gdbarch, off); |
9c04cab7 AC |
2942 | set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte); |
2943 | set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size); | |
9c04cab7 | 2944 | set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type); |
7a78ae4e ND |
2945 | |
2946 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2947 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2948 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2949 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2950 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2951 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2952 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
2953 | if (sysv_abi) |
2954 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
2955 | else | |
2956 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 2957 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 2958 | |
11269d7e | 2959 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
8b148df9 AC |
2960 | if (sysv_abi && wordsize == 8) |
2961 | /* PPC64 SYSV. */ | |
2962 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
2963 | else if (!sysv_abi && wordsize == 4) | |
5bffac25 AC |
2964 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
2965 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. | |
2966 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to | |
2967 | 224. */ | |
2968 | set_gdbarch_frame_red_zone_size (gdbarch, 224); | |
7a78ae4e | 2969 | |
781a750d AC |
2970 | set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible); |
2971 | set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual); | |
2972 | set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw); | |
9f744501 JB |
2973 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum); |
2974 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum); | |
2ea5f656 KB |
2975 | /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() |
2976 | is correct for the SysV ABI when the wordsize is 8, but I'm also | |
2977 | fairly certain that ppc_sysv_abi_push_arguments() will give even | |
2978 | worse results since it only works for 32-bit code. So, for the moment, | |
2979 | we're better off calling rs6000_push_arguments() since it works for | |
2980 | 64-bit code. At some point in the future, this matter needs to be | |
2981 | revisited. */ | |
2982 | if (sysv_abi && wordsize == 4) | |
77b2b6d4 | 2983 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
8be9034a AC |
2984 | else if (sysv_abi && wordsize == 8) |
2985 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); | |
9aa1e687 | 2986 | else |
77b2b6d4 | 2987 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
7a78ae4e | 2988 | |
74055713 | 2989 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); |
7a78ae4e ND |
2990 | |
2991 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); | |
2992 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7a78ae4e ND |
2993 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
2994 | ||
6066c3de AC |
2995 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
2996 | for the descriptor and ".FN" for the entry-point -- a user | |
2997 | specifying "break FN" will unexpectedly end up with a breakpoint | |
2998 | on the descriptor and not the function. This architecture method | |
2999 | transforms any breakpoints on descriptors into breakpoints on the | |
3000 | corresponding entry point. */ | |
3001 | if (sysv_abi && wordsize == 8) | |
3002 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); | |
3003 | ||
7a78ae4e ND |
3004 | /* Not sure on this. FIXMEmgo */ |
3005 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
3006 | ||
05580c65 | 3007 | if (!sysv_abi) |
7b112f9c | 3008 | set_gdbarch_use_struct_convention (gdbarch, |
b9ff3018 | 3009 | rs6000_use_struct_convention); |
8e0662df | 3010 | |
15813d3f AC |
3011 | if (!sysv_abi) |
3012 | { | |
3013 | /* Handle RS/6000 function pointers (which are really function | |
3014 | descriptors). */ | |
f517ea4e PS |
3015 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
3016 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 3017 | } |
7a78ae4e | 3018 | |
143985b7 AF |
3019 | /* Helpers for function argument information. */ |
3020 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
3021 | ||
7b112f9c | 3022 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 3023 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 3024 | |
61a65099 KB |
3025 | switch (info.osabi) |
3026 | { | |
3027 | case GDB_OSABI_NETBSD_AOUT: | |
3028 | case GDB_OSABI_NETBSD_ELF: | |
3029 | case GDB_OSABI_UNKNOWN: | |
3030 | case GDB_OSABI_LINUX: | |
3031 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
3032 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3033 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3034 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
3035 | break; | |
3036 | default: | |
61a65099 | 3037 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
3038 | |
3039 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
3040 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3041 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3042 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
61a65099 KB |
3043 | } |
3044 | ||
ef5200c1 AC |
3045 | if (from_xcoff_exec) |
3046 | { | |
3047 | /* NOTE: jimix/2003-06-09: This test should really check for | |
3048 | GDB_OSABI_AIX when that is defined and becomes | |
3049 | available. (Actually, once things are properly split apart, | |
3050 | the test goes away.) */ | |
3051 | /* RS6000/AIX does not support PT_STEP. Has to be simulated. */ | |
3052 | set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step); | |
3053 | } | |
3054 | ||
7a78ae4e | 3055 | return gdbarch; |
c906108c SS |
3056 | } |
3057 | ||
7b112f9c JT |
3058 | static void |
3059 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3060 | { | |
3061 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3062 | ||
3063 | if (tdep == NULL) | |
3064 | return; | |
3065 | ||
4be87837 | 3066 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
3067 | } |
3068 | ||
1fcc0bb8 EZ |
3069 | static struct cmd_list_element *info_powerpc_cmdlist = NULL; |
3070 | ||
3071 | static void | |
3072 | rs6000_info_powerpc_command (char *args, int from_tty) | |
3073 | { | |
3074 | help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); | |
3075 | } | |
3076 | ||
c906108c SS |
3077 | /* Initialization code. */ |
3078 | ||
a78f21af | 3079 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
b9362cc7 | 3080 | |
c906108c | 3081 | void |
fba45db2 | 3082 | _initialize_rs6000_tdep (void) |
c906108c | 3083 | { |
7b112f9c JT |
3084 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
3085 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
1fcc0bb8 EZ |
3086 | |
3087 | /* Add root prefix command for "info powerpc" commands */ | |
3088 | add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, | |
3089 | "Various POWERPC info specific commands.", | |
3090 | &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); | |
c906108c | 3091 | } |